1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2019 HiSilicon Limited. */
3 #ifndef HISI_ACC_QM_H
4 #define HISI_ACC_QM_H
5
6 #include <linux/bitfield.h>
7 #include <linux/debugfs.h>
8 #include <linux/iopoll.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11
12 #define QM_QNUM_V1 4096
13 #define QM_QNUM_V2 1024
14 #define QM_MAX_VFS_NUM_V2 63
15
16 /* qm user domain */
17 #define QM_ARUSER_M_CFG_1 0x100088
18 #define AXUSER_SNOOP_ENABLE BIT(30)
19 #define AXUSER_CMD_TYPE GENMASK(14, 12)
20 #define AXUSER_CMD_SMMU_NORMAL 1
21 #define AXUSER_NS BIT(6)
22 #define AXUSER_NO BIT(5)
23 #define AXUSER_FP BIT(4)
24 #define AXUSER_SSV BIT(0)
25 #define AXUSER_BASE (AXUSER_SNOOP_ENABLE | \
26 FIELD_PREP(AXUSER_CMD_TYPE, \
27 AXUSER_CMD_SMMU_NORMAL) | \
28 AXUSER_NS | AXUSER_NO | AXUSER_FP)
29 #define QM_ARUSER_M_CFG_ENABLE 0x100090
30 #define ARUSER_M_CFG_ENABLE 0xfffffffe
31 #define QM_AWUSER_M_CFG_1 0x100098
32 #define QM_AWUSER_M_CFG_ENABLE 0x1000a0
33 #define AWUSER_M_CFG_ENABLE 0xfffffffe
34 #define QM_WUSER_M_CFG_ENABLE 0x1000a8
35 #define WUSER_M_CFG_ENABLE 0xffffffff
36
37 /* mailbox */
38 #define QM_MB_CMD_SQC 0x0
39 #define QM_MB_CMD_CQC 0x1
40 #define QM_MB_CMD_EQC 0x2
41 #define QM_MB_CMD_AEQC 0x3
42 #define QM_MB_CMD_SQC_BT 0x4
43 #define QM_MB_CMD_CQC_BT 0x5
44 #define QM_MB_CMD_SQC_VFT_V2 0x6
45 #define QM_MB_CMD_STOP_QP 0x8
46 #define QM_MB_CMD_FLUSH_QM 0x9
47 #define QM_MB_CMD_SRC 0xc
48 #define QM_MB_CMD_DST 0xd
49
50 #define QM_MB_CMD_SEND_BASE 0x300
51 #define QM_MB_EVENT_SHIFT 8
52 #define QM_MB_BUSY_SHIFT 13
53 #define QM_MB_OP_SHIFT 14
54 #define QM_MB_CMD_DATA_ADDR_L 0x304
55 #define QM_MB_CMD_DATA_ADDR_H 0x308
56 #define QM_MB_MAX_WAIT_CNT 6000
57
58 /* doorbell */
59 #define QM_DOORBELL_CMD_SQ 0
60 #define QM_DOORBELL_CMD_CQ 1
61 #define QM_DOORBELL_CMD_EQ 2
62 #define QM_DOORBELL_CMD_AEQ 3
63
64 #define QM_DOORBELL_SQ_CQ_BASE_V2 0x1000
65 #define QM_DOORBELL_EQ_AEQ_BASE_V2 0x2000
66 #define QM_QP_MAX_NUM_SHIFT 11
67 #define QM_DB_CMD_SHIFT_V2 12
68 #define QM_DB_RAND_SHIFT_V2 16
69 #define QM_DB_INDEX_SHIFT_V2 32
70 #define QM_DB_PRIORITY_SHIFT_V2 48
71 #define QM_VF_STATE 0x60
72
73 /* qm cache */
74 #define QM_CACHE_CTL 0x100050
75 #define SQC_CACHE_ENABLE BIT(0)
76 #define CQC_CACHE_ENABLE BIT(1)
77 #define SQC_CACHE_WB_ENABLE BIT(4)
78 #define SQC_CACHE_WB_THRD GENMASK(10, 5)
79 #define CQC_CACHE_WB_ENABLE BIT(11)
80 #define CQC_CACHE_WB_THRD GENMASK(17, 12)
81 #define QM_AXI_M_CFG 0x1000ac
82 #define AXI_M_CFG 0xffff
83 #define QM_AXI_M_CFG_ENABLE 0x1000b0
84 #define AM_CFG_SINGLE_PORT_MAX_TRANS 0x300014
85 #define AXI_M_CFG_ENABLE 0xffffffff
86 #define QM_PEH_AXUSER_CFG 0x1000cc
87 #define QM_PEH_AXUSER_CFG_ENABLE 0x1000d0
88 #define PEH_AXUSER_CFG 0x401001
89 #define PEH_AXUSER_CFG_ENABLE 0xffffffff
90
91 #define QM_MIN_QNUM 2
92 #define HISI_ACC_SGL_SGE_NR_MAX 255
93 #define QM_SHAPER_CFG 0x100164
94 #define QM_SHAPER_ENABLE BIT(30)
95 #define QM_SHAPER_TYPE1_OFFSET 10
96
97 /* page number for queue file region */
98 #define QM_DOORBELL_PAGE_NR 1
99
100 #define QM_DEV_ALG_MAX_LEN 256
101
102 /* uacce mode of the driver */
103 #define UACCE_MODE_NOUACCE 0 /* don't use uacce */
104 #define UACCE_MODE_SVA 1 /* use uacce sva mode */
105 #define UACCE_MODE_DESC "0(default) means only register to crypto, 1 means both register to crypto and uacce"
106
107 enum qm_stop_reason {
108 QM_NORMAL,
109 QM_SOFT_RESET,
110 QM_DOWN,
111 };
112
113 enum qm_state {
114 QM_WORK = 0,
115 QM_STOP,
116 };
117
118 enum qp_state {
119 QP_START = 1,
120 QP_STOP,
121 };
122
123 enum qm_hw_ver {
124 QM_HW_V1 = 0x20,
125 QM_HW_V2 = 0x21,
126 QM_HW_V3 = 0x30,
127 QM_HW_V4 = 0x50,
128 };
129
130 enum qm_fun_type {
131 QM_HW_PF,
132 QM_HW_VF,
133 };
134
135 enum qm_debug_file {
136 CURRENT_QM,
137 CURRENT_Q,
138 CLEAR_ENABLE,
139 DEBUG_FILE_NUM,
140 };
141
142 enum qm_vf_state {
143 QM_READY = 0,
144 QM_NOT_READY,
145 };
146
147 enum qm_misc_ctl_bits {
148 QM_DRIVER_REMOVING = 0x0,
149 QM_RST_SCHED,
150 QM_RESETTING,
151 QM_MODULE_PARAM,
152 };
153
154 enum qm_cap_bits {
155 QM_SUPPORT_DB_ISOLATION = 0x0,
156 QM_SUPPORT_FUNC_QOS,
157 QM_SUPPORT_STOP_QP,
158 QM_SUPPORT_STOP_FUNC,
159 QM_SUPPORT_MB_COMMAND,
160 QM_SUPPORT_SVA_PREFETCH,
161 QM_SUPPORT_RPM,
162 QM_SUPPORT_DAE,
163 };
164
165 struct qm_dev_alg {
166 u64 alg_msk;
167 const char *alg;
168 };
169
170 struct qm_dev_dfx {
171 u32 dev_state;
172 u32 dev_timeout;
173 };
174
175 struct dfx_diff_registers {
176 u32 *regs;
177 u32 reg_offset;
178 u32 reg_len;
179 };
180
181 struct qm_dfx {
182 atomic64_t err_irq_cnt;
183 atomic64_t aeq_irq_cnt;
184 atomic64_t abnormal_irq_cnt;
185 atomic64_t create_qp_err_cnt;
186 atomic64_t mb_err_cnt;
187 };
188
189 struct debugfs_file {
190 enum qm_debug_file index;
191 struct mutex lock;
192 struct qm_debug *debug;
193 };
194
195 struct qm_debug {
196 u32 curr_qm_qp_num;
197 u32 sqe_mask_offset;
198 u32 sqe_mask_len;
199 struct qm_dfx dfx;
200 struct dentry *debug_root;
201 struct dentry *qm_d;
202 struct debugfs_file files[DEBUG_FILE_NUM];
203 struct qm_dev_dfx dev_dfx;
204 unsigned int *qm_last_words;
205 /* ACC engines recoreding last regs */
206 unsigned int *last_words;
207 struct dfx_diff_registers *qm_diff_regs;
208 struct dfx_diff_registers *acc_diff_regs;
209 };
210
211 struct qm_shaper_factor {
212 u32 func_qos;
213 u64 cir_b;
214 u64 cir_u;
215 u64 cir_s;
216 u64 cbs_s;
217 };
218
219 struct qm_dma {
220 void *va;
221 dma_addr_t dma;
222 size_t size;
223 };
224
225 struct hisi_qm_status {
226 u32 eq_head;
227 bool eqc_phase;
228 u32 aeq_head;
229 bool aeqc_phase;
230 atomic_t flags;
231 int stop_reason;
232 };
233
234 struct hisi_qm;
235
236 enum acc_err_result {
237 ACC_ERR_NONE,
238 ACC_ERR_NEED_RESET,
239 ACC_ERR_RECOVERED,
240 };
241
242 struct hisi_qm_err_info {
243 char *acpi_rst;
244 u32 msi_wr_port;
245 u32 ecc_2bits_mask;
246 u32 qm_shutdown_mask;
247 u32 dev_shutdown_mask;
248 u32 qm_reset_mask;
249 u32 dev_reset_mask;
250 u32 ce;
251 u32 nfe;
252 u32 fe;
253 };
254
255 struct hisi_qm_err_status {
256 u32 is_qm_ecc_mbit;
257 u32 is_dev_ecc_mbit;
258 };
259
260 struct hisi_qm_err_ini {
261 int (*hw_init)(struct hisi_qm *qm);
262 void (*hw_err_enable)(struct hisi_qm *qm);
263 void (*hw_err_disable)(struct hisi_qm *qm);
264 u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
265 void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);
266 void (*open_axi_master_ooo)(struct hisi_qm *qm);
267 void (*close_axi_master_ooo)(struct hisi_qm *qm);
268 void (*open_sva_prefetch)(struct hisi_qm *qm);
269 void (*close_sva_prefetch)(struct hisi_qm *qm);
270 void (*show_last_dfx_regs)(struct hisi_qm *qm);
271 void (*err_info_init)(struct hisi_qm *qm);
272 enum acc_err_result (*get_err_result)(struct hisi_qm *qm);
273 bool (*dev_is_abnormal)(struct hisi_qm *qm);
274 int (*set_priv_status)(struct hisi_qm *qm);
275 };
276
277 struct hisi_qm_cap_info {
278 u32 type;
279 /* Register offset */
280 u32 offset;
281 /* Bit offset in register */
282 u32 shift;
283 u32 mask;
284 u32 v1_val;
285 u32 v2_val;
286 u32 v3_val;
287 };
288
289 struct hisi_qm_cap_query_info {
290 u32 type;
291 const char *name;
292 u32 offset;
293 u32 v1_val;
294 u32 v2_val;
295 u32 v3_val;
296 };
297
298 struct hisi_qm_cap_record {
299 u32 type;
300 const char *name;
301 u32 cap_val;
302 };
303
304 struct hisi_qm_cap_tables {
305 u32 qm_cap_size;
306 struct hisi_qm_cap_record *qm_cap_table;
307 u32 dev_cap_size;
308 struct hisi_qm_cap_record *dev_cap_table;
309 };
310
311 struct hisi_qm_list {
312 struct mutex lock;
313 struct list_head list;
314 int (*register_to_crypto)(struct hisi_qm *qm);
315 void (*unregister_from_crypto)(struct hisi_qm *qm);
316 };
317
318 struct hisi_qm_poll_data {
319 struct hisi_qm *qm;
320 struct work_struct work;
321 u16 *qp_finish_id;
322 u16 eqe_num;
323 };
324
325 /**
326 * struct qm_err_isolate
327 * @isolate_lock: protects device error log
328 * @err_threshold: user config error threshold which triggers isolation
329 * @is_isolate: device isolation state
330 * @uacce_hw_errs: index into qm device error list
331 */
332 struct qm_err_isolate {
333 struct mutex isolate_lock;
334 u32 err_threshold;
335 bool is_isolate;
336 struct list_head qm_hw_errs;
337 };
338
339 struct qm_rsv_buf {
340 struct qm_sqc *sqc;
341 struct qm_cqc *cqc;
342 struct qm_eqc *eqc;
343 struct qm_aeqc *aeqc;
344 dma_addr_t sqc_dma;
345 dma_addr_t cqc_dma;
346 dma_addr_t eqc_dma;
347 dma_addr_t aeqc_dma;
348 struct qm_dma qcdma;
349 };
350
351 struct hisi_qm {
352 enum qm_hw_ver ver;
353 enum qm_fun_type fun_type;
354 const char *dev_name;
355 struct pci_dev *pdev;
356 void __iomem *io_base;
357 void __iomem *db_io_base;
358
359 /* Capbility version, 0: not supports */
360 u32 cap_ver;
361 u32 sqe_size;
362 u32 qp_base;
363 u32 qp_num;
364 u32 qp_in_used;
365 u32 ctrl_qp_num;
366 u32 max_qp_num;
367 u32 vfs_num;
368 u32 db_interval;
369 u16 eq_depth;
370 u16 aeq_depth;
371 struct list_head list;
372 struct hisi_qm_list *qm_list;
373
374 struct qm_dma qdma;
375 struct qm_sqc *sqc;
376 struct qm_cqc *cqc;
377 struct qm_eqe *eqe;
378 struct qm_aeqe *aeqe;
379 dma_addr_t sqc_dma;
380 dma_addr_t cqc_dma;
381 dma_addr_t eqe_dma;
382 dma_addr_t aeqe_dma;
383 struct qm_rsv_buf xqc_buf;
384
385 struct hisi_qm_status status;
386 const struct hisi_qm_err_ini *err_ini;
387 struct hisi_qm_err_info err_info;
388 struct hisi_qm_err_status err_status;
389 /* driver removing and reset sched */
390 unsigned long misc_ctl;
391 /* Device capability bit */
392 unsigned long caps;
393
394 struct rw_semaphore qps_lock;
395 struct idr qp_idr;
396 struct hisi_qp *qp_array;
397 struct hisi_qm_poll_data *poll_data;
398
399 struct mutex mailbox_lock;
400
401 struct mutex ifc_lock;
402
403 const struct hisi_qm_hw_ops *ops;
404
405 struct qm_debug debug;
406
407 u32 error_mask;
408
409 struct workqueue_struct *wq;
410 struct work_struct rst_work;
411 struct work_struct cmd_process;
412
413 bool use_sva;
414
415 resource_size_t phys_base;
416 resource_size_t db_phys_base;
417 struct uacce_device *uacce;
418 int mode;
419 struct qm_shaper_factor *factor;
420 u32 mb_qos;
421 u32 type_rate;
422 struct qm_err_isolate isolate_data;
423
424 struct hisi_qm_cap_tables cap_tables;
425 };
426
427 struct hisi_qp_status {
428 atomic_t used;
429 u16 sq_tail;
430 u16 cq_head;
431 bool cqc_phase;
432 atomic_t flags;
433 };
434
435 struct hisi_qp_ops {
436 int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
437 };
438
439 struct hisi_qp {
440 u32 qp_id;
441 u16 sq_depth;
442 u16 cq_depth;
443 u8 alg_type;
444 u8 req_type;
445
446 struct qm_dma qdma;
447 void *sqe;
448 struct qm_cqe *cqe;
449 dma_addr_t sqe_dma;
450 dma_addr_t cqe_dma;
451
452 struct hisi_qp_status qp_status;
453 struct hisi_qp_ops *hw_ops;
454 void *qp_ctx;
455 void (*req_cb)(struct hisi_qp *qp, void *data);
456 void (*event_cb)(struct hisi_qp *qp);
457
458 struct hisi_qm *qm;
459 bool is_resetting;
460 bool is_in_kernel;
461 u16 pasid;
462 struct uacce_queue *uacce_q;
463 };
464
vfs_num_set(const char * val,const struct kernel_param * kp)465 static inline int vfs_num_set(const char *val, const struct kernel_param *kp)
466 {
467 u32 n;
468 int ret;
469
470 if (!val)
471 return -EINVAL;
472
473 ret = kstrtou32(val, 10, &n);
474 if (ret < 0)
475 return ret;
476
477 if (n > QM_MAX_VFS_NUM_V2)
478 return -EINVAL;
479
480 return param_set_int(val, kp);
481 }
482
mode_set(const char * val,const struct kernel_param * kp)483 static inline int mode_set(const char *val, const struct kernel_param *kp)
484 {
485 u32 n;
486 int ret;
487
488 if (!val)
489 return -EINVAL;
490
491 ret = kstrtou32(val, 10, &n);
492 if (ret != 0 || (n != UACCE_MODE_SVA &&
493 n != UACCE_MODE_NOUACCE))
494 return -EINVAL;
495
496 return param_set_int(val, kp);
497 }
498
uacce_mode_set(const char * val,const struct kernel_param * kp)499 static inline int uacce_mode_set(const char *val, const struct kernel_param *kp)
500 {
501 return mode_set(val, kp);
502 }
503
hisi_qm_init_list(struct hisi_qm_list * qm_list)504 static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
505 {
506 INIT_LIST_HEAD(&qm_list->list);
507 mutex_init(&qm_list->lock);
508 }
509
hisi_qm_add_list(struct hisi_qm * qm,struct hisi_qm_list * qm_list)510 static inline void hisi_qm_add_list(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
511 {
512 mutex_lock(&qm_list->lock);
513 list_add_tail(&qm->list, &qm_list->list);
514 mutex_unlock(&qm_list->lock);
515 }
516
hisi_qm_del_list(struct hisi_qm * qm,struct hisi_qm_list * qm_list)517 static inline void hisi_qm_del_list(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
518 {
519 mutex_lock(&qm_list->lock);
520 list_del(&qm->list);
521 mutex_unlock(&qm_list->lock);
522 }
523
524 int hisi_qm_q_num_set(const char *val, const struct kernel_param *kp,
525 unsigned int device);
526 int hisi_qm_init(struct hisi_qm *qm);
527 void hisi_qm_uninit(struct hisi_qm *qm);
528 int hisi_qm_start(struct hisi_qm *qm);
529 int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
530 int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
531 void hisi_qm_stop_qp(struct hisi_qp *qp);
532 int hisi_qp_send(struct hisi_qp *qp, const void *msg);
533 void hisi_qm_debug_init(struct hisi_qm *qm);
534 void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
535 int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
536 int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
537 int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
538 void hisi_qm_dev_err_init(struct hisi_qm *qm);
539 void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
540 int hisi_qm_regs_debugfs_init(struct hisi_qm *qm,
541 struct dfx_diff_registers *dregs, u32 reg_len);
542 void hisi_qm_regs_debugfs_uninit(struct hisi_qm *qm, u32 reg_len);
543 void hisi_qm_acc_diff_regs_dump(struct hisi_qm *qm, struct seq_file *s,
544 struct dfx_diff_registers *dregs, u32 regs_len);
545
546 pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
547 pci_channel_state_t state);
548 pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
549 void hisi_qm_reset_prepare(struct pci_dev *pdev);
550 void hisi_qm_reset_done(struct pci_dev *pdev);
551
552 int hisi_qm_wait_mb_ready(struct hisi_qm *qm);
553 int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
554 bool op);
555
556 struct hisi_acc_sgl_pool;
557 struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
558 struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
559 u32 index, dma_addr_t *hw_sgl_dma);
560 void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
561 struct hisi_acc_hw_sgl *hw_sgl);
562 struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
563 u32 count, u32 sge_nr);
564 void hisi_acc_free_sgl_pool(struct device *dev,
565 struct hisi_acc_sgl_pool *pool);
566 int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
567 u8 alg_type, int node, struct hisi_qp **qps);
568 void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
569 void hisi_qm_dev_shutdown(struct pci_dev *pdev);
570 void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
571 int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard);
572 void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard);
573 int hisi_qm_resume(struct device *dev);
574 int hisi_qm_suspend(struct device *dev);
575 void hisi_qm_pm_uninit(struct hisi_qm *qm);
576 void hisi_qm_pm_init(struct hisi_qm *qm);
577 int hisi_qm_get_dfx_access(struct hisi_qm *qm);
578 void hisi_qm_put_dfx_access(struct hisi_qm *qm);
579 void hisi_qm_regs_dump(struct seq_file *s, struct debugfs_regset32 *regset);
580 u32 hisi_qm_get_hw_info(struct hisi_qm *qm,
581 const struct hisi_qm_cap_info *info_table,
582 u32 index, bool is_read);
583 u32 hisi_qm_get_cap_value(struct hisi_qm *qm,
584 const struct hisi_qm_cap_query_info *info_table,
585 u32 index, bool is_read);
586 int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs,
587 u32 dev_algs_size);
588
589 /* Used by VFIO ACC live migration driver */
590 struct pci_driver *hisi_sec_get_pf_driver(void);
591 struct pci_driver *hisi_hpre_get_pf_driver(void);
592 struct pci_driver *hisi_zip_get_pf_driver(void);
593 #endif
594