1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #include <stdint.h> 4 #include "raminit.h" 5 6 const struct dll_setting default_ddr2_667_ctrl[7] = { 7 /* tap pi db delay coarse */ 8 {13, 0, 1, 0, 0, 0}, /* clkset0 */ 9 {4, 1, 0, 0, 0, 0}, /* ctrl0 */ 10 {13, 0, 1, 0, 0, 0}, /* clkset1 */ 11 {4, 5, 0, 0, 0, 0}, /* cmd */ 12 {4, 1, 0, 0, 0, 0}, /* ctrl1 */ 13 {4, 1, 0, 0, 0, 0}, /* ctrl2 */ 14 {4, 1, 0, 0, 0, 0}, /* ctrl3 */ 15 }; 16 17 const struct dll_setting default_ddr2_667_dqs[TOTAL_BYTELANES] = { 18 {1, 5, 1, 1, 1, 0}, 19 {1, 6, 1, 1, 1, 0}, 20 {2, 0, 1, 1, 1, 0}, 21 {2, 1, 1, 1, 1, 0}, 22 {2, 1, 1, 1, 1, 0}, 23 {14, 6, 1, 0, 0, 0}, 24 {14, 3, 1, 0, 0, 0}, 25 {14, 0, 1, 0, 0, 0}, 26 }; 27 28 const struct dll_setting default_ddr2_667_dq[TOTAL_BYTELANES] = { 29 {9, 0, 0, 0, 1, 0}, 30 {9, 1, 0, 0, 1, 0}, 31 {9, 2, 0, 0, 1, 0}, 32 {9, 2, 0, 0, 1, 0}, 33 {9, 1, 0, 0, 1, 0}, 34 {6, 4, 0, 0, 1, 0}, 35 {6, 2, 0, 0, 1, 0}, 36 {5, 4, 0, 0, 1, 0}, 37 }; 38 39 const struct dll_setting default_ddr2_800_ctrl[7] = { 40 /* tap pi db delay coarse */ 41 {11, 5, 1, 0, 0, 0}, 42 {0, 5, 1, 1, 0, 0}, 43 {11, 5, 1, 0, 0, 0}, 44 {1, 4, 1, 1, 0, 0}, 45 {0, 5, 1, 1, 0, 0}, 46 {0, 5, 1, 1, 0, 0}, 47 {0, 5, 1, 1, 0, 0}, 48 }; 49 50 const struct dll_setting default_ddr2_800_dqs[TOTAL_BYTELANES] = { 51 {2, 5, 1, 1, 1, 0}, 52 {2, 6, 1, 1, 1, 0}, 53 {3, 0, 1, 1, 1, 0}, 54 {3, 0, 1, 1, 1, 0}, 55 {3, 3, 1, 1, 1, 0}, 56 {2, 0, 1, 1, 1, 0}, 57 {1, 3, 1, 1, 1, 0}, 58 {0, 3, 1, 1, 1, 0}, 59 }; 60 61 const struct dll_setting default_ddr2_800_dq[TOTAL_BYTELANES] = { 62 {9, 3, 0, 0, 1, 0}, 63 {9, 4, 0, 0, 1, 0}, 64 {9, 5, 0, 0, 1, 0}, 65 {9, 6, 0, 0, 1, 0}, 66 {10, 0, 0, 0, 1, 0}, 67 {8, 1, 0, 0, 1, 0}, 68 {7, 5, 0, 0, 1, 0}, 69 {6, 2, 0, 0, 1, 0}, 70 }; 71 72 const struct dll_setting default_ddr3_800_ctrl[2][7] = { 73 { /* 1N */ 74 /* tap pi db(2) delay coarse */ 75 {8, 2, 0, 0, 0, 0}, 76 {8, 4, 0, 0, 0, 0}, 77 {9, 5, 0, 0, 0, 0}, 78 {6, 1, 0, 0, 0, 0}, 79 {8, 4, 0, 0, 0, 0}, 80 {10, 0, 0, 0, 0, 0}, 81 {10, 0, 0, 0, 0, 0}, 82 }, 83 { /* 2N */ 84 {2, 2, 1, 1, 0, 0}, 85 {2, 4, 1, 1, 0, 0}, 86 {3, 5, 0, 0, 0, 0}, 87 {3, 2, 1, 1, 0, 0}, 88 {2, 4, 1, 1, 0, 0}, 89 {3, 6, 0, 0, 0, 0}, 90 {3, 6, 0, 0, 0, 0}, 91 }, 92 }; 93 94 const struct dll_setting default_ddr3_800_dqs[2][TOTAL_BYTELANES] = { 95 { /* 1N */ 96 {12, 0, 1, 0, 0, 0}, 97 {1, 1, 1, 1, 1, 0}, 98 {2, 4, 1, 1, 1, 0}, 99 {3, 5, 0, 0, 1, 0}, 100 {4, 3, 0, 0, 1, 0}, 101 {5, 2, 0, 0, 1, 0}, 102 {6, 1, 0, 0, 1, 0}, 103 {6, 4, 0, 0, 1, 0}, 104 }, 105 { /* 2N */ 106 {5, 6, 0, 0, 0, 0}, 107 {8, 0, 0, 0, 0, 0}, 108 {9, 4, 0, 0, 0, 0}, 109 {10, 4, 1, 0, 0, 0}, 110 {11, 3, 1, 0, 0, 0}, 111 {12, 1, 1, 0, 0, 0}, 112 {0, 1, 1, 1, 1, 0}, 113 {0, 3, 1, 1, 1, 0}, 114 }, 115 }; 116 117 const struct dll_setting default_ddr3_800_dq[2][TOTAL_BYTELANES] = { 118 { /* 1N */ 119 {4, 1, 0, 0, 1, 0}, 120 {6, 4, 0, 0, 1, 0}, 121 {8, 1, 0, 0, 1, 0}, 122 {8, 6, 0, 0, 1, 0}, 123 {9, 5, 0, 0, 1, 0}, 124 {10, 2, 0, 0, 1, 0}, 125 {10, 6, 1, 0, 1, 0}, 126 {11, 4, 1, 0, 1, 0}, 127 }, 128 { /* 2N */ 129 {11, 0, 1, 0, 0, 0}, 130 {0, 3, 1, 1, 1, 0}, 131 {2, 1, 1, 1, 1, 0}, 132 {2, 5, 1, 1, 1, 0}, 133 {3, 5, 0, 0, 1, 0}, 134 {4, 2, 0, 0, 1, 0}, 135 {4, 6, 0, 0, 1, 0}, 136 {5, 4, 0, 0, 1, 0}, 137 }, 138 }; 139 140 const struct dll_setting default_ddr3_1067_ctrl[2][7] = { 141 { /* 1N */ 142 {8, 5, 0, 0, 0, 0}, 143 {7, 6, 0, 0, 0, 0}, 144 {10, 2, 1, 0, 0, 0}, 145 {4, 4, 0, 0, 0, 0}, 146 {7, 6, 0, 0, 0, 0}, 147 {9, 2, 1, 0, 0, 0}, 148 {9, 2, 1, 0, 0, 0}, 149 }, 150 { /* 2N */ 151 {1, 5, 1, 1, 0, 0}, 152 {0, 6, 1, 1, 0, 0}, 153 {3, 2, 0, 0, 0, 0}, 154 {2, 6, 1, 1, 0, 0}, 155 {0, 6, 1, 1, 0, 0}, 156 {2, 2, 1, 1, 0, 0}, 157 {2, 2, 1, 1, 0, 0}, 158 }, 159 }; 160 161 const struct dll_setting default_ddr3_1067_dqs[2][TOTAL_BYTELANES] = { 162 { /* 1N */ 163 {2, 5, 1, 1, 1, 0}, 164 {5, 1, 0, 0, 1, 0}, 165 {6, 6, 0, 0, 1, 0}, 166 {8, 0, 0, 0, 1, 0}, 167 {8, 6, 0, 0, 1, 0}, 168 {9, 6, 1, 0, 1, 0}, 169 {10, 6, 1, 0, 1, 0}, 170 {0, 1, 1, 1, 0, 1}, 171 }, 172 { /* 2N */ 173 {6, 4, 0, 0, 0, 0}, 174 {9, 1, 1, 0, 0, 0}, 175 {10, 6, 1, 0, 0, 0}, 176 {1, 0, 1, 1, 1, 0}, 177 {1, 6, 1, 1, 1, 0}, 178 {2, 5, 1, 1, 1, 0}, 179 {3, 5, 0, 0, 1, 0}, 180 {4, 1, 0, 0, 1, 0}, 181 }, 182 }; 183 184 const struct dll_setting default_ddr3_1067_dq[2][TOTAL_BYTELANES] = { 185 { /* 1N */ 186 {6, 5, 0, 0, 1, 0}, 187 {9, 3, 1, 0, 1, 0}, 188 {0, 2, 1, 1, 0, 1}, 189 {1, 0, 1, 1, 0, 1}, 190 {2, 0, 1, 1, 0, 1}, 191 {2, 5, 1, 1, 0, 1}, 192 {3, 2, 0, 0, 0, 1}, 193 {4, 1, 0, 0, 0, 1}, 194 }, 195 { /* 2N */ 196 {10, 5, 1, 0, 0, 0}, 197 {2, 3, 1, 1, 1, 0}, 198 {4, 1, 0, 0, 1, 0}, 199 {5, 0, 0, 0, 1, 0}, 200 {6, 0, 0, 0, 1, 0}, 201 {6, 5, 0, 0, 1, 0}, 202 {7, 2, 0, 0, 1, 0}, 203 {8, 1, 0, 0, 1, 0}, 204 }, 205 }; 206 207 const struct dll_setting default_ddr3_1333_ctrl[2][7] = { 208 { /* 1N */ 209 {8, 5, 0, 0, 0, 0}, 210 {9, 0, 1, 0, 0, 0}, 211 {10, 2, 1, 0, 0, 0}, 212 {0, 0, 1, 1, 0, 0}, 213 {9, 0, 1, 0, 0, 0}, 214 {10, 4, 1, 0, 0, 0}, 215 {10, 4, 1, 0, 0, 0}, 216 }, 217 { /* 2N */ 218 {1, 6, 1, 1, 0, 0}, 219 {2, 2, 1, 1, 0, 0}, 220 {4, 2, 0, 0, 0, 0}, 221 {3, 1, 1, 1, 0, 0}, 222 {2, 2, 1, 1, 0, 0}, 223 {4, 5, 0, 0, 0, 0}, 224 {4, 5, 0, 0, 0, 0}, 225 }, 226 }; 227 228 const struct dll_setting default_ddr3_1333_dqs[2][TOTAL_BYTELANES] = { 229 { /* 1N */ 230 {2, 4, 1, 1, 1, 0}, 231 {5, 1, 0, 0, 1, 0}, 232 {6, 6, 0, 0, 1, 0}, 233 {8, 0, 0, 0, 1, 0}, 234 {8, 6, 0, 0, 1, 0}, 235 {9, 5, 1, 0, 1, 0}, 236 {10, 6, 1, 0, 1, 0}, 237 {0, 1, 1, 1, 0, 1}, 238 }, 239 { /* 2N */ 240 {10, 4, 0, 0, 0, 0}, 241 {0, 3, 1, 1, 1, 0}, 242 {3, 2, 1, 1, 1, 0}, 243 {5, 0, 0, 0, 1, 0}, 244 {6, 1, 0, 0, 1, 0}, 245 {7, 4, 0, 0, 1, 0}, 246 {9, 2, 0, 0, 1, 0}, 247 {9, 6, 0, 0, 1, 0}, 248 }, 249 }; 250 251 const struct dll_setting default_ddr3_1333_dq[2][TOTAL_BYTELANES] = { 252 { /* 1N */ 253 {6, 5, 0, 0, 1, 0}, 254 {9, 3, 1, 0, 1, 0}, 255 {0, 2, 1, 1, 0, 1}, 256 {1, 0, 1, 1, 0, 1}, 257 {2, 0, 1, 1, 0, 1}, 258 {2, 5, 1, 1, 0, 1}, 259 {3, 2, 0, 0, 0, 1}, 260 {4, 1, 0, 0, 0, 1}, 261 }, 262 { /* 2N */ 263 {1, 3, 1, 1, 1, 0}, 264 {5, 6, 0, 0, 1, 0}, 265 {8, 5, 0, 0, 1, 0}, 266 {10, 2, 0, 0, 1, 0}, 267 {11, 1, 0, 0, 1, 0}, 268 {12, 3, 1, 0, 1, 0}, 269 {13, 6, 1, 0, 1, 0}, 270 {0, 3, 1, 1, 0, 1}, 271 }, 272 }; 273 274 const u8 ddr3_emrs1_rtt_nom_config[16][4] = { /* [Config][Rank] */ 275 {0x00, 0x00, 0x00, 0x00}, /* NC_NC */ 276 {0x11, 0x00, 0x00, 0x00}, /* 8S_NC */ 277 {0x11, 0x11, 0x00, 0x00}, /* 8D_NC */ 278 {0x11, 0x00, 0x00, 0x00}, /* 16S_NC */ 279 {0x00, 0x00, 0x11, 0x00}, /* NC_8S */ 280 {0x81, 0x00, 0x81, 0x00}, /* 8S_8S */ 281 {0x81, 0x81, 0x81, 0x00}, /* 8D_8S */ 282 {0x81, 0x00, 0x81, 0x00}, /* 16S_8S */ 283 {0x00, 0x00, 0x11, 0x11}, /* NC_8D */ 284 {0x81, 0x00, 0x81, 0x81}, /* 8S_8D */ 285 {0x81, 0x81, 0x81, 0x81}, /* 8D_8D */ 286 {0x81, 0x00, 0x81, 0x81}, /* 16S_8D */ 287 {0x00, 0x00, 0x11, 0x00}, /* NC_16S */ 288 {0x81, 0x00, 0x81, 0x00}, /* 8S_16S */ 289 {0x81, 0x81, 0x81, 0x00}, /* 8D_16S */ 290 {0x81, 0x00, 0x81, 0x00}, /* 16S_16S */ 291 }; 292 293 const u8 post_jedec_tab[3][4][2] = { /* [FSB][DDR freq][17:13 or 12:8] */ 294 { /* FSB DDR */ 295 {0x3, 0x5}, /* 800 667 */ 296 {0x3, 0x4}, /* 800 800 */ 297 }, 298 { 299 {0x4, 0x8}, /* 1067 667 */ 300 {0x4, 0x6}, /* 1067 800 */ 301 {0x3, 0x5}, /* 1067 1066 */ 302 }, 303 { 304 {0x5, 0x9}, /* 1333 667 */ 305 {0x4, 0x7}, /* 1333 800 */ 306 {0x4, 0x7}, /* 1333 1066 */ 307 {0x4, 0x7}, /* 1333 1333 */ 308 }, 309 }; 310 311 const u32 ddr3_c2_tab[2][3][6][2] = { /* [n-mode][ddr3 freq][CAS][reg] */ 312 /* 115h[15:0] 117h[23:0] */ 313 { /* 1N mode */ 314 { /* DDR3 800 */ 315 {0x0189, 0x000aaa}, /* CAS = 5 */ 316 {0x0189, 0x101aaa}, /* CAS = 6 */ 317 }, 318 { /* DDR3 1067 */ 319 {0x0000, 0x000000}, /* CAS = 5 - Not supported */ 320 {0x0089, 0x000bbb}, /* CAS = 6 */ 321 {0x0099, 0x101bbb}, /* CAS = 7 */ 322 {0x0099, 0x202bbb}, /* CAS = 8 */ 323 }, 324 { /* DDR3 1333 */ 325 {0x0000, 0x000000}, /* CAS = 5 - Not supported */ 326 {0x0000, 0x000000}, /* CAS = 6 - Not supported */ 327 {0x0000, 0x000000}, /* CAS = 7 - Not supported */ 328 {0x129a, 0x0078dc}, /* CAS = 8 */ 329 {0x028a, 0x0078dc}, /* CAS = 9 */ 330 {0x028a, 0x1088dc}, /* CAS = 10 */ 331 }, 332 }, 333 { /* 2N mode */ 334 { /* DDR3 800 */ 335 {0x0189, 0x000aaa}, /* CAS = 5 */ 336 {0x0189, 0x101aaa}, /* CAS = 6 */ 337 }, 338 { /* DDR3 1067 */ 339 {0x0000, 0x000000}, /* CAS = 5 - Not supported */ 340 {0x0089, 0x000bbb}, /* CAS = 6 */ 341 {0x0099, 0x101bbb}, /* CAS = 7 */ 342 {0x0099, 0x202bbb}, /* CAS = 8 */ 343 }, 344 { /* DDR3 1333 */ 345 {0x0000, 0x000000}, /* CAS = 5 - Not supported */ 346 {0x0000, 0x000000}, /* CAS = 6 - Not supported */ 347 {0x0000, 0x000000}, /* CAS = 7 - Not supported */ 348 {0x019a, 0x0078dc}, /* CAS = 8 */ 349 {0x019a, 0x1088dc}, /* CAS = 9 */ 350 {0x019a, 0x2098dc}, /* CAS = 10 */ 351 }, 352 }, 353 }; 354 355 const u8 ddr3_c2_x264[3][6] = { /* [freq][cas] */ 356 { /* DDR3 800 */ 357 0x78, /* CAS = 5 */ 358 0x89, /* CAS = 6 */ 359 }, 360 { /* DDR3 1066 */ 361 0x00, /* CAS = 5 - Not supported */ 362 0xff, /* CAS = 6 */ 363 0x8a, /* CAS = 7 */ 364 0x9a, /* CAS = 8 */ 365 }, 366 { /* DDR3 1333 */ 367 0x00, /* CAS = 5 - Not supported */ 368 0x00, /* CAS = 6 - Not supported */ 369 0xff, /* CAS = 7 - Not supported */ 370 0xff, /* CAS = 8 */ 371 0xff, /* CAS = 9 */ 372 0xff, /* CAS = 10 */ 373 }, 374 }; 375 376 const u16 ddr3_c2_x23c[3][6]={ /* [freq][cas] */ 377 { /* DDR3 800 */ 378 0x9bbb, /* CAS = 5 */ 379 0x8bbb, /* CAS = 6 */ 380 }, 381 { /* DDR3 1066 */ 382 0x0000, /* CAS = 5 - Not supported */ 383 0x9baa, /* CAS = 6 */ 384 0x8caa, /* CAS = 7 */ 385 0x7daa, /* CAS = 8 */ 386 }, 387 { /* DDR3 1333 */ 388 0x0000, /* CAS = 5 - Not supported */ 389 0x0000, /* CAS = 6 - Not supported */ 390 0x0000, /* CAS = 7 - Not supported */ 391 0xaecb, /* CAS = 8 */ 392 0x9fcb, /* CAS = 9 */ 393 0x8fcb, /* CAS = 10 */ 394 }, 395 }; 396