1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #include <device/mmio.h> 4 5 #define PORT_TUNE1_MASK 0xf0 6 7 /* QUSB2PHY_PWR_CTRL1 register related bits */ 8 #define POWER_DOWN BIT(0) 9 10 /* DEBUG_CTRL2 register value to program VSTATUS MUX for PHY status */ 11 #define DEBUG_CTRL2_MUX_PLL_LOCK_STATUS 0x4 12 13 /* STAT5 register bits */ 14 #define VSTATUS_PLL_LOCK_STATUS_MASK BIT(0) 15 16 /* QUSB PHY register values */ 17 #define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x03 18 #define QUSB2PHY_PLL_CLOCK_INVERTERS 0x7c 19 #define QUSB2PHY_PLL_CMODE 0x80 20 #define QUSB2PHY_PLL_LOCK_DELAY 0x0a 21 #define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0x19 22 #define QUSB2PHY_PLL_BIAS_CONTROL_1 0x40 23 #define QUSB2PHY_PLL_BIAS_CONTROL_2 0x22 24 #define QUSB2PHY_PWR_CTRL2 0x21 25 #define QUSB2PHY_IMP_CTRL1 0x08 26 #define QUSB2PHY_IMP_CTRL2 0x58 27 #define QUSB2PHY_PORT_TUNE1 0xc5 28 #define QUSB2PHY_PORT_TUNE2 0x29 29 #define QUSB2PHY_PORT_TUNE3 0xca 30 #define QUSB2PHY_PORT_TUNE4 0x04 31 #define QUSB2PHY_PORT_TUNE5 0x03 32 #define QUSB2PHY_CHG_CTRL2 0x30 33 34 35 #define QFPROM_BASE 0x00780000 36 #define QUSB_PRIM_PHY_BASE 0x088e3000 37 #define QUSB_PRIM_PHY_DIG_BASE 0x088e3200 38 39 #define HS_USB_PRIM_PHY_BASE QUSB_PRIM_PHY_BASE 40 41 struct usb_board_data { 42 /* Register values going to override from the boardfile */ 43 u32 pll_bias_control_2; 44 u32 imp_ctrl1; 45 u32 port_tune1; 46 }; 47 48 struct usb_qusb_phy_dig { 49 u8 rsvd1[16]; 50 u32 pwr_ctrl1; 51 u32 pwr_ctrl2; 52 u8 rsvd2[8]; 53 u32 imp_ctrl1; 54 u32 imp_ctrl2; 55 u8 rsvd3[20]; 56 u32 chg_ctrl2; 57 u32 tune1; 58 u32 tune2; 59 u32 tune3; 60 u32 tune4; 61 u32 tune5; 62 u8 rsvd4[44]; 63 u32 debug_ctrl2; 64 u8 rsvd5[28]; 65 u32 debug_stat5; 66 }; 67 check_member(usb_qusb_phy_dig, tune5, 0x50); 68 check_member(usb_qusb_phy_dig, debug_ctrl2, 0x80); 69 check_member(usb_qusb_phy_dig, debug_stat5, 0xA0); 70 71 struct usb_qusb_phy_pll { 72 u8 rsvd0[4]; 73 u32 analog_controls_two; 74 u8 rsvd1[36]; 75 u32 cmode; 76 u8 rsvd2[132]; 77 u32 dig_tim; 78 u8 rsvd3[204]; 79 u32 lock_delay; 80 u8 rsvd4[4]; 81 u32 clock_inverters; 82 u8 rsvd5[4]; 83 u32 bias_ctrl_1; 84 u32 bias_ctrl_2; 85 }; 86 check_member(usb_qusb_phy_pll, cmode, 0x2C); 87 check_member(usb_qusb_phy_pll, bias_ctrl_2, 0x198); 88 check_member(usb_qusb_phy_pll, dig_tim, 0xB4); 89 90 struct hs_usb_phy_reg { 91 struct usb_qusb_phy_pll *phy_pll; 92 struct usb_qusb_phy_dig *phy_dig; 93 struct usb_board_data *board_data; 94 u32 efuse_offset; 95 }; 96