1 /*
2 * Copyright 2024 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "core_types.h"
27 #include "dcn35_clk_mgr.h"
28
29 #define DCN_BASE__INST0_SEG1 0x000000C0
30 #define mmCLK1_CLK_PLL_REQ 0x16E37
31
32 #define mmCLK1_CLK0_DFS_CNTL 0x16E69
33 #define mmCLK1_CLK1_DFS_CNTL 0x16E6C
34 #define mmCLK1_CLK2_DFS_CNTL 0x16E6F
35 #define mmCLK1_CLK3_DFS_CNTL 0x16E72
36 #define mmCLK1_CLK4_DFS_CNTL 0x16E75
37 #define mmCLK1_CLK5_DFS_CNTL 0x16E78
38
39 #define mmCLK1_CLK0_CURRENT_CNT 0x16EFC
40 #define mmCLK1_CLK1_CURRENT_CNT 0x16EFD
41 #define mmCLK1_CLK2_CURRENT_CNT 0x16EFE
42 #define mmCLK1_CLK3_CURRENT_CNT 0x16EFF
43 #define mmCLK1_CLK4_CURRENT_CNT 0x16F00
44 #define mmCLK1_CLK5_CURRENT_CNT 0x16F01
45
46 #define mmCLK1_CLK0_BYPASS_CNTL 0x16E8A
47 #define mmCLK1_CLK1_BYPASS_CNTL 0x16E93
48 #define mmCLK1_CLK2_BYPASS_CNTL 0x16E9C
49 #define mmCLK1_CLK3_BYPASS_CNTL 0x16EA5
50 #define mmCLK1_CLK4_BYPASS_CNTL 0x16EAE
51 #define mmCLK1_CLK5_BYPASS_CNTL 0x16EB7
52
53 #define mmCLK1_CLK0_DS_CNTL 0x16E83
54 #define mmCLK1_CLK1_DS_CNTL 0x16E8C
55 #define mmCLK1_CLK2_DS_CNTL 0x16E95
56 #define mmCLK1_CLK3_DS_CNTL 0x16E9E
57 #define mmCLK1_CLK4_DS_CNTL 0x16EA7
58 #define mmCLK1_CLK5_DS_CNTL 0x16EB0
59
60 #define mmCLK1_CLK0_ALLOW_DS 0x16E84
61 #define mmCLK1_CLK1_ALLOW_DS 0x16E8D
62 #define mmCLK1_CLK2_ALLOW_DS 0x16E96
63 #define mmCLK1_CLK3_ALLOW_DS 0x16E9F
64 #define mmCLK1_CLK4_ALLOW_DS 0x16EA8
65 #define mmCLK1_CLK5_ALLOW_DS 0x16EB1
66
67 #define mmCLK5_spll_field_8 0x1B04B
68 #define mmDENTIST_DISPCLK_CNTL 0x0124
69 #define regDENTIST_DISPCLK_CNTL 0x0064
70 #define regDENTIST_DISPCLK_CNTL_BASE_IDX 1
71
72 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
73 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
74 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
75 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
76 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
77 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
78
79 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L
80
81 // DENTIST_DISPCLK_CNTL
82 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0
83 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8
84 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13
85 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14
86 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18
87 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL
88 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L
89 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L
90 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK 0x00100000L
91 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK 0x7F000000L
92
93 #define CLK5_spll_field_8__spll_ssc_en_MASK 0x00002000L
94
95 #define REG(reg) \
96 (clk_mgr->regs->reg)
97
98 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
99
100 #define BASE(seg) BASE_INNER(seg)
101
102 #define SR(reg_name)\
103 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
104 reg ## reg_name
105
106 #define CLK_SR_DCN35(reg_name)\
107 .reg_name = mm ## reg_name
108
109 static const struct clk_mgr_registers clk_mgr_regs_dcn351 = {
110 CLK_REG_LIST_DCN35()
111 };
112
113 static const struct clk_mgr_shift clk_mgr_shift_dcn351 = {
114 CLK_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
115 };
116
117 static const struct clk_mgr_mask clk_mgr_mask_dcn351 = {
118 CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)
119 };
120
121 #define TO_CLK_MGR_DCN35(clk_mgr)\
122 container_of(clk_mgr, struct clk_mgr_dcn35, base)
123
124
dcn351_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn35 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)125 void dcn351_clk_mgr_construct(
126 struct dc_context *ctx,
127 struct clk_mgr_dcn35 *clk_mgr,
128 struct pp_smu_funcs *pp_smu,
129 struct dccg *dccg)
130 {
131 /*register offset changed*/
132 clk_mgr->base.regs = &clk_mgr_regs_dcn351;
133 clk_mgr->base.clk_mgr_shift = &clk_mgr_shift_dcn351;
134 clk_mgr->base.clk_mgr_mask = &clk_mgr_mask_dcn351;
135
136 dcn35_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
137
138 }
139
140
141