1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Support for Intel Camera Imaging ISP subsystem.
4 * Copyright (c) 2015, Intel Corporation.
5 */
6
7 #ifndef __CSI_RX_PRIVATE_H_INCLUDED__
8 #define __CSI_RX_PRIVATE_H_INCLUDED__
9
10 #include "rx_csi_defs.h"
11 #include "mipi_backend_defs.h"
12 #include "csi_rx.h"
13
14 #include "device_access.h" /* ia_css_device_load_uint32 */
15
16 #include "assert_support.h" /* assert */
17 #include "print_support.h" /* print */
18
19 /*****************************************************
20 *
21 * Device level interface (DLI).
22 *
23 *****************************************************/
24 /**
25 * @brief Load the register value.
26 * Refer to "csi_rx_public.h" for details.
27 */
csi_rx_fe_ctrl_reg_load(const csi_rx_frontend_ID_t ID,const hrt_address reg)28 static inline hrt_data csi_rx_fe_ctrl_reg_load(
29 const csi_rx_frontend_ID_t ID,
30 const hrt_address reg)
31 {
32 assert(ID < N_CSI_RX_FRONTEND_ID);
33 assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1);
34 return ia_css_device_load_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof(
35 hrt_data));
36 }
37
38 /**
39 * @brief Store a value to the register.
40 * Refer to "ibuf_ctrl_public.h" for details.
41 */
csi_rx_fe_ctrl_reg_store(const csi_rx_frontend_ID_t ID,const hrt_address reg,const hrt_data value)42 static inline void csi_rx_fe_ctrl_reg_store(
43 const csi_rx_frontend_ID_t ID,
44 const hrt_address reg,
45 const hrt_data value)
46 {
47 assert(ID < N_CSI_RX_FRONTEND_ID);
48 assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1);
49
50 ia_css_device_store_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof(hrt_data),
51 value);
52 }
53
54 /**
55 * @brief Load the register value.
56 * Refer to "csi_rx_public.h" for details.
57 */
csi_rx_be_ctrl_reg_load(const csi_rx_backend_ID_t ID,const hrt_address reg)58 static inline hrt_data csi_rx_be_ctrl_reg_load(
59 const csi_rx_backend_ID_t ID,
60 const hrt_address reg)
61 {
62 assert(ID < N_CSI_RX_BACKEND_ID);
63 assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1);
64 return ia_css_device_load_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg * sizeof(
65 hrt_data));
66 }
67
68 /**
69 * @brief Store a value to the register.
70 * Refer to "ibuf_ctrl_public.h" for details.
71 */
csi_rx_be_ctrl_reg_store(const csi_rx_backend_ID_t ID,const hrt_address reg,const hrt_data value)72 static inline void csi_rx_be_ctrl_reg_store(
73 const csi_rx_backend_ID_t ID,
74 const hrt_address reg,
75 const hrt_data value)
76 {
77 assert(ID < N_CSI_RX_BACKEND_ID);
78 assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1);
79
80 ia_css_device_store_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg * sizeof(hrt_data),
81 value);
82 }
83
84 /* end of DLI */
85
86 /*****************************************************
87 *
88 * Native command interface (NCI).
89 *
90 *****************************************************/
91 /**
92 * @brief Get the state of the csi rx fe dlane process.
93 * Refer to "csi_rx_public.h" for details.
94 */
csi_rx_fe_ctrl_get_dlane_state(const csi_rx_frontend_ID_t ID,const u32 lane,csi_rx_fe_ctrl_lane_t * dlane_state)95 static inline void csi_rx_fe_ctrl_get_dlane_state(
96 const csi_rx_frontend_ID_t ID,
97 const u32 lane,
98 csi_rx_fe_ctrl_lane_t *dlane_state)
99 {
100 dlane_state->termen =
101 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_TERMEN_DLANE_REG_IDX(lane));
102 dlane_state->settle =
103 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_SETTLE_DLANE_REG_IDX(lane));
104 }
105
106 /**
107 * @brief Get the csi rx fe state.
108 * Refer to "csi_rx_public.h" for details.
109 */
csi_rx_fe_ctrl_get_state(const csi_rx_frontend_ID_t ID,csi_rx_fe_ctrl_state_t * state)110 static inline void csi_rx_fe_ctrl_get_state(
111 const csi_rx_frontend_ID_t ID,
112 csi_rx_fe_ctrl_state_t *state)
113 {
114 u32 i;
115
116 state->enable =
117 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_ENABLE_REG_IDX);
118 state->nof_enable_lanes =
119 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_NOF_ENABLED_LANES_REG_IDX);
120 state->error_handling =
121 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_ERROR_HANDLING_REG_IDX);
122 state->status =
123 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_REG_IDX);
124 state->status_dlane_hs =
125 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX);
126 state->status_dlane_lp =
127 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX);
128 state->clane.termen =
129 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_TERMEN_CLANE_REG_IDX);
130 state->clane.settle =
131 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_SETTLE_CLANE_REG_IDX);
132
133 /*
134 * Get the values of the register-set per
135 * dlane.
136 */
137 for (i = 0; i < N_CSI_RX_FE_CTRL_DLANES[ID]; i++) {
138 csi_rx_fe_ctrl_get_dlane_state(
139 ID,
140 i,
141 &state->dlane[i]);
142 }
143 }
144
145 /**
146 * @brief dump the csi rx fe state.
147 * Refer to "csi_rx_public.h" for details.
148 */
csi_rx_fe_ctrl_dump_state(const csi_rx_frontend_ID_t ID,csi_rx_fe_ctrl_state_t * state)149 static inline void csi_rx_fe_ctrl_dump_state(
150 const csi_rx_frontend_ID_t ID,
151 csi_rx_fe_ctrl_state_t *state)
152 {
153 u32 i;
154
155 ia_css_print("CSI RX FE STATE Controller %d Enable state 0x%x\n", ID,
156 state->enable);
157 ia_css_print("CSI RX FE STATE Controller %d No Of enable lanes 0x%x\n", ID,
158 state->nof_enable_lanes);
159 ia_css_print("CSI RX FE STATE Controller %d Error handling 0x%x\n", ID,
160 state->error_handling);
161 ia_css_print("CSI RX FE STATE Controller %d Status 0x%x\n", ID, state->status);
162 ia_css_print("CSI RX FE STATE Controller %d Status Dlane HS 0x%x\n", ID,
163 state->status_dlane_hs);
164 ia_css_print("CSI RX FE STATE Controller %d Status Dlane LP 0x%x\n", ID,
165 state->status_dlane_lp);
166 ia_css_print("CSI RX FE STATE Controller %d Status term enable LP 0x%x\n", ID,
167 state->clane.termen);
168 ia_css_print("CSI RX FE STATE Controller %d Status term settle LP 0x%x\n", ID,
169 state->clane.settle);
170
171 /*
172 * Get the values of the register-set per
173 * dlane.
174 */
175 for (i = 0; i < N_CSI_RX_FE_CTRL_DLANES[ID]; i++) {
176 ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d termen 0x%x\n", ID, i,
177 state->dlane[i].termen);
178 ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d settle 0x%x\n", ID, i,
179 state->dlane[i].settle);
180 }
181 }
182
183 /**
184 * @brief Get the csi rx be state.
185 * Refer to "csi_rx_public.h" for details.
186 */
csi_rx_be_ctrl_get_state(const csi_rx_backend_ID_t ID,csi_rx_be_ctrl_state_t * state)187 static inline void csi_rx_be_ctrl_get_state(
188 const csi_rx_backend_ID_t ID,
189 csi_rx_be_ctrl_state_t *state)
190 {
191 u32 i;
192
193 state->enable =
194 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_ENABLE_REG_IDX);
195
196 state->status =
197 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_STATUS_REG_IDX);
198
199 for (i = 0; i < N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) {
200 state->comp_format_reg[i] =
201 csi_rx_be_ctrl_reg_load(ID,
202 _HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX + i);
203 }
204
205 state->raw16 =
206 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_IDX);
207
208 state->raw18 =
209 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_IDX);
210 state->force_raw8 =
211 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_FORCE_RAW8_REG_IDX);
212 state->irq_status =
213 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_IRQ_STATUS_REG_IDX);
214 #if 0 /* device access error for these registers */
215 /* ToDo: rootcause this failure */
216 state->custom_mode_enable =
217 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_EN_REG_IDX);
218
219 state->custom_mode_data_state =
220 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX);
221 for (i = 0; i < N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) {
222 state->pec[i] =
223 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX + i);
224 }
225 state->custom_mode_valid_eop_config =
226 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_REG_IDX);
227 #endif
228 state->global_lut_disregard_reg =
229 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_IDX);
230 state->packet_status_stall =
231 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_IDX);
232 /*
233 * Get the values of the register-set per
234 * lut.
235 */
236 for (i = 0; i < N_SHORT_PACKET_LUT_ENTRIES[ID]; i++) {
237 state->short_packet_lut_entry[i] =
238 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_IDX + i);
239 }
240 for (i = 0; i < N_LONG_PACKET_LUT_ENTRIES[ID]; i++) {
241 state->long_packet_lut_entry[i] =
242 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_LP_LUT_ENTRY_0_REG_IDX + i);
243 }
244 }
245
246 /**
247 * @brief Dump the csi rx be state.
248 * Refer to "csi_rx_public.h" for details.
249 */
csi_rx_be_ctrl_dump_state(const csi_rx_backend_ID_t ID,csi_rx_be_ctrl_state_t * state)250 static inline void csi_rx_be_ctrl_dump_state(
251 const csi_rx_backend_ID_t ID,
252 csi_rx_be_ctrl_state_t *state)
253 {
254 u32 i;
255
256 ia_css_print("CSI RX BE STATE Controller %d Enable 0x%x\n", ID, state->enable);
257 ia_css_print("CSI RX BE STATE Controller %d Status 0x%x\n", ID, state->status);
258
259 for (i = 0; i < N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) {
260 ia_css_print("CSI RX BE STATE Controller %d comp format reg vc%d value 0x%x\n",
261 ID, i, state->status);
262 }
263 ia_css_print("CSI RX BE STATE Controller %d RAW16 0x%x\n", ID, state->raw16);
264 ia_css_print("CSI RX BE STATE Controller %d RAW18 0x%x\n", ID, state->raw18);
265 ia_css_print("CSI RX BE STATE Controller %d Force RAW8 0x%x\n", ID,
266 state->force_raw8);
267 ia_css_print("CSI RX BE STATE Controller %d IRQ state 0x%x\n", ID,
268 state->irq_status);
269 #if 0 /* ToDo:Getting device access error for this register */
270 for (i = 0; i < N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) {
271 ia_css_print("CSI RX BE STATE Controller %d PEC ID %d custom pec 0x%x\n", ID, i,
272 state->pec[i]);
273 }
274 #endif
275 ia_css_print("CSI RX BE STATE Controller %d Global LUT disregard reg 0x%x\n",
276 ID, state->global_lut_disregard_reg);
277 ia_css_print("CSI RX BE STATE Controller %d packet stall reg 0x%x\n", ID,
278 state->packet_status_stall);
279 /*
280 * Get the values of the register-set per
281 * lut.
282 */
283 for (i = 0; i < N_SHORT_PACKET_LUT_ENTRIES[ID]; i++) {
284 ia_css_print("CSI RX BE STATE Controller ID %d Short packet entry %d short packet lut id 0x%x\n",
285 ID, i,
286 state->short_packet_lut_entry[i]);
287 }
288 for (i = 0; i < N_LONG_PACKET_LUT_ENTRIES[ID]; i++) {
289 ia_css_print("CSI RX BE STATE Controller ID %d Long packet entry %d long packet lut id 0x%x\n",
290 ID, i,
291 state->long_packet_lut_entry[i]);
292 }
293 }
294
295 /* end of NCI */
296
297 #endif /* __CSI_RX_PRIVATE_H_INCLUDED__ */
298