1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * Based on radeon_winsys.h which is:
6 * Copyright 2008 Corbin Simpson <[email protected]>
7 * Copyright 2010 Marek Olšák <[email protected]>
8 *
9 * SPDX-License-Identifier: MIT
10 */
11
12 #ifndef RADV_RADEON_WINSYS_H
13 #define RADV_RADEON_WINSYS_H
14
15 #include <stdbool.h>
16 #include <stdint.h>
17 #include <stdio.h>
18 #include <stdlib.h>
19 #include <string.h>
20 #include "util/u_math.h"
21 #include "util/u_memory.h"
22 #include <vulkan/vulkan.h>
23 #include "amd_family.h"
24
25 struct radeon_info;
26 struct ac_surf_info;
27 struct radeon_surf;
28 struct vk_sync_type;
29 struct vk_sync_wait;
30 struct vk_sync_signal;
31
32 enum radeon_bo_domain { /* bitfield */
33 RADEON_DOMAIN_GTT = 2,
34 RADEON_DOMAIN_VRAM = 4,
35 RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT,
36 RADEON_DOMAIN_GDS = 8,
37 RADEON_DOMAIN_OA = 16,
38 };
39
40 enum radeon_bo_flag { /* bitfield */
41 RADEON_FLAG_GTT_WC = (1 << 0),
42 RADEON_FLAG_CPU_ACCESS = (1 << 1),
43 RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
44 RADEON_FLAG_VIRTUAL = (1 << 3),
45 RADEON_FLAG_VA_UNCACHED = (1 << 4),
46 RADEON_FLAG_IMPLICIT_SYNC = (1 << 5),
47 RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 6),
48 RADEON_FLAG_READ_ONLY = (1 << 7),
49 RADEON_FLAG_32BIT = (1 << 8),
50 RADEON_FLAG_PREFER_LOCAL_BO = (1 << 9),
51 RADEON_FLAG_ZERO_VRAM = (1 << 10),
52 RADEON_FLAG_REPLAYABLE = (1 << 11),
53 RADEON_FLAG_DISCARDABLE = (1 << 12),
54 };
55
56 enum radeon_ctx_priority {
57 RADEON_CTX_PRIORITY_INVALID = -1,
58 RADEON_CTX_PRIORITY_LOW = 0,
59 RADEON_CTX_PRIORITY_MEDIUM,
60 RADEON_CTX_PRIORITY_HIGH,
61 RADEON_CTX_PRIORITY_REALTIME,
62 };
63
64 enum radeon_ctx_pstate {
65 RADEON_CTX_PSTATE_NONE = 0,
66 RADEON_CTX_PSTATE_STANDARD,
67 RADEON_CTX_PSTATE_MIN_SCLK,
68 RADEON_CTX_PSTATE_MIN_MCLK,
69 RADEON_CTX_PSTATE_PEAK,
70 };
71
72 enum radeon_value_id {
73 RADEON_ALLOCATED_VRAM,
74 RADEON_ALLOCATED_VRAM_VIS,
75 RADEON_ALLOCATED_GTT,
76 RADEON_TIMESTAMP,
77 RADEON_NUM_BYTES_MOVED,
78 RADEON_NUM_EVICTIONS,
79 RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
80 RADEON_VRAM_USAGE,
81 RADEON_VRAM_VIS_USAGE,
82 RADEON_GTT_USAGE,
83 RADEON_GPU_TEMPERATURE,
84 RADEON_CURRENT_SCLK,
85 RADEON_CURRENT_MCLK,
86 };
87
88 struct radeon_cmdbuf {
89 /* These are uint64_t to tell the compiler that buf can't alias them.
90 * If they're uint32_t the generated code needs to redundantly
91 * store and reload them between buf writes. */
92 uint64_t cdw; /* Number of used dwords. */
93 uint64_t max_dw; /* Maximum number of dwords. */
94 uint64_t reserved_dw; /* Number of dwords reserved through radeon_check_space() */
95 uint32_t *buf; /* The base pointer of the chunk. */
96 };
97
98 #define RADEON_SURF_TYPE_MASK 0xFF
99 #define RADEON_SURF_TYPE_SHIFT 0
100 #define RADEON_SURF_TYPE_1D 0
101 #define RADEON_SURF_TYPE_2D 1
102 #define RADEON_SURF_TYPE_3D 2
103 #define RADEON_SURF_TYPE_CUBEMAP 3
104 #define RADEON_SURF_TYPE_1D_ARRAY 4
105 #define RADEON_SURF_TYPE_2D_ARRAY 5
106 #define RADEON_SURF_MODE_MASK 0xFF
107 #define RADEON_SURF_MODE_SHIFT 8
108
109 #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_##field##_SHIFT) & RADEON_SURF_##field##_MASK)
110 #define RADEON_SURF_SET(v, field) (((v)&RADEON_SURF_##field##_MASK) << RADEON_SURF_##field##_SHIFT)
111 #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_##field##_MASK << RADEON_SURF_##field##_SHIFT))
112
113 enum radeon_bo_layout {
114 RADEON_LAYOUT_LINEAR = 0,
115 RADEON_LAYOUT_TILED,
116 RADEON_LAYOUT_SQUARETILED,
117
118 RADEON_LAYOUT_UNKNOWN
119 };
120
121 /* Tiling info for display code, DRI sharing, and other data. */
122 struct radeon_bo_metadata {
123 /* Tiling flags describing the texture layout for display code
124 * and DRI sharing.
125 */
126 union {
127 struct {
128 enum radeon_bo_layout microtile;
129 enum radeon_bo_layout macrotile;
130 unsigned pipe_config;
131 unsigned bankw;
132 unsigned bankh;
133 unsigned tile_split;
134 unsigned mtilea;
135 unsigned num_banks;
136 unsigned stride;
137 bool scanout;
138 } legacy;
139
140 struct {
141 /* surface flags */
142 unsigned swizzle_mode : 5;
143 bool scanout;
144 uint32_t dcc_offset_256b;
145 uint32_t dcc_pitch_max;
146 bool dcc_independent_64b_blocks;
147 bool dcc_independent_128b_blocks;
148 unsigned dcc_max_compressed_block_size;
149 } gfx9;
150 } u;
151
152 /* Additional metadata associated with the buffer, in bytes.
153 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
154 * Supported by amdgpu only.
155 */
156 uint32_t size_metadata;
157 uint32_t metadata[64];
158 };
159
160 struct radeon_winsys_ctx;
161
162 struct radeon_winsys_bo {
163 uint64_t va;
164 uint64_t size;
165 /* buffer is created with AMDGPU_GEM_CREATE_VM_ALWAYS_VALID */
166 bool is_local;
167 bool vram_no_cpu_access;
168 /* buffer is added to the BO list of all submissions */
169 bool use_global_list;
170 enum radeon_bo_domain initial_domain;
171 };
172
173 struct radv_winsys_submit_info {
174 enum amd_ip_type ip_type;
175 int queue_index;
176 unsigned cs_count;
177 unsigned initial_preamble_count;
178 unsigned continue_preamble_count;
179 unsigned postamble_count;
180 struct radeon_cmdbuf **cs_array;
181 struct radeon_cmdbuf **initial_preamble_cs;
182 struct radeon_cmdbuf **continue_preamble_cs;
183 struct radeon_cmdbuf **postamble_cs;
184 bool uses_shadow_regs;
185 };
186
187 /* Kernel effectively allows 0-31. This sets some priorities for fixed
188 * functionality buffers */
189 enum {
190 RADV_BO_PRIORITY_APPLICATION_MAX = 28,
191
192 /* virtual buffers have 0 priority since the priority is not used. */
193 RADV_BO_PRIORITY_VIRTUAL = 0,
194
195 RADV_BO_PRIORITY_METADATA = 10,
196 /* This should be considerably lower than most of the stuff below,
197 * but how much lower is hard to say since we don't know application
198 * assignments. Put it pretty high since it is GTT anyway. */
199 RADV_BO_PRIORITY_QUERY_POOL = 29,
200
201 RADV_BO_PRIORITY_DESCRIPTOR = 30,
202 RADV_BO_PRIORITY_UPLOAD_BUFFER = 30,
203 RADV_BO_PRIORITY_FENCE = 30,
204 RADV_BO_PRIORITY_SHADER = 31,
205 RADV_BO_PRIORITY_SCRATCH = 31,
206 RADV_BO_PRIORITY_CS = 31,
207 };
208
209 struct radv_winsys_gpuvm_fault_info {
210 uint64_t addr;
211 uint32_t status;
212 uint32_t vmhub;
213 };
214
215 enum radv_cs_dump_type {
216 RADV_CS_DUMP_TYPE_IBS,
217 RADV_CS_DUMP_TYPE_CTX_ROLLS,
218 };
219
220 struct radeon_winsys {
221 void (*destroy)(struct radeon_winsys *ws);
222
223 void (*query_info)(struct radeon_winsys *ws, struct radeon_info *gpu_info);
224
225 uint64_t (*query_value)(struct radeon_winsys *ws, enum radeon_value_id value);
226
227 bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset, unsigned num_registers, uint32_t *out);
228
229 const char *(*get_chip_name)(struct radeon_winsys *ws);
230
231 bool (*query_gpuvm_fault)(struct radeon_winsys *ws, struct radv_winsys_gpuvm_fault_info *fault_info);
232
233 VkResult (*buffer_create)(struct radeon_winsys *ws, uint64_t size, unsigned alignment, enum radeon_bo_domain domain,
234 enum radeon_bo_flag flags, unsigned priority, uint64_t address,
235 struct radeon_winsys_bo **out_bo);
236
237 void (*buffer_destroy)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo);
238 void *(*buffer_map)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo, bool use_fixed_addr, void *fixed_addr);
239
240 VkResult (*buffer_from_ptr)(struct radeon_winsys *ws, void *pointer, uint64_t size, unsigned priority,
241 struct radeon_winsys_bo **out_bo);
242
243 VkResult (*buffer_from_fd)(struct radeon_winsys *ws, int fd, unsigned priority, struct radeon_winsys_bo **out_bo,
244 uint64_t *alloc_size);
245
246 bool (*buffer_get_fd)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo, int *fd);
247
248 bool (*buffer_get_flags_from_fd)(struct radeon_winsys *ws, int fd, enum radeon_bo_domain *domains,
249 enum radeon_bo_flag *flags);
250
251 void (*buffer_unmap)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo, bool replace);
252
253 void (*buffer_set_metadata)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo, struct radeon_bo_metadata *md);
254 void (*buffer_get_metadata)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo, struct radeon_bo_metadata *md);
255
256 VkResult (*buffer_virtual_bind)(struct radeon_winsys *ws, struct radeon_winsys_bo *parent, uint64_t offset,
257 uint64_t size, struct radeon_winsys_bo *bo, uint64_t bo_offset);
258
259 VkResult (*buffer_make_resident)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo, bool resident);
260
261 VkResult (*ctx_create)(struct radeon_winsys *ws, enum radeon_ctx_priority priority, struct radeon_winsys_ctx **ctx);
262 void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
263
264 bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx, enum amd_ip_type amd_ip_type, int ring_index);
265
266 int (*ctx_set_pstate)(struct radeon_winsys_ctx *ctx, uint32_t pstate);
267
268 enum radeon_bo_domain (*cs_domain)(const struct radeon_winsys *ws);
269
270 struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws, enum amd_ip_type amd_ip_type, bool is_secondary);
271
272 void (*cs_destroy)(struct radeon_cmdbuf *cs);
273
274 void (*cs_reset)(struct radeon_cmdbuf *cs);
275
276 bool (*cs_chain)(struct radeon_cmdbuf *cs, struct radeon_cmdbuf *next_cs, bool pre_en);
277
278 void (*cs_unchain)(struct radeon_cmdbuf *cs);
279
280 VkResult (*cs_finalize)(struct radeon_cmdbuf *cs);
281
282 void (*cs_grow)(struct radeon_cmdbuf *cs, size_t min_size);
283
284 VkResult (*cs_submit)(struct radeon_winsys_ctx *ctx, const struct radv_winsys_submit_info *submit,
285 uint32_t wait_count, const struct vk_sync_wait *waits, uint32_t signal_count,
286 const struct vk_sync_signal *signals);
287
288 void (*cs_add_buffer)(struct radeon_cmdbuf *cs, struct radeon_winsys_bo *bo);
289
290 void (*cs_execute_secondary)(struct radeon_cmdbuf *parent, struct radeon_cmdbuf *child, bool allow_ib2);
291
292 void (*cs_execute_ib)(struct radeon_cmdbuf *cs, struct radeon_winsys_bo *bo, const uint64_t va, const uint32_t cdw,
293 const bool predicate);
294
295 void (*cs_dump)(struct radeon_cmdbuf *cs, FILE *file, const int *trace_ids, int trace_id_count,
296 enum radv_cs_dump_type type);
297
298 void (*cs_annotate)(struct radeon_cmdbuf *cs, const char *marker);
299
300 void (*cs_pad)(struct radeon_cmdbuf *cs, unsigned leave_dw_space);
301
302 void (*dump_bo_ranges)(struct radeon_winsys *ws, FILE *file);
303
304 void (*dump_bo_log)(struct radeon_winsys *ws, FILE *file);
305
306 int (*surface_init)(struct radeon_winsys *ws, const struct ac_surf_info *surf_info, struct radeon_surf *surf);
307
308 int (*get_fd)(struct radeon_winsys *ws);
309
310 struct ac_addrlib *(*get_addrlib)(struct radeon_winsys *ws);
311
312 const struct vk_sync_type *const *(*get_sync_types)(struct radeon_winsys *ws);
313 };
314
315 static inline void
radeon_emit(struct radeon_cmdbuf * cs,uint32_t value)316 radeon_emit(struct radeon_cmdbuf *cs, uint32_t value)
317 {
318 assert(cs->cdw < cs->reserved_dw);
319 cs->buf[cs->cdw++] = value;
320 }
321
322 static inline void
radeon_emit_direct(struct radeon_cmdbuf * cs,uint32_t offset,uint32_t value)323 radeon_emit_direct(struct radeon_cmdbuf *cs, uint32_t offset, uint32_t value)
324 {
325 assert(offset < cs->reserved_dw);
326 cs->buf[offset] = value;
327 }
328
329 static inline void
radeon_emit_array(struct radeon_cmdbuf * cs,const uint32_t * values,unsigned count)330 radeon_emit_array(struct radeon_cmdbuf *cs, const uint32_t *values, unsigned count)
331 {
332 assert(cs->cdw + count <= cs->reserved_dw);
333 memcpy(cs->buf + cs->cdw, values, count * 4);
334 cs->cdw += count;
335 }
336
337 static inline uint64_t
radv_buffer_get_va(const struct radeon_winsys_bo * bo)338 radv_buffer_get_va(const struct radeon_winsys_bo *bo)
339 {
340 return bo->va;
341 }
342
343 static inline bool
radv_buffer_is_resident(const struct radeon_winsys_bo * bo)344 radv_buffer_is_resident(const struct radeon_winsys_bo *bo)
345 {
346 return bo->use_global_list || bo->is_local;
347 }
348
349 static inline void
radv_cs_add_buffer(struct radeon_winsys * ws,struct radeon_cmdbuf * cs,struct radeon_winsys_bo * bo)350 radv_cs_add_buffer(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_winsys_bo *bo)
351 {
352 if (radv_buffer_is_resident(bo))
353 return;
354
355 ws->cs_add_buffer(cs, bo);
356 }
357
358 static inline void *
radv_buffer_map(struct radeon_winsys * ws,struct radeon_winsys_bo * bo)359 radv_buffer_map(struct radeon_winsys *ws, struct radeon_winsys_bo *bo)
360 {
361 return ws->buffer_map(ws, bo, false, NULL);
362 }
363
364 #endif /* RADV_RADEON_WINSYS_H */
365