1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #ifndef __SOC_NVIDIA_TEGRA210_CLOCK_H__
4 #define __SOC_NVIDIA_TEGRA210_CLOCK_H__
5
6 #include <arch/hlt.h>
7 #include <console/console.h>
8 #include <device/mmio.h>
9 #include <soc/clk_rst.h>
10 #include <stdint.h>
11
12 enum {
13 CLK_L_CPU = 0x1 << 0,
14 CLK_L_COP = 0x1 << 1,
15 CLK_L_TRIG_SYS = 0x1 << 2,
16 CLK_L_RTC = 0x1 << 4,
17 CLK_L_TMR = 0x1 << 5,
18 CLK_L_UARTA = 0x1 << 6,
19 CLK_L_UARTB = 0x1 << 7,
20 CLK_L_GPIO = 0x1 << 8,
21 CLK_L_SDMMC2 = 0x1 << 9,
22 CLK_L_SPDIF = 0x1 << 10,
23 CLK_L_I2S2 = 0x1 << 11,
24 CLK_L_I2C1 = 0x1 << 12,
25 CLK_L_NDFLASH = 0x1 << 13,
26 CLK_L_SDMMC1 = 0x1 << 14,
27 CLK_L_SDMMC4 = 0x1 << 15,
28 CLK_L_PWM = 0x1 << 17,
29 CLK_L_I2S3 = 0x1 << 18,
30 CLK_L_EPP = 0x1 << 19,
31 CLK_L_VI = 0x1 << 20,
32 CLK_L_2D = 0x1 << 21,
33 CLK_L_USBD = 0x1 << 22,
34 CLK_L_ISP = 0x1 << 23,
35 CLK_L_3D = 0x1 << 24,
36 CLK_L_DISP2 = 0x1 << 26,
37 CLK_L_DISP1 = 0x1 << 27,
38 CLK_L_HOST1X = 0x1 << 28,
39 CLK_L_VCP = 0x1 << 29,
40 CLK_L_I2S1 = 0x1 << 30,
41 CLK_L_CACHE2 = 0x1 << 31,
42
43 CLK_H_MEM = 0x1 << 0,
44 CLK_H_AHBDMA = 0x1 << 1,
45 CLK_H_APBDMA = 0x1 << 2,
46 CLK_H_KBC = 0x1 << 4,
47 CLK_H_STAT_MON = 0x1 << 5,
48 CLK_H_PMC = 0x1 << 6,
49 CLK_H_FUSE = 0x1 << 7,
50 CLK_H_KFUSE = 0x1 << 8,
51 CLK_H_SBC1 = 0x1 << 9,
52 CLK_H_SNOR = 0x1 << 10,
53 CLK_H_JTAG2TBC = 0x1 << 11,
54 CLK_H_SBC2 = 0x1 << 12,
55 CLK_H_SBC3 = 0x1 << 14,
56 CLK_H_I2C5 = 0x1 << 15,
57 CLK_H_DSI = 0x1 << 16,
58 CLK_H_HSI = 0x1 << 18,
59 CLK_H_HDMI = 0x1 << 19,
60 CLK_H_CSI = 0x1 << 20,
61 CLK_H_I2C2 = 0x1 << 22,
62 CLK_H_UARTC = 0x1 << 23,
63 CLK_H_MIPI_CAL = 0x1 << 24,
64 CLK_H_EMC = 0x1 << 25,
65 CLK_H_USB2 = 0x1 << 26,
66 CLK_H_USB3 = 0x1 << 27,
67 CLK_H_MPE = 0x1 << 28,
68 CLK_H_VDE = 0x1 << 29,
69 CLK_H_BSEA = 0x1 << 30,
70 CLK_H_BSEV = 0x1 << 31,
71
72 CLK_U_UARTD = 0x1 << 1,
73 CLK_U_UARTE = 0x1 << 2,
74 CLK_U_I2C3 = 0x1 << 3,
75 CLK_U_SBC4 = 0x1 << 4,
76 CLK_U_SDMMC3 = 0x1 << 5,
77 CLK_U_PCIE = 0x1 << 6,
78 CLK_U_OWR = 0x1 << 7,
79 CLK_U_AFI = 0x1 << 8,
80 CLK_U_CSITE = 0x1 << 9,
81 CLK_U_PCIEXCLK = 0x1 << 10,
82 CLK_U_AVPUCQ = 0x1 << 11,
83 CLK_U_TRACECLKIN = 0x1 << 13,
84 CLK_U_SOC_THERM = 0x1 << 14,
85 CLK_U_DTV = 0x1 << 15,
86 CLK_U_NAND_SPEED = 0x1 << 16,
87 CLK_U_I2C_SLOW = 0x1 << 17,
88 CLK_U_DSIB = 0x1 << 18,
89 CLK_U_TSEC = 0x1 << 19,
90 CLK_U_IRAMA = 0x1 << 20,
91 CLK_U_IRAMB = 0x1 << 21,
92 CLK_U_IRAMC = 0x1 << 22,
93
94 // Clock reset.
95 CLK_U_EMUCIF = 0x1 << 23,
96 // Clock enable.
97 CLK_U_IRAMD = 0x1 << 23,
98
99 CLK_U_CRAM2 = 0x2 << 24,
100 CLK_U_XUSB_HOST = 0x1 << 25,
101 CLK_U_MSENC = 0x1 << 27,
102 CLK_U_SUS_OUT = 0x1 << 28,
103 CLK_U_DEV2_OUT = 0x1 << 29,
104 CLK_U_DEV1_OUT = 0x1 << 30,
105 CLK_U_XUSB_DEV = 0x1 << 31,
106
107 CLK_V_CPUG = 0x1 << 0,
108 CLK_V_CPULP = 0x1 << 1,
109 CLK_V_3D2 = 0x1 << 2,
110 CLK_V_MSELECT = 0x1 << 3,
111 CLK_V_I2S4 = 0x1 << 5,
112 CLK_V_I2S5 = 0x1 << 6,
113 CLK_V_I2C4 = 0x1 << 7,
114 CLK_V_SBC5 = 0x1 << 8,
115 CLK_V_SBC6 = 0x1 << 9,
116 CLK_V_AHUB = 0x1 << 10,
117 CLK_V_APB2APE = 0x1 << 11,
118 CLK_V_HDA2CODEC_2X = 0x1 << 15,
119 CLK_V_ATOMICS = 0x1 << 16,
120 CLK_V_ACTMON = 0x1 << 23,
121 CLK_V_EXTPERIPH1 = 0x1 << 24,
122 CLK_V_SATA = 0x1 << 28,
123 CLK_V_HDA = 0x1 << 29,
124
125 CLK_W_HDA2HDMICODEC = 0x1 << 0,
126 CLK_W_SATACOLD = 0x1 << 1,
127 CLK_W_CEC = 0x1 << 8,
128 CLK_W_XUSB_PADCTL = 0x1 << 14,
129 CLK_W_ENTROPY = 0x1 << 21,
130 CLK_W_DVFS = 0x1 << 27,
131 CLK_W_XUSB_SS = 0x1 << 28,
132
133 CLK_X_GPU = 0x1 << 24,
134 CLK_X_SOR1 = 0x1 << 23,
135 CLK_X_SOR0 = 0x1 << 22,
136 CLK_X_DPAUX = 0x1 << 21,
137 CLK_X_VIC = 0x1 << 18,
138 CLK_X_UART_FST_MIPI_CAL = 0x1 << 17,
139 CLK_X_MIPIBIF = 0x1 << 13,
140 CLK_X_I2C6 = 0x1 << 6,
141 CLK_X_ETR = 0x1 << 3,
142 CLK_X_SPARE = 0x1 << 0,
143
144 CLK_Y_APE = 0x1 << 6,
145 CLK_Y_DPAUX1 = 0x1 << 15,
146 CLK_Y_QSPI = 0x1 << 19,
147 CLK_Y_SOR_SAFE = 0x1 << 30,
148 };
149
150 enum {
151 PLLP = 0,
152 PLLC2 = 1,
153 PLLC = 2,
154 PLLC_OUT1 = 3,
155 PLLM = 4,
156 CLK_M = 5,
157 CLK_S = 6,
158 PLLE = 7,
159 PLLA = 8,
160 PLLD = 9,
161 PLLD2 = 10,
162 PLLC4_OUT0 = 11,
163 PLLC4_OUT1 = 12,
164 PLLC4_OUT2 = 13,
165 PLLC4_OUT3 = 14,
166 PLLC4_OUT0_L = 15,
167 PLLC4_OUT1_L = 16,
168 PLLC4_OUT2_L = 17,
169 PLLD_OUT0 = 18,
170 PLLP_OUT3 = 19,
171 PLLC2_OUT0 = 20,
172 UNUSED0 = 100,
173 UNUSED1 = 101,
174 UNUSED2 = 102,
175 UNUSED3 = 103,
176 UNUSED4 = 104,
177 UNUSED5 = 105,
178 UNUSED6 = 106,
179 UNUSED7 = 107,
180 };
181
182 #define CLK_SRC_DEV_ID(dev, src) CLK_SRC_##dev##_##src
183 #define CLK_SRC_FREQ_ID(dev, src) CLK_SRC_FREQ_##dev##_##src
184
185 #define CLK_SRC_DEVICE(dev, a, b, c, d, e, f, g, h) \
186 CLK_SRC_DEV_ID(dev, a) = 0, \
187 CLK_SRC_DEV_ID(dev, b) = 1, \
188 CLK_SRC_DEV_ID(dev, c) = 2, \
189 CLK_SRC_DEV_ID(dev, d) = 3, \
190 CLK_SRC_DEV_ID(dev, e) = 4, \
191 CLK_SRC_DEV_ID(dev, f) = 5, \
192 CLK_SRC_DEV_ID(dev, g) = 6, \
193 CLK_SRC_DEV_ID(dev, h) = 7, \
194 CLK_SRC_FREQ_ID(dev, a) = a, \
195 CLK_SRC_FREQ_ID(dev, b) = b, \
196 CLK_SRC_FREQ_ID(dev, c) = c, \
197 CLK_SRC_FREQ_ID(dev, d) = d, \
198 CLK_SRC_FREQ_ID(dev, e) = e, \
199 CLK_SRC_FREQ_ID(dev, f) = f, \
200 CLK_SRC_FREQ_ID(dev, g) = g, \
201 CLK_SRC_FREQ_ID(dev, h) = h
202
203 enum {
204 CLK_SRC_DEVICE(disp1, PLLP, PLLD, PLLD_OUT0, UNUSED3, UNUSED4, PLLD2,
205 CLK_M, UNUSED7),
206 CLK_SRC_DEVICE(host1x, PLLC4_OUT1, PLLC2, PLLC, PLLC4_OUT2, PLLP, CLK_M,
207 PLLA, PLLC4_OUT0),
208 CLK_SRC_DEVICE(I2C1, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4, PLLC4_OUT1,
209 CLK_M, PLLC4_OUT2),
210 CLK_SRC_DEVICE(I2C2, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4, PLLC4_OUT1,
211 CLK_M, PLLC4_OUT2),
212 CLK_SRC_DEVICE(I2C3, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4, PLLC4_OUT1,
213 CLK_M, PLLC4_OUT2),
214 CLK_SRC_DEVICE(I2C5, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4, PLLC4_OUT1,
215 CLK_M, PLLC4_OUT2),
216 CLK_SRC_DEVICE(I2C6, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4, PLLC4_OUT1,
217 CLK_M, PLLC4_OUT2),
218 CLK_SRC_DEVICE(I2S1, PLLA, UNUSED1, CLK_S, UNUSED3, PLLP, UNUSED5,
219 CLK_M, UNUSED7),
220 CLK_SRC_DEVICE(mselect, PLLP, PLLC2, PLLC, PLLC4_OUT2, PLLC4_OUT1,
221 CLK_S, CLK_M, PLLC4_OUT0),
222 CLK_SRC_DEVICE(SPI1, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4, PLLC4_OUT1,
223 CLK_M, PLLC4_OUT2),
224 CLK_SRC_DEVICE(SPI4, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4, PLLC4_OUT1,
225 CLK_M, PLLC4_OUT2),
226 CLK_SRC_DEVICE(SDMMC1, PLLP, PLLA, PLLC, PLLC4_OUT2, PLLM, PLLE, CLK_M,
227 PLLC4_OUT0),
228 CLK_SRC_DEVICE(SDMMC4, PLLP, PLLC4_OUT2_L, PLLC4_OUT0_L, PLLC4_OUT2,
229 PLLC4_OUT1, PLLC4_OUT1_L, CLK_M, PLLC4_OUT0),
230 CLK_SRC_DEVICE(UARTA, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4,
231 PLLC4_OUT1, CLK_M, PLLC4_OUT2),
232 CLK_SRC_DEVICE(UARTB, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4,
233 PLLC4_OUT1, CLK_M, PLLC4_OUT2),
234 CLK_SRC_DEVICE(UARTC, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4,
235 PLLC4_OUT1, CLK_M, PLLC4_OUT2),
236 CLK_SRC_DEVICE(UARTD, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4,
237 PLLC4_OUT1, CLK_M, PLLC4_OUT2),
238 CLK_SRC_DEVICE(UARTE, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4,
239 PLLC4_OUT1, CLK_M, PLLC4_OUT2),
240 CLK_SRC_DEVICE(i2s1, PLLA, UNUSED1, CLK_S, UNUSED3, PLLP, UNUSED5,
241 CLK_M, UNUSED7),
242 CLK_SRC_DEVICE(extperiph1, PLLA, CLK_S, PLLP, CLK_M, PLLE, UNUSED5,
243 UNUSED6, UNUSED7),
244 CLK_SRC_DEVICE(QSPI, PLLP, PLLC_OUT1, PLLC, UNUSED3, PLLC4_OUT2,
245 PLLC4_OUT1, CLK_M, PLLC4_OUT0),
246 CLK_SRC_DEVICE(uart_fst_mipi_cal, PLLP_OUT3, PLLP, PLLC, UNUSED3, PLLC2_OUT0,
247 UNUSED5, CLK_M, UNUSED7),
248 };
249
250 /* PLL stabilization delay in usec */
251 #define CLOCK_PLL_STABLE_DELAY_US 300
252
253 #define IO_STABILIZATION_DELAY (2)
254 #define LOGIC_STABILIZATION_DELAY (2)
255
256 /* Calculate clock fractional divider value from ref and target frequencies.
257 * This is for a U7.1 format. This is not well written up in the book and
258 * there have been some questions about this macro, so here we go.
259 * U7.1 format is defined as (ddddddd+1) + (h*.5)
260 * The lowest order bit is actually a fractional bit.
261 * Hence, the divider can be thought of as 9 bits.
262 * So:
263 * divider = ((ref/freq) << 1 - 1) (upper 7 bits) |
264 * (ref/freq & 1) (low order half-bit)
265 * however we can't do fractional arithmetic ... these are integers!
266 * So we normalize by shifting the result left 1 bit, and extracting
267 * ddddddd and h directly to the returned u8.
268 * divider = 2*(ref/freq);
269 * We want to
270 * preserve 7 bits of divisor and one bit of fraction, in 8 bits, as well as
271 * subtract one from ddddddd. Since we computed ref*2, the dddddd is now nicely
272 * situated in the upper 7 bits, and the h is sitting there in the low order
273 * bit. To subtract 1 from ddddddd, just subtract 2 from the 8-bit number
274 * and voila, upper 7 bits are (ref/freq-1), and lowest bit is h. Since you
275 * will assign this to a u8, it gets nicely truncated for you.
276 */
277 #define CLK_DIVIDER(REF, FREQ) (DIV_ROUND_UP(((REF) * 2), (FREQ)) - 2)
278
279 /* Calculate clock frequency value from reference and clock divider value
280 * The discussion in the book is pretty lacking.
281 * The idea is that we need to divide a ref clock by a divisor
282 * in U7.1 format, where 7 upper bits are the integer
283 * and lowest order bit is a fraction.
284 * from the book, U7.1 is (ddddddd+1) + (h*.5)
285 * To normalize to an actual number, we might do this:
286 * ((d>>7+1)&0x7f) + (d&1 >> 1)
287 * but as you might guess, the low order bit would be lost.
288 * Since we can't express the fractional bit, we need to multiply it all by 2.
289 * ((d + 2)&0xfe) + (d & 1)
290 * Since we're just adding +2, the lowest order bit is preserved. Hence
291 * (d+2) is the same as ((d + 2)&0xfe) + (d & 1)
292 *
293 * Since you multiply denominator * 2 (by NOT shifting it),
294 * you multiply numerator * 2 to cancel it out.
295 */
296 #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / ((REG) + 2))
297
_clock_set_div(u32 * reg,const char * name,u32 div,u32 div_mask,u32 src)298 static inline void _clock_set_div(u32 *reg, const char *name, u32 div,
299 u32 div_mask, u32 src)
300 {
301 // The I2C and UART divisors are 16 bit while all the others are 8 bit.
302 // The I2C clocks are handled by the specialized macro below, but the
303 // UART clocks aren't. Don't use this function on UART clocks.
304 if (div & ~div_mask) {
305 printk(BIOS_ERR, "%s clock divisor overflow!", name);
306 hlt();
307 }
308 clrsetbits32(reg, CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
309 src << CLK_SOURCE_SHIFT | div);
310 }
311
312 #define get_i2c_clk_div(src, freq) \
313 (DIV_ROUND_UP(src, (freq) * (0x19 + 1) * 8) - 1)
314 #define get_clk_div(src,freq) CLK_DIVIDER(src,freq)
315 #define CLK_DIV_MASK 0xff
316 #define CLK_DIV_MASK_I2C 0xffff
317
318 #define clock_configure_source(device, src, freq) \
319 _clock_set_div(CLK_RST_REG(clk_src_##device), #device, \
320 get_clk_div(TEGRA_##src##_KHZ, freq), CLK_DIV_MASK, \
321 CLK_SRC_DEV_ID(device, src))
322
323 /* soc-specific */
324 #define TEGRA_CLK_M_KHZ (clock_get_osc_khz()/2)
325 #define TEGRA_PLLX_KHZ CONFIG_PLLX_KHZ
326 #define TEGRA_PLLP_KHZ (408000)
327 #define TEGRA_PLLP_OUT3_KHZ (68000)
328 #define TEGRA_PLLC_KHZ (600000)
329 #define TEGRA_PLLD_KHZ (925000)
330 #define TEGRA_PLLD_OUT0_KHZ (TEGRA_PLLD_KHZ/2)
331 #define TEGRA_PLLU_KHZ (960000)
332
333 #define clock_enable(l, h, u, v, w, x, y) \
334 do { \
335 u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x, y}; \
336 clock_enable_regs(bits); \
337 } while (0)
338
339 #define clock_disable(l, h, u, v, w, x, y) \
340 do { \
341 u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x, y}; \
342 clock_disable_regs(bits); \
343 } while (0)
344
345 #define clock_set_reset(l, h, u, v, w, x, y) \
346 do { \
347 u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x, y}; \
348 clock_set_reset_regs(bits); \
349 } while (0)
350
351 #define clock_clr_reset(l, h, u, v, w, x, y) \
352 do { \
353 u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x, y}; \
354 clock_clr_reset_regs(bits); \
355 } while (0)
356
357 #define clock_enable_l(l) clock_enable(l, 0, 0, 0, 0, 0, 0)
358 #define clock_enable_h(h) clock_enable(0, h, 0, 0, 0, 0, 0)
359 #define clock_enable_u(u) clock_enable(0, 0, u, 0, 0, 0, 0)
360 #define clock_enable_v(v) clock_enable(0, 0, 0, v, 0, 0, 0)
361 #define clock_enable_w(w) clock_enable(0, 0, 0, 0, w, 0, 0)
362 #define clock_enable_x(x) clock_enable(0, 0, 0, 0, 0, x, 0)
363 #define clock_enable_y(y) clock_enable(0, 0, 0, 0, 0, 0, y)
364
365 #define clock_disable_l(l) clock_disable(l, 0, 0, 0, 0, 0, 0)
366 #define clock_disable_h(h) clock_disable(0, h, 0, 0, 0, 0, 0)
367 #define clock_disable_u(u) clock_disable(0, 0, u, 0, 0, 0, 0)
368 #define clock_disable_v(v) clock_disable(0, 0, 0, v, 0, 0, 0)
369 #define clock_disable_w(w) clock_disable(0, 0, 0, 0, w, 0, 0)
370 #define clock_disable_x(x) clock_disable(0, 0, 0, 0, 0, x, 0)
371 #define clock_disable_y(y) clock_disable(0, 0, 0, 0, 0, 0, y)
372
373 #define clock_set_reset_l(l) clock_set_reset(l, 0, 0, 0, 0, 0, 0)
374 #define clock_set_reset_h(h) clock_set_reset(0, h, 0, 0, 0, 0, 0)
375 #define clock_set_reset_u(u) clock_set_reset(0, 0, u, 0, 0, 0, 0)
376 #define clock_set_reset_v(v) clock_set_reset(0, 0, 0, v, 0, 0, 0)
377 #define clock_set_reset_w(w) clock_set_reset(0, 0, 0, 0, w, 0, 0)
378 #define clock_set_reset_x(x) clock_set_reset(0, 0, 0, 0, 0, x, 0)
379 #define clock_set_reset_y(x) clock_set_reset(0, 0, 0, 0, 0, y, 0)
380
381 #define clock_clr_reset_l(l) clock_clr_reset(l, 0, 0, 0, 0, 0, 0)
382 #define clock_clr_reset_h(h) clock_clr_reset(0, h, 0, 0, 0, 0, 0)
383 #define clock_clr_reset_u(u) clock_clr_reset(0, 0, u, 0, 0, 0, 0)
384 #define clock_clr_reset_v(v) clock_clr_reset(0, 0, 0, v, 0, 0, 0)
385 #define clock_clr_reset_w(w) clock_clr_reset(0, 0, 0, 0, w, 0, 0)
386 #define clock_clr_reset_x(x) clock_clr_reset(0, 0, 0, 0, 0, x, 0)
387 #define clock_clr_reset_y(y) clock_clr_reset(0, 0, 0, 0, 0, 0, y)
388
389 #define clock_enable_clear_reset_l(l) \
390 clock_enable_clear_reset(l, 0, 0, 0, 0, 0, 0)
391 #define clock_enable_clear_reset_h(h) \
392 clock_enable_clear_reset(0, h, 0, 0, 0, 0, 0)
393 #define clock_enable_clear_reset_u(u) \
394 clock_enable_clear_reset(0, 0, u, 0, 0, 0, 0)
395 #define clock_enable_clear_reset_v(v) \
396 clock_enable_clear_reset(0, 0, 0, v, 0, 0, 0)
397 #define clock_enable_clear_reset_w(w) \
398 clock_enable_clear_reset(0, 0, 0, 0, w, 0, 0)
399 #define clock_enable_clear_reset_x(x) \
400 clock_enable_clear_reset(0, 0, 0, 0, 0, x, 0)
401 #define clock_enable_clear_reset_y(y) \
402 clock_enable_clear_reset(0, 0, 0, 0, 0, 0, y)
403
404 int clock_get_osc_khz(void);
405 int clock_get_pll_input_khz(void);
406 /*
407 * Configure PLLD to requested frequency. Returned value is closest match
408 * within the PLLD's constraints or 0 if an error.
409 */
410 u32 clock_configure_plld(u32 frequency);
411 void clock_early_uart(void);
412 void clock_external_output(int clk_id);
413 void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 kvco, u32 kcp,
414 u32 stable_time, u32 emc_source, u32 same_freq);
415 void clock_cpu0_config(void);
416 void clock_halt_avp(void);
417 void clock_enable_regs(u32 bits[DEV_CONFIG_BLOCKS]);
418 void clock_disable_regs(u32 bits[DEV_CONFIG_BLOCKS]);
419 void clock_set_reset_regs(u32 bits[DEV_CONFIG_BLOCKS]);
420 void clock_clr_reset_regs(u32 bits[DEV_CONFIG_BLOCKS]);
421 void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x, u32 y);
422 void clock_grp_enable_clear_reset(u32 val, u32 *clk_enb_set_reg,
423 u32 *rst_dev_clr_reg);
424 void clock_reset_l(u32 l);
425 void clock_reset_h(u32 h);
426 void clock_reset_u(u32 u);
427 void clock_reset_v(u32 v);
428 void clock_reset_w(u32 w);
429 void clock_reset_x(u32 x);
430 void clock_reset_y(u32 y);
431 void clock_init(void);
432 void clock_init_arm_generic_timer(void);
433 void sor_clock_stop(void);
434 void sor_clock_start(void);
435 void clock_enable_audio(void);
436
437 #endif /* __SOC_NVIDIA_TEGRA210_CLOCK_H__ */
438