1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_NVIDIA_TEGRA210_FUNIT_CFG_H 4 #define __SOC_NVIDIA_TEGRA210_FUNIT_CFG_H 5 6 #include <soc/clock.h> 7 #include <soc/padconfig.h> 8 #include <soc/pinmux.h> 9 #include <stdint.h> 10 11 #define FUNIT_INDEX(_name) FUNIT_##_name 12 13 enum { 14 FUNIT_INDEX(I2C1), 15 FUNIT_INDEX(I2C2), 16 FUNIT_INDEX(I2C3), 17 FUNIT_INDEX(I2C5), 18 FUNIT_INDEX(I2C6), 19 FUNIT_INDEX(SDMMC1), 20 FUNIT_INDEX(SDMMC4), 21 FUNIT_INDEX(USBD), 22 FUNIT_INDEX(USB2), 23 FUNIT_INDEX(QSPI), 24 FUNIT_INDEX(I2S1), 25 FUNIT_INDEX_MAX, 26 }; 27 28 /* 29 * Note: these bus numbers are dependent on the driver implementations, and 30 * currently the I2C is 0-based and SPI is 1-based in its indexing. 31 */ 32 enum { 33 I2C1_BUS = 0, 34 I2C2_BUS = 1, 35 I2C3_BUS = 2, 36 I2C5_BUS = 4, 37 I2CPWR_BUS = I2C5_BUS, 38 I2C6_BUS = 5, 39 QSPI_BUS = 7, 40 41 SPI1_BUS = 1, 42 SPI4_BUS = 4, 43 }; 44 45 struct funit_cfg { 46 uint32_t funit_index; 47 uint32_t clk_src_id; 48 uint32_t clk_src_freq_id; 49 uint32_t clk_dev_freq_khz; 50 struct pad_config const* pad_cfg; 51 size_t pad_cfg_size; 52 }; 53 54 #define FUNIT_CFG(_funit,_clk_src,_clk_freq,_cfg,_cfg_size) \ 55 { \ 56 .funit_index = FUNIT_INDEX(_funit), \ 57 .clk_src_id = CLK_SRC_DEV_ID(_funit, _clk_src), \ 58 .clk_src_freq_id = CLK_SRC_FREQ_ID(_funit, _clk_src), \ 59 .clk_dev_freq_khz = _clk_freq, \ 60 .pad_cfg = _cfg, \ 61 .pad_cfg_size = _cfg_size, \ 62 } 63 64 #define FUNIT_CFG_USB(_funit) \ 65 { \ 66 .funit_index = FUNIT_INDEX(_funit), \ 67 .pad_cfg = NULL, \ 68 .pad_cfg_size = 0, \ 69 } 70 71 /* 72 * Configure the funits associated with entry according to the configuration. 73 */ 74 void soc_configure_funits(const struct funit_cfg * const entries, size_t num); 75 76 #endif /* __SOC_NVIDIA_TEGRA210_FUNIT_CFG_H */ 77