1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_MEDIATEK_DSI_COMMON_H 4 #define SOC_MEDIATEK_DSI_COMMON_H 5 6 #include <commonlib/helpers.h> 7 #include <edid.h> 8 #include <mipi/dsi.h> 9 #include <types.h> 10 #include <soc/addressmap.h> 11 12 enum mipi_dsi_pixel_format { 13 MIPI_DSI_FMT_RGB888, 14 MIPI_DSI_FMT_RGB666, 15 MIPI_DSI_FMT_RGB666_PACKED, 16 MIPI_DSI_FMT_RGB565 17 }; 18 19 /* video mode */ 20 enum { 21 MIPI_DSI_MODE_VIDEO = BIT(0), 22 /* video burst mode */ 23 MIPI_DSI_MODE_VIDEO_BURST = BIT(1), 24 /* video pulse mode */ 25 MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2), 26 /* enable auto vertical count mode */ 27 MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3), 28 /* enable hsync-end packets in vsync-pulse and v-porch area */ 29 MIPI_DSI_MODE_VIDEO_HSE = BIT(4), 30 /* disable hfront-porch area */ 31 MIPI_DSI_MODE_VIDEO_HFP = BIT(5), 32 /* disable hback-porch area */ 33 MIPI_DSI_MODE_VIDEO_HBP = BIT(6), 34 /* disable hsync-active area */ 35 MIPI_DSI_MODE_VIDEO_HSA = BIT(7), 36 /* flush display FIFO on vsync pulse */ 37 MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8), 38 /* disable EoT packets in HS mode */ 39 MIPI_DSI_MODE_EOT_PACKET = BIT(9), 40 /* device supports non-continuous clock behavior (DSI spec 5.6.1) */ 41 MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10), 42 /* transmit data in low power */ 43 MIPI_DSI_MODE_LPM = BIT(11), 44 /* dsi per line's data end same time on all lanes */ 45 MIPI_DSI_MODE_LINE_END = BIT(12), 46 }; 47 48 static struct dsi_regs *const dsi0 = (void *)DSI0_BASE; 49 50 /* DSI_INTSTA */ 51 enum { 52 LPRX_RD_RDY_INT_FLAG = BIT(0), 53 CMD_DONE_INT_FLAG = BIT(1), 54 TE_RDY_INT_FLAG = BIT(2), 55 VM_DONE_INT_FLAG = BIT(3), 56 EXT_TE_RDY_INT_FLAG = BIT(4), 57 DSI_BUSY = BIT(31), 58 }; 59 60 /* DSI_CON_CTRL */ 61 enum { 62 DSI_RESET = BIT(0), 63 DSI_EN = BIT(1), 64 DPHY_RESET = BIT(2), 65 DSI_DUAL = BIT(4), 66 }; 67 68 /* DSI_MODE_CTRL */ 69 enum { 70 MODE = 3, 71 CMD_MODE = 0, 72 SYNC_PULSE_MODE = 1, 73 SYNC_EVENT_MODE = 2, 74 BURST_MODE = 3, 75 FRM_MODE = BIT(16), 76 MIX_MODE = BIT(17) 77 }; 78 79 /* DSI_TXRX_CTRL */ 80 enum { 81 EOTP_DISABLE = BIT(6), 82 NON_CONTINUOUS_CLK = BIT(16), 83 }; 84 85 /* DSI_PSCTRL */ 86 enum { 87 DSI_PS_WC = 0x3fff, 88 DSI_PS_SEL = (3 << 16), 89 PACKED_PS_16BIT_RGB565 = (0 << 16), 90 LOOSELY_PS_18BIT_RGB666 = (1 << 16), 91 PACKED_PS_18BIT_RGB666 = (2 << 16), 92 PACKED_PS_24BIT_RGB888 = (3 << 16), 93 94 DSI_PSCON_CUSTOM_HEADER_SHIFT = 26, 95 }; 96 97 /* DSI_SIZE_CON */ 98 enum { 99 DSI_SIZE_CON_HEIGHT_SHIFT = 16, 100 DSI_SIZE_CON_WIDTH_SHIFT = 0, 101 }; 102 103 /* DSI_CMDQ_SIZE */ 104 enum { 105 CMDQ_SIZE = 0x3f, 106 }; 107 108 /* DSI_PHY_LCCON */ 109 enum { 110 LC_HS_TX_EN = BIT(0), 111 LC_ULPM_EN = BIT(1), 112 LC_WAKEUP_EN = BIT(2) 113 }; 114 115 /*DSI_PHY_LD0CON */ 116 enum { 117 LD0_RM_TRIG_EN = BIT(0), 118 LD0_ULPM_EN = BIT(1), 119 LD0_WAKEUP_EN = BIT(2) 120 }; 121 122 enum { 123 LPX = (0xff << 0), 124 HS_PRPR = (0xff << 8), 125 HS_ZERO = (0xff << 16), 126 HS_TRAIL = (0xff << 24) 127 }; 128 129 enum { 130 TA_GO = (0xff << 0), 131 TA_SURE = (0xff << 8), 132 TA_GET = (0xff << 16), 133 DA_HS_EXIT = (0xff << 24) 134 }; 135 136 enum { 137 CONT_DET = (0xff << 0), 138 CLK_ZERO = (0xf << 16), 139 CLK_TRAIL = (0xff << 24) 140 }; 141 142 enum { 143 CLK_HS_PRPR = (0xff << 0), 144 CLK_HS_POST = (0xff << 8), 145 CLK_HS_EXIT = (0xf << 16) 146 }; 147 148 /* DSI_VM_CMD_CON */ 149 enum { 150 VM_CMD_EN = BIT(0), 151 TS_VFP_EN = BIT(5), 152 }; 153 154 /* DSI_CMDQ0 */ 155 enum { 156 CONFIG = (0xff << 0), 157 SHORT_PACKET = 0, 158 LONG_PACKET = 2, 159 BTA = BIT(2), 160 DATA_ID = (0xff << 8), 161 DATA_0 = (0xff << 16), 162 DATA_1 = (0xff << 24), 163 }; 164 165 /* DSI_FORCE_COMMIT */ 166 enum { 167 DSI_FORCE_COMMIT_USE_MMSYS = BIT(0), 168 DSI_FORCE_COMMIT_ALWAYS = BIT(1), 169 }; 170 171 struct mtk_phy_timing { 172 u8 lpx; 173 u8 da_hs_prepare; 174 u8 da_hs_zero; 175 u8 da_hs_trail; 176 177 u8 ta_go; 178 u8 ta_sure; 179 u8 ta_get; 180 u8 da_hs_exit; 181 182 u8 da_hs_sync; 183 u8 clk_hs_zero; 184 u8 clk_hs_trail; 185 186 u8 clk_hs_prepare; 187 u8 clk_hs_post; 188 u8 clk_hs_exit; 189 190 u32 d_phy; 191 }; 192 193 /* Functions that each SOC should provide. */ 194 void mtk_dsi_reset(void); 195 void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes); 196 197 /* Functions as weak no-ops that can be overridden. */ 198 void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing); 199 200 /* Public API provided in common/dsi.c */ 201 int mtk_dsi_bpp_from_format(u32 format); 202 int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid, 203 const u8 *init_commands); 204 205 #endif /* SOC_MEDIATEK_DSI_COMMON_H */ 206