1 /*********************************************************************************************************************** 2 * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. 3 * 4 * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products 5 * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are 6 * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use 7 * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property 8 * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas 9 * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION 10 * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT 11 * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES 12 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR 13 * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM 14 * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION 15 * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, 16 * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, 17 * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY 18 * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. 19 **********************************************************************************************************************/ 20 21 #ifndef R_GPT_H 22 #define R_GPT_H 23 24 /*******************************************************************************************************************//** 25 * @addtogroup GPT 26 * @{ 27 **********************************************************************************************************************/ 28 29 /*********************************************************************************************************************** 30 * Includes 31 **********************************************************************************************************************/ 32 #include "bsp_api.h" 33 #include "r_timer_api.h" 34 35 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 36 FSP_HEADER 37 38 /*********************************************************************************************************************** 39 * Macro definitions 40 **********************************************************************************************************************/ 41 42 /*********************************************************************************************************************** 43 * Typedef definitions 44 **********************************************************************************************************************/ 45 46 /** Input/Output pins, used to select which duty cycle to update in R_GPT_DutyCycleSet(). */ 47 typedef enum e_gpt_io_pin 48 { 49 GPT_IO_PIN_GTIOCA = 0, ///< GTIOCA 50 GPT_IO_PIN_GTIOCB = 1, ///< GTIOCB 51 GPT_IO_PIN_GTIOCA_AND_GTIOCB = 2, ///< GTIOCA and GTIOCB 52 GPT_IO_PIN_TROUGH = 4, ///< Used in @ref R_GPT_DutyCycleSet when Triangle-wave PWM Mode 3 is selected. 53 GPT_IO_PIN_CREST = 8, ///< Used in @ref R_GPT_DutyCycleSet when Triangle-wave PWM Mode 3 is selected. 54 GPT_IO_PIN_ONE_SHOT_LEADING_EDGE = 4, ///< Used in @ref R_GPT_DutyCycleSet to set GTCCRC and GTCCRE registers when One-Shot Pulse mode is selected. 55 GPT_IO_PIN_ONE_SHOT_TRAILING_EDGE = 8, ///< Used in @ref R_GPT_DutyCycleSet to set GTCCRD and GTCCRF registers when One-Shot Pulse mode is selected. 56 } gpt_io_pin_t; 57 58 /** Forced buffer push operation used in One-Sot Pulse mode with R_GPT_DutyCycleSet(). */ 59 typedef enum e_gpt_buffer_force_push 60 { 61 GPT_BUFFER_FORCE_PUSH = 64, ///< Used in @ref R_GPT_DutyCycleSet to force push the data from GTCCRn registers to temporary buffer A or B when One-Shot Pulse mode is selected. 62 } gpt_buffer_force_push; 63 64 /** Level of GPT pin */ 65 typedef enum e_gpt_pin_level 66 { 67 GPT_PIN_LEVEL_LOW = 0, ///< Pin level low 68 GPT_PIN_LEVEL_HIGH = 1, ///< Pin level high 69 } gpt_pin_level_t; 70 71 /** Sources can be used to start the timer, stop the timer, count up, or count down. These enumerations represent 72 * a bitmask. Multiple sources can be ORed together. */ 73 typedef enum e_gpt_source 74 { 75 /** No active event sources. */ 76 GPT_SOURCE_NONE = 0U, 77 78 /** Action performed on GTETRGA rising edge. **/ 79 GPT_SOURCE_GTETRGA_RISING = (1U << 0), 80 81 /** Action performed on GTETRGA falling edge. **/ 82 GPT_SOURCE_GTETRGA_FALLING = (1U << 1), 83 84 /** Action performed on GTETRGB rising edge. **/ 85 GPT_SOURCE_GTETRGB_RISING = (1U << 2), 86 87 /** Action performed on GTETRGB falling edge. **/ 88 GPT_SOURCE_GTETRGB_FALLING = (1U << 3), 89 90 /** Action performed on GTETRGC rising edge. **/ 91 GPT_SOURCE_GTETRGC_RISING = (1U << 4), 92 93 /** Action performed on GTETRGC falling edge. **/ 94 GPT_SOURCE_GTETRGC_FALLING = (1U << 5), 95 96 /** Action performed on GTETRGB rising edge. **/ 97 GPT_SOURCE_GTETRGD_RISING = (1U << 6), 98 99 /** Action performed on GTETRGB falling edge. **/ 100 GPT_SOURCE_GTETRGD_FALLING = (1U << 7), 101 102 /** Action performed when GTIOCA input rises while GTIOCB is low. **/ 103 GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW = (1U << 8), 104 105 /** Action performed when GTIOCA input rises while GTIOCB is high. **/ 106 GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH = (1U << 9), 107 108 /** Action performed when GTIOCA input falls while GTIOCB is low. **/ 109 GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW = (1U << 10), 110 111 /** Action performed when GTIOCA input falls while GTIOCB is high. **/ 112 GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH = (1U << 11), 113 114 /** Action performed when GTIOCB input rises while GTIOCA is low. **/ 115 GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_LOW = (1U << 12), 116 117 /** Action performed when GTIOCB input rises while GTIOCA is high. **/ 118 GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_HIGH = (1U << 13), 119 120 /** Action performed when GTIOCB input falls while GTIOCA is low. **/ 121 GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_LOW = (1U << 14), 122 123 /** Action performed when GTIOCB input falls while GTIOCA is high. **/ 124 GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_HIGH = (1U << 15), 125 126 /** Action performed on ELC GPTA event. **/ 127 GPT_SOURCE_GPT_A = (1U << 16), 128 129 /** Action performed on ELC GPTB event. **/ 130 GPT_SOURCE_GPT_B = (1U << 17), 131 132 /** Action performed on ELC GPTC event. **/ 133 GPT_SOURCE_GPT_C = (1U << 18), 134 135 /** Action performed on ELC GPTD event. **/ 136 GPT_SOURCE_GPT_D = (1U << 19), 137 138 /** Action performed on ELC GPTE event. **/ 139 GPT_SOURCE_GPT_E = (1U << 20), 140 141 /** Action performed on ELC GPTF event. **/ 142 GPT_SOURCE_GPT_F = (1U << 21), 143 144 /** Action performed on ELC GPTG event. **/ 145 GPT_SOURCE_GPT_G = (1U << 22), 146 147 /** Action performed on ELC GPTH event. **/ 148 GPT_SOURCE_GPT_H = (1U << 23), 149 } gpt_source_t; 150 151 /** Configurations for output pins. */ 152 typedef struct s_gpt_output_pin 153 { 154 bool output_enabled; ///< Set to true to enable output, false to disable output 155 gpt_pin_level_t stop_level; ///< Select a stop level from ::gpt_pin_level_t 156 } gpt_output_pin_t; 157 158 /** Custom GTIOR settings used for configuring GTIOCxA and GTIOCxB pins. */ 159 typedef struct s_gpt_gtior_setting 160 { 161 union 162 { 163 uint32_t gtior; 164 struct 165 { 166 /* Settings for GTIOCxA pin. */ 167 uint32_t gtioa : 5; ///< GTIOCA Pin Function Select. 168 uint32_t : 1; // Reserved 169 uint32_t oadflt : 1; ///< GTIOCA Pin Output Value Setting at the Count Stop. 170 uint32_t oahld : 1; ///< GTIOCA Pin Output Setting at the Start/Stop Count. 171 uint32_t oae : 1; ///< GTIOCA Pin Output Enable 172 uint32_t oadf : 2; ///< GTIOCA Pin Disable Value Setting. 173 uint32_t : 2; /// Reserved 174 uint32_t nfaen : 1; /// Noise Filter A Enable. 175 uint32_t nfcsa : 2; /// Noise Filter A Sampling Clock Select. 176 177 /* Settings for GTIOCxB pin. */ 178 uint32_t gtiob : 5; ///< GTIOCB Pin Function Select. 179 uint32_t : 1; // Reserved 180 uint32_t obdflt : 1; ///< GTIOCB Pin Output Value Setting at the Count Stop. 181 uint32_t obhld : 1; ///< GTIOCB Pin Output Setting at the Start/Stop Count. 182 uint32_t obe : 1; ///< GTIOCB Pin Output Enable 183 uint32_t obdf : 2; ///< GTIOCB Pin Disable Value Setting. 184 uint32_t : 2; /// Reserved 185 uint32_t nfben : 1; /// Noise Filter B Enable. 186 uint32_t nfcsb : 2; /// Noise Filter B Sampling Clock Select. 187 } gtior_b; 188 }; 189 } gpt_gtior_setting_t; 190 191 /** Input capture signal noise filter (debounce) setting. Only available for input signals GTIOCxA and GTIOCxB. 192 * The noise filter samples the external signal at intervals of the PCLK divided by one of the values. 193 * When 3 consecutive samples are at the same level (high or low), then that level is passed on as 194 * the observed state of the signal. See "Noise Filter Function" in the hardware manual, GPT section. 195 */ 196 typedef enum e_gpt_capture_filter 197 { 198 GPT_CAPTURE_FILTER_NONE = 0U, ///< None - no filtering 199 GPT_CAPTURE_FILTER_PCLKD_DIV_1 = 1U, ///< PCLK/1 - fast sampling 200 GPT_CAPTURE_FILTER_PCLKD_DIV_4 = 3U, ///< PCLK/4 201 GPT_CAPTURE_FILTER_PCLKD_DIV_16 = 5U, ///< PCLK/16 202 GPT_CAPTURE_FILTER_PCLKD_DIV_64 = 7U, ///< PCLK/64 - slow sampling 203 } gpt_capture_filter_t; 204 205 /** Trigger options to start A/D conversion. */ 206 typedef enum e_gpt_adc_trigger 207 { 208 GPT_ADC_TRIGGER_NONE = 0U, ///< None - no output disable request 209 GPT_ADC_TRIGGER_UP_COUNT_START_ADC_A = 1U << 0, ///< Request A/D conversion from ADC unit 0 at up counting compare match of @ref gpt_extended_pwm_cfg_t::adc_a_compare_match 210 GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_A = 1U << 1, ///< Request A/D conversion from ADC unit 0 at down counting compare match of @ref gpt_extended_pwm_cfg_t::adc_a_compare_match 211 GPT_ADC_TRIGGER_UP_COUNT_START_ADC_B = 1U << 2, ///< Request A/D conversion from ADC unit 1 at up counting compare match of @ref gpt_extended_pwm_cfg_t::adc_b_compare_match 212 GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_B = 1U << 3, ///< Request A/D conversion from ADC unit 1 at down counting compare match of @ref gpt_extended_pwm_cfg_t::adc_b_compare_match 213 } gpt_adc_trigger_t; 214 215 /** POEG channel to link to this channel. */ 216 typedef enum e_gpt_poeg_link 217 { 218 GPT_POEG_LINK_POEG0 = 0U, ///< Link this GPT channel to POEG channel 0 (GTETRGA) 219 GPT_POEG_LINK_POEG1 = 1U, ///< Link this GPT channel to POEG channel 1 (GTETRGB) 220 GPT_POEG_LINK_POEG2 = 2U, ///< Link this GPT channel to POEG channel 2 (GTETRGC) 221 GPT_POEG_LINK_POEG3 = 3U, ///< Link this GPT channel to POEG channel 3 (GTETRGD) 222 } gpt_poeg_link_t; 223 224 /** Select trigger to send output disable request to POEG. */ 225 typedef enum e_gpt_output_disable 226 { 227 GPT_OUTPUT_DISABLE_NONE = 0U, ///< None - no output disable request 228 GPT_OUTPUT_DISABLE_DEAD_TIME_ERROR = 1U << 0, ///< Request output disable if a dead time error occurs 229 GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_HIGH = 1U << 1, ///< Request output disable if GTIOCA and GTIOCB are high at the same time 230 GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_LOW = 1U << 2, ///< Request output disable if GTIOCA and GTIOCB are low at the same time 231 } gpt_output_disable_t; 232 233 /** Disable level options for GTIOC pins. */ 234 typedef enum e_gpt_gtioc_disable 235 { 236 GPT_GTIOC_DISABLE_PROHIBITED = 0U, ///< Do not allow output disable 237 GPT_GTIOC_DISABLE_SET_HI_Z = 1U, ///< Set GTIOC to high impedance when output is disabled 238 GPT_GTIOC_DISABLE_LEVEL_LOW = 2U, ///< Set GTIOC level low when output is disabled 239 GPT_GTIOC_DISABLE_LEVEL_HIGH = 3U, ///< Set GTIOC level high when output is disabled 240 } gpt_gtioc_disable_t; 241 242 /** Trigger options to start A/D conversion. */ 243 typedef enum e_gpt_adc_compare_match 244 { 245 GPT_ADC_COMPARE_MATCH_ADC_A = 0U, ///< Set A/D conversion start request value for GPT A/D converter start request A 246 GPT_ADC_COMPARE_MATCH_ADC_B = 3U, ///< Set A/D conversion start request value for GPT A/D converter start request B 247 } gpt_adc_compare_match_t; 248 249 /** Interrupt skipping modes */ 250 typedef enum e_gpt_interrupt_skip_source 251 { 252 GPT_INTERRUPT_SKIP_SOURCE_NONE = 0U, ///< Do not skip interrupts 253 GPT_INTERRUPT_SKIP_SOURCE_OVERFLOW_UNDERFLOW = 1U, ///< Count and skip overflow and underflow interrupts 254 255 /** Count crest interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in 256 * @ref gpt_interrupt_skip_count_t. When the interrupt does fire, the trough interrupt fires before the crest 257 * interrupt. */ 258 GPT_INTERRUPT_SKIP_SOURCE_CREST = 1U, 259 260 /** Count trough interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in 261 * @ref gpt_interrupt_skip_count_t. When the interrupt does fire, the crest interrupt fires before the trough 262 * interrupt. */ 263 GPT_INTERRUPT_SKIP_SOURCE_TROUGH = 2U, 264 } gpt_interrupt_skip_source_t; 265 266 /** Number of interrupts to skip between events */ 267 typedef enum e_gpt_interrupt_skip_count 268 { 269 GPT_INTERRUPT_SKIP_COUNT_0 = 0U, ///< Do not skip interrupts 270 GPT_INTERRUPT_SKIP_COUNT_1, ///< Skip one interrupt 271 GPT_INTERRUPT_SKIP_COUNT_2, ///< Skip two interrupts 272 GPT_INTERRUPT_SKIP_COUNT_3, ///< Skip three interrupts 273 GPT_INTERRUPT_SKIP_COUNT_4, ///< Skip four interrupts 274 GPT_INTERRUPT_SKIP_COUNT_5, ///< Skip five interrupts 275 GPT_INTERRUPT_SKIP_COUNT_6, ///< Skip six interrupts 276 GPT_INTERRUPT_SKIP_COUNT_7, ///< Skip seven interrupts 277 } gpt_interrupt_skip_count_t; 278 279 /** ADC events to skip during interrupt skipping */ 280 typedef enum e_gpt_interrupt_skip_adc 281 { 282 GPT_INTERRUPT_SKIP_ADC_NONE = 0U, ///< Do not skip ADC events 283 GPT_INTERRUPT_SKIP_ADC_A = 1U, ///< Skip ADC A events 284 GPT_INTERRUPT_SKIP_ADC_B = 4U, ///< Skip ADC B events 285 GPT_INTERRUPT_SKIP_ADC_A_AND_B = 5U, ///< Skip ADC A and B events 286 } gpt_interrupt_skip_adc_t; 287 288 /** Delay setting for the PWM Delay Generation Circuit (PDG). */ 289 typedef enum e_gpt_pwm_output_delay_setting 290 { 291 GPT_PWM_OUTPUT_DELAY_SETTING_0_32, ///< Delay is not applied. 292 GPT_PWM_OUTPUT_DELAY_SETTING_1_32, ///< Delay of 1 / 32 GTCLK period applied. 293 GPT_PWM_OUTPUT_DELAY_SETTING_2_32, ///< Delay of 2 / 32 GTCLK period applied. 294 GPT_PWM_OUTPUT_DELAY_SETTING_3_32, ///< Delay of 3 / 32 GTCLK period applied. 295 GPT_PWM_OUTPUT_DELAY_SETTING_4_32, ///< Delay of 4 / 32 GTCLK period applied. 296 GPT_PWM_OUTPUT_DELAY_SETTING_5_32, ///< Delay of 5 / 32 GTCLK period applied. 297 GPT_PWM_OUTPUT_DELAY_SETTING_6_32, ///< Delay of 6 / 32 GTCLK period applied. 298 GPT_PWM_OUTPUT_DELAY_SETTING_7_32, ///< Delay of 7 / 32 GTCLK period applied. 299 GPT_PWM_OUTPUT_DELAY_SETTING_8_32, ///< Delay of 8 / 32 GTCLK period applied. 300 GPT_PWM_OUTPUT_DELAY_SETTING_9_32, ///< Delay of 9 / 32 GTCLK period applied. 301 GPT_PWM_OUTPUT_DELAY_SETTING_10_32, ///< Delay of 10 / 32 GTCLK period applied. 302 GPT_PWM_OUTPUT_DELAY_SETTING_11_32, ///< Delay of 11 / 32 GTCLK period applied. 303 GPT_PWM_OUTPUT_DELAY_SETTING_12_32, ///< Delay of 12 / 32 GTCLK period applied. 304 GPT_PWM_OUTPUT_DELAY_SETTING_13_32, ///< Delay of 13 / 32 GTCLK period applied. 305 GPT_PWM_OUTPUT_DELAY_SETTING_14_32, ///< Delay of 14 / 32 GTCLK period applied. 306 GPT_PWM_OUTPUT_DELAY_SETTING_15_32, ///< Delay of 15 / 32 GTCLK period applied. 307 GPT_PWM_OUTPUT_DELAY_SETTING_16_32, ///< Delay of 16 / 32 GTCLK period applied. 308 GPT_PWM_OUTPUT_DELAY_SETTING_17_32, ///< Delay of 17 / 32 GTCLK period applied. 309 GPT_PWM_OUTPUT_DELAY_SETTING_18_32, ///< Delay of 18 / 32 GTCLK period applied. 310 GPT_PWM_OUTPUT_DELAY_SETTING_19_32, ///< Delay of 19 / 32 GTCLK period applied. 311 GPT_PWM_OUTPUT_DELAY_SETTING_20_32, ///< Delay of 20 / 32 GTCLK period applied. 312 GPT_PWM_OUTPUT_DELAY_SETTING_21_32, ///< Delay of 21 / 32 GTCLK period applied. 313 GPT_PWM_OUTPUT_DELAY_SETTING_22_32, ///< Delay of 22 / 32 GTCLK period applied. 314 GPT_PWM_OUTPUT_DELAY_SETTING_23_32, ///< Delay of 23 / 32 GTCLK period applied. 315 GPT_PWM_OUTPUT_DELAY_SETTING_24_32, ///< Delay of 24 / 32 GTCLK period applied. 316 GPT_PWM_OUTPUT_DELAY_SETTING_25_32, ///< Delay of 25 / 32 GTCLK period applied. 317 GPT_PWM_OUTPUT_DELAY_SETTING_26_32, ///< Delay of 26 / 32 GTCLK period applied. 318 GPT_PWM_OUTPUT_DELAY_SETTING_27_32, ///< Delay of 27 / 32 GTCLK period applied. 319 GPT_PWM_OUTPUT_DELAY_SETTING_28_32, ///< Delay of 28 / 32 GTCLK period applied. 320 GPT_PWM_OUTPUT_DELAY_SETTING_29_32, ///< Delay of 29 / 32 GTCLK period applied. 321 GPT_PWM_OUTPUT_DELAY_SETTING_30_32, ///< Delay of 30 / 32 GTCLK period applied. 322 GPT_PWM_OUTPUT_DELAY_SETTING_31_32, ///< Delay of 31 / 32 GTCLK period applied. 323 GPT_PWM_OUTPUT_DELAY_SETTING_BYPASS, ///< Bypass the PWM Output Delay Circuit. 324 } gpt_pwm_output_delay_setting_t; 325 326 /** Select which PWM Output Delay setting to apply. */ 327 typedef enum e_gpt_pwm_output_delay_edge 328 { 329 GPT_PWM_OUTPUT_DELAY_EDGE_RISING, ///< Configure the PWM Output Delay setting for rising edge. 330 GPT_PWM_OUTPUT_DELAY_EDGE_FALLING, ///< Configure the PWM Output Delay setting for falling edge. 331 } gpt_pwm_output_delay_edge_t; 332 333 /** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */ 334 typedef struct st_gpt_instance_ctrl 335 { 336 uint32_t open; // Whether or not channel is open 337 const timer_cfg_t * p_cfg; // Pointer to initial configurations 338 R_GPT0_Type * p_reg; // Base register for this channel 339 uint32_t channel_mask; // Channel bitmask 340 timer_variant_t variant; // Timer variant 341 342 void (* p_callback)(timer_callback_args_t *); // Pointer to callback 343 timer_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory 344 void const * p_context; // Pointer to context to be passed into callback function 345 } gpt_instance_ctrl_t; 346 347 /** GPT extension for advanced PWM features. */ 348 typedef struct st_gpt_extended_pwm_cfg 349 { 350 uint8_t trough_ipl; ///< Trough interrupt priority 351 IRQn_Type trough_irq; ///< Trough interrupt 352 gpt_poeg_link_t poeg_link; ///< Select which POEG channel controls output disable for this GPT channel 353 gpt_output_disable_t output_disable; ///< Select which trigger sources request output disable from POEG 354 gpt_adc_trigger_t adc_trigger; ///< Select trigger sources to start A/D conversion 355 uint32_t dead_time_count_up; ///< Set a dead time value for counting up 356 uint32_t dead_time_count_down; ///< Set a dead time value for counting down (available on GPT32E and GPT32EH only) 357 uint32_t adc_a_compare_match; ///< Select the compare match value used to trigger an A/D conversion start request using ELC_EVENT_GPT<channel>_AD_TRIG_A 358 uint32_t adc_b_compare_match; ///< Select the compare match value used to trigger an A/D conversion start request using ELC_EVENT_GPT<channel>_AD_TRIG_B 359 gpt_interrupt_skip_source_t interrupt_skip_source; ///< Interrupt source to count for interrupt skipping 360 gpt_interrupt_skip_count_t interrupt_skip_count; ///< Number of interrupts to skip between events 361 gpt_interrupt_skip_adc_t interrupt_skip_adc; ///< ADC events to skip when interrupt skipping is enabled 362 gpt_gtioc_disable_t gtioca_disable_setting; ///< DEPRECATED - Select how to configure GTIOCA when output is disabled 363 gpt_gtioc_disable_t gtiocb_disable_setting; ///< DEPRECATED - Select how to configure GTIOCB when output is disabled 364 } gpt_extended_pwm_cfg_t; 365 366 /** GPT extension configures the output pins for GPT. */ 367 typedef struct st_gpt_extended_cfg 368 { 369 gpt_output_pin_t gtioca; ///< DEPRECATED - Configuration for GPT I/O pin A 370 gpt_output_pin_t gtiocb; ///< DEPRECATED - Configuration for GPT I/O pin B 371 gpt_source_t start_source; ///< Event sources that trigger the timer to start 372 gpt_source_t stop_source; ///< Event sources that trigger the timer to stop 373 gpt_source_t clear_source; ///< Event sources that trigger the timer to clear 374 gpt_source_t capture_a_source; ///< Event sources that trigger capture of GTIOCA 375 gpt_source_t capture_b_source; ///< Event sources that trigger capture of GTIOCB 376 377 /** Event sources that trigger a single up count. If GPT_SOURCE_NONE is selected for both count_up_source 378 * and count_down_source, then the timer count source is PCLK. */ 379 gpt_source_t count_up_source; 380 381 /** Event sources that trigger a single down count. If GPT_SOURCE_NONE is selected for both count_up_source 382 * and count_down_source, then the timer count source is PCLK. */ 383 gpt_source_t count_down_source; 384 385 /* Debounce filter for GTIOCxA input signal pin (DEPRECATED). */ 386 gpt_capture_filter_t capture_filter_gtioca; 387 388 /* Debounce filter for GTIOCxB input signal pin (DEPRECATED). */ 389 gpt_capture_filter_t capture_filter_gtiocb; 390 391 uint8_t capture_a_ipl; ///< Capture A interrupt priority 392 uint8_t capture_b_ipl; ///< Capture B interrupt priority 393 IRQn_Type capture_a_irq; ///< Capture A interrupt 394 IRQn_Type capture_b_irq; ///< Capture B interrupt 395 gpt_extended_pwm_cfg_t const * p_pwm_cfg; ///< Advanced PWM features, optional 396 gpt_gtior_setting_t gtior_setting; ///< Custom GTIOR settings used for configuring GTIOCxA and GTIOCxB pins. 397 } gpt_extended_cfg_t; 398 399 /********************************************************************************************************************** 400 * Exported global variables 401 **********************************************************************************************************************/ 402 403 /** @cond INC_HEADER_DEFS_SEC */ 404 /** Filled in Interface API structure for this Instance. */ 405 extern const timer_api_t g_timer_on_gpt; 406 407 /** @endcond */ 408 409 /*********************************************************************************************************************** 410 * Public APIs 411 **********************************************************************************************************************/ 412 fsp_err_t R_GPT_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); 413 fsp_err_t R_GPT_Stop(timer_ctrl_t * const p_ctrl); 414 fsp_err_t R_GPT_Start(timer_ctrl_t * const p_ctrl); 415 fsp_err_t R_GPT_Reset(timer_ctrl_t * const p_ctrl); 416 fsp_err_t R_GPT_Enable(timer_ctrl_t * const p_ctrl); 417 fsp_err_t R_GPT_Disable(timer_ctrl_t * const p_ctrl); 418 fsp_err_t R_GPT_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts); 419 fsp_err_t R_GPT_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin); 420 fsp_err_t R_GPT_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info); 421 fsp_err_t R_GPT_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); 422 fsp_err_t R_GPT_CounterSet(timer_ctrl_t * const p_ctrl, uint32_t counter); 423 fsp_err_t R_GPT_OutputEnable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin); 424 fsp_err_t R_GPT_OutputDisable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin); 425 fsp_err_t R_GPT_AdcTriggerSet(timer_ctrl_t * const p_ctrl, 426 gpt_adc_compare_match_t which_compare_match, 427 uint32_t compare_match_value); 428 fsp_err_t R_GPT_PwmOutputDelaySet(timer_ctrl_t * const p_ctrl, 429 gpt_pwm_output_delay_edge_t edge, 430 gpt_pwm_output_delay_setting_t delay_setting, 431 uint32_t const pin); 432 fsp_err_t R_GPT_CallbackSet(timer_ctrl_t * const p_api_ctrl, 433 void ( * p_callback)(timer_callback_args_t *), 434 void const * const p_context, 435 timer_callback_args_t * const p_callback_memory); 436 fsp_err_t R_GPT_Close(timer_ctrl_t * const p_ctrl); 437 fsp_err_t R_GPT_PwmOutputDelayInitialize(); 438 439 /*******************************************************************************************************************//** 440 * @} (end defgroup GPT) 441 **********************************************************************************************************************/ 442 443 /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 444 FSP_FOOTER 445 446 #endif 447