1 /***********************************************************************************************************************
2 * Copyright [2015-2017] Renesas Electronics Corporation and/or its licensors. All Rights Reserved.
3 *
4 * This file is part of Renesas SynergyTM Software Package (SSP)
5 *
6 * The contents of this file (the "contents") are proprietary and confidential to Renesas Electronics Corporation
7 * and/or its licensors ("Renesas") and subject to statutory and contractual protections.
8 *
9 * This file is subject to a Renesas SSP license agreement. Unless otherwise agreed in an SSP license agreement with
10 * Renesas: 1) you may not use, copy, modify, distribute, display, or perform the contents; 2) you may not use any name
11 * or mark of Renesas for advertising or publicity purposes or in connection with your use of the contents; 3) RENESAS
12 * MAKES NO WARRANTY OR REPRESENTATIONS ABOUT THE SUITABILITY OF THE CONTENTS FOR ANY PURPOSE; THE CONTENTS ARE PROVIDED
13 * "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
14 * PARTICULAR PURPOSE, AND NON-INFRINGEMENT; AND 4) RENESAS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, OR
15 * CONSEQUENTIAL DAMAGES, INCLUDING DAMAGES RESULTING FROM LOSS OF USE, DATA, OR PROJECTS, WHETHER IN AN ACTION OF
16 * CONTRACT OR TORT, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE CONTENTS. Third-party contents
17 * included in this file may be subject to different terms.
18 **********************************************************************************************************************/
19 /***********************************************************************************************************************
20 * File Name : bsp_clocks.c
21 * Description : Calls the CGC module to setup the system clocks. Settings for clocks are based on macros in
22 * bsp_clock_cfg.h.
23 ***********************************************************************************************************************/
24
25 /*******************************************************************************************************************//**
26 * @ingroup BSP_MCU_S1JA
27 * @defgroup BSP_MCU_CLOCKS_S1JA Clock Initialization
28 *
29 * Functions in this file configure the system clocks based upon the macros in bsp_clock_cfg.h.
30 *
31 * @{
32 **********************************************************************************************************************/
33
34
35
36 /***********************************************************************************************************************
37 Includes <System Includes> , "Project Includes"
38 ***********************************************************************************************************************/
39 #include "bsp_api.h"
40
41 #if defined(BSP_MCU_GROUP_S1JA)
42
43 #include "r_cgc_api.h"
44 #include "r_cgc.h"
45
46 /***********************************************************************************************************************
47 Macro definitions
48 ***********************************************************************************************************************/
49 #define CGC_ZERO_WAIT_CYCLES (0U)
50 #define CGC_TWO_WAIT_CYCLES (1U)
51
52 #define CGC_MAX_ZERO_WAIT_FREQ (32000000U)
53
54 /* Key code for writing PRCR register. */
55 #define CGC_PRCR_KEY (0xA500U)
56 #define CGC_PRCR_UNLOCK ((CGC_PRCR_KEY) | 0x1U)
57 #define CGC_PRCR_LOCK ((CGC_PRCR_KEY) | 0x0U)
58
59 /***********************************************************************************************************************
60 Typedef definitions
61 ***********************************************************************************************************************/
62
63 /***********************************************************************************************************************
64 Exported global variables (to be accessed by other files)
65 ***********************************************************************************************************************/
66
67 /***********************************************************************************************************************
68 Private global variables and functions
69 ***********************************************************************************************************************/
70
71 /*******************************************************************************************************************//**
72 * @brief Sets up system clocks.
73 **********************************************************************************************************************/
bsp_clock_init(void)74 void bsp_clock_init (void)
75 {
76 ssp_err_t err = SSP_SUCCESS;
77 cgc_system_clock_cfg_t sys_cfg;
78 cgc_clock_t clock;
79
80 g_cgc_on_cgc.init();
81
82 R_BSP_CacheSet(BSP_CACHE_STATE_ON); // Turn on cache.
83
84 /** MOCO is default clock out of reset. Enable new clock if chosen. S1JA has no PLL. */
85 clock = BSP_CFG_CLOCK_SOURCE;
86 err = g_cgc_on_cgc.clockStart(clock, NULL);
87
88 /** If the system clock has failed to start call the unrecoverable error handler. */
89 if((SSP_SUCCESS != err) && (SSP_ERR_CLOCK_ACTIVE != err))
90 {
91 BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(0);
92 }
93
94 /** MOCO, LOCO, and subclock do not have stabilization flags that can be checked. */
95 if ((CGC_CLOCK_MOCO != clock) && (CGC_CLOCK_LOCO != clock) && (CGC_CLOCK_SUBCLOCK != clock))
96 {
97 while (SSP_ERR_STABILIZED != g_cgc_on_cgc.clockCheck(clock))
98 {
99 /** Wait for clock source to stabilize */
100 }
101 }
102
103 sys_cfg.iclk_div = BSP_CFG_ICK_DIV;
104 sys_cfg.pclkb_div = BSP_CFG_PCKB_DIV;
105 sys_cfg.pclkd_div = BSP_CFG_PCKD_DIV;
106 sys_cfg.fclk_div = BSP_CFG_FCK_DIV;
107
108 /** Set which clock to use for system clock and divisors for all system clocks. */
109 err = g_cgc_on_cgc.systemClockSet(clock, &sys_cfg);
110
111 /** If the system clock has failed to be configured properly call the unrecoverable error handler. */
112 if(SSP_SUCCESS != err)
113 {
114 BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(0);
115 }
116 }
117
118 /*******************************************************************************************************************//**
119 * @brief Returns frequency of CPU clock in Hz.
120 *
121 * @retval Frequency of the CPU in Hertz
122 **********************************************************************************************************************/
bsp_cpu_clock_get(void)123 uint32_t bsp_cpu_clock_get (void)
124 {
125 uint32_t freq = (uint32_t)0;
126
127 g_cgc_on_cgc.systemClockFreqGet(CGC_SYSTEM_CLOCKS_ICLK, &freq);
128
129 return freq;
130 }
131
132 /*******************************************************************************************************************//**
133 * @brief This function sets the value of the MEMWAIT register which controls wait cycles for flash read access.
134 * @param[in] setting
135 * @retval none
136 **********************************************************************************************************************/
bsp_clocks_mem_wait_set(uint32_t setting)137 __STATIC_INLINE void bsp_clocks_mem_wait_set (uint32_t setting)
138 {
139 R_SYSTEM->PRCR = CGC_PRCR_UNLOCK;
140 R_SYSTEM->MEMWAITCR_b.MEMWAIT = (uint8_t)(setting & 0x01);
141 R_SYSTEM->PRCR = CGC_PRCR_LOCK;
142 }
143
144
145 /*******************************************************************************************************************//**
146 * @brief This function gets the value of the MEMWAIT register
147 * @retval MEMWAIT setting
148 **********************************************************************************************************************/
bsp_clocks_mem_wait_get(void)149 __STATIC_INLINE uint32_t bsp_clocks_mem_wait_get (void)
150 {
151 return (R_SYSTEM->MEMWAITCR_b.MEMWAIT);
152 }
153
bsp_clock_set_callback(bsp_clock_set_callback_args_t * p_args)154 ssp_err_t bsp_clock_set_callback(bsp_clock_set_callback_args_t * p_args)
155 {
156 uint32_t current_frequency = p_args->current_freq_hz;
157 if (BSP_CLOCK_SET_EVENT_PRE_CHANGE == p_args->event)
158 {
159 uint32_t requested_frequency = p_args->requested_freq_hz;
160
161 /* If the requested frequency is greater than 32 MHz, the current frequency must be less than 32 MHz and the
162 * mcu must be in high speed mode, before changing wait cycles to 2.
163 * S1JA does not require SRAM wait state control. In fact the register is unimplemented for the S1JA. */
164 if (requested_frequency > CGC_MAX_ZERO_WAIT_FREQ)
165 {
166 if ((((current_frequency <= CGC_MAX_ZERO_WAIT_FREQ)) &&
167 (0 == R_SYSTEM->OPCCR_b.OPCM)))
168 {
169 bsp_clocks_mem_wait_set(CGC_TWO_WAIT_CYCLES); // change ROM wait cycles if frequency not above 32 MHz and in
170 // high speed mode
171 }
172 else if (bsp_clocks_mem_wait_get() != CGC_TWO_WAIT_CYCLES)
173 {
174 return SSP_ERR_INVALID_MODE; // else, error if not in 2 wait cycles already
175 }
176 else
177 {
178 /* following coding rules */
179 }
180 }
181 }
182 if (BSP_CLOCK_SET_EVENT_POST_CHANGE == p_args->event)
183 {
184 /** The current frequency must be less than 32 MHz and the mcu must be in high speed mode, before changing
185 * wait cycles to 0.
186 */
187 if (((current_frequency <= CGC_MAX_ZERO_WAIT_FREQ)) && (0 == R_SYSTEM->OPCCR_b.OPCM))
188 {
189 bsp_clocks_mem_wait_set(CGC_ZERO_WAIT_CYCLES); ///< No MEMWAIT cycles
190 }
191 }
192 return SSP_SUCCESS;
193 }
194
195 #endif
196
197
198
199
200 /** @} (end defgroup BSP_MCU_CLOCKS_S1JA) */
201