1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <acpi/acpi.h>
5 #include <arch/hpet.h>
6 #include <device/pci_ops.h>
7 #include <stdint.h>
8 #include <cpu/intel/model_2065x/model_2065x.h>
9 #include <device/device.h>
10 #include <device/pci.h>
11 #include <device/pci_ids.h>
12 #include "chip.h"
13 #include <commonlib/bsd/helpers.h>
14 #include "ironlake.h"
15 #include <cpu/intel/smm_reloc.h>
16
17 static int bridge_revision_id = -1;
18
bridge_silicon_revision(void)19 int bridge_silicon_revision(void)
20 {
21 if (bridge_revision_id < 0) {
22 uint8_t stepping = cpuid_eax(1) & 0x0f;
23 uint8_t bridge_id = pci_read_config16(pcidev_on_root(0, 0), PCI_DEVICE_ID);
24 bridge_revision_id = (bridge_id & 0xf0) | stepping;
25 }
26 return bridge_revision_id;
27 }
28
29 /*
30 * Reserve everything between A segment and 1MB:
31 *
32 * 0xa0000 - 0xbffff: legacy VGA
33 * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
34 * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
35 */
36
add_fixed_resources(struct device * dev,int index)37 static void add_fixed_resources(struct device *dev, int index)
38 {
39 /* 0xe0000000-0xf0000000 PCIe config.
40 0xfed10000-0xfed14000 MCH
41 0xfed17000-0xfed18000 HECI
42 0xfed18000-0xfed19000 DMI
43 0xfed19000-0xfed1a000 EPBAR
44 0xfed1c000-0xfed20000 RCBA
45 0xfed90000-0xfed94000 IOMMU
46 0xff800000-0xffffffff ROM. */
47
48 mmio_range(dev, index++, HPET_BASE_ADDRESS, 0x00100000);
49 mmio_from_to(dev, index++, 0xa0000, 0xc0000);
50 reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB);
51 }
52
53 #if CONFIG(HAVE_ACPI_TABLES)
northbridge_acpi_name(const struct device * dev)54 static const char *northbridge_acpi_name(const struct device *dev)
55 {
56 if (dev->path.type == DEVICE_PATH_DOMAIN)
57 return "PCI0";
58
59 if (!is_pci_dev_on_bus(dev, 0))
60 return NULL;
61
62 switch (dev->path.pci.devfn) {
63 case PCI_DEVFN(0, 0):
64 return "MCHC";
65 }
66
67 return NULL;
68 }
69 #endif
70
71 struct device_operations ironlake_pci_domain_ops = {
72 .read_resources = pci_domain_read_resources,
73 .set_resources = pci_domain_set_resources,
74 .scan_bus = pci_host_bridge_scan_bus,
75 #if CONFIG(HAVE_ACPI_TABLES)
76 .acpi_name = northbridge_acpi_name,
77 #endif
78 };
79
mc_read_resources(struct device * dev)80 static void mc_read_resources(struct device *dev)
81 {
82 uint32_t tseg_base, tseg_end;
83 uint64_t touud;
84 uint16_t reg16;
85 int index = 3;
86
87 pci_dev_read_resources(dev);
88
89 mmconf_resource(dev, 0x50);
90
91 tseg_base = pci_read_config32(pcidev_on_root(0, 0), TSEG);
92 tseg_end = tseg_base + CONFIG_SMM_TSEG_SIZE;
93 touud = pci_read_config16(pcidev_on_root(0, 0),
94 TOUUD);
95
96 printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base);
97 printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned int)touud);
98
99 /* Report the memory regions */
100 ram_range(dev, index++, 0, 0xa0000);
101 ram_from_to(dev, index++, 1 * MiB, tseg_base);
102
103 mmio_range(dev, index++, tseg_base, CONFIG_SMM_TSEG_SIZE);
104
105 reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC);
106 const int uma_sizes_gtt[16] =
107 { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 };
108 /* Igd memory */
109 const int uma_sizes_igd[16] = {
110 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352, 256, 512
111 };
112 u32 igd_base, gtt_base;
113 int uma_size_igd, uma_size_gtt;
114
115 uma_size_igd = uma_sizes_igd[(reg16 >> 4) & 0xF];
116 uma_size_gtt = uma_sizes_gtt[(reg16 >> 8) & 0xF];
117
118 igd_base =
119 pci_read_config32(pcidev_on_root(0, 0), IGD_BASE);
120 gtt_base =
121 pci_read_config32(pcidev_on_root(0, 0), GTT_BASE);
122 if (gtt_base > tseg_end) {
123 /* Reserve the gap. MMIO doesn't work in this range. Keep
124 it uncacheable, though, for easier MTRR allocation. */
125 mmio_from_to(dev, index++, tseg_end, gtt_base);
126 }
127 mmio_range(dev, index++, gtt_base, uma_size_gtt * MiB);
128 mmio_range(dev, index++, igd_base, uma_size_igd * MiB);
129
130 upper_ram_end(dev, index++, touud * MiB);
131
132 /* This memory is not DMA-capable. */
133 if (touud >= 8192 - 64)
134 bad_ram_range(dev, index++, 0x1fc000000ULL, 0x004000000);
135
136 add_fixed_resources(dev, index);
137 }
138
northbridge_init(struct device * dev)139 static void northbridge_init(struct device *dev)
140 {
141 /* Clear error status bits */
142 dmibar_write32(DMIUESTS, 0xffffffff);
143 dmibar_write32(DMICESTS, 0xffffffff);
144
145 dmibar_setbits32(DMILLTC, 1 << 29);
146
147 dmibar_setbits32(0x1f8, 1 << 16);
148
149 dmibar_setbits32(DMILCTL, 1 << 1 | 1 << 0);
150 }
151
152 /* Disable unused PEG devices based on devicetree before PCI enumeration */
ironlake_init(void * const chip_info)153 static void ironlake_init(void *const chip_info)
154 {
155 u32 deven_mask = UINT32_MAX;
156 const struct device *dev;
157
158 dev = pcidev_on_root(1, 0);
159 if (!dev || !dev->enabled) {
160 printk(BIOS_DEBUG, "Disabling PEG10.\n");
161 deven_mask &= ~DEVEN_PEG10;
162 }
163 dev = pcidev_on_root(2, 0);
164 if (!dev || !dev->enabled) {
165 printk(BIOS_DEBUG, "Disabling IGD.\n");
166 deven_mask &= ~DEVEN_IGD;
167 }
168 const struct device *const d0f0 = pcidev_on_root(0, 0);
169 if (d0f0)
170 pci_update_config32(d0f0, DEVEN, deven_mask, 0);
171 }
172
173 static struct device_operations mc_ops = {
174 .read_resources = mc_read_resources,
175 .set_resources = pci_dev_set_resources,
176 .enable_resources = pci_dev_enable_resources,
177 .init = northbridge_init,
178 .acpi_fill_ssdt = generate_cpu_entries,
179 .ops_pci = &pci_dev_ops_pci,
180 };
181
182 /*
183 * The host bridge PCI device ID can be changed by the firmware. There
184 * is no documentation about it, though. There's 'official' IDs, which
185 * appear in spec updates and Windows drivers, and 'mysterious' IDs,
186 * which Intel doesn't want OSes to know about and thus are not listed.
187 *
188 * The current coreboot code seems to be able to change the device ID
189 * of the host bridge, but it seems to be missing a warm reset so that
190 * the device ID changes. Account for the 'mysterious' device IDs in
191 * the northbridge driver, so that booting an OS has a chance to work.
192 */
193 static const unsigned short pci_device_ids[] = {
194 /* 'Official' DIDs */
195 0x0040, /* Clarkdale */
196 0x0044, /* Arrandale */
197 0x0048, /* Unknown, but it appears in OS drivers and raminit */
198
199 /* Mysterious DIDs, taken from Linux' intel-agp driver */
200 0x0062, /* Arrandale A-? */
201 0x0069, /* Clarkdale K-0 */
202 0x006a, /* Arrandale K-0 */
203 0
204 };
205
206 static const struct pci_driver mc_driver_ilk __pci_driver = {
207 .ops = &mc_ops,
208 .vendor = PCI_VID_INTEL,
209 .devices = pci_device_ids,
210 };
211
212 struct device_operations ironlake_cpu_bus_ops = {
213 .read_resources = noop_read_resources,
214 .set_resources = noop_set_resources,
215 .init = mp_cpu_bus_init,
216 };
217
218 struct chip_operations northbridge_intel_ironlake_ops = {
219 .name = "Intel Ironlake integrated Northbridge",
220 .init = ironlake_init,
221 };
222