1 /**
2 * \file
3 *
4 * \brief SAMV71-XULTRA board init.
5 *
6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43 /*
44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
45 */
46
47 #include "compiler.h"
48 #include "board.h"
49 #include "conf_board.h"
50 #include "ioport.h"
51 #include "pio.h"
52 #ifdef CONF_BOARD_CONFIG_MPU_AT_INIT
53 #include "mpu.h"
54 #endif
55
56 /**
57 * \brief Set peripheral mode for IOPORT pins.
58 * It will configure port mode and disable pin mode (but enable peripheral).
59 * \param port IOPORT port to configure
60 * \param masks IOPORT pin masks to configure
61 * \param mode Mode masks to configure for the specified pin (\ref ioport_modes)
62 */
63 #define ioport_set_port_peripheral_mode(port, masks, mode) \
64 do {\
65 ioport_set_port_mode(port, masks, mode);\
66 ioport_disable_port(port, masks);\
67 } while (0)
68
69 /**
70 * \brief Set peripheral mode for one single IOPORT pin.
71 * It will configure port mode and disable pin mode (but enable peripheral).
72 * \param pin IOPORT pin to configure
73 * \param mode Mode masks to configure for the specified pin (\ref ioport_modes)
74 */
75 #define ioport_set_pin_peripheral_mode(pin, mode) \
76 do {\
77 ioport_set_pin_mode(pin, mode);\
78 ioport_disable_pin(pin);\
79 } while (0)
80
81 /**
82 * \brief Set input mode for one single IOPORT pin.
83 * It will configure port mode and disable pin mode (but enable peripheral).
84 * \param pin IOPORT pin to configure
85 * \param mode Mode masks to configure for the specified pin (\ref ioport_modes)
86 * \param sense Sense for interrupt detection (\ref ioport_sense)
87 */
88 #define ioport_set_pin_input_mode(pin, mode, sense) \
89 do {\
90 ioport_set_pin_dir(pin, IOPORT_DIR_INPUT);\
91 ioport_set_pin_mode(pin, mode);\
92 ioport_set_pin_sense_mode(pin, sense);\
93 } while (0)
94
95
96
97 /**
98 * Default memory map
99 * Address range Memory region Memory type Shareability Cache policy
100 * 0x00000000- 0x1FFFFFFF Code Normal Non-shareable WT
101 * 0x20000000- 0x3FFFFFFF SRAM Normal Non-shareable WBWA
102 * 0x40000000- 0x5FFFFFFF Peripheral Device Non-shareable -
103 * 0x60000000- 0x7FFFFFFF RAM Normal Non-shareable WBWA
104 * 0x80000000- 0x9FFFFFFF RAM Normal Non-shareable WT
105 * 0xA0000000- 0xBFFFFFFF Device Device Shareable
106 * 0xC0000000- 0xDFFFFFFF Device Device Non Shareable
107 * 0xE0000000- 0xFFFFFFFF System - -
108 */
109
110 #ifdef CONF_BOARD_CONFIG_MPU_AT_INIT
111 /**
112 * \brief Set up a memory region.
113 */
_setup_memory_region(void)114 static void _setup_memory_region( void )
115 {
116
117 uint32_t dw_region_base_addr;
118 uint32_t dw_region_attr;
119
120 __DMB();
121
122 /**
123 * ITCM memory region --- Normal
124 * START_Addr:- 0x00000000UL
125 * END_Addr:- 0x00400000UL
126 */
127 dw_region_base_addr =
128 ITCM_START_ADDRESS |
129 MPU_REGION_VALID |
130 MPU_DEFAULT_ITCM_REGION;
131
132 dw_region_attr =
133 MPU_AP_PRIVILEGED_READ_WRITE |
134 mpu_cal_mpu_region_size(ITCM_END_ADDRESS - ITCM_START_ADDRESS) |
135 MPU_REGION_ENABLE;
136
137 mpu_set_region( dw_region_base_addr, dw_region_attr);
138
139 /**
140 * Internal flash memory region --- Normal read-only
141 * (update to Strongly ordered in write accesses)
142 * START_Addr:- 0x00400000UL
143 * END_Addr:- 0x00600000UL
144 */
145
146 dw_region_base_addr =
147 IFLASH_START_ADDRESS |
148 MPU_REGION_VALID |
149 MPU_DEFAULT_IFLASH_REGION;
150
151 dw_region_attr =
152 MPU_AP_READONLY |
153 INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) |
154 mpu_cal_mpu_region_size(IFLASH_END_ADDRESS - IFLASH_START_ADDRESS) |
155 MPU_REGION_ENABLE;
156
157 mpu_set_region( dw_region_base_addr, dw_region_attr);
158
159 /**
160 * DTCM memory region --- Normal
161 * START_Addr:- 0x20000000L
162 * END_Addr:- 0x20400000UL
163 */
164
165 /* DTCM memory region */
166 dw_region_base_addr =
167 DTCM_START_ADDRESS |
168 MPU_REGION_VALID |
169 MPU_DEFAULT_DTCM_REGION;
170
171 dw_region_attr =
172 MPU_AP_PRIVILEGED_READ_WRITE |
173 mpu_cal_mpu_region_size(DTCM_END_ADDRESS - DTCM_START_ADDRESS) |
174 MPU_REGION_ENABLE;
175
176 mpu_set_region( dw_region_base_addr, dw_region_attr);
177
178 /**
179 * SRAM Cacheable memory region --- Normal
180 * START_Addr:- 0x20400000UL
181 * END_Addr:- 0x2043FFFFUL
182 */
183 /* SRAM memory region */
184 dw_region_base_addr =
185 SRAM_FIRST_START_ADDRESS |
186 MPU_REGION_VALID |
187 MPU_DEFAULT_SRAM_REGION_1;
188
189 dw_region_attr =
190 MPU_AP_FULL_ACCESS |
191 INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) |
192 mpu_cal_mpu_region_size(SRAM_FIRST_END_ADDRESS - SRAM_FIRST_START_ADDRESS)
193 | MPU_REGION_ENABLE;
194
195 mpu_set_region( dw_region_base_addr, dw_region_attr);
196
197
198 /**
199 * Internal SRAM second partition memory region --- Normal
200 * START_Addr:- 0x20440000UL
201 * END_Addr:- 0x2045FFFFUL
202 */
203 /* SRAM memory region */
204 dw_region_base_addr =
205 SRAM_SECOND_START_ADDRESS |
206 MPU_REGION_VALID |
207 MPU_DEFAULT_SRAM_REGION_2;
208
209 dw_region_attr =
210 MPU_AP_FULL_ACCESS |
211 INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) |
212 mpu_cal_mpu_region_size(SRAM_SECOND_END_ADDRESS - SRAM_SECOND_START_ADDRESS) |
213 MPU_REGION_ENABLE;
214
215 mpu_set_region( dw_region_base_addr, dw_region_attr);
216
217 #ifdef MPU_HAS_NOCACHE_REGION
218 dw_region_base_addr =
219 SRAM_NOCACHE_START_ADDRESS |
220 MPU_REGION_VALID |
221 MPU_NOCACHE_SRAM_REGION;
222
223 dw_region_attr =
224 MPU_AP_FULL_ACCESS |
225 INNER_OUTER_NORMAL_NOCACHE_TYPE( SHAREABLE ) |
226 mpu_cal_mpu_region_size(NOCACHE_SRAM_REGION_SIZE) |
227 MPU_REGION_ENABLE;
228
229 mpu_set_region( dw_region_base_addr, dw_region_attr);
230 #endif
231
232 /**
233 * Peripheral memory region --- DEVICE Shareable
234 * START_Addr:- 0x40000000UL
235 * END_Addr:- 0x5FFFFFFFUL
236 */
237 dw_region_base_addr =
238 PERIPHERALS_START_ADDRESS |
239 MPU_REGION_VALID |
240 MPU_PERIPHERALS_REGION;
241
242 dw_region_attr = MPU_AP_FULL_ACCESS |
243 MPU_REGION_EXECUTE_NEVER |
244 SHAREABLE_DEVICE_TYPE |
245 mpu_cal_mpu_region_size(PERIPHERALS_END_ADDRESS - PERIPHERALS_START_ADDRESS)
246 |MPU_REGION_ENABLE;
247
248 mpu_set_region( dw_region_base_addr, dw_region_attr);
249
250
251 /**
252 * External EBI memory memory region --- Strongly Ordered
253 * START_Addr:- 0x60000000UL
254 * END_Addr:- 0x6FFFFFFFUL
255 */
256 dw_region_base_addr =
257 EXT_EBI_START_ADDRESS |
258 MPU_REGION_VALID |
259 MPU_EXT_EBI_REGION;
260
261 dw_region_attr =
262 MPU_AP_FULL_ACCESS |
263 /* External memory Must be defined with 'Device' or 'Strongly Ordered' attribute for write accesses (AXI) */
264 STRONGLY_ORDERED_SHAREABLE_TYPE |
265 mpu_cal_mpu_region_size(EXT_EBI_END_ADDRESS - EXT_EBI_START_ADDRESS) |
266 MPU_REGION_ENABLE;
267
268 mpu_set_region( dw_region_base_addr, dw_region_attr);
269
270 /**
271 * SDRAM cacheable memory region --- Normal
272 * START_Addr:- 0x70000000UL
273 * END_Addr:- 0x7FFFFFFFUL
274 */
275 dw_region_base_addr =
276 SDRAM_START_ADDRESS |
277 MPU_REGION_VALID |
278 MPU_DEFAULT_SDRAM_REGION;
279
280 dw_region_attr =
281 MPU_AP_FULL_ACCESS |
282 INNER_NORMAL_WB_RWA_TYPE( SHAREABLE ) |
283 mpu_cal_mpu_region_size(SDRAM_END_ADDRESS - SDRAM_START_ADDRESS) |
284 MPU_REGION_ENABLE;
285
286 mpu_set_region( dw_region_base_addr, dw_region_attr);
287
288 /**
289 * QSPI memory region --- Strongly ordered
290 * START_Addr:- 0x80000000UL
291 * END_Addr:- 0x9FFFFFFFUL
292 */
293 dw_region_base_addr =
294 QSPI_START_ADDRESS |
295 MPU_REGION_VALID |
296 MPU_QSPIMEM_REGION;
297
298 dw_region_attr =
299 MPU_AP_FULL_ACCESS |
300 STRONGLY_ORDERED_SHAREABLE_TYPE |
301 mpu_cal_mpu_region_size(QSPI_END_ADDRESS - QSPI_START_ADDRESS) |
302 MPU_REGION_ENABLE;
303
304 mpu_set_region( dw_region_base_addr, dw_region_attr);
305
306
307 /**
308 * USB RAM Memory region --- Device
309 * START_Addr:- 0xA0100000UL
310 * END_Addr:- 0xA01FFFFFUL
311 */
312 dw_region_base_addr =
313 USBHSRAM_START_ADDRESS |
314 MPU_REGION_VALID |
315 MPU_USBHSRAM_REGION;
316
317 dw_region_attr =
318 MPU_AP_FULL_ACCESS |
319 MPU_REGION_EXECUTE_NEVER |
320 SHAREABLE_DEVICE_TYPE |
321 mpu_cal_mpu_region_size(USBHSRAM_END_ADDRESS - USBHSRAM_START_ADDRESS) |
322 MPU_REGION_ENABLE;
323
324 mpu_set_region( dw_region_base_addr, dw_region_attr);
325
326
327 /* Enable the memory management fault , Bus Fault, Usage Fault exception */
328 SCB->SHCSR |= (SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk
329 | SCB_SHCSR_USGFAULTENA_Msk);
330
331 /* Enable the MPU region */
332 mpu_enable( MPU_ENABLE | MPU_PRIVDEFENA);
333
334 __DSB();
335 __ISB();
336 }
337 #endif
338
board_init(void)339 void board_init(void)
340 {
341 #ifndef CONF_BOARD_KEEP_WATCHDOG_AT_INIT
342 /* Disable the watchdog */
343 WDT->WDT_MR = WDT_MR_WDDIS;
344 #endif
345
346 /* Initialize IOPORTs */
347 ioport_init();
348
349 /* Configure the pins connected to LED as output and set their
350 * default initial state to high (LED off).
351 */
352 ioport_set_pin_dir(LED0_GPIO, IOPORT_DIR_OUTPUT);
353 ioport_set_pin_level(LED0_GPIO, LED0_INACTIVE_LEVEL);
354 ioport_set_pin_dir(LED1_GPIO, IOPORT_DIR_OUTPUT);
355 ioport_set_pin_level(LED1_GPIO, LED0_INACTIVE_LEVEL);
356
357 /* Configure Push Button pins */
358 ioport_set_pin_input_mode(GPIO_PUSH_BUTTON_1, GPIO_PUSH_BUTTON_1_FLAGS,
359 GPIO_PUSH_BUTTON_1_SENSE);
360
361 #ifdef CONF_BOARD_UART_CONSOLE
362 /* Configure UART pins */
363 ioport_set_pin_peripheral_mode(USART1_RXD_GPIO, USART1_RXD_FLAGS);
364 MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4;
365 ioport_set_pin_peripheral_mode(USART1_TXD_GPIO, USART1_TXD_FLAGS);
366 #endif
367
368 #ifdef CONF_BOARD_TWIHS0
369 ioport_set_pin_peripheral_mode(TWIHS0_DATA_GPIO, TWIHS0_DATA_FLAGS);
370 ioport_set_pin_peripheral_mode(TWIHS0_CLK_GPIO, TWIHS0_CLK_FLAGS);
371 #endif
372
373
374 #ifdef CONF_BOARD_CAN0
375 /* Configure the CAN0 TX and RX pins. */
376 ioport_set_pin_peripheral_mode(PIN_CAN0_RX_IDX, PIN_CAN0_RX_FLAGS);
377 ioport_set_pin_peripheral_mode(PIN_CAN0_TX_IDX, PIN_CAN0_TX_FLAGS);
378 /* Configure the transiver0 RS & EN pins. */
379 ioport_set_pin_dir(PIN_CAN0_TR_RS_IDX, IOPORT_DIR_OUTPUT);
380 ioport_set_pin_dir(PIN_CAN0_TR_EN_IDX, IOPORT_DIR_OUTPUT);
381 #endif
382
383 #ifdef CONF_BOARD_CAN1
384 /* Configure the CAN1 TX and RX pin. */
385 ioport_set_pin_peripheral_mode(PIN_CAN1_RX_IDX, PIN_CAN1_RX_FLAGS);
386 ioport_set_pin_peripheral_mode(PIN_CAN1_TX_IDX, PIN_CAN1_TX_FLAGS);
387
388 #endif
389
390
391 #ifdef CONF_BOARD_SPI
392 ioport_set_pin_peripheral_mode(SPI0_MISO_GPIO, SPI0_MISO_FLAGS);
393 ioport_set_pin_peripheral_mode(SPI0_MOSI_GPIO, SPI0_MOSI_FLAGS);
394 ioport_set_pin_peripheral_mode(SPI0_NPCS0_GPIO, SPI0_NPCS0_FLAGS);
395 ioport_set_pin_peripheral_mode(SPI0_SPCK_GPIO, SPI0_SPCK_FLAGS);
396 #endif
397
398 #ifdef CONF_BOARD_QSPI
399 ioport_set_pin_peripheral_mode(QSPI_QSCK_GPIO, QSPI_QSCK_FLAGS);
400 ioport_set_pin_peripheral_mode(QSPI_QCS_GPIO, QSPI_QCS_FLAGS);
401 ioport_set_pin_peripheral_mode(QSPI_QIO0_GPIO, QSPI_QIO0_FLAGS);
402 ioport_set_pin_peripheral_mode(QSPI_QIO1_GPIO, QSPI_QIO1_FLAGS);
403 ioport_set_pin_peripheral_mode(QSPI_QIO2_GPIO, QSPI_QIO2_FLAGS);
404 ioport_set_pin_peripheral_mode(QSPI_QIO3_GPIO, QSPI_QIO3_FLAGS);
405 #endif
406
407 #ifdef CONF_BOARD_PWM_LED0
408 /* Configure PWM LED0 pin */
409 ioport_set_pin_peripheral_mode(PIN_PWM_LED0_GPIO, PIN_PWM_LED0_FLAGS);
410 #endif
411
412 #ifdef CONF_BOARD_PWM_LED1
413 /* Configure PWM LED1 pin */
414 ioport_set_pin_peripheral_mode(PIN_PWM_LED1_GPIO, PIN_PWM_LED1_FLAGS);
415 #endif
416
417
418 #ifdef CONF_BOARD_USART_RXD
419 /* Configure USART RXD pin */
420 ioport_set_pin_peripheral_mode(USART0_RXD_GPIO, USART0_RXD_FLAGS);
421 #endif
422
423 #ifdef CONF_BOARD_USART_TXD
424 /* Configure USART TXD pin */
425 ioport_set_pin_peripheral_mode(USART0_TXD_GPIO, USART0_TXD_FLAGS);
426 #endif
427
428 #ifdef CONF_BOARD_USART_SCK
429 /* Configure USART synchronous communication SCK pin */
430 ioport_set_pin_peripheral_mode(PIN_USART0_SCK_IDX,PIN_USART0_SCK_FLAGS);
431 #endif
432
433 #ifdef CONF_BOARD_USART_CTS
434 /* Configure USART synchronous communication CTS pin */
435 ioport_set_pin_peripheral_mode(PIN_USART0_CTS_IDX,PIN_USART0_CTS_FLAGS);
436 #endif
437
438 #ifdef CONF_BOARD_USART_RTS
439 /* Configure USART RTS pin */
440 ioport_set_pin_peripheral_mode(PIN_USART0_RTS_IDX, PIN_USART0_RTS_FLAGS);
441 #endif
442
443 #ifdef CONF_BOARD_SD_MMC_HSMCI
444 /* Configure HSMCI pins */
445 ioport_set_pin_peripheral_mode(PIN_HSMCI_MCCDA_GPIO, PIN_HSMCI_MCCDA_FLAGS);
446 ioport_set_pin_peripheral_mode(PIN_HSMCI_MCCK_GPIO, PIN_HSMCI_MCCK_FLAGS);
447 ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA0_GPIO, PIN_HSMCI_MCDA0_FLAGS);
448 ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA1_GPIO, PIN_HSMCI_MCDA1_FLAGS);
449 ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA2_GPIO, PIN_HSMCI_MCDA2_FLAGS);
450 ioport_set_pin_peripheral_mode(PIN_HSMCI_MCDA3_GPIO, PIN_HSMCI_MCDA3_FLAGS);
451 ioport_set_pin_peripheral_mode(SD_MMC_0_CD_GPIO, SD_MMC_0_CD_FLAGS);
452 #endif
453
454 #ifdef CONF_BOARD_ILI9488
455 /**LCD pin configure on EBI*/
456 pio_configure(PIN_EBI_RESET_PIO, PIN_EBI_RESET_TYPE, PIN_EBI_RESET_MASK, PIN_EBI_RESET_ATTRI);
457 pio_configure(PIN_EBI_CDS_PIO, PIN_EBI_CDS_TYPE, PIN_EBI_CDS_MASK, PIN_EBI_CDS_ATTRI);
458 pio_configure(PIN_EBI_DATAL_PIO, PIN_EBI_DATAL_TYPE, PIN_EBI_DATAL_MASK, PIN_EBI_DATAL_ATTRI);
459 pio_configure(PIN_EBI_DATAH_0_PIO, PIN_EBI_DATAH_0_TYPE, PIN_EBI_DATAH_0_MASK, PIN_EBI_DATAH_0_ATTRI);
460 pio_configure(PIN_EBI_DATAH_1_PIO, PIN_EBI_DATAH_1_TYPE, PIN_EBI_DATAH_1_MASK, PIN_EBI_DATAH_1_ATTRI);
461 pio_configure(PIN_EBI_NWE_PIO, PIN_EBI_NWE_TYPE, PIN_EBI_NWE_MASK, PIN_EBI_NWE_ATTRI);
462 pio_configure(PIN_EBI_NRD_PIO, PIN_EBI_NRD_TYPE, PIN_EBI_NRD_MASK, PIN_EBI_NRD_ATTRI);
463 pio_configure(PIN_EBI_CS_PIO, PIN_EBI_CS_TYPE, PIN_EBI_CS_MASK, PIN_EBI_CS_ATTRI);
464 pio_configure(PIN_EBI_BACKLIGHT_PIO, PIN_EBI_BACKLIGHT_TYPE, PIN_EBI_BACKLIGHT_MASK, PIN_EBI_BACKLIGHT_ATTRI);
465 pio_set(PIN_EBI_BACKLIGHT_PIO, PIN_EBI_BACKLIGHT_MASK);
466 #endif
467
468 #if (defined CONF_BOARD_USB_PORT)
469 # if defined(CONF_BOARD_USB_VBUS_DETECT)
470 ioport_set_pin_dir(USB_VBUS_PIN, IOPORT_DIR_INPUT);
471 # endif
472 # if defined(CONF_BOARD_USB_ID_DETECT)
473 ioport_set_pin_dir(USB_ID_PIN, IOPORT_DIR_INPUT);
474 # endif
475 #endif
476
477 #ifdef CONF_BOARD_SDRAMC
478 pio_configure_pin(SDRAM_BA0_PIO, SDRAM_BA0_FLAGS);
479 pio_configure_pin(SDRAM_SDCK_PIO, SDRAM_SDCK_FLAGS);
480 pio_configure_pin(SDRAM_SDCKE_PIO, SDRAM_SDCKE_FLAGS);
481 pio_configure_pin(SDRAM_SDCS_PIO, SDRAM_SDCS_FLAGS);
482 pio_configure_pin(SDRAM_RAS_PIO, SDRAM_RAS_FLAGS);
483 pio_configure_pin(SDRAM_CAS_PIO, SDRAM_CAS_FLAGS);
484 pio_configure_pin(SDRAM_SDWE_PIO, SDRAM_SDWE_FLAGS);
485 pio_configure_pin(SDRAM_NBS0_PIO, SDRAM_NBS0_FLAGS);
486 pio_configure_pin(SDRAM_NBS1_PIO, SDRAM_NBS1_FLAGS);
487 pio_configure_pin(SDRAM_A2_PIO, SDRAM_A_FLAGS);
488 pio_configure_pin(SDRAM_A3_PIO, SDRAM_A_FLAGS);
489 pio_configure_pin(SDRAM_A4_PIO, SDRAM_A_FLAGS);
490 pio_configure_pin(SDRAM_A5_PIO, SDRAM_A_FLAGS);
491 pio_configure_pin(SDRAM_A6_PIO, SDRAM_A_FLAGS);
492 pio_configure_pin(SDRAM_A7_PIO, SDRAM_A_FLAGS);
493 pio_configure_pin(SDRAM_A8_PIO, SDRAM_A_FLAGS);
494 pio_configure_pin(SDRAM_A9_PIO, SDRAM_A_FLAGS);
495 pio_configure_pin(SDRAM_A10_PIO, SDRAM_A_FLAGS);
496 pio_configure_pin(SDRAM_A11_PIO, SDRAM_A_FLAGS);
497 pio_configure_pin(SDRAM_SDA10_PIO, SDRAM_SDA10_FLAGS);
498 pio_configure_pin(SDRAM_D0_PIO, SDRAM_D_FLAGS);
499 pio_configure_pin(SDRAM_D1_PIO, SDRAM_D_FLAGS);
500 pio_configure_pin(SDRAM_D2_PIO, SDRAM_D_FLAGS);
501 pio_configure_pin(SDRAM_D3_PIO, SDRAM_D_FLAGS);
502 pio_configure_pin(SDRAM_D4_PIO, SDRAM_D_FLAGS);
503 pio_configure_pin(SDRAM_D5_PIO, SDRAM_D_FLAGS);
504 pio_configure_pin(SDRAM_D6_PIO, SDRAM_D_FLAGS);
505 pio_configure_pin(SDRAM_D7_PIO, SDRAM_D_FLAGS);
506 pio_configure_pin(SDRAM_D8_PIO, SDRAM_D_FLAGS);
507 pio_configure_pin(SDRAM_D9_PIO, SDRAM_D_FLAGS);
508 pio_configure_pin(SDRAM_D10_PIO, SDRAM_D_FLAGS);
509 pio_configure_pin(SDRAM_D11_PIO, SDRAM_D_FLAGS);
510 pio_configure_pin(SDRAM_D12_PIO, SDRAM_D_FLAGS);
511 pio_configure_pin(SDRAM_D13_PIO, SDRAM_D_FLAGS);
512 pio_configure_pin(SDRAM_D14_PIO, SDRAM_D_FLAGS);
513 pio_configure_pin(SDRAM_D15_PIO, SDRAM_D_FLAGS);
514
515 MATRIX->CCFG_SMCNFCS = CCFG_SMCNFCS_SDRAMEN;
516 #endif
517
518 #ifdef CONF_BOARD_CONFIG_MPU_AT_INIT
519 _setup_memory_region();
520 #endif
521 }
522