1 #ifndef __BDK_CSRS_SMI_H__
2 #define __BDK_CSRS_SMI_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***************
6 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights
7 * reserved.
8 *
9 *
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15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided
20 * with the distribution.
21
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23 * its contributors may be used to endorse or promote products
24 * derived from this software without specific prior written
25 * permission.
26
27 * This Software, including technical data, may be subject to U.S. export control
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29 * regulations, and may be subject to export or import regulations in other
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31
32 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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41 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
42 ***********************license end**************************************/
43
44
45 /**
46 * @file
47 *
48 * Configuration and status register (CSR) address and type definitions for
49 * Cavium SMI.
50 *
51 * This file is auto generated. Do not edit.
52 *
53 */
54
55 /**
56 * Enumeration smi_bar_e
57 *
58 * SMI Base Address Register Enumeration
59 * Enumerates the base address registers.
60 */
61 #define BDK_SMI_BAR_E_SMI_PF_BAR0_CN8 (0x87e005000000ll)
62 #define BDK_SMI_BAR_E_SMI_PF_BAR0_CN8_SIZE 0x800000ull
63 #define BDK_SMI_BAR_E_SMI_PF_BAR0_CN9 (0x87e005000000ll)
64 #define BDK_SMI_BAR_E_SMI_PF_BAR0_CN9_SIZE 0x100000ull
65
66 /**
67 * Register (RSL) smi_#_clk
68 *
69 * SMI Clock Control Register
70 * This register determines the SMI timing characteristics.
71 * If software wants to change SMI CLK timing parameters ([SAMPLE]/[SAMPLE_HI]), software
72 * must delay the SMI_()_CLK CSR write by at least 512 coprocessor-clock cycles after the
73 * previous SMI operation is finished.
74 */
75 union bdk_smi_x_clk
76 {
77 uint64_t u;
78 struct bdk_smi_x_clk_s
79 {
80 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
81 uint64_t reserved_25_63 : 39;
82 uint64_t mode : 1; /**< [ 24: 24](R/W) IEEE operating mode; 0 = Clause 22 compliant, 1 = Clause 45 compliant. */
83 uint64_t reserved_21_23 : 3;
84 uint64_t sample_hi : 5; /**< [ 20: 16](R/W) Sample (extended bits). Specifies in coprocessor clock cycles when to sample read data. */
85 uint64_t sample_mode : 1; /**< [ 15: 15](R/W) Read data sampling mode.
86 According to the 802.3 specification, on read operations, the STA transitions SMIn_MDC and
87 the PHY drives SMIn_MDIO with some delay relative to that edge. This is Edge1.
88 The STA then samples SMIn_MDIO on the next rising edge of SMIn_MDC. This is Edge2. The
89 read data can be sampled relative to either edge.
90 0 = Sample time is relative to Edge2.
91 1 = Sample time is relative to Edge1. */
92 uint64_t reserved_14 : 1;
93 uint64_t clk_idle : 1; /**< [ 13: 13](R/W) SMIn_MDC toggle. When set, this bit causes SMIn_MDC not to toggle on idle cycles. */
94 uint64_t preamble : 1; /**< [ 12: 12](R/W) Preamble. When this bit is set, the 32-bit preamble is sent first on SMI transactions.
95 This field must be set to 1 when [MODE] = 1 in order for the receiving PHY to correctly
96 frame the transaction. */
97 uint64_t sample : 4; /**< [ 11: 8](R/W) Sample read data. Specifies the number of coprocessor clock cycles after the rising edge
98 of SMIn_MDC to wait before sampling read data.
99
100 _ ([SAMPLE_HI],[SAMPLE]) \> 1
101
102 _ ([SAMPLE_HI],[SAMPLE]) + 3 \<= 2 * [PHASE] */
103 uint64_t phase : 8; /**< [ 7: 0](R/W) MDC clock phase. Specifies the number of coprocessor clock cycles that make up an SMIn_MDC
104 phase.
105
106 _ [PHASE] \> 2 */
107 #else /* Word 0 - Little Endian */
108 uint64_t phase : 8; /**< [ 7: 0](R/W) MDC clock phase. Specifies the number of coprocessor clock cycles that make up an SMIn_MDC
109 phase.
110
111 _ [PHASE] \> 2 */
112 uint64_t sample : 4; /**< [ 11: 8](R/W) Sample read data. Specifies the number of coprocessor clock cycles after the rising edge
113 of SMIn_MDC to wait before sampling read data.
114
115 _ ([SAMPLE_HI],[SAMPLE]) \> 1
116
117 _ ([SAMPLE_HI],[SAMPLE]) + 3 \<= 2 * [PHASE] */
118 uint64_t preamble : 1; /**< [ 12: 12](R/W) Preamble. When this bit is set, the 32-bit preamble is sent first on SMI transactions.
119 This field must be set to 1 when [MODE] = 1 in order for the receiving PHY to correctly
120 frame the transaction. */
121 uint64_t clk_idle : 1; /**< [ 13: 13](R/W) SMIn_MDC toggle. When set, this bit causes SMIn_MDC not to toggle on idle cycles. */
122 uint64_t reserved_14 : 1;
123 uint64_t sample_mode : 1; /**< [ 15: 15](R/W) Read data sampling mode.
124 According to the 802.3 specification, on read operations, the STA transitions SMIn_MDC and
125 the PHY drives SMIn_MDIO with some delay relative to that edge. This is Edge1.
126 The STA then samples SMIn_MDIO on the next rising edge of SMIn_MDC. This is Edge2. The
127 read data can be sampled relative to either edge.
128 0 = Sample time is relative to Edge2.
129 1 = Sample time is relative to Edge1. */
130 uint64_t sample_hi : 5; /**< [ 20: 16](R/W) Sample (extended bits). Specifies in coprocessor clock cycles when to sample read data. */
131 uint64_t reserved_21_23 : 3;
132 uint64_t mode : 1; /**< [ 24: 24](R/W) IEEE operating mode; 0 = Clause 22 compliant, 1 = Clause 45 compliant. */
133 uint64_t reserved_25_63 : 39;
134 #endif /* Word 0 - End */
135 } s;
136 /* struct bdk_smi_x_clk_s cn8; */
137 struct bdk_smi_x_clk_cn9
138 {
139 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
140 uint64_t reserved_25_63 : 39;
141 uint64_t mode : 1; /**< [ 24: 24](R/W) IEEE operating mode; 0 = Clause 22 compliant, 1 = Clause 45 compliant. */
142 uint64_t reserved_21_23 : 3;
143 uint64_t sample_hi : 5; /**< [ 20: 16](R/W) Sample (extended bits). Specifies in coprocessor clock cycles when to sample read data. */
144 uint64_t sample_mode : 1; /**< [ 15: 15](R/W) Read data sampling mode.
145 According to the 802.3 specification, on read operations, the STA transitions SMIn_MDC and
146 the PHY drives SMIn_MDIO with some delay relative to that edge. This is Edge1.
147 The STA then samples SMIn_MDIO on the next rising edge of SMIn_MDC. This is Edge2. The
148 read data can be sampled relative to either edge.
149 0 = Sample time is relative to Edge2.
150 1 = Sample time is relative to Edge1. */
151 uint64_t reserved_14 : 1;
152 uint64_t clk_idle : 1; /**< [ 13: 13](R/W) SMIn_MDC toggle. When set, this bit causes SMIn_MDC not to toggle on idle cycles. */
153 uint64_t preamble : 1; /**< [ 12: 12](R/W) Preamble. When this bit is set, the 32-bit preamble is sent first on SMI transactions.
154 This field must be set to 1 when [MODE] = 1 in order for the receiving PHY to correctly
155 frame the transaction. */
156 uint64_t sample : 4; /**< [ 11: 8](R/W) Sample read data. Specifies the number of coprocessor clock cycles after the rising edge
157 of SMIn_MDC to wait before sampling read data.
158
159 _ ([SAMPLE_HI],[SAMPLE]) \> 1
160
161 _ ([SAMPLE_HI],[SAMPLE]) + 3 \<= 2 * [PHASE] */
162 uint64_t phase : 8; /**< [ 7: 0](R/W) MDC clock phase. Specifies the number of coprocessor clock cycles that make up an SMIn_MDC
163 phase.
164
165 _ [PHASE] \> 2
166
167 Internal:
168 FIXME number of 100MHz clocks or coproc clocks based on CSR that defaults to 100MHz. */
169 #else /* Word 0 - Little Endian */
170 uint64_t phase : 8; /**< [ 7: 0](R/W) MDC clock phase. Specifies the number of coprocessor clock cycles that make up an SMIn_MDC
171 phase.
172
173 _ [PHASE] \> 2
174
175 Internal:
176 FIXME number of 100MHz clocks or coproc clocks based on CSR that defaults to 100MHz. */
177 uint64_t sample : 4; /**< [ 11: 8](R/W) Sample read data. Specifies the number of coprocessor clock cycles after the rising edge
178 of SMIn_MDC to wait before sampling read data.
179
180 _ ([SAMPLE_HI],[SAMPLE]) \> 1
181
182 _ ([SAMPLE_HI],[SAMPLE]) + 3 \<= 2 * [PHASE] */
183 uint64_t preamble : 1; /**< [ 12: 12](R/W) Preamble. When this bit is set, the 32-bit preamble is sent first on SMI transactions.
184 This field must be set to 1 when [MODE] = 1 in order for the receiving PHY to correctly
185 frame the transaction. */
186 uint64_t clk_idle : 1; /**< [ 13: 13](R/W) SMIn_MDC toggle. When set, this bit causes SMIn_MDC not to toggle on idle cycles. */
187 uint64_t reserved_14 : 1;
188 uint64_t sample_mode : 1; /**< [ 15: 15](R/W) Read data sampling mode.
189 According to the 802.3 specification, on read operations, the STA transitions SMIn_MDC and
190 the PHY drives SMIn_MDIO with some delay relative to that edge. This is Edge1.
191 The STA then samples SMIn_MDIO on the next rising edge of SMIn_MDC. This is Edge2. The
192 read data can be sampled relative to either edge.
193 0 = Sample time is relative to Edge2.
194 1 = Sample time is relative to Edge1. */
195 uint64_t sample_hi : 5; /**< [ 20: 16](R/W) Sample (extended bits). Specifies in coprocessor clock cycles when to sample read data. */
196 uint64_t reserved_21_23 : 3;
197 uint64_t mode : 1; /**< [ 24: 24](R/W) IEEE operating mode; 0 = Clause 22 compliant, 1 = Clause 45 compliant. */
198 uint64_t reserved_25_63 : 39;
199 #endif /* Word 0 - End */
200 } cn9;
201 };
202 typedef union bdk_smi_x_clk bdk_smi_x_clk_t;
203
204 static inline uint64_t BDK_SMI_X_CLK(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SMI_X_CLK(unsigned long a)205 static inline uint64_t BDK_SMI_X_CLK(unsigned long a)
206 {
207 if (a<=1)
208 return 0x87e005003818ll + 0x80ll * ((a) & 0x1);
209 __bdk_csr_fatal("SMI_X_CLK", 1, a, 0, 0, 0);
210 }
211
212 #define typedef_BDK_SMI_X_CLK(a) bdk_smi_x_clk_t
213 #define bustype_BDK_SMI_X_CLK(a) BDK_CSR_TYPE_RSL
214 #define basename_BDK_SMI_X_CLK(a) "SMI_X_CLK"
215 #define device_bar_BDK_SMI_X_CLK(a) 0x0 /* PF_BAR0 */
216 #define busnum_BDK_SMI_X_CLK(a) (a)
217 #define arguments_BDK_SMI_X_CLK(a) (a),-1,-1,-1
218
219 /**
220 * Register (RSL) smi_#_clken
221 *
222 * SMI Clock Enable Register
223 * This register is to force conditional clock enable.
224 */
225 union bdk_smi_x_clken
226 {
227 uint64_t u;
228 struct bdk_smi_x_clken_s
229 {
230 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
231 uint64_t reserved_1_63 : 63;
232 uint64_t clken : 1; /**< [ 0: 0](R/W) Force the conditional clocking within SMI to be always on. For diagnostic use only. */
233 #else /* Word 0 - Little Endian */
234 uint64_t clken : 1; /**< [ 0: 0](R/W) Force the conditional clocking within SMI to be always on. For diagnostic use only. */
235 uint64_t reserved_1_63 : 63;
236 #endif /* Word 0 - End */
237 } s;
238 /* struct bdk_smi_x_clken_s cn; */
239 };
240 typedef union bdk_smi_x_clken bdk_smi_x_clken_t;
241
242 static inline uint64_t BDK_SMI_X_CLKEN(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SMI_X_CLKEN(unsigned long a)243 static inline uint64_t BDK_SMI_X_CLKEN(unsigned long a)
244 {
245 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=1))
246 return 0x87e005003830ll + 0x80ll * ((a) & 0x1);
247 __bdk_csr_fatal("SMI_X_CLKEN", 1, a, 0, 0, 0);
248 }
249
250 #define typedef_BDK_SMI_X_CLKEN(a) bdk_smi_x_clken_t
251 #define bustype_BDK_SMI_X_CLKEN(a) BDK_CSR_TYPE_RSL
252 #define basename_BDK_SMI_X_CLKEN(a) "SMI_X_CLKEN"
253 #define device_bar_BDK_SMI_X_CLKEN(a) 0x0 /* PF_BAR0 */
254 #define busnum_BDK_SMI_X_CLKEN(a) (a)
255 #define arguments_BDK_SMI_X_CLKEN(a) (a),-1,-1,-1
256
257 /**
258 * Register (RSL) smi_#_cmd
259 *
260 * SMI Command Control Register
261 * This register forces a read or write command to the PHY. Write operations to this register
262 * create SMI transactions. Software will poll (depending on the transaction type).
263 */
264 union bdk_smi_x_cmd
265 {
266 uint64_t u;
267 struct bdk_smi_x_cmd_s
268 {
269 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
270 uint64_t reserved_18_63 : 46;
271 uint64_t phy_op : 2; /**< [ 17: 16](R/W) PHY opcode, depending on SMI_()_CLK[MODE] setting.
272 * If SMI_()_CLK[MODE] = 0 (\<=1Gbs / Clause 22):
273 0 = Write operation, encoded in the frame as 01.
274 1 = Read operation, encoded in the frame as 10.
275
276 * If SMI_()_CLK[MODE] = 1 (\>1Gbs / Clause 45):
277 0x0 = Address.
278 0x1 = Write.
279 0x2 = Post-read-increment-address.
280 0x3 = Read. */
281 uint64_t reserved_13_15 : 3;
282 uint64_t phy_adr : 5; /**< [ 12: 8](R/W) PHY address. */
283 uint64_t reserved_5_7 : 3;
284 uint64_t reg_adr : 5; /**< [ 4: 0](R/W) PHY register offset. */
285 #else /* Word 0 - Little Endian */
286 uint64_t reg_adr : 5; /**< [ 4: 0](R/W) PHY register offset. */
287 uint64_t reserved_5_7 : 3;
288 uint64_t phy_adr : 5; /**< [ 12: 8](R/W) PHY address. */
289 uint64_t reserved_13_15 : 3;
290 uint64_t phy_op : 2; /**< [ 17: 16](R/W) PHY opcode, depending on SMI_()_CLK[MODE] setting.
291 * If SMI_()_CLK[MODE] = 0 (\<=1Gbs / Clause 22):
292 0 = Write operation, encoded in the frame as 01.
293 1 = Read operation, encoded in the frame as 10.
294
295 * If SMI_()_CLK[MODE] = 1 (\>1Gbs / Clause 45):
296 0x0 = Address.
297 0x1 = Write.
298 0x2 = Post-read-increment-address.
299 0x3 = Read. */
300 uint64_t reserved_18_63 : 46;
301 #endif /* Word 0 - End */
302 } s;
303 /* struct bdk_smi_x_cmd_s cn; */
304 };
305 typedef union bdk_smi_x_cmd bdk_smi_x_cmd_t;
306
307 static inline uint64_t BDK_SMI_X_CMD(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SMI_X_CMD(unsigned long a)308 static inline uint64_t BDK_SMI_X_CMD(unsigned long a)
309 {
310 if (a<=1)
311 return 0x87e005003800ll + 0x80ll * ((a) & 0x1);
312 __bdk_csr_fatal("SMI_X_CMD", 1, a, 0, 0, 0);
313 }
314
315 #define typedef_BDK_SMI_X_CMD(a) bdk_smi_x_cmd_t
316 #define bustype_BDK_SMI_X_CMD(a) BDK_CSR_TYPE_RSL
317 #define basename_BDK_SMI_X_CMD(a) "SMI_X_CMD"
318 #define device_bar_BDK_SMI_X_CMD(a) 0x0 /* PF_BAR0 */
319 #define busnum_BDK_SMI_X_CMD(a) (a)
320 #define arguments_BDK_SMI_X_CMD(a) (a),-1,-1,-1
321
322 /**
323 * Register (RSL) smi_#_en
324 *
325 * SMI Enable Register
326 * Enables the SMI interface.
327 */
328 union bdk_smi_x_en
329 {
330 uint64_t u;
331 struct bdk_smi_x_en_s
332 {
333 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
334 uint64_t reserved_1_63 : 63;
335 uint64_t en : 1; /**< [ 0: 0](R/W) SMI/MDIO interface enable:
336 1 = Enable interface.
337 0 = Disable interface: no transactions, no SMIn_MDC transitions. */
338 #else /* Word 0 - Little Endian */
339 uint64_t en : 1; /**< [ 0: 0](R/W) SMI/MDIO interface enable:
340 1 = Enable interface.
341 0 = Disable interface: no transactions, no SMIn_MDC transitions. */
342 uint64_t reserved_1_63 : 63;
343 #endif /* Word 0 - End */
344 } s;
345 /* struct bdk_smi_x_en_s cn; */
346 };
347 typedef union bdk_smi_x_en bdk_smi_x_en_t;
348
349 static inline uint64_t BDK_SMI_X_EN(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SMI_X_EN(unsigned long a)350 static inline uint64_t BDK_SMI_X_EN(unsigned long a)
351 {
352 if (a<=1)
353 return 0x87e005003820ll + 0x80ll * ((a) & 0x1);
354 __bdk_csr_fatal("SMI_X_EN", 1, a, 0, 0, 0);
355 }
356
357 #define typedef_BDK_SMI_X_EN(a) bdk_smi_x_en_t
358 #define bustype_BDK_SMI_X_EN(a) BDK_CSR_TYPE_RSL
359 #define basename_BDK_SMI_X_EN(a) "SMI_X_EN"
360 #define device_bar_BDK_SMI_X_EN(a) 0x0 /* PF_BAR0 */
361 #define busnum_BDK_SMI_X_EN(a) (a)
362 #define arguments_BDK_SMI_X_EN(a) (a),-1,-1,-1
363
364 /**
365 * Register (RSL) smi_#_rd_dat
366 *
367 * SMI Read Data Register
368 * This register contains the data in a read operation.
369 */
370 union bdk_smi_x_rd_dat
371 {
372 uint64_t u;
373 struct bdk_smi_x_rd_dat_s
374 {
375 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
376 uint64_t reserved_18_63 : 46;
377 uint64_t pending : 1; /**< [ 17: 17](RO/H) Read transaction pending. Indicates that an SMI read transaction is in flight. */
378 uint64_t val : 1; /**< [ 16: 16](RO/H) Read data valid. Asserts when the read transaction completes. A read to this register clears [VAL]. */
379 uint64_t dat : 16; /**< [ 15: 0](RO/H) Read data. */
380 #else /* Word 0 - Little Endian */
381 uint64_t dat : 16; /**< [ 15: 0](RO/H) Read data. */
382 uint64_t val : 1; /**< [ 16: 16](RO/H) Read data valid. Asserts when the read transaction completes. A read to this register clears [VAL]. */
383 uint64_t pending : 1; /**< [ 17: 17](RO/H) Read transaction pending. Indicates that an SMI read transaction is in flight. */
384 uint64_t reserved_18_63 : 46;
385 #endif /* Word 0 - End */
386 } s;
387 /* struct bdk_smi_x_rd_dat_s cn; */
388 };
389 typedef union bdk_smi_x_rd_dat bdk_smi_x_rd_dat_t;
390
391 static inline uint64_t BDK_SMI_X_RD_DAT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SMI_X_RD_DAT(unsigned long a)392 static inline uint64_t BDK_SMI_X_RD_DAT(unsigned long a)
393 {
394 if (a<=1)
395 return 0x87e005003810ll + 0x80ll * ((a) & 0x1);
396 __bdk_csr_fatal("SMI_X_RD_DAT", 1, a, 0, 0, 0);
397 }
398
399 #define typedef_BDK_SMI_X_RD_DAT(a) bdk_smi_x_rd_dat_t
400 #define bustype_BDK_SMI_X_RD_DAT(a) BDK_CSR_TYPE_RSL
401 #define basename_BDK_SMI_X_RD_DAT(a) "SMI_X_RD_DAT"
402 #define device_bar_BDK_SMI_X_RD_DAT(a) 0x0 /* PF_BAR0 */
403 #define busnum_BDK_SMI_X_RD_DAT(a) (a)
404 #define arguments_BDK_SMI_X_RD_DAT(a) (a),-1,-1,-1
405
406 /**
407 * Register (RSL) smi_#_wr_dat
408 *
409 * SMI Write Data Register
410 * This register provides the data for a write operation.
411 */
412 union bdk_smi_x_wr_dat
413 {
414 uint64_t u;
415 struct bdk_smi_x_wr_dat_s
416 {
417 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
418 uint64_t reserved_18_63 : 46;
419 uint64_t pending : 1; /**< [ 17: 17](RO/H) Write transaction pending. Indicates that an SMI write transaction is in flight. */
420 uint64_t val : 1; /**< [ 16: 16](RO/H) Write data valid. Asserts when the write transaction completes. A read to this
421 register clears [VAL]. */
422 uint64_t dat : 16; /**< [ 15: 0](R/W/H) Write data. */
423 #else /* Word 0 - Little Endian */
424 uint64_t dat : 16; /**< [ 15: 0](R/W/H) Write data. */
425 uint64_t val : 1; /**< [ 16: 16](RO/H) Write data valid. Asserts when the write transaction completes. A read to this
426 register clears [VAL]. */
427 uint64_t pending : 1; /**< [ 17: 17](RO/H) Write transaction pending. Indicates that an SMI write transaction is in flight. */
428 uint64_t reserved_18_63 : 46;
429 #endif /* Word 0 - End */
430 } s;
431 /* struct bdk_smi_x_wr_dat_s cn; */
432 };
433 typedef union bdk_smi_x_wr_dat bdk_smi_x_wr_dat_t;
434
435 static inline uint64_t BDK_SMI_X_WR_DAT(unsigned long a) __attribute__ ((pure, always_inline));
BDK_SMI_X_WR_DAT(unsigned long a)436 static inline uint64_t BDK_SMI_X_WR_DAT(unsigned long a)
437 {
438 if (a<=1)
439 return 0x87e005003808ll + 0x80ll * ((a) & 0x1);
440 __bdk_csr_fatal("SMI_X_WR_DAT", 1, a, 0, 0, 0);
441 }
442
443 #define typedef_BDK_SMI_X_WR_DAT(a) bdk_smi_x_wr_dat_t
444 #define bustype_BDK_SMI_X_WR_DAT(a) BDK_CSR_TYPE_RSL
445 #define basename_BDK_SMI_X_WR_DAT(a) "SMI_X_WR_DAT"
446 #define device_bar_BDK_SMI_X_WR_DAT(a) 0x0 /* PF_BAR0 */
447 #define busnum_BDK_SMI_X_WR_DAT(a) (a)
448 #define arguments_BDK_SMI_X_WR_DAT(a) (a),-1,-1,-1
449
450 /**
451 * Register (RSL) smi_drv_ctl
452 *
453 * SMI Drive Strength Control Register
454 * Enables the SMI interface.
455 */
456 union bdk_smi_drv_ctl
457 {
458 uint64_t u;
459 struct bdk_smi_drv_ctl_s
460 {
461 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
462 uint64_t reserved_11_63 : 53;
463 uint64_t pctl : 3; /**< [ 10: 8](R/W) PCTL drive strength control bits. Suggested values:
464 0x4 = 60 ohm.
465 0x6 = 40 ohm.
466 0x7 = 30 ohm. */
467 uint64_t reserved_3_7 : 5;
468 uint64_t nctl : 3; /**< [ 2: 0](R/W) NCTL drive strength control bits. Suggested values:
469 0x4 = 60 ohm.
470 0x6 = 40 ohm.
471 0x7 = 30 ohm. */
472 #else /* Word 0 - Little Endian */
473 uint64_t nctl : 3; /**< [ 2: 0](R/W) NCTL drive strength control bits. Suggested values:
474 0x4 = 60 ohm.
475 0x6 = 40 ohm.
476 0x7 = 30 ohm. */
477 uint64_t reserved_3_7 : 5;
478 uint64_t pctl : 3; /**< [ 10: 8](R/W) PCTL drive strength control bits. Suggested values:
479 0x4 = 60 ohm.
480 0x6 = 40 ohm.
481 0x7 = 30 ohm. */
482 uint64_t reserved_11_63 : 53;
483 #endif /* Word 0 - End */
484 } s;
485 /* struct bdk_smi_drv_ctl_s cn; */
486 };
487 typedef union bdk_smi_drv_ctl bdk_smi_drv_ctl_t;
488
489 #define BDK_SMI_DRV_CTL BDK_SMI_DRV_CTL_FUNC()
490 static inline uint64_t BDK_SMI_DRV_CTL_FUNC(void) __attribute__ ((pure, always_inline));
BDK_SMI_DRV_CTL_FUNC(void)491 static inline uint64_t BDK_SMI_DRV_CTL_FUNC(void)
492 {
493 return 0x87e005003828ll;
494 }
495
496 #define typedef_BDK_SMI_DRV_CTL bdk_smi_drv_ctl_t
497 #define bustype_BDK_SMI_DRV_CTL BDK_CSR_TYPE_RSL
498 #define basename_BDK_SMI_DRV_CTL "SMI_DRV_CTL"
499 #define device_bar_BDK_SMI_DRV_CTL 0x0 /* PF_BAR0 */
500 #define busnum_BDK_SMI_DRV_CTL 0
501 #define arguments_BDK_SMI_DRV_CTL -1,-1,-1,-1
502
503 /**
504 * Register (RSL) smi_drv_rsvd
505 *
506 * INTERNAL: SMI Drive Reserve Register
507 *
508 * Enables the SMI1 interface.
509 */
510 union bdk_smi_drv_rsvd
511 {
512 uint64_t u;
513 struct bdk_smi_drv_rsvd_s
514 {
515 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
516 uint64_t reserved_11_63 : 53;
517 uint64_t pctl : 3; /**< [ 10: 8](R/W) Reserved. */
518 uint64_t reserved_3_7 : 5;
519 uint64_t nctl : 3; /**< [ 2: 0](R/W) Reserved. */
520 #else /* Word 0 - Little Endian */
521 uint64_t nctl : 3; /**< [ 2: 0](R/W) Reserved. */
522 uint64_t reserved_3_7 : 5;
523 uint64_t pctl : 3; /**< [ 10: 8](R/W) Reserved. */
524 uint64_t reserved_11_63 : 53;
525 #endif /* Word 0 - End */
526 } s;
527 /* struct bdk_smi_drv_rsvd_s cn; */
528 };
529 typedef union bdk_smi_drv_rsvd bdk_smi_drv_rsvd_t;
530
531 #define BDK_SMI_DRV_RSVD BDK_SMI_DRV_RSVD_FUNC()
532 static inline uint64_t BDK_SMI_DRV_RSVD_FUNC(void) __attribute__ ((pure, always_inline));
BDK_SMI_DRV_RSVD_FUNC(void)533 static inline uint64_t BDK_SMI_DRV_RSVD_FUNC(void)
534 {
535 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX))
536 return 0x87e0050038a8ll;
537 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX))
538 return 0x87e0050038a8ll;
539 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
540 return 0x87e0050038a8ll;
541 __bdk_csr_fatal("SMI_DRV_RSVD", 0, 0, 0, 0, 0);
542 }
543
544 #define typedef_BDK_SMI_DRV_RSVD bdk_smi_drv_rsvd_t
545 #define bustype_BDK_SMI_DRV_RSVD BDK_CSR_TYPE_RSL
546 #define basename_BDK_SMI_DRV_RSVD "SMI_DRV_RSVD"
547 #define device_bar_BDK_SMI_DRV_RSVD 0x0 /* PF_BAR0 */
548 #define busnum_BDK_SMI_DRV_RSVD 0
549 #define arguments_BDK_SMI_DRV_RSVD -1,-1,-1,-1
550
551 #endif /* __BDK_CSRS_SMI_H__ */
552