1 #ifndef __BDK_CSRS_GPIO_H__
2 #define __BDK_CSRS_GPIO_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***************
6 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights
7 * reserved.
8 *
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are
12 * met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided
20 * with the distribution.
21
22 * * Neither the name of Cavium Inc. nor the names of
23 * its contributors may be used to endorse or promote products
24 * derived from this software without specific prior written
25 * permission.
26
27 * This Software, including technical data, may be subject to U.S. export control
28 * laws, including the U.S. Export Administration Act and its associated
29 * regulations, and may be subject to export or import regulations in other
30 * countries.
31
32 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
33 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
34 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
35 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
36 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
37 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
38 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
39 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
40 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
41 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
42 ***********************license end**************************************/
43
44
45 /**
46 * @file
47 *
48 * Configuration and status register (CSR) address and type definitions for
49 * Cavium GPIO.
50 *
51 * This file is auto generated. Do not edit.
52 *
53 */
54
55 /**
56 * Enumeration gpio_assigned_pin_e
57 *
58 * GPIO Assigned Pin Number Enumeration
59 * Enumerates GPIO pin numbers which have certain dedicated hardware and boot usage.
60 */
61 #define BDK_GPIO_ASSIGNED_PIN_E_BOOT_REQ (9)
62 #define BDK_GPIO_ASSIGNED_PIN_E_BOOT_WAIT (0xe)
63 #define BDK_GPIO_ASSIGNED_PIN_E_EJTAG_TCK (0x13)
64 #define BDK_GPIO_ASSIGNED_PIN_E_EJTAG_TDI (0x14)
65 #define BDK_GPIO_ASSIGNED_PIN_E_EJTAG_TDO (0x12)
66 #define BDK_GPIO_ASSIGNED_PIN_E_EJTAG_TMS (0x15)
67 #define BDK_GPIO_ASSIGNED_PIN_E_EMMC_POWER (8)
68 #define BDK_GPIO_ASSIGNED_PIN_E_FAILED (0xa)
69 #define BDK_GPIO_ASSIGNED_PIN_E_FAIL_CODE (0xb)
70 #define BDK_GPIO_ASSIGNED_PIN_E_NCSI_CRS_DV (0x1f)
71 #define BDK_GPIO_ASSIGNED_PIN_E_NCSI_REF_CLK (0x1a)
72 #define BDK_GPIO_ASSIGNED_PIN_E_NCSI_RXD0 (0x1c)
73 #define BDK_GPIO_ASSIGNED_PIN_E_NCSI_RXD1 (0x1d)
74 #define BDK_GPIO_ASSIGNED_PIN_E_NCSI_RX_ER (0x1e)
75 #define BDK_GPIO_ASSIGNED_PIN_E_NCSI_TXD0 (0x18)
76 #define BDK_GPIO_ASSIGNED_PIN_E_NCSI_TXD1 (0x19)
77 #define BDK_GPIO_ASSIGNED_PIN_E_NCSI_TX_EN (0x1b)
78 #define BDK_GPIO_ASSIGNED_PIN_E_PSPI_CLK (0x27)
79 #define BDK_GPIO_ASSIGNED_PIN_E_PSPI_CS (0x2a)
80 #define BDK_GPIO_ASSIGNED_PIN_E_PSPI_MISO (0x29)
81 #define BDK_GPIO_ASSIGNED_PIN_E_PSPI_MOSI (0x28)
82 #define BDK_GPIO_ASSIGNED_PIN_E_SPI1_CLK (0x24)
83 #define BDK_GPIO_ASSIGNED_PIN_E_SPI1_CS0 (0x25)
84 #define BDK_GPIO_ASSIGNED_PIN_E_SPI1_CS1 (0x26)
85 #define BDK_GPIO_ASSIGNED_PIN_E_SPI1_IO0 (0x20)
86 #define BDK_GPIO_ASSIGNED_PIN_E_SPI1_IO1 (0x21)
87 #define BDK_GPIO_ASSIGNED_PIN_E_SPI1_IO2 (0x22)
88 #define BDK_GPIO_ASSIGNED_PIN_E_SPI1_IO3 (0x23)
89 #define BDK_GPIO_ASSIGNED_PIN_E_SWP_RESET_L (0x2c)
90 #define BDK_GPIO_ASSIGNED_PIN_E_SWP_SPI1_CS3 (0x2b)
91 #define BDK_GPIO_ASSIGNED_PIN_E_UART7_CTS_L (0x16)
92 #define BDK_GPIO_ASSIGNED_PIN_E_UART7_RTS_L (0xc)
93 #define BDK_GPIO_ASSIGNED_PIN_E_UART7_SIN (0x17)
94 #define BDK_GPIO_ASSIGNED_PIN_E_UART7_SOUT (0xd)
95
96 /**
97 * Enumeration gpio_bar_e
98 *
99 * GPIO Base Address Register Enumeration
100 * Enumerates the base address registers.
101 */
102 #define BDK_GPIO_BAR_E_GPIO_PF_BAR0_CN8 (0x803000000000ll)
103 #define BDK_GPIO_BAR_E_GPIO_PF_BAR0_CN8_SIZE 0x800000ull
104 #define BDK_GPIO_BAR_E_GPIO_PF_BAR0_CN9 (0x803000000000ll)
105 #define BDK_GPIO_BAR_E_GPIO_PF_BAR0_CN9_SIZE 0x10000ull
106 #define BDK_GPIO_BAR_E_GPIO_PF_BAR4 (0x803000f00000ll)
107 #define BDK_GPIO_BAR_E_GPIO_PF_BAR4_SIZE 0x100000ull
108
109 /**
110 * Enumeration gpio_int_vec_e
111 *
112 * GPIO MSI-X Vector Enumeration
113 * Enumerates the MSI-X interrupt vectors.
114 */
115 #define BDK_GPIO_INT_VEC_E_INTR_PINX_CN9(a) (0x36 + 2 * (a))
116 #define BDK_GPIO_INT_VEC_E_INTR_PINX_CN81XX(a) (4 + 2 * (a))
117 #define BDK_GPIO_INT_VEC_E_INTR_PINX_CN88XX(a) (0x30 + 2 * (a))
118 #define BDK_GPIO_INT_VEC_E_INTR_PINX_CN83XX(a) (0x18 + 2 * (a))
119 #define BDK_GPIO_INT_VEC_E_INTR_PINX_CLEAR_CN9(a) (0x37 + 2 * (a))
120 #define BDK_GPIO_INT_VEC_E_INTR_PINX_CLEAR_CN81XX(a) (5 + 2 * (a))
121 #define BDK_GPIO_INT_VEC_E_INTR_PINX_CLEAR_CN88XX(a) (0x31 + 2 * (a))
122 #define BDK_GPIO_INT_VEC_E_INTR_PINX_CLEAR_CN83XX(a) (0x19 + 2 * (a))
123 #define BDK_GPIO_INT_VEC_E_MC_INTR_PPX(a) (0 + (a))
124
125 /**
126 * Enumeration gpio_pin_sel_e
127 *
128 * GPIO Pin Select Enumeration
129 * Enumerates the GPIO pin function selections for GPIO_BIT_CFG()[PIN_SEL].
130 *
131 * The GPIO pins can be configured as either input, output or input/output/bidirectional
132 * depending on the GPIO_PIN_SEL_E used as described in the value's description. When
133 * a GPIO pin is used as input, the value is provided to the described function, and is
134 * also readable via GPIO_RX_DAT.
135 *
136 * Multiple GPIO pins may not be configured to point to the same input encoding, or
137 * the input result is unpredictable (e.g. GPIO_BIT_CFG(1)[PIN_SEL] and
138 * GPIO_BIT_CFG(2)[PIN_SEL] cannot both be 0x80).
139 *
140 * If a given select is not assigned to any pin, then that virtual input receives a
141 * logical zero. E.g. if no GPIO_BIT_CFG()[PIN_SEL] has the value ::OCLA_EXT_TRIGGER,
142 * then the GPIO will provide the OCLA block's external trigger input with the value of
143 * zero.
144 *
145 * Internal:
146 * FIXME keep PCM_* as reserved encodings.
147 */
148 #define BDK_GPIO_PIN_SEL_E_BOOT_REQ (0x3e0)
149 #define BDK_GPIO_PIN_SEL_E_BOOT_WAIT (0x3e1)
150 #define BDK_GPIO_PIN_SEL_E_BTS_BFN_CLK (0x506)
151 #define BDK_GPIO_PIN_SEL_E_BTS_BFN_IN (0x505)
152 #define BDK_GPIO_PIN_SEL_E_BTS_BFN_OUT (0x510)
153 #define BDK_GPIO_PIN_SEL_E_BTS_CGBFN_OUT (0x50d)
154 #define BDK_GPIO_PIN_SEL_E_BTS_CGCLK_OUT (0x50e)
155 #define BDK_GPIO_PIN_SEL_E_BTS_CGTENMS_OUT (0x50c)
156 #define BDK_GPIO_PIN_SEL_E_BTS_DAC_CLK (0x511)
157 #define BDK_GPIO_PIN_SEL_E_BTS_EXTREFX_CLK(a) (0x500 + (a))
158 #define BDK_GPIO_PIN_SEL_E_BTS_PWM_DOUT (0x513)
159 #define BDK_GPIO_PIN_SEL_E_BTS_PWM_SCLK (0x512)
160 #define BDK_GPIO_PIN_SEL_E_BTS_RFP_IN (0x504)
161 #define BDK_GPIO_PIN_SEL_E_BTS_RFP_OUT (0x50f)
162 #define BDK_GPIO_PIN_SEL_E_BTS_TPX(a) (0x508 + (a))
163 #define BDK_GPIO_PIN_SEL_E_CER_CATERR (0x3fb)
164 #define BDK_GPIO_PIN_SEL_E_CER_ERR0 (0x3f8)
165 #define BDK_GPIO_PIN_SEL_E_CER_ERR1 (0x3f9)
166 #define BDK_GPIO_PIN_SEL_E_CER_ERR2 (0x3fa)
167 #define BDK_GPIO_PIN_SEL_E_CGXX_LMACX_RX(a,b) (0x4a0 + 4 * (a) + (b))
168 #define BDK_GPIO_PIN_SEL_E_CGXX_LMACX_RXTX(a,b) (0x4e0 + 4 * (a) + (b))
169 #define BDK_GPIO_PIN_SEL_E_CGXX_LMACX_TX(a,b) (0x4c0 + 4 * (a) + (b))
170 #define BDK_GPIO_PIN_SEL_E_CORE_RESET_IN (0x480)
171 #define BDK_GPIO_PIN_SEL_E_CORE_RESET_OUT (0x481)
172 #define BDK_GPIO_PIN_SEL_E_EJTAG_TCK (0x3f1)
173 #define BDK_GPIO_PIN_SEL_E_EJTAG_TDI (0x3f0)
174 #define BDK_GPIO_PIN_SEL_E_EJTAG_TDO (0x3f4)
175 #define BDK_GPIO_PIN_SEL_E_EJTAG_TMS (0x3f2)
176 #define BDK_GPIO_PIN_SEL_E_GPIO_CLKX_CN8(a) (5 + (a))
177 #define BDK_GPIO_PIN_SEL_E_GPIO_CLKX_CN9(a) (0x260 + (a))
178 #define BDK_GPIO_PIN_SEL_E_GPIO_CLK_SYNCEX(a) (3 + (a))
179 #define BDK_GPIO_PIN_SEL_E_GPIO_PTP_CKOUT (1)
180 #define BDK_GPIO_PIN_SEL_E_GPIO_PTP_PPS (2)
181 #define BDK_GPIO_PIN_SEL_E_GPIO_PTP_SYSCK (8)
182 #define BDK_GPIO_PIN_SEL_E_GPIO_SW (0)
183 #define BDK_GPIO_PIN_SEL_E_LMCX_ECC_CN9(a) (0x3d0 + (a))
184 #define BDK_GPIO_PIN_SEL_E_LMCX_ECC_CN81XX(a) (0x237 + (a))
185 #define BDK_GPIO_PIN_SEL_E_LMCX_ECC_CN88XX(a) (0x70 + (a))
186 #define BDK_GPIO_PIN_SEL_E_LMCX_ECC_CN83XX(a) (0x237 + (a))
187 #define BDK_GPIO_PIN_SEL_E_MCDX_IN_CN9(a) (0x23f + (a))
188 #define BDK_GPIO_PIN_SEL_E_MCDX_IN_CN81XX(a) (0x23f + (a))
189 #define BDK_GPIO_PIN_SEL_E_MCDX_IN_CN88XX(a) (0xb0 + (a))
190 #define BDK_GPIO_PIN_SEL_E_MCDX_IN_CN83XX(a) (0x23f + (a))
191 #define BDK_GPIO_PIN_SEL_E_MCDX_OUT_CN9(a) (0x242 + (a))
192 #define BDK_GPIO_PIN_SEL_E_MCDX_OUT_CN81XX(a) (0x242 + (a))
193 #define BDK_GPIO_PIN_SEL_E_MCDX_OUT_CN88XX(a) (0x14 + (a))
194 #define BDK_GPIO_PIN_SEL_E_MCDX_OUT_CN83XX(a) (0x242 + (a))
195 #define BDK_GPIO_PIN_SEL_E_MCP_RESET_IN (0x482)
196 #define BDK_GPIO_PIN_SEL_E_MCP_RESET_OUT (0x483)
197 #define BDK_GPIO_PIN_SEL_E_NCSI_CRS_DV (0x258)
198 #define BDK_GPIO_PIN_SEL_E_NCSI_REF_CLK (0x25c)
199 #define BDK_GPIO_PIN_SEL_E_NCSI_RXDX(a) (0x25a + (a))
200 #define BDK_GPIO_PIN_SEL_E_NCSI_RX_ER (0x259)
201 #define BDK_GPIO_PIN_SEL_E_NCSI_TXDX(a) (0x25e + (a))
202 #define BDK_GPIO_PIN_SEL_E_NCSI_TX_EN (0x25d)
203 #define BDK_GPIO_PIN_SEL_E_OCLA_EXT_TRIGGER_CN9 (0x231)
204 #define BDK_GPIO_PIN_SEL_E_OCLA_EXT_TRIGGER_CN81XX (0x231)
205 #define BDK_GPIO_PIN_SEL_E_OCLA_EXT_TRIGGER_CN88XX (0x8a)
206 #define BDK_GPIO_PIN_SEL_E_OCLA_EXT_TRIGGER_CN83XX (0x231)
207 #define BDK_GPIO_PIN_SEL_E_PBUS_ADX(a) (0xfa + (a))
208 #define BDK_GPIO_PIN_SEL_E_PBUS_ALEX(a) (0xe8 + (a))
209 #define BDK_GPIO_PIN_SEL_E_PBUS_CEX(a) (0xec + (a))
210 #define BDK_GPIO_PIN_SEL_E_PBUS_CLE (0xe0)
211 #define BDK_GPIO_PIN_SEL_E_PBUS_DIR (0xe4)
212 #define BDK_GPIO_PIN_SEL_E_PBUS_DMACKX(a) (0xe6 + (a))
213 #define BDK_GPIO_PIN_SEL_E_PBUS_DMARQX(a) (0x11a + (a))
214 #define BDK_GPIO_PIN_SEL_E_PBUS_OE (0xe3)
215 #define BDK_GPIO_PIN_SEL_E_PBUS_WAIT (0xe1)
216 #define BDK_GPIO_PIN_SEL_E_PBUS_WE (0xe2)
217 #define BDK_GPIO_PIN_SEL_E_PCM_BCLKX(a) (0x246 + (a))
218 #define BDK_GPIO_PIN_SEL_E_PCM_DATAX(a) (0x24c + (a))
219 #define BDK_GPIO_PIN_SEL_E_PCM_FSYNCX(a) (0x24a + (a))
220 #define BDK_GPIO_PIN_SEL_E_PSPI_CLK (0x28d)
221 #define BDK_GPIO_PIN_SEL_E_PSPI_CS (0x290)
222 #define BDK_GPIO_PIN_SEL_E_PSPI_MISO (0x28f)
223 #define BDK_GPIO_PIN_SEL_E_PSPI_MOSI (0x28e)
224 #define BDK_GPIO_PIN_SEL_E_PTP_EVTCNT (0x252)
225 #define BDK_GPIO_PIN_SEL_E_PTP_EXT_CLK (0x250)
226 #define BDK_GPIO_PIN_SEL_E_PTP_TSTMP (0x251)
227 #define BDK_GPIO_PIN_SEL_E_SATAX_ACT_LED_CN9(a) (0x420 + (a))
228 #define BDK_GPIO_PIN_SEL_E_SATAX_ACT_LED_CN81XX(a) (0x16a + (a))
229 #define BDK_GPIO_PIN_SEL_E_SATAX_ACT_LED_CN88XX(a) (0x60 + (a))
230 #define BDK_GPIO_PIN_SEL_E_SATAX_ACT_LED_CN83XX(a) (0x16a + (a))
231 #define BDK_GPIO_PIN_SEL_E_SATAX_CP_DET_CN9(a) (0x440 + (a))
232 #define BDK_GPIO_PIN_SEL_E_SATAX_CP_DET_CN81XX(a) (0x18b + (a))
233 #define BDK_GPIO_PIN_SEL_E_SATAX_CP_DET_CN88XX(a) (0x90 + (a))
234 #define BDK_GPIO_PIN_SEL_E_SATAX_CP_DET_CN83XX(a) (0x18b + (a))
235 #define BDK_GPIO_PIN_SEL_E_SATAX_CP_POD_CN9(a) (0x400 + (a))
236 #define BDK_GPIO_PIN_SEL_E_SATAX_CP_POD_CN81XX(a) (0x145 + (a))
237 #define BDK_GPIO_PIN_SEL_E_SATAX_CP_POD_CN88XX(a) (0x50 + (a))
238 #define BDK_GPIO_PIN_SEL_E_SATAX_CP_POD_CN83XX(a) (0x145 + (a))
239 #define BDK_GPIO_PIN_SEL_E_SATAX_MP_SWITCH_CN9(a) (0x460 + (a))
240 #define BDK_GPIO_PIN_SEL_E_SATAX_MP_SWITCH_CN81XX(a) (0x200 + (a))
241 #define BDK_GPIO_PIN_SEL_E_SATAX_MP_SWITCH_CN88XX(a) (0xa0 + (a))
242 #define BDK_GPIO_PIN_SEL_E_SATAX_MP_SWITCH_CN83XX(a) (0x200 + (a))
243 #define BDK_GPIO_PIN_SEL_E_SATA_LAB_LB_CN9 (0x18a)
244 #define BDK_GPIO_PIN_SEL_E_SATA_LAB_LB_CN81XX (0x18a)
245 #define BDK_GPIO_PIN_SEL_E_SATA_LAB_LB_CN88XX (0x8e)
246 #define BDK_GPIO_PIN_SEL_E_SATA_LAB_LB_CN83XX (0x18a)
247 #define BDK_GPIO_PIN_SEL_E_SCP_RESET_IN (0x484)
248 #define BDK_GPIO_PIN_SEL_E_SCP_RESET_OUT (0x485)
249 #define BDK_GPIO_PIN_SEL_E_SGPIO_ACT_LEDX_CN9(a) (0x2c0 + (a))
250 #define BDK_GPIO_PIN_SEL_E_SGPIO_ACT_LEDX_CN81XX(a) (0xf + (a))
251 #define BDK_GPIO_PIN_SEL_E_SGPIO_ACT_LEDX_CN88XX(a) (0x20 + (a))
252 #define BDK_GPIO_PIN_SEL_E_SGPIO_ACT_LEDX_CN83XX(a) (0xf + (a))
253 #define BDK_GPIO_PIN_SEL_E_SGPIO_ERR_LEDX_CN9(a) (0x340 + (a))
254 #define BDK_GPIO_PIN_SEL_E_SGPIO_ERR_LEDX_CN81XX(a) (0x90 + (a))
255 #define BDK_GPIO_PIN_SEL_E_SGPIO_ERR_LEDX_CN88XX(a) (0x30 + (a))
256 #define BDK_GPIO_PIN_SEL_E_SGPIO_ERR_LEDX_CN83XX(a) (0x90 + (a))
257 #define BDK_GPIO_PIN_SEL_E_SGPIO_LOC_LEDX_CN9(a) (0x300 + (a))
258 #define BDK_GPIO_PIN_SEL_E_SGPIO_LOC_LEDX_CN81XX(a) (0x50 + (a))
259 #define BDK_GPIO_PIN_SEL_E_SGPIO_LOC_LEDX_CN88XX(a) (0x40 + (a))
260 #define BDK_GPIO_PIN_SEL_E_SGPIO_LOC_LEDX_CN83XX(a) (0x50 + (a))
261 #define BDK_GPIO_PIN_SEL_E_SGPIO_SCLOCK_CN9 (0x2a0)
262 #define BDK_GPIO_PIN_SEL_E_SGPIO_SCLOCK_CN81XX (9)
263 #define BDK_GPIO_PIN_SEL_E_SGPIO_SCLOCK_CN88XX (0xb)
264 #define BDK_GPIO_PIN_SEL_E_SGPIO_SCLOCK_CN83XX (9)
265 #define BDK_GPIO_PIN_SEL_E_SGPIO_SDATAINX_CN9(a) (0x380 + (a))
266 #define BDK_GPIO_PIN_SEL_E_SGPIO_SDATAINX_CN81XX(a) (0xd0 + (a))
267 #define BDK_GPIO_PIN_SEL_E_SGPIO_SDATAINX_CN88XX(a) (0x80 + (a))
268 #define BDK_GPIO_PIN_SEL_E_SGPIO_SDATAINX_CN83XX(a) (0xd0 + (a))
269 #define BDK_GPIO_PIN_SEL_E_SGPIO_SDATAOUTX_CN9(a) (0x2b0 + (a))
270 #define BDK_GPIO_PIN_SEL_E_SGPIO_SDATAOUTX_CN81XX(a) (0xb + (a))
271 #define BDK_GPIO_PIN_SEL_E_SGPIO_SDATAOUTX_CN88XX(a) (0x10 + (a))
272 #define BDK_GPIO_PIN_SEL_E_SGPIO_SDATAOUTX_CN83XX(a) (0xb + (a))
273 #define BDK_GPIO_PIN_SEL_E_SGPIO_SLOAD_CN9 (0x2a1)
274 #define BDK_GPIO_PIN_SEL_E_SGPIO_SLOAD_CN81XX (0xa)
275 #define BDK_GPIO_PIN_SEL_E_SGPIO_SLOAD_CN88XX (0xc)
276 #define BDK_GPIO_PIN_SEL_E_SGPIO_SLOAD_CN83XX (0xa)
277 #define BDK_GPIO_PIN_SEL_E_SPI0_CSX(a) (0x278 + (a))
278 #define BDK_GPIO_PIN_SEL_E_SPI1_CLK (0x280)
279 #define BDK_GPIO_PIN_SEL_E_SPI1_CSX(a) (0x284 + (a))
280 #define BDK_GPIO_PIN_SEL_E_SPI1_IOX(a) (0x288 + (a))
281 #define BDK_GPIO_PIN_SEL_E_SPI_CSX_CN81XX(a) (0x233 + (a))
282 #define BDK_GPIO_PIN_SEL_E_SPI_CSX_CN88XX(a) (0x18 + (a))
283 #define BDK_GPIO_PIN_SEL_E_SPI_CSX_CN83XX(a) (0x233 + (a))
284 #define BDK_GPIO_PIN_SEL_E_TIMER_CN9 (0x11c)
285 #define BDK_GPIO_PIN_SEL_E_TIMER_CN81XX (0x11c)
286 #define BDK_GPIO_PIN_SEL_E_TIMER_CN88XX (0x8b)
287 #define BDK_GPIO_PIN_SEL_E_TIMER_CN83XX (0x11c)
288 #define BDK_GPIO_PIN_SEL_E_TIM_GPIO_CLK (0x230)
289 #define BDK_GPIO_PIN_SEL_E_TWS_SCLX(a) (0x294 + (a))
290 #define BDK_GPIO_PIN_SEL_E_TWS_SDAX(a) (0x29a + (a))
291 #define BDK_GPIO_PIN_SEL_E_UARTX_CTS_CN8(a) (0x13f + (a))
292 #define BDK_GPIO_PIN_SEL_E_UARTX_CTS_CN9(a) (0x3c0 + (a))
293 #define BDK_GPIO_PIN_SEL_E_UARTX_DCD_CN8(a) (0x131 + (a))
294 #define BDK_GPIO_PIN_SEL_E_UARTX_DCD_CN9(a) (0x3b0 + (a))
295 #define BDK_GPIO_PIN_SEL_E_UARTX_DCD_N(a) (0x84 + (a))
296 #define BDK_GPIO_PIN_SEL_E_UARTX_DSR_CN9(a) (0x3b8 + (a))
297 #define BDK_GPIO_PIN_SEL_E_UARTX_DSR_CN81XX(a) (0x139 + (a))
298 #define BDK_GPIO_PIN_SEL_E_UARTX_DSR_CN88XX(a) (0x88 + (a))
299 #define BDK_GPIO_PIN_SEL_E_UARTX_DSR_CN83XX(a) (0x139 + (a))
300 #define BDK_GPIO_PIN_SEL_E_UARTX_DTR_CN8(a) (0x11d + (a))
301 #define BDK_GPIO_PIN_SEL_E_UARTX_DTR_CN9(a) (0x390 + (a))
302 #define BDK_GPIO_PIN_SEL_E_UARTX_DTR_N(a) (9 + (a))
303 #define BDK_GPIO_PIN_SEL_E_UARTX_RI_CN9(a) (0x3a8 + (a))
304 #define BDK_GPIO_PIN_SEL_E_UARTX_RI_CN81XX(a) (0x129 + (a))
305 #define BDK_GPIO_PIN_SEL_E_UARTX_RI_CN88XX(a) (0x86 + (a))
306 #define BDK_GPIO_PIN_SEL_E_UARTX_RI_CN83XX(a) (0x129 + (a))
307 #define BDK_GPIO_PIN_SEL_E_UARTX_RTS_CN8(a) (0x123 + (a))
308 #define BDK_GPIO_PIN_SEL_E_UARTX_RTS_CN9(a) (0x398 + (a))
309 #define BDK_GPIO_PIN_SEL_E_UARTX_SIN_CN8(a) (0x141 + (a))
310 #define BDK_GPIO_PIN_SEL_E_UARTX_SIN_CN9(a) (0x3c8 + (a))
311 #define BDK_GPIO_PIN_SEL_E_UARTX_SOUT_CN8(a) (0x125 + (a))
312 #define BDK_GPIO_PIN_SEL_E_UARTX_SOUT_CN9(a) (0x3a0 + (a))
313 #define BDK_GPIO_PIN_SEL_E_USBX_OVR_CRNT_CN9(a) (0x228 + (a))
314 #define BDK_GPIO_PIN_SEL_E_USBX_OVR_CRNT_CN81XX(a) (0x228 + (a))
315 #define BDK_GPIO_PIN_SEL_E_USBX_OVR_CRNT_CN88XX(a) (0x8c + (a))
316 #define BDK_GPIO_PIN_SEL_E_USBX_OVR_CRNT_CN83XX(a) (0x228 + (a))
317 #define BDK_GPIO_PIN_SEL_E_USBX_VBUS_CTRL_CN9(a) (0x220 + (a))
318 #define BDK_GPIO_PIN_SEL_E_USBX_VBUS_CTRL_CN81XX(a) (0x220 + (a))
319 #define BDK_GPIO_PIN_SEL_E_USBX_VBUS_CTRL_CN88XX(a) (0x74 + (a))
320 #define BDK_GPIO_PIN_SEL_E_USBX_VBUS_CTRL_CN83XX(a) (0x220 + (a))
321
322 /**
323 * Enumeration gpio_strap_pin_e
324 *
325 * GPIO Strap Pin Number Enumeration
326 * Enumerates GPIO pin numbers with their associated strap functions. The names of
327 * these values are used as the documented name of each
328 * strap. e.g. GPIO_STRAP_PIN_E::BOOT_METHOD0 describes the GPIO0/BOOT_METHOD0 strap.
329 */
330 #define BDK_GPIO_STRAP_PIN_E_AVS_DISABLE (9)
331 #define BDK_GPIO_STRAP_PIN_E_BOOT_METHOD0 (0)
332 #define BDK_GPIO_STRAP_PIN_E_BOOT_METHOD1 (1)
333 #define BDK_GPIO_STRAP_PIN_E_BOOT_METHOD2 (2)
334 #define BDK_GPIO_STRAP_PIN_E_BOOT_METHOD3 (3)
335 #define BDK_GPIO_STRAP_PIN_E_BOOT_METHOD4 (0xc)
336 #define BDK_GPIO_STRAP_PIN_E_BOOT_METHOD5 (0xd)
337 #define BDK_GPIO_STRAP_PIN_E_CCPI_NODE_ID (0xb)
338 #define BDK_GPIO_STRAP_PIN_E_GSER_CLK0_TERM_SEL0 (0x10)
339 #define BDK_GPIO_STRAP_PIN_E_GSER_CLK0_TERM_SEL1 (0x11)
340 #define BDK_GPIO_STRAP_PIN_E_MCP_DBG_ON_GPIO (4)
341 #define BDK_GPIO_STRAP_PIN_E_NCSI_ON_GPIO (5)
342 #define BDK_GPIO_STRAP_PIN_E_PCIE0_EP_MODE (0x18)
343 #define BDK_GPIO_STRAP_PIN_E_PCIE2_EP_MODE (0x19)
344 #define BDK_GPIO_STRAP_PIN_E_TRUSTED_MODE (0xa)
345
346 /**
347 * Register (NCB) gpio_bit_cfg#
348 *
349 * GPIO Bit Configuration Registers
350 * Each register provides configuration information for the corresponding GPIO pin.
351 *
352 * Each index is only accessible to the requestor(s) permitted with GPIO_BIT_PERMIT().
353 *
354 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
355 */
356 union bdk_gpio_bit_cfgx
357 {
358 uint64_t u;
359 struct bdk_gpio_bit_cfgx_s
360 {
361 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
362 uint64_t reserved_27_63 : 37;
363 uint64_t pin_sel : 11; /**< [ 26: 16](R/W) Selects which signal is reported to GPIO output, or which signal GPIO input need to
364 connect. Each GPIO pin can be configured either input-only or output-only depending
365 function selected, as enumerated by GPIO_PIN_SEL_E. For GPIO input selects,
366 the GPIO signal used is after glitch filter and XOR inverter (GPIO_BIT_CFG()[PIN_XOR]). */
367 uint64_t reserved_15 : 1;
368 uint64_t blink_en : 2; /**< [ 14: 13](R/W) GPIO pin output blink filter enable. This function is after the [PIN_SEL]
369 multiplexing but before the [PIN_XOR] inverter and [TX_OD] overdriver
370 conversion. When blink filter is enabled, the pin output will generate blinking
371 pattern based on configuration of GPIO_BLINK_CFG.
372 0x0 = Disable blink filter.
373 0x1 = Enable blink filter based on the start of activity.
374 0x2 = Enable blink filter based on the end of activity, essentially based on
375 inversion of blink filter's input.
376 0x3 = Disable blink filter. */
377 uint64_t tx_od : 1; /**< [ 12: 12](R/W) GPIO output open-drain conversion. This function is after PIN_SEL MUX
378 and [PIN_XOR] inverter.
379 When set, the pin output will connect to zero, and pin enable
380 will connect to original pin output. With both [TX_OD] and [PIN_XOR] set, a transmit
381 of 1 will tristate the pin output driver to archive open-drain function. */
382 uint64_t fil_sel : 4; /**< [ 11: 8](R/W) Filter select. Global counter bit-select (controls sample rate).
383 Filter and XOR inverter are also applicable to GPIO input muxing signals and interrupts. */
384 uint64_t fil_cnt : 4; /**< [ 7: 4](R/W) Filter count. Specifies the number of consecutive samples ([FIL_CNT]+1) to change state.
385 Zero to disable the filter.
386 Filter and XOR inverter are also applicable to GPIO input muxing signals and interrupts. */
387 uint64_t int_type : 1; /**< [ 3: 3](R/W) Type of interrupt when pin is an input and [INT_EN] set. When set, rising edge
388 interrupt, else level interrupt. The GPIO signal used to generate interrupt is after
389 the filter and after the XOR inverter. */
390 uint64_t int_en : 1; /**< [ 2: 2](R/W) Pin controls interrupt.
391
392 If set, assertions of this pin after [PIN_XOR] will set GPIO_INTR()[INTR].
393
394 If set and [INT_TYPE] is clear (level-sensitive), deassertions of this pin
395 after [PIN_XOR] will clear GPIO_INTR()[INTR].
396
397 This does NOT control if interrupts are enabled towards the MSI-X vector,
398 for that see GPIO_INTR()[INTR_ENA]. */
399 uint64_t pin_xor : 1; /**< [ 1: 1](R/W) GPIO data inversion. When set, inverts the receiving or transmitting GPIO signal.
400 For GPIO output, this inversion is after all GPIO [PIN_SEL] muxes. This inversion function
401 is applicable to any GPIO output mux signals, also used to control GPIO_RX_DAT.
402 For GPIO input, this inversion is before the GPIO [PIN_SEL] muxes, as used to control
403 GPIO interrupts. */
404 uint64_t tx_oe : 1; /**< [ 0: 0](R/W) Transmit output enable. When set to 1, the GPIO pin can be driven as an output
405 pin if GPIO_BIT_CFG()[PIN_SEL] selects GPIO_PIN_SEL_E::GPIO_SW. [TX_OE] is only
406 used along with GPIO_TX_SET or GPIO_TX_CLR, and [TX_OE] function is before
407 GPIO_BIT_CFG()[PIN_SEL] mux. */
408 #else /* Word 0 - Little Endian */
409 uint64_t tx_oe : 1; /**< [ 0: 0](R/W) Transmit output enable. When set to 1, the GPIO pin can be driven as an output
410 pin if GPIO_BIT_CFG()[PIN_SEL] selects GPIO_PIN_SEL_E::GPIO_SW. [TX_OE] is only
411 used along with GPIO_TX_SET or GPIO_TX_CLR, and [TX_OE] function is before
412 GPIO_BIT_CFG()[PIN_SEL] mux. */
413 uint64_t pin_xor : 1; /**< [ 1: 1](R/W) GPIO data inversion. When set, inverts the receiving or transmitting GPIO signal.
414 For GPIO output, this inversion is after all GPIO [PIN_SEL] muxes. This inversion function
415 is applicable to any GPIO output mux signals, also used to control GPIO_RX_DAT.
416 For GPIO input, this inversion is before the GPIO [PIN_SEL] muxes, as used to control
417 GPIO interrupts. */
418 uint64_t int_en : 1; /**< [ 2: 2](R/W) Pin controls interrupt.
419
420 If set, assertions of this pin after [PIN_XOR] will set GPIO_INTR()[INTR].
421
422 If set and [INT_TYPE] is clear (level-sensitive), deassertions of this pin
423 after [PIN_XOR] will clear GPIO_INTR()[INTR].
424
425 This does NOT control if interrupts are enabled towards the MSI-X vector,
426 for that see GPIO_INTR()[INTR_ENA]. */
427 uint64_t int_type : 1; /**< [ 3: 3](R/W) Type of interrupt when pin is an input and [INT_EN] set. When set, rising edge
428 interrupt, else level interrupt. The GPIO signal used to generate interrupt is after
429 the filter and after the XOR inverter. */
430 uint64_t fil_cnt : 4; /**< [ 7: 4](R/W) Filter count. Specifies the number of consecutive samples ([FIL_CNT]+1) to change state.
431 Zero to disable the filter.
432 Filter and XOR inverter are also applicable to GPIO input muxing signals and interrupts. */
433 uint64_t fil_sel : 4; /**< [ 11: 8](R/W) Filter select. Global counter bit-select (controls sample rate).
434 Filter and XOR inverter are also applicable to GPIO input muxing signals and interrupts. */
435 uint64_t tx_od : 1; /**< [ 12: 12](R/W) GPIO output open-drain conversion. This function is after PIN_SEL MUX
436 and [PIN_XOR] inverter.
437 When set, the pin output will connect to zero, and pin enable
438 will connect to original pin output. With both [TX_OD] and [PIN_XOR] set, a transmit
439 of 1 will tristate the pin output driver to archive open-drain function. */
440 uint64_t blink_en : 2; /**< [ 14: 13](R/W) GPIO pin output blink filter enable. This function is after the [PIN_SEL]
441 multiplexing but before the [PIN_XOR] inverter and [TX_OD] overdriver
442 conversion. When blink filter is enabled, the pin output will generate blinking
443 pattern based on configuration of GPIO_BLINK_CFG.
444 0x0 = Disable blink filter.
445 0x1 = Enable blink filter based on the start of activity.
446 0x2 = Enable blink filter based on the end of activity, essentially based on
447 inversion of blink filter's input.
448 0x3 = Disable blink filter. */
449 uint64_t reserved_15 : 1;
450 uint64_t pin_sel : 11; /**< [ 26: 16](R/W) Selects which signal is reported to GPIO output, or which signal GPIO input need to
451 connect. Each GPIO pin can be configured either input-only or output-only depending
452 function selected, as enumerated by GPIO_PIN_SEL_E. For GPIO input selects,
453 the GPIO signal used is after glitch filter and XOR inverter (GPIO_BIT_CFG()[PIN_XOR]). */
454 uint64_t reserved_27_63 : 37;
455 #endif /* Word 0 - End */
456 } s;
457 struct bdk_gpio_bit_cfgx_cn9
458 {
459 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
460 uint64_t reserved_27_63 : 37;
461 uint64_t pin_sel : 11; /**< [ 26: 16](R/W) Selects which signal is reported to GPIO output, or which signal GPIO input need
462 to connect. Each GPIO pin can be configured either input-only, output only or
463 input/output depending on function selected, as enumerated by
464 GPIO_PIN_SEL_E. For GPIO input selects, the GPIO signal used is after glitch
465 filter and XOR inverter (GPIO_BIT_CFG()[PIN_XOR]). */
466 uint64_t reserved_15 : 1;
467 uint64_t blink_en : 2; /**< [ 14: 13](R/W) GPIO pin output blink filter enable. This function is after the [PIN_SEL]
468 multiplexing but before the [PIN_XOR] inverter and [TX_OD] overdriver
469 conversion. When blink filter is enabled, the pin output will generate blinking
470 pattern based on configuration of GPIO_BLINK_CFG.
471 0x0 = Disable blink filter.
472 0x1 = Enable blink filter based on the start of activity.
473 0x2 = Enable blink filter based on the end of activity, essentially based on
474 inversion of blink filter's input.
475 0x3 = Disable blink filter. */
476 uint64_t tx_od : 1; /**< [ 12: 12](R/W) GPIO output open-drain conversion. This function is after the [PIN_SEL]
477 multiplexing, [PIN_XOR] inverter, and [BLINK_EN] activity filter.
478 When set, the pin output will connect to zero, and pin enable
479 will connect to original pin output. With both [TX_OD] and [PIN_XOR] set, a transmit
480 of 1 will tristate the pin output driver to achieve open-drain function
481 with additional pullup on board. */
482 uint64_t fil_sel : 4; /**< [ 11: 8](R/W) Filter select. Global counter bit-select (controls sample rate).
483 Filter and XOR inverter are also applicable to GPIO input muxing signals and interrupts. */
484 uint64_t fil_cnt : 4; /**< [ 7: 4](R/W) Filter count. Specifies the number of consecutive samples ([FIL_CNT]+1) to change state.
485 Zero to disable the filter.
486 Filter and XOR inverter are also applicable to GPIO input muxing signals and interrupts. */
487 uint64_t int_type : 1; /**< [ 3: 3](R/W) Type of interrupt when pin is an input and [INT_EN] set. When set, rising edge
488 interrupt, else level interrupt. The GPIO signal used to generate interrupt is after
489 the filter and after the XOR inverter. */
490 uint64_t int_en : 1; /**< [ 2: 2](R/W) Pin controls interrupt.
491
492 If set, assertions of this pin after [PIN_XOR] will set GPIO_INTR()[INTR].
493
494 If set and [INT_TYPE] is clear (level-sensitive), deassertions of this pin
495 after [PIN_XOR] will clear GPIO_INTR()[INTR].
496
497 This does NOT control if interrupts are enabled towards the MSI-X vector,
498 for that see GPIO_INTR()[INTR_ENA_W1S]. */
499 uint64_t pin_xor : 1; /**< [ 1: 1](R/W) GPIO data inversion. When set, inverts the receiving or transmitting GPIO signal.
500 For GPIO output, this inversion is after all GPIO [PIN_SEL] muxes. This inversion function
501 is applicable to any GPIO output mux signals, also used to control GPIO_RX_DAT.
502 For GPIO input, this inversion is before the GPIO [PIN_SEL] muxes, as used to control
503 GPIO interrupts. */
504 uint64_t tx_oe : 1; /**< [ 0: 0](R/W) Transmit output enable. When set to 1, the GPIO pin can be driven as an output
505 pin if GPIO_BIT_CFG()[PIN_SEL] selects GPIO_PIN_SEL_E::GPIO_SW. [TX_OE] is only
506 used along with GPIO_TX_SET or GPIO_TX_CLR, and [TX_OE] function is before
507 GPIO_BIT_CFG()[PIN_SEL] mux. */
508 #else /* Word 0 - Little Endian */
509 uint64_t tx_oe : 1; /**< [ 0: 0](R/W) Transmit output enable. When set to 1, the GPIO pin can be driven as an output
510 pin if GPIO_BIT_CFG()[PIN_SEL] selects GPIO_PIN_SEL_E::GPIO_SW. [TX_OE] is only
511 used along with GPIO_TX_SET or GPIO_TX_CLR, and [TX_OE] function is before
512 GPIO_BIT_CFG()[PIN_SEL] mux. */
513 uint64_t pin_xor : 1; /**< [ 1: 1](R/W) GPIO data inversion. When set, inverts the receiving or transmitting GPIO signal.
514 For GPIO output, this inversion is after all GPIO [PIN_SEL] muxes. This inversion function
515 is applicable to any GPIO output mux signals, also used to control GPIO_RX_DAT.
516 For GPIO input, this inversion is before the GPIO [PIN_SEL] muxes, as used to control
517 GPIO interrupts. */
518 uint64_t int_en : 1; /**< [ 2: 2](R/W) Pin controls interrupt.
519
520 If set, assertions of this pin after [PIN_XOR] will set GPIO_INTR()[INTR].
521
522 If set and [INT_TYPE] is clear (level-sensitive), deassertions of this pin
523 after [PIN_XOR] will clear GPIO_INTR()[INTR].
524
525 This does NOT control if interrupts are enabled towards the MSI-X vector,
526 for that see GPIO_INTR()[INTR_ENA_W1S]. */
527 uint64_t int_type : 1; /**< [ 3: 3](R/W) Type of interrupt when pin is an input and [INT_EN] set. When set, rising edge
528 interrupt, else level interrupt. The GPIO signal used to generate interrupt is after
529 the filter and after the XOR inverter. */
530 uint64_t fil_cnt : 4; /**< [ 7: 4](R/W) Filter count. Specifies the number of consecutive samples ([FIL_CNT]+1) to change state.
531 Zero to disable the filter.
532 Filter and XOR inverter are also applicable to GPIO input muxing signals and interrupts. */
533 uint64_t fil_sel : 4; /**< [ 11: 8](R/W) Filter select. Global counter bit-select (controls sample rate).
534 Filter and XOR inverter are also applicable to GPIO input muxing signals and interrupts. */
535 uint64_t tx_od : 1; /**< [ 12: 12](R/W) GPIO output open-drain conversion. This function is after the [PIN_SEL]
536 multiplexing, [PIN_XOR] inverter, and [BLINK_EN] activity filter.
537 When set, the pin output will connect to zero, and pin enable
538 will connect to original pin output. With both [TX_OD] and [PIN_XOR] set, a transmit
539 of 1 will tristate the pin output driver to achieve open-drain function
540 with additional pullup on board. */
541 uint64_t blink_en : 2; /**< [ 14: 13](R/W) GPIO pin output blink filter enable. This function is after the [PIN_SEL]
542 multiplexing but before the [PIN_XOR] inverter and [TX_OD] overdriver
543 conversion. When blink filter is enabled, the pin output will generate blinking
544 pattern based on configuration of GPIO_BLINK_CFG.
545 0x0 = Disable blink filter.
546 0x1 = Enable blink filter based on the start of activity.
547 0x2 = Enable blink filter based on the end of activity, essentially based on
548 inversion of blink filter's input.
549 0x3 = Disable blink filter. */
550 uint64_t reserved_15 : 1;
551 uint64_t pin_sel : 11; /**< [ 26: 16](R/W) Selects which signal is reported to GPIO output, or which signal GPIO input need
552 to connect. Each GPIO pin can be configured either input-only, output only or
553 input/output depending on function selected, as enumerated by
554 GPIO_PIN_SEL_E. For GPIO input selects, the GPIO signal used is after glitch
555 filter and XOR inverter (GPIO_BIT_CFG()[PIN_XOR]). */
556 uint64_t reserved_27_63 : 37;
557 #endif /* Word 0 - End */
558 } cn9;
559 struct bdk_gpio_bit_cfgx_cn81xx
560 {
561 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
562 uint64_t reserved_26_63 : 38;
563 uint64_t pin_sel : 10; /**< [ 25: 16](R/W) Selects which signal is reported to GPIO output, or which signal GPIO input need to
564 connect. Each GPIO pin can be configured either input-only or output-only depending
565 function selected, as enumerated by GPIO_PIN_SEL_E. For GPIO input selects,
566 the GPIO signal used is after glitch filter and XOR inverter (GPIO_BIT_CFG()[PIN_XOR]). */
567 uint64_t reserved_13_15 : 3;
568 uint64_t tx_od : 1; /**< [ 12: 12](R/W) GPIO output open-drain conversion. This function is after PIN_SEL MUX
569 and [PIN_XOR] inverter.
570 When set, the pin output will connect to zero, and pin enable
571 will connect to original pin output. With both [TX_OD] and [PIN_XOR] set, a transmit
572 of 1 will tristate the pin output driver to archive open-drain function. */
573 uint64_t fil_sel : 4; /**< [ 11: 8](R/W) Filter select. Global counter bit-select (controls sample rate).
574 Filter and XOR inverter are also applicable to GPIO input muxing signals and interrupts. */
575 uint64_t fil_cnt : 4; /**< [ 7: 4](R/W) Filter count. Specifies the number of consecutive samples ([FIL_CNT]+1) to change state.
576 Zero to disable the filter.
577 Filter and XOR inverter are also applicable to GPIO input muxing signals and interrupts. */
578 uint64_t int_type : 1; /**< [ 3: 3](R/W) Type of interrupt when pin is an input and [INT_EN] set. When set, rising edge
579 interrupt, else level interrupt. The GPIO signal used to generate interrupt is after
580 the filter and after the XOR inverter. */
581 uint64_t int_en : 1; /**< [ 2: 2](R/W) Pin controls interrupt.
582
583 If set, assertions of this pin after [PIN_XOR] will set GPIO_INTR()[INTR].
584
585 If set and [INT_TYPE] is clear (level-sensitive), deassertions of this pin
586 after [PIN_XOR] will clear GPIO_INTR()[INTR].
587
588 This does NOT control if interrupts are enabled towards the MSI-X vector,
589 for that see GPIO_INTR()[INTR_ENA]. */
590 uint64_t pin_xor : 1; /**< [ 1: 1](R/W) GPIO data inversion. When set, inverts the receiving or transmitting GPIO signal.
591 For GPIO output, this inversion is after all GPIO [PIN_SEL] muxes. This inversion function
592 is applicable to any GPIO output mux signals, also used to control GPIO_RX_DAT.
593 For GPIO input, this inversion is before the GPIO [PIN_SEL] muxes, as used to control
594 GPIO interrupts. */
595 uint64_t tx_oe : 1; /**< [ 0: 0](R/W) Transmit output enable. When set to 1, the GPIO pin can be driven as an output
596 pin if GPIO_BIT_CFG()[PIN_SEL] selects GPIO_PIN_SEL_E::GPIO_SW. [TX_OE] is only
597 used along with GPIO_TX_SET or GPIO_TX_CLR, and [TX_OE] function is before
598 GPIO_BIT_CFG()[PIN_SEL] mux. */
599 #else /* Word 0 - Little Endian */
600 uint64_t tx_oe : 1; /**< [ 0: 0](R/W) Transmit output enable. When set to 1, the GPIO pin can be driven as an output
601 pin if GPIO_BIT_CFG()[PIN_SEL] selects GPIO_PIN_SEL_E::GPIO_SW. [TX_OE] is only
602 used along with GPIO_TX_SET or GPIO_TX_CLR, and [TX_OE] function is before
603 GPIO_BIT_CFG()[PIN_SEL] mux. */
604 uint64_t pin_xor : 1; /**< [ 1: 1](R/W) GPIO data inversion. When set, inverts the receiving or transmitting GPIO signal.
605 For GPIO output, this inversion is after all GPIO [PIN_SEL] muxes. This inversion function
606 is applicable to any GPIO output mux signals, also used to control GPIO_RX_DAT.
607 For GPIO input, this inversion is before the GPIO [PIN_SEL] muxes, as used to control
608 GPIO interrupts. */
609 uint64_t int_en : 1; /**< [ 2: 2](R/W) Pin controls interrupt.
610
611 If set, assertions of this pin after [PIN_XOR] will set GPIO_INTR()[INTR].
612
613 If set and [INT_TYPE] is clear (level-sensitive), deassertions of this pin
614 after [PIN_XOR] will clear GPIO_INTR()[INTR].
615
616 This does NOT control if interrupts are enabled towards the MSI-X vector,
617 for that see GPIO_INTR()[INTR_ENA]. */
618 uint64_t int_type : 1; /**< [ 3: 3](R/W) Type of interrupt when pin is an input and [INT_EN] set. When set, rising edge
619 interrupt, else level interrupt. The GPIO signal used to generate interrupt is after
620 the filter and after the XOR inverter. */
621 uint64_t fil_cnt : 4; /**< [ 7: 4](R/W) Filter count. Specifies the number of consecutive samples ([FIL_CNT]+1) to change state.
622 Zero to disable the filter.
623 Filter and XOR inverter are also applicable to GPIO input muxing signals and interrupts. */
624 uint64_t fil_sel : 4; /**< [ 11: 8](R/W) Filter select. Global counter bit-select (controls sample rate).
625 Filter and XOR inverter are also applicable to GPIO input muxing signals and interrupts. */
626 uint64_t tx_od : 1; /**< [ 12: 12](R/W) GPIO output open-drain conversion. This function is after PIN_SEL MUX
627 and [PIN_XOR] inverter.
628 When set, the pin output will connect to zero, and pin enable
629 will connect to original pin output. With both [TX_OD] and [PIN_XOR] set, a transmit
630 of 1 will tristate the pin output driver to archive open-drain function. */
631 uint64_t reserved_13_15 : 3;
632 uint64_t pin_sel : 10; /**< [ 25: 16](R/W) Selects which signal is reported to GPIO output, or which signal GPIO input need to
633 connect. Each GPIO pin can be configured either input-only or output-only depending
634 function selected, as enumerated by GPIO_PIN_SEL_E. For GPIO input selects,
635 the GPIO signal used is after glitch filter and XOR inverter (GPIO_BIT_CFG()[PIN_XOR]). */
636 uint64_t reserved_26_63 : 38;
637 #endif /* Word 0 - End */
638 } cn81xx;
639 struct bdk_gpio_bit_cfgx_cn88xx
640 {
641 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
642 uint64_t reserved_24_63 : 40;
643 uint64_t pin_sel : 8; /**< [ 23: 16](R/W) Selects which signal is reported to GPIO output, or which signal GPIO input need to
644 connect. Each GPIO pin can be configured either input-only or output-only depending
645 function selected, as enumerated by GPIO_PIN_SEL_E. For GPIO input selects,
646 the GPIO signal used is after glitch filter and XOR inverter (GPIO_BIT_CFG()[PIN_XOR]). */
647 uint64_t reserved_13_15 : 3;
648 uint64_t tx_od : 1; /**< [ 12: 12](R/W) GPIO output open-drain conversion. This function is after PIN_SEL MUX
649 and [PIN_XOR] inverter.
650 When set, the pin output will connect to zero, and pin enable
651 will connect to original pin output. With both [TX_OD] and [PIN_XOR] set, a transmit
652 of 1 will tristate the pin output driver to archive open-drain function. */
653 uint64_t fil_sel : 4; /**< [ 11: 8](R/W) Filter select. Global counter bit-select (controls sample rate).
654 Filter and XOR inverter are also applicable to GPIO input muxing signals and interrupts. */
655 uint64_t fil_cnt : 4; /**< [ 7: 4](R/W) Filter count. Specifies the number of consecutive samples ([FIL_CNT]+1) to change state.
656 Zero to disable the filter.
657 Filter and XOR inverter are also applicable to GPIO input muxing signals and interrupts. */
658 uint64_t int_type : 1; /**< [ 3: 3](R/W) Type of interrupt when pin is an input and [INT_EN] set. When set, rising edge
659 interrupt, else level interrupt. The GPIO signal used to generate interrupt is after
660 the filter and after the XOR inverter. */
661 uint64_t int_en : 1; /**< [ 2: 2](R/W) Pin controls interrupt.
662
663 If set, assertions of this pin after [PIN_XOR] will set GPIO_INTR()[INTR].
664
665 If set and [INT_TYPE] is clear (level-sensitive), deassertions of this pin
666 after [PIN_XOR] will clear GPIO_INTR()[INTR].
667
668 This does NOT control if interrupts are enabled towards the MSI-X vector,
669 for that see GPIO_INTR()[INTR_ENA]. */
670 uint64_t pin_xor : 1; /**< [ 1: 1](R/W) GPIO data inversion. When set, inverts the receiving or transmitting GPIO signal.
671 For GPIO output, this inversion is after all GPIO [PIN_SEL] muxes. This inversion function
672 is applicable to any GPIO output mux signals, also used to control GPIO_RX_DAT.
673 For GPIO input, this inversion is before the GPIO [PIN_SEL] muxes, as used to control
674 GPIO interrupts. */
675 uint64_t tx_oe : 1; /**< [ 0: 0](R/W) Transmit output enable. When set to 1, the GPIO pin can be driven as an output
676 pin if GPIO_BIT_CFG()[PIN_SEL] selects GPIO_PIN_SEL_E::GPIO_SW. [TX_OE] is only
677 used along with GPIO_TX_SET or GPIO_TX_CLR, and [TX_OE] function is before
678 GPIO_BIT_CFG()[PIN_SEL] mux. */
679 #else /* Word 0 - Little Endian */
680 uint64_t tx_oe : 1; /**< [ 0: 0](R/W) Transmit output enable. When set to 1, the GPIO pin can be driven as an output
681 pin if GPIO_BIT_CFG()[PIN_SEL] selects GPIO_PIN_SEL_E::GPIO_SW. [TX_OE] is only
682 used along with GPIO_TX_SET or GPIO_TX_CLR, and [TX_OE] function is before
683 GPIO_BIT_CFG()[PIN_SEL] mux. */
684 uint64_t pin_xor : 1; /**< [ 1: 1](R/W) GPIO data inversion. When set, inverts the receiving or transmitting GPIO signal.
685 For GPIO output, this inversion is after all GPIO [PIN_SEL] muxes. This inversion function
686 is applicable to any GPIO output mux signals, also used to control GPIO_RX_DAT.
687 For GPIO input, this inversion is before the GPIO [PIN_SEL] muxes, as used to control
688 GPIO interrupts. */
689 uint64_t int_en : 1; /**< [ 2: 2](R/W) Pin controls interrupt.
690
691 If set, assertions of this pin after [PIN_XOR] will set GPIO_INTR()[INTR].
692
693 If set and [INT_TYPE] is clear (level-sensitive), deassertions of this pin
694 after [PIN_XOR] will clear GPIO_INTR()[INTR].
695
696 This does NOT control if interrupts are enabled towards the MSI-X vector,
697 for that see GPIO_INTR()[INTR_ENA]. */
698 uint64_t int_type : 1; /**< [ 3: 3](R/W) Type of interrupt when pin is an input and [INT_EN] set. When set, rising edge
699 interrupt, else level interrupt. The GPIO signal used to generate interrupt is after
700 the filter and after the XOR inverter. */
701 uint64_t fil_cnt : 4; /**< [ 7: 4](R/W) Filter count. Specifies the number of consecutive samples ([FIL_CNT]+1) to change state.
702 Zero to disable the filter.
703 Filter and XOR inverter are also applicable to GPIO input muxing signals and interrupts. */
704 uint64_t fil_sel : 4; /**< [ 11: 8](R/W) Filter select. Global counter bit-select (controls sample rate).
705 Filter and XOR inverter are also applicable to GPIO input muxing signals and interrupts. */
706 uint64_t tx_od : 1; /**< [ 12: 12](R/W) GPIO output open-drain conversion. This function is after PIN_SEL MUX
707 and [PIN_XOR] inverter.
708 When set, the pin output will connect to zero, and pin enable
709 will connect to original pin output. With both [TX_OD] and [PIN_XOR] set, a transmit
710 of 1 will tristate the pin output driver to archive open-drain function. */
711 uint64_t reserved_13_15 : 3;
712 uint64_t pin_sel : 8; /**< [ 23: 16](R/W) Selects which signal is reported to GPIO output, or which signal GPIO input need to
713 connect. Each GPIO pin can be configured either input-only or output-only depending
714 function selected, as enumerated by GPIO_PIN_SEL_E. For GPIO input selects,
715 the GPIO signal used is after glitch filter and XOR inverter (GPIO_BIT_CFG()[PIN_XOR]). */
716 uint64_t reserved_24_63 : 40;
717 #endif /* Word 0 - End */
718 } cn88xx;
719 /* struct bdk_gpio_bit_cfgx_cn81xx cn83xx; */
720 };
721 typedef union bdk_gpio_bit_cfgx bdk_gpio_bit_cfgx_t;
722
723 static inline uint64_t BDK_GPIO_BIT_CFGX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GPIO_BIT_CFGX(unsigned long a)724 static inline uint64_t BDK_GPIO_BIT_CFGX(unsigned long a)
725 {
726 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=47))
727 return 0x803000000400ll + 8ll * ((a) & 0x3f);
728 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=79))
729 return 0x803000000400ll + 8ll * ((a) & 0x7f);
730 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=50))
731 return 0x803000000400ll + 8ll * ((a) & 0x3f);
732 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=63))
733 return 0x803000000400ll + 8ll * ((a) & 0x3f);
734 __bdk_csr_fatal("GPIO_BIT_CFGX", 1, a, 0, 0, 0);
735 }
736
737 #define typedef_BDK_GPIO_BIT_CFGX(a) bdk_gpio_bit_cfgx_t
738 #define bustype_BDK_GPIO_BIT_CFGX(a) BDK_CSR_TYPE_NCB
739 #define basename_BDK_GPIO_BIT_CFGX(a) "GPIO_BIT_CFGX"
740 #define device_bar_BDK_GPIO_BIT_CFGX(a) 0x0 /* PF_BAR0 */
741 #define busnum_BDK_GPIO_BIT_CFGX(a) (a)
742 #define arguments_BDK_GPIO_BIT_CFGX(a) (a),-1,-1,-1
743
744 /**
745 * Register (NCB) gpio_bit_permit#
746 *
747 * GPIO Bit Permit Register
748 * This register determines which requestor(s) are permitted to access which GPIO pins.
749 *
750 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
751 * (That is, only the GPIO_PERMIT permitted agent can change the permission settings of
752 * all requestors.)
753 *
754 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
755 */
756 union bdk_gpio_bit_permitx
757 {
758 uint64_t u;
759 struct bdk_gpio_bit_permitx_s
760 {
761 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
762 uint64_t reserved_4_63 : 60;
763 uint64_t permitdis : 4; /**< [ 3: 0](R/W) Each bit, if set, disables the given requestor from accessing the corresponding pin.
764 If a disabled requestor makes a request, the access becomes read-zero/write ignored.
765 \<0\> = Disable APs (non MCP/SCP) secure world from accessing the pin.
766 \<1\> = Disable APs (non MCP/SCP) nonsecure world from accessing the pin.
767 \<2\> = Disable XCP0 (SCP) from accessing the pin.
768 \<3\> = Disable XCP1 (MCP) from accessing the pin. */
769 #else /* Word 0 - Little Endian */
770 uint64_t permitdis : 4; /**< [ 3: 0](R/W) Each bit, if set, disables the given requestor from accessing the corresponding pin.
771 If a disabled requestor makes a request, the access becomes read-zero/write ignored.
772 \<0\> = Disable APs (non MCP/SCP) secure world from accessing the pin.
773 \<1\> = Disable APs (non MCP/SCP) nonsecure world from accessing the pin.
774 \<2\> = Disable XCP0 (SCP) from accessing the pin.
775 \<3\> = Disable XCP1 (MCP) from accessing the pin. */
776 uint64_t reserved_4_63 : 60;
777 #endif /* Word 0 - End */
778 } s;
779 /* struct bdk_gpio_bit_permitx_s cn; */
780 };
781 typedef union bdk_gpio_bit_permitx bdk_gpio_bit_permitx_t;
782
783 static inline uint64_t BDK_GPIO_BIT_PERMITX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GPIO_BIT_PERMITX(unsigned long a)784 static inline uint64_t BDK_GPIO_BIT_PERMITX(unsigned long a)
785 {
786 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=63))
787 return 0x803000002000ll + 8ll * ((a) & 0x3f);
788 __bdk_csr_fatal("GPIO_BIT_PERMITX", 1, a, 0, 0, 0);
789 }
790
791 #define typedef_BDK_GPIO_BIT_PERMITX(a) bdk_gpio_bit_permitx_t
792 #define bustype_BDK_GPIO_BIT_PERMITX(a) BDK_CSR_TYPE_NCB
793 #define basename_BDK_GPIO_BIT_PERMITX(a) "GPIO_BIT_PERMITX"
794 #define device_bar_BDK_GPIO_BIT_PERMITX(a) 0x0 /* PF_BAR0 */
795 #define busnum_BDK_GPIO_BIT_PERMITX(a) (a)
796 #define arguments_BDK_GPIO_BIT_PERMITX(a) (a),-1,-1,-1
797
798 /**
799 * Register (NCB) gpio_blink_cfg
800 *
801 * GPIO Output Blinker Configuration Register
802 * This register configures the blink generator.
803 *
804 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
805 *
806 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
807 */
808 union bdk_gpio_blink_cfg
809 {
810 uint64_t u;
811 struct bdk_gpio_blink_cfg_s
812 {
813 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
814 uint64_t reserved_16_63 : 48;
815 uint64_t force_off : 4; /**< [ 15: 12](R/W) Force activity off time. The minimum amount of time to disable the activity indicator if
816 it has been continually enabled for the [MAX_ON] time.
817 0x0 = No minimum.
818 0x1 = 1/8 second.
819 ...
820 0xF = 15/8 seconds. */
821 uint64_t max_on : 4; /**< [ 11: 8](R/W) Maximum activity on time. The maximum amount of time to enable the activity indicator.
822 0x0 = No maximum.
823 0x1 = 1/4 second.
824 ...
825 0xF = 15/4 seconds. */
826 uint64_t stretch_off : 4; /**< [ 7: 4](R/W) Stretch activity off. The minimum amount of time to disable the activity indicator.
827 0x0 = No minimum.
828 0x1 = 1/64 second.
829 ...
830 0xF = 15/64 seconds. */
831 uint64_t stretch_on : 4; /**< [ 3: 0](R/W) Stretch activity on. The minimum amount of time to enable the activity indicator.
832 0x0 = 1/64 second.
833 0x1 = 2/64 second.
834 ...
835 0xF = 16/64 seconds. */
836 #else /* Word 0 - Little Endian */
837 uint64_t stretch_on : 4; /**< [ 3: 0](R/W) Stretch activity on. The minimum amount of time to enable the activity indicator.
838 0x0 = 1/64 second.
839 0x1 = 2/64 second.
840 ...
841 0xF = 16/64 seconds. */
842 uint64_t stretch_off : 4; /**< [ 7: 4](R/W) Stretch activity off. The minimum amount of time to disable the activity indicator.
843 0x0 = No minimum.
844 0x1 = 1/64 second.
845 ...
846 0xF = 15/64 seconds. */
847 uint64_t max_on : 4; /**< [ 11: 8](R/W) Maximum activity on time. The maximum amount of time to enable the activity indicator.
848 0x0 = No maximum.
849 0x1 = 1/4 second.
850 ...
851 0xF = 15/4 seconds. */
852 uint64_t force_off : 4; /**< [ 15: 12](R/W) Force activity off time. The minimum amount of time to disable the activity indicator if
853 it has been continually enabled for the [MAX_ON] time.
854 0x0 = No minimum.
855 0x1 = 1/8 second.
856 ...
857 0xF = 15/8 seconds. */
858 uint64_t reserved_16_63 : 48;
859 #endif /* Word 0 - End */
860 } s;
861 /* struct bdk_gpio_blink_cfg_s cn; */
862 };
863 typedef union bdk_gpio_blink_cfg bdk_gpio_blink_cfg_t;
864
865 #define BDK_GPIO_BLINK_CFG BDK_GPIO_BLINK_CFG_FUNC()
866 static inline uint64_t BDK_GPIO_BLINK_CFG_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_BLINK_CFG_FUNC(void)867 static inline uint64_t BDK_GPIO_BLINK_CFG_FUNC(void)
868 {
869 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
870 return 0x803000001440ll;
871 __bdk_csr_fatal("GPIO_BLINK_CFG", 0, 0, 0, 0, 0);
872 }
873
874 #define typedef_BDK_GPIO_BLINK_CFG bdk_gpio_blink_cfg_t
875 #define bustype_BDK_GPIO_BLINK_CFG BDK_CSR_TYPE_NCB
876 #define basename_BDK_GPIO_BLINK_CFG "GPIO_BLINK_CFG"
877 #define device_bar_BDK_GPIO_BLINK_CFG 0x0 /* PF_BAR0 */
878 #define busnum_BDK_GPIO_BLINK_CFG 0
879 #define arguments_BDK_GPIO_BLINK_CFG -1,-1,-1,-1
880
881 /**
882 * Register (NCB) gpio_blink_freq
883 *
884 * GPIO Blink Clock Register
885 * This register configures the blink generator.
886 *
887 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
888 *
889 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
890 */
891 union bdk_gpio_blink_freq
892 {
893 uint64_t u;
894 struct bdk_gpio_blink_freq_s
895 {
896 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
897 uint64_t reserved_27_63 : 37;
898 uint64_t div : 27; /**< [ 26: 0](R/W) Number of 100 MHz reference clocks in 1/64th of a second. */
899 #else /* Word 0 - Little Endian */
900 uint64_t div : 27; /**< [ 26: 0](R/W) Number of 100 MHz reference clocks in 1/64th of a second. */
901 uint64_t reserved_27_63 : 37;
902 #endif /* Word 0 - End */
903 } s;
904 /* struct bdk_gpio_blink_freq_s cn; */
905 };
906 typedef union bdk_gpio_blink_freq bdk_gpio_blink_freq_t;
907
908 #define BDK_GPIO_BLINK_FREQ BDK_GPIO_BLINK_FREQ_FUNC()
909 static inline uint64_t BDK_GPIO_BLINK_FREQ_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_BLINK_FREQ_FUNC(void)910 static inline uint64_t BDK_GPIO_BLINK_FREQ_FUNC(void)
911 {
912 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
913 return 0x803000001448ll;
914 __bdk_csr_fatal("GPIO_BLINK_FREQ", 0, 0, 0, 0, 0);
915 }
916
917 #define typedef_BDK_GPIO_BLINK_FREQ bdk_gpio_blink_freq_t
918 #define bustype_BDK_GPIO_BLINK_FREQ BDK_CSR_TYPE_NCB
919 #define basename_BDK_GPIO_BLINK_FREQ "GPIO_BLINK_FREQ"
920 #define device_bar_BDK_GPIO_BLINK_FREQ 0x0 /* PF_BAR0 */
921 #define busnum_BDK_GPIO_BLINK_FREQ 0
922 #define arguments_BDK_GPIO_BLINK_FREQ -1,-1,-1,-1
923
924 /**
925 * Register (NCB) gpio_cer_err_w1c
926 *
927 * GPIO Central Error Write-One-to-Clear Register
928 * Internal:
929 * FIXME algorithm int_w1c.
930 */
931 union bdk_gpio_cer_err_w1c
932 {
933 uint64_t u;
934 struct bdk_gpio_cer_err_w1c_s
935 {
936 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
937 uint64_t reserved_4_63 : 60;
938 uint64_t caterr : 1; /**< [ 3: 3](R/W1S) Set the selectable-GPIO GPIO_PIN_SEL_E::CER_CATERR output, to indicate a
939 catastrophic error to the BMC. */
940 uint64_t err2 : 1; /**< [ 2: 2](R/W1S) Set the selectable-GPIO GPIO_PIN_SEL_E::CER_ERR2 output, to indicate an error to the BMC. */
941 uint64_t err1 : 1; /**< [ 1: 1](R/W1S) Set the selectable-GPIO GPIO_PIN_SEL_E::CER_ERR1 output, to indicate an error to the BMC. */
942 uint64_t err0 : 1; /**< [ 0: 0](R/W1S) Set the selectable-GPIO GPIO_PIN_SEL_E::CER_ERR0 GPIO output, to indicate an error to the BMC. */
943 #else /* Word 0 - Little Endian */
944 uint64_t err0 : 1; /**< [ 0: 0](R/W1S) Set the selectable-GPIO GPIO_PIN_SEL_E::CER_ERR0 GPIO output, to indicate an error to the BMC. */
945 uint64_t err1 : 1; /**< [ 1: 1](R/W1S) Set the selectable-GPIO GPIO_PIN_SEL_E::CER_ERR1 output, to indicate an error to the BMC. */
946 uint64_t err2 : 1; /**< [ 2: 2](R/W1S) Set the selectable-GPIO GPIO_PIN_SEL_E::CER_ERR2 output, to indicate an error to the BMC. */
947 uint64_t caterr : 1; /**< [ 3: 3](R/W1S) Set the selectable-GPIO GPIO_PIN_SEL_E::CER_CATERR output, to indicate a
948 catastrophic error to the BMC. */
949 uint64_t reserved_4_63 : 60;
950 #endif /* Word 0 - End */
951 } s;
952 /* struct bdk_gpio_cer_err_w1c_s cn; */
953 };
954 typedef union bdk_gpio_cer_err_w1c bdk_gpio_cer_err_w1c_t;
955
956 #define BDK_GPIO_CER_ERR_W1C BDK_GPIO_CER_ERR_W1C_FUNC()
957 static inline uint64_t BDK_GPIO_CER_ERR_W1C_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_CER_ERR_W1C_FUNC(void)958 static inline uint64_t BDK_GPIO_CER_ERR_W1C_FUNC(void)
959 {
960 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
961 return 0x803000001608ll;
962 __bdk_csr_fatal("GPIO_CER_ERR_W1C", 0, 0, 0, 0, 0);
963 }
964
965 #define typedef_BDK_GPIO_CER_ERR_W1C bdk_gpio_cer_err_w1c_t
966 #define bustype_BDK_GPIO_CER_ERR_W1C BDK_CSR_TYPE_NCB
967 #define basename_BDK_GPIO_CER_ERR_W1C "GPIO_CER_ERR_W1C"
968 #define device_bar_BDK_GPIO_CER_ERR_W1C 0x0 /* PF_BAR0 */
969 #define busnum_BDK_GPIO_CER_ERR_W1C 0
970 #define arguments_BDK_GPIO_CER_ERR_W1C -1,-1,-1,-1
971
972 /**
973 * Register (NCB) gpio_cer_err_w1s
974 *
975 * GPIO Central Error Write-One-to-Set Register
976 * This register report CER Errors to GPIO pins, TBD.
977 *
978 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
979 */
980 union bdk_gpio_cer_err_w1s
981 {
982 uint64_t u;
983 struct bdk_gpio_cer_err_w1s_s
984 {
985 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
986 uint64_t reserved_4_63 : 60;
987 uint64_t caterr : 1; /**< [ 3: 3](R/W1S) Set the selectable-GPIO GPIO_PIN_SEL_E::CER_CATERR output, to indicate a
988 catastrophic error to the BMC. */
989 uint64_t err2 : 1; /**< [ 2: 2](R/W1S) Set the selectable-GPIO GPIO_PIN_SEL_E::CER_ERR2 output, to indicate an error to the BMC. */
990 uint64_t err1 : 1; /**< [ 1: 1](R/W1S) Set the selectable-GPIO GPIO_PIN_SEL_E::CER_ERR1 output, to indicate an error to the BMC. */
991 uint64_t err0 : 1; /**< [ 0: 0](R/W1S) Set the selectable-GPIO GPIO_PIN_SEL_E::CER_ERR0 GPIO output, to indicate an error to the BMC. */
992 #else /* Word 0 - Little Endian */
993 uint64_t err0 : 1; /**< [ 0: 0](R/W1S) Set the selectable-GPIO GPIO_PIN_SEL_E::CER_ERR0 GPIO output, to indicate an error to the BMC. */
994 uint64_t err1 : 1; /**< [ 1: 1](R/W1S) Set the selectable-GPIO GPIO_PIN_SEL_E::CER_ERR1 output, to indicate an error to the BMC. */
995 uint64_t err2 : 1; /**< [ 2: 2](R/W1S) Set the selectable-GPIO GPIO_PIN_SEL_E::CER_ERR2 output, to indicate an error to the BMC. */
996 uint64_t caterr : 1; /**< [ 3: 3](R/W1S) Set the selectable-GPIO GPIO_PIN_SEL_E::CER_CATERR output, to indicate a
997 catastrophic error to the BMC. */
998 uint64_t reserved_4_63 : 60;
999 #endif /* Word 0 - End */
1000 } s;
1001 /* struct bdk_gpio_cer_err_w1s_s cn; */
1002 };
1003 typedef union bdk_gpio_cer_err_w1s bdk_gpio_cer_err_w1s_t;
1004
1005 #define BDK_GPIO_CER_ERR_W1S BDK_GPIO_CER_ERR_W1S_FUNC()
1006 static inline uint64_t BDK_GPIO_CER_ERR_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_CER_ERR_W1S_FUNC(void)1007 static inline uint64_t BDK_GPIO_CER_ERR_W1S_FUNC(void)
1008 {
1009 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1010 return 0x803000001600ll;
1011 __bdk_csr_fatal("GPIO_CER_ERR_W1S", 0, 0, 0, 0, 0);
1012 }
1013
1014 #define typedef_BDK_GPIO_CER_ERR_W1S bdk_gpio_cer_err_w1s_t
1015 #define bustype_BDK_GPIO_CER_ERR_W1S BDK_CSR_TYPE_NCB
1016 #define basename_BDK_GPIO_CER_ERR_W1S "GPIO_CER_ERR_W1S"
1017 #define device_bar_BDK_GPIO_CER_ERR_W1S 0x0 /* PF_BAR0 */
1018 #define busnum_BDK_GPIO_CER_ERR_W1S 0
1019 #define arguments_BDK_GPIO_CER_ERR_W1S -1,-1,-1,-1
1020
1021 /**
1022 * Register (NCB) gpio_clk_gen#
1023 *
1024 * GPIO Clock Generator Registers
1025 * This register configures the clock generators. The number of generators is
1026 * discoverable in GPIO_CONST[CLKGEN].
1027 *
1028 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
1029 *
1030 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1031 */
1032 union bdk_gpio_clk_genx
1033 {
1034 uint64_t u;
1035 struct bdk_gpio_clk_genx_s
1036 {
1037 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1038 uint64_t high : 32; /**< [ 63: 32](R/W) Determines the high period of the GPIO clock generator. [HIGH] defines the
1039 number of coprocessor clocks in GPIO clock high period. Writing [HIGH] = 0
1040 changes clock generator back original 50% duty cycle, which is backward
1041 compatible. */
1042 uint64_t n : 32; /**< [ 31: 0](R/W) Determines the frequency of the GPIO clock generator. N should be less than or equal to
1043 2^31-1.
1044 The frequency of the GPIO clock generator equals the coprocessor-clock frequency times N
1045 divided by 2^32.
1046 Writing N = 0x0 stops the clock generator. */
1047 #else /* Word 0 - Little Endian */
1048 uint64_t n : 32; /**< [ 31: 0](R/W) Determines the frequency of the GPIO clock generator. N should be less than or equal to
1049 2^31-1.
1050 The frequency of the GPIO clock generator equals the coprocessor-clock frequency times N
1051 divided by 2^32.
1052 Writing N = 0x0 stops the clock generator. */
1053 uint64_t high : 32; /**< [ 63: 32](R/W) Determines the high period of the GPIO clock generator. [HIGH] defines the
1054 number of coprocessor clocks in GPIO clock high period. Writing [HIGH] = 0
1055 changes clock generator back original 50% duty cycle, which is backward
1056 compatible. */
1057 #endif /* Word 0 - End */
1058 } s;
1059 struct bdk_gpio_clk_genx_cn8
1060 {
1061 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1062 uint64_t reserved_32_63 : 32;
1063 uint64_t n : 32; /**< [ 31: 0](R/W) Determines the frequency of the GPIO clock generator. N should be less than or equal to
1064 2^31-1.
1065 The frequency of the GPIO clock generator equals the coprocessor-clock frequency times N
1066 divided by 2^32.
1067 Writing N = 0x0 stops the clock generator. */
1068 #else /* Word 0 - Little Endian */
1069 uint64_t n : 32; /**< [ 31: 0](R/W) Determines the frequency of the GPIO clock generator. N should be less than or equal to
1070 2^31-1.
1071 The frequency of the GPIO clock generator equals the coprocessor-clock frequency times N
1072 divided by 2^32.
1073 Writing N = 0x0 stops the clock generator. */
1074 uint64_t reserved_32_63 : 32;
1075 #endif /* Word 0 - End */
1076 } cn8;
1077 struct bdk_gpio_clk_genx_cn9
1078 {
1079 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1080 uint64_t high : 32; /**< [ 63: 32](R/W) Determines the high period of the GPIO clock generator. [HIGH] defines the
1081 number of coprocessor clocks in GPIO clock high period. Writing [HIGH] = 0
1082 changes clock generator back original 50% duty cycle, which is backward
1083 compatible. */
1084 uint64_t n : 32; /**< [ 31: 0](R/W) Determines the frequency of the GPIO clock generator. [N] should be less than or
1085 equal to 2^31-1. The frequency of the GPIO clock generator equals the
1086 coprocessor-clock frequency times [N] divided by 2^32. Writing [N] = 0x0 stops
1087 the clock generator. */
1088 #else /* Word 0 - Little Endian */
1089 uint64_t n : 32; /**< [ 31: 0](R/W) Determines the frequency of the GPIO clock generator. [N] should be less than or
1090 equal to 2^31-1. The frequency of the GPIO clock generator equals the
1091 coprocessor-clock frequency times [N] divided by 2^32. Writing [N] = 0x0 stops
1092 the clock generator. */
1093 uint64_t high : 32; /**< [ 63: 32](R/W) Determines the high period of the GPIO clock generator. [HIGH] defines the
1094 number of coprocessor clocks in GPIO clock high period. Writing [HIGH] = 0
1095 changes clock generator back original 50% duty cycle, which is backward
1096 compatible. */
1097 #endif /* Word 0 - End */
1098 } cn9;
1099 };
1100 typedef union bdk_gpio_clk_genx bdk_gpio_clk_genx_t;
1101
1102 static inline uint64_t BDK_GPIO_CLK_GENX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GPIO_CLK_GENX(unsigned long a)1103 static inline uint64_t BDK_GPIO_CLK_GENX(unsigned long a)
1104 {
1105 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX) && (a<=3))
1106 return 0x803000000040ll + 8ll * ((a) & 0x3);
1107 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=7))
1108 return 0x803000001800ll + 8ll * ((a) & 0x7);
1109 __bdk_csr_fatal("GPIO_CLK_GENX", 1, a, 0, 0, 0);
1110 }
1111
1112 #define typedef_BDK_GPIO_CLK_GENX(a) bdk_gpio_clk_genx_t
1113 #define bustype_BDK_GPIO_CLK_GENX(a) BDK_CSR_TYPE_NCB
1114 #define basename_BDK_GPIO_CLK_GENX(a) "GPIO_CLK_GENX"
1115 #define device_bar_BDK_GPIO_CLK_GENX(a) 0x0 /* PF_BAR0 */
1116 #define busnum_BDK_GPIO_CLK_GENX(a) (a)
1117 #define arguments_BDK_GPIO_CLK_GENX(a) (a),-1,-1,-1
1118
1119 /**
1120 * Register (NCB) gpio_clk_synce#
1121 *
1122 * GPIO Clock SyncE Registers
1123 * A GSER can be configured as a clock source. The GPIO block can support up to two
1124 * unique clocks to send out any GPIO pin as configured when GPIO_BIT_CFG()[PIN_SEL] =
1125 * GPIO_PIN_SEL_E::GPIO_CLK_SYNCE(0..1). The clock can be divided by 20, 40, 80 or 160
1126 * of the selected GSER SerDes clock. Legal values are based on the number of SerDes.
1127 *
1128 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
1129 *
1130 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1131 */
1132 union bdk_gpio_clk_syncex
1133 {
1134 uint64_t u;
1135 struct bdk_gpio_clk_syncex_s
1136 {
1137 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1138 uint64_t reserved_12_63 : 52;
1139 uint64_t qlm_sel : 4; /**< [ 11: 8](R/W) Selects which GSER(0..3) to select from. */
1140 uint64_t reserved_4_7 : 4;
1141 uint64_t div : 2; /**< [ 3: 2](R/W) GPIO internal clock division of the GSER SerDes recovered clock to create the
1142 output clock. The maximum supported GPIO output frequency is 125 MHz.
1143 0x0 = Divide by 20.
1144 0x1 = Divide by 40.
1145 0x2 = Divide by 80.
1146 0x3 = Divide by 160. */
1147 uint64_t lane_sel : 2; /**< [ 1: 0](R/W) Which RX lane within the GSER selected with [QLM_SEL] to use as the GPIO
1148 internal QLMx clock. */
1149 #else /* Word 0 - Little Endian */
1150 uint64_t lane_sel : 2; /**< [ 1: 0](R/W) Which RX lane within the GSER selected with [QLM_SEL] to use as the GPIO
1151 internal QLMx clock. */
1152 uint64_t div : 2; /**< [ 3: 2](R/W) GPIO internal clock division of the GSER SerDes recovered clock to create the
1153 output clock. The maximum supported GPIO output frequency is 125 MHz.
1154 0x0 = Divide by 20.
1155 0x1 = Divide by 40.
1156 0x2 = Divide by 80.
1157 0x3 = Divide by 160. */
1158 uint64_t reserved_4_7 : 4;
1159 uint64_t qlm_sel : 4; /**< [ 11: 8](R/W) Selects which GSER(0..3) to select from. */
1160 uint64_t reserved_12_63 : 52;
1161 #endif /* Word 0 - End */
1162 } s;
1163 struct bdk_gpio_clk_syncex_cn9
1164 {
1165 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1166 uint64_t reserved_12_63 : 52;
1167 uint64_t qlm_sel : 4; /**< [ 11: 8](R/W) Selects which GSER to select from. */
1168 uint64_t reserved_4_7 : 4;
1169 uint64_t div : 2; /**< [ 3: 2](R/W) GPIO internal clock division of the GSER SerDes recovered clock to create the
1170 output clock. The maximum supported GPIO output frequency is 125 MHz.
1171 0x0 = Divide by 20.
1172 0x1 = Divide by 40.
1173 0x2 = Divide by 80.
1174 0x3 = Divide by 160. */
1175 uint64_t lane_sel : 2; /**< [ 1: 0](R/W) Which RX lane within the GSER permitted with [QLM_SEL] to use as the GPIO
1176 internal QLMx clock. Note that GSER 0..3 have four selections each while
1177 GSER 4..6 have two selections each. */
1178 #else /* Word 0 - Little Endian */
1179 uint64_t lane_sel : 2; /**< [ 1: 0](R/W) Which RX lane within the GSER permitted with [QLM_SEL] to use as the GPIO
1180 internal QLMx clock. Note that GSER 0..3 have four selections each while
1181 GSER 4..6 have two selections each. */
1182 uint64_t div : 2; /**< [ 3: 2](R/W) GPIO internal clock division of the GSER SerDes recovered clock to create the
1183 output clock. The maximum supported GPIO output frequency is 125 MHz.
1184 0x0 = Divide by 20.
1185 0x1 = Divide by 40.
1186 0x2 = Divide by 80.
1187 0x3 = Divide by 160. */
1188 uint64_t reserved_4_7 : 4;
1189 uint64_t qlm_sel : 4; /**< [ 11: 8](R/W) Selects which GSER to select from. */
1190 uint64_t reserved_12_63 : 52;
1191 #endif /* Word 0 - End */
1192 } cn9;
1193 /* struct bdk_gpio_clk_syncex_s cn81xx; */
1194 struct bdk_gpio_clk_syncex_cn88xx
1195 {
1196 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1197 uint64_t reserved_12_63 : 52;
1198 uint64_t qlm_sel : 4; /**< [ 11: 8](R/W) Selects which GSER(0..7) to select from. */
1199 uint64_t reserved_4_7 : 4;
1200 uint64_t div : 2; /**< [ 3: 2](R/W) GPIO internal clock division of the GSER SerDes recovered clock to create the
1201 output clock. The maximum supported GPIO output frequency is 125 MHz.
1202 0x0 = Divide by 20.
1203 0x1 = Divide by 40.
1204 0x2 = Divide by 80.
1205 0x3 = Divide by 160. */
1206 uint64_t lane_sel : 2; /**< [ 1: 0](R/W) Which RX lane within the GSER selected with [QLM_SEL] to use as the GPIO
1207 internal QLMx clock. */
1208 #else /* Word 0 - Little Endian */
1209 uint64_t lane_sel : 2; /**< [ 1: 0](R/W) Which RX lane within the GSER selected with [QLM_SEL] to use as the GPIO
1210 internal QLMx clock. */
1211 uint64_t div : 2; /**< [ 3: 2](R/W) GPIO internal clock division of the GSER SerDes recovered clock to create the
1212 output clock. The maximum supported GPIO output frequency is 125 MHz.
1213 0x0 = Divide by 20.
1214 0x1 = Divide by 40.
1215 0x2 = Divide by 80.
1216 0x3 = Divide by 160. */
1217 uint64_t reserved_4_7 : 4;
1218 uint64_t qlm_sel : 4; /**< [ 11: 8](R/W) Selects which GSER(0..7) to select from. */
1219 uint64_t reserved_12_63 : 52;
1220 #endif /* Word 0 - End */
1221 } cn88xx;
1222 struct bdk_gpio_clk_syncex_cn83xx
1223 {
1224 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1225 uint64_t reserved_12_63 : 52;
1226 uint64_t qlm_sel : 4; /**< [ 11: 8](R/W) Selects which GSER(0..6) to select from. */
1227 uint64_t reserved_4_7 : 4;
1228 uint64_t div : 2; /**< [ 3: 2](R/W) GPIO internal clock division of the GSER SerDes recovered clock to create the
1229 output clock. The maximum supported GPIO output frequency is 125 MHz.
1230 0x0 = Divide by 20.
1231 0x1 = Divide by 40.
1232 0x2 = Divide by 80.
1233 0x3 = Divide by 160. */
1234 uint64_t lane_sel : 2; /**< [ 1: 0](R/W) Which RX lane within the GSER selected with [QLM_SEL] to use as the GPIO
1235 internal QLMx clock. Note that GSER 0..3 have four selections each while
1236 GSER 4..6 have two selections each. */
1237 #else /* Word 0 - Little Endian */
1238 uint64_t lane_sel : 2; /**< [ 1: 0](R/W) Which RX lane within the GSER selected with [QLM_SEL] to use as the GPIO
1239 internal QLMx clock. Note that GSER 0..3 have four selections each while
1240 GSER 4..6 have two selections each. */
1241 uint64_t div : 2; /**< [ 3: 2](R/W) GPIO internal clock division of the GSER SerDes recovered clock to create the
1242 output clock. The maximum supported GPIO output frequency is 125 MHz.
1243 0x0 = Divide by 20.
1244 0x1 = Divide by 40.
1245 0x2 = Divide by 80.
1246 0x3 = Divide by 160. */
1247 uint64_t reserved_4_7 : 4;
1248 uint64_t qlm_sel : 4; /**< [ 11: 8](R/W) Selects which GSER(0..6) to select from. */
1249 uint64_t reserved_12_63 : 52;
1250 #endif /* Word 0 - End */
1251 } cn83xx;
1252 };
1253 typedef union bdk_gpio_clk_syncex bdk_gpio_clk_syncex_t;
1254
1255 static inline uint64_t BDK_GPIO_CLK_SYNCEX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GPIO_CLK_SYNCEX(unsigned long a)1256 static inline uint64_t BDK_GPIO_CLK_SYNCEX(unsigned long a)
1257 {
1258 if (a<=1)
1259 return 0x803000000060ll + 8ll * ((a) & 0x1);
1260 __bdk_csr_fatal("GPIO_CLK_SYNCEX", 1, a, 0, 0, 0);
1261 }
1262
1263 #define typedef_BDK_GPIO_CLK_SYNCEX(a) bdk_gpio_clk_syncex_t
1264 #define bustype_BDK_GPIO_CLK_SYNCEX(a) BDK_CSR_TYPE_NCB
1265 #define basename_BDK_GPIO_CLK_SYNCEX(a) "GPIO_CLK_SYNCEX"
1266 #define device_bar_BDK_GPIO_CLK_SYNCEX(a) 0x0 /* PF_BAR0 */
1267 #define busnum_BDK_GPIO_CLK_SYNCEX(a) (a)
1268 #define arguments_BDK_GPIO_CLK_SYNCEX(a) (a),-1,-1,-1
1269
1270 /**
1271 * Register (NCB) gpio_comp
1272 *
1273 * GPIO Compensation Register
1274 */
1275 union bdk_gpio_comp
1276 {
1277 uint64_t u;
1278 struct bdk_gpio_comp_s
1279 {
1280 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1281 uint64_t reserved_11_63 : 53;
1282 uint64_t pctl : 3; /**< [ 10: 8](R/W) GPIO bus driver PCTL. Suggested values:
1283 0x4 = 60 ohm.
1284 0x6 = 40 ohm.
1285 0x7 = 30 ohm. */
1286 uint64_t reserved_3_7 : 5;
1287 uint64_t nctl : 3; /**< [ 2: 0](R/W) GPIO bus driver NCTL. Suggested values:
1288 0x4 = 60 ohm.
1289 0x6 = 40 ohm.
1290 0x7 = 30 ohm. */
1291 #else /* Word 0 - Little Endian */
1292 uint64_t nctl : 3; /**< [ 2: 0](R/W) GPIO bus driver NCTL. Suggested values:
1293 0x4 = 60 ohm.
1294 0x6 = 40 ohm.
1295 0x7 = 30 ohm. */
1296 uint64_t reserved_3_7 : 5;
1297 uint64_t pctl : 3; /**< [ 10: 8](R/W) GPIO bus driver PCTL. Suggested values:
1298 0x4 = 60 ohm.
1299 0x6 = 40 ohm.
1300 0x7 = 30 ohm. */
1301 uint64_t reserved_11_63 : 53;
1302 #endif /* Word 0 - End */
1303 } s;
1304 /* struct bdk_gpio_comp_s cn; */
1305 };
1306 typedef union bdk_gpio_comp bdk_gpio_comp_t;
1307
1308 #define BDK_GPIO_COMP BDK_GPIO_COMP_FUNC()
1309 static inline uint64_t BDK_GPIO_COMP_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_COMP_FUNC(void)1310 static inline uint64_t BDK_GPIO_COMP_FUNC(void)
1311 {
1312 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
1313 return 0x803000000080ll;
1314 __bdk_csr_fatal("GPIO_COMP", 0, 0, 0, 0, 0);
1315 }
1316
1317 #define typedef_BDK_GPIO_COMP bdk_gpio_comp_t
1318 #define bustype_BDK_GPIO_COMP BDK_CSR_TYPE_NCB
1319 #define basename_BDK_GPIO_COMP "GPIO_COMP"
1320 #define device_bar_BDK_GPIO_COMP 0x0 /* PF_BAR0 */
1321 #define busnum_BDK_GPIO_COMP 0
1322 #define arguments_BDK_GPIO_COMP -1,-1,-1,-1
1323
1324 /**
1325 * Register (NCB) gpio_const
1326 *
1327 * GPIO Constants Register
1328 * This register contains constants for software discovery.
1329 *
1330 * This register is accessible to all requestors (regardless of GPIO_PERMIT).
1331 *
1332 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1333 */
1334 union bdk_gpio_const
1335 {
1336 uint64_t u;
1337 struct bdk_gpio_const_s
1338 {
1339 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1340 uint64_t reserved_20_63 : 44;
1341 uint64_t clkgen : 4; /**< [ 19: 16](RO) Number of clock generators in GPIO. */
1342 uint64_t pp : 8; /**< [ 15: 8](RO) Number of PP vectors in GPIO_INT_VEC_E::MC_INTR_PP(). */
1343 uint64_t gpios : 8; /**< [ 7: 0](RO) Number of GPIOs implemented. */
1344 #else /* Word 0 - Little Endian */
1345 uint64_t gpios : 8; /**< [ 7: 0](RO) Number of GPIOs implemented. */
1346 uint64_t pp : 8; /**< [ 15: 8](RO) Number of PP vectors in GPIO_INT_VEC_E::MC_INTR_PP(). */
1347 uint64_t clkgen : 4; /**< [ 19: 16](RO) Number of clock generators in GPIO. */
1348 uint64_t reserved_20_63 : 44;
1349 #endif /* Word 0 - End */
1350 } s;
1351 struct bdk_gpio_const_cn8
1352 {
1353 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1354 uint64_t reserved_16_63 : 48;
1355 uint64_t pp : 8; /**< [ 15: 8](RO) Number of PP vectors in GPIO_INT_VEC_E::MC_INTR_PP(). */
1356 uint64_t gpios : 8; /**< [ 7: 0](RO) Number of GPIOs implemented. */
1357 #else /* Word 0 - Little Endian */
1358 uint64_t gpios : 8; /**< [ 7: 0](RO) Number of GPIOs implemented. */
1359 uint64_t pp : 8; /**< [ 15: 8](RO) Number of PP vectors in GPIO_INT_VEC_E::MC_INTR_PP(). */
1360 uint64_t reserved_16_63 : 48;
1361 #endif /* Word 0 - End */
1362 } cn8;
1363 /* struct bdk_gpio_const_s cn9; */
1364 };
1365 typedef union bdk_gpio_const bdk_gpio_const_t;
1366
1367 #define BDK_GPIO_CONST BDK_GPIO_CONST_FUNC()
1368 static inline uint64_t BDK_GPIO_CONST_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_CONST_FUNC(void)1369 static inline uint64_t BDK_GPIO_CONST_FUNC(void)
1370 {
1371 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX))
1372 return 0x803000000090ll;
1373 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX))
1374 return 0x803000000090ll;
1375 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1376 return 0x803000000090ll;
1377 __bdk_csr_fatal("GPIO_CONST", 0, 0, 0, 0, 0);
1378 }
1379
1380 #define typedef_BDK_GPIO_CONST bdk_gpio_const_t
1381 #define bustype_BDK_GPIO_CONST BDK_CSR_TYPE_NCB
1382 #define basename_BDK_GPIO_CONST "GPIO_CONST"
1383 #define device_bar_BDK_GPIO_CONST 0x0 /* PF_BAR0 */
1384 #define busnum_BDK_GPIO_CONST 0
1385 #define arguments_BDK_GPIO_CONST -1,-1,-1,-1
1386
1387 /**
1388 * Register (NCB) gpio_intr#
1389 *
1390 * GPIO Bit Interrupt Registers
1391 * Each register provides interrupt information for the corresponding GPIO pin.
1392 * GPIO_INTR() interrupts can be level or edge interrupts depending on GPIO_BIT_CFG()[INT_TYPE].
1393 *
1394 * Each index is only accessible to the requestor(s) permitted with GPIO_BIT_PERMIT().
1395 *
1396 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1397 */
1398 union bdk_gpio_intrx
1399 {
1400 uint64_t u;
1401 struct bdk_gpio_intrx_s
1402 {
1403 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1404 uint64_t reserved_4_63 : 60;
1405 uint64_t intr_ena_w1s : 1; /**< [ 3: 3](R/W1S) GPIO signaled interrupt enable. Write one to set interrupt enable.
1406 [INTR_ENA_W1S] and [INTR_ENA_W1C] both read the interrupt enable state. */
1407 uint64_t intr_ena_w1c : 1; /**< [ 2: 2](R/W1C) GPIO signaled interrupt enable. Write one to clear interrupt enable.
1408 [INTR_ENA_W1S] and [INTR_ENA_W1C] both read the interrupt enable state. */
1409 uint64_t intr_w1s : 1; /**< [ 1: 1](R/W1S/H) GPIO signaled interrupt. If interrupts are edge-sensitive, write one to set, otherwise
1410 will clear automatically when GPIO pin de-asserts.
1411 [INTR_W1S] and [INTR] both read the interrupt state. */
1412 uint64_t intr : 1; /**< [ 0: 0](R/W1C/H) GPIO signaled interrupt. If interrupts are edge-sensitive, write one to clear, otherwise
1413 will clear automatically when GPIO pin de-asserts.
1414 [INTR_W1S] and [INTR] both read the interrupt state.
1415 An interrupt set event is sent when [INTR_ENA_W1S] reads as set. */
1416 #else /* Word 0 - Little Endian */
1417 uint64_t intr : 1; /**< [ 0: 0](R/W1C/H) GPIO signaled interrupt. If interrupts are edge-sensitive, write one to clear, otherwise
1418 will clear automatically when GPIO pin de-asserts.
1419 [INTR_W1S] and [INTR] both read the interrupt state.
1420 An interrupt set event is sent when [INTR_ENA_W1S] reads as set. */
1421 uint64_t intr_w1s : 1; /**< [ 1: 1](R/W1S/H) GPIO signaled interrupt. If interrupts are edge-sensitive, write one to set, otherwise
1422 will clear automatically when GPIO pin de-asserts.
1423 [INTR_W1S] and [INTR] both read the interrupt state. */
1424 uint64_t intr_ena_w1c : 1; /**< [ 2: 2](R/W1C) GPIO signaled interrupt enable. Write one to clear interrupt enable.
1425 [INTR_ENA_W1S] and [INTR_ENA_W1C] both read the interrupt enable state. */
1426 uint64_t intr_ena_w1s : 1; /**< [ 3: 3](R/W1S) GPIO signaled interrupt enable. Write one to set interrupt enable.
1427 [INTR_ENA_W1S] and [INTR_ENA_W1C] both read the interrupt enable state. */
1428 uint64_t reserved_4_63 : 60;
1429 #endif /* Word 0 - End */
1430 } s;
1431 /* struct bdk_gpio_intrx_s cn; */
1432 };
1433 typedef union bdk_gpio_intrx bdk_gpio_intrx_t;
1434
1435 static inline uint64_t BDK_GPIO_INTRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GPIO_INTRX(unsigned long a)1436 static inline uint64_t BDK_GPIO_INTRX(unsigned long a)
1437 {
1438 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=47))
1439 return 0x803000000800ll + 8ll * ((a) & 0x3f);
1440 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=79))
1441 return 0x803000000800ll + 8ll * ((a) & 0x7f);
1442 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=50))
1443 return 0x803000000800ll + 8ll * ((a) & 0x3f);
1444 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=63))
1445 return 0x803000000800ll + 8ll * ((a) & 0x3f);
1446 __bdk_csr_fatal("GPIO_INTRX", 1, a, 0, 0, 0);
1447 }
1448
1449 #define typedef_BDK_GPIO_INTRX(a) bdk_gpio_intrx_t
1450 #define bustype_BDK_GPIO_INTRX(a) BDK_CSR_TYPE_NCB
1451 #define basename_BDK_GPIO_INTRX(a) "GPIO_INTRX"
1452 #define device_bar_BDK_GPIO_INTRX(a) 0x0 /* PF_BAR0 */
1453 #define busnum_BDK_GPIO_INTRX(a) (a)
1454 #define arguments_BDK_GPIO_INTRX(a) (a),-1,-1,-1
1455
1456 /**
1457 * Register (NCB) gpio_io_ctl
1458 *
1459 * GPIO I/O Control Register
1460 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
1461 *
1462 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1463 */
1464 union bdk_gpio_io_ctl
1465 {
1466 uint64_t u;
1467 struct bdk_gpio_io_ctl_s
1468 {
1469 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1470 uint64_t reserved_12_63 : 52;
1471 uint64_t drive2 : 2; /**< [ 11: 10](R/W) GPIO\<63:48\> pin output drive strength.
1472 0x0 = 2 mA.
1473 0x1 = 4 mA.
1474 0x2 = 8 mA.
1475 0x3 = 16 mA. */
1476 uint64_t reserved_9 : 1;
1477 uint64_t slew2 : 1; /**< [ 8: 8](R/W) GPIO\<63:48\> pin output slew rate control.
1478 0 = Low slew rate.
1479 1 = High slew rate. */
1480 uint64_t drive1 : 2; /**< [ 7: 6](R/W) GPIO\<47:24\> pin output drive strength.
1481 0x0 = 2 mA.
1482 0x1 = 4 mA.
1483 0x2 = 8 mA.
1484 0x3 = 16 mA. */
1485 uint64_t reserved_5 : 1;
1486 uint64_t slew1 : 1; /**< [ 4: 4](R/W) GPIO\<47:24\> pin output slew rate control.
1487 0 = Low slew rate.
1488 1 = High slew rate. */
1489 uint64_t drive0 : 2; /**< [ 3: 2](R/W) GPIO\<23:0\> pin output drive strength.
1490 0x0 = 2 mA.
1491 0x1 = 4 mA.
1492 0x2 = 8 mA.
1493 0x3 = 16 mA. */
1494 uint64_t reserved_1 : 1;
1495 uint64_t slew0 : 1; /**< [ 0: 0](R/W) GPIO\<23:0\> pin output slew rate control.
1496 0 = Low slew rate.
1497 1 = High slew rate. */
1498 #else /* Word 0 - Little Endian */
1499 uint64_t slew0 : 1; /**< [ 0: 0](R/W) GPIO\<23:0\> pin output slew rate control.
1500 0 = Low slew rate.
1501 1 = High slew rate. */
1502 uint64_t reserved_1 : 1;
1503 uint64_t drive0 : 2; /**< [ 3: 2](R/W) GPIO\<23:0\> pin output drive strength.
1504 0x0 = 2 mA.
1505 0x1 = 4 mA.
1506 0x2 = 8 mA.
1507 0x3 = 16 mA. */
1508 uint64_t slew1 : 1; /**< [ 4: 4](R/W) GPIO\<47:24\> pin output slew rate control.
1509 0 = Low slew rate.
1510 1 = High slew rate. */
1511 uint64_t reserved_5 : 1;
1512 uint64_t drive1 : 2; /**< [ 7: 6](R/W) GPIO\<47:24\> pin output drive strength.
1513 0x0 = 2 mA.
1514 0x1 = 4 mA.
1515 0x2 = 8 mA.
1516 0x3 = 16 mA. */
1517 uint64_t slew2 : 1; /**< [ 8: 8](R/W) GPIO\<63:48\> pin output slew rate control.
1518 0 = Low slew rate.
1519 1 = High slew rate. */
1520 uint64_t reserved_9 : 1;
1521 uint64_t drive2 : 2; /**< [ 11: 10](R/W) GPIO\<63:48\> pin output drive strength.
1522 0x0 = 2 mA.
1523 0x1 = 4 mA.
1524 0x2 = 8 mA.
1525 0x3 = 16 mA. */
1526 uint64_t reserved_12_63 : 52;
1527 #endif /* Word 0 - End */
1528 } s;
1529 /* struct bdk_gpio_io_ctl_s cn; */
1530 };
1531 typedef union bdk_gpio_io_ctl bdk_gpio_io_ctl_t;
1532
1533 #define BDK_GPIO_IO_CTL BDK_GPIO_IO_CTL_FUNC()
1534 static inline uint64_t BDK_GPIO_IO_CTL_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_IO_CTL_FUNC(void)1535 static inline uint64_t BDK_GPIO_IO_CTL_FUNC(void)
1536 {
1537 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1538 return 0x803000000080ll;
1539 __bdk_csr_fatal("GPIO_IO_CTL", 0, 0, 0, 0, 0);
1540 }
1541
1542 #define typedef_BDK_GPIO_IO_CTL bdk_gpio_io_ctl_t
1543 #define bustype_BDK_GPIO_IO_CTL BDK_CSR_TYPE_NCB
1544 #define basename_BDK_GPIO_IO_CTL "GPIO_IO_CTL"
1545 #define device_bar_BDK_GPIO_IO_CTL 0x0 /* PF_BAR0 */
1546 #define busnum_BDK_GPIO_IO_CTL 0
1547 #define arguments_BDK_GPIO_IO_CTL -1,-1,-1,-1
1548
1549 /**
1550 * Register (NCB) gpio_mc_intr#
1551 *
1552 * GPIO Bit Multicast Interrupt Registers
1553 * Each register provides interrupt multicasting for GPIO(4..7).
1554 *
1555 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
1556 *
1557 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1558 */
1559 union bdk_gpio_mc_intrx
1560 {
1561 uint64_t u;
1562 struct bdk_gpio_mc_intrx_s
1563 {
1564 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1565 uint64_t reserved_48_63 : 16;
1566 uint64_t intr : 48; /**< [ 47: 0](R/W1C/H) GPIO interrupt for each core. When corresponding GPIO4-7 is edge-triggered and MULTI_CAST
1567 is enabled, a GPIO assertion will set all 48 bits. Each bit is expected to be routed to
1568 interrupt a different core using the CIU, and each core will then write one to clear its
1569 corresponding bit in this register. */
1570 #else /* Word 0 - Little Endian */
1571 uint64_t intr : 48; /**< [ 47: 0](R/W1C/H) GPIO interrupt for each core. When corresponding GPIO4-7 is edge-triggered and MULTI_CAST
1572 is enabled, a GPIO assertion will set all 48 bits. Each bit is expected to be routed to
1573 interrupt a different core using the CIU, and each core will then write one to clear its
1574 corresponding bit in this register. */
1575 uint64_t reserved_48_63 : 16;
1576 #endif /* Word 0 - End */
1577 } s;
1578 /* struct bdk_gpio_mc_intrx_s cn8; */
1579 struct bdk_gpio_mc_intrx_cn9
1580 {
1581 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1582 uint64_t reserved_24_63 : 40;
1583 uint64_t intr : 24; /**< [ 23: 0](R/W1C/H) GPIO interrupt for each core. When corresponding GPIO4-7 is edge-triggered and GPIO_MULTI_CAST[EN]
1584 is enabled, a GPIO assertion will set all 24 bits. Each bit is expected to be routed to
1585 interrupt a different core using the CIU, and each core will then write one to clear its
1586 corresponding bit in this register. */
1587 #else /* Word 0 - Little Endian */
1588 uint64_t intr : 24; /**< [ 23: 0](R/W1C/H) GPIO interrupt for each core. When corresponding GPIO4-7 is edge-triggered and GPIO_MULTI_CAST[EN]
1589 is enabled, a GPIO assertion will set all 24 bits. Each bit is expected to be routed to
1590 interrupt a different core using the CIU, and each core will then write one to clear its
1591 corresponding bit in this register. */
1592 uint64_t reserved_24_63 : 40;
1593 #endif /* Word 0 - End */
1594 } cn9;
1595 };
1596 typedef union bdk_gpio_mc_intrx bdk_gpio_mc_intrx_t;
1597
1598 static inline uint64_t BDK_GPIO_MC_INTRX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GPIO_MC_INTRX(unsigned long a)1599 static inline uint64_t BDK_GPIO_MC_INTRX(unsigned long a)
1600 {
1601 if ((a>=4)&&(a<=7))
1602 return 0x803000001000ll + 8ll * ((a) & 0x7);
1603 __bdk_csr_fatal("GPIO_MC_INTRX", 1, a, 0, 0, 0);
1604 }
1605
1606 #define typedef_BDK_GPIO_MC_INTRX(a) bdk_gpio_mc_intrx_t
1607 #define bustype_BDK_GPIO_MC_INTRX(a) BDK_CSR_TYPE_NCB
1608 #define basename_BDK_GPIO_MC_INTRX(a) "GPIO_MC_INTRX"
1609 #define device_bar_BDK_GPIO_MC_INTRX(a) 0x0 /* PF_BAR0 */
1610 #define busnum_BDK_GPIO_MC_INTRX(a) (a)
1611 #define arguments_BDK_GPIO_MC_INTRX(a) (a),-1,-1,-1
1612
1613 /**
1614 * Register (NCB) gpio_mc_intr#_ena_w1c
1615 *
1616 * GPIO Bit Multicast Interrupt Registers
1617 * This register clears interrupt enable bits.
1618 */
1619 union bdk_gpio_mc_intrx_ena_w1c
1620 {
1621 uint64_t u;
1622 struct bdk_gpio_mc_intrx_ena_w1c_s
1623 {
1624 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1625 uint64_t reserved_48_63 : 16;
1626 uint64_t intr : 48; /**< [ 47: 0](R/W1C/H) Reads or clears enable for GPIO_MC_INTR(4..7)[INTR]. */
1627 #else /* Word 0 - Little Endian */
1628 uint64_t intr : 48; /**< [ 47: 0](R/W1C/H) Reads or clears enable for GPIO_MC_INTR(4..7)[INTR]. */
1629 uint64_t reserved_48_63 : 16;
1630 #endif /* Word 0 - End */
1631 } s;
1632 /* struct bdk_gpio_mc_intrx_ena_w1c_s cn8; */
1633 struct bdk_gpio_mc_intrx_ena_w1c_cn9
1634 {
1635 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1636 uint64_t reserved_24_63 : 40;
1637 uint64_t intr : 24; /**< [ 23: 0](R/W1C/H) Reads or clears enable for GPIO_MC_INTR(4..7)[INTR]. */
1638 #else /* Word 0 - Little Endian */
1639 uint64_t intr : 24; /**< [ 23: 0](R/W1C/H) Reads or clears enable for GPIO_MC_INTR(4..7)[INTR]. */
1640 uint64_t reserved_24_63 : 40;
1641 #endif /* Word 0 - End */
1642 } cn9;
1643 };
1644 typedef union bdk_gpio_mc_intrx_ena_w1c bdk_gpio_mc_intrx_ena_w1c_t;
1645
1646 static inline uint64_t BDK_GPIO_MC_INTRX_ENA_W1C(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GPIO_MC_INTRX_ENA_W1C(unsigned long a)1647 static inline uint64_t BDK_GPIO_MC_INTRX_ENA_W1C(unsigned long a)
1648 {
1649 if ((a>=4)&&(a<=7))
1650 return 0x803000001200ll + 8ll * ((a) & 0x7);
1651 __bdk_csr_fatal("GPIO_MC_INTRX_ENA_W1C", 1, a, 0, 0, 0);
1652 }
1653
1654 #define typedef_BDK_GPIO_MC_INTRX_ENA_W1C(a) bdk_gpio_mc_intrx_ena_w1c_t
1655 #define bustype_BDK_GPIO_MC_INTRX_ENA_W1C(a) BDK_CSR_TYPE_NCB
1656 #define basename_BDK_GPIO_MC_INTRX_ENA_W1C(a) "GPIO_MC_INTRX_ENA_W1C"
1657 #define device_bar_BDK_GPIO_MC_INTRX_ENA_W1C(a) 0x0 /* PF_BAR0 */
1658 #define busnum_BDK_GPIO_MC_INTRX_ENA_W1C(a) (a)
1659 #define arguments_BDK_GPIO_MC_INTRX_ENA_W1C(a) (a),-1,-1,-1
1660
1661 /**
1662 * Register (NCB) gpio_mc_intr#_ena_w1s
1663 *
1664 * GPIO Bit Multicast Interrupt Registers
1665 * This register sets interrupt enable bits.
1666 */
1667 union bdk_gpio_mc_intrx_ena_w1s
1668 {
1669 uint64_t u;
1670 struct bdk_gpio_mc_intrx_ena_w1s_s
1671 {
1672 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1673 uint64_t reserved_48_63 : 16;
1674 uint64_t intr : 48; /**< [ 47: 0](R/W1S/H) Reads or sets enable for GPIO_MC_INTR(4..7)[INTR]. */
1675 #else /* Word 0 - Little Endian */
1676 uint64_t intr : 48; /**< [ 47: 0](R/W1S/H) Reads or sets enable for GPIO_MC_INTR(4..7)[INTR]. */
1677 uint64_t reserved_48_63 : 16;
1678 #endif /* Word 0 - End */
1679 } s;
1680 /* struct bdk_gpio_mc_intrx_ena_w1s_s cn8; */
1681 struct bdk_gpio_mc_intrx_ena_w1s_cn9
1682 {
1683 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1684 uint64_t reserved_24_63 : 40;
1685 uint64_t intr : 24; /**< [ 23: 0](R/W1S/H) Reads or sets enable for GPIO_MC_INTR(4..7)[INTR]. */
1686 #else /* Word 0 - Little Endian */
1687 uint64_t intr : 24; /**< [ 23: 0](R/W1S/H) Reads or sets enable for GPIO_MC_INTR(4..7)[INTR]. */
1688 uint64_t reserved_24_63 : 40;
1689 #endif /* Word 0 - End */
1690 } cn9;
1691 };
1692 typedef union bdk_gpio_mc_intrx_ena_w1s bdk_gpio_mc_intrx_ena_w1s_t;
1693
1694 static inline uint64_t BDK_GPIO_MC_INTRX_ENA_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GPIO_MC_INTRX_ENA_W1S(unsigned long a)1695 static inline uint64_t BDK_GPIO_MC_INTRX_ENA_W1S(unsigned long a)
1696 {
1697 if ((a>=4)&&(a<=7))
1698 return 0x803000001300ll + 8ll * ((a) & 0x7);
1699 __bdk_csr_fatal("GPIO_MC_INTRX_ENA_W1S", 1, a, 0, 0, 0);
1700 }
1701
1702 #define typedef_BDK_GPIO_MC_INTRX_ENA_W1S(a) bdk_gpio_mc_intrx_ena_w1s_t
1703 #define bustype_BDK_GPIO_MC_INTRX_ENA_W1S(a) BDK_CSR_TYPE_NCB
1704 #define basename_BDK_GPIO_MC_INTRX_ENA_W1S(a) "GPIO_MC_INTRX_ENA_W1S"
1705 #define device_bar_BDK_GPIO_MC_INTRX_ENA_W1S(a) 0x0 /* PF_BAR0 */
1706 #define busnum_BDK_GPIO_MC_INTRX_ENA_W1S(a) (a)
1707 #define arguments_BDK_GPIO_MC_INTRX_ENA_W1S(a) (a),-1,-1,-1
1708
1709 /**
1710 * Register (NCB) gpio_mc_intr#_w1s
1711 *
1712 * GPIO Bit Multicast Interrupt Registers
1713 * This register sets interrupt bits.
1714 */
1715 union bdk_gpio_mc_intrx_w1s
1716 {
1717 uint64_t u;
1718 struct bdk_gpio_mc_intrx_w1s_s
1719 {
1720 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1721 uint64_t reserved_48_63 : 16;
1722 uint64_t intr : 48; /**< [ 47: 0](R/W1S/H) Reads or sets GPIO_MC_INTR(4..7)[INTR]. */
1723 #else /* Word 0 - Little Endian */
1724 uint64_t intr : 48; /**< [ 47: 0](R/W1S/H) Reads or sets GPIO_MC_INTR(4..7)[INTR]. */
1725 uint64_t reserved_48_63 : 16;
1726 #endif /* Word 0 - End */
1727 } s;
1728 /* struct bdk_gpio_mc_intrx_w1s_s cn8; */
1729 struct bdk_gpio_mc_intrx_w1s_cn9
1730 {
1731 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1732 uint64_t reserved_24_63 : 40;
1733 uint64_t intr : 24; /**< [ 23: 0](R/W1S/H) Reads or sets GPIO_MC_INTR(4..7)[INTR]. */
1734 #else /* Word 0 - Little Endian */
1735 uint64_t intr : 24; /**< [ 23: 0](R/W1S/H) Reads or sets GPIO_MC_INTR(4..7)[INTR]. */
1736 uint64_t reserved_24_63 : 40;
1737 #endif /* Word 0 - End */
1738 } cn9;
1739 };
1740 typedef union bdk_gpio_mc_intrx_w1s bdk_gpio_mc_intrx_w1s_t;
1741
1742 static inline uint64_t BDK_GPIO_MC_INTRX_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GPIO_MC_INTRX_W1S(unsigned long a)1743 static inline uint64_t BDK_GPIO_MC_INTRX_W1S(unsigned long a)
1744 {
1745 if ((a>=4)&&(a<=7))
1746 return 0x803000001100ll + 8ll * ((a) & 0x7);
1747 __bdk_csr_fatal("GPIO_MC_INTRX_W1S", 1, a, 0, 0, 0);
1748 }
1749
1750 #define typedef_BDK_GPIO_MC_INTRX_W1S(a) bdk_gpio_mc_intrx_w1s_t
1751 #define bustype_BDK_GPIO_MC_INTRX_W1S(a) BDK_CSR_TYPE_NCB
1752 #define basename_BDK_GPIO_MC_INTRX_W1S(a) "GPIO_MC_INTRX_W1S"
1753 #define device_bar_BDK_GPIO_MC_INTRX_W1S(a) 0x0 /* PF_BAR0 */
1754 #define busnum_BDK_GPIO_MC_INTRX_W1S(a) (a)
1755 #define arguments_BDK_GPIO_MC_INTRX_W1S(a) (a),-1,-1,-1
1756
1757 /**
1758 * Register (NCB) gpio_misc_strap
1759 *
1760 * GPIO Misc Strap Value Register
1761 * This register contains the miscellaneous strap state.
1762 *
1763 * This register is accessible to all requestors (regardless of GPIO_PERMIT).
1764 *
1765 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1766 */
1767 union bdk_gpio_misc_strap
1768 {
1769 uint64_t u;
1770 struct bdk_gpio_misc_strap_s
1771 {
1772 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1773 uint64_t reserved_18_63 : 46;
1774 uint64_t uart1_rts : 1; /**< [ 17: 17](RO/H) State of UART1_RTS_N pin strap sampled when DCOK asserts. */
1775 uint64_t uart0_rts : 1; /**< [ 16: 16](RO/H) State of UART0_RTS_N pin strap sampled when DCOK asserts. */
1776 uint64_t reserved_0_15 : 16;
1777 #else /* Word 0 - Little Endian */
1778 uint64_t reserved_0_15 : 16;
1779 uint64_t uart0_rts : 1; /**< [ 16: 16](RO/H) State of UART0_RTS_N pin strap sampled when DCOK asserts. */
1780 uint64_t uart1_rts : 1; /**< [ 17: 17](RO/H) State of UART1_RTS_N pin strap sampled when DCOK asserts. */
1781 uint64_t reserved_18_63 : 46;
1782 #endif /* Word 0 - End */
1783 } s;
1784 /* struct bdk_gpio_misc_strap_s cn; */
1785 };
1786 typedef union bdk_gpio_misc_strap bdk_gpio_misc_strap_t;
1787
1788 #define BDK_GPIO_MISC_STRAP BDK_GPIO_MISC_STRAP_FUNC()
1789 static inline uint64_t BDK_GPIO_MISC_STRAP_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_MISC_STRAP_FUNC(void)1790 static inline uint64_t BDK_GPIO_MISC_STRAP_FUNC(void)
1791 {
1792 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1793 return 0x803000000030ll;
1794 __bdk_csr_fatal("GPIO_MISC_STRAP", 0, 0, 0, 0, 0);
1795 }
1796
1797 #define typedef_BDK_GPIO_MISC_STRAP bdk_gpio_misc_strap_t
1798 #define bustype_BDK_GPIO_MISC_STRAP BDK_CSR_TYPE_NCB
1799 #define basename_BDK_GPIO_MISC_STRAP "GPIO_MISC_STRAP"
1800 #define device_bar_BDK_GPIO_MISC_STRAP 0x0 /* PF_BAR0 */
1801 #define busnum_BDK_GPIO_MISC_STRAP 0
1802 #define arguments_BDK_GPIO_MISC_STRAP -1,-1,-1,-1
1803
1804 /**
1805 * Register (NCB) gpio_misc_supply
1806 *
1807 * GPIO Misc Supply Value Register
1808 * This register contains the state of the GPIO power supplies.
1809 *
1810 * This register is accessible to all requestors (regardless of GPIO_PERMIT).
1811 *
1812 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1813 */
1814 union bdk_gpio_misc_supply
1815 {
1816 uint64_t u;
1817 struct bdk_gpio_misc_supply_s
1818 {
1819 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1820 uint64_t reserved_22_63 : 42;
1821 uint64_t vdet_avs : 2; /**< [ 21: 20](RO/H) Sensed I/O power supply setting for AVS bus:
1822 0x0 = 3.3 V.
1823 0x1 = 2.5 V.
1824 0x2/0x3 = 1.8 V.
1825 _ All other values reserved. */
1826 uint64_t vdet_emmc : 2; /**< [ 19: 18](RO/H) Sensed I/O power supply setting for EMMC bus:
1827 0x0 = 3.3 V.
1828 0x1 = 2.5 V.
1829 0x2/0x3 = 1.8 V.
1830 _ All other values reserved. */
1831 uint64_t vdet_gpio0 : 2; /**< [ 17: 16](RO/H) Sensed I/O power supply setting for GPIO0..23.
1832 0x0 = 3.3 V.
1833 0x1 = 2.5 V.
1834 0x2/0x3 = 1.8 V.
1835 _ All other values reserved. */
1836 uint64_t vdet_gpio24 : 2; /**< [ 15: 14](RO/H) Sensed I/O power supply setting for GPIO24..47.
1837 0x0 = 3.3 V.
1838 0x1 = 2.5 V.
1839 0x2/0x3 = 1.8 V.
1840 _ All other values reserved. */
1841 uint64_t vdet_gpio48 : 2; /**< [ 13: 12](RO/H) Sensed I/O power supply setting for GPIO48..63.
1842 0x0 = 3.3 V.
1843 0x1 = 2.5 V.
1844 0x2/0x3 = 1.8 V.
1845 _ All other values reserved. */
1846 uint64_t vdet_io_e : 2; /**< [ 11: 10](RO/H) Sensed I/O power supply setting for generic east IO pins:
1847 0x0 = 3.3 V.
1848 0x1 = 2.5 V.
1849 0x2/0x3 = 1.8 V.
1850 _ All other values reserved. */
1851 uint64_t vdet_io_n : 2; /**< [ 9: 8](RO/H) Sensed I/O power supply setting for generic north IO pins:
1852 0x0 = 3.3 V.
1853 0x1 = 2.5 V.
1854 0x2/0x3 = 1.8 V.
1855 _ All other values reserved. */
1856 uint64_t vdet_pci : 2; /**< [ 7: 6](RO/H) Sensed I/O power supply setting for PCI IO pins:
1857 0x0 = 3.3 V.
1858 0x1 = 2.5 V.
1859 0x2/0x3 = 1.8 V.
1860 _ All other values reserved. */
1861 uint64_t vdet_smi : 2; /**< [ 5: 4](RO/H) Sensed I/O power supply setting for SMI bus:
1862 0x0 = 3.3 V.
1863 0x1 = 2.5 V.
1864 0x2/0x3 = 1.8 V.
1865 _ All other values reserved. */
1866 uint64_t vdet_spi : 2; /**< [ 3: 2](RO/H) Sensed I/O power supply setting for SPI0 bus:
1867 0x0 = 3.3 V.
1868 0x1 = 2.5 V.
1869 0x2/0x3 = 1.8 V.
1870 _ All other values reserved. */
1871 uint64_t vdet_tws_avs : 2; /**< [ 1: 0](RO/H) Sensed I/O power supply setting for TWSI and AVS:
1872 0x0 = 3.3 V.
1873 0x1 = 2.5 V.
1874 0x2/0x3 = 1.8 V.
1875 _ All other values reserved. */
1876 #else /* Word 0 - Little Endian */
1877 uint64_t vdet_tws_avs : 2; /**< [ 1: 0](RO/H) Sensed I/O power supply setting for TWSI and AVS:
1878 0x0 = 3.3 V.
1879 0x1 = 2.5 V.
1880 0x2/0x3 = 1.8 V.
1881 _ All other values reserved. */
1882 uint64_t vdet_spi : 2; /**< [ 3: 2](RO/H) Sensed I/O power supply setting for SPI0 bus:
1883 0x0 = 3.3 V.
1884 0x1 = 2.5 V.
1885 0x2/0x3 = 1.8 V.
1886 _ All other values reserved. */
1887 uint64_t vdet_smi : 2; /**< [ 5: 4](RO/H) Sensed I/O power supply setting for SMI bus:
1888 0x0 = 3.3 V.
1889 0x1 = 2.5 V.
1890 0x2/0x3 = 1.8 V.
1891 _ All other values reserved. */
1892 uint64_t vdet_pci : 2; /**< [ 7: 6](RO/H) Sensed I/O power supply setting for PCI IO pins:
1893 0x0 = 3.3 V.
1894 0x1 = 2.5 V.
1895 0x2/0x3 = 1.8 V.
1896 _ All other values reserved. */
1897 uint64_t vdet_io_n : 2; /**< [ 9: 8](RO/H) Sensed I/O power supply setting for generic north IO pins:
1898 0x0 = 3.3 V.
1899 0x1 = 2.5 V.
1900 0x2/0x3 = 1.8 V.
1901 _ All other values reserved. */
1902 uint64_t vdet_io_e : 2; /**< [ 11: 10](RO/H) Sensed I/O power supply setting for generic east IO pins:
1903 0x0 = 3.3 V.
1904 0x1 = 2.5 V.
1905 0x2/0x3 = 1.8 V.
1906 _ All other values reserved. */
1907 uint64_t vdet_gpio48 : 2; /**< [ 13: 12](RO/H) Sensed I/O power supply setting for GPIO48..63.
1908 0x0 = 3.3 V.
1909 0x1 = 2.5 V.
1910 0x2/0x3 = 1.8 V.
1911 _ All other values reserved. */
1912 uint64_t vdet_gpio24 : 2; /**< [ 15: 14](RO/H) Sensed I/O power supply setting for GPIO24..47.
1913 0x0 = 3.3 V.
1914 0x1 = 2.5 V.
1915 0x2/0x3 = 1.8 V.
1916 _ All other values reserved. */
1917 uint64_t vdet_gpio0 : 2; /**< [ 17: 16](RO/H) Sensed I/O power supply setting for GPIO0..23.
1918 0x0 = 3.3 V.
1919 0x1 = 2.5 V.
1920 0x2/0x3 = 1.8 V.
1921 _ All other values reserved. */
1922 uint64_t vdet_emmc : 2; /**< [ 19: 18](RO/H) Sensed I/O power supply setting for EMMC bus:
1923 0x0 = 3.3 V.
1924 0x1 = 2.5 V.
1925 0x2/0x3 = 1.8 V.
1926 _ All other values reserved. */
1927 uint64_t vdet_avs : 2; /**< [ 21: 20](RO/H) Sensed I/O power supply setting for AVS bus:
1928 0x0 = 3.3 V.
1929 0x1 = 2.5 V.
1930 0x2/0x3 = 1.8 V.
1931 _ All other values reserved. */
1932 uint64_t reserved_22_63 : 42;
1933 #endif /* Word 0 - End */
1934 } s;
1935 /* struct bdk_gpio_misc_supply_s cn; */
1936 };
1937 typedef union bdk_gpio_misc_supply bdk_gpio_misc_supply_t;
1938
1939 #define BDK_GPIO_MISC_SUPPLY BDK_GPIO_MISC_SUPPLY_FUNC()
1940 static inline uint64_t BDK_GPIO_MISC_SUPPLY_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_MISC_SUPPLY_FUNC(void)1941 static inline uint64_t BDK_GPIO_MISC_SUPPLY_FUNC(void)
1942 {
1943 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1944 return 0x803000000038ll;
1945 __bdk_csr_fatal("GPIO_MISC_SUPPLY", 0, 0, 0, 0, 0);
1946 }
1947
1948 #define typedef_BDK_GPIO_MISC_SUPPLY bdk_gpio_misc_supply_t
1949 #define bustype_BDK_GPIO_MISC_SUPPLY BDK_CSR_TYPE_NCB
1950 #define basename_BDK_GPIO_MISC_SUPPLY "GPIO_MISC_SUPPLY"
1951 #define device_bar_BDK_GPIO_MISC_SUPPLY 0x0 /* PF_BAR0 */
1952 #define busnum_BDK_GPIO_MISC_SUPPLY 0
1953 #define arguments_BDK_GPIO_MISC_SUPPLY -1,-1,-1,-1
1954
1955 /**
1956 * Register (NCB) gpio_msix_pba#
1957 *
1958 * GPIO MSI-X Pending Bit Array Registers
1959 * This register is the MSI-X PBA table; the bit number is indexed by the GPIO_INT_VEC_E enumeration.
1960 *
1961 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1962 */
1963 union bdk_gpio_msix_pbax
1964 {
1965 uint64_t u;
1966 struct bdk_gpio_msix_pbax_s
1967 {
1968 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1969 uint64_t pend : 64; /**< [ 63: 0](RO) Pending message for the associated GPIO_MSIX_VEC()_CTL, enumerated by
1970 GPIO_INT_VEC_E. Bits
1971 that have no associated GPIO_INT_VEC_E are 0. */
1972 #else /* Word 0 - Little Endian */
1973 uint64_t pend : 64; /**< [ 63: 0](RO) Pending message for the associated GPIO_MSIX_VEC()_CTL, enumerated by
1974 GPIO_INT_VEC_E. Bits
1975 that have no associated GPIO_INT_VEC_E are 0. */
1976 #endif /* Word 0 - End */
1977 } s;
1978 /* struct bdk_gpio_msix_pbax_s cn; */
1979 };
1980 typedef union bdk_gpio_msix_pbax bdk_gpio_msix_pbax_t;
1981
1982 static inline uint64_t BDK_GPIO_MSIX_PBAX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GPIO_MSIX_PBAX(unsigned long a)1983 static inline uint64_t BDK_GPIO_MSIX_PBAX(unsigned long a)
1984 {
1985 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1986 return 0x803000ff0000ll + 8ll * ((a) & 0x1);
1987 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=2))
1988 return 0x803000ff0000ll + 8ll * ((a) & 0x3);
1989 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=2))
1990 return 0x803000ff0000ll + 8ll * ((a) & 0x3);
1991 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=2))
1992 return 0x803000ff0000ll + 8ll * ((a) & 0x3);
1993 __bdk_csr_fatal("GPIO_MSIX_PBAX", 1, a, 0, 0, 0);
1994 }
1995
1996 #define typedef_BDK_GPIO_MSIX_PBAX(a) bdk_gpio_msix_pbax_t
1997 #define bustype_BDK_GPIO_MSIX_PBAX(a) BDK_CSR_TYPE_NCB
1998 #define basename_BDK_GPIO_MSIX_PBAX(a) "GPIO_MSIX_PBAX"
1999 #define device_bar_BDK_GPIO_MSIX_PBAX(a) 0x4 /* PF_BAR4 */
2000 #define busnum_BDK_GPIO_MSIX_PBAX(a) (a)
2001 #define arguments_BDK_GPIO_MSIX_PBAX(a) (a),-1,-1,-1
2002
2003 /**
2004 * Register (NCB) gpio_msix_vec#_addr
2005 *
2006 * GPIO MSI-X Vector-Table Address Register
2007 * This register is the MSI-X vector table, indexed by the GPIO_INT_VEC_E enumeration.
2008 *
2009 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2010 */
2011 union bdk_gpio_msix_vecx_addr
2012 {
2013 uint64_t u;
2014 struct bdk_gpio_msix_vecx_addr_s
2015 {
2016 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2017 uint64_t reserved_53_63 : 11;
2018 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
2019 uint64_t reserved_1 : 1;
2020 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
2021 0 = This vector may be read or written by either secure or nonsecure states.
2022 1 = This vector's GPIO_MSIX_VEC()_ADDR, GPIO_MSIX_VEC()_CTL, and corresponding
2023 bit of GPIO_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
2024 by the nonsecure world.
2025
2026 If PCCPF_GPIO_VSEC_SCTL[MSIX_SEC] (for documentation, see PCCPF_XXX_VSEC_SCTL[MSIX_SEC])
2027 is set, all vectors are secure and function as if [SECVEC] was set. */
2028 #else /* Word 0 - Little Endian */
2029 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
2030 0 = This vector may be read or written by either secure or nonsecure states.
2031 1 = This vector's GPIO_MSIX_VEC()_ADDR, GPIO_MSIX_VEC()_CTL, and corresponding
2032 bit of GPIO_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
2033 by the nonsecure world.
2034
2035 If PCCPF_GPIO_VSEC_SCTL[MSIX_SEC] (for documentation, see PCCPF_XXX_VSEC_SCTL[MSIX_SEC])
2036 is set, all vectors are secure and function as if [SECVEC] was set. */
2037 uint64_t reserved_1 : 1;
2038 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
2039 uint64_t reserved_53_63 : 11;
2040 #endif /* Word 0 - End */
2041 } s;
2042 struct bdk_gpio_msix_vecx_addr_cn8
2043 {
2044 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2045 uint64_t reserved_49_63 : 15;
2046 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
2047 uint64_t reserved_1 : 1;
2048 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
2049 0 = This vector may be read or written by either secure or nonsecure states.
2050 1 = This vector's GPIO_MSIX_VEC()_ADDR, GPIO_MSIX_VEC()_CTL, and corresponding
2051 bit of GPIO_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
2052 by the nonsecure world.
2053
2054 If PCCPF_GPIO_VSEC_SCTL[MSIX_SEC] (for documentation, see PCCPF_XXX_VSEC_SCTL[MSIX_SEC])
2055 is set, all vectors are secure and function as if [SECVEC] was set. */
2056 #else /* Word 0 - Little Endian */
2057 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
2058 0 = This vector may be read or written by either secure or nonsecure states.
2059 1 = This vector's GPIO_MSIX_VEC()_ADDR, GPIO_MSIX_VEC()_CTL, and corresponding
2060 bit of GPIO_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
2061 by the nonsecure world.
2062
2063 If PCCPF_GPIO_VSEC_SCTL[MSIX_SEC] (for documentation, see PCCPF_XXX_VSEC_SCTL[MSIX_SEC])
2064 is set, all vectors are secure and function as if [SECVEC] was set. */
2065 uint64_t reserved_1 : 1;
2066 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
2067 uint64_t reserved_49_63 : 15;
2068 #endif /* Word 0 - End */
2069 } cn8;
2070 /* struct bdk_gpio_msix_vecx_addr_s cn9; */
2071 };
2072 typedef union bdk_gpio_msix_vecx_addr bdk_gpio_msix_vecx_addr_t;
2073
2074 static inline uint64_t BDK_GPIO_MSIX_VECX_ADDR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GPIO_MSIX_VECX_ADDR(unsigned long a)2075 static inline uint64_t BDK_GPIO_MSIX_VECX_ADDR(unsigned long a)
2076 {
2077 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=99))
2078 return 0x803000f00000ll + 0x10ll * ((a) & 0x7f);
2079 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=183))
2080 return 0x803000f00000ll + 0x10ll * ((a) & 0xff);
2081 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=149))
2082 return 0x803000f00000ll + 0x10ll * ((a) & 0xff);
2083 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=181))
2084 return 0x803000f00000ll + 0x10ll * ((a) & 0xff);
2085 __bdk_csr_fatal("GPIO_MSIX_VECX_ADDR", 1, a, 0, 0, 0);
2086 }
2087
2088 #define typedef_BDK_GPIO_MSIX_VECX_ADDR(a) bdk_gpio_msix_vecx_addr_t
2089 #define bustype_BDK_GPIO_MSIX_VECX_ADDR(a) BDK_CSR_TYPE_NCB
2090 #define basename_BDK_GPIO_MSIX_VECX_ADDR(a) "GPIO_MSIX_VECX_ADDR"
2091 #define device_bar_BDK_GPIO_MSIX_VECX_ADDR(a) 0x4 /* PF_BAR4 */
2092 #define busnum_BDK_GPIO_MSIX_VECX_ADDR(a) (a)
2093 #define arguments_BDK_GPIO_MSIX_VECX_ADDR(a) (a),-1,-1,-1
2094
2095 /**
2096 * Register (NCB) gpio_msix_vec#_ctl
2097 *
2098 * GPIO MSI-X Vector-Table Control and Data Register
2099 * This register is the MSI-X vector table, indexed by the GPIO_INT_VEC_E enumeration.
2100 *
2101 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2102 */
2103 union bdk_gpio_msix_vecx_ctl
2104 {
2105 uint64_t u;
2106 struct bdk_gpio_msix_vecx_ctl_s
2107 {
2108 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2109 uint64_t reserved_33_63 : 31;
2110 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
2111 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
2112 #else /* Word 0 - Little Endian */
2113 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
2114 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
2115 uint64_t reserved_33_63 : 31;
2116 #endif /* Word 0 - End */
2117 } s;
2118 struct bdk_gpio_msix_vecx_ctl_cn8
2119 {
2120 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2121 uint64_t reserved_33_63 : 31;
2122 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
2123 uint64_t reserved_20_31 : 12;
2124 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
2125 #else /* Word 0 - Little Endian */
2126 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
2127 uint64_t reserved_20_31 : 12;
2128 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
2129 uint64_t reserved_33_63 : 31;
2130 #endif /* Word 0 - End */
2131 } cn8;
2132 /* struct bdk_gpio_msix_vecx_ctl_s cn9; */
2133 };
2134 typedef union bdk_gpio_msix_vecx_ctl bdk_gpio_msix_vecx_ctl_t;
2135
2136 static inline uint64_t BDK_GPIO_MSIX_VECX_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GPIO_MSIX_VECX_CTL(unsigned long a)2137 static inline uint64_t BDK_GPIO_MSIX_VECX_CTL(unsigned long a)
2138 {
2139 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=99))
2140 return 0x803000f00008ll + 0x10ll * ((a) & 0x7f);
2141 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=183))
2142 return 0x803000f00008ll + 0x10ll * ((a) & 0xff);
2143 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=149))
2144 return 0x803000f00008ll + 0x10ll * ((a) & 0xff);
2145 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=181))
2146 return 0x803000f00008ll + 0x10ll * ((a) & 0xff);
2147 __bdk_csr_fatal("GPIO_MSIX_VECX_CTL", 1, a, 0, 0, 0);
2148 }
2149
2150 #define typedef_BDK_GPIO_MSIX_VECX_CTL(a) bdk_gpio_msix_vecx_ctl_t
2151 #define bustype_BDK_GPIO_MSIX_VECX_CTL(a) BDK_CSR_TYPE_NCB
2152 #define basename_BDK_GPIO_MSIX_VECX_CTL(a) "GPIO_MSIX_VECX_CTL"
2153 #define device_bar_BDK_GPIO_MSIX_VECX_CTL(a) 0x4 /* PF_BAR4 */
2154 #define busnum_BDK_GPIO_MSIX_VECX_CTL(a) (a)
2155 #define arguments_BDK_GPIO_MSIX_VECX_CTL(a) (a),-1,-1,-1
2156
2157 /**
2158 * Register (NCB) gpio_multi_cast
2159 *
2160 * GPIO Multicast Register
2161 * This register enables multicast GPIO interrupts.
2162 *
2163 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
2164 *
2165 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2166 */
2167 union bdk_gpio_multi_cast
2168 {
2169 uint64_t u;
2170 struct bdk_gpio_multi_cast_s
2171 {
2172 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2173 uint64_t reserved_1_63 : 63;
2174 uint64_t en : 1; /**< [ 0: 0](R/W) Enable GPIO interrupt multicast mode. When [EN] is set, GPIO\<7:4\> functions in multicast
2175 mode allowing these four GPIOs to interrupt multiple cores. Multicast functionality allows
2176 the GPIO to exist as per-core interrupts as opposed to a global interrupt. */
2177 #else /* Word 0 - Little Endian */
2178 uint64_t en : 1; /**< [ 0: 0](R/W) Enable GPIO interrupt multicast mode. When [EN] is set, GPIO\<7:4\> functions in multicast
2179 mode allowing these four GPIOs to interrupt multiple cores. Multicast functionality allows
2180 the GPIO to exist as per-core interrupts as opposed to a global interrupt. */
2181 uint64_t reserved_1_63 : 63;
2182 #endif /* Word 0 - End */
2183 } s;
2184 /* struct bdk_gpio_multi_cast_s cn; */
2185 };
2186 typedef union bdk_gpio_multi_cast bdk_gpio_multi_cast_t;
2187
2188 #define BDK_GPIO_MULTI_CAST BDK_GPIO_MULTI_CAST_FUNC()
2189 static inline uint64_t BDK_GPIO_MULTI_CAST_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_MULTI_CAST_FUNC(void)2190 static inline uint64_t BDK_GPIO_MULTI_CAST_FUNC(void)
2191 {
2192 return 0x803000000018ll;
2193 }
2194
2195 #define typedef_BDK_GPIO_MULTI_CAST bdk_gpio_multi_cast_t
2196 #define bustype_BDK_GPIO_MULTI_CAST BDK_CSR_TYPE_NCB
2197 #define basename_BDK_GPIO_MULTI_CAST "GPIO_MULTI_CAST"
2198 #define device_bar_BDK_GPIO_MULTI_CAST 0x0 /* PF_BAR0 */
2199 #define busnum_BDK_GPIO_MULTI_CAST 0
2200 #define arguments_BDK_GPIO_MULTI_CAST -1,-1,-1,-1
2201
2202 /**
2203 * Register (NCB) gpio_ocla_exten_trig
2204 *
2205 * GPIO OCLA External Trigger Register
2206 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
2207 *
2208 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2209 */
2210 union bdk_gpio_ocla_exten_trig
2211 {
2212 uint64_t u;
2213 struct bdk_gpio_ocla_exten_trig_s
2214 {
2215 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2216 uint64_t reserved_1_63 : 63;
2217 uint64_t m_trig : 1; /**< [ 0: 0](R/W) Manual trigger. Assert the OCLA trigger for GPIO-based triggering. This manual
2218 trigger is ORed with the optional GPIO input pin selected with
2219 GPIO_BIT_CFG()[PIN_SEL] = GPIO_PIN_SEL_E::OCLA_EXT_TRIGGER. */
2220 #else /* Word 0 - Little Endian */
2221 uint64_t m_trig : 1; /**< [ 0: 0](R/W) Manual trigger. Assert the OCLA trigger for GPIO-based triggering. This manual
2222 trigger is ORed with the optional GPIO input pin selected with
2223 GPIO_BIT_CFG()[PIN_SEL] = GPIO_PIN_SEL_E::OCLA_EXT_TRIGGER. */
2224 uint64_t reserved_1_63 : 63;
2225 #endif /* Word 0 - End */
2226 } s;
2227 /* struct bdk_gpio_ocla_exten_trig_s cn8; */
2228 struct bdk_gpio_ocla_exten_trig_cn9
2229 {
2230 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2231 uint64_t reserved_1_63 : 63;
2232 uint64_t m_trig : 1; /**< [ 0: 0](R/W) Manual trigger. Assert the OCLA trigger for GPIO-based triggering. This manual
2233 trigger is ORed with the optional GPIO input pin permitted with
2234 GPIO_BIT_CFG()[PIN_SEL] = GPIO_PIN_SEL_E::OCLA_EXT_TRIGGER. */
2235 #else /* Word 0 - Little Endian */
2236 uint64_t m_trig : 1; /**< [ 0: 0](R/W) Manual trigger. Assert the OCLA trigger for GPIO-based triggering. This manual
2237 trigger is ORed with the optional GPIO input pin permitted with
2238 GPIO_BIT_CFG()[PIN_SEL] = GPIO_PIN_SEL_E::OCLA_EXT_TRIGGER. */
2239 uint64_t reserved_1_63 : 63;
2240 #endif /* Word 0 - End */
2241 } cn9;
2242 };
2243 typedef union bdk_gpio_ocla_exten_trig bdk_gpio_ocla_exten_trig_t;
2244
2245 #define BDK_GPIO_OCLA_EXTEN_TRIG BDK_GPIO_OCLA_EXTEN_TRIG_FUNC()
2246 static inline uint64_t BDK_GPIO_OCLA_EXTEN_TRIG_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_OCLA_EXTEN_TRIG_FUNC(void)2247 static inline uint64_t BDK_GPIO_OCLA_EXTEN_TRIG_FUNC(void)
2248 {
2249 return 0x803000000020ll;
2250 }
2251
2252 #define typedef_BDK_GPIO_OCLA_EXTEN_TRIG bdk_gpio_ocla_exten_trig_t
2253 #define bustype_BDK_GPIO_OCLA_EXTEN_TRIG BDK_CSR_TYPE_NCB
2254 #define basename_BDK_GPIO_OCLA_EXTEN_TRIG "GPIO_OCLA_EXTEN_TRIG"
2255 #define device_bar_BDK_GPIO_OCLA_EXTEN_TRIG 0x0 /* PF_BAR0 */
2256 #define busnum_BDK_GPIO_OCLA_EXTEN_TRIG 0
2257 #define arguments_BDK_GPIO_OCLA_EXTEN_TRIG -1,-1,-1,-1
2258
2259 /**
2260 * Register (NCB) gpio_permit
2261 *
2262 * GPIO Permit Register
2263 * This register determines which requestor(s) are permitted to access which GPIO global
2264 * registers.
2265 *
2266 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
2267 * (That is, only the GPIO_PERMIT permitted agent can change the permission settings of
2268 * all requestors.)
2269 *
2270 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2271 */
2272 union bdk_gpio_permit
2273 {
2274 uint64_t u;
2275 struct bdk_gpio_permit_s
2276 {
2277 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2278 uint64_t reserved_4_63 : 60;
2279 uint64_t permitdis : 4; /**< [ 3: 0](R/W) Each bit, if set, disables the given requestor from accessing GPIO global registers.
2280 If a disabled requestor makes a request, the access becomes read-zero/write ignored.
2281 \<0\> = Disable AP/NCSI/JTAG (non MCP/SCP) secure world from accessing GPIO global registers.
2282 \<1\> = Disable AP/NCSI/JTAG (non MCP/SCP) nonsecure world from accessing GPIO global registers.
2283 \<2\> = Disable XCP0 (SCP) from accessing GPIO global registers.
2284 \<3\> = Disable XCP1 (MCP) from accessing GPIO global registers. */
2285 #else /* Word 0 - Little Endian */
2286 uint64_t permitdis : 4; /**< [ 3: 0](R/W) Each bit, if set, disables the given requestor from accessing GPIO global registers.
2287 If a disabled requestor makes a request, the access becomes read-zero/write ignored.
2288 \<0\> = Disable AP/NCSI/JTAG (non MCP/SCP) secure world from accessing GPIO global registers.
2289 \<1\> = Disable AP/NCSI/JTAG (non MCP/SCP) nonsecure world from accessing GPIO global registers.
2290 \<2\> = Disable XCP0 (SCP) from accessing GPIO global registers.
2291 \<3\> = Disable XCP1 (MCP) from accessing GPIO global registers. */
2292 uint64_t reserved_4_63 : 60;
2293 #endif /* Word 0 - End */
2294 } s;
2295 /* struct bdk_gpio_permit_s cn; */
2296 };
2297 typedef union bdk_gpio_permit bdk_gpio_permit_t;
2298
2299 #define BDK_GPIO_PERMIT BDK_GPIO_PERMIT_FUNC()
2300 static inline uint64_t BDK_GPIO_PERMIT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_PERMIT_FUNC(void)2301 static inline uint64_t BDK_GPIO_PERMIT_FUNC(void)
2302 {
2303 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
2304 return 0x803000001500ll;
2305 __bdk_csr_fatal("GPIO_PERMIT", 0, 0, 0, 0, 0);
2306 }
2307
2308 #define typedef_BDK_GPIO_PERMIT bdk_gpio_permit_t
2309 #define bustype_BDK_GPIO_PERMIT BDK_CSR_TYPE_NCB
2310 #define basename_BDK_GPIO_PERMIT "GPIO_PERMIT"
2311 #define device_bar_BDK_GPIO_PERMIT 0x0 /* PF_BAR0 */
2312 #define busnum_BDK_GPIO_PERMIT 0
2313 #define arguments_BDK_GPIO_PERMIT -1,-1,-1,-1
2314
2315 /**
2316 * Register (NCB) gpio_pkg_ver
2317 *
2318 * Chip Package Version Register
2319 * This register reads the package version.
2320 */
2321 union bdk_gpio_pkg_ver
2322 {
2323 uint64_t u;
2324 struct bdk_gpio_pkg_ver_s
2325 {
2326 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2327 uint64_t reserved_3_63 : 61;
2328 uint64_t pkg_ver : 3; /**< [ 2: 0](RO/H) Reads the package version straps, which are set by the package.
2329 0x0 = 47.5 x 47.5mm package non-SWP.
2330 0x1 = 40 x 40mm package.
2331 0x2 = 47.5 x 47.5mm package with SWP. */
2332 #else /* Word 0 - Little Endian */
2333 uint64_t pkg_ver : 3; /**< [ 2: 0](RO/H) Reads the package version straps, which are set by the package.
2334 0x0 = 47.5 x 47.5mm package non-SWP.
2335 0x1 = 40 x 40mm package.
2336 0x2 = 47.5 x 47.5mm package with SWP. */
2337 uint64_t reserved_3_63 : 61;
2338 #endif /* Word 0 - End */
2339 } s;
2340 /* struct bdk_gpio_pkg_ver_s cn; */
2341 };
2342 typedef union bdk_gpio_pkg_ver bdk_gpio_pkg_ver_t;
2343
2344 #define BDK_GPIO_PKG_VER BDK_GPIO_PKG_VER_FUNC()
2345 static inline uint64_t BDK_GPIO_PKG_VER_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_PKG_VER_FUNC(void)2346 static inline uint64_t BDK_GPIO_PKG_VER_FUNC(void)
2347 {
2348 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
2349 return 0x803000001610ll;
2350 __bdk_csr_fatal("GPIO_PKG_VER", 0, 0, 0, 0, 0);
2351 }
2352
2353 #define typedef_BDK_GPIO_PKG_VER bdk_gpio_pkg_ver_t
2354 #define bustype_BDK_GPIO_PKG_VER BDK_CSR_TYPE_NCB
2355 #define basename_BDK_GPIO_PKG_VER "GPIO_PKG_VER"
2356 #define device_bar_BDK_GPIO_PKG_VER 0x0 /* PF_BAR0 */
2357 #define busnum_BDK_GPIO_PKG_VER 0
2358 #define arguments_BDK_GPIO_PKG_VER -1,-1,-1,-1
2359
2360 /**
2361 * Register (NCB) gpio_pspi_ctl
2362 *
2363 * GPIO Expansion ROM SPI Control Register
2364 * This register is only accessible to the requestor(s) permitted with GPIO_PERMIT.
2365 *
2366 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2367 */
2368 union bdk_gpio_pspi_ctl
2369 {
2370 uint64_t u;
2371 struct bdk_gpio_pspi_ctl_s
2372 {
2373 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2374 uint64_t reserved_1_63 : 63;
2375 uint64_t pspi_gpio : 1; /**< [ 0: 0](R/W) PSPI GPIO reset override.
2376 When set, this field causes the GPIO pins 39-43 to maintain their
2377 values through a chip reset. This bit is typically set when PCIe Expansion RIM
2378 is required and a PEM has been configured as an end point.
2379 When cleared, the GPIOs are reset during a chip domain reset.
2380 This register is reset only on a cold domain reset. */
2381 #else /* Word 0 - Little Endian */
2382 uint64_t pspi_gpio : 1; /**< [ 0: 0](R/W) PSPI GPIO reset override.
2383 When set, this field causes the GPIO pins 39-43 to maintain their
2384 values through a chip reset. This bit is typically set when PCIe Expansion RIM
2385 is required and a PEM has been configured as an end point.
2386 When cleared, the GPIOs are reset during a chip domain reset.
2387 This register is reset only on a cold domain reset. */
2388 uint64_t reserved_1_63 : 63;
2389 #endif /* Word 0 - End */
2390 } s;
2391 /* struct bdk_gpio_pspi_ctl_s cn; */
2392 };
2393 typedef union bdk_gpio_pspi_ctl bdk_gpio_pspi_ctl_t;
2394
2395 #define BDK_GPIO_PSPI_CTL BDK_GPIO_PSPI_CTL_FUNC()
2396 static inline uint64_t BDK_GPIO_PSPI_CTL_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_PSPI_CTL_FUNC(void)2397 static inline uint64_t BDK_GPIO_PSPI_CTL_FUNC(void)
2398 {
2399 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
2400 return 0x803000000088ll;
2401 __bdk_csr_fatal("GPIO_PSPI_CTL", 0, 0, 0, 0, 0);
2402 }
2403
2404 #define typedef_BDK_GPIO_PSPI_CTL bdk_gpio_pspi_ctl_t
2405 #define bustype_BDK_GPIO_PSPI_CTL BDK_CSR_TYPE_NCB
2406 #define basename_BDK_GPIO_PSPI_CTL "GPIO_PSPI_CTL"
2407 #define device_bar_BDK_GPIO_PSPI_CTL 0x0 /* PF_BAR0 */
2408 #define busnum_BDK_GPIO_PSPI_CTL 0
2409 #define arguments_BDK_GPIO_PSPI_CTL -1,-1,-1,-1
2410
2411 /**
2412 * Register (NCB) gpio_rx1_dat
2413 *
2414 * GPIO Receive Data Extension Register
2415 * See GPIO_RX_DAT.
2416 */
2417 union bdk_gpio_rx1_dat
2418 {
2419 uint64_t u;
2420 struct bdk_gpio_rx1_dat_s
2421 {
2422 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2423 uint64_t reserved_32_63 : 32;
2424 uint64_t dat : 32; /**< [ 31: 0](RO/H) GPIO read data. */
2425 #else /* Word 0 - Little Endian */
2426 uint64_t dat : 32; /**< [ 31: 0](RO/H) GPIO read data. */
2427 uint64_t reserved_32_63 : 32;
2428 #endif /* Word 0 - End */
2429 } s;
2430 struct bdk_gpio_rx1_dat_cn81xx
2431 {
2432 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2433 uint64_t reserved_29_63 : 35;
2434 uint64_t dat : 29; /**< [ 28: 0](RO/H) GPIO read data. */
2435 #else /* Word 0 - Little Endian */
2436 uint64_t dat : 29; /**< [ 28: 0](RO/H) GPIO read data. */
2437 uint64_t reserved_29_63 : 35;
2438 #endif /* Word 0 - End */
2439 } cn81xx;
2440 struct bdk_gpio_rx1_dat_cn83xx
2441 {
2442 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2443 uint64_t reserved_16_63 : 48;
2444 uint64_t dat : 16; /**< [ 15: 0](RO/H) GPIO read data. */
2445 #else /* Word 0 - Little Endian */
2446 uint64_t dat : 16; /**< [ 15: 0](RO/H) GPIO read data. */
2447 uint64_t reserved_16_63 : 48;
2448 #endif /* Word 0 - End */
2449 } cn83xx;
2450 struct bdk_gpio_rx1_dat_cn9
2451 {
2452 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2453 uint64_t reserved_32_63 : 32;
2454 uint64_t dat : 32; /**< [ 31: 0](RO/H) GPIO read data. Unimplemented pins bits read as zero. */
2455 #else /* Word 0 - Little Endian */
2456 uint64_t dat : 32; /**< [ 31: 0](RO/H) GPIO read data. Unimplemented pins bits read as zero. */
2457 uint64_t reserved_32_63 : 32;
2458 #endif /* Word 0 - End */
2459 } cn9;
2460 };
2461 typedef union bdk_gpio_rx1_dat bdk_gpio_rx1_dat_t;
2462
2463 #define BDK_GPIO_RX1_DAT BDK_GPIO_RX1_DAT_FUNC()
2464 static inline uint64_t BDK_GPIO_RX1_DAT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_RX1_DAT_FUNC(void)2465 static inline uint64_t BDK_GPIO_RX1_DAT_FUNC(void)
2466 {
2467 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX))
2468 return 0x803000001400ll;
2469 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX))
2470 return 0x803000001400ll;
2471 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
2472 return 0x803000001400ll;
2473 __bdk_csr_fatal("GPIO_RX1_DAT", 0, 0, 0, 0, 0);
2474 }
2475
2476 #define typedef_BDK_GPIO_RX1_DAT bdk_gpio_rx1_dat_t
2477 #define bustype_BDK_GPIO_RX1_DAT BDK_CSR_TYPE_NCB
2478 #define basename_BDK_GPIO_RX1_DAT "GPIO_RX1_DAT"
2479 #define device_bar_BDK_GPIO_RX1_DAT 0x0 /* PF_BAR0 */
2480 #define busnum_BDK_GPIO_RX1_DAT 0
2481 #define arguments_BDK_GPIO_RX1_DAT -1,-1,-1,-1
2482
2483 /**
2484 * Register (NCB) gpio_rx_dat
2485 *
2486 * GPIO Receive Data Register
2487 * This register contains the state of the GPIO pins, which is after glitch filter and XOR
2488 * inverter (GPIO_BIT_CFG()[PIN_XOR]). GPIO inputs always report to GPIO_RX_DAT despite of
2489 * the value of GPIO_BIT_CFG()[PIN_SEL].
2490 * GPIO_RX_DAT reads GPIO input data for the first 64 GPIOs, and GPIO_RX1_DAT the remainder.
2491 *
2492 * Each bit in this register is only accessible to the requestor(s) permitted with
2493 * GPIO_BIT_PERMIT(), but error will not be reported when there are bits are not
2494 * permitted by GPIO_BIT_PERMIT().
2495 *
2496 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2497 */
2498 union bdk_gpio_rx_dat
2499 {
2500 uint64_t u;
2501 struct bdk_gpio_rx_dat_s
2502 {
2503 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2504 uint64_t dat : 64; /**< [ 63: 0](RO/H) GPIO read data. */
2505 #else /* Word 0 - Little Endian */
2506 uint64_t dat : 64; /**< [ 63: 0](RO/H) GPIO read data. */
2507 #endif /* Word 0 - End */
2508 } s;
2509 /* struct bdk_gpio_rx_dat_s cn9; */
2510 struct bdk_gpio_rx_dat_cn81xx
2511 {
2512 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2513 uint64_t reserved_48_63 : 16;
2514 uint64_t dat : 48; /**< [ 47: 0](RO/H) GPIO read data. */
2515 #else /* Word 0 - Little Endian */
2516 uint64_t dat : 48; /**< [ 47: 0](RO/H) GPIO read data. */
2517 uint64_t reserved_48_63 : 16;
2518 #endif /* Word 0 - End */
2519 } cn81xx;
2520 struct bdk_gpio_rx_dat_cn88xx
2521 {
2522 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2523 uint64_t reserved_51_63 : 13;
2524 uint64_t dat : 51; /**< [ 50: 0](RO/H) GPIO read data. */
2525 #else /* Word 0 - Little Endian */
2526 uint64_t dat : 51; /**< [ 50: 0](RO/H) GPIO read data. */
2527 uint64_t reserved_51_63 : 13;
2528 #endif /* Word 0 - End */
2529 } cn88xx;
2530 /* struct bdk_gpio_rx_dat_s cn83xx; */
2531 };
2532 typedef union bdk_gpio_rx_dat bdk_gpio_rx_dat_t;
2533
2534 #define BDK_GPIO_RX_DAT BDK_GPIO_RX_DAT_FUNC()
2535 static inline uint64_t BDK_GPIO_RX_DAT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_RX_DAT_FUNC(void)2536 static inline uint64_t BDK_GPIO_RX_DAT_FUNC(void)
2537 {
2538 return 0x803000000000ll;
2539 }
2540
2541 #define typedef_BDK_GPIO_RX_DAT bdk_gpio_rx_dat_t
2542 #define bustype_BDK_GPIO_RX_DAT BDK_CSR_TYPE_NCB
2543 #define basename_BDK_GPIO_RX_DAT "GPIO_RX_DAT"
2544 #define device_bar_BDK_GPIO_RX_DAT 0x0 /* PF_BAR0 */
2545 #define busnum_BDK_GPIO_RX_DAT 0
2546 #define arguments_BDK_GPIO_RX_DAT -1,-1,-1,-1
2547
2548 /**
2549 * Register (NCB) gpio_strap
2550 *
2551 * GPIO Strap Value Register
2552 * This register contains the first 64 GPIO strap data captured at the rising edge of DC_OK.
2553 * GPIO_STRAP1 contains the remaining GPIOs.
2554 *
2555 * This register is accessible to all requestors (regardless of GPIO_PERMIT).
2556 *
2557 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2558 */
2559 union bdk_gpio_strap
2560 {
2561 uint64_t u;
2562 struct bdk_gpio_strap_s
2563 {
2564 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2565 uint64_t strap : 64; /**< [ 63: 0](RO/H) GPIO strap data. */
2566 #else /* Word 0 - Little Endian */
2567 uint64_t strap : 64; /**< [ 63: 0](RO/H) GPIO strap data. */
2568 #endif /* Word 0 - End */
2569 } s;
2570 struct bdk_gpio_strap_cn9
2571 {
2572 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2573 uint64_t strap : 64; /**< [ 63: 0](RO/H) GPIO strap data of GPIO pins less than 64. Unimplemented pins bits read as 0. */
2574 #else /* Word 0 - Little Endian */
2575 uint64_t strap : 64; /**< [ 63: 0](RO/H) GPIO strap data of GPIO pins less than 64. Unimplemented pins bits read as 0. */
2576 #endif /* Word 0 - End */
2577 } cn9;
2578 struct bdk_gpio_strap_cn81xx
2579 {
2580 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2581 uint64_t reserved_48_63 : 16;
2582 uint64_t strap : 48; /**< [ 47: 0](RO/H) GPIO strap data of GPIO pins less than 64. Unimplemented pins bits read as 0. */
2583 #else /* Word 0 - Little Endian */
2584 uint64_t strap : 48; /**< [ 47: 0](RO/H) GPIO strap data of GPIO pins less than 64. Unimplemented pins bits read as 0. */
2585 uint64_t reserved_48_63 : 16;
2586 #endif /* Word 0 - End */
2587 } cn81xx;
2588 struct bdk_gpio_strap_cn88xx
2589 {
2590 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2591 uint64_t reserved_51_63 : 13;
2592 uint64_t strap : 51; /**< [ 50: 0](RO/H) GPIO strap data. */
2593 #else /* Word 0 - Little Endian */
2594 uint64_t strap : 51; /**< [ 50: 0](RO/H) GPIO strap data. */
2595 uint64_t reserved_51_63 : 13;
2596 #endif /* Word 0 - End */
2597 } cn88xx;
2598 /* struct bdk_gpio_strap_cn9 cn83xx; */
2599 };
2600 typedef union bdk_gpio_strap bdk_gpio_strap_t;
2601
2602 #define BDK_GPIO_STRAP BDK_GPIO_STRAP_FUNC()
2603 static inline uint64_t BDK_GPIO_STRAP_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_STRAP_FUNC(void)2604 static inline uint64_t BDK_GPIO_STRAP_FUNC(void)
2605 {
2606 return 0x803000000028ll;
2607 }
2608
2609 #define typedef_BDK_GPIO_STRAP bdk_gpio_strap_t
2610 #define bustype_BDK_GPIO_STRAP BDK_CSR_TYPE_NCB
2611 #define basename_BDK_GPIO_STRAP "GPIO_STRAP"
2612 #define device_bar_BDK_GPIO_STRAP 0x0 /* PF_BAR0 */
2613 #define busnum_BDK_GPIO_STRAP 0
2614 #define arguments_BDK_GPIO_STRAP -1,-1,-1,-1
2615
2616 /**
2617 * Register (NCB) gpio_strap1
2618 *
2619 * GPIO Strap Value Register
2620 * See GPIO_STRAP.
2621 */
2622 union bdk_gpio_strap1
2623 {
2624 uint64_t u;
2625 struct bdk_gpio_strap1_s
2626 {
2627 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2628 uint64_t reserved_32_63 : 32;
2629 uint64_t strap : 32; /**< [ 31: 0](RO/H) GPIO strap data of GPIO pins 64-79. Unimplemented pins bits read as 0. */
2630 #else /* Word 0 - Little Endian */
2631 uint64_t strap : 32; /**< [ 31: 0](RO/H) GPIO strap data of GPIO pins 64-79. Unimplemented pins bits read as 0. */
2632 uint64_t reserved_32_63 : 32;
2633 #endif /* Word 0 - End */
2634 } s;
2635 struct bdk_gpio_strap1_cn81xx
2636 {
2637 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2638 uint64_t reserved_29_63 : 35;
2639 uint64_t strap : 29; /**< [ 28: 0](RO/H) GPIO strap data of GPIO pins less than 64. Unimplemented pins bits read as 0. */
2640 #else /* Word 0 - Little Endian */
2641 uint64_t strap : 29; /**< [ 28: 0](RO/H) GPIO strap data of GPIO pins less than 64. Unimplemented pins bits read as 0. */
2642 uint64_t reserved_29_63 : 35;
2643 #endif /* Word 0 - End */
2644 } cn81xx;
2645 struct bdk_gpio_strap1_cn83xx
2646 {
2647 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2648 uint64_t reserved_16_63 : 48;
2649 uint64_t strap : 16; /**< [ 15: 0](RO/H) GPIO strap data of GPIO pins 64-79. Unimplemented pins bits read as 0. */
2650 #else /* Word 0 - Little Endian */
2651 uint64_t strap : 16; /**< [ 15: 0](RO/H) GPIO strap data of GPIO pins 64-79. Unimplemented pins bits read as 0. */
2652 uint64_t reserved_16_63 : 48;
2653 #endif /* Word 0 - End */
2654 } cn83xx;
2655 struct bdk_gpio_strap1_cn9
2656 {
2657 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2658 uint64_t reserved_32_63 : 32;
2659 uint64_t strap : 32; /**< [ 31: 0](RO/H) GPIO strap data of GPIO pins 64 and above. Unimplemented pins bits read as 0. */
2660 #else /* Word 0 - Little Endian */
2661 uint64_t strap : 32; /**< [ 31: 0](RO/H) GPIO strap data of GPIO pins 64 and above. Unimplemented pins bits read as 0. */
2662 uint64_t reserved_32_63 : 32;
2663 #endif /* Word 0 - End */
2664 } cn9;
2665 };
2666 typedef union bdk_gpio_strap1 bdk_gpio_strap1_t;
2667
2668 #define BDK_GPIO_STRAP1 BDK_GPIO_STRAP1_FUNC()
2669 static inline uint64_t BDK_GPIO_STRAP1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_STRAP1_FUNC(void)2670 static inline uint64_t BDK_GPIO_STRAP1_FUNC(void)
2671 {
2672 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX))
2673 return 0x803000001418ll;
2674 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX))
2675 return 0x803000001418ll;
2676 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
2677 return 0x803000001418ll;
2678 __bdk_csr_fatal("GPIO_STRAP1", 0, 0, 0, 0, 0);
2679 }
2680
2681 #define typedef_BDK_GPIO_STRAP1 bdk_gpio_strap1_t
2682 #define bustype_BDK_GPIO_STRAP1 BDK_CSR_TYPE_NCB
2683 #define basename_BDK_GPIO_STRAP1 "GPIO_STRAP1"
2684 #define device_bar_BDK_GPIO_STRAP1 0x0 /* PF_BAR0 */
2685 #define busnum_BDK_GPIO_STRAP1 0
2686 #define arguments_BDK_GPIO_STRAP1 -1,-1,-1,-1
2687
2688 /**
2689 * Register (NCB) gpio_tx1_clr
2690 *
2691 * GPIO Transmit Clear Mask Register
2692 * See GPIO_TX_CLR.
2693 */
2694 union bdk_gpio_tx1_clr
2695 {
2696 uint64_t u;
2697 struct bdk_gpio_tx1_clr_s
2698 {
2699 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2700 uint64_t reserved_32_63 : 32;
2701 uint64_t clr : 32; /**< [ 31: 0](R/W1C/H) Clear mask. Bit mask to indicate which GPIO_TX1_DAT bits to set to 0. When read, CLR
2702 returns the GPIO_TX1_DAT storage. */
2703 #else /* Word 0 - Little Endian */
2704 uint64_t clr : 32; /**< [ 31: 0](R/W1C/H) Clear mask. Bit mask to indicate which GPIO_TX1_DAT bits to set to 0. When read, CLR
2705 returns the GPIO_TX1_DAT storage. */
2706 uint64_t reserved_32_63 : 32;
2707 #endif /* Word 0 - End */
2708 } s;
2709 struct bdk_gpio_tx1_clr_cn81xx
2710 {
2711 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2712 uint64_t reserved_29_63 : 35;
2713 uint64_t clr : 29; /**< [ 28: 0](R/W1C/H) Clear mask. Bit mask to indicate which GPIO_TX1_DAT bits to set to 0. When read, CLR
2714 returns the GPIO_TX1_DAT storage. */
2715 #else /* Word 0 - Little Endian */
2716 uint64_t clr : 29; /**< [ 28: 0](R/W1C/H) Clear mask. Bit mask to indicate which GPIO_TX1_DAT bits to set to 0. When read, CLR
2717 returns the GPIO_TX1_DAT storage. */
2718 uint64_t reserved_29_63 : 35;
2719 #endif /* Word 0 - End */
2720 } cn81xx;
2721 struct bdk_gpio_tx1_clr_cn83xx
2722 {
2723 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2724 uint64_t reserved_16_63 : 48;
2725 uint64_t clr : 16; /**< [ 15: 0](R/W1C/H) Clear mask. Bit mask to indicate which GPIO_TX1_DAT bits to set to 0. When read, CLR
2726 returns the GPIO_TX1_DAT storage. */
2727 #else /* Word 0 - Little Endian */
2728 uint64_t clr : 16; /**< [ 15: 0](R/W1C/H) Clear mask. Bit mask to indicate which GPIO_TX1_DAT bits to set to 0. When read, CLR
2729 returns the GPIO_TX1_DAT storage. */
2730 uint64_t reserved_16_63 : 48;
2731 #endif /* Word 0 - End */
2732 } cn83xx;
2733 struct bdk_gpio_tx1_clr_cn9
2734 {
2735 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2736 uint64_t reserved_32_63 : 32;
2737 uint64_t clr : 32; /**< [ 31: 0](R/W1C/H) Clear mask. Bit mask to indicate which GPIO_TX1_DAT bits to set to 0. When read, CLR
2738 returns the GPIO_TX1_DAT storage. Unimplemented pins bits read as 0. */
2739 #else /* Word 0 - Little Endian */
2740 uint64_t clr : 32; /**< [ 31: 0](R/W1C/H) Clear mask. Bit mask to indicate which GPIO_TX1_DAT bits to set to 0. When read, CLR
2741 returns the GPIO_TX1_DAT storage. Unimplemented pins bits read as 0. */
2742 uint64_t reserved_32_63 : 32;
2743 #endif /* Word 0 - End */
2744 } cn9;
2745 };
2746 typedef union bdk_gpio_tx1_clr bdk_gpio_tx1_clr_t;
2747
2748 #define BDK_GPIO_TX1_CLR BDK_GPIO_TX1_CLR_FUNC()
2749 static inline uint64_t BDK_GPIO_TX1_CLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_TX1_CLR_FUNC(void)2750 static inline uint64_t BDK_GPIO_TX1_CLR_FUNC(void)
2751 {
2752 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX))
2753 return 0x803000001410ll;
2754 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX))
2755 return 0x803000001410ll;
2756 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
2757 return 0x803000001410ll;
2758 __bdk_csr_fatal("GPIO_TX1_CLR", 0, 0, 0, 0, 0);
2759 }
2760
2761 #define typedef_BDK_GPIO_TX1_CLR bdk_gpio_tx1_clr_t
2762 #define bustype_BDK_GPIO_TX1_CLR BDK_CSR_TYPE_NCB
2763 #define basename_BDK_GPIO_TX1_CLR "GPIO_TX1_CLR"
2764 #define device_bar_BDK_GPIO_TX1_CLR 0x0 /* PF_BAR0 */
2765 #define busnum_BDK_GPIO_TX1_CLR 0
2766 #define arguments_BDK_GPIO_TX1_CLR -1,-1,-1,-1
2767
2768 /**
2769 * Register (NCB) gpio_tx1_set
2770 *
2771 * GPIO Transmit Set Mask Register
2772 * See GPIO_TX_SET.
2773 */
2774 union bdk_gpio_tx1_set
2775 {
2776 uint64_t u;
2777 struct bdk_gpio_tx1_set_s
2778 {
2779 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2780 uint64_t reserved_32_63 : 32;
2781 uint64_t set : 32; /**< [ 31: 0](R/W1S/H) Set mask. Bit mask to indicate which GPIO_TX1_DAT bits to set to 1. When read, SET
2782 returns the GPIO_TX1_DAT storage. */
2783 #else /* Word 0 - Little Endian */
2784 uint64_t set : 32; /**< [ 31: 0](R/W1S/H) Set mask. Bit mask to indicate which GPIO_TX1_DAT bits to set to 1. When read, SET
2785 returns the GPIO_TX1_DAT storage. */
2786 uint64_t reserved_32_63 : 32;
2787 #endif /* Word 0 - End */
2788 } s;
2789 struct bdk_gpio_tx1_set_cn81xx
2790 {
2791 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2792 uint64_t reserved_29_63 : 35;
2793 uint64_t set : 29; /**< [ 28: 0](R/W1S/H) Set mask. Bit mask to indicate which GPIO_TX1_DAT bits to set to 1. When read, SET
2794 returns the GPIO_TX1_DAT storage. */
2795 #else /* Word 0 - Little Endian */
2796 uint64_t set : 29; /**< [ 28: 0](R/W1S/H) Set mask. Bit mask to indicate which GPIO_TX1_DAT bits to set to 1. When read, SET
2797 returns the GPIO_TX1_DAT storage. */
2798 uint64_t reserved_29_63 : 35;
2799 #endif /* Word 0 - End */
2800 } cn81xx;
2801 struct bdk_gpio_tx1_set_cn83xx
2802 {
2803 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2804 uint64_t reserved_16_63 : 48;
2805 uint64_t set : 16; /**< [ 15: 0](R/W1S/H) Set mask. Bit mask to indicate which GPIO_TX1_DAT bits to set to 1. When read, SET
2806 returns the GPIO_TX1_DAT storage. */
2807 #else /* Word 0 - Little Endian */
2808 uint64_t set : 16; /**< [ 15: 0](R/W1S/H) Set mask. Bit mask to indicate which GPIO_TX1_DAT bits to set to 1. When read, SET
2809 returns the GPIO_TX1_DAT storage. */
2810 uint64_t reserved_16_63 : 48;
2811 #endif /* Word 0 - End */
2812 } cn83xx;
2813 struct bdk_gpio_tx1_set_cn9
2814 {
2815 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2816 uint64_t reserved_32_63 : 32;
2817 uint64_t set : 32; /**< [ 31: 0](R/W1S/H) Set mask. Bit mask to indicate which GPIO_TX1_DAT bits to set to 1. When read, SET
2818 returns the GPIO_TX1_DAT storage. Unimplemented pins bits read as 0. */
2819 #else /* Word 0 - Little Endian */
2820 uint64_t set : 32; /**< [ 31: 0](R/W1S/H) Set mask. Bit mask to indicate which GPIO_TX1_DAT bits to set to 1. When read, SET
2821 returns the GPIO_TX1_DAT storage. Unimplemented pins bits read as 0. */
2822 uint64_t reserved_32_63 : 32;
2823 #endif /* Word 0 - End */
2824 } cn9;
2825 };
2826 typedef union bdk_gpio_tx1_set bdk_gpio_tx1_set_t;
2827
2828 #define BDK_GPIO_TX1_SET BDK_GPIO_TX1_SET_FUNC()
2829 static inline uint64_t BDK_GPIO_TX1_SET_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_TX1_SET_FUNC(void)2830 static inline uint64_t BDK_GPIO_TX1_SET_FUNC(void)
2831 {
2832 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX))
2833 return 0x803000001408ll;
2834 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX))
2835 return 0x803000001408ll;
2836 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
2837 return 0x803000001408ll;
2838 __bdk_csr_fatal("GPIO_TX1_SET", 0, 0, 0, 0, 0);
2839 }
2840
2841 #define typedef_BDK_GPIO_TX1_SET bdk_gpio_tx1_set_t
2842 #define bustype_BDK_GPIO_TX1_SET BDK_CSR_TYPE_NCB
2843 #define basename_BDK_GPIO_TX1_SET "GPIO_TX1_SET"
2844 #define device_bar_BDK_GPIO_TX1_SET 0x0 /* PF_BAR0 */
2845 #define busnum_BDK_GPIO_TX1_SET 0
2846 #define arguments_BDK_GPIO_TX1_SET -1,-1,-1,-1
2847
2848 /**
2849 * Register (NCB) gpio_tx_clr
2850 *
2851 * GPIO Transmit Clear Mask Register
2852 * This register clears GPIO output data for the first 64 GPIOs, and GPIO_TX1_CLR the
2853 * remainder.
2854 *
2855 * Each bit in this register is only accessible to the requestor(s) permitted with
2856 * GPIO_BIT_PERMIT(), but error will not be reported when there are bits are not
2857 * permitted by GPIO_BIT_PERMIT().
2858 *
2859 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2860 */
2861 union bdk_gpio_tx_clr
2862 {
2863 uint64_t u;
2864 struct bdk_gpio_tx_clr_s
2865 {
2866 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2867 uint64_t clr : 64; /**< [ 63: 0](R/W1C/H) Clear mask. Bit mask to indicate which GPIO_TX_DAT bits to set to 0. When read, [CLR]
2868 returns the GPIO_TX_DAT storage. */
2869 #else /* Word 0 - Little Endian */
2870 uint64_t clr : 64; /**< [ 63: 0](R/W1C/H) Clear mask. Bit mask to indicate which GPIO_TX_DAT bits to set to 0. When read, [CLR]
2871 returns the GPIO_TX_DAT storage. */
2872 #endif /* Word 0 - End */
2873 } s;
2874 /* struct bdk_gpio_tx_clr_s cn9; */
2875 struct bdk_gpio_tx_clr_cn81xx
2876 {
2877 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2878 uint64_t reserved_48_63 : 16;
2879 uint64_t clr : 48; /**< [ 47: 0](R/W1C/H) Clear mask. Bit mask to indicate which GPIO_TX_DAT bits to set to 0. When read, [CLR]
2880 returns the GPIO_TX_DAT storage. */
2881 #else /* Word 0 - Little Endian */
2882 uint64_t clr : 48; /**< [ 47: 0](R/W1C/H) Clear mask. Bit mask to indicate which GPIO_TX_DAT bits to set to 0. When read, [CLR]
2883 returns the GPIO_TX_DAT storage. */
2884 uint64_t reserved_48_63 : 16;
2885 #endif /* Word 0 - End */
2886 } cn81xx;
2887 struct bdk_gpio_tx_clr_cn88xx
2888 {
2889 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2890 uint64_t reserved_51_63 : 13;
2891 uint64_t clr : 51; /**< [ 50: 0](R/W1C/H) Clear mask. Bit mask to indicate which GPIO_TX_DAT bits to set to 0. When read, [CLR]
2892 returns the GPIO_TX_DAT storage. */
2893 #else /* Word 0 - Little Endian */
2894 uint64_t clr : 51; /**< [ 50: 0](R/W1C/H) Clear mask. Bit mask to indicate which GPIO_TX_DAT bits to set to 0. When read, [CLR]
2895 returns the GPIO_TX_DAT storage. */
2896 uint64_t reserved_51_63 : 13;
2897 #endif /* Word 0 - End */
2898 } cn88xx;
2899 /* struct bdk_gpio_tx_clr_s cn83xx; */
2900 };
2901 typedef union bdk_gpio_tx_clr bdk_gpio_tx_clr_t;
2902
2903 #define BDK_GPIO_TX_CLR BDK_GPIO_TX_CLR_FUNC()
2904 static inline uint64_t BDK_GPIO_TX_CLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_TX_CLR_FUNC(void)2905 static inline uint64_t BDK_GPIO_TX_CLR_FUNC(void)
2906 {
2907 return 0x803000000010ll;
2908 }
2909
2910 #define typedef_BDK_GPIO_TX_CLR bdk_gpio_tx_clr_t
2911 #define bustype_BDK_GPIO_TX_CLR BDK_CSR_TYPE_NCB
2912 #define basename_BDK_GPIO_TX_CLR "GPIO_TX_CLR"
2913 #define device_bar_BDK_GPIO_TX_CLR 0x0 /* PF_BAR0 */
2914 #define busnum_BDK_GPIO_TX_CLR 0
2915 #define arguments_BDK_GPIO_TX_CLR -1,-1,-1,-1
2916
2917 /**
2918 * Register (NCB) gpio_tx_set
2919 *
2920 * GPIO Transmit Set Mask Register
2921 * This register sets GPIO output data. GPIO_TX_SET sets the first 64 GPIOs, and
2922 * GPIO_TX1_SET the remainder.
2923 *
2924 * Each bit in this register is only accessible to the requestor(s) permitted with
2925 * GPIO_BIT_PERMIT(), but error will not be reported when there are bits are not
2926 * permitted by GPIO_BIT_PERMIT().
2927 *
2928 * When permitted, this register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2929 */
2930 union bdk_gpio_tx_set
2931 {
2932 uint64_t u;
2933 struct bdk_gpio_tx_set_s
2934 {
2935 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2936 uint64_t set : 64; /**< [ 63: 0](R/W1S/H) Set mask. Bit mask to indicate which GPIO_TX_DAT bits to set to 1. When read, [SET]
2937 returns the GPIO_TX_DAT storage. */
2938 #else /* Word 0 - Little Endian */
2939 uint64_t set : 64; /**< [ 63: 0](R/W1S/H) Set mask. Bit mask to indicate which GPIO_TX_DAT bits to set to 1. When read, [SET]
2940 returns the GPIO_TX_DAT storage. */
2941 #endif /* Word 0 - End */
2942 } s;
2943 struct bdk_gpio_tx_set_cn9
2944 {
2945 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2946 uint64_t set : 64; /**< [ 63: 0](R/W1S/H) Set mask. Bit mask to indicate which GPIO_TX_DAT bits to set to 1. When read,
2947 [SET] returns the GPIO_TX_DAT storage. */
2948 #else /* Word 0 - Little Endian */
2949 uint64_t set : 64; /**< [ 63: 0](R/W1S/H) Set mask. Bit mask to indicate which GPIO_TX_DAT bits to set to 1. When read,
2950 [SET] returns the GPIO_TX_DAT storage. */
2951 #endif /* Word 0 - End */
2952 } cn9;
2953 struct bdk_gpio_tx_set_cn81xx
2954 {
2955 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2956 uint64_t reserved_48_63 : 16;
2957 uint64_t set : 48; /**< [ 47: 0](R/W1S/H) Set mask. Bit mask to indicate which GPIO_TX_DAT bits to set to 1. When read, [SET]
2958 returns the GPIO_TX_DAT storage. */
2959 #else /* Word 0 - Little Endian */
2960 uint64_t set : 48; /**< [ 47: 0](R/W1S/H) Set mask. Bit mask to indicate which GPIO_TX_DAT bits to set to 1. When read, [SET]
2961 returns the GPIO_TX_DAT storage. */
2962 uint64_t reserved_48_63 : 16;
2963 #endif /* Word 0 - End */
2964 } cn81xx;
2965 struct bdk_gpio_tx_set_cn88xx
2966 {
2967 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2968 uint64_t reserved_51_63 : 13;
2969 uint64_t set : 51; /**< [ 50: 0](R/W1S/H) Set mask. Bit mask to indicate which GPIO_TX_DAT bits to set to 1. When read, [SET]
2970 returns the GPIO_TX_DAT storage. */
2971 #else /* Word 0 - Little Endian */
2972 uint64_t set : 51; /**< [ 50: 0](R/W1S/H) Set mask. Bit mask to indicate which GPIO_TX_DAT bits to set to 1. When read, [SET]
2973 returns the GPIO_TX_DAT storage. */
2974 uint64_t reserved_51_63 : 13;
2975 #endif /* Word 0 - End */
2976 } cn88xx;
2977 /* struct bdk_gpio_tx_set_s cn83xx; */
2978 };
2979 typedef union bdk_gpio_tx_set bdk_gpio_tx_set_t;
2980
2981 #define BDK_GPIO_TX_SET BDK_GPIO_TX_SET_FUNC()
2982 static inline uint64_t BDK_GPIO_TX_SET_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GPIO_TX_SET_FUNC(void)2983 static inline uint64_t BDK_GPIO_TX_SET_FUNC(void)
2984 {
2985 return 0x803000000008ll;
2986 }
2987
2988 #define typedef_BDK_GPIO_TX_SET bdk_gpio_tx_set_t
2989 #define bustype_BDK_GPIO_TX_SET BDK_CSR_TYPE_NCB
2990 #define basename_BDK_GPIO_TX_SET "GPIO_TX_SET"
2991 #define device_bar_BDK_GPIO_TX_SET 0x0 /* PF_BAR0 */
2992 #define busnum_BDK_GPIO_TX_SET 0
2993 #define arguments_BDK_GPIO_TX_SET -1,-1,-1,-1
2994
2995 #endif /* __BDK_CSRS_GPIO_H__ */
2996