1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Microchip Image Sensor Controller (ISC) common driver base
4 *
5 * Copyright (C) 2016-2019 Microchip Technology, Inc.
6 *
7 * Author: Songjun Wu
8 * Author: Eugen Hristev <[email protected]>
9 *
10 */
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/math64.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_graph.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20 #include <linux/videodev2.h>
21 #include <linux/atmel-isc-media.h>
22
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-event.h>
26 #include <media/v4l2-image-sizes.h>
27 #include <media/v4l2-ioctl.h>
28 #include <media/v4l2-fwnode.h>
29 #include <media/v4l2-subdev.h>
30 #include <media/videobuf2-dma-contig.h>
31
32 #include "atmel-isc-regs.h"
33 #include "atmel-isc.h"
34
35 static unsigned int debug;
36 module_param(debug, int, 0644);
37 MODULE_PARM_DESC(debug, "debug level (0-2)");
38
39 static unsigned int sensor_preferred = 1;
40 module_param(sensor_preferred, uint, 0644);
41 MODULE_PARM_DESC(sensor_preferred,
42 "Sensor is preferred to output the specified format (1-on 0-off), default 1");
43
44 #define ISC_IS_FORMAT_RAW(mbus_code) \
45 (((mbus_code) & 0xf000) == 0x3000)
46
47 #define ISC_IS_FORMAT_GREY(mbus_code) \
48 (((mbus_code) == MEDIA_BUS_FMT_Y10_1X10) | \
49 (((mbus_code) == MEDIA_BUS_FMT_Y8_1X8)))
50
isc_update_v4l2_ctrls(struct isc_device * isc)51 static inline void isc_update_v4l2_ctrls(struct isc_device *isc)
52 {
53 struct isc_ctrls *ctrls = &isc->ctrls;
54
55 /* In here we set the v4l2 controls w.r.t. our pipeline config */
56 v4l2_ctrl_s_ctrl(isc->r_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_R]);
57 v4l2_ctrl_s_ctrl(isc->b_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_B]);
58 v4l2_ctrl_s_ctrl(isc->gr_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GR]);
59 v4l2_ctrl_s_ctrl(isc->gb_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GB]);
60
61 v4l2_ctrl_s_ctrl(isc->r_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_R]);
62 v4l2_ctrl_s_ctrl(isc->b_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_B]);
63 v4l2_ctrl_s_ctrl(isc->gr_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GR]);
64 v4l2_ctrl_s_ctrl(isc->gb_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GB]);
65 }
66
isc_update_awb_ctrls(struct isc_device * isc)67 static inline void isc_update_awb_ctrls(struct isc_device *isc)
68 {
69 struct isc_ctrls *ctrls = &isc->ctrls;
70
71 /* In here we set our actual hw pipeline config */
72
73 regmap_write(isc->regmap, ISC_WB_O_RGR,
74 ((ctrls->offset[ISC_HIS_CFG_MODE_R])) |
75 ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16));
76 regmap_write(isc->regmap, ISC_WB_O_BGB,
77 ((ctrls->offset[ISC_HIS_CFG_MODE_B])) |
78 ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16));
79 regmap_write(isc->regmap, ISC_WB_G_RGR,
80 ctrls->gain[ISC_HIS_CFG_MODE_R] |
81 (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16));
82 regmap_write(isc->regmap, ISC_WB_G_BGB,
83 ctrls->gain[ISC_HIS_CFG_MODE_B] |
84 (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16));
85 }
86
isc_reset_awb_ctrls(struct isc_device * isc)87 static inline void isc_reset_awb_ctrls(struct isc_device *isc)
88 {
89 unsigned int c;
90
91 for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
92 /* gains have a fixed point at 9 decimals */
93 isc->ctrls.gain[c] = 1 << 9;
94 /* offsets are in 2's complements */
95 isc->ctrls.offset[c] = 0;
96 }
97 }
98
99
isc_queue_setup(struct vb2_queue * vq,unsigned int * nbuffers,unsigned int * nplanes,unsigned int sizes[],struct device * alloc_devs[])100 static int isc_queue_setup(struct vb2_queue *vq,
101 unsigned int *nbuffers, unsigned int *nplanes,
102 unsigned int sizes[], struct device *alloc_devs[])
103 {
104 struct isc_device *isc = vb2_get_drv_priv(vq);
105 unsigned int size = isc->fmt.fmt.pix.sizeimage;
106
107 if (*nplanes)
108 return sizes[0] < size ? -EINVAL : 0;
109
110 *nplanes = 1;
111 sizes[0] = size;
112
113 return 0;
114 }
115
isc_buffer_prepare(struct vb2_buffer * vb)116 static int isc_buffer_prepare(struct vb2_buffer *vb)
117 {
118 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
119 struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
120 unsigned long size = isc->fmt.fmt.pix.sizeimage;
121
122 if (vb2_plane_size(vb, 0) < size) {
123 v4l2_err(&isc->v4l2_dev, "buffer too small (%lu < %lu)\n",
124 vb2_plane_size(vb, 0), size);
125 return -EINVAL;
126 }
127
128 vb2_set_plane_payload(vb, 0, size);
129
130 vbuf->field = isc->fmt.fmt.pix.field;
131
132 return 0;
133 }
134
isc_crop_pfe(struct isc_device * isc)135 static void isc_crop_pfe(struct isc_device *isc)
136 {
137 struct regmap *regmap = isc->regmap;
138 u32 h, w;
139
140 h = isc->fmt.fmt.pix.height;
141 w = isc->fmt.fmt.pix.width;
142
143 /*
144 * In case the sensor is not RAW, it will output a pixel (12-16 bits)
145 * with two samples on the ISC Data bus (which is 8-12)
146 * ISC will count each sample, so, we need to multiply these values
147 * by two, to get the real number of samples for the required pixels.
148 */
149 if (!ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) {
150 h <<= 1;
151 w <<= 1;
152 }
153
154 /*
155 * We limit the column/row count that the ISC will output according
156 * to the configured resolution that we want.
157 * This will avoid the situation where the sensor is misconfigured,
158 * sending more data, and the ISC will just take it and DMA to memory,
159 * causing corruption.
160 */
161 regmap_write(regmap, ISC_PFE_CFG1,
162 (ISC_PFE_CFG1_COLMIN(0) & ISC_PFE_CFG1_COLMIN_MASK) |
163 (ISC_PFE_CFG1_COLMAX(w - 1) & ISC_PFE_CFG1_COLMAX_MASK));
164
165 regmap_write(regmap, ISC_PFE_CFG2,
166 (ISC_PFE_CFG2_ROWMIN(0) & ISC_PFE_CFG2_ROWMIN_MASK) |
167 (ISC_PFE_CFG2_ROWMAX(h - 1) & ISC_PFE_CFG2_ROWMAX_MASK));
168
169 regmap_update_bits(regmap, ISC_PFE_CFG0,
170 ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN,
171 ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN);
172 }
173
isc_start_dma(struct isc_device * isc)174 static void isc_start_dma(struct isc_device *isc)
175 {
176 struct regmap *regmap = isc->regmap;
177 u32 sizeimage = isc->fmt.fmt.pix.sizeimage;
178 u32 dctrl_dview;
179 dma_addr_t addr0;
180
181 addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0);
182 regmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0);
183
184 switch (isc->config.fourcc) {
185 case V4L2_PIX_FMT_YUV420:
186 regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
187 addr0 + (sizeimage * 2) / 3);
188 regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
189 addr0 + (sizeimage * 5) / 6);
190 break;
191 case V4L2_PIX_FMT_YUV422P:
192 regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
193 addr0 + sizeimage / 2);
194 regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
195 addr0 + (sizeimage * 3) / 4);
196 break;
197 default:
198 break;
199 }
200
201 dctrl_dview = isc->config.dctrl_dview;
202
203 regmap_write(regmap, ISC_DCTRL + isc->offsets.dma,
204 dctrl_dview | ISC_DCTRL_IE_IS);
205 spin_lock(&isc->awb_lock);
206 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE);
207 spin_unlock(&isc->awb_lock);
208 }
209
isc_set_pipeline(struct isc_device * isc,u32 pipeline)210 static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
211 {
212 struct regmap *regmap = isc->regmap;
213 struct isc_ctrls *ctrls = &isc->ctrls;
214 u32 val, bay_cfg;
215 const u32 *gamma;
216 unsigned int i;
217
218 /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */
219 for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
220 val = pipeline & BIT(i) ? 1 : 0;
221 regmap_field_write(isc->pipeline[i], val);
222 }
223
224 if (!pipeline)
225 return;
226
227 bay_cfg = isc->config.sd_format->cfa_baycfg;
228
229 regmap_write(regmap, ISC_WB_CFG, bay_cfg);
230 isc_update_awb_ctrls(isc);
231 isc_update_v4l2_ctrls(isc);
232
233 regmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL);
234
235 gamma = &isc->gamma_table[ctrls->gamma_index][0];
236 regmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES);
237 regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);
238 regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);
239
240 isc->config_dpc(isc);
241 isc->config_csc(isc);
242 isc->config_cbc(isc);
243 isc->config_cc(isc);
244 isc->config_gam(isc);
245 }
246
isc_update_profile(struct isc_device * isc)247 static int isc_update_profile(struct isc_device *isc)
248 {
249 struct regmap *regmap = isc->regmap;
250 u32 sr;
251 int counter = 100;
252
253 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_UPPRO);
254
255 regmap_read(regmap, ISC_CTRLSR, &sr);
256 while ((sr & ISC_CTRL_UPPRO) && counter--) {
257 usleep_range(1000, 2000);
258 regmap_read(regmap, ISC_CTRLSR, &sr);
259 }
260
261 if (counter < 0) {
262 v4l2_warn(&isc->v4l2_dev, "Time out to update profile\n");
263 return -ETIMEDOUT;
264 }
265
266 return 0;
267 }
268
isc_set_histogram(struct isc_device * isc,bool enable)269 static void isc_set_histogram(struct isc_device *isc, bool enable)
270 {
271 struct regmap *regmap = isc->regmap;
272 struct isc_ctrls *ctrls = &isc->ctrls;
273
274 if (enable) {
275 regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
276 ISC_HIS_CFG_MODE_GR |
277 (isc->config.sd_format->cfa_baycfg
278 << ISC_HIS_CFG_BAYSEL_SHIFT) |
279 ISC_HIS_CFG_RAR);
280 regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
281 ISC_HIS_CTRL_EN);
282 regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE);
283 ctrls->hist_id = ISC_HIS_CFG_MODE_GR;
284 isc_update_profile(isc);
285 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
286
287 ctrls->hist_stat = HIST_ENABLED;
288 } else {
289 regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE);
290 regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
291 ISC_HIS_CTRL_DIS);
292
293 ctrls->hist_stat = HIST_DISABLED;
294 }
295 }
296
isc_configure(struct isc_device * isc)297 static int isc_configure(struct isc_device *isc)
298 {
299 struct regmap *regmap = isc->regmap;
300 u32 pfe_cfg0, dcfg, mask, pipeline;
301 struct isc_subdev_entity *subdev = isc->current_subdev;
302
303 pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps;
304 pipeline = isc->config.bits_pipeline;
305
306 dcfg = isc->config.dcfg_imode | isc->dcfg;
307
308 pfe_cfg0 |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;
309 mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |
310 ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW |
311 ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC |
312 ISC_PFE_CFG0_CCIR656 | ISC_PFE_CFG0_MIPI;
313
314 regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);
315
316 isc->config_rlp(isc);
317
318 regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg);
319
320 /* Set the pipeline */
321 isc_set_pipeline(isc, pipeline);
322
323 /*
324 * The current implemented histogram is available for RAW R, B, GB, GR
325 * channels. We need to check if sensor is outputting RAW BAYER
326 */
327 if (isc->ctrls.awb &&
328 ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
329 isc_set_histogram(isc, true);
330 else
331 isc_set_histogram(isc, false);
332
333 /* Update profile */
334 return isc_update_profile(isc);
335 }
336
isc_start_streaming(struct vb2_queue * vq,unsigned int count)337 static int isc_start_streaming(struct vb2_queue *vq, unsigned int count)
338 {
339 struct isc_device *isc = vb2_get_drv_priv(vq);
340 struct regmap *regmap = isc->regmap;
341 struct isc_buffer *buf;
342 unsigned long flags;
343 int ret;
344
345 /* Enable stream on the sub device */
346 ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 1);
347 if (ret && ret != -ENOIOCTLCMD) {
348 v4l2_err(&isc->v4l2_dev, "stream on failed in subdev %d\n",
349 ret);
350 goto err_start_stream;
351 }
352
353 ret = pm_runtime_resume_and_get(isc->dev);
354 if (ret < 0) {
355 v4l2_err(&isc->v4l2_dev, "RPM resume failed in subdev %d\n",
356 ret);
357 goto err_pm_get;
358 }
359
360 ret = isc_configure(isc);
361 if (unlikely(ret))
362 goto err_configure;
363
364 /* Enable DMA interrupt */
365 regmap_write(regmap, ISC_INTEN, ISC_INT_DDONE);
366
367 spin_lock_irqsave(&isc->dma_queue_lock, flags);
368
369 isc->sequence = 0;
370 isc->stop = false;
371 reinit_completion(&isc->comp);
372
373 isc->cur_frm = list_first_entry(&isc->dma_queue,
374 struct isc_buffer, list);
375 list_del(&isc->cur_frm->list);
376
377 isc_crop_pfe(isc);
378 isc_start_dma(isc);
379
380 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
381
382 /* if we streaming from RAW, we can do one-shot white balance adj */
383 if (ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
384 v4l2_ctrl_activate(isc->do_wb_ctrl, true);
385
386 return 0;
387
388 err_configure:
389 pm_runtime_put_sync(isc->dev);
390 err_pm_get:
391 v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
392
393 err_start_stream:
394 spin_lock_irqsave(&isc->dma_queue_lock, flags);
395 list_for_each_entry(buf, &isc->dma_queue, list)
396 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
397 INIT_LIST_HEAD(&isc->dma_queue);
398 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
399
400 return ret;
401 }
402
isc_stop_streaming(struct vb2_queue * vq)403 static void isc_stop_streaming(struct vb2_queue *vq)
404 {
405 struct isc_device *isc = vb2_get_drv_priv(vq);
406 unsigned long flags;
407 struct isc_buffer *buf;
408 int ret;
409
410 mutex_lock(&isc->awb_mutex);
411 v4l2_ctrl_activate(isc->do_wb_ctrl, false);
412
413 isc->stop = true;
414
415 /* Wait until the end of the current frame */
416 if (isc->cur_frm && !wait_for_completion_timeout(&isc->comp, 5 * HZ))
417 v4l2_err(&isc->v4l2_dev,
418 "Timeout waiting for end of the capture\n");
419
420 mutex_unlock(&isc->awb_mutex);
421
422 /* Disable DMA interrupt */
423 regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE);
424
425 pm_runtime_put_sync(isc->dev);
426
427 /* Disable stream on the sub device */
428 ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
429 if (ret && ret != -ENOIOCTLCMD)
430 v4l2_err(&isc->v4l2_dev, "stream off failed in subdev\n");
431
432 /* Release all active buffers */
433 spin_lock_irqsave(&isc->dma_queue_lock, flags);
434 if (unlikely(isc->cur_frm)) {
435 vb2_buffer_done(&isc->cur_frm->vb.vb2_buf,
436 VB2_BUF_STATE_ERROR);
437 isc->cur_frm = NULL;
438 }
439 list_for_each_entry(buf, &isc->dma_queue, list)
440 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
441 INIT_LIST_HEAD(&isc->dma_queue);
442 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
443 }
444
isc_buffer_queue(struct vb2_buffer * vb)445 static void isc_buffer_queue(struct vb2_buffer *vb)
446 {
447 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
448 struct isc_buffer *buf = container_of(vbuf, struct isc_buffer, vb);
449 struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
450 unsigned long flags;
451
452 spin_lock_irqsave(&isc->dma_queue_lock, flags);
453 if (!isc->cur_frm && list_empty(&isc->dma_queue) &&
454 vb2_start_streaming_called(vb->vb2_queue)) {
455 isc->cur_frm = buf;
456 isc_start_dma(isc);
457 } else
458 list_add_tail(&buf->list, &isc->dma_queue);
459 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
460 }
461
find_format_by_fourcc(struct isc_device * isc,unsigned int fourcc)462 static struct isc_format *find_format_by_fourcc(struct isc_device *isc,
463 unsigned int fourcc)
464 {
465 unsigned int num_formats = isc->num_user_formats;
466 struct isc_format *fmt;
467 unsigned int i;
468
469 for (i = 0; i < num_formats; i++) {
470 fmt = isc->user_formats[i];
471 if (fmt->fourcc == fourcc)
472 return fmt;
473 }
474
475 return NULL;
476 }
477
478 static const struct vb2_ops isc_vb2_ops = {
479 .queue_setup = isc_queue_setup,
480 .buf_prepare = isc_buffer_prepare,
481 .start_streaming = isc_start_streaming,
482 .stop_streaming = isc_stop_streaming,
483 .buf_queue = isc_buffer_queue,
484 };
485
isc_querycap(struct file * file,void * priv,struct v4l2_capability * cap)486 static int isc_querycap(struct file *file, void *priv,
487 struct v4l2_capability *cap)
488 {
489 strscpy(cap->driver, "microchip-isc", sizeof(cap->driver));
490 strscpy(cap->card, "Atmel Image Sensor Controller", sizeof(cap->card));
491
492 return 0;
493 }
494
isc_enum_fmt_vid_cap(struct file * file,void * priv,struct v4l2_fmtdesc * f)495 static int isc_enum_fmt_vid_cap(struct file *file, void *priv,
496 struct v4l2_fmtdesc *f)
497 {
498 struct isc_device *isc = video_drvdata(file);
499 u32 index = f->index;
500 u32 i, supported_index;
501
502 if (index < isc->controller_formats_size) {
503 f->pixelformat = isc->controller_formats[index].fourcc;
504 return 0;
505 }
506
507 index -= isc->controller_formats_size;
508
509 supported_index = 0;
510
511 for (i = 0; i < isc->formats_list_size; i++) {
512 if (!ISC_IS_FORMAT_RAW(isc->formats_list[i].mbus_code) ||
513 !isc->formats_list[i].sd_support)
514 continue;
515 if (supported_index == index) {
516 f->pixelformat = isc->formats_list[i].fourcc;
517 return 0;
518 }
519 supported_index++;
520 }
521
522 return -EINVAL;
523 }
524
isc_g_fmt_vid_cap(struct file * file,void * priv,struct v4l2_format * fmt)525 static int isc_g_fmt_vid_cap(struct file *file, void *priv,
526 struct v4l2_format *fmt)
527 {
528 struct isc_device *isc = video_drvdata(file);
529
530 *fmt = isc->fmt;
531
532 return 0;
533 }
534
535 /*
536 * Checks the current configured format, if ISC can output it,
537 * considering which type of format the ISC receives from the sensor
538 */
isc_try_validate_formats(struct isc_device * isc)539 static int isc_try_validate_formats(struct isc_device *isc)
540 {
541 int ret;
542 bool bayer = false, yuv = false, rgb = false, grey = false;
543
544 /* all formats supported by the RLP module are OK */
545 switch (isc->try_config.fourcc) {
546 case V4L2_PIX_FMT_SBGGR8:
547 case V4L2_PIX_FMT_SGBRG8:
548 case V4L2_PIX_FMT_SGRBG8:
549 case V4L2_PIX_FMT_SRGGB8:
550 case V4L2_PIX_FMT_SBGGR10:
551 case V4L2_PIX_FMT_SGBRG10:
552 case V4L2_PIX_FMT_SGRBG10:
553 case V4L2_PIX_FMT_SRGGB10:
554 case V4L2_PIX_FMT_SBGGR12:
555 case V4L2_PIX_FMT_SGBRG12:
556 case V4L2_PIX_FMT_SGRBG12:
557 case V4L2_PIX_FMT_SRGGB12:
558 ret = 0;
559 bayer = true;
560 break;
561
562 case V4L2_PIX_FMT_YUV420:
563 case V4L2_PIX_FMT_YUV422P:
564 case V4L2_PIX_FMT_YUYV:
565 case V4L2_PIX_FMT_UYVY:
566 case V4L2_PIX_FMT_VYUY:
567 ret = 0;
568 yuv = true;
569 break;
570
571 case V4L2_PIX_FMT_RGB565:
572 case V4L2_PIX_FMT_ABGR32:
573 case V4L2_PIX_FMT_XBGR32:
574 case V4L2_PIX_FMT_ARGB444:
575 case V4L2_PIX_FMT_ARGB555:
576 ret = 0;
577 rgb = true;
578 break;
579 case V4L2_PIX_FMT_GREY:
580 case V4L2_PIX_FMT_Y10:
581 case V4L2_PIX_FMT_Y16:
582 ret = 0;
583 grey = true;
584 break;
585 default:
586 /* any other different formats are not supported */
587 ret = -EINVAL;
588 }
589 v4l2_dbg(1, debug, &isc->v4l2_dev,
590 "Format validation, requested rgb=%u, yuv=%u, grey=%u, bayer=%u\n",
591 rgb, yuv, grey, bayer);
592
593 /* we cannot output RAW if we do not receive RAW */
594 if ((bayer) && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
595 return -EINVAL;
596
597 /* we cannot output GREY if we do not receive RAW/GREY */
598 if (grey && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code) &&
599 !ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code))
600 return -EINVAL;
601
602 return ret;
603 }
604
605 /*
606 * Configures the RLP and DMA modules, depending on the output format
607 * configured for the ISC.
608 * If direct_dump == true, just dump raw data 8/16 bits depending on format.
609 */
isc_try_configure_rlp_dma(struct isc_device * isc,bool direct_dump)610 static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump)
611 {
612 isc->try_config.rlp_cfg_mode = 0;
613
614 switch (isc->try_config.fourcc) {
615 case V4L2_PIX_FMT_SBGGR8:
616 case V4L2_PIX_FMT_SGBRG8:
617 case V4L2_PIX_FMT_SGRBG8:
618 case V4L2_PIX_FMT_SRGGB8:
619 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
620 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
621 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
622 isc->try_config.bpp = 8;
623 isc->try_config.bpp_v4l2 = 8;
624 break;
625 case V4L2_PIX_FMT_SBGGR10:
626 case V4L2_PIX_FMT_SGBRG10:
627 case V4L2_PIX_FMT_SGRBG10:
628 case V4L2_PIX_FMT_SRGGB10:
629 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10;
630 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
631 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
632 isc->try_config.bpp = 16;
633 isc->try_config.bpp_v4l2 = 16;
634 break;
635 case V4L2_PIX_FMT_SBGGR12:
636 case V4L2_PIX_FMT_SGBRG12:
637 case V4L2_PIX_FMT_SGRBG12:
638 case V4L2_PIX_FMT_SRGGB12:
639 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12;
640 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
641 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
642 isc->try_config.bpp = 16;
643 isc->try_config.bpp_v4l2 = 16;
644 break;
645 case V4L2_PIX_FMT_RGB565:
646 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_RGB565;
647 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
648 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
649 isc->try_config.bpp = 16;
650 isc->try_config.bpp_v4l2 = 16;
651 break;
652 case V4L2_PIX_FMT_ARGB444:
653 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB444;
654 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
655 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
656 isc->try_config.bpp = 16;
657 isc->try_config.bpp_v4l2 = 16;
658 break;
659 case V4L2_PIX_FMT_ARGB555:
660 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB555;
661 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
662 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
663 isc->try_config.bpp = 16;
664 isc->try_config.bpp_v4l2 = 16;
665 break;
666 case V4L2_PIX_FMT_ABGR32:
667 case V4L2_PIX_FMT_XBGR32:
668 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB32;
669 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
670 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
671 isc->try_config.bpp = 32;
672 isc->try_config.bpp_v4l2 = 32;
673 break;
674 case V4L2_PIX_FMT_YUV420:
675 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
676 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC420P;
677 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
678 isc->try_config.bpp = 12;
679 isc->try_config.bpp_v4l2 = 8; /* only first plane */
680 break;
681 case V4L2_PIX_FMT_YUV422P:
682 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
683 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC422P;
684 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
685 isc->try_config.bpp = 16;
686 isc->try_config.bpp_v4l2 = 8; /* only first plane */
687 break;
688 case V4L2_PIX_FMT_YUYV:
689 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_YUYV;
690 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
691 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
692 isc->try_config.bpp = 16;
693 isc->try_config.bpp_v4l2 = 16;
694 break;
695 case V4L2_PIX_FMT_UYVY:
696 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_UYVY;
697 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
698 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
699 isc->try_config.bpp = 16;
700 isc->try_config.bpp_v4l2 = 16;
701 break;
702 case V4L2_PIX_FMT_VYUY:
703 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_VYUY;
704 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
705 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
706 isc->try_config.bpp = 16;
707 isc->try_config.bpp_v4l2 = 16;
708 break;
709 case V4L2_PIX_FMT_GREY:
710 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY8;
711 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
712 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
713 isc->try_config.bpp = 8;
714 isc->try_config.bpp_v4l2 = 8;
715 break;
716 case V4L2_PIX_FMT_Y16:
717 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10 | ISC_RLP_CFG_LSH;
718 fallthrough;
719 case V4L2_PIX_FMT_Y10:
720 isc->try_config.rlp_cfg_mode |= ISC_RLP_CFG_MODE_DATY10;
721 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
722 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
723 isc->try_config.bpp = 16;
724 isc->try_config.bpp_v4l2 = 16;
725 break;
726 default:
727 return -EINVAL;
728 }
729
730 if (direct_dump) {
731 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
732 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
733 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
734 return 0;
735 }
736
737 return 0;
738 }
739
740 /*
741 * Configuring pipeline modules, depending on which format the ISC outputs
742 * and considering which format it has as input from the sensor.
743 */
isc_try_configure_pipeline(struct isc_device * isc)744 static int isc_try_configure_pipeline(struct isc_device *isc)
745 {
746 switch (isc->try_config.fourcc) {
747 case V4L2_PIX_FMT_RGB565:
748 case V4L2_PIX_FMT_ARGB555:
749 case V4L2_PIX_FMT_ARGB444:
750 case V4L2_PIX_FMT_ABGR32:
751 case V4L2_PIX_FMT_XBGR32:
752 /* if sensor format is RAW, we convert inside ISC */
753 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
754 isc->try_config.bits_pipeline = CFA_ENABLE |
755 WB_ENABLE | GAM_ENABLES | DPC_BLCENABLE |
756 CC_ENABLE;
757 } else {
758 isc->try_config.bits_pipeline = 0x0;
759 }
760 break;
761 case V4L2_PIX_FMT_YUV420:
762 /* if sensor format is RAW, we convert inside ISC */
763 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
764 isc->try_config.bits_pipeline = CFA_ENABLE |
765 CSC_ENABLE | GAM_ENABLES | WB_ENABLE |
766 SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE |
767 DPC_BLCENABLE;
768 } else {
769 isc->try_config.bits_pipeline = 0x0;
770 }
771 break;
772 case V4L2_PIX_FMT_YUV422P:
773 /* if sensor format is RAW, we convert inside ISC */
774 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
775 isc->try_config.bits_pipeline = CFA_ENABLE |
776 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
777 SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE;
778 } else {
779 isc->try_config.bits_pipeline = 0x0;
780 }
781 break;
782 case V4L2_PIX_FMT_YUYV:
783 case V4L2_PIX_FMT_UYVY:
784 case V4L2_PIX_FMT_VYUY:
785 /* if sensor format is RAW, we convert inside ISC */
786 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
787 isc->try_config.bits_pipeline = CFA_ENABLE |
788 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
789 SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE;
790 } else {
791 isc->try_config.bits_pipeline = 0x0;
792 }
793 break;
794 case V4L2_PIX_FMT_GREY:
795 case V4L2_PIX_FMT_Y16:
796 /* if sensor format is RAW, we convert inside ISC */
797 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
798 isc->try_config.bits_pipeline = CFA_ENABLE |
799 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
800 CBC_ENABLE | DPC_BLCENABLE;
801 } else {
802 isc->try_config.bits_pipeline = 0x0;
803 }
804 break;
805 default:
806 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
807 isc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE;
808 else
809 isc->try_config.bits_pipeline = 0x0;
810 }
811
812 /* Tune the pipeline to product specific */
813 isc->adapt_pipeline(isc);
814
815 return 0;
816 }
817
isc_try_fse(struct isc_device * isc,struct v4l2_subdev_state * sd_state)818 static void isc_try_fse(struct isc_device *isc,
819 struct v4l2_subdev_state *sd_state)
820 {
821 struct v4l2_rect *try_crop =
822 v4l2_subdev_state_get_crop(sd_state, 0);
823 struct v4l2_subdev_frame_size_enum fse = {
824 .which = V4L2_SUBDEV_FORMAT_TRY,
825 };
826 int ret;
827
828 /*
829 * If we do not know yet which format the subdev is using, we cannot
830 * do anything.
831 */
832 if (!isc->try_config.sd_format)
833 return;
834
835 fse.code = isc->try_config.sd_format->mbus_code;
836
837 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size,
838 sd_state, &fse);
839 /*
840 * Attempt to obtain format size from subdev. If not available,
841 * just use the maximum ISC can receive.
842 */
843 if (ret) {
844 try_crop->width = isc->max_width;
845 try_crop->height = isc->max_height;
846 } else {
847 try_crop->width = fse.max_width;
848 try_crop->height = fse.max_height;
849 }
850 }
851
isc_try_fmt(struct isc_device * isc,struct v4l2_format * f,u32 * code)852 static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f,
853 u32 *code)
854 {
855 int i;
856 struct isc_format *sd_fmt = NULL, *direct_fmt = NULL;
857 struct v4l2_pix_format *pixfmt = &f->fmt.pix;
858 struct v4l2_subdev_pad_config pad_cfg = {};
859 struct v4l2_subdev_state pad_state = {
860 .pads = &pad_cfg,
861 };
862 struct v4l2_subdev_format format = {
863 .which = V4L2_SUBDEV_FORMAT_TRY,
864 };
865 u32 mbus_code;
866 int ret;
867 bool rlp_dma_direct_dump = false;
868
869 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
870 return -EINVAL;
871
872 /* Step 1: find a RAW format that is supported */
873 for (i = 0; i < isc->num_user_formats; i++) {
874 if (ISC_IS_FORMAT_RAW(isc->user_formats[i]->mbus_code)) {
875 sd_fmt = isc->user_formats[i];
876 break;
877 }
878 }
879 /* Step 2: We can continue with this RAW format, or we can look
880 * for better: maybe sensor supports directly what we need.
881 */
882 direct_fmt = find_format_by_fourcc(isc, pixfmt->pixelformat);
883
884 /* Step 3: We have both. We decide given the module parameter which
885 * one to use.
886 */
887 if (direct_fmt && sd_fmt && sensor_preferred)
888 sd_fmt = direct_fmt;
889
890 /* Step 4: we do not have RAW but we have a direct format. Use it. */
891 if (direct_fmt && !sd_fmt)
892 sd_fmt = direct_fmt;
893
894 /* Step 5: if we are using a direct format, we need to package
895 * everything as 8 bit data and just dump it
896 */
897 if (sd_fmt == direct_fmt)
898 rlp_dma_direct_dump = true;
899
900 /* Step 6: We have no format. This can happen if the userspace
901 * requests some weird/invalid format.
902 * In this case, default to whatever we have
903 */
904 if (!sd_fmt && !direct_fmt) {
905 sd_fmt = isc->user_formats[isc->num_user_formats - 1];
906 v4l2_dbg(1, debug, &isc->v4l2_dev,
907 "Sensor not supporting %.4s, using %.4s\n",
908 (char *)&pixfmt->pixelformat, (char *)&sd_fmt->fourcc);
909 }
910
911 if (!sd_fmt) {
912 ret = -EINVAL;
913 goto isc_try_fmt_err;
914 }
915
916 /* Step 7: Print out what we decided for debugging */
917 v4l2_dbg(1, debug, &isc->v4l2_dev,
918 "Preferring to have sensor using format %.4s\n",
919 (char *)&sd_fmt->fourcc);
920
921 /* Step 8: at this moment we decided which format the subdev will use */
922 isc->try_config.sd_format = sd_fmt;
923
924 /* Limit to Atmel ISC hardware capabilities */
925 if (pixfmt->width > isc->max_width)
926 pixfmt->width = isc->max_width;
927 if (pixfmt->height > isc->max_height)
928 pixfmt->height = isc->max_height;
929
930 /*
931 * The mbus format is the one the subdev outputs.
932 * The pixels will be transferred in this format Sensor -> ISC
933 */
934 mbus_code = sd_fmt->mbus_code;
935
936 /*
937 * Validate formats. If the required format is not OK, default to raw.
938 */
939
940 isc->try_config.fourcc = pixfmt->pixelformat;
941
942 if (isc_try_validate_formats(isc)) {
943 pixfmt->pixelformat = isc->try_config.fourcc = sd_fmt->fourcc;
944 /* Re-try to validate the new format */
945 ret = isc_try_validate_formats(isc);
946 if (ret)
947 goto isc_try_fmt_err;
948 }
949
950 ret = isc_try_configure_rlp_dma(isc, rlp_dma_direct_dump);
951 if (ret)
952 goto isc_try_fmt_err;
953
954 ret = isc_try_configure_pipeline(isc);
955 if (ret)
956 goto isc_try_fmt_err;
957
958 /* Obtain frame sizes if possible to have crop requirements ready */
959 isc_try_fse(isc, &pad_state);
960
961 v4l2_fill_mbus_format(&format.format, pixfmt, mbus_code);
962 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, set_fmt,
963 &pad_state, &format);
964 if (ret < 0)
965 goto isc_try_fmt_subdev_err;
966
967 v4l2_fill_pix_format(pixfmt, &format.format);
968
969 /* Limit to Atmel ISC hardware capabilities */
970 if (pixfmt->width > isc->max_width)
971 pixfmt->width = isc->max_width;
972 if (pixfmt->height > isc->max_height)
973 pixfmt->height = isc->max_height;
974
975 pixfmt->field = V4L2_FIELD_NONE;
976 pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp_v4l2) >> 3;
977 pixfmt->sizeimage = ((pixfmt->width * isc->try_config.bpp) >> 3) *
978 pixfmt->height;
979
980 if (code)
981 *code = mbus_code;
982
983 return 0;
984
985 isc_try_fmt_err:
986 v4l2_err(&isc->v4l2_dev, "Could not find any possible format for a working pipeline\n");
987 isc_try_fmt_subdev_err:
988 memset(&isc->try_config, 0, sizeof(isc->try_config));
989
990 return ret;
991 }
992
isc_set_fmt(struct isc_device * isc,struct v4l2_format * f)993 static int isc_set_fmt(struct isc_device *isc, struct v4l2_format *f)
994 {
995 struct v4l2_subdev_format format = {
996 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
997 };
998 u32 mbus_code = 0;
999 int ret;
1000
1001 ret = isc_try_fmt(isc, f, &mbus_code);
1002 if (ret)
1003 return ret;
1004
1005 v4l2_fill_mbus_format(&format.format, &f->fmt.pix, mbus_code);
1006 ret = v4l2_subdev_call(isc->current_subdev->sd, pad,
1007 set_fmt, NULL, &format);
1008 if (ret < 0)
1009 return ret;
1010
1011 /* Limit to Atmel ISC hardware capabilities */
1012 if (f->fmt.pix.width > isc->max_width)
1013 f->fmt.pix.width = isc->max_width;
1014 if (f->fmt.pix.height > isc->max_height)
1015 f->fmt.pix.height = isc->max_height;
1016
1017 isc->fmt = *f;
1018
1019 if (isc->try_config.sd_format && isc->config.sd_format &&
1020 isc->try_config.sd_format != isc->config.sd_format) {
1021 isc->ctrls.hist_stat = HIST_INIT;
1022 isc_reset_awb_ctrls(isc);
1023 isc_update_v4l2_ctrls(isc);
1024 }
1025 /* make the try configuration active */
1026 isc->config = isc->try_config;
1027
1028 v4l2_dbg(1, debug, &isc->v4l2_dev, "New ISC configuration in place\n");
1029
1030 return 0;
1031 }
1032
isc_s_fmt_vid_cap(struct file * file,void * priv,struct v4l2_format * f)1033 static int isc_s_fmt_vid_cap(struct file *file, void *priv,
1034 struct v4l2_format *f)
1035 {
1036 struct isc_device *isc = video_drvdata(file);
1037
1038 if (vb2_is_busy(&isc->vb2_vidq))
1039 return -EBUSY;
1040
1041 return isc_set_fmt(isc, f);
1042 }
1043
isc_try_fmt_vid_cap(struct file * file,void * priv,struct v4l2_format * f)1044 static int isc_try_fmt_vid_cap(struct file *file, void *priv,
1045 struct v4l2_format *f)
1046 {
1047 struct isc_device *isc = video_drvdata(file);
1048
1049 return isc_try_fmt(isc, f, NULL);
1050 }
1051
isc_enum_input(struct file * file,void * priv,struct v4l2_input * inp)1052 static int isc_enum_input(struct file *file, void *priv,
1053 struct v4l2_input *inp)
1054 {
1055 if (inp->index != 0)
1056 return -EINVAL;
1057
1058 inp->type = V4L2_INPUT_TYPE_CAMERA;
1059 inp->std = 0;
1060 strscpy(inp->name, "Camera", sizeof(inp->name));
1061
1062 return 0;
1063 }
1064
isc_g_input(struct file * file,void * priv,unsigned int * i)1065 static int isc_g_input(struct file *file, void *priv, unsigned int *i)
1066 {
1067 *i = 0;
1068
1069 return 0;
1070 }
1071
isc_s_input(struct file * file,void * priv,unsigned int i)1072 static int isc_s_input(struct file *file, void *priv, unsigned int i)
1073 {
1074 if (i > 0)
1075 return -EINVAL;
1076
1077 return 0;
1078 }
1079
isc_g_parm(struct file * file,void * fh,struct v4l2_streamparm * a)1080 static int isc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1081 {
1082 struct isc_device *isc = video_drvdata(file);
1083
1084 return v4l2_g_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1085 }
1086
isc_s_parm(struct file * file,void * fh,struct v4l2_streamparm * a)1087 static int isc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1088 {
1089 struct isc_device *isc = video_drvdata(file);
1090
1091 return v4l2_s_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1092 }
1093
isc_enum_framesizes(struct file * file,void * fh,struct v4l2_frmsizeenum * fsize)1094 static int isc_enum_framesizes(struct file *file, void *fh,
1095 struct v4l2_frmsizeenum *fsize)
1096 {
1097 struct isc_device *isc = video_drvdata(file);
1098 int ret = -EINVAL;
1099 int i;
1100
1101 if (fsize->index)
1102 return -EINVAL;
1103
1104 for (i = 0; i < isc->num_user_formats; i++)
1105 if (isc->user_formats[i]->fourcc == fsize->pixel_format)
1106 ret = 0;
1107
1108 for (i = 0; i < isc->controller_formats_size; i++)
1109 if (isc->controller_formats[i].fourcc == fsize->pixel_format)
1110 ret = 0;
1111
1112 if (ret)
1113 return ret;
1114
1115 fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
1116
1117 fsize->stepwise.min_width = 16;
1118 fsize->stepwise.max_width = isc->max_width;
1119 fsize->stepwise.min_height = 16;
1120 fsize->stepwise.max_height = isc->max_height;
1121 fsize->stepwise.step_width = 1;
1122 fsize->stepwise.step_height = 1;
1123
1124 return 0;
1125 }
1126
1127 static const struct v4l2_ioctl_ops isc_ioctl_ops = {
1128 .vidioc_querycap = isc_querycap,
1129 .vidioc_enum_fmt_vid_cap = isc_enum_fmt_vid_cap,
1130 .vidioc_g_fmt_vid_cap = isc_g_fmt_vid_cap,
1131 .vidioc_s_fmt_vid_cap = isc_s_fmt_vid_cap,
1132 .vidioc_try_fmt_vid_cap = isc_try_fmt_vid_cap,
1133
1134 .vidioc_enum_input = isc_enum_input,
1135 .vidioc_g_input = isc_g_input,
1136 .vidioc_s_input = isc_s_input,
1137
1138 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1139 .vidioc_querybuf = vb2_ioctl_querybuf,
1140 .vidioc_qbuf = vb2_ioctl_qbuf,
1141 .vidioc_expbuf = vb2_ioctl_expbuf,
1142 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1143 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1144 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1145 .vidioc_streamon = vb2_ioctl_streamon,
1146 .vidioc_streamoff = vb2_ioctl_streamoff,
1147
1148 .vidioc_g_parm = isc_g_parm,
1149 .vidioc_s_parm = isc_s_parm,
1150 .vidioc_enum_framesizes = isc_enum_framesizes,
1151
1152 .vidioc_log_status = v4l2_ctrl_log_status,
1153 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1154 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1155 };
1156
isc_open(struct file * file)1157 static int isc_open(struct file *file)
1158 {
1159 struct isc_device *isc = video_drvdata(file);
1160 struct v4l2_subdev *sd = isc->current_subdev->sd;
1161 int ret;
1162
1163 if (mutex_lock_interruptible(&isc->lock))
1164 return -ERESTARTSYS;
1165
1166 ret = v4l2_fh_open(file);
1167 if (ret < 0)
1168 goto unlock;
1169
1170 if (!v4l2_fh_is_singular_file(file))
1171 goto unlock;
1172
1173 ret = v4l2_subdev_call(sd, core, s_power, 1);
1174 if (ret < 0 && ret != -ENOIOCTLCMD) {
1175 v4l2_fh_release(file);
1176 goto unlock;
1177 }
1178
1179 ret = isc_set_fmt(isc, &isc->fmt);
1180 if (ret) {
1181 v4l2_subdev_call(sd, core, s_power, 0);
1182 v4l2_fh_release(file);
1183 }
1184
1185 unlock:
1186 mutex_unlock(&isc->lock);
1187 return ret;
1188 }
1189
isc_release(struct file * file)1190 static int isc_release(struct file *file)
1191 {
1192 struct isc_device *isc = video_drvdata(file);
1193 struct v4l2_subdev *sd = isc->current_subdev->sd;
1194 bool fh_singular;
1195 int ret;
1196
1197 mutex_lock(&isc->lock);
1198
1199 fh_singular = v4l2_fh_is_singular_file(file);
1200
1201 ret = _vb2_fop_release(file, NULL);
1202
1203 if (fh_singular)
1204 v4l2_subdev_call(sd, core, s_power, 0);
1205
1206 mutex_unlock(&isc->lock);
1207
1208 return ret;
1209 }
1210
1211 static const struct v4l2_file_operations isc_fops = {
1212 .owner = THIS_MODULE,
1213 .open = isc_open,
1214 .release = isc_release,
1215 .unlocked_ioctl = video_ioctl2,
1216 .read = vb2_fop_read,
1217 .mmap = vb2_fop_mmap,
1218 .poll = vb2_fop_poll,
1219 };
1220
atmel_isc_interrupt(int irq,void * dev_id)1221 irqreturn_t atmel_isc_interrupt(int irq, void *dev_id)
1222 {
1223 struct isc_device *isc = (struct isc_device *)dev_id;
1224 struct regmap *regmap = isc->regmap;
1225 u32 isc_intsr, isc_intmask, pending;
1226 irqreturn_t ret = IRQ_NONE;
1227
1228 regmap_read(regmap, ISC_INTSR, &isc_intsr);
1229 regmap_read(regmap, ISC_INTMASK, &isc_intmask);
1230
1231 pending = isc_intsr & isc_intmask;
1232
1233 if (likely(pending & ISC_INT_DDONE)) {
1234 spin_lock(&isc->dma_queue_lock);
1235 if (isc->cur_frm) {
1236 struct vb2_v4l2_buffer *vbuf = &isc->cur_frm->vb;
1237 struct vb2_buffer *vb = &vbuf->vb2_buf;
1238
1239 vb->timestamp = ktime_get_ns();
1240 vbuf->sequence = isc->sequence++;
1241 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1242 isc->cur_frm = NULL;
1243 }
1244
1245 if (!list_empty(&isc->dma_queue) && !isc->stop) {
1246 isc->cur_frm = list_first_entry(&isc->dma_queue,
1247 struct isc_buffer, list);
1248 list_del(&isc->cur_frm->list);
1249
1250 isc_start_dma(isc);
1251 }
1252
1253 if (isc->stop)
1254 complete(&isc->comp);
1255
1256 ret = IRQ_HANDLED;
1257 spin_unlock(&isc->dma_queue_lock);
1258 }
1259
1260 if (pending & ISC_INT_HISDONE) {
1261 schedule_work(&isc->awb_work);
1262 ret = IRQ_HANDLED;
1263 }
1264
1265 return ret;
1266 }
1267 EXPORT_SYMBOL_GPL(atmel_isc_interrupt);
1268
isc_hist_count(struct isc_device * isc,u32 * min,u32 * max)1269 static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max)
1270 {
1271 struct regmap *regmap = isc->regmap;
1272 struct isc_ctrls *ctrls = &isc->ctrls;
1273 u32 *hist_count = &ctrls->hist_count[ctrls->hist_id];
1274 u32 *hist_entry = &ctrls->hist_entry[0];
1275 u32 i;
1276
1277 *min = 0;
1278 *max = HIST_ENTRIES;
1279
1280 regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry,
1281 hist_entry, HIST_ENTRIES);
1282
1283 *hist_count = 0;
1284 /*
1285 * we deliberately ignore the end of the histogram,
1286 * the most white pixels
1287 */
1288 for (i = 1; i < HIST_ENTRIES; i++) {
1289 if (*hist_entry && !*min)
1290 *min = i;
1291 if (*hist_entry)
1292 *max = i;
1293 *hist_count += i * (*hist_entry++);
1294 }
1295
1296 if (!*min)
1297 *min = 1;
1298
1299 v4l2_dbg(1, debug, &isc->v4l2_dev,
1300 "isc wb: hist_id %u, hist_count %u",
1301 ctrls->hist_id, *hist_count);
1302 }
1303
isc_wb_update(struct isc_ctrls * ctrls)1304 static void isc_wb_update(struct isc_ctrls *ctrls)
1305 {
1306 struct isc_device *isc = container_of(ctrls, struct isc_device, ctrls);
1307 u32 *hist_count = &ctrls->hist_count[0];
1308 u32 c, offset[4];
1309 u64 avg = 0;
1310 /* We compute two gains, stretch gain and grey world gain */
1311 u32 s_gain[4], gw_gain[4];
1312
1313 /*
1314 * According to Grey World, we need to set gains for R/B to normalize
1315 * them towards the green channel.
1316 * Thus we want to keep Green as fixed and adjust only Red/Blue
1317 * Compute the average of the both green channels first
1318 */
1319 avg = (u64)hist_count[ISC_HIS_CFG_MODE_GR] +
1320 (u64)hist_count[ISC_HIS_CFG_MODE_GB];
1321 avg >>= 1;
1322
1323 v4l2_dbg(1, debug, &isc->v4l2_dev,
1324 "isc wb: green components average %llu\n", avg);
1325
1326 /* Green histogram is null, nothing to do */
1327 if (!avg)
1328 return;
1329
1330 for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
1331 /*
1332 * the color offset is the minimum value of the histogram.
1333 * we stretch this color to the full range by substracting
1334 * this value from the color component.
1335 */
1336 offset[c] = ctrls->hist_minmax[c][HIST_MIN_INDEX];
1337 /*
1338 * The offset is always at least 1. If the offset is 1, we do
1339 * not need to adjust it, so our result must be zero.
1340 * the offset is computed in a histogram on 9 bits (0..512)
1341 * but the offset in register is based on
1342 * 12 bits pipeline (0..4096).
1343 * we need to shift with the 3 bits that the histogram is
1344 * ignoring
1345 */
1346 ctrls->offset[c] = (offset[c] - 1) << 3;
1347
1348 /*
1349 * the offset is then taken and converted to 2's complements,
1350 * and must be negative, as we subtract this value from the
1351 * color components
1352 */
1353 ctrls->offset[c] = -ctrls->offset[c];
1354
1355 /*
1356 * the stretch gain is the total number of histogram bins
1357 * divided by the actual range of color component (Max - Min)
1358 * If we compute gain like this, the actual color component
1359 * will be stretched to the full histogram.
1360 * We need to shift 9 bits for precision, we have 9 bits for
1361 * decimals
1362 */
1363 s_gain[c] = (HIST_ENTRIES << 9) /
1364 (ctrls->hist_minmax[c][HIST_MAX_INDEX] -
1365 ctrls->hist_minmax[c][HIST_MIN_INDEX] + 1);
1366
1367 /*
1368 * Now we have to compute the gain w.r.t. the average.
1369 * Add/lose gain to the component towards the average.
1370 * If it happens that the component is zero, use the
1371 * fixed point value : 1.0 gain.
1372 */
1373 if (hist_count[c])
1374 gw_gain[c] = div_u64(avg << 9, hist_count[c]);
1375 else
1376 gw_gain[c] = 1 << 9;
1377
1378 v4l2_dbg(1, debug, &isc->v4l2_dev,
1379 "isc wb: component %d, s_gain %u, gw_gain %u\n",
1380 c, s_gain[c], gw_gain[c]);
1381 /* multiply both gains and adjust for decimals */
1382 ctrls->gain[c] = s_gain[c] * gw_gain[c];
1383 ctrls->gain[c] >>= 9;
1384
1385 /* make sure we are not out of range */
1386 ctrls->gain[c] = clamp_val(ctrls->gain[c], 0, GENMASK(12, 0));
1387
1388 v4l2_dbg(1, debug, &isc->v4l2_dev,
1389 "isc wb: component %d, final gain %u\n",
1390 c, ctrls->gain[c]);
1391 }
1392 }
1393
isc_awb_work(struct work_struct * w)1394 static void isc_awb_work(struct work_struct *w)
1395 {
1396 struct isc_device *isc =
1397 container_of(w, struct isc_device, awb_work);
1398 struct regmap *regmap = isc->regmap;
1399 struct isc_ctrls *ctrls = &isc->ctrls;
1400 u32 hist_id = ctrls->hist_id;
1401 u32 baysel;
1402 unsigned long flags;
1403 u32 min, max;
1404 int ret;
1405
1406 if (ctrls->hist_stat != HIST_ENABLED)
1407 return;
1408
1409 isc_hist_count(isc, &min, &max);
1410
1411 v4l2_dbg(1, debug, &isc->v4l2_dev,
1412 "isc wb mode %d: hist min %u , max %u\n", hist_id, min, max);
1413
1414 ctrls->hist_minmax[hist_id][HIST_MIN_INDEX] = min;
1415 ctrls->hist_minmax[hist_id][HIST_MAX_INDEX] = max;
1416
1417 if (hist_id != ISC_HIS_CFG_MODE_B) {
1418 hist_id++;
1419 } else {
1420 isc_wb_update(ctrls);
1421 hist_id = ISC_HIS_CFG_MODE_GR;
1422 }
1423
1424 ctrls->hist_id = hist_id;
1425 baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT;
1426
1427 ret = pm_runtime_resume_and_get(isc->dev);
1428 if (ret < 0)
1429 return;
1430
1431 /*
1432 * only update if we have all the required histograms and controls
1433 * if awb has been disabled, we need to reset registers as well.
1434 */
1435 if (hist_id == ISC_HIS_CFG_MODE_GR || ctrls->awb == ISC_WB_NONE) {
1436 /*
1437 * It may happen that DMA Done IRQ will trigger while we are
1438 * updating white balance registers here.
1439 * In that case, only parts of the controls have been updated.
1440 * We can avoid that by locking the section.
1441 */
1442 spin_lock_irqsave(&isc->awb_lock, flags);
1443 isc_update_awb_ctrls(isc);
1444 spin_unlock_irqrestore(&isc->awb_lock, flags);
1445
1446 /*
1447 * if we are doing just the one time white balance adjustment,
1448 * we are basically done.
1449 */
1450 if (ctrls->awb == ISC_WB_ONETIME) {
1451 v4l2_info(&isc->v4l2_dev,
1452 "Completed one time white-balance adjustment.\n");
1453 /* update the v4l2 controls values */
1454 isc_update_v4l2_ctrls(isc);
1455 ctrls->awb = ISC_WB_NONE;
1456 }
1457 }
1458 regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
1459 hist_id | baysel | ISC_HIS_CFG_RAR);
1460
1461 /*
1462 * We have to make sure the streaming has not stopped meanwhile.
1463 * ISC requires a frame to clock the internal profile update.
1464 * To avoid issues, lock the sequence with a mutex
1465 */
1466 mutex_lock(&isc->awb_mutex);
1467
1468 /* streaming is not active anymore */
1469 if (isc->stop) {
1470 mutex_unlock(&isc->awb_mutex);
1471 return;
1472 }
1473
1474 isc_update_profile(isc);
1475
1476 mutex_unlock(&isc->awb_mutex);
1477
1478 /* if awb has been disabled, we don't need to start another histogram */
1479 if (ctrls->awb)
1480 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
1481
1482 pm_runtime_put_sync(isc->dev);
1483 }
1484
isc_s_ctrl(struct v4l2_ctrl * ctrl)1485 static int isc_s_ctrl(struct v4l2_ctrl *ctrl)
1486 {
1487 struct isc_device *isc = container_of(ctrl->handler,
1488 struct isc_device, ctrls.handler);
1489 struct isc_ctrls *ctrls = &isc->ctrls;
1490
1491 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
1492 return 0;
1493
1494 switch (ctrl->id) {
1495 case V4L2_CID_BRIGHTNESS:
1496 ctrls->brightness = ctrl->val & ISC_CBC_BRIGHT_MASK;
1497 break;
1498 case V4L2_CID_CONTRAST:
1499 ctrls->contrast = ctrl->val & ISC_CBC_CONTRAST_MASK;
1500 break;
1501 case V4L2_CID_GAMMA:
1502 ctrls->gamma_index = ctrl->val;
1503 break;
1504 default:
1505 return -EINVAL;
1506 }
1507
1508 return 0;
1509 }
1510
1511 static const struct v4l2_ctrl_ops isc_ctrl_ops = {
1512 .s_ctrl = isc_s_ctrl,
1513 };
1514
isc_s_awb_ctrl(struct v4l2_ctrl * ctrl)1515 static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl)
1516 {
1517 struct isc_device *isc = container_of(ctrl->handler,
1518 struct isc_device, ctrls.handler);
1519 struct isc_ctrls *ctrls = &isc->ctrls;
1520
1521 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
1522 return 0;
1523
1524 switch (ctrl->id) {
1525 case V4L2_CID_AUTO_WHITE_BALANCE:
1526 if (ctrl->val == 1)
1527 ctrls->awb = ISC_WB_AUTO;
1528 else
1529 ctrls->awb = ISC_WB_NONE;
1530
1531 /* configure the controls with new values from v4l2 */
1532 if (ctrl->cluster[ISC_CTRL_R_GAIN]->is_new)
1533 ctrls->gain[ISC_HIS_CFG_MODE_R] = isc->r_gain_ctrl->val;
1534 if (ctrl->cluster[ISC_CTRL_B_GAIN]->is_new)
1535 ctrls->gain[ISC_HIS_CFG_MODE_B] = isc->b_gain_ctrl->val;
1536 if (ctrl->cluster[ISC_CTRL_GR_GAIN]->is_new)
1537 ctrls->gain[ISC_HIS_CFG_MODE_GR] = isc->gr_gain_ctrl->val;
1538 if (ctrl->cluster[ISC_CTRL_GB_GAIN]->is_new)
1539 ctrls->gain[ISC_HIS_CFG_MODE_GB] = isc->gb_gain_ctrl->val;
1540
1541 if (ctrl->cluster[ISC_CTRL_R_OFF]->is_new)
1542 ctrls->offset[ISC_HIS_CFG_MODE_R] = isc->r_off_ctrl->val;
1543 if (ctrl->cluster[ISC_CTRL_B_OFF]->is_new)
1544 ctrls->offset[ISC_HIS_CFG_MODE_B] = isc->b_off_ctrl->val;
1545 if (ctrl->cluster[ISC_CTRL_GR_OFF]->is_new)
1546 ctrls->offset[ISC_HIS_CFG_MODE_GR] = isc->gr_off_ctrl->val;
1547 if (ctrl->cluster[ISC_CTRL_GB_OFF]->is_new)
1548 ctrls->offset[ISC_HIS_CFG_MODE_GB] = isc->gb_off_ctrl->val;
1549
1550 isc_update_awb_ctrls(isc);
1551
1552 mutex_lock(&isc->awb_mutex);
1553 if (vb2_is_streaming(&isc->vb2_vidq)) {
1554 /*
1555 * If we are streaming, we can update profile to
1556 * have the new settings in place.
1557 */
1558 isc_update_profile(isc);
1559 } else {
1560 /*
1561 * The auto cluster will activate automatically this
1562 * control. This has to be deactivated when not
1563 * streaming.
1564 */
1565 v4l2_ctrl_activate(isc->do_wb_ctrl, false);
1566 }
1567 mutex_unlock(&isc->awb_mutex);
1568
1569 /* if we have autowhitebalance on, start histogram procedure */
1570 if (ctrls->awb == ISC_WB_AUTO &&
1571 vb2_is_streaming(&isc->vb2_vidq) &&
1572 ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
1573 isc_set_histogram(isc, true);
1574
1575 /*
1576 * for one time whitebalance adjustment, check the button,
1577 * if it's pressed, perform the one time operation.
1578 */
1579 if (ctrls->awb == ISC_WB_NONE &&
1580 ctrl->cluster[ISC_CTRL_DO_WB]->is_new &&
1581 !(ctrl->cluster[ISC_CTRL_DO_WB]->flags &
1582 V4L2_CTRL_FLAG_INACTIVE)) {
1583 ctrls->awb = ISC_WB_ONETIME;
1584 isc_set_histogram(isc, true);
1585 v4l2_dbg(1, debug, &isc->v4l2_dev,
1586 "One time white-balance started.\n");
1587 }
1588 return 0;
1589 }
1590 return 0;
1591 }
1592
isc_g_volatile_awb_ctrl(struct v4l2_ctrl * ctrl)1593 static int isc_g_volatile_awb_ctrl(struct v4l2_ctrl *ctrl)
1594 {
1595 struct isc_device *isc = container_of(ctrl->handler,
1596 struct isc_device, ctrls.handler);
1597 struct isc_ctrls *ctrls = &isc->ctrls;
1598
1599 switch (ctrl->id) {
1600 /* being a cluster, this id will be called for every control */
1601 case V4L2_CID_AUTO_WHITE_BALANCE:
1602 ctrl->cluster[ISC_CTRL_R_GAIN]->val =
1603 ctrls->gain[ISC_HIS_CFG_MODE_R];
1604 ctrl->cluster[ISC_CTRL_B_GAIN]->val =
1605 ctrls->gain[ISC_HIS_CFG_MODE_B];
1606 ctrl->cluster[ISC_CTRL_GR_GAIN]->val =
1607 ctrls->gain[ISC_HIS_CFG_MODE_GR];
1608 ctrl->cluster[ISC_CTRL_GB_GAIN]->val =
1609 ctrls->gain[ISC_HIS_CFG_MODE_GB];
1610
1611 ctrl->cluster[ISC_CTRL_R_OFF]->val =
1612 ctrls->offset[ISC_HIS_CFG_MODE_R];
1613 ctrl->cluster[ISC_CTRL_B_OFF]->val =
1614 ctrls->offset[ISC_HIS_CFG_MODE_B];
1615 ctrl->cluster[ISC_CTRL_GR_OFF]->val =
1616 ctrls->offset[ISC_HIS_CFG_MODE_GR];
1617 ctrl->cluster[ISC_CTRL_GB_OFF]->val =
1618 ctrls->offset[ISC_HIS_CFG_MODE_GB];
1619 break;
1620 }
1621 return 0;
1622 }
1623
1624 static const struct v4l2_ctrl_ops isc_awb_ops = {
1625 .s_ctrl = isc_s_awb_ctrl,
1626 .g_volatile_ctrl = isc_g_volatile_awb_ctrl,
1627 };
1628
1629 #define ISC_CTRL_OFF(_name, _id, _name_str) \
1630 static const struct v4l2_ctrl_config _name = { \
1631 .ops = &isc_awb_ops, \
1632 .id = _id, \
1633 .name = _name_str, \
1634 .type = V4L2_CTRL_TYPE_INTEGER, \
1635 .flags = V4L2_CTRL_FLAG_SLIDER, \
1636 .min = -4095, \
1637 .max = 4095, \
1638 .step = 1, \
1639 .def = 0, \
1640 }
1641
1642 ISC_CTRL_OFF(isc_r_off_ctrl, ISC_CID_R_OFFSET, "Red Component Offset");
1643 ISC_CTRL_OFF(isc_b_off_ctrl, ISC_CID_B_OFFSET, "Blue Component Offset");
1644 ISC_CTRL_OFF(isc_gr_off_ctrl, ISC_CID_GR_OFFSET, "Green Red Component Offset");
1645 ISC_CTRL_OFF(isc_gb_off_ctrl, ISC_CID_GB_OFFSET, "Green Blue Component Offset");
1646
1647 #define ISC_CTRL_GAIN(_name, _id, _name_str) \
1648 static const struct v4l2_ctrl_config _name = { \
1649 .ops = &isc_awb_ops, \
1650 .id = _id, \
1651 .name = _name_str, \
1652 .type = V4L2_CTRL_TYPE_INTEGER, \
1653 .flags = V4L2_CTRL_FLAG_SLIDER, \
1654 .min = 0, \
1655 .max = 8191, \
1656 .step = 1, \
1657 .def = 512, \
1658 }
1659
1660 ISC_CTRL_GAIN(isc_r_gain_ctrl, ISC_CID_R_GAIN, "Red Component Gain");
1661 ISC_CTRL_GAIN(isc_b_gain_ctrl, ISC_CID_B_GAIN, "Blue Component Gain");
1662 ISC_CTRL_GAIN(isc_gr_gain_ctrl, ISC_CID_GR_GAIN, "Green Red Component Gain");
1663 ISC_CTRL_GAIN(isc_gb_gain_ctrl, ISC_CID_GB_GAIN, "Green Blue Component Gain");
1664
isc_ctrl_init(struct isc_device * isc)1665 static int isc_ctrl_init(struct isc_device *isc)
1666 {
1667 const struct v4l2_ctrl_ops *ops = &isc_ctrl_ops;
1668 struct isc_ctrls *ctrls = &isc->ctrls;
1669 struct v4l2_ctrl_handler *hdl = &ctrls->handler;
1670 int ret;
1671
1672 ctrls->hist_stat = HIST_INIT;
1673 isc_reset_awb_ctrls(isc);
1674
1675 ret = v4l2_ctrl_handler_init(hdl, 13);
1676 if (ret < 0)
1677 return ret;
1678
1679 /* Initialize product specific controls. For example, contrast */
1680 isc->config_ctrls(isc, ops);
1681
1682 ctrls->brightness = 0;
1683
1684 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0);
1685 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1,
1686 isc->gamma_max);
1687 isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
1688 V4L2_CID_AUTO_WHITE_BALANCE,
1689 0, 1, 1, 1);
1690
1691 /* do_white_balance is a button, so min,max,step,default are ignored */
1692 isc->do_wb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
1693 V4L2_CID_DO_WHITE_BALANCE,
1694 0, 0, 0, 0);
1695
1696 if (!isc->do_wb_ctrl) {
1697 ret = hdl->error;
1698 v4l2_ctrl_handler_free(hdl);
1699 return ret;
1700 }
1701
1702 v4l2_ctrl_activate(isc->do_wb_ctrl, false);
1703
1704 isc->r_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_gain_ctrl, NULL);
1705 isc->b_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_gain_ctrl, NULL);
1706 isc->gr_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_gain_ctrl, NULL);
1707 isc->gb_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_gain_ctrl, NULL);
1708 isc->r_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_off_ctrl, NULL);
1709 isc->b_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_off_ctrl, NULL);
1710 isc->gr_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_off_ctrl, NULL);
1711 isc->gb_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_off_ctrl, NULL);
1712
1713 /*
1714 * The cluster is in auto mode with autowhitebalance enabled
1715 * and manual mode otherwise.
1716 */
1717 v4l2_ctrl_auto_cluster(10, &isc->awb_ctrl, 0, true);
1718
1719 v4l2_ctrl_handler_setup(hdl);
1720
1721 return 0;
1722 }
1723
isc_async_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_connection * asd)1724 static int isc_async_bound(struct v4l2_async_notifier *notifier,
1725 struct v4l2_subdev *subdev,
1726 struct v4l2_async_connection *asd)
1727 {
1728 struct isc_device *isc = container_of(notifier->v4l2_dev,
1729 struct isc_device, v4l2_dev);
1730 struct isc_subdev_entity *subdev_entity =
1731 container_of(notifier, struct isc_subdev_entity, notifier);
1732
1733 if (video_is_registered(&isc->video_dev)) {
1734 v4l2_err(&isc->v4l2_dev, "only supports one sub-device.\n");
1735 return -EBUSY;
1736 }
1737
1738 subdev_entity->sd = subdev;
1739
1740 return 0;
1741 }
1742
isc_async_unbind(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_connection * asd)1743 static void isc_async_unbind(struct v4l2_async_notifier *notifier,
1744 struct v4l2_subdev *subdev,
1745 struct v4l2_async_connection *asd)
1746 {
1747 struct isc_device *isc = container_of(notifier->v4l2_dev,
1748 struct isc_device, v4l2_dev);
1749 mutex_destroy(&isc->awb_mutex);
1750 cancel_work_sync(&isc->awb_work);
1751 video_unregister_device(&isc->video_dev);
1752 v4l2_ctrl_handler_free(&isc->ctrls.handler);
1753 }
1754
find_format_by_code(struct isc_device * isc,unsigned int code,int * index)1755 static struct isc_format *find_format_by_code(struct isc_device *isc,
1756 unsigned int code, int *index)
1757 {
1758 struct isc_format *fmt = &isc->formats_list[0];
1759 unsigned int i;
1760
1761 for (i = 0; i < isc->formats_list_size; i++) {
1762 if (fmt->mbus_code == code) {
1763 *index = i;
1764 return fmt;
1765 }
1766
1767 fmt++;
1768 }
1769
1770 return NULL;
1771 }
1772
isc_formats_init(struct isc_device * isc)1773 static int isc_formats_init(struct isc_device *isc)
1774 {
1775 struct isc_format *fmt;
1776 struct v4l2_subdev *subdev = isc->current_subdev->sd;
1777 unsigned int num_fmts, i, j;
1778 u32 list_size = isc->formats_list_size;
1779 struct v4l2_subdev_mbus_code_enum mbus_code = {
1780 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1781 };
1782
1783 num_fmts = 0;
1784 while (!v4l2_subdev_call(subdev, pad, enum_mbus_code,
1785 NULL, &mbus_code)) {
1786 mbus_code.index++;
1787
1788 fmt = find_format_by_code(isc, mbus_code.code, &i);
1789 if (!fmt) {
1790 v4l2_warn(&isc->v4l2_dev, "Mbus code %x not supported\n",
1791 mbus_code.code);
1792 continue;
1793 }
1794
1795 fmt->sd_support = true;
1796 num_fmts++;
1797 }
1798
1799 if (!num_fmts)
1800 return -ENXIO;
1801
1802 isc->num_user_formats = num_fmts;
1803 isc->user_formats = devm_kcalloc(isc->dev,
1804 num_fmts, sizeof(*isc->user_formats),
1805 GFP_KERNEL);
1806 if (!isc->user_formats)
1807 return -ENOMEM;
1808
1809 fmt = &isc->formats_list[0];
1810 for (i = 0, j = 0; i < list_size; i++) {
1811 if (fmt->sd_support)
1812 isc->user_formats[j++] = fmt;
1813 fmt++;
1814 }
1815
1816 return 0;
1817 }
1818
isc_set_default_fmt(struct isc_device * isc)1819 static int isc_set_default_fmt(struct isc_device *isc)
1820 {
1821 struct v4l2_format f = {
1822 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
1823 .fmt.pix = {
1824 .width = VGA_WIDTH,
1825 .height = VGA_HEIGHT,
1826 .field = V4L2_FIELD_NONE,
1827 .pixelformat = isc->user_formats[0]->fourcc,
1828 },
1829 };
1830 int ret;
1831
1832 ret = isc_try_fmt(isc, &f, NULL);
1833 if (ret)
1834 return ret;
1835
1836 isc->fmt = f;
1837 return 0;
1838 }
1839
isc_async_complete(struct v4l2_async_notifier * notifier)1840 static int isc_async_complete(struct v4l2_async_notifier *notifier)
1841 {
1842 struct isc_device *isc = container_of(notifier->v4l2_dev,
1843 struct isc_device, v4l2_dev);
1844 struct video_device *vdev = &isc->video_dev;
1845 struct vb2_queue *q = &isc->vb2_vidq;
1846 int ret = 0;
1847
1848 INIT_WORK(&isc->awb_work, isc_awb_work);
1849
1850 ret = v4l2_device_register_subdev_nodes(&isc->v4l2_dev);
1851 if (ret < 0) {
1852 v4l2_err(&isc->v4l2_dev, "Failed to register subdev nodes\n");
1853 return ret;
1854 }
1855
1856 isc->current_subdev = container_of(notifier,
1857 struct isc_subdev_entity, notifier);
1858 mutex_init(&isc->lock);
1859 mutex_init(&isc->awb_mutex);
1860
1861 init_completion(&isc->comp);
1862
1863 /* Initialize videobuf2 queue */
1864 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1865 q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
1866 q->drv_priv = isc;
1867 q->buf_struct_size = sizeof(struct isc_buffer);
1868 q->ops = &isc_vb2_ops;
1869 q->mem_ops = &vb2_dma_contig_memops;
1870 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1871 q->lock = &isc->lock;
1872 q->min_queued_buffers = 1;
1873 q->dev = isc->dev;
1874
1875 ret = vb2_queue_init(q);
1876 if (ret < 0) {
1877 v4l2_err(&isc->v4l2_dev,
1878 "vb2_queue_init() failed: %d\n", ret);
1879 goto isc_async_complete_err;
1880 }
1881
1882 /* Init video dma queues */
1883 INIT_LIST_HEAD(&isc->dma_queue);
1884 spin_lock_init(&isc->dma_queue_lock);
1885 spin_lock_init(&isc->awb_lock);
1886
1887 ret = isc_formats_init(isc);
1888 if (ret < 0) {
1889 v4l2_err(&isc->v4l2_dev,
1890 "Init format failed: %d\n", ret);
1891 goto isc_async_complete_err;
1892 }
1893
1894 ret = isc_set_default_fmt(isc);
1895 if (ret) {
1896 v4l2_err(&isc->v4l2_dev, "Could not set default format\n");
1897 goto isc_async_complete_err;
1898 }
1899
1900 ret = isc_ctrl_init(isc);
1901 if (ret) {
1902 v4l2_err(&isc->v4l2_dev, "Init isc ctrols failed: %d\n", ret);
1903 goto isc_async_complete_err;
1904 }
1905
1906 /* Register video device */
1907 strscpy(vdev->name, KBUILD_MODNAME, sizeof(vdev->name));
1908 vdev->release = video_device_release_empty;
1909 vdev->fops = &isc_fops;
1910 vdev->ioctl_ops = &isc_ioctl_ops;
1911 vdev->v4l2_dev = &isc->v4l2_dev;
1912 vdev->vfl_dir = VFL_DIR_RX;
1913 vdev->queue = q;
1914 vdev->lock = &isc->lock;
1915 vdev->ctrl_handler = &isc->ctrls.handler;
1916 vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE;
1917 video_set_drvdata(vdev, isc);
1918
1919 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
1920 if (ret < 0) {
1921 v4l2_err(&isc->v4l2_dev,
1922 "video_register_device failed: %d\n", ret);
1923 goto isc_async_complete_err;
1924 }
1925
1926 return 0;
1927
1928 isc_async_complete_err:
1929 mutex_destroy(&isc->awb_mutex);
1930 mutex_destroy(&isc->lock);
1931 return ret;
1932 }
1933
1934 const struct v4l2_async_notifier_operations atmel_isc_async_ops = {
1935 .bound = isc_async_bound,
1936 .unbind = isc_async_unbind,
1937 .complete = isc_async_complete,
1938 };
1939 EXPORT_SYMBOL_GPL(atmel_isc_async_ops);
1940
atmel_isc_subdev_cleanup(struct isc_device * isc)1941 void atmel_isc_subdev_cleanup(struct isc_device *isc)
1942 {
1943 struct isc_subdev_entity *subdev_entity;
1944
1945 list_for_each_entry(subdev_entity, &isc->subdev_entities, list) {
1946 v4l2_async_nf_unregister(&subdev_entity->notifier);
1947 v4l2_async_nf_cleanup(&subdev_entity->notifier);
1948 }
1949
1950 INIT_LIST_HEAD(&isc->subdev_entities);
1951 }
1952 EXPORT_SYMBOL_GPL(atmel_isc_subdev_cleanup);
1953
atmel_isc_pipeline_init(struct isc_device * isc)1954 int atmel_isc_pipeline_init(struct isc_device *isc)
1955 {
1956 struct device *dev = isc->dev;
1957 struct regmap *regmap = isc->regmap;
1958 struct regmap_field *regs;
1959 unsigned int i;
1960
1961 /*
1962 * DPCEN-->GDCEN-->BLCEN-->WB-->CFA-->CC-->
1963 * GAM-->VHXS-->CSC-->CBC-->SUB422-->SUB420
1964 */
1965 const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = {
1966 REG_FIELD(ISC_DPC_CTRL, 0, 0),
1967 REG_FIELD(ISC_DPC_CTRL, 1, 1),
1968 REG_FIELD(ISC_DPC_CTRL, 2, 2),
1969 REG_FIELD(ISC_WB_CTRL, 0, 0),
1970 REG_FIELD(ISC_CFA_CTRL, 0, 0),
1971 REG_FIELD(ISC_CC_CTRL, 0, 0),
1972 REG_FIELD(ISC_GAM_CTRL, 0, 0),
1973 REG_FIELD(ISC_GAM_CTRL, 1, 1),
1974 REG_FIELD(ISC_GAM_CTRL, 2, 2),
1975 REG_FIELD(ISC_GAM_CTRL, 3, 3),
1976 REG_FIELD(ISC_VHXS_CTRL, 0, 0),
1977 REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),
1978 REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),
1979 REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0),
1980 REG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0),
1981 };
1982
1983 for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
1984 regs = devm_regmap_field_alloc(dev, regmap, regfields[i]);
1985 if (IS_ERR(regs))
1986 return PTR_ERR(regs);
1987
1988 isc->pipeline[i] = regs;
1989 }
1990
1991 return 0;
1992 }
1993 EXPORT_SYMBOL_GPL(atmel_isc_pipeline_init);
1994
1995 /* regmap configuration */
1996 #define ATMEL_ISC_REG_MAX 0xd5c
1997 const struct regmap_config atmel_isc_regmap_config = {
1998 .reg_bits = 32,
1999 .reg_stride = 4,
2000 .val_bits = 32,
2001 .max_register = ATMEL_ISC_REG_MAX,
2002 };
2003 EXPORT_SYMBOL_GPL(atmel_isc_regmap_config);
2004
2005 MODULE_AUTHOR("Songjun Wu");
2006 MODULE_AUTHOR("Eugen Hristev");
2007 MODULE_DESCRIPTION("Atmel ISC common code base");
2008 MODULE_LICENSE("GPL v2");
2009