1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLAT_ARM_H 7 #define PLAT_ARM_H 8 9 #include <stdbool.h> 10 #include <stdint.h> 11 12 #include <common/desc_image_load.h> 13 #include <drivers/arm/tzc_common.h> 14 #include <lib/bakery_lock.h> 15 #include <lib/cassert.h> 16 #include <lib/el3_runtime/cpu_data.h> 17 #include <lib/gpt_rme/gpt_rme.h> 18 #include <lib/spinlock.h> 19 #include <lib/transfer_list.h> 20 #include <lib/utils_def.h> 21 #include <lib/xlat_tables/xlat_tables_compat.h> 22 23 /******************************************************************************* 24 * Forward declarations 25 ******************************************************************************/ 26 struct meminfo; 27 struct image_info; 28 struct bl_params; 29 30 typedef struct arm_tzc_regions_info { 31 unsigned long long base; 32 unsigned long long end; 33 unsigned int sec_attr; 34 unsigned int nsaid_permissions; 35 } arm_tzc_regions_info_t; 36 37 typedef struct arm_gpt_info { 38 pas_region_t *pas_region_base; 39 unsigned int pas_region_count; 40 uintptr_t l0_base; 41 uintptr_t l1_base; 42 size_t l0_size; 43 size_t l1_size; 44 gpccr_pps_e pps; 45 gpccr_pgs_e pgs; 46 } arm_gpt_info_t; 47 48 /******************************************************************************* 49 * Default mapping definition of the TrustZone Controller for ARM standard 50 * platforms. 51 * Configure: 52 * - Region 0 with no access; 53 * - Region 1 with secure access only; 54 * - the remaining DRAM regions access from the given Non-Secure masters. 55 ******************************************************************************/ 56 57 #if ENABLE_RME 58 #define ARM_TZC_RME_REGIONS_DEF \ 59 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\ 60 {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \ 61 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 62 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 63 /* Realm and Shared area share the same PAS */ \ 64 {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 65 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 66 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 67 PLAT_ARM_TZC_NS_DEV_ACCESS} 68 #endif 69 70 #if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) 71 #define ARM_TZC_REGIONS_DEF \ 72 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ 73 TZC_REGION_S_RDWR, 0}, \ 74 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 75 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 76 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 77 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 78 {PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \ 79 PLAT_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \ 80 PLAT_ARM_TZC_NS_DEV_ACCESS} 81 82 #elif ENABLE_RME 83 #if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 84 MEASURED_BOOT 85 #define ARM_TZC_REGIONS_DEF \ 86 ARM_TZC_RME_REGIONS_DEF, \ 87 {ARM_EVENT_LOG_DRAM1_BASE, ARM_EVENT_LOG_DRAM1_END, \ 88 TZC_REGION_S_RDWR, 0} 89 #else 90 #define ARM_TZC_REGIONS_DEF \ 91 ARM_TZC_RME_REGIONS_DEF 92 #endif 93 94 #else 95 #define ARM_TZC_REGIONS_DEF \ 96 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ 97 TZC_REGION_S_RDWR, 0}, \ 98 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 99 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 100 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 101 PLAT_ARM_TZC_NS_DEV_ACCESS} 102 #endif 103 104 #define ARM_CASSERT_MMAP \ 105 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ 106 assert_plat_arm_mmap_mismatch); \ 107 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ 108 <= MAX_MMAP_REGIONS, \ 109 assert_max_mmap_regions); 110 111 void arm_setup_romlib(void); 112 113 #if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) 114 /* 115 * Use this macro to instantiate lock before it is used in below 116 * arm_lock_xxx() macros 117 */ 118 #define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock) 119 #define ARM_LOCK_GET_INSTANCE (&arm_lock) 120 121 #if !HW_ASSISTED_COHERENCY 122 #define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock) 123 #else 124 #define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock 125 #endif 126 #define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock) 127 128 /* 129 * These are wrapper macros to the Coherent Memory Bakery Lock API. 130 */ 131 #define arm_lock_init() bakery_lock_init(&arm_lock) 132 #define arm_lock_get() bakery_lock_get(&arm_lock) 133 #define arm_lock_release() bakery_lock_release(&arm_lock) 134 135 #else 136 137 /* 138 * Empty macros for all other BL stages other than BL31 and BL32 139 */ 140 #define ARM_INSTANTIATE_LOCK static int arm_lock __unused 141 #define ARM_LOCK_GET_INSTANCE 0 142 #define arm_lock_init() 143 #define arm_lock_get() 144 #define arm_lock_release() 145 146 #endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */ 147 148 #if ARM_RECOM_STATE_ID_ENC 149 /* 150 * Macros used to parse state information from State-ID if it is using the 151 * recommended encoding for State-ID. 152 */ 153 #define ARM_LOCAL_PSTATE_WIDTH 4 154 #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) 155 156 /* Last in Level for the OS-initiated */ 157 #define ARM_LAST_AT_PLVL_MASK (ARM_LOCAL_PSTATE_MASK << \ 158 (ARM_LOCAL_PSTATE_WIDTH * \ 159 (PLAT_MAX_PWR_LVL + 1))) 160 161 /* Macros to construct the composite power state */ 162 163 /* Make composite power state parameter till power level 0 */ 164 #if PSCI_EXTENDED_STATE_ID 165 166 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 167 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 168 #else 169 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 170 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 171 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 172 ((type) << PSTATE_TYPE_SHIFT)) 173 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 174 175 /* Make composite power state parameter till power level 1 */ 176 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 177 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ 178 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 179 180 /* Make composite power state parameter till power level 2 */ 181 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 182 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ 183 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 184 185 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 186 187 /* ARM State switch error codes */ 188 #define STATE_SW_E_PARAM (-2) 189 #define STATE_SW_E_DENIED (-3) 190 191 /* plat_get_rotpk_info() flags */ 192 #define ARM_ROTPK_REGS_ID 1 193 #define ARM_ROTPK_DEVEL_RSA_ID 2 194 #define ARM_ROTPK_DEVEL_ECDSA_ID 3 195 #define ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID 4 196 #define ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID 5 197 198 #define ARM_USE_DEVEL_ROTPK \ 199 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \ 200 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) || \ 201 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID) || \ 202 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID) 203 204 /* IO storage utility functions */ 205 int arm_io_setup(void); 206 207 /* Set image specification in IO block policy */ 208 int arm_set_image_source(unsigned int image_id, const char *part_name, 209 uintptr_t *dev_handle, uintptr_t *image_spec); 210 void arm_set_fip_addr(uint32_t active_fw_bank_idx); 211 212 /* Security utility functions */ 213 void arm_tzc400_setup(uintptr_t tzc_base, 214 const arm_tzc_regions_info_t *tzc_regions); 215 struct tzc_dmc500_driver_data; 216 void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, 217 const arm_tzc_regions_info_t *tzc_regions); 218 219 /* Console utility functions */ 220 void arm_console_boot_init(void); 221 void arm_console_boot_end(void); 222 void arm_console_runtime_init(void); 223 void arm_console_runtime_end(void); 224 225 /* Systimer utility function */ 226 void arm_configure_sys_timer(void); 227 228 /* PM utility functions */ 229 int arm_validate_power_state(unsigned int power_state, 230 psci_power_state_t *req_state); 231 int arm_validate_psci_entrypoint(uintptr_t entrypoint); 232 int arm_validate_ns_entrypoint(uintptr_t entrypoint); 233 void arm_system_pwr_domain_save(void); 234 void arm_system_pwr_domain_resume(void); 235 int arm_psci_read_mem_protect(int *enabled); 236 int arm_nor_psci_write_mem_protect(int val); 237 void arm_nor_psci_do_static_mem_protect(void); 238 void arm_nor_psci_do_dyn_mem_protect(void); 239 int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); 240 241 /* Topology utility function */ 242 int arm_check_mpidr(u_register_t mpidr); 243 244 /* BL1 utility functions */ 245 void arm_bl1_early_platform_setup(void); 246 void arm_bl1_platform_setup(void); 247 void arm_bl1_plat_arch_setup(void); 248 249 /* BL2 utility functions */ 250 void arm_bl2_early_platform_setup(uintptr_t fw_config, struct meminfo *mem_layout); 251 void arm_bl2_platform_setup(void); 252 void arm_bl2_plat_arch_setup(void); 253 uint32_t arm_get_spsr_for_bl32_entry(void); 254 uint32_t arm_get_spsr_for_bl33_entry(void); 255 int arm_bl2_plat_handle_post_image_load(unsigned int image_id); 256 int arm_bl2_handle_post_image_load(unsigned int image_id); 257 struct bl_params *arm_get_next_bl_params(void); 258 void arm_bl2_setup_next_ep_info(bl_mem_params_node_t *next_param_node); 259 260 /* BL2 at EL3 functions */ 261 void arm_bl2_el3_early_platform_setup(void); 262 void arm_bl2_el3_plat_arch_setup(void); 263 264 /* BL2U utility functions */ 265 void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, 266 void *plat_info); 267 void arm_bl2u_platform_setup(void); 268 void arm_bl2u_plat_arch_setup(void); 269 270 /* BL31 utility functions */ 271 #if TRANSFER_LIST 272 void arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1, 273 u_register_t arg2, u_register_t arg3); 274 #else 275 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 276 uintptr_t hw_config, void *plat_params_from_bl2); 277 #endif 278 void arm_bl31_platform_setup(void); 279 void arm_bl31_plat_runtime_setup(void); 280 void arm_bl31_plat_arch_setup(void); 281 282 /* Firmware Handoff utility functions */ 283 void arm_transfer_list_dyn_cfg_init(struct transfer_list_header *secure_tl); 284 void arm_transfer_list_populate_ep_info(bl_mem_params_node_t *next_param_node, 285 struct transfer_list_header *secure_tl, 286 struct transfer_list_header *ns_tl); 287 void arm_transfer_list_copy_hw_config(struct transfer_list_header *secure_tl, 288 struct transfer_list_header *ns_tl); 289 290 /* TSP utility functions */ 291 void arm_tsp_early_platform_setup(void); 292 293 /* SP_MIN utility functions */ 294 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, 295 uintptr_t hw_config, void *plat_params_from_bl2); 296 void arm_sp_min_plat_runtime_setup(void); 297 void arm_sp_min_plat_arch_setup(void); 298 299 /* FIP TOC validity check */ 300 bool arm_io_is_toc_valid(void); 301 302 /* Utility functions for Dynamic Config */ 303 304 void arm_bl1_set_mbedtls_heap(void); 305 int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); 306 307 #if IMAGE_BL2 308 void arm_bl2_dyn_cfg_init(void); 309 #endif /* IMAGE_BL2 */ 310 311 #if MEASURED_BOOT 312 #if DICE_PROTECTION_ENVIRONMENT 313 int arm_set_nt_fw_info(int *ctx_handle); 314 int arm_set_tb_fw_info(int *ctx_handle); 315 int arm_get_tb_fw_info(int *ctx_handle); 316 #else 317 /* Specific to event log backend */ 318 int arm_set_tos_fw_info(uintptr_t log_addr, size_t log_size); 319 int arm_set_nt_fw_info( 320 /* 321 * Currently OP-TEE does not support reading DTBs from Secure memory 322 * and this option should be removed when feature is supported. 323 */ 324 #ifdef SPD_opteed 325 uintptr_t log_addr, 326 #endif 327 size_t log_size, uintptr_t *ns_log_addr); 328 int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size, 329 size_t log_max_size); 330 int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size, 331 size_t *log_max_size); 332 #endif /* DICE_PROTECTION_ENVIRONMENT */ 333 #endif /* MEASURED_BOOT */ 334 335 /* 336 * Free the memory storing initialization code only used during an images boot 337 * time so it can be reclaimed for runtime data 338 */ 339 void arm_free_init_memory(void); 340 341 /* 342 * Make the higher level translation tables read-only 343 */ 344 void arm_xlat_make_tables_readonly(void); 345 346 /* 347 * Mandatory functions required in ARM standard platforms 348 */ 349 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); 350 void plat_arm_gic_driver_init(void); 351 void plat_arm_gic_init(void); 352 void plat_arm_gic_cpuif_enable(void); 353 void plat_arm_gic_cpuif_disable(void); 354 void plat_arm_gic_redistif_on(void); 355 void plat_arm_gic_redistif_off(void); 356 void plat_arm_gic_pcpu_init(void); 357 void plat_arm_gic_save(void); 358 void plat_arm_gic_resume(void); 359 void plat_arm_security_setup(void); 360 void plat_arm_pwrc_setup(void); 361 void plat_arm_interconnect_init(void); 362 void plat_arm_interconnect_enter_coherency(void); 363 void plat_arm_interconnect_exit_coherency(void); 364 void plat_arm_program_trusted_mailbox(uintptr_t address); 365 bool plat_arm_bl1_fwu_needed(void); 366 __dead2 void plat_arm_error_handler(int err); 367 __dead2 void plat_arm_system_reset(void); 368 369 /* 370 * Optional functions in ARM standard platforms 371 */ 372 void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames); 373 int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, 374 unsigned int *flags); 375 int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len, 376 unsigned int *flags); 377 int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len, 378 unsigned int *flags); 379 int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len, 380 unsigned int *flags); 381 382 #if ARM_PLAT_MT 383 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); 384 #endif 385 386 unsigned int plat_cluster_id_by_mpidr(u_register_t mpidr); 387 388 /* 389 * This function is called after loading SCP_BL2 image and it is used to perform 390 * any platform-specific actions required to handle the SCP firmware. 391 */ 392 int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); 393 394 /* 395 * Optional functions required in ARM standard platforms 396 */ 397 void plat_arm_io_setup(void); 398 int plat_arm_get_alt_image_source( 399 unsigned int image_id, 400 uintptr_t *dev_handle, 401 uintptr_t *image_spec); 402 unsigned int plat_arm_calc_core_pos(u_register_t mpidr); 403 const mmap_region_t *plat_arm_get_mmap(void); 404 405 const arm_gpt_info_t *plat_arm_get_gpt_info(void); 406 void arm_gpt_setup(void); 407 408 /* Allow platform to override psci_pm_ops during runtime */ 409 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); 410 411 /* Execution state switch in ARM platforms */ 412 int arm_execution_state_switch(unsigned int smc_fid, 413 uint32_t pc_hi, 414 uint32_t pc_lo, 415 uint32_t cookie_hi, 416 uint32_t cookie_lo, 417 void *handle); 418 419 /* Optional functions for SP_MIN */ 420 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 421 u_register_t arg2, u_register_t arg3); 422 423 /* global variables */ 424 extern plat_psci_ops_t plat_arm_psci_pm_ops; 425 extern const mmap_region_t plat_arm_mmap[]; 426 extern const unsigned int arm_pm_idle_states[]; 427 428 /* secure watchdog */ 429 void plat_arm_secure_wdt_start(void); 430 void plat_arm_secure_wdt_stop(void); 431 void plat_arm_secure_wdt_refresh(void); 432 433 /* Get SOC-ID of ARM platform */ 434 uint32_t plat_arm_get_soc_id(void); 435 436 #endif /* PLAT_ARM_H */ 437