1 /*
2 * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /* ----------------------------------------------------------------------
20 * Project: CMSIS NN Library
21 * Title: arm_convolve_HWC_q7_basic.c
22 * Description: Q7 version of convolution
23 *
24 * $Date: 13. July 2018
25 * $Revision: V.1.0.0
26 *
27 * Target Processor: Cortex-M cores
28 *
29 * -------------------------------------------------------------------- */
30 #include "arm_math.h"
31 #include "arm_nnfunctions.h"
32
33 /**
34 * @ingroup groupNN
35 */
36
37 /**
38 * @addtogroup NNConv
39 * @{
40 */
41
42 /**
43 * @brief Basic Q7 convolution function (non-sqaure shape)
44 * @param[in] Im_in pointer to input tensor
45 * @param[in] dim_im_in_x input tensor dimention x
46 * @param[in] dim_im_in_y input tensor dimention y
47 * @param[in] ch_im_in number of input tensor channels
48 * @param[in] wt pointer to kernel weights
49 * @param[in] ch_im_out number of filters, i.e., output tensor channels
50 * @param[in] dim_kernel_x filter kernel size x
51 * @param[in] dim_kernel_y filter kernel size y
52 * @param[in] padding_x padding size x
53 * @param[in] padding_y padding size y
54 * @param[in] stride_x convolution stride x
55 * @param[in] stride_y convolution stride y
56 * @param[in] bias pointer to bias
57 * @param[in] bias_shift amount of left-shift for bias
58 * @param[in] out_shift amount of right-shift for output
59 * @param[in,out] Im_out pointer to output tensor
60 * @param[in] dim_im_out_x output tensor dimension x
61 * @param[in] dim_im_out_y output tensor dimension y
62 * @param[in,out] bufferA pointer to buffer space for input
63 * @param[in,out] bufferB pointer to buffer space for output
64 * @return The function returns <code>ARM_MATH_SUCCESS</code>
65 */
66
arm_convolve_HWC_q7_basic_nonsquare(const q7_t * Im_in,const uint16_t dim_im_in_x,const uint16_t dim_im_in_y,const uint16_t ch_im_in,const q7_t * wt,const uint16_t ch_im_out,const uint16_t dim_kernel_x,const uint16_t dim_kernel_y,const uint16_t padding_x,const uint16_t padding_y,const uint16_t stride_x,const uint16_t stride_y,const q7_t * bias,const uint16_t bias_shift,const uint16_t out_shift,q7_t * Im_out,const uint16_t dim_im_out_x,const uint16_t dim_im_out_y,q15_t * bufferA,q7_t * bufferB)67 arm_status arm_convolve_HWC_q7_basic_nonsquare(const q7_t * Im_in,
68 const uint16_t dim_im_in_x,
69 const uint16_t dim_im_in_y,
70 const uint16_t ch_im_in,
71 const q7_t * wt,
72 const uint16_t ch_im_out,
73 const uint16_t dim_kernel_x,
74 const uint16_t dim_kernel_y,
75 const uint16_t padding_x,
76 const uint16_t padding_y,
77 const uint16_t stride_x,
78 const uint16_t stride_y,
79 const q7_t * bias,
80 const uint16_t bias_shift,
81 const uint16_t out_shift,
82 q7_t * Im_out,
83 const uint16_t dim_im_out_x,
84 const uint16_t dim_im_out_y,
85 q15_t * bufferA,
86 q7_t * bufferB)
87 {
88
89 #if defined (ARM_MATH_DSP)
90 /* Run the following code for Cortex-M4 and Cortex-M7 */
91
92 int16_t i_out_y, i_out_x, i_ker_y, i_ker_x;
93
94 /*
95 * Here we use bufferA as q15_t internally as computation are done with q15_t level
96 * im2col are done to output in q15_t format from q7_t input
97 */
98 q15_t *pBuffer = bufferA;
99 q7_t *pOut = Im_out;
100
101 /* This part implements the im2col function */
102 for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++)
103 {
104 for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++)
105 {
106 for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; i_ker_y++)
107 {
108 for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; i_ker_x++)
109 {
110 if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x)
111 {
112 /* Filling 0 for out-of-bound paddings */
113 /* arm_fill_q15(0, pBuffer, ch_im_in); */
114 memset(pBuffer, 0, sizeof(q15_t)*ch_im_in);
115 } else
116 {
117 /* Copying the pixel data to column */
118 arm_q7_to_q15_no_shift((q7_t *)
119 Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in);
120 }
121 pBuffer += ch_im_in;
122 }
123 }
124
125 /* Computation is filed for every 2 columns */
126 if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_y * dim_kernel_x)
127 {
128 pOut =
129 arm_nn_mat_mult_kernel_q7_q15(wt, bufferA,
130 ch_im_out,
131 ch_im_in *
132 dim_kernel_y * dim_kernel_x, bias_shift, out_shift, bias, pOut);
133
134 /* counter reset */
135 pBuffer = bufferA;
136 }
137 }
138 }
139
140 /* left-over because odd number of output pixels */
141 if (pBuffer != bufferA)
142 {
143 const q7_t *pA = wt;
144 int i;
145
146 for (i = 0; i < ch_im_out; i++)
147 {
148 /* Load the accumulator with bias first */
149 q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
150
151 /* Point to the beging of the im2col buffer */
152 q15_t *pB = bufferA;
153
154 /* Each time it process 4 entries */
155 uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 2;
156
157 while (colCnt)
158 {
159 q31_t inA1, inA2;
160 q31_t inB1, inB2;
161
162 pA = (q7_t *) read_and_pad((void *)pA, &inA1, &inA2);
163
164 inB1 = *__SIMD32(pB)++;
165 sum = __SMLAD(inA1, inB1, sum);
166 inB2 = *__SIMD32(pB)++;
167 sum = __SMLAD(inA2, inB2, sum);
168
169 colCnt--;
170 }
171 colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x3;
172 while (colCnt)
173 {
174 q7_t inA1 = *pA++;
175 q15_t inB1 = *pB++;
176 sum += inA1 * inB1;
177 colCnt--;
178 }
179 *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8);
180 }
181 }
182 #else
183 /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
184
185 uint16_t i, j, k, l, m, n;
186 int conv_out;
187 signed char in_row, in_col;
188
189 for (i = 0; i < ch_im_out; i++)
190 {
191 for (j = 0; j < dim_im_out_y; j++)
192 {
193 for (k = 0; k < dim_im_out_x; k++)
194 {
195 conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
196 for (m = 0; m < dim_kernel_y; m++)
197 {
198 for (n = 0; n < dim_kernel_x; n++)
199 {
200 // if-for implementation
201 in_row = stride_y * j + m - padding_y;
202 in_col = stride_x * k + n - padding_x;
203 if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x)
204 {
205 for (l = 0; l < ch_im_in; l++)
206 {
207 conv_out +=
208 Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] *
209 wt[i * ch_im_in * dim_kernel_y * dim_kernel_x +
210 (m * dim_kernel_x + n) * ch_im_in + l];
211 }
212 }
213 }
214 }
215 Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8);
216 }
217 }
218 }
219
220 #endif /* ARM_MATH_DSP */
221
222 /* Return to application */
223 return ARM_MATH_SUCCESS;
224 }
225
226 /**
227 * @} end of NNConv group
228 */
229