1 /*
2 * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /* ----------------------------------------------------------------------
20 * Project: CMSIS NN Library
21 * Title: arm_convolve_HWC_q7_RGB.c
22 * Description: Q7 version of convolution for RGB image
23 *
24 * $Date: 17. January 2018
25 * $Revision: V.1.0.0
26 *
27 * Target Processor: Cortex-M cores
28 *
29 * -------------------------------------------------------------------- */
30 #include "arm_math.h"
31 #include "arm_nnfunctions.h"
32
33 /**
34 * @ingroup groupNN
35 */
36
37 /**
38 * @addtogroup NNConv
39 * @{
40 */
41
42 /**
43 * @brief Q7 convolution function for RGB image
44 * @param[in] Im_in pointer to input tensor
45 * @param[in] dim_im_in input tensor dimention
46 * @param[in] ch_im_in number of input tensor channels
47 * @param[in] wt pointer to kernel weights
48 * @param[in] ch_im_out number of filters, i.e., output tensor channels
49 * @param[in] dim_kernel filter kernel size
50 * @param[in] padding padding sizes
51 * @param[in] stride convolution stride
52 * @param[in] bias pointer to bias
53 * @param[in] bias_shift amount of left-shift for bias
54 * @param[in] out_shift amount of right-shift for output
55 * @param[in,out] Im_out pointer to output tensor
56 * @param[in] dim_im_out output tensor dimension
57 * @param[in,out] bufferA pointer to buffer space for input
58 * @param[in,out] bufferB pointer to buffer space for output
59 * @return The function returns either
60 * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
61 *
62 * @details
63 *
64 * <b>Buffer size:</b>
65 *
66 * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel
67 *
68 * bufferB size: 0
69 *
70 * <b>Input dimension constraints:</b>
71 *
72 * ch_im_in equals 3
73 *
74 * This kernel is written exclusively for convolution with ch_im_in
75 * equals 3. This applies on the first layer of CNNs which has input
76 * image with RGB format.
77 */
78
79 arm_status
arm_convolve_HWC_q7_RGB(const q7_t * Im_in,const uint16_t dim_im_in,const uint16_t ch_im_in,const q7_t * wt,const uint16_t ch_im_out,const uint16_t dim_kernel,const uint16_t padding,const uint16_t stride,const q7_t * bias,const uint16_t bias_shift,const uint16_t out_shift,q7_t * Im_out,const uint16_t dim_im_out,q15_t * bufferA,q7_t * bufferB)80 arm_convolve_HWC_q7_RGB(const q7_t * Im_in,
81 const uint16_t dim_im_in,
82 const uint16_t ch_im_in,
83 const q7_t * wt,
84 const uint16_t ch_im_out,
85 const uint16_t dim_kernel,
86 const uint16_t padding,
87 const uint16_t stride,
88 const q7_t * bias,
89 const uint16_t bias_shift,
90 const uint16_t out_shift,
91 q7_t * Im_out, const uint16_t dim_im_out, q15_t * bufferA, q7_t * bufferB)
92 {
93
94 #if defined (ARM_MATH_DSP)
95 /* Run the following code for Cortex-M4 and Cortex-M7 */
96 int16_t i_out_y, i_out_x, i_ker_y, i_ker_x;
97
98 /*
99 * Here we use bufferA as q15_t internally as computation are done with q15_t level
100 * im2col are done to output in q15_t format from q7_t input
101 */
102 q15_t *pBuffer = bufferA;
103 q7_t *pOut = Im_out;
104
105 // check if number of input channels is 3
106 if (ch_im_in != 3)
107 {
108 return ARM_MATH_SIZE_MISMATCH;
109 }
110 // This part implements the im2col function
111 for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++)
112 {
113 for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++)
114 {
115 for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++)
116 {
117 for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++)
118 {
119 if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in)
120 {
121 /* Equivalent to arm_fill_q15(0, pBuffer, ch_im_in) with assumption: ch_im_in = 3 */
122 *__SIMD32(pBuffer) = 0x0;
123 *(pBuffer + 2) = 0;
124 pBuffer += 3;
125 } else
126 {
127 /*
128 * Equivalent to:
129 * arm_q7_to_q15_no_shift( (q7_t*)Im_in+(i_ker_y*dim_im_in+i_ker_x)*3, pBuffer, 3);
130 */
131
132 const q7_t *pPixel = Im_in + (i_ker_y * dim_im_in + i_ker_x) * 3;
133 q31_t buf = *__SIMD32(pPixel);
134
135 union arm_nnword top;
136 union arm_nnword bottom;
137
138 top.word = __SXTB16(buf);
139 bottom.word = __SXTB16(__ROR(buf, 8));
140
141 #ifndef ARM_MATH_BIG_ENDIAN
142 /*
143 * little-endian, | omit | 3rd | 2nd | 1st |
144 * MSB LSB
145 * top | 3rd | 1st |; bottom | omit | 2nd |
146 *
147 * version 1, need to swap 2nd and 3rd weight
148 * *__SIMD32(pBuffer) = top.word;
149 * *(pBuffer+2) = bottom.half_words[0];
150 *
151 * version 2, no weight shuffling required
152 */
153 *pBuffer++ = top.half_words[0];
154 *__SIMD32(pBuffer) = __PKHBT(bottom.word, top.word, 0);
155 #else
156 /*
157 * big-endian, | 1st | 2nd | 3rd | omit |
158 * MSB LSB
159 * top | 2nd | omit |; bottom | 1st | 3rd |
160 *
161 * version 1, need to swap 2nd and 3rd weight
162 * *__SIMD32(pBuffer) = bottom.word;
163 * *(pBuffer+2) = top.half_words[1];
164 *
165 * version 2, no weight shuffling required
166 */
167 *pBuffer++ = bottom.half_words[0];
168 *__SIMD32(pBuffer) = __PKHTB(top.word, bottom.word, 0);
169 #endif
170 pBuffer += 2;
171 }
172 }
173 }
174
175 if (pBuffer == bufferA + 2 * 3 * dim_kernel * dim_kernel)
176 {
177 pOut =
178 arm_nn_mat_mult_kernel_q7_q15(wt, bufferA,
179 ch_im_out,
180 3 * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut);
181
182 /* counter reset */
183 pBuffer = bufferA;
184 }
185 }
186 }
187
188 /* left-over because odd number of output pixels */
189 if (pBuffer != bufferA)
190 {
191 const q7_t *pA = wt;
192 int i;
193
194 for (i = 0; i < ch_im_out; i++)
195 {
196 q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
197 q15_t *pB = bufferA;
198 /* basically each time it process 4 entries */
199 uint16_t colCnt = 3 * dim_kernel * dim_kernel >> 2;
200
201 while (colCnt)
202 {
203
204 q31_t inA1, inA2;
205 q31_t inB1, inB2;
206
207 pA = (q7_t *) read_and_pad((void *)pA, &inA1, &inA2);
208
209 inB1 = *__SIMD32(pB)++;
210 sum = __SMLAD(inA1, inB1, sum);
211 inB2 = *__SIMD32(pB)++;
212 sum = __SMLAD(inA2, inB2, sum);
213
214 colCnt--;
215 }
216 colCnt = 3 * dim_kernel * dim_kernel & 0x3;
217 while (colCnt)
218 {
219 q7_t inA1 = *pA++;
220 q15_t inB1 = *pB++;
221 sum += inA1 * inB1;
222 colCnt--;
223 }
224 *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8);
225 }
226 }
227 #else
228 /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
229
230 uint16_t i, j, k, l, m, n;
231 int conv_out;
232 signed char in_row, in_col;
233
234 // check if number of input channels is 3
235 if (ch_im_in != 3)
236 {
237 return ARM_MATH_SIZE_MISMATCH;
238 }
239
240 for (i = 0; i < ch_im_out; i++)
241 {
242 for (j = 0; j < dim_im_out; j++)
243 {
244 for (k = 0; k < dim_im_out; k++)
245 {
246 conv_out = (bias[i] << bias_shift) + NN_ROUND(out_shift);
247 for (m = 0; m < dim_kernel; m++)
248 {
249 for (n = 0; n < dim_kernel; n++)
250 {
251 /* if-for implementation */
252 in_row = stride * j + m - padding;
253 in_col = stride * k + n - padding;
254 if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in)
255 {
256 for (l = 0; l < ch_im_in; l++)
257 {
258 conv_out +=
259 Im_in[(in_row * dim_im_in + in_col) * ch_im_in +
260 l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel +
261 n) * ch_im_in + l];
262 }
263 }
264 }
265 }
266 Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8);
267 }
268 }
269 }
270
271 #endif /* ARM_MATH_DSP */
272
273 /* Return to application */
274 return (ARM_MATH_SUCCESS);
275 }
276
277 /**
278 * @} end of NNConv group
279 */
280