1 /*
2 * Copyright (c) 2023, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /* TF-A system header */
8 #include <common/debug.h>
9 #include <drivers/delay_timer.h>
10 #include <lib/mmio.h>
11 #include <lib/spinlock.h>
12
13 /* Vendor header */
14 #include "apusys.h"
15 #include "apusys_rv.h"
16 #include "apusys_rv_mbox_mpu.h"
17 #include "emi_mpu.h"
18
19 static spinlock_t apusys_rv_lock;
20
apusys_rv_mbox_mpu_init(void)21 void apusys_rv_mbox_mpu_init(void)
22 {
23 int i;
24
25 for (i = 0; i < APU_MBOX_NUM; i++) {
26 mmio_write_32(APU_MBOX_FUNC_CFG(i),
27 (MBOX_CTRL_LOCK |
28 (mbox_mpu_setting_tab[i].no_mpu << MBOX_NO_MPU_SHIFT)));
29 mmio_write_32(APU_MBOX_DOMAIN_CFG(i),
30 (MBOX_CTRL_LOCK |
31 (mbox_mpu_setting_tab[i].rx_ns << MBOX_RX_NS_SHIFT) |
32 (mbox_mpu_setting_tab[i].rx_domain << MBOX_RX_DOMAIN_SHIFT) |
33 (mbox_mpu_setting_tab[i].tx_ns << MBOX_TX_NS_SHIFT) |
34 (mbox_mpu_setting_tab[i].tx_domain << MBOX_TX_DOMAIN_SHIFT)));
35 }
36 }
37
apusys_kernel_apusys_rv_setup_reviser(void)38 int apusys_kernel_apusys_rv_setup_reviser(void)
39 {
40 spin_lock(&apusys_rv_lock);
41
42 mmio_write_32(USERFW_CTXT, CFG_4GB_SEL_EN | CFG_4GB_SEL);
43 mmio_write_32(SECUREFW_CTXT, CFG_4GB_SEL_EN | CFG_4GB_SEL);
44
45 mmio_write_32(UP_IOMMU_CTRL, MMU_CTRL_LOCK | MMU_CTRL | MMU_EN);
46
47 mmio_write_32(UP_NORMAL_DOMAIN_NS,
48 (UP_NORMAL_DOMAIN << UP_DOMAIN_SHIFT) | (UP_NORMAL_NS << UP_NS_SHIFT));
49 mmio_write_32(UP_PRI_DOMAIN_NS,
50 (UP_PRI_DOMAIN << UP_DOMAIN_SHIFT) | (UP_PRI_NS << UP_NS_SHIFT));
51
52 mmio_write_32(UP_CORE0_VABASE0,
53 VLD | PARTIAL_ENABLE | (THREAD_NUM_PRI << THREAD_NUM_SHIFT));
54 mmio_write_32(UP_CORE0_MVABASE0, VASIZE_1MB | (APU_SEC_FW_IOVA >> MVA_34BIT_SHIFT));
55
56 mmio_write_32(UP_CORE0_VABASE1,
57 VLD | PARTIAL_ENABLE | (THREAD_NUM_NORMAL << THREAD_NUM_SHIFT));
58 mmio_write_32(UP_CORE0_MVABASE1, VASIZE_1MB | (APU_SEC_FW_IOVA >> MVA_34BIT_SHIFT));
59
60 spin_unlock(&apusys_rv_lock);
61
62 return 0;
63 }
64
apusys_kernel_apusys_rv_reset_mp(void)65 int apusys_kernel_apusys_rv_reset_mp(void)
66 {
67 spin_lock(&apusys_rv_lock);
68
69 mmio_write_32(MD32_SYS_CTRL, MD32_SYS_CTRL_RST);
70
71 dsb();
72 udelay(RESET_DEALY_US);
73
74 mmio_write_32(MD32_SYS_CTRL, MD32_G2B_CG_EN | MD32_DBG_EN | MD32_DM_AWUSER_IOMMU_EN |
75 MD32_DM_ARUSER_IOMMU_EN | MD32_PM_AWUSER_IOMMU_EN | MD32_PM_ARUSER_IOMMU_EN |
76 MD32_SOFT_RSTN);
77
78 mmio_write_32(MD32_CLK_CTRL, MD32_CLK_EN);
79 mmio_write_32(UP_WAKE_HOST_MASK0, WDT_IRQ_EN);
80 mmio_write_32(UP_WAKE_HOST_MASK1, MBOX0_IRQ_EN | MBOX1_IRQ_EN | MBOX2_IRQ_EN);
81
82 spin_unlock(&apusys_rv_lock);
83
84 return 0;
85 }
86
apusys_kernel_apusys_rv_setup_boot(void)87 int apusys_kernel_apusys_rv_setup_boot(void)
88 {
89 spin_lock(&apusys_rv_lock);
90
91 mmio_write_32(MD32_BOOT_CTRL, APU_SEC_FW_IOVA);
92
93 mmio_write_32(MD32_PRE_DEFINE, (PREDEFINE_CACHE_TCM << PREDEF_1G_OFS) |
94 (PREDEFINE_CACHE << PREDEF_2G_OFS) | (PREDEFINE_CACHE << PREDEF_3G_OFS) |
95 (PREDEFINE_CACHE << PREDEF_4G_OFS));
96
97 spin_unlock(&apusys_rv_lock);
98 return 0;
99 }
100
apusys_kernel_apusys_rv_start_mp(void)101 int apusys_kernel_apusys_rv_start_mp(void)
102 {
103 spin_lock(&apusys_rv_lock);
104 mmio_write_32(MD32_RUNSTALL, MD32_RUN);
105 spin_unlock(&apusys_rv_lock);
106
107 return 0;
108 }
109
apusys_kernel_apusys_rv_stop_mp(void)110 int apusys_kernel_apusys_rv_stop_mp(void)
111 {
112 spin_lock(&apusys_rv_lock);
113 mmio_write_32(MD32_RUNSTALL, MD32_STALL);
114 spin_unlock(&apusys_rv_lock);
115
116 return 0;
117 }
118
apusys_kernel_apusys_rv_setup_sec_mem(void)119 int apusys_kernel_apusys_rv_setup_sec_mem(void)
120 {
121 int ret;
122
123 spin_lock(&apusys_rv_lock);
124
125 ret = set_apu_emi_mpu_region();
126 if (ret != 0) {
127 ERROR(MODULE_TAG "%s: set emimpu protection failed\n", __func__);
128 }
129
130 spin_unlock(&apusys_rv_lock);
131 return ret;
132 }
133
apusys_kernel_apusys_rv_disable_wdt_isr(void)134 int apusys_kernel_apusys_rv_disable_wdt_isr(void)
135 {
136 spin_lock(&apusys_rv_lock);
137 mmio_clrbits_32(WDT_CTRL0, WDT_EN);
138 spin_unlock(&apusys_rv_lock);
139
140 return 0;
141 }
142
apusys_kernel_apusys_rv_clear_wdt_isr(void)143 int apusys_kernel_apusys_rv_clear_wdt_isr(void)
144 {
145 spin_lock(&apusys_rv_lock);
146 mmio_clrbits_32(UP_INT_EN2, DBG_APB_EN);
147 mmio_write_32(WDT_INT, WDT_INT_W1C);
148 spin_unlock(&apusys_rv_lock);
149
150 return 0;
151 }
152
apusys_kernel_apusys_rv_cg_gating(void)153 int apusys_kernel_apusys_rv_cg_gating(void)
154 {
155 spin_lock(&apusys_rv_lock);
156 mmio_write_32(MD32_CLK_CTRL, MD32_CLK_DIS);
157 spin_unlock(&apusys_rv_lock);
158
159 return 0;
160 }
161
apusys_kernel_apusys_rv_cg_ungating(void)162 int apusys_kernel_apusys_rv_cg_ungating(void)
163 {
164 spin_lock(&apusys_rv_lock);
165 mmio_write_32(MD32_CLK_CTRL, MD32_CLK_EN);
166 spin_unlock(&apusys_rv_lock);
167
168 return 0;
169 }
170