1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_ROCKCHIP_RK3399_CLOCK_H__ 4 #define __SOC_ROCKCHIP_RK3399_CLOCK_H__ 5 6 #include <soc/addressmap.h> 7 #include <types.h> 8 9 struct rk3399_pmucru_reg { 10 u32 ppll_con[6]; 11 u32 reserved[0x1a]; 12 u32 pmucru_clksel[6]; 13 u32 pmucru_clkfrac_con[2]; 14 u32 reserved2[0x18]; 15 u32 pmucru_clkgate_con[3]; 16 u32 reserved3; 17 u32 pmucru_softrst_con[2]; 18 u32 reserved4[2]; 19 u32 pmucru_rstnhold_con[2]; 20 u32 reserved5[2]; 21 u32 pmucru_gatedis_con[2]; 22 }; 23 check_member(rk3399_pmucru_reg, pmucru_gatedis_con[1], 0x134); 24 25 struct rk3399_cru_reg { 26 u32 apll_l_con[6]; 27 u32 reserved[2]; 28 u32 apll_b_con[6]; 29 u32 reserved1[2]; 30 u32 dpll_con[6]; 31 u32 reserved2[2]; 32 u32 cpll_con[6]; 33 u32 reserved3[2]; 34 u32 gpll_con[6]; 35 u32 reserved4[2]; 36 u32 npll_con[6]; 37 u32 reserved5[2]; 38 u32 vpll_con[6]; 39 u32 reserved6[0x0a]; 40 u32 clksel_con[108]; 41 u32 reserved7[0x14]; 42 u32 clkgate_con[35]; 43 u32 reserved8[0x1d]; 44 u32 softrst_con[21]; 45 u32 reserved9[0x2b]; 46 u32 glb_srst_fst_value; 47 u32 glb_srst_snd_value; 48 u32 glb_cnt_th; 49 u32 misc_con; 50 u32 glb_rst_con; 51 u32 glb_rst_st; 52 u32 reserved10[0x1a]; 53 u32 sdmmc_con[2]; 54 u32 sdio0_con[2]; 55 u32 sdio1_con[2]; 56 }; 57 check_member(rk3399_cru_reg, sdio1_con[1], 0x594); 58 59 static struct rk3399_pmucru_reg * const pmucru_ptr = (void *)PMUCRU_BASE; 60 static struct rk3399_cru_reg * const cru_ptr = (void *)CRU_BASE; 61 62 #define OSC_HZ (24*MHz) 63 #define GPLL_HZ (594*MHz) 64 #define CPLL_HZ (800*MHz) 65 #define PPLL_HZ (676*MHz) 66 67 #define PMU_PCLK_HZ 96571428 68 69 #define ACLKM_CORE_HZ (300*MHz) 70 #define ATCLK_CORE_HZ (300*MHz) 71 #define PCLK_DBG_HZ (100*MHz) 72 73 #define PERIHP_ACLK_HZ (148500*KHz) 74 #define PERIHP_HCLK_HZ (148500*KHz) 75 #define PERIHP_PCLK_HZ (37125*KHz) 76 77 #define PERILP0_ACLK_HZ (99000*KHz) 78 #define PERILP0_HCLK_HZ (99000*KHz) 79 #define PERILP0_PCLK_HZ (49500*KHz) 80 81 #define PERILP1_HCLK_HZ (99000*KHz) 82 #define PERILP1_PCLK_HZ (99000*KHz) 83 84 #define PWM_CLOCK_HZ PMU_PCLK_HZ 85 86 enum apll_frequencies { 87 APLL_1512_MHZ, 88 APLL_600_MHZ, 89 }; 90 91 enum cpu_cluster { 92 CPU_CLUSTER_LITTLE, 93 CPU_CLUSTER_BIG, 94 }; 95 96 void rkclk_init(void); 97 int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz); 98 void rkclk_configure_cpu(enum apll_frequencies freq, enum cpu_cluster cluster); 99 void rkclk_configure_ddr(unsigned int hz); 100 void rkclk_configure_emmc(void); 101 void rkclk_configure_i2s(unsigned int hz); 102 void rkclk_configure_saradc(unsigned int hz); 103 void rkclk_configure_spi(unsigned int bus, unsigned int hz); 104 void rkclk_configure_tsadc(unsigned int hz); 105 void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz); 106 void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy); 107 int rkclk_was_watchdog_reset(void); 108 uint32_t rkclk_i2c_clock_for_bus(unsigned int bus); 109 void rkclk_configure_edp(unsigned int hz); 110 void rkclk_configure_mipi(void); 111 112 #endif /* __SOC_ROCKCHIP_RK3399_CLOCK_H__ */ 113