1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef AMD_COMMON_ACP_H 4 #define AMD_COMMON_ACP_H 5 6 #include <types.h> 7 8 struct acp_config { 9 enum { 10 #if CONFIG(SOC_AMD_COMMON_BLOCK_ACP_GEN2) 11 ACP_PINS_HDA_3SDI = 1, /* HDA 3xSDI */ 12 ACP_PINS_HDA_1SDI_1SW = 2, /* HDA 1xSDI, SW w/Data0 */ 13 ACP_PINS_4SW_1SW = 3, /* SW w/Data0-3, SW w/Data0 */ 14 ACP_PINS_HDA_3SDI_PDM2 = 4, /* HDA 3xSDI, PDM 2CH */ 15 ACP_PINS_HDA_1SDI_PDM6 = 5, /* HDA 1xSDI, PDM 6CH */ 16 ACP_PINS_HDA_1SDI_1SW_PDM2 = 6, /* HDA 1xSDI, SW w/Data0, PDM 2CH */ 17 ACP_PINS_4SW_PDM6 = 7, /* SW w/Data0-3, PDM 6CH */ 18 ACP_PINS_4SW_1SW_PDM2 = 8, /* SW w/Data0-3, SW w/Data0, PDM 2CH */ 19 ACP_PINS_I2S = 9, /* 3xI2S, Refclk, Intr */ 20 ACP_PINS_HDA_3SDI_PDM6_I2S = 10,/* HDA 3xSDI, PDM 6CH, I2S */ 21 ACP_PINS_HDA_3SDI_PDM8 = 11, /* HDA 3xSDI, PDM 8CH */ 22 ACP_PINS_HDA_1SDI_1SW_PDM6_I2S = 12,/* HDA 1xSDI, SW w/Data0, PDM 6CH, I2S */ 23 ACP_PINS_4SW_1SW_PDM6_I2S = 13, /* SW w/Data0-3, SW w/Data0, PDM 6CH, I2S */ 24 ACP_PINS_4SW_1SW_PDM8 = 14, /* SW w/Data0-3, SW w/Data0, PDM 8CH */ 25 #else 26 I2S_PINS_MAX_HDA = 0, /* HDA w/reset 3xSDI, SW w/Data0 */ 27 I2S_PINS_MAX_MHDA = 1, /* HDA no reset 3xSDI, SW w/Data0-1 */ 28 I2S_PINS_MIN_HDA = 2, /* HDA w/reset 1xSDI, SW w/Data0-2 */ 29 I2S_PINS_MIN_MHDA = 3, /* HDA no reset 1xSDI, SW w/Data0-3 */ 30 I2S_PINS_I2S_TDM = 4, 31 I2S_PINS_UNCONF = 7, /* All pads will be input mode */ 32 #endif 33 } acp_pin_cfg; 34 35 /* Enable ACP I2S wake feature (0 = disable, 1 = enable) */ 36 u8 acp_i2s_wake_enable; 37 /* Enable ACP PME (0 = disable, 1 = enable) */ 38 u8 acp_pme_enable; 39 40 /* 41 * DMIC present (optional) to support ACP DMIC hardware runtime detection on the 42 * platform. If dmic_present is set to true, it will populate the _WOV ACPI method. 43 */ 44 bool dmic_present; 45 }; 46 47 #endif /* AMD_COMMON_ACP_H */ 48