1 /*
2  * Copyright (c) 2021-2022 Arm Limited.
3  *
4  * SPDX-License-Identifier: MIT
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to
8  * deal in the Software without restriction, including without limitation the
9  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10  * sell copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in all
14  * copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22  * SOFTWARE.
23  */
24 
25 #if defined(__aarch64__)
26 
27 #include "pooling.hpp"
28 #include <cstdint>
29 #include <cstddef>
30 #include <cstring>
31 #include <cmath>
32 
33 
34 namespace arm_conv {
35 namespace pooling {
36 
37 namespace {
38   struct RescaleParams
39   {
40     int32_t multiplier, shift;
41   };
42 
43   constexpr RescaleParams rescale_params[8] = {
44     {0x40000000, -0},  // 1/2
45     {0x55555556, -1},  // 1/3
46     {0x40000000, -1},  // 1/4
47     {0x66666666, -2},  // 1/5
48     {0x55555556, -2},  // 1/6
49     {0x49249249, -2},  // 1/7
50     {0x40000000, -2},  // 1/8
51     {0x71c71c72, -3},  // 1/9
52   };
53 }
54 
a64_u8q_nhwc_avg_generic_depthfirst_impl(const uint64_t window_cells,const uint64_t n_valid_cells,uint64_t n_channels,const uint8_t * const * const inptrs,uint8_t * outptr,const Requantize32 & qp)55 void a64_u8q_nhwc_avg_generic_depthfirst_impl(
56   const uint64_t window_cells,
57   const uint64_t n_valid_cells,
58   uint64_t n_channels,
59   const uint8_t *const *const inptrs,
60   uint8_t *outptr,
61   const Requantize32 &qp
62 )
63 {
64   if (n_valid_cells == 1 && window_cells == 1)
65   {
66     // In this case, simply copy from the input to the output
67     std::memcpy(outptr, *inptrs, n_channels);
68     return;
69   }
70 
71   // Compute (or look up) the rescale values
72   int32_t shift_value = 0, rescale_value = 0;
73   if (2 <= window_cells && window_cells <= 9)
74   {
75     auto &params = rescale_params[window_cells - 2];
76     rescale_value = params.multiplier;
77     shift_value = params.shift;
78   }
79   else
80   {
81     auto f_rescale_value = 1.0f / static_cast<float>(window_cells);
82 
83     shift_value = 0;
84     while (f_rescale_value < 0.5f)
85     {
86       shift_value--;
87       f_rescale_value *= 2.0f;
88     }
89 
90     int64_t long_rescale_value = round(f_rescale_value * static_cast<float>(1ll << 31));
91     if (long_rescale_value == (1ll << 31))
92     {
93       shift_value++;
94       long_rescale_value >>= 1;
95     }
96     rescale_value = static_cast<int32_t>(long_rescale_value);
97   }
98 
99 
100   // Initialise the accumulators such that the offsets are subtracted for all
101   // valid inputs.
102   const int32_t accumulator_init = -qp.input_offset * n_valid_cells;
103 
104   // Combine together the rescale value for the requantization and the scaling
105   // factor for the average pool.
106   const int32_t shift = qp.per_layer_left_shift - qp.per_layer_right_shift + shift_value;
107   const int32_t left_shift = shift > 0 ? shift : 0;
108   const int32_t right_shift = shift <= 0 ? shift : 0;
109 
110   int32_t combined_rescale_value = 0;
111   __asm__ __volatile__ (
112       "mov v16.s[0], %w[per_layer_mul]\n"
113       "mov v17.s[0], %w[rescale_value]\n"
114       "sqrdmulh s18, s16, s17\n"
115       "mov %w[combined_rescale_value], v18.s[0]\n"
116     : [combined_rescale_value] "=r" (combined_rescale_value)
117     : [per_layer_mul] "r" (qp.per_layer_mul), [rescale_value] "r" (rescale_value)
118     : "v16", "v17", "v18"
119   );
120 
121   __asm__ __volatile__(
122     "cmp %x[n_channels], #0x40\n"
123     "mov x26, #0x0\n"
124     "mov x25, #0x10\n"  // cntb _, ALL, #1
125     "mov x24, #0x20\n"  // cntb _, ALL, #2
126     "mov x23, #0x30\n"  // cntb _, ALL, #3
127     "blt 7f\n"
128     "1:"  // 4-vectors of channels
129     "ld1r { v15.4s }, [%x[accumulator_init]]\n"
130     "lsr x22, %x[n_valid_cells], #0x1\n"
131     "mov v14.16b, v15.16b\n"
132     "mov v13.16b, v15.16b\n"
133     "mov v12.16b, v15.16b\n"
134     "mov v11.16b, v15.16b\n"
135     "mov x19, %x[inptrs]\n"
136     "mov v10.16b, v15.16b\n"
137     "mov v9.16b, v15.16b\n"
138     "mov v8.16b, v15.16b\n"
139     "mov v7.16b, v15.16b\n"
140     "mov v6.16b, v15.16b\n"
141     "mov v5.16b, v15.16b\n"
142     "mov v4.16b, v15.16b\n"
143     "mov v3.16b, v15.16b\n"
144     "mov v2.16b, v15.16b\n"
145     "mov v1.16b, v15.16b\n"
146     "mov v0.16b, v15.16b\n"
147     "cbz x22, 4f\n"
148     "ldp x21, x20, [x19, #0x0]\n"
149     "subs x22, x22, #0x1\n"
150     "add x19, x19, #0x10\n"
151     "ldr q31, [x21, x26]\n"
152     "ldr q30, [x20, x26]\n"
153     "ldr q29, [x21, x25]\n"
154     "ldr q28, [x20, x25]\n"
155     "ldr q27, [x21, x24]\n"
156     "ldr q26, [x20, x24]\n"
157     "ldr q25, [x21, x23]\n"
158     "ldr q24, [x20, x23]\n"
159     "beq 3f\n"
160     "2:"  // 4-vectors of channels: 2 inputs loop
161     "uaddl v23.8h, v31.8b, v30.8b\n"
162     "uaddl2 v22.8h, v31.16b, v30.16b\n"
163     "ldp x21, x20, [x19, #0x0]\n"
164     "subs x22, x22, #0x1\n"
165     "uaddl v21.8h, v29.8b, v28.8b\n"
166     "uaddl2 v20.8h, v29.16b, v28.16b\n"
167     "add x19, x19, #0x10\n"
168     "ldr q31, [x21, x26]\n"
169     "uaddl v19.8h, v27.8b, v26.8b\n"
170     "uaddl2 v18.8h, v27.16b, v26.16b\n"
171     "ldr q30, [x20, x26]\n"
172     "ldr q29, [x21, x25]\n"
173     "uaddl v17.8h, v25.8b, v24.8b\n"
174     "uaddl2 v16.8h, v25.16b, v24.16b\n"
175     "ldr q28, [x20, x25]\n"
176     "ldr q27, [x21, x24]\n"
177     "uaddw v15.4s, v15.4s, v23.4h\n"
178     "uaddw2 v14.4s, v14.4s, v23.8h\n"
179     "ldr q26, [x20, x24]\n"
180     "ldr q25, [x21, x23]\n"
181     "uaddw v13.4s, v13.4s, v22.4h\n"
182     "uaddw2 v12.4s, v12.4s, v22.8h\n"
183     "ldr q24, [x20, x23]\n"
184     "uaddw v11.4s, v11.4s, v21.4h\n"
185     "uaddw2 v10.4s, v10.4s, v21.8h\n"
186     "uaddw v9.4s, v9.4s, v20.4h\n"
187     "uaddw2 v8.4s, v8.4s, v20.8h\n"
188     "uaddw v7.4s, v7.4s, v19.4h\n"
189     "uaddw2 v6.4s, v6.4s, v19.8h\n"
190     "uaddw v5.4s, v5.4s, v18.4h\n"
191     "uaddw2 v4.4s, v4.4s, v18.8h\n"
192     "uaddw v3.4s, v3.4s, v17.4h\n"
193     "uaddw2 v2.4s, v2.4s, v17.8h\n"
194     "uaddw v1.4s, v1.4s, v16.4h\n"
195     "uaddw2 v0.4s, v0.4s, v16.8h\n"
196     "bgt 2b\n"
197     "3:"  // 4-vectors of channels: 2 inputs tail
198     "uaddl v23.8h, v31.8b, v30.8b\n"
199     "uaddl2 v22.8h, v31.16b, v30.16b\n"
200     "uaddl v21.8h, v29.8b, v28.8b\n"
201     "uaddl2 v20.8h, v29.16b, v28.16b\n"
202     "uaddl v19.8h, v27.8b, v26.8b\n"
203     "uaddl2 v18.8h, v27.16b, v26.16b\n"
204     "uaddl v17.8h, v25.8b, v24.8b\n"
205     "uaddl2 v16.8h, v25.16b, v24.16b\n"
206     "uaddw v15.4s, v15.4s, v23.4h\n"
207     "uaddw2 v14.4s, v14.4s, v23.8h\n"
208     "uaddw v13.4s, v13.4s, v22.4h\n"
209     "uaddw2 v12.4s, v12.4s, v22.8h\n"
210     "uaddw v11.4s, v11.4s, v21.4h\n"
211     "uaddw2 v10.4s, v10.4s, v21.8h\n"
212     "uaddw v9.4s, v9.4s, v20.4h\n"
213     "uaddw2 v8.4s, v8.4s, v20.8h\n"
214     "uaddw v7.4s, v7.4s, v19.4h\n"
215     "uaddw2 v6.4s, v6.4s, v19.8h\n"
216     "uaddw v5.4s, v5.4s, v18.4h\n"
217     "uaddw2 v4.4s, v4.4s, v18.8h\n"
218     "uaddw v3.4s, v3.4s, v17.4h\n"
219     "uaddw2 v2.4s, v2.4s, v17.8h\n"
220     "uaddw v1.4s, v1.4s, v16.4h\n"
221     "uaddw2 v0.4s, v0.4s, v16.8h\n"
222     "4:"  // 4-vectors of channels: After loop
223     "ands x20, %x[n_valid_cells], #0x1\n"
224     "beq 6f\n"
225     "5:"  // 4-vectors of channels: Single input loop
226     "ldr x21, [x19], #0x8\n"
227     "ldr q31, [x21, x26]\n"
228     "uxtl v23.8h, v31.8b\n"
229     "uxtl2 v22.8h, v31.16b\n"
230     "ldr q29, [x21, x25]\n"
231     "ldr q27, [x21, x24]\n"
232     "uxtl v21.8h, v29.8b\n"
233     "uxtl2 v20.8h, v29.16b\n"
234     "ldr q25, [x21, x23]\n"
235     "uxtl v19.8h, v27.8b\n"
236     "uxtl2 v18.8h, v27.16b\n"
237     "subs x20, x20, #0x1\n"
238     "uxtl v17.8h, v25.8b\n"
239     "uxtl2 v16.8h, v25.16b\n"
240     "uaddw v15.4s, v15.4s, v23.4h\n"
241     "uaddw2 v14.4s, v14.4s, v23.8h\n"
242     "uaddw v13.4s, v13.4s, v22.4h\n"
243     "uaddw2 v12.4s, v12.4s, v22.8h\n"
244     "uaddw v11.4s, v11.4s, v21.4h\n"
245     "uaddw2 v10.4s, v10.4s, v21.8h\n"
246     "uaddw v9.4s, v9.4s, v20.4h\n"
247     "uaddw2 v8.4s, v8.4s, v20.8h\n"
248     "uaddw v7.4s, v7.4s, v19.4h\n"
249     "uaddw2 v6.4s, v6.4s, v19.8h\n"
250     "uaddw v5.4s, v5.4s, v18.4h\n"
251     "uaddw2 v4.4s, v4.4s, v18.8h\n"
252     "uaddw v3.4s, v3.4s, v17.4h\n"
253     "uaddw2 v2.4s, v2.4s, v17.8h\n"
254     "uaddw v1.4s, v1.4s, v16.4h\n"
255     "uaddw2 v0.4s, v0.4s, v16.8h\n"
256     "bgt 5b\n"
257     "6:"  // 4-vectors of channels: Single input loop: End
258     "ld1r { v19.4s }, [%x[left_shift]]\n"
259     "ld1r { v18.4s }, [%x[combined_rescale_value]]\n"
260     "srshl v15.4s, v15.4s, v19.4s\n"
261     "srshl v14.4s, v14.4s, v19.4s\n"
262     "srshl v13.4s, v13.4s, v19.4s\n"
263     "srshl v12.4s, v12.4s, v19.4s\n"
264     "ld1r { v17.4s }, [%x[right_shift]]\n"
265     "add x19, %x[quant_params], %[offsetof_qp_output_offset]\n"
266     "srshl v11.4s, v11.4s, v19.4s\n"
267     "srshl v10.4s, v10.4s, v19.4s\n"
268     "ld1r { v16.4s }, [x19]\n"
269     "sub %x[n_channels], %x[n_channels], #0x40\n"
270     "srshl v9.4s, v9.4s, v19.4s\n"
271     "srshl v8.4s, v8.4s, v19.4s\n"
272     "cmp %x[n_channels], #0x40\n"
273     "srshl v7.4s, v7.4s, v19.4s\n"
274     "srshl v6.4s, v6.4s, v19.4s\n"
275     "srshl v5.4s, v5.4s, v19.4s\n"
276     "srshl v4.4s, v4.4s, v19.4s\n"
277     "srshl v3.4s, v3.4s, v19.4s\n"
278     "srshl v2.4s, v2.4s, v19.4s\n"
279     "srshl v1.4s, v1.4s, v19.4s\n"
280     "srshl v0.4s, v0.4s, v19.4s\n"
281     "sqrdmulh v15.4s, v15.4s, v18.4s\n"
282     "sqrdmulh v14.4s, v14.4s, v18.4s\n"
283     "sqrdmulh v13.4s, v13.4s, v18.4s\n"
284     "sqrdmulh v12.4s, v12.4s, v18.4s\n"
285     "sqrdmulh v11.4s, v11.4s, v18.4s\n"
286     "sqrdmulh v10.4s, v10.4s, v18.4s\n"
287     "sqrdmulh v9.4s, v9.4s, v18.4s\n"
288     "sqrdmulh v8.4s, v8.4s, v18.4s\n"
289     "sqrdmulh v7.4s, v7.4s, v18.4s\n"
290     "sqrdmulh v6.4s, v6.4s, v18.4s\n"
291     "sqrdmulh v5.4s, v5.4s, v18.4s\n"
292     "sqrdmulh v4.4s, v4.4s, v18.4s\n"
293     "sqrdmulh v3.4s, v3.4s, v18.4s\n"
294     "sqrdmulh v2.4s, v2.4s, v18.4s\n"
295     "sqrdmulh v1.4s, v1.4s, v18.4s\n"
296     "sqrdmulh v0.4s, v0.4s, v18.4s\n"
297     "srshl v15.4s, v15.4s, v17.4s\n"
298     "srshl v14.4s, v14.4s, v17.4s\n"
299     "srshl v13.4s, v13.4s, v17.4s\n"
300     "srshl v12.4s, v12.4s, v17.4s\n"
301     "srshl v11.4s, v11.4s, v17.4s\n"
302     "srshl v10.4s, v10.4s, v17.4s\n"
303     "srshl v9.4s, v9.4s, v17.4s\n"
304     "srshl v8.4s, v8.4s, v17.4s\n"
305     "srshl v7.4s, v7.4s, v17.4s\n"
306     "srshl v6.4s, v6.4s, v17.4s\n"
307     "srshl v5.4s, v5.4s, v17.4s\n"
308     "srshl v4.4s, v4.4s, v17.4s\n"
309     "srshl v3.4s, v3.4s, v17.4s\n"
310     "srshl v2.4s, v2.4s, v17.4s\n"
311     "srshl v1.4s, v1.4s, v17.4s\n"
312     "srshl v0.4s, v0.4s, v17.4s\n"
313     "add v15.4s, v15.4s, v16.4s\n"
314     "add v14.4s, v14.4s, v16.4s\n"
315     "add v13.4s, v13.4s, v16.4s\n"
316     "add v12.4s, v12.4s, v16.4s\n"
317     "add v11.4s, v11.4s, v16.4s\n"
318     "add v10.4s, v10.4s, v16.4s\n"
319     "add v9.4s, v9.4s, v16.4s\n"
320     "add v8.4s, v8.4s, v16.4s\n"
321     "add v7.4s, v7.4s, v16.4s\n"
322     "add v6.4s, v6.4s, v16.4s\n"
323     "add v5.4s, v5.4s, v16.4s\n"
324     "add v4.4s, v4.4s, v16.4s\n"
325     "add v3.4s, v3.4s, v16.4s\n"
326     "add v2.4s, v2.4s, v16.4s\n"
327     "add v1.4s, v1.4s, v16.4s\n"
328     "add v0.4s, v0.4s, v16.4s\n"
329     "movi v16.4s, #0x0\n"
330     "smax v15.4s, v15.4s, v16.4s\n"
331     "smax v14.4s, v14.4s, v16.4s\n"
332     "smax v13.4s, v13.4s, v16.4s\n"
333     "smax v12.4s, v12.4s, v16.4s\n"
334     "smax v11.4s, v11.4s, v16.4s\n"
335     "smax v10.4s, v10.4s, v16.4s\n"
336     "smax v9.4s, v9.4s, v16.4s\n"
337     "smax v8.4s, v8.4s, v16.4s\n"
338     "smax v7.4s, v7.4s, v16.4s\n"
339     "smax v6.4s, v6.4s, v16.4s\n"
340     "smax v5.4s, v5.4s, v16.4s\n"
341     "smax v4.4s, v4.4s, v16.4s\n"
342     "smax v3.4s, v3.4s, v16.4s\n"
343     "smax v2.4s, v2.4s, v16.4s\n"
344     "smax v1.4s, v1.4s, v16.4s\n"
345     "smax v0.4s, v0.4s, v16.4s\n"
346     "movi v16.4s, #0xff\n"
347     "smin v15.4s, v15.4s, v16.4s\n"
348     "smin v14.4s, v14.4s, v16.4s\n"
349     "smin v13.4s, v13.4s, v16.4s\n"
350     "smin v12.4s, v12.4s, v16.4s\n"
351     "smin v11.4s, v11.4s, v16.4s\n"
352     "smin v10.4s, v10.4s, v16.4s\n"
353     "smin v9.4s, v9.4s, v16.4s\n"
354     "smin v8.4s, v8.4s, v16.4s\n"
355     "smin v7.4s, v7.4s, v16.4s\n"
356     "smin v6.4s, v6.4s, v16.4s\n"
357     "smin v5.4s, v5.4s, v16.4s\n"
358     "smin v4.4s, v4.4s, v16.4s\n"
359     "smin v3.4s, v3.4s, v16.4s\n"
360     "smin v2.4s, v2.4s, v16.4s\n"
361     "smin v1.4s, v1.4s, v16.4s\n"
362     "smin v0.4s, v0.4s, v16.4s\n"
363     "uzp1 v23.16b, v15.16b, v14.16b\n"
364     "uzp1 v16.16b, v13.16b, v12.16b\n"
365     "uzp1 v22.16b, v11.16b, v10.16b\n"
366     "uzp1 v18.16b, v9.16b, v8.16b\n"
367     "uzp1 v21.16b, v7.16b, v6.16b\n"
368     "uzp1 v17.16b, v5.16b, v4.16b\n"
369     "uzp1 v20.16b, v3.16b, v2.16b\n"
370     "uzp1 v19.16b, v1.16b, v0.16b\n"
371     "uzp1 v16.16b, v23.16b, v16.16b\n"
372     "uzp1 v18.16b, v22.16b, v18.16b\n"
373     "str q16, [%x[outptr], x26]\n"
374     "add x26, x26, #0x40\n"
375     "uzp1 v17.16b, v21.16b, v17.16b\n"
376     "uzp1 v16.16b, v20.16b, v19.16b\n"
377     "str q18, [%x[outptr], x25]\n"
378     "add x25, x25, #0x40\n"
379     "str q17, [%x[outptr], x24]\n"
380     "add x24, x24, #0x40\n"
381     "str q16, [%x[outptr], x23]\n"
382     "add x23, x23, #0x40\n"
383     "bge 1b\n"
384     "cbz %x[n_channels], 43f\n"
385     "7:"  // Single vector of channels
386     "cmp %x[n_channels], #0x10\n"
387     "blt 14f\n"
388     "8:"  // Single vector of channels: Loop
389     "ld1r { v15.4s }, [%x[accumulator_init]]\n"
390     "lsr x22, %x[n_valid_cells], #0x1\n"
391     "mov v14.16b, v15.16b\n"
392     "mov v13.16b, v15.16b\n"
393     "mov v12.16b, v15.16b\n"
394     "mov x19, %x[inptrs]\n"
395     "cbz x22, 11f\n"
396     "ldp x21, x20, [x19, #0x0]\n"
397     "subs x22, x22, #0x1\n"
398     "add x19, x19, #0x10\n"
399     "ldr q31, [x21, x26]\n"
400     "ldr q30, [x20, x26]\n"
401     "beq 10f\n"
402     "9:"  // Single vector of channels: Loop: 2 inputs loop
403     "uaddl v23.8h, v31.8b, v30.8b\n"
404     "uaddl2 v22.8h, v31.16b, v30.16b\n"
405     "ldp x21, x20, [x19, #0x0]\n"
406     "subs x22, x22, #0x1\n"
407     "uaddw v15.4s, v15.4s, v23.4h\n"
408     "uaddw2 v14.4s, v14.4s, v23.8h\n"
409     "add x19, x19, #0x10\n"
410     "ldr q31, [x21, x26]\n"
411     "uaddw v13.4s, v13.4s, v22.4h\n"
412     "uaddw2 v12.4s, v12.4s, v22.8h\n"
413     "ldr q30, [x20, x26]\n"
414     "bgt 9b\n"
415     "10:"  // Single vector of channels: Loop: 2 inputs tail
416     "uaddl v23.8h, v31.8b, v30.8b\n"
417     "uaddl2 v22.8h, v31.16b, v30.16b\n"
418     "uaddw v15.4s, v15.4s, v23.4h\n"
419     "uaddw2 v14.4s, v14.4s, v23.8h\n"
420     "uaddw v13.4s, v13.4s, v22.4h\n"
421     "uaddw2 v12.4s, v12.4s, v22.8h\n"
422     "11:"  // Single vector of channels: Loop: After loop
423     "ands x20, %x[n_valid_cells], #0x1\n"
424     "beq 13f\n"
425     "12:"  // Single vector of channels: Loop: Single input loop
426     "ldr x21, [x19], #0x8\n"
427     "ldr q31, [x21, x26]\n"
428     "uxtl v23.8h, v31.8b\n"
429     "uxtl2 v22.8h, v31.16b\n"
430     "subs x20, x20, #0x1\n"
431     "uaddw v15.4s, v15.4s, v23.4h\n"
432     "uaddw2 v14.4s, v14.4s, v23.8h\n"
433     "uaddw v13.4s, v13.4s, v22.4h\n"
434     "uaddw2 v12.4s, v12.4s, v22.8h\n"
435     "bgt 12b\n"
436     "13:"  // Single vector of channels: Loop: Single input loop: End
437     "ld1r { v19.4s }, [%x[left_shift]]\n"
438     "ld1r { v18.4s }, [%x[combined_rescale_value]]\n"
439     "srshl v15.4s, v15.4s, v19.4s\n"
440     "srshl v14.4s, v14.4s, v19.4s\n"
441     "srshl v13.4s, v13.4s, v19.4s\n"
442     "srshl v12.4s, v12.4s, v19.4s\n"
443     "ld1r { v17.4s }, [%x[right_shift]]\n"
444     "add x19, %x[quant_params], %[offsetof_qp_output_offset]\n"
445     "sqrdmulh v15.4s, v15.4s, v18.4s\n"
446     "sqrdmulh v14.4s, v14.4s, v18.4s\n"
447     "ld1r { v16.4s }, [x19]\n"
448     "sub %x[n_channels], %x[n_channels], #0x10\n"
449     "sqrdmulh v13.4s, v13.4s, v18.4s\n"
450     "sqrdmulh v12.4s, v12.4s, v18.4s\n"
451     "cmp %x[n_channels], #0x10\n"
452     "srshl v15.4s, v15.4s, v17.4s\n"
453     "srshl v14.4s, v14.4s, v17.4s\n"
454     "srshl v13.4s, v13.4s, v17.4s\n"
455     "srshl v12.4s, v12.4s, v17.4s\n"
456     "add v15.4s, v15.4s, v16.4s\n"
457     "add v14.4s, v14.4s, v16.4s\n"
458     "add v13.4s, v13.4s, v16.4s\n"
459     "add v12.4s, v12.4s, v16.4s\n"
460     "movi v16.4s, #0x0\n"
461     "smax v15.4s, v15.4s, v16.4s\n"
462     "smax v14.4s, v14.4s, v16.4s\n"
463     "smax v13.4s, v13.4s, v16.4s\n"
464     "smax v12.4s, v12.4s, v16.4s\n"
465     "movi v16.4s, #0xff\n"
466     "smin v15.4s, v15.4s, v16.4s\n"
467     "smin v14.4s, v14.4s, v16.4s\n"
468     "smin v13.4s, v13.4s, v16.4s\n"
469     "smin v12.4s, v12.4s, v16.4s\n"
470     "uzp1 v23.16b, v15.16b, v14.16b\n"
471     "uzp1 v16.16b, v13.16b, v12.16b\n"
472     "uzp1 v16.16b, v23.16b, v16.16b\n"
473     "str q16, [%x[outptr], x26]\n"
474     "add x26, x26, #0x10\n"
475     "bge 8b\n"
476     "cbz %x[n_channels], 43f\n"
477     "14:"  // Oddments
478     "ld1r { v15.4s }, [%x[accumulator_init]]\n"
479     "lsr x22, %x[n_valid_cells], #0x1\n"
480     "add %x[outptr], %x[outptr], x26\n"
481     "mov v14.16b, v15.16b\n"
482     "mov v13.16b, v15.16b\n"
483     "mov v12.16b, v15.16b\n"
484     "mov x19, %x[inptrs]\n"
485     "cbz x22, 24f\n"
486     "15:"  // Oddments: 2 inputs loop
487     "ldp x21, x20, [x19, #0x0]\n"
488     "add x19, x19, #0x10\n"
489     "add x21, x21, x26\n"
490     "movi v31.16b, #0x0\n"
491     "add x20, x20, x26\n"
492     "movi v30.16b, #0x0\n"
493     "tbz %x[n_channels], #3, 19f\n"
494     "ldr d31, [x21], #0x8\n"
495     "ldr d30, [x20], #0x8\n"
496     "tbz %x[n_channels], #2, 17f\n"
497     "ld1 { v31.s }[2], [x21], #0x4\n"
498     "ld1 { v30.s }[2], [x20], #0x4\n"
499     "tbz %x[n_channels], #1, 16f\n"
500     "ld1 { v31.h }[6], [x21], #0x2\n"
501     "ld1 { v30.h }[6], [x20], #0x2\n"
502     "tbz %x[n_channels], #0, 23f\n"
503     "ld1 { v31.b }[14], [x21], #0x1\n"
504     "ld1 { v30.b }[14], [x20], #0x1\n"
505     "b 23f\n"
506     "16:"  // Oddments: 2 inputs loop: Load: Bit 3: Bit 2: Bit 1: Unset
507     "tbz %x[n_channels], #0, 23f\n"
508     "ld1 { v31.b }[12], [x21], #0x1\n"
509     "ld1 { v30.b }[12], [x20], #0x1\n"
510     "b 23f\n"
511     "17:"  // Oddments: 2 inputs loop: Load: Bit 3: Bit 2: Unset
512     "tbz %x[n_channels], #1, 18f\n"
513     "ld1 { v31.h }[4], [x21], #0x2\n"
514     "ld1 { v30.h }[4], [x20], #0x2\n"
515     "tbz %x[n_channels], #0, 23f\n"
516     "ld1 { v31.b }[10], [x21], #0x1\n"
517     "ld1 { v30.b }[10], [x20], #0x1\n"
518     "b 23f\n"
519     "18:"  // Oddments: 2 inputs loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset
520     "tbz %x[n_channels], #0, 23f\n"
521     "ld1 { v31.b }[8], [x21], #0x1\n"
522     "ld1 { v30.b }[8], [x20], #0x1\n"
523     "b 23f\n"
524     "19:"  // Oddments: 2 inputs loop: Load: Bit 3: Unset
525     "tbz %x[n_channels], #2, 21f\n"
526     "ldr s31, [x21], #0x4\n"
527     "ldr s30, [x20], #0x4\n"
528     "tbz %x[n_channels], #1, 20f\n"
529     "ld1 { v31.h }[2], [x21], #0x2\n"
530     "ld1 { v30.h }[2], [x20], #0x2\n"
531     "tbz %x[n_channels], #0, 23f\n"
532     "ld1 { v31.b }[6], [x21], #0x1\n"
533     "ld1 { v30.b }[6], [x20], #0x1\n"
534     "b 23f\n"
535     "20:"  // Oddments: 2 inputs loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset
536     "tbz %x[n_channels], #0, 23f\n"
537     "ld1 { v31.b }[4], [x21], #0x1\n"
538     "ld1 { v30.b }[4], [x20], #0x1\n"
539     "b 23f\n"
540     "21:"  // Oddments: 2 inputs loop: Load: Bit 3: Unset: Bit 2: Unset
541     "tbz %x[n_channels], #1, 22f\n"
542     "ldr h31, [x21], #0x2\n"
543     "ldr h30, [x20], #0x2\n"
544     "tbz %x[n_channels], #0, 23f\n"
545     "ld1 { v31.b }[2], [x21], #0x1\n"
546     "ld1 { v30.b }[2], [x20], #0x1\n"
547     "b 23f\n"
548     "22:"  // Oddments: 2 inputs loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset
549     "tbz %x[n_channels], #0, 23f\n"
550     "ldr b31, [x21], #0x1\n"
551     "ldr b30, [x20], #0x1\n"
552     "23:"  // Oddments: 2 inputs loop: Load: Bit 3: End
553     "uaddl v23.8h, v31.8b, v30.8b\n"
554     "uaddl2 v22.8h, v31.16b, v30.16b\n"
555     "subs x22, x22, #0x1\n"
556     "uaddw v15.4s, v15.4s, v23.4h\n"
557     "uaddw2 v14.4s, v14.4s, v23.8h\n"
558     "uaddw v13.4s, v13.4s, v22.4h\n"
559     "uaddw2 v12.4s, v12.4s, v22.8h\n"
560     "bgt 15b\n"
561     "24:"  // Oddments: After loop
562     "ands x20, %x[n_valid_cells], #0x1\n"
563     "beq 34f\n"
564     "25:"  // Oddments: Single input loop
565     "ldr x21, [x19], #0x8\n"
566     "add x21, x21, x26\n"
567     "movi v31.16b, #0x0\n"
568     "tbz %x[n_channels], #3, 29f\n"
569     "ldr d31, [x21], #0x8\n"
570     "tbz %x[n_channels], #2, 27f\n"
571     "ld1 { v31.s }[2], [x21], #0x4\n"
572     "tbz %x[n_channels], #1, 26f\n"
573     "ld1 { v31.h }[6], [x21], #0x2\n"
574     "tbz %x[n_channels], #0, 33f\n"
575     "ld1 { v31.b }[14], [x21], #0x1\n"
576     "b 33f\n"
577     "26:"  // Oddments: Single input loop: Load: Bit 3: Bit 2: Bit 1: Unset
578     "tbz %x[n_channels], #0, 33f\n"
579     "ld1 { v31.b }[12], [x21], #0x1\n"
580     "b 33f\n"
581     "27:"  // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset
582     "tbz %x[n_channels], #1, 28f\n"
583     "ld1 { v31.h }[4], [x21], #0x2\n"
584     "tbz %x[n_channels], #0, 33f\n"
585     "ld1 { v31.b }[10], [x21], #0x1\n"
586     "b 33f\n"
587     "28:"  // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset
588     "tbz %x[n_channels], #0, 33f\n"
589     "ld1 { v31.b }[8], [x21], #0x1\n"
590     "b 33f\n"
591     "29:"  // Oddments: Single input loop: Load: Bit 3: Unset
592     "tbz %x[n_channels], #2, 31f\n"
593     "ldr s31, [x21], #0x4\n"
594     "tbz %x[n_channels], #1, 30f\n"
595     "ld1 { v31.h }[2], [x21], #0x2\n"
596     "tbz %x[n_channels], #0, 33f\n"
597     "ld1 { v31.b }[6], [x21], #0x1\n"
598     "b 33f\n"
599     "30:"  // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset
600     "tbz %x[n_channels], #0, 33f\n"
601     "ld1 { v31.b }[4], [x21], #0x1\n"
602     "b 33f\n"
603     "31:"  // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset
604     "tbz %x[n_channels], #1, 32f\n"
605     "ldr h31, [x21], #0x2\n"
606     "tbz %x[n_channels], #0, 33f\n"
607     "ld1 { v31.b }[2], [x21], #0x1\n"
608     "b 33f\n"
609     "32:"  // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset
610     "tbz %x[n_channels], #0, 33f\n"
611     "ldr b31, [x21], #0x1\n"
612     "33:"  // Oddments: Single input loop: Load: Bit 3: End
613     "uxtl v23.8h, v31.8b\n"
614     "uxtl2 v22.8h, v31.16b\n"
615     "subs x20, x20, #0x1\n"
616     "uaddw v15.4s, v15.4s, v23.4h\n"
617     "uaddw2 v14.4s, v14.4s, v23.8h\n"
618     "uaddw v13.4s, v13.4s, v22.4h\n"
619     "uaddw2 v12.4s, v12.4s, v22.8h\n"
620     "bgt 25b\n"
621     "34:"  // Oddments: Single input loop: End
622     "ld1r { v19.4s }, [%x[left_shift]]\n"
623     "ld1r { v18.4s }, [%x[combined_rescale_value]]\n"
624     "srshl v15.4s, v15.4s, v19.4s\n"
625     "srshl v14.4s, v14.4s, v19.4s\n"
626     "srshl v13.4s, v13.4s, v19.4s\n"
627     "srshl v12.4s, v12.4s, v19.4s\n"
628     "ld1r { v17.4s }, [%x[right_shift]]\n"
629     "add x19, %x[quant_params], %[offsetof_qp_output_offset]\n"
630     "sqrdmulh v15.4s, v15.4s, v18.4s\n"
631     "sqrdmulh v14.4s, v14.4s, v18.4s\n"
632     "ld1r { v16.4s }, [x19]\n"
633     "sqrdmulh v13.4s, v13.4s, v18.4s\n"
634     "sqrdmulh v12.4s, v12.4s, v18.4s\n"
635     "srshl v15.4s, v15.4s, v17.4s\n"
636     "srshl v14.4s, v14.4s, v17.4s\n"
637     "srshl v13.4s, v13.4s, v17.4s\n"
638     "srshl v12.4s, v12.4s, v17.4s\n"
639     "add v15.4s, v15.4s, v16.4s\n"
640     "add v14.4s, v14.4s, v16.4s\n"
641     "add v13.4s, v13.4s, v16.4s\n"
642     "add v12.4s, v12.4s, v16.4s\n"
643     "movi v16.4s, #0x0\n"
644     "smax v15.4s, v15.4s, v16.4s\n"
645     "smax v14.4s, v14.4s, v16.4s\n"
646     "smax v13.4s, v13.4s, v16.4s\n"
647     "smax v12.4s, v12.4s, v16.4s\n"
648     "movi v16.4s, #0xff\n"
649     "smin v15.4s, v15.4s, v16.4s\n"
650     "smin v14.4s, v14.4s, v16.4s\n"
651     "smin v13.4s, v13.4s, v16.4s\n"
652     "smin v12.4s, v12.4s, v16.4s\n"
653     "uzp1 v23.16b, v15.16b, v14.16b\n"
654     "uzp1 v16.16b, v13.16b, v12.16b\n"
655     "uzp1 v16.16b, v23.16b, v16.16b\n"
656     "tbz %x[n_channels], #3, 38f\n"
657     "st1 { v16.d }[0], [%x[outptr]], #0x8\n"
658     "tbz %x[n_channels], #2, 36f\n"
659     "st1 { v16.s }[2], [%x[outptr]], #0x4\n"
660     "tbz %x[n_channels], #1, 35f\n"
661     "st1 { v16.h }[6], [%x[outptr]], #0x2\n"
662     "tbz %x[n_channels], #0, 42f\n"
663     "st1 { v16.b }[14], [%x[outptr]], #0x1\n"
664     "b 42f\n"
665     "35:"  // Oddments: Store: Bit 3: Bit 2: Bit 1: Unset
666     "tbz %x[n_channels], #0, 42f\n"
667     "st1 { v16.b }[12], [%x[outptr]], #0x1\n"
668     "b 42f\n"
669     "36:"  // Oddments: Store: Bit 3: Bit 2: Unset
670     "tbz %x[n_channels], #1, 37f\n"
671     "st1 { v16.h }[4], [%x[outptr]], #0x2\n"
672     "tbz %x[n_channels], #0, 42f\n"
673     "st1 { v16.b }[10], [%x[outptr]], #0x1\n"
674     "b 42f\n"
675     "37:"  // Oddments: Store: Bit 3: Bit 2: Unset: Bit 1: Unset
676     "tbz %x[n_channels], #0, 42f\n"
677     "st1 { v16.b }[8], [%x[outptr]], #0x1\n"
678     "b 42f\n"
679     "38:"  // Oddments: Store: Bit 3: Unset
680     "tbz %x[n_channels], #2, 40f\n"
681     "st1 { v16.s }[0], [%x[outptr]], #0x4\n"
682     "tbz %x[n_channels], #1, 39f\n"
683     "st1 { v16.h }[2], [%x[outptr]], #0x2\n"
684     "tbz %x[n_channels], #0, 42f\n"
685     "st1 { v16.b }[6], [%x[outptr]], #0x1\n"
686     "b 42f\n"
687     "39:"  // Oddments: Store: Bit 3: Unset: Bit 2: Bit 1: Unset
688     "tbz %x[n_channels], #0, 42f\n"
689     "st1 { v16.b }[4], [%x[outptr]], #0x1\n"
690     "b 42f\n"
691     "40:"  // Oddments: Store: Bit 3: Unset: Bit 2: Unset
692     "tbz %x[n_channels], #1, 41f\n"
693     "st1 { v16.h }[0], [%x[outptr]], #0x2\n"
694     "tbz %x[n_channels], #0, 42f\n"
695     "st1 { v16.b }[2], [%x[outptr]], #0x1\n"
696     "b 42f\n"
697     "41:"  // Oddments: Store: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset
698     "tbz %x[n_channels], #0, 42f\n"
699     "st1 { v16.b }[0], [%x[outptr]], #0x1\n"
700     "42:"  // Oddments: Store: Bit 3: End
701     "43:"  // End
702     : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr)
703     : [accumulator_init] "r" (&accumulator_init), [combined_rescale_value] "r" (&combined_rescale_value), [inptrs] "r" (inptrs), [left_shift] "r" (&left_shift), [n_valid_cells] "r" (n_valid_cells), [offsetof_qp_output_offset] "I" (offsetof(Requantize32, output_offset)), [quant_params] "r" (&qp), [right_shift] "r" (&right_shift)
704     : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26"
705   );
706 }
707 
708 }  // namespace pooling
709 }  // namespace arm_conv
710 #endif  // defined(__aarch64__)
711