1 /*
2  * Copyright (c) 2021-2022 Arm Limited.
3  *
4  * SPDX-License-Identifier: MIT
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to
8  * deal in the Software without restriction, including without limitation the
9  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10  * sell copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in all
14  * copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22  * SOFTWARE.
23  */
24 
25 #if defined(__aarch64__)
26 
27 #include <cstdint>
28 #include <cstddef>
29 
30 namespace arm_conv {
31 namespace pooling {
32 
33 
a64_u8_nhwc_max_generic_depthfirst_impl(const uint64_t,const uint64_t n_valid_cells,uint64_t n_channels,const uint8_t * const * const inptrs,uint8_t * outptr)34 void a64_u8_nhwc_max_generic_depthfirst_impl(
35   const uint64_t,
36   const uint64_t n_valid_cells,
37   uint64_t n_channels,
38   const uint8_t *const *const inptrs,
39   uint8_t *outptr
40 )
41 {
42   __asm__ __volatile__(
43     "cmp %x[n_channels], #0x40\n"
44     "mov x28, #0x0\n"
45     "mov x27, #0x10\n"  // cntb _, ALL, #1
46     "mov x26, #0x20\n"  // cntb _, ALL, #2
47     "mov x25, #0x30\n"  // cntb _, ALL, #3
48     "blt 7f\n"
49     "1:"  // 4-vectors of channels
50     "lsr x24, %x[n_valid_cells], #0x2\n"
51     "movi v6.16b, #0x0\n"
52     "movi v5.16b, #0x0\n"
53     "mov x19, %x[inptrs]\n"
54     "movi v4.16b, #0x0\n"
55     "movi v3.16b, #0x0\n"
56     "cbz x24, 4f\n"
57     "ldp x23, x22, [x19, #0x0]\n"
58     "ldp x21, x20, [x19, #0x10]\n"
59     "subs x24, x24, #0x1\n"
60     "add x19, x19, #0x20\n"
61     "ldr q2, [x23, x28]\n"
62     "ldr q1, [x22, x28]\n"
63     "ldr q0, [x21, x28]\n"
64     "ldr q31, [x20, x28]\n"
65     "ldr q30, [x23, x27]\n"
66     "ldr q22, [x22, x27]\n"
67     "ldr q29, [x21, x27]\n"
68     "ldr q28, [x20, x27]\n"
69     "ldr q27, [x23, x26]\n"
70     "ldr q21, [x22, x26]\n"
71     "ldr q26, [x21, x26]\n"
72     "ldr q17, [x20, x26]\n"
73     "ldr q25, [x23, x25]\n"
74     "ldr q20, [x22, x25]\n"
75     "ldr q24, [x21, x25]\n"
76     "ldr q16, [x20, x25]\n"
77     "beq 3f\n"
78     "2:"  // 4-vectors of channels: 4 inputs loop
79     "umax v23.16b, v2.16b, v1.16b\n"
80     "umax v19.16b, v0.16b, v31.16b\n"
81     "ldp x23, x22, [x19, #0x0]\n"
82     "ldp x21, x20, [x19, #0x10]\n"
83     "umax v22.16b, v30.16b, v22.16b\n"
84     "umax v18.16b, v29.16b, v28.16b\n"
85     "subs x24, x24, #0x1\n"
86     "add x19, x19, #0x20\n"
87     "umax v21.16b, v27.16b, v21.16b\n"
88     "umax v17.16b, v26.16b, v17.16b\n"
89     "ldr q2, [x23, x28]\n"
90     "ldr q1, [x22, x28]\n"
91     "umax v20.16b, v25.16b, v20.16b\n"
92     "umax v16.16b, v24.16b, v16.16b\n"
93     "ldr q0, [x21, x28]\n"
94     "ldr q31, [x20, x28]\n"
95     "umax v19.16b, v23.16b, v19.16b\n"
96     "umax v18.16b, v22.16b, v18.16b\n"
97     "ldr q30, [x23, x27]\n"
98     "ldr q22, [x22, x27]\n"
99     "umax v17.16b, v21.16b, v17.16b\n"
100     "umax v16.16b, v20.16b, v16.16b\n"
101     "ldr q29, [x21, x27]\n"
102     "ldr q28, [x20, x27]\n"
103     "umax v6.16b, v6.16b, v19.16b\n"
104     "umax v5.16b, v5.16b, v18.16b\n"
105     "ldr q27, [x23, x26]\n"
106     "ldr q21, [x22, x26]\n"
107     "umax v4.16b, v4.16b, v17.16b\n"
108     "umax v3.16b, v3.16b, v16.16b\n"
109     "ldr q26, [x21, x26]\n"
110     "ldr q17, [x20, x26]\n"
111     "ldr q25, [x23, x25]\n"
112     "ldr q20, [x22, x25]\n"
113     "ldr q24, [x21, x25]\n"
114     "ldr q16, [x20, x25]\n"
115     "bgt 2b\n"
116     "3:"  // 4-vectors of channels: 4 inputs tail
117     "umax v23.16b, v2.16b, v1.16b\n"
118     "umax v19.16b, v0.16b, v31.16b\n"
119     "umax v22.16b, v30.16b, v22.16b\n"
120     "umax v18.16b, v29.16b, v28.16b\n"
121     "umax v21.16b, v27.16b, v21.16b\n"
122     "umax v17.16b, v26.16b, v17.16b\n"
123     "umax v20.16b, v25.16b, v20.16b\n"
124     "umax v16.16b, v24.16b, v16.16b\n"
125     "umax v19.16b, v23.16b, v19.16b\n"
126     "umax v18.16b, v22.16b, v18.16b\n"
127     "umax v17.16b, v21.16b, v17.16b\n"
128     "umax v16.16b, v20.16b, v16.16b\n"
129     "umax v6.16b, v6.16b, v19.16b\n"
130     "umax v5.16b, v5.16b, v18.16b\n"
131     "umax v4.16b, v4.16b, v17.16b\n"
132     "umax v3.16b, v3.16b, v16.16b\n"
133     "4:"  // 4-vectors of channels: After loop
134     "ands x20, %x[n_valid_cells], #0x3\n"
135     "beq 6f\n"
136     "5:"  // 4-vectors of channels: Single input loop
137     "ldr x23, [x19], #0x8\n"
138     "ldr q2, [x23, x28]\n"
139     "subs x20, x20, #0x1\n"
140     "umax v6.16b, v6.16b, v2.16b\n"
141     "ldr q30, [x23, x27]\n"
142     "ldr q27, [x23, x26]\n"
143     "umax v5.16b, v5.16b, v30.16b\n"
144     "umax v4.16b, v4.16b, v27.16b\n"
145     "ldr q25, [x23, x25]\n"
146     "umax v3.16b, v3.16b, v25.16b\n"
147     "bgt 5b\n"
148     "6:"  // 4-vectors of channels: Single input loop: End
149     "sub %x[n_channels], %x[n_channels], #0x40\n"
150     "cmp %x[n_channels], #0x40\n"
151     "str q6, [%x[outptr], x28]\n"
152     "str q5, [%x[outptr], x27]\n"
153     "add x28, x28, #0x40\n"
154     "add x27, x27, #0x40\n"
155     "str q4, [%x[outptr], x26]\n"
156     "add x26, x26, #0x40\n"
157     "str q3, [%x[outptr], x25]\n"
158     "add x25, x25, #0x40\n"
159     "bge 1b\n"
160     "cbz %x[n_channels], 43f\n"
161     "7:"  // Single vector of channels
162     "cmp %x[n_channels], #0x10\n"
163     "blt 14f\n"
164     "8:"  // Single vector of channels: Loop
165     "lsr x24, %x[n_valid_cells], #0x2\n"
166     "movi v6.16b, #0x0\n"
167     "mov x19, %x[inptrs]\n"
168     "cbz x24, 11f\n"
169     "ldp x23, x22, [x19, #0x0]\n"
170     "ldp x21, x20, [x19, #0x10]\n"
171     "subs x24, x24, #0x1\n"
172     "add x19, x19, #0x20\n"
173     "ldr q2, [x23, x28]\n"
174     "ldr q1, [x22, x28]\n"
175     "ldr q0, [x21, x28]\n"
176     "ldr q31, [x20, x28]\n"
177     "beq 10f\n"
178     "9:"  // Single vector of channels: Loop: 4 inputs loop
179     "umax v23.16b, v2.16b, v1.16b\n"
180     "umax v19.16b, v0.16b, v31.16b\n"
181     "ldp x23, x22, [x19, #0x0]\n"
182     "ldp x21, x20, [x19, #0x10]\n"
183     "umax v19.16b, v23.16b, v19.16b\n"
184     "subs x24, x24, #0x1\n"
185     "umax v6.16b, v6.16b, v19.16b\n"
186     "add x19, x19, #0x20\n"
187     "ldr q2, [x23, x28]\n"
188     "ldr q1, [x22, x28]\n"
189     "ldr q0, [x21, x28]\n"
190     "ldr q31, [x20, x28]\n"
191     "bgt 9b\n"
192     "10:"  // Single vector of channels: Loop: 4 inputs tail
193     "umax v23.16b, v2.16b, v1.16b\n"
194     "umax v19.16b, v0.16b, v31.16b\n"
195     "umax v19.16b, v23.16b, v19.16b\n"
196     "umax v6.16b, v6.16b, v19.16b\n"
197     "11:"  // Single vector of channels: Loop: After loop
198     "ands x20, %x[n_valid_cells], #0x3\n"
199     "beq 13f\n"
200     "12:"  // Single vector of channels: Loop: Single input loop
201     "ldr x23, [x19], #0x8\n"
202     "ldr q2, [x23, x28]\n"
203     "subs x20, x20, #0x1\n"
204     "umax v6.16b, v6.16b, v2.16b\n"
205     "bgt 12b\n"
206     "13:"  // Single vector of channels: Loop: Single input loop: End
207     "sub %x[n_channels], %x[n_channels], #0x10\n"
208     "cmp %x[n_channels], #0x10\n"
209     "str q6, [%x[outptr], x28]\n"
210     "add x28, x28, #0x10\n"
211     "bge 8b\n"
212     "cbz %x[n_channels], 43f\n"
213     "14:"  // Oddments
214     "lsr x24, %x[n_valid_cells], #0x2\n"
215     "add %x[outptr], %x[outptr], x28\n"
216     "movi v6.16b, #0x0\n"
217     "mov x19, %x[inptrs]\n"
218     "cbz x24, 24f\n"
219     "15:"  // Oddments: 4 inputs loop
220     "ldp x23, x22, [x19, #0x0]\n"
221     "ldp x21, x20, [x19, #0x10]\n"
222     "add x19, x19, #0x20\n"
223     "add x23, x23, x28\n"
224     "add x22, x22, x28\n"
225     "add x21, x21, x28\n"
226     "movi v2.16b, #0x0\n"
227     "movi v1.16b, #0x0\n"
228     "add x20, x20, x28\n"
229     "movi v0.16b, #0x0\n"
230     "movi v31.16b, #0x0\n"
231     "tbz %x[n_channels], #3, 19f\n"
232     "ldr d2, [x23], #0x8\n"
233     "ldr d1, [x22], #0x8\n"
234     "ldr d0, [x21], #0x8\n"
235     "ldr d31, [x20], #0x8\n"
236     "tbz %x[n_channels], #2, 17f\n"
237     "ld1 { v2.s }[2], [x23], #0x4\n"
238     "ld1 { v1.s }[2], [x22], #0x4\n"
239     "ld1 { v0.s }[2], [x21], #0x4\n"
240     "ld1 { v31.s }[2], [x20], #0x4\n"
241     "tbz %x[n_channels], #1, 16f\n"
242     "ld1 { v2.h }[6], [x23], #0x2\n"
243     "ld1 { v1.h }[6], [x22], #0x2\n"
244     "ld1 { v0.h }[6], [x21], #0x2\n"
245     "ld1 { v31.h }[6], [x20], #0x2\n"
246     "tbz %x[n_channels], #0, 23f\n"
247     "ld1 { v2.b }[14], [x23], #0x1\n"
248     "ld1 { v1.b }[14], [x22], #0x1\n"
249     "ld1 { v0.b }[14], [x21], #0x1\n"
250     "ld1 { v31.b }[14], [x20], #0x1\n"
251     "b 23f\n"
252     "16:"  // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Bit 1: Unset
253     "tbz %x[n_channels], #0, 23f\n"
254     "ld1 { v2.b }[12], [x23], #0x1\n"
255     "ld1 { v1.b }[12], [x22], #0x1\n"
256     "ld1 { v0.b }[12], [x21], #0x1\n"
257     "ld1 { v31.b }[12], [x20], #0x1\n"
258     "b 23f\n"
259     "17:"  // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Unset
260     "tbz %x[n_channels], #1, 18f\n"
261     "ld1 { v2.h }[4], [x23], #0x2\n"
262     "ld1 { v1.h }[4], [x22], #0x2\n"
263     "ld1 { v0.h }[4], [x21], #0x2\n"
264     "ld1 { v31.h }[4], [x20], #0x2\n"
265     "tbz %x[n_channels], #0, 23f\n"
266     "ld1 { v2.b }[10], [x23], #0x1\n"
267     "ld1 { v1.b }[10], [x22], #0x1\n"
268     "ld1 { v0.b }[10], [x21], #0x1\n"
269     "ld1 { v31.b }[10], [x20], #0x1\n"
270     "b 23f\n"
271     "18:"  // Oddments: 4 inputs loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset
272     "tbz %x[n_channels], #0, 23f\n"
273     "ld1 { v2.b }[8], [x23], #0x1\n"
274     "ld1 { v1.b }[8], [x22], #0x1\n"
275     "ld1 { v0.b }[8], [x21], #0x1\n"
276     "ld1 { v31.b }[8], [x20], #0x1\n"
277     "b 23f\n"
278     "19:"  // Oddments: 4 inputs loop: Load: Bit 3: Unset
279     "tbz %x[n_channels], #2, 21f\n"
280     "ldr s2, [x23], #0x4\n"
281     "ldr s1, [x22], #0x4\n"
282     "ldr s0, [x21], #0x4\n"
283     "ldr s31, [x20], #0x4\n"
284     "tbz %x[n_channels], #1, 20f\n"
285     "ld1 { v2.h }[2], [x23], #0x2\n"
286     "ld1 { v1.h }[2], [x22], #0x2\n"
287     "ld1 { v0.h }[2], [x21], #0x2\n"
288     "ld1 { v31.h }[2], [x20], #0x2\n"
289     "tbz %x[n_channels], #0, 23f\n"
290     "ld1 { v2.b }[6], [x23], #0x1\n"
291     "ld1 { v1.b }[6], [x22], #0x1\n"
292     "ld1 { v0.b }[6], [x21], #0x1\n"
293     "ld1 { v31.b }[6], [x20], #0x1\n"
294     "b 23f\n"
295     "20:"  // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset
296     "tbz %x[n_channels], #0, 23f\n"
297     "ld1 { v2.b }[4], [x23], #0x1\n"
298     "ld1 { v1.b }[4], [x22], #0x1\n"
299     "ld1 { v0.b }[4], [x21], #0x1\n"
300     "ld1 { v31.b }[4], [x20], #0x1\n"
301     "b 23f\n"
302     "21:"  // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Unset
303     "tbz %x[n_channels], #1, 22f\n"
304     "ldr h2, [x23], #0x2\n"
305     "ldr h1, [x22], #0x2\n"
306     "ldr h0, [x21], #0x2\n"
307     "ldr h31, [x20], #0x2\n"
308     "tbz %x[n_channels], #0, 23f\n"
309     "ld1 { v2.b }[2], [x23], #0x1\n"
310     "ld1 { v1.b }[2], [x22], #0x1\n"
311     "ld1 { v0.b }[2], [x21], #0x1\n"
312     "ld1 { v31.b }[2], [x20], #0x1\n"
313     "b 23f\n"
314     "22:"  // Oddments: 4 inputs loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset
315     "tbz %x[n_channels], #0, 23f\n"
316     "ldr b2, [x23], #0x1\n"
317     "ldr b1, [x22], #0x1\n"
318     "ldr b0, [x21], #0x1\n"
319     "ldr b31, [x20], #0x1\n"
320     "23:"  // Oddments: 4 inputs loop: Load: Bit 3: End
321     "umax v23.16b, v2.16b, v1.16b\n"
322     "umax v19.16b, v0.16b, v31.16b\n"
323     "subs x24, x24, #0x1\n"
324     "umax v19.16b, v23.16b, v19.16b\n"
325     "umax v6.16b, v6.16b, v19.16b\n"
326     "bgt 15b\n"
327     "24:"  // Oddments: After loop
328     "ands x20, %x[n_valid_cells], #0x3\n"
329     "beq 34f\n"
330     "25:"  // Oddments: Single input loop
331     "ldr x23, [x19], #0x8\n"
332     "add x23, x23, x28\n"
333     "movi v2.16b, #0x0\n"
334     "tbz %x[n_channels], #3, 29f\n"
335     "ldr d2, [x23], #0x8\n"
336     "tbz %x[n_channels], #2, 27f\n"
337     "ld1 { v2.s }[2], [x23], #0x4\n"
338     "tbz %x[n_channels], #1, 26f\n"
339     "ld1 { v2.h }[6], [x23], #0x2\n"
340     "tbz %x[n_channels], #0, 33f\n"
341     "ld1 { v2.b }[14], [x23], #0x1\n"
342     "b 33f\n"
343     "26:"  // Oddments: Single input loop: Load: Bit 3: Bit 2: Bit 1: Unset
344     "tbz %x[n_channels], #0, 33f\n"
345     "ld1 { v2.b }[12], [x23], #0x1\n"
346     "b 33f\n"
347     "27:"  // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset
348     "tbz %x[n_channels], #1, 28f\n"
349     "ld1 { v2.h }[4], [x23], #0x2\n"
350     "tbz %x[n_channels], #0, 33f\n"
351     "ld1 { v2.b }[10], [x23], #0x1\n"
352     "b 33f\n"
353     "28:"  // Oddments: Single input loop: Load: Bit 3: Bit 2: Unset: Bit 1: Unset
354     "tbz %x[n_channels], #0, 33f\n"
355     "ld1 { v2.b }[8], [x23], #0x1\n"
356     "b 33f\n"
357     "29:"  // Oddments: Single input loop: Load: Bit 3: Unset
358     "tbz %x[n_channels], #2, 31f\n"
359     "ldr s2, [x23], #0x4\n"
360     "tbz %x[n_channels], #1, 30f\n"
361     "ld1 { v2.h }[2], [x23], #0x2\n"
362     "tbz %x[n_channels], #0, 33f\n"
363     "ld1 { v2.b }[6], [x23], #0x1\n"
364     "b 33f\n"
365     "30:"  // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Bit 1: Unset
366     "tbz %x[n_channels], #0, 33f\n"
367     "ld1 { v2.b }[4], [x23], #0x1\n"
368     "b 33f\n"
369     "31:"  // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset
370     "tbz %x[n_channels], #1, 32f\n"
371     "ldr h2, [x23], #0x2\n"
372     "tbz %x[n_channels], #0, 33f\n"
373     "ld1 { v2.b }[2], [x23], #0x1\n"
374     "b 33f\n"
375     "32:"  // Oddments: Single input loop: Load: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset
376     "tbz %x[n_channels], #0, 33f\n"
377     "ldr b2, [x23], #0x1\n"
378     "33:"  // Oddments: Single input loop: Load: Bit 3: End
379     "subs x20, x20, #0x1\n"
380     "umax v6.16b, v6.16b, v2.16b\n"
381     "bgt 25b\n"
382     "34:"  // Oddments: Single input loop: End
383     "tbz %x[n_channels], #3, 38f\n"
384     "st1 { v6.d }[0], [%x[outptr]], #0x8\n"
385     "tbz %x[n_channels], #2, 36f\n"
386     "st1 { v6.s }[2], [%x[outptr]], #0x4\n"
387     "tbz %x[n_channels], #1, 35f\n"
388     "st1 { v6.h }[6], [%x[outptr]], #0x2\n"
389     "tbz %x[n_channels], #0, 42f\n"
390     "st1 { v6.b }[14], [%x[outptr]], #0x1\n"
391     "b 42f\n"
392     "35:"  // Oddments: Store: Bit 3: Bit 2: Bit 1: Unset
393     "tbz %x[n_channels], #0, 42f\n"
394     "st1 { v6.b }[12], [%x[outptr]], #0x1\n"
395     "b 42f\n"
396     "36:"  // Oddments: Store: Bit 3: Bit 2: Unset
397     "tbz %x[n_channels], #1, 37f\n"
398     "st1 { v6.h }[4], [%x[outptr]], #0x2\n"
399     "tbz %x[n_channels], #0, 42f\n"
400     "st1 { v6.b }[10], [%x[outptr]], #0x1\n"
401     "b 42f\n"
402     "37:"  // Oddments: Store: Bit 3: Bit 2: Unset: Bit 1: Unset
403     "tbz %x[n_channels], #0, 42f\n"
404     "st1 { v6.b }[8], [%x[outptr]], #0x1\n"
405     "b 42f\n"
406     "38:"  // Oddments: Store: Bit 3: Unset
407     "tbz %x[n_channels], #2, 40f\n"
408     "st1 { v6.s }[0], [%x[outptr]], #0x4\n"
409     "tbz %x[n_channels], #1, 39f\n"
410     "st1 { v6.h }[2], [%x[outptr]], #0x2\n"
411     "tbz %x[n_channels], #0, 42f\n"
412     "st1 { v6.b }[6], [%x[outptr]], #0x1\n"
413     "b 42f\n"
414     "39:"  // Oddments: Store: Bit 3: Unset: Bit 2: Bit 1: Unset
415     "tbz %x[n_channels], #0, 42f\n"
416     "st1 { v6.b }[4], [%x[outptr]], #0x1\n"
417     "b 42f\n"
418     "40:"  // Oddments: Store: Bit 3: Unset: Bit 2: Unset
419     "tbz %x[n_channels], #1, 41f\n"
420     "st1 { v6.h }[0], [%x[outptr]], #0x2\n"
421     "tbz %x[n_channels], #0, 42f\n"
422     "st1 { v6.b }[2], [%x[outptr]], #0x1\n"
423     "b 42f\n"
424     "41:"  // Oddments: Store: Bit 3: Unset: Bit 2: Unset: Bit 1: Unset
425     "tbz %x[n_channels], #0, 42f\n"
426     "st1 { v6.b }[0], [%x[outptr]], #0x1\n"
427     "42:"  // Oddments: Store: Bit 3: End
428     "43:"  // End
429     : [n_channels] "+&r" (n_channels), [outptr] "+&r" (outptr)
430     : [inptrs] "r" (inptrs), [n_valid_cells] "r" (n_valid_cells)
431     : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
432   );
433 }
434 
435 }  // namespace pooling
436 }  // namespace arm_conv
437 #endif  // defined(__aarch64__)
438