1 /*
2 * Copyright (c) 2012-2015 Travis Geiselbrecht
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files
6 * (the "Software"), to deal in the Software without restriction,
7 * including without limitation the rights to use, copy, modify, merge,
8 * publish, distribute, sublicense, and/or sell copies of the Software,
9 * and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <debug.h>
24 #include <arch.h>
25 #include <arch/ops.h>
26 #include <arch/arm.h>
27 #include <kernel/thread.h>
28 #include <kernel/debug.h>
29 #include <platform.h>
30 #include <arch/arm/cm.h>
31 #include <target.h>
32
33 extern void *vectab;
34
35 #if ARM_CM_DYNAMIC_PRIORITY_SIZE
36 unsigned int arm_cm_num_irq_pri_bits;
37 unsigned int arm_cm_irq_pri_mask;
38 #endif
39
arch_early_init(void)40 void arch_early_init(void)
41 {
42
43 arch_disable_ints();
44
45 #if (__CORTEX_M >= 0x03) || (CORTEX_SC >= 300)
46 uint i;
47 /* set the vector table base */
48 SCB->VTOR = (uint32_t)&vectab;
49
50 #if ARM_CM_DYNAMIC_PRIORITY_SIZE
51 /* number of priorities */
52 for (i=0; i < 7; i++) {
53 __set_BASEPRI(1 << i);
54 if (__get_BASEPRI() != 0)
55 break;
56 }
57 arm_cm_num_irq_pri_bits = 8 - i;
58 arm_cm_irq_pri_mask = ~((1 << i) - 1) & 0xff;
59 #endif
60
61 /* clear any pending interrupts and set all the vectors to medium priority */
62 uint groups = (SCnSCB->ICTR & 0xf) + 1;
63 for (i = 0; i < groups; i++) {
64 NVIC->ICER[i] = 0xffffffff;
65 NVIC->ICPR[i] = 0xffffffff;
66 for (uint j = 0; j < 32; j++) {
67 NVIC_SetPriority(i*32 + j, arm_cm_medium_priority());
68 }
69 }
70
71 /* leave BASEPRI at 0 */
72 __set_BASEPRI(0);
73
74 /* set priority grouping to 0 */
75 NVIC_SetPriorityGrouping(0);
76
77 /* enable certain faults */
78 SCB->SHCSR |= (SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk);
79
80 /* set the svc and pendsv priority level to pretty low */
81 #endif
82 NVIC_SetPriority(SVCall_IRQn, arm_cm_lowest_priority());
83 NVIC_SetPriority(PendSV_IRQn, arm_cm_lowest_priority());
84
85 /* set systick and debugmonitor to medium priority */
86 NVIC_SetPriority(SysTick_IRQn, arm_cm_medium_priority());
87
88 #if (__CORTEX_M >= 0x03)
89 NVIC_SetPriority(DebugMonitor_IRQn, arm_cm_medium_priority());
90 #endif
91
92 /* FPU settings ------------------------------------------------------------*/
93 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
94 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
95 #endif
96
97 #if ARM_WITH_CACHE
98 arch_enable_cache(UCACHE);
99 #endif
100 }
101
arch_init(void)102 void arch_init(void)
103 {
104 #if ENABLE_CYCLE_COUNTER
105 *REG32(SCB_DEMCR) |= 0x01000000; // global trace enable
106 *REG32(DWT_CYCCNT) = 0;
107 *REG32(DWT_CTRL) |= 1; // enable cycle counter
108 #endif
109 printf("CONTROL 0x%x\n", __get_CONTROL());
110 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
111 printf("FPSCR 0x%x\n", __get_FPSCR());
112 printf("FPCCR 0x%x\n", FPU->FPCCR);
113 #endif
114 }
115
arch_quiesce(void)116 void arch_quiesce(void)
117 {
118 #if ARM_WITH_CACHE
119 arch_disable_cache(UCACHE);
120 #endif
121 }
122
arch_idle(void)123 void arch_idle(void)
124 {
125 __asm__ volatile("wfi");
126 }
127
128 #if (__CORTEX_M >= 0x03) || (CORTEX_SC >= 300)
129
_arm_cm_set_irqpri(uint32_t pri)130 void _arm_cm_set_irqpri(uint32_t pri)
131 {
132 if (pri == 0) {
133 __disable_irq(); // cpsid i
134 __set_BASEPRI(0);
135 } else if (pri >= 256) {
136 __set_BASEPRI(0);
137 __enable_irq();
138 } else {
139 uint32_t _pri = pri & arm_cm_irq_pri_mask;
140
141 if (_pri == 0)
142 __set_BASEPRI(1 << (8 - arm_cm_num_irq_pri_bits));
143 else
144 __set_BASEPRI(_pri);
145 __enable_irq(); // cpsie i
146 }
147 }
148 #endif
149
150
arm_cm_irq_entry(void)151 void arm_cm_irq_entry(void)
152 {
153 // Set PRIMASK to 1
154 // This is so that later calls to arch_ints_disabled() returns true while we're inside the int handler
155 // Note: this will probably screw up future efforts to stack higher priority interrupts since we're setting
156 // the cpu to essentially max interrupt priority here. Will have to rethink it then.
157 __disable_irq();
158
159 THREAD_STATS_INC(interrupts);
160 KEVLOG_IRQ_ENTER(__get_IPSR());
161
162 target_set_debug_led(1, true);
163 }
164
arm_cm_irq_exit(bool reschedule)165 void arm_cm_irq_exit(bool reschedule)
166 {
167 target_set_debug_led(1, false);
168
169 if (reschedule)
170 arm_cm_trigger_preempt();
171
172 KEVLOG_IRQ_EXIT(__get_IPSR());
173
174 __enable_irq(); // clear PRIMASK
175 }
176
arch_chain_load(void * entry,ulong arg0,ulong arg1,ulong arg2,ulong arg3)177 void arch_chain_load(void *entry, ulong arg0, ulong arg1, ulong arg2, ulong arg3)
178 {
179 #if (__CORTEX_M >= 0x03)
180
181 uint32_t *vectab = (uint32_t *)entry;
182
183 __asm__ volatile(
184 "mov r0, %[arg0]; "
185 "mov r1, %[arg1]; "
186 "mov r2, %[arg2]; "
187 "mov r3, %[arg3]; "
188 "mov sp, %[SP]; "
189 "bx %[entry]; "
190 :
191 : [arg0]"r"(arg0),
192 [arg1]"r"(arg1),
193 [arg2]"r"(arg2),
194 [arg3]"r"(arg3),
195 [SP]"r"(vectab[0]),
196 [entry]"r"(vectab[1])
197 : "r0", "r1", "r2", "r3"
198 );
199
200 __UNREACHABLE;
201 #else
202 PANIC_UNIMPLEMENTED;
203 #endif
204 }
205