1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_ospi.h 4 * @author MCD Application Team 5 * @brief Header file of OSPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2018 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L4xx_HAL_OSPI_H 22 #define STM32L4xx_HAL_OSPI_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l4xx_hal_def.h" 30 31 #if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2) 32 33 /** @addtogroup STM32L4xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup OSPI 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup OSPI_Exported_Types OSPI Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief OSPI Init structure definition 48 */ 49 typedef struct 50 { 51 uint32_t FifoThreshold; /* This is the threshold used by the Peripheral to generate the interrupt 52 indicating that data are available in reception or free place 53 is available in transmission. 54 This parameter can be a value between 1 and 32 */ 55 uint32_t DualQuad; /* It enables or not the dual-quad mode which allow to access up to 56 quad mode on two different devices to increase the throughput. 57 This parameter can be a value of @ref OSPI_DualQuad */ 58 uint32_t MemoryType; /* It indicates the external device type connected to the OSPI. 59 This parameter can be a value of @ref OSPI_MemoryType */ 60 uint32_t DeviceSize; /* It defines the size of the external device connected to the OSPI, 61 it corresponds to the number of address bits required to access 62 the external device. 63 This parameter can be a value between 1 and 32 */ 64 uint32_t ChipSelectHighTime; /* It defines the minimun number of clocks which the chip select 65 must remain high between commands. 66 This parameter can be a value between 1 and 8 */ 67 uint32_t FreeRunningClock; /* It enables or not the free running clock. 68 This parameter can be a value of @ref OSPI_FreeRunningClock */ 69 uint32_t ClockMode; /* It indicates the level of clock when the chip select is released. 70 This parameter can be a value of @ref OSPI_ClockMode */ 71 uint32_t WrapSize; /* It indicates the wrap-size corresponding the external device configuration. 72 This parameter can be a value of @ref OSPI_WrapSize */ 73 uint32_t ClockPrescaler; /* It specifies the prescaler factor used for generating 74 the external clock based on the AHB clock. 75 This parameter can be a value between 1 and 256 */ 76 uint32_t SampleShifting; /* It allows to delay to 1/2 cycle the data sampling in order 77 to take in account external signal delays. 78 This parameter can be a value of @ref OSPI_SampleShifting */ 79 uint32_t DelayHoldQuarterCycle; /* It allows to hold to 1/4 cycle the data. 80 This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */ 81 uint32_t ChipSelectBoundary; /* It enables the transaction boundary feature and 82 defines the boundary of bytes to release the chip select. 83 This parameter can be a value between 0 and 31 */ 84 #if defined (OCTOSPI_DCR4_REFRESH) 85 uint32_t Refresh; /* It enables the refresh rate feature. The chip select is released every 86 Refresh+1 clock cycles. 87 This parameter can be a value between 0 and 0xFFFFFFFF */ 88 #endif 89 }OSPI_InitTypeDef; 90 91 /** 92 * @brief HAL OSPI Handle Structure definition 93 */ 94 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 95 typedef struct __OSPI_HandleTypeDef 96 #else 97 typedef struct 98 #endif 99 { 100 OCTOSPI_TypeDef *Instance; /* OSPI registers base address */ 101 OSPI_InitTypeDef Init; /* OSPI initialization parameters */ 102 uint8_t *pBuffPtr; /* Address of the OSPI buffer for transfer */ 103 __IO uint32_t XferSize; /* Number of data to transfer */ 104 __IO uint32_t XferCount; /* Counter of data transferred */ 105 DMA_HandleTypeDef *hdma; /* Handle of the DMA channel used for the transfer */ 106 __IO uint32_t State; /* Internal state of the OSPI HAL driver */ 107 __IO uint32_t ErrorCode; /* Error code in case of HAL driver internal error */ 108 uint32_t Timeout; /* Timeout used for the OSPI external device access */ 109 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 110 void (* ErrorCallback) (struct __OSPI_HandleTypeDef *hospi); 111 void (* AbortCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 112 void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi); 113 void (* CmdCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 114 void (* RxCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 115 void (* TxCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 116 void (* RxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 117 void (* TxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 118 void (* StatusMatchCallback) (struct __OSPI_HandleTypeDef *hospi); 119 void (* TimeOutCallback) (struct __OSPI_HandleTypeDef *hospi); 120 121 void (* MspInitCallback) (struct __OSPI_HandleTypeDef *hospi); 122 void (* MspDeInitCallback) (struct __OSPI_HandleTypeDef *hospi); 123 #endif 124 }OSPI_HandleTypeDef; 125 126 /** 127 * @brief HAL OSPI Regular Command Structure definition 128 */ 129 typedef struct 130 { 131 uint32_t OperationType; /* It indicates if the configuration applies to the common regsiters or 132 to the registers for the write operation (these registers are only 133 used for memory-mapped mode). 134 This parameter can be a value of @ref OSPI_OperationType */ 135 uint32_t FlashId; /* It indicates which external device is selected for this command (it 136 applies only if Dualquad is disabled in the initialization structure). 137 This parameter can be a value of @ref OSPI_FlashId */ 138 uint32_t Instruction; /* It contains the instruction to be sent to the device. 139 This parameter can be a value between 0 and 0xFFFFFFFF */ 140 uint32_t InstructionMode; /* It indicates the mode of the instruction. 141 This parameter can be a value of @ref OSPI_InstructionMode */ 142 uint32_t InstructionSize; /* It indicates the size of the instruction. 143 This parameter can be a value of @ref OSPI_InstructionSize */ 144 uint32_t InstructionDtrMode; /* It enables or not the DTR mode for the instruction phase. 145 This parameter can be a value of @ref OSPI_InstructionDtrMode */ 146 uint32_t Address; /* It contains the address to be sent to the device. 147 This parameter can be a value between 0 and 0xFFFFFFFF */ 148 uint32_t AddressMode; /* It indicates the mode of the address. 149 This parameter can be a value of @ref OSPI_AddressMode */ 150 uint32_t AddressSize; /* It indicates the size of the address. 151 This parameter can be a value of @ref OSPI_AddressSize */ 152 uint32_t AddressDtrMode; /* It enables or not the DTR mode for the address phase. 153 This parameter can be a value of @ref OSPI_AddressDtrMode */ 154 uint32_t AlternateBytes; /* It contains the alternate bytes to be sent to the device. 155 This parameter can be a value between 0 and 0xFFFFFFFF */ 156 uint32_t AlternateBytesMode; /* It indicates the mode of the alternate bytes. 157 This parameter can be a value of @ref OSPI_AlternateBytesMode */ 158 uint32_t AlternateBytesSize; /* It indicates the size of the alternate bytes. 159 This parameter can be a value of @ref OSPI_AlternateBytesSize */ 160 uint32_t AlternateBytesDtrMode; /* It enables or not the DTR mode for the alternate bytes phase. 161 This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */ 162 uint32_t DataMode; /* It indicates the mode of the data. 163 This parameter can be a value of @ref OSPI_DataMode */ 164 uint32_t NbData; /* It indicates the number of data transferred with this command. 165 This field is only used for indirect mode. 166 This parameter can be a value between 1 and 0xFFFFFFFF */ 167 uint32_t DataDtrMode; /* It enables or not the DTR mode for the data phase. 168 This parameter can be a value of @ref OSPI_DataDtrMode */ 169 uint32_t DummyCycles; /* It indicates the number of dummy cycles inserted before data phase. 170 This parameter can be a value between 0 and 31 */ 171 uint32_t DQSMode; /* It enables or not the data strobe management. 172 This parameter can be a value of @ref OSPI_DQSMode */ 173 uint32_t SIOOMode; /* It enables or not the SIOO mode. 174 This parameter can be a value of @ref OSPI_SIOOMode */ 175 }OSPI_RegularCmdTypeDef; 176 177 /** 178 * @brief HAL OSPI Hyperbus Configuration Structure definition 179 */ 180 typedef struct 181 { 182 uint32_t RWRecoveryTime; /* It indicates the number of cycles for the device read write recovery time. 183 This parameter can be a value between 0 and 255 */ 184 uint32_t AccessTime; /* It indicates the number of cycles for the device acces time. 185 This parameter can be a value between 0 and 255 */ 186 uint32_t WriteZeroLatency; /* It enables or not the latency for the write access. 187 This parameter can be a value of @ref OSPI_WriteZeroLatency */ 188 uint32_t LatencyMode; /* It configures the latency mode. 189 This parameter can be a value of @ref OSPI_LatencyMode */ 190 }OSPI_HyperbusCfgTypeDef; 191 192 /** 193 * @brief HAL OSPI Hyperbus Command Structure definition 194 */ 195 typedef struct 196 { 197 uint32_t AddressSpace; /* It indicates the address space accessed by the command. 198 This parameter can be a value of @ref OSPI_AddressSpace */ 199 uint32_t Address; /* It contains the address to be sent tot he device. 200 This parameter can be a value between 0 and 0xFFFFFFFF */ 201 uint32_t AddressSize; /* It indicates the size of the address. 202 This parameter can be a value of @ref OSPI_AddressSize */ 203 uint32_t NbData; /* It indicates the number of data transferred with this command. 204 This field is only used for indirect mode. 205 This parameter can be a value between 1 and 0xFFFFFFFF 206 In case of autopolling mode, this parameter can be any value between 1 and 4 */ 207 uint32_t DQSMode; /* It enables or not the data strobe management. 208 This parameter can be a value of @ref OSPI_DQSMode */ 209 }OSPI_HyperbusCmdTypeDef; 210 211 /** 212 * @brief HAL OSPI Auto Polling mode configuration structure definition 213 */ 214 typedef struct 215 { 216 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. 217 This parameter can be any value between 0 and 0xFFFFFFFF */ 218 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. 219 This parameter can be any value between 0 and 0xFFFFFFFF */ 220 uint32_t MatchMode; /* Specifies the method used for determining a match. 221 This parameter can be a value of @ref OSPI_MatchMode */ 222 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. 223 This parameter can be a value of @ref OSPI_AutomaticStop */ 224 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. 225 This parameter can be any value between 0 and 0xFFFF */ 226 }OSPI_AutoPollingTypeDef; 227 228 /** 229 * @brief HAL OSPI Memory Mapped mode configuration structure definition 230 */ 231 typedef struct 232 { 233 uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. 234 This parameter can be a value of @ref OSPI_TimeOutActivation */ 235 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. 236 This parameter can be any value between 0 and 0xFFFF */ 237 }OSPI_MemoryMappedTypeDef; 238 239 /** 240 * @brief HAL OSPI IO Manager Configuration structure definition 241 */ 242 typedef struct 243 { 244 uint32_t ClkPort; /* It indicates which port of the OSPI IO Manager is used for the CLK pins. 245 This parameter can be a value between 1 and 8 */ 246 uint32_t DQSPort; /* It indicates which port of the OSPI IO Manager is used for the DQS pin. 247 This parameter can be a value between 1 and 8 */ 248 uint32_t NCSPort; /* It indicates which port of the OSPI IO Manager is used for the NCS pin. 249 This parameter can be a value between 1 and 8 */ 250 uint32_t IOLowPort; /* It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins. 251 This parameter can be a value of @ref OSPIM_IOPort */ 252 uint32_t IOHighPort; /* It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins. 253 This parameter can be a value of @ref OSPIM_IOPort */ 254 #if defined (OCTOSPIM_CR_MUXEN) 255 uint32_t Req2AckTime; /* It indicates the minimum switching duration (in number of clock cycles) expected 256 if some signals are multiplexed in the OSPI IO Manager with the other OSPI. 257 This parameter can be a value between 1 and 256 */ 258 #endif 259 }OSPIM_CfgTypeDef; 260 261 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 262 /** 263 * @brief HAL OSPI Callback ID enumeration definition 264 */ 265 typedef enum 266 { 267 HAL_OSPI_ERROR_CB_ID = 0x00U, /*!< OSPI Error Callback ID */ 268 HAL_OSPI_ABORT_CB_ID = 0x01U, /*!< OSPI Abort Callback ID */ 269 HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< OSPI FIFO Threshold Callback ID */ 270 HAL_OSPI_CMD_CPLT_CB_ID = 0x03U, /*!< OSPI Command Complete Callback ID */ 271 HAL_OSPI_RX_CPLT_CB_ID = 0x04U, /*!< OSPI Rx Complete Callback ID */ 272 HAL_OSPI_TX_CPLT_CB_ID = 0x05U, /*!< OSPI Tx Complete Callback ID */ 273 HAL_OSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< OSPI Rx Half Complete Callback ID */ 274 HAL_OSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< OSPI Tx Half Complete Callback ID */ 275 HAL_OSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< OSPI Status Match Callback ID */ 276 HAL_OSPI_TIMEOUT_CB_ID = 0x09U, /*!< OSPI Timeout Callback ID */ 277 278 HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, /*!< OSPI MspInit Callback ID */ 279 HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< OSPI MspDeInit Callback ID */ 280 }HAL_OSPI_CallbackIDTypeDef; 281 282 /** 283 * @brief HAL OSPI Callback pointer definition 284 */ 285 typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); 286 #endif 287 /** 288 * @} 289 */ 290 291 /* Exported constants --------------------------------------------------------*/ 292 /** @defgroup OSPI_Exported_Constants OSPI Exported Constants 293 * @{ 294 */ 295 296 /** @defgroup OSPI_State OSPI State 297 * @{ 298 */ 299 #define HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U) /*!< Initial state */ 300 #define HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */ 301 #define HAL_OSPI_STATE_READY ((uint32_t)0x00000002U) /*!< Driver ready to be used */ 302 #define HAL_OSPI_STATE_CMD_CFG ((uint32_t)0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */ 303 #define HAL_OSPI_STATE_READ_CMD_CFG ((uint32_t)0x00000014U) /*!< Read command configuration done, not the write command configuration */ 304 #define HAL_OSPI_STATE_WRITE_CMD_CFG ((uint32_t)0x00000024U) /*!< Write command configuration done, not the read command configuration */ 305 #define HAL_OSPI_STATE_BUSY_CMD ((uint32_t)0x00000008U) /*!< Command without data on-going */ 306 #define HAL_OSPI_STATE_BUSY_TX ((uint32_t)0x00000018U) /*!< Indirect Tx on-going */ 307 #define HAL_OSPI_STATE_BUSY_RX ((uint32_t)0x00000028U) /*!< Indirect Rx on-going */ 308 #define HAL_OSPI_STATE_BUSY_AUTO_POLLING ((uint32_t)0x00000048U) /*!< Auto-polling on-going */ 309 #define HAL_OSPI_STATE_BUSY_MEM_MAPPED ((uint32_t)0x00000088U) /*!< Memory-mapped on-going */ 310 #define HAL_OSPI_STATE_ABORT ((uint32_t)0x00000100U) /*!< Abort on-going */ 311 #define HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U) /*!< Blocking error, driver should be re-initialized */ 312 /** 313 * @} 314 */ 315 316 /** @defgroup OSPI_ErrorCode OSPI Error Code 317 * @{ 318 */ 319 #define HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 320 #define HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ 321 #define HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */ 322 #define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ 323 #define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ 324 #define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */ 325 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 326 #define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid callback error */ 327 #endif 328 /** 329 * @} 330 */ 331 332 /** @defgroup OSPI_DualQuad OSPI Dual-Quad 333 * @{ 334 */ 335 #define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */ 336 #define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */ 337 /** 338 * @} 339 */ 340 341 /** @defgroup OSPI_MemoryType OSPI Memory Type 342 * @{ 343 */ 344 #define HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U) /*!< Micron mode */ 345 #define HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */ 346 #if !defined(STM32L4R5xx)&&!defined(STM32L4R7xx)&&!defined(STM32L4R9xx)&&!defined(STM32L4S5xx)&&!defined(STM32L4S7xx)&&!defined(STM32L4S9xx) 347 #define HAL_OSPI_MEMTYPE_APMEMORY ((uint32_t)OCTOSPI_DCR1_MTYP_1) /*!< AP Memory mode */ 348 #endif 349 #define HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */ 350 #define HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */ 351 /** 352 * @} 353 */ 354 355 /** @defgroup OSPI_FreeRunningClock OSPI Free Running Clock 356 * @{ 357 */ 358 #define HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U) /*!< CLK is not free running */ 359 #define HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK) /*!< CLK is free running (always provided) */ 360 /** 361 * @} 362 */ 363 364 /** @defgroup OSPI_ClockMode OSPI Clock Mode 365 * @{ 366 */ 367 #define HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!< CLK must stay low while nCS is high */ 368 #define HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */ 369 /** 370 * @} 371 */ 372 373 /** @defgroup OSPI_WrapSize OSPI Wrap-Size 374 * @{ 375 */ 376 #define HAL_OSPI_WRAP_NOT_SUPPORTED ((uint32_t)0x00000000U) /*!< wrapped reads are not supported by the memory */ 377 #define HAL_OSPI_WRAP_16_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */ 378 #define HAL_OSPI_WRAP_32_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */ 379 #define HAL_OSPI_WRAP_64_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_2) /*!< external memory supports wrap size of 64 bytes */ 380 #define HAL_OSPI_WRAP_128_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */ 381 /** 382 * @} 383 */ 384 385 /** @defgroup OSPI_SampleShifting OSPI Sample Shifting 386 * @{ 387 */ 388 #define HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!< No shift */ 389 #define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */ 390 /** 391 * @} 392 */ 393 394 /** @defgroup OSPI_DelayHoldQuarterCycle OSPI Delay Hold Quarter Cycle 395 * @{ 396 */ 397 #define HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U) /*!< No Delay */ 398 #define HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */ 399 /** 400 * @} 401 */ 402 403 /** @defgroup OSPI_OperationType OSPI Operation Type 404 * @{ 405 */ 406 #define HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */ 407 #define HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U) /*!< Read configuration (memory-mapped mode) */ 408 #define HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U) /*!< Write configuration (memory-mapped mode) */ 409 /** 410 * @} 411 */ 412 413 /** @defgroup OSPI_FlashID OSPI Flash Id 414 * @{ 415 */ 416 #define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U) /*!< FLASH 1 selected */ 417 #define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL) /*!< FLASH 2 selected */ 418 /** 419 * @} 420 */ 421 422 /** @defgroup OSPI_InstructionMode OSPI Instruction Mode 423 * @{ 424 */ 425 #define HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!< No instruction */ 426 #define HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0) /*!< Instruction on a single line */ 427 #define HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1) /*!< Instruction on two lines */ 428 #define HAL_OSPI_INSTRUCTION_4_LINES ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1)) /*!< Instruction on four lines */ 429 #define HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2) /*!< Instruction on eight lines */ 430 /** 431 * @} 432 */ 433 434 /** @defgroup OSPI_InstructionSize OSPI Instruction Size 435 * @{ 436 */ 437 #define HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit instruction */ 438 #define HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0) /*!< 16-bit instruction */ 439 #define HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1) /*!< 24-bit instruction */ 440 #define HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE) /*!< 32-bit instruction */ 441 /** 442 * @} 443 */ 444 445 /** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode 446 * @{ 447 */ 448 #define HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for instruction phase */ 449 #define HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */ 450 /** 451 * @} 452 */ 453 454 /** @defgroup OSPI_AddressMode OSPI Address Mode 455 * @{ 456 */ 457 #define HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!< No address */ 458 #define HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0) /*!< Address on a single line */ 459 #define HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1) /*!< Address on two lines */ 460 #define HAL_OSPI_ADDRESS_4_LINES ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1)) /*!< Address on four lines */ 461 #define HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2) /*!< Address on eight lines */ 462 /** 463 * @} 464 */ 465 466 /** @defgroup OSPI_AddressSize OSPI Address Size 467 * @{ 468 */ 469 #define HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit address */ 470 #define HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0) /*!< 16-bit address */ 471 #define HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1) /*!< 24-bit address */ 472 #define HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE) /*!< 32-bit address */ 473 /** 474 * @} 475 */ 476 477 /** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode 478 * @{ 479 */ 480 #define HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for address phase */ 481 #define HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */ 482 /** 483 * @} 484 */ 485 486 /** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode 487 * @{ 488 */ 489 #define HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!< No alternate bytes */ 490 #define HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */ 491 #define HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */ 492 #define HAL_OSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */ 493 #define HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */ 494 /** 495 * @} 496 */ 497 498 /** @defgroup OSPI_AlternateBytesSize OSPI Alternate Bytes Size 499 * @{ 500 */ 501 #define HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit alternate bytes */ 502 #define HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */ 503 #define HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */ 504 #define HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */ 505 /** 506 * @} 507 */ 508 509 /** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode 510 * @{ 511 */ 512 #define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for alternate bytes phase */ 513 #define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */ 514 /** 515 * @} 516 */ 517 518 /** @defgroup OSPI_DataMode OSPI Data Mode 519 * @{ 520 */ 521 #define HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U) /*!< No data */ 522 #define HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0) /*!< Data on a single line */ 523 #define HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1) /*!< Data on two lines */ 524 #define HAL_OSPI_DATA_4_LINES ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1)) /*!< Data on four lines */ 525 #define HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2) /*!< Data on eight lines */ 526 /** 527 * @} 528 */ 529 530 /** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode 531 * @{ 532 */ 533 #define HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for data phase */ 534 #define HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */ 535 /** 536 * @} 537 */ 538 539 /** @defgroup OSPI_DQSMode OSPI DQS Mode 540 * @{ 541 */ 542 #define HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U) /*!< DQS disabled */ 543 #define HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE) /*!< DQS enabled */ 544 /** 545 * @} 546 */ 547 548 /** @defgroup OSPI_SIOOMode OSPI SIOO Mode 549 * @{ 550 */ 551 #define HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!< Send instruction on every transaction */ 552 #define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO) /*!< Send instruction only for the first command */ 553 /** 554 * @} 555 */ 556 557 /** @defgroup OSPI_WriteZeroLatency OSPI Hyperbus Write Zero Latency Activation 558 * @{ 559 */ 560 #define HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U) /*!< Latency on write accesses */ 561 #define HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL) /*!< No latency on write accesses */ 562 /** 563 * @} 564 */ 565 566 /** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode 567 * @{ 568 */ 569 #define HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U) /*!< Variable initial latency */ 570 #define HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM) /*!< Fixed latency */ 571 /** 572 * @} 573 */ 574 575 /** @defgroup OSPI_AddressSpace OSPI Hyperbus Address Space 576 * @{ 577 */ 578 #define HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U) /*!< HyperBus memory mode */ 579 #define HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */ 580 /** 581 * @} 582 */ 583 584 /** @defgroup OSPI_MatchMode OSPI Match Mode 585 * @{ 586 */ 587 #define HAL_OSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!< AND match mode between unmasked bits */ 588 #define HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bits */ 589 /** 590 * @} 591 */ 592 593 /** @defgroup OSPI_AutomaticStop OSPI Automatic Stop 594 * @{ 595 */ 596 #define HAL_OSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!< AutoPolling stops only with abort or OSPI disabling */ 597 #define HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */ 598 /** 599 * @} 600 */ 601 602 /** @defgroup OSPI_TimeOutActivation OSPI Timeout Activation 603 * @{ 604 */ 605 #define HAL_OSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!< Timeout counter disabled, nCS remains active */ 606 #define HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */ 607 /** 608 * @} 609 */ 610 611 /** @defgroup OSPI_Flags OSPI Flags 612 * @{ 613 */ 614 #define HAL_OSPI_FLAG_BUSY OCTOSPI_SR_BUSY /*!< Busy flag: operation is ongoing */ 615 #define HAL_OSPI_FLAG_TO OCTOSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */ 616 #define HAL_OSPI_FLAG_SM OCTOSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */ 617 #define HAL_OSPI_FLAG_FT OCTOSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */ 618 #define HAL_OSPI_FLAG_TC OCTOSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */ 619 #define HAL_OSPI_FLAG_TE OCTOSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */ 620 /** 621 * @} 622 */ 623 624 /** @defgroup OSPI_Interrupts OSPI Interrupts 625 * @{ 626 */ 627 #define HAL_OSPI_IT_TO OCTOSPI_CR_TOIE /*!< Interrupt on the timeout flag */ 628 #define HAL_OSPI_IT_SM OCTOSPI_CR_SMIE /*!< Interrupt on the status match flag */ 629 #define HAL_OSPI_IT_FT OCTOSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */ 630 #define HAL_OSPI_IT_TC OCTOSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */ 631 #define HAL_OSPI_IT_TE OCTOSPI_CR_TEIE /*!< Interrupt on the transfer error flag */ 632 /** 633 * @} 634 */ 635 636 /** @defgroup OSPI_Timeout_definition OSPI Timeout definition 637 * @{ 638 */ 639 #define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */ 640 /** 641 * @} 642 */ 643 644 /** @defgroup OSPIM_IOPort OSPI IO Manager IO Port 645 * @{ 646 */ 647 #define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U)) /*!< Port 1 - IO[3:0] */ 648 #define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U)) /*!< Port 1 - IO[7:4] */ 649 #define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U)) /*!< Port 2 - IO[3:0] */ 650 #define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U)) /*!< Port 2 - IO[7:4] */ 651 /** 652 * @} 653 */ 654 /** 655 * @} 656 */ 657 658 /* Exported macros -----------------------------------------------------------*/ 659 /** @defgroup OSPI_Exported_Macros OSPI Exported Macros 660 * @{ 661 */ 662 /** @brief Reset OSPI handle state. 663 * @param __HANDLE__ OSPI handle. 664 * @retval None 665 */ 666 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 667 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 668 (__HANDLE__)->State = HAL_OSPI_STATE_RESET; \ 669 (__HANDLE__)->MspInitCallback = NULL; \ 670 (__HANDLE__)->MspDeInitCallback = NULL; \ 671 } while(0) 672 #else 673 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET) 674 #endif 675 676 /** @brief Enable the OSPI peripheral. 677 * @param __HANDLE__ specifies the OSPI Handle. 678 * @retval None 679 */ 680 #define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) 681 682 /** @brief Disable the OSPI peripheral. 683 * @param __HANDLE__ specifies the OSPI Handle. 684 * @retval None 685 */ 686 #define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) 687 688 /** @brief Enable the specified OSPI interrupt. 689 * @param __HANDLE__ specifies the OSPI Handle. 690 * @param __INTERRUPT__ specifies the OSPI interrupt source to enable. 691 * This parameter can be one of the following values: 692 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 693 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 694 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 695 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 696 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 697 * @retval None 698 */ 699 #define __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 700 701 702 /** @brief Disable the specified OSPI interrupt. 703 * @param __HANDLE__ specifies the OSPI Handle. 704 * @param __INTERRUPT__ specifies the OSPI interrupt source to disable. 705 * This parameter can be one of the following values: 706 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 707 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 708 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 709 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 710 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 711 * @retval None 712 */ 713 #define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 714 715 /** @brief Check whether the specified OSPI interrupt source is enabled or not. 716 * @param __HANDLE__ specifies the OSPI Handle. 717 * @param __INTERRUPT__ specifies the OSPI interrupt source to check. 718 * This parameter can be one of the following values: 719 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 720 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 721 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 722 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 723 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 724 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 725 */ 726 #define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 727 728 /** 729 * @brief Check whether the selected OSPI flag is set or not. 730 * @param __HANDLE__ specifies the OSPI Handle. 731 * @param __FLAG__ specifies the OSPI flag to check. 732 * This parameter can be one of the following values: 733 * @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag 734 * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag 735 * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag 736 * @arg HAL_OSPI_FLAG_FT: OSPI FIFO threshold flag 737 * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag 738 * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag 739 * @retval None 740 */ 741 #define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) 742 743 /** @brief Clears the specified OSPI's flag status. 744 * @param __HANDLE__ specifies the OSPI Handle. 745 * @param __FLAG__ specifies the OSPI clear register flag that needs to be set 746 * This parameter can be one of the following values: 747 * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag 748 * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag 749 * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag 750 * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag 751 * @retval None 752 */ 753 #define __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 754 755 /** 756 * @} 757 */ 758 759 /* Exported functions --------------------------------------------------------*/ 760 /** @addtogroup OSPI_Exported_Functions 761 * @{ 762 */ 763 764 /* Initialization/de-initialization functions ********************************/ 765 /** @addtogroup OSPI_Exported_Functions_Group1 766 * @{ 767 */ 768 HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi); 769 void HAL_OSPI_MspInit (OSPI_HandleTypeDef *hospi); 770 HAL_StatusTypeDef HAL_OSPI_DeInit (OSPI_HandleTypeDef *hospi); 771 void HAL_OSPI_MspDeInit (OSPI_HandleTypeDef *hospi); 772 773 /** 774 * @} 775 */ 776 777 /* IO operation functions *****************************************************/ 778 /** @addtogroup OSPI_Exported_Functions_Group2 779 * @{ 780 */ 781 /* OSPI IRQ handler function */ 782 void HAL_OSPI_IRQHandler (OSPI_HandleTypeDef *hospi); 783 784 /* OSPI command configuration functions */ 785 HAL_StatusTypeDef HAL_OSPI_Command (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout); 786 HAL_StatusTypeDef HAL_OSPI_Command_IT (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); 787 HAL_StatusTypeDef HAL_OSPI_HyperbusCfg (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout); 788 HAL_StatusTypeDef HAL_OSPI_HyperbusCmd (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout); 789 790 /* OSPI indirect mode functions */ 791 HAL_StatusTypeDef HAL_OSPI_Transmit (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); 792 HAL_StatusTypeDef HAL_OSPI_Receive (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); 793 HAL_StatusTypeDef HAL_OSPI_Transmit_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData); 794 HAL_StatusTypeDef HAL_OSPI_Receive_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData); 795 HAL_StatusTypeDef HAL_OSPI_Transmit_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData); 796 HAL_StatusTypeDef HAL_OSPI_Receive_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData); 797 798 /* OSPI status flag polling mode functions */ 799 HAL_StatusTypeDef HAL_OSPI_AutoPolling (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 800 HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg); 801 802 /* OSPI memory-mapped mode functions */ 803 HAL_StatusTypeDef HAL_OSPI_MemoryMapped (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg); 804 805 /* Callback functions in non-blocking modes ***********************************/ 806 void HAL_OSPI_ErrorCallback (OSPI_HandleTypeDef *hospi); 807 void HAL_OSPI_AbortCpltCallback (OSPI_HandleTypeDef *hospi); 808 void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi); 809 810 /* OSPI indirect mode functions */ 811 void HAL_OSPI_CmdCpltCallback (OSPI_HandleTypeDef *hospi); 812 void HAL_OSPI_RxCpltCallback (OSPI_HandleTypeDef *hospi); 813 void HAL_OSPI_TxCpltCallback (OSPI_HandleTypeDef *hospi); 814 void HAL_OSPI_RxHalfCpltCallback (OSPI_HandleTypeDef *hospi); 815 void HAL_OSPI_TxHalfCpltCallback (OSPI_HandleTypeDef *hospi); 816 817 /* OSPI status flag polling mode functions */ 818 void HAL_OSPI_StatusMatchCallback (OSPI_HandleTypeDef *hospi); 819 820 /* OSPI memory-mapped mode functions */ 821 void HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi); 822 823 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 824 /* OSPI callback registering/unregistering */ 825 HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback); 826 HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID); 827 #endif 828 /** 829 * @} 830 */ 831 832 /* Peripheral Control and State functions ************************************/ 833 /** @addtogroup OSPI_Exported_Functions_Group3 834 * @{ 835 */ 836 HAL_StatusTypeDef HAL_OSPI_Abort (OSPI_HandleTypeDef *hospi); 837 HAL_StatusTypeDef HAL_OSPI_Abort_IT (OSPI_HandleTypeDef *hospi); 838 HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold (OSPI_HandleTypeDef *hospi, uint32_t Threshold); 839 uint32_t HAL_OSPI_GetFifoThreshold (OSPI_HandleTypeDef *hospi); 840 HAL_StatusTypeDef HAL_OSPI_SetTimeout (OSPI_HandleTypeDef *hospi, uint32_t Timeout); 841 uint32_t HAL_OSPI_GetError (OSPI_HandleTypeDef *hospi); 842 uint32_t HAL_OSPI_GetState (OSPI_HandleTypeDef *hospi); 843 844 /** 845 * @} 846 */ 847 848 /* OSPI IO Manager configuration function ************************************/ 849 /** @addtogroup OSPI_Exported_Functions_Group4 850 * @{ 851 */ 852 HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout); 853 854 /** 855 * @} 856 */ 857 858 /** 859 * @} 860 */ 861 /* End of exported functions -------------------------------------------------*/ 862 863 /* Private macros ------------------------------------------------------------*/ 864 /** 865 @cond 0 866 */ 867 #define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1U) && ((THRESHOLD) <= 32U)) 868 869 #define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \ 870 ((MODE) == HAL_OSPI_DUALQUAD_ENABLE)) 871 872 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 873 #define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ 874 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ 875 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \ 876 ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) 877 #else 878 #define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ 879 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ 880 ((TYPE) == HAL_OSPI_MEMTYPE_APMEMORY) || \ 881 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \ 882 ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) 883 #endif 884 885 #define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U)) 886 887 #define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 8U)) 888 889 #define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \ 890 ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE)) 891 892 #define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \ 893 ((MODE) == HAL_OSPI_CLOCK_MODE_3)) 894 895 #define IS_OSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_OSPI_WRAP_NOT_SUPPORTED) || \ 896 ((SIZE) == HAL_OSPI_WRAP_16_BYTES) || \ 897 ((SIZE) == HAL_OSPI_WRAP_32_BYTES) || \ 898 ((SIZE) == HAL_OSPI_WRAP_64_BYTES) || \ 899 ((SIZE) == HAL_OSPI_WRAP_128_BYTES)) 900 901 #define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 256U)) 902 903 #define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \ 904 ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE)) 905 906 #define IS_OSPI_DHQC(CYCLE) (((CYCLE) == HAL_OSPI_DHQC_DISABLE) || \ 907 ((CYCLE) == HAL_OSPI_DHQC_ENABLE)) 908 909 #define IS_OSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \ 910 ((TYPE) == HAL_OSPI_OPTYPE_READ_CFG) || \ 911 ((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG)) 912 913 #define IS_OSPI_FLASH_ID(FLASHID) (((FLASHID) == HAL_OSPI_FLASH_ID_1) || \ 914 ((FLASHID) == HAL_OSPI_FLASH_ID_2)) 915 916 #define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \ 917 ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \ 918 ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \ 919 ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \ 920 ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES)) 921 922 #define IS_OSPI_INSTRUCTION_SIZE(SIZE) (((SIZE) == HAL_OSPI_INSTRUCTION_8_BITS) || \ 923 ((SIZE) == HAL_OSPI_INSTRUCTION_16_BITS) || \ 924 ((SIZE) == HAL_OSPI_INSTRUCTION_24_BITS) || \ 925 ((SIZE) == HAL_OSPI_INSTRUCTION_32_BITS)) 926 927 #define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \ 928 ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) 929 930 #define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \ 931 ((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \ 932 ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \ 933 ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \ 934 ((MODE) == HAL_OSPI_ADDRESS_8_LINES)) 935 936 #define IS_OSPI_ADDRESS_SIZE(SIZE) (((SIZE) == HAL_OSPI_ADDRESS_8_BITS) || \ 937 ((SIZE) == HAL_OSPI_ADDRESS_16_BITS) || \ 938 ((SIZE) == HAL_OSPI_ADDRESS_24_BITS) || \ 939 ((SIZE) == HAL_OSPI_ADDRESS_32_BITS)) 940 941 #define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \ 942 ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE)) 943 944 #define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \ 945 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \ 946 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \ 947 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \ 948 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES)) 949 950 #define IS_OSPI_ALT_BYTES_SIZE(SIZE) (((SIZE) == HAL_OSPI_ALTERNATE_BYTES_8_BITS) || \ 951 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_16_BITS) || \ 952 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_24_BITS) || \ 953 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_32_BITS)) 954 955 #define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \ 956 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE)) 957 958 #define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \ 959 ((MODE) == HAL_OSPI_DATA_1_LINE) || \ 960 ((MODE) == HAL_OSPI_DATA_2_LINES) || \ 961 ((MODE) == HAL_OSPI_DATA_4_LINES) || \ 962 ((MODE) == HAL_OSPI_DATA_8_LINES)) 963 964 #define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1U) 965 966 #define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \ 967 ((MODE) == HAL_OSPI_DATA_DTR_ENABLE)) 968 969 #define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U) 970 971 #define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \ 972 ((MODE) == HAL_OSPI_DQS_ENABLE)) 973 974 #define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \ 975 ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD)) 976 977 #define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255U) 978 979 #define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255U) 980 981 #define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \ 982 ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE)) 983 984 #define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \ 985 ((MODE) == HAL_OSPI_FIXED_LATENCY)) 986 987 #define IS_OSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_OSPI_MEMORY_ADDRESS_SPACE) || \ 988 ((SPACE) == HAL_OSPI_REGISTER_ADDRESS_SPACE)) 989 990 #define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \ 991 ((MODE) == HAL_OSPI_MATCH_MODE_OR)) 992 993 #define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \ 994 ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE)) 995 996 #define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU) 997 998 #define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 999 1000 #define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \ 1001 ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)) 1002 1003 #define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 1004 1005 #define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U) 1006 1007 #define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 2U)) 1008 1009 #define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \ 1010 ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \ 1011 ((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \ 1012 ((PORT) == HAL_OSPIM_IOPORT_2_HIGH)) 1013 1014 #if defined (OCTOSPIM_CR_MUXEN) 1015 #define IS_OSPIM_REQ2ACKTIME(TIME) ((TIME >= 1) && (TIME <= 256)) 1016 #endif 1017 /** 1018 @endcond 1019 */ 1020 1021 /* End of private macros -----------------------------------------------------*/ 1022 1023 /** 1024 * @} 1025 */ 1026 1027 /** 1028 * @} 1029 */ 1030 1031 #endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */ 1032 1033 #ifdef __cplusplus 1034 } 1035 #endif 1036 1037 #endif /* STM32L4xx_HAL_OSPI_H */ 1038 1039 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1040