1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2010-2015, Intel Corporation. 5 */ 6 7 #ifndef __INPUT_SYSTEM_2400_LOCAL_H_INCLUDED__ 8 #define __INPUT_SYSTEM_2400_LOCAL_H_INCLUDED__ 9 10 #include "input_system_defs.h" /* HIVE_ISYS_GPREG_MULTICAST_A_IDX,... */ 11 12 /* 13 * _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX, 14 * _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX,... 15 */ 16 #include "css_receiver_2400_defs.h" 17 18 #include "isp_capture_defs.h" 19 20 #include "isp_acquisition_defs.h" 21 #include "input_system_ctrl_defs.h" 22 23 struct target_cfg2400_s { 24 input_switch_cfg_channel_t input_switch_channel_cfg; 25 target_isp_cfg_t target_isp_cfg; 26 target_sp_cfg_t target_sp_cfg; 27 target_strm2mem_cfg_t target_strm2mem_cfg; 28 }; 29 30 // Configuration of a channel. 31 struct channel_cfg_s { 32 u32 ch_id; 33 backend_channel_cfg_t backend_ch; 34 input_system_source_t source_type; 35 source_cfg_t source_cfg; 36 target_cfg2400_t target_cfg; 37 }; 38 39 // Complete configuration for input system. 40 struct input_system_cfg2400_s { 41 input_system_source_t source_type; 42 input_system_config_flags_t source_type_flags; 43 //channel_cfg_t channel[N_CHANNELS]; 44 input_system_config_flags_t ch_flags[N_CHANNELS]; 45 // This is the place where the buffers' settings are collected, as given. 46 csi_cfg_t csi_value[N_CSI_PORTS]; 47 input_system_config_flags_t csi_flags[N_CSI_PORTS]; 48 49 // Possible another struct for ib. 50 // This buffers set at the end, based on the all configurations. 51 isp2400_ib_buffer_t csi_buffer[N_CSI_PORTS]; 52 input_system_config_flags_t csi_buffer_flags[N_CSI_PORTS]; 53 isp2400_ib_buffer_t acquisition_buffer_unique; 54 input_system_config_flags_t acquisition_buffer_unique_flags; 55 u32 unallocated_ib_mem_words; // Used for check.DEFAULT = IB_CAPACITY_IN_WORDS. 56 //uint32_t acq_allocated_ib_mem_words; 57 58 input_system_connection_t multicast[N_CSI_PORTS]; 59 input_system_multiplex_t multiplexer; 60 input_system_config_flags_t multiplexer_flags; 61 62 tpg_cfg_t tpg_value; 63 input_system_config_flags_t tpg_flags; 64 prbs_cfg_t prbs_value; 65 input_system_config_flags_t prbs_flags; 66 gpfifo_cfg_t gpfifo_value; 67 input_system_config_flags_t gpfifo_flags; 68 69 input_switch_cfg_t input_switch_cfg; 70 71 target_isp_cfg_t target_isp[N_CHANNELS]; 72 input_system_config_flags_t target_isp_flags[N_CHANNELS]; 73 target_sp_cfg_t target_sp[N_CHANNELS]; 74 input_system_config_flags_t target_sp_flags[N_CHANNELS]; 75 target_strm2mem_cfg_t target_strm2mem[N_CHANNELS]; 76 input_system_config_flags_t target_strm2mem_flags[N_CHANNELS]; 77 78 input_system_config_flags_t session_flags; 79 80 }; 81 82 /* 83 * For each MIPI port 84 */ 85 #define _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX _HRT_CSS_RECEIVER_2400_DEVICE_READY_REG_IDX 86 #define _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX _HRT_CSS_RECEIVER_2400_IRQ_STATUS_REG_IDX 87 #define _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX _HRT_CSS_RECEIVER_2400_IRQ_ENABLE_REG_IDX 88 #define _HRT_CSS_RECEIVER_TIMEOUT_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX 89 #define _HRT_CSS_RECEIVER_INIT_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX 90 /* new regs for each MIPI port w.r.t. 2300 */ 91 #define _HRT_CSS_RECEIVER_RAW16_18_DATAID_REG_IDX _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_REG_IDX 92 #define _HRT_CSS_RECEIVER_SYNC_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX 93 #define _HRT_CSS_RECEIVER_RX_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX 94 95 /* _HRT_CSS_RECEIVER_2400_COMP_FORMAT_REG_IDX is not defined per MIPI port but per channel */ 96 /* _HRT_CSS_RECEIVER_2400_COMP_PREDICT_REG_IDX is not defined per MIPI port but per channel */ 97 #define _HRT_CSS_RECEIVER_FS_TO_LS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_FS_TO_LS_DELAY_REG_IDX 98 #define _HRT_CSS_RECEIVER_LS_TO_DATA_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LS_TO_DATA_DELAY_REG_IDX 99 #define _HRT_CSS_RECEIVER_DATA_TO_LE_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_DATA_TO_LE_DELAY_REG_IDX 100 #define _HRT_CSS_RECEIVER_LE_TO_FE_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX 101 #define _HRT_CSS_RECEIVER_FE_TO_FS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_FE_TO_FS_DELAY_REG_IDX 102 #define _HRT_CSS_RECEIVER_LE_TO_LS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LE_TO_LS_DELAY_REG_IDX 103 #define _HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX 104 #define _HRT_CSS_RECEIVER_BACKEND_RST_REG_IDX _HRT_CSS_RECEIVER_2400_BACKEND_RST_REG_IDX 105 #define _HRT_CSS_RECEIVER_RAW18_REG_IDX _HRT_CSS_RECEIVER_2400_RAW18_REG_IDX 106 #define _HRT_CSS_RECEIVER_FORCE_RAW8_REG_IDX _HRT_CSS_RECEIVER_2400_FORCE_RAW8_REG_IDX 107 #define _HRT_CSS_RECEIVER_RAW16_REG_IDX _HRT_CSS_RECEIVER_2400_RAW16_REG_IDX 108 109 /* Previously MIPI port regs, now 2x2 logical channel regs */ 110 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC0_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX 111 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC0_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX 112 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC1_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX 113 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC1_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX 114 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC2_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX 115 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC2_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX 116 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC3_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX 117 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC3_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX 118 119 /* Second backend is at offset 0x0700 w.r.t. the first port at offset 0x0100 */ 120 #define _HRT_CSS_BE_OFFSET 448 121 #define _HRT_CSS_RECEIVER_BE_GSP_ACC_OVL_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_GSP_ACC_OVL_REG_IDX + _HRT_CSS_BE_OFFSET) 122 #define _HRT_CSS_RECEIVER_BE_SRST_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_SRST_REG_IDX + _HRT_CSS_BE_OFFSET) 123 #define _HRT_CSS_RECEIVER_BE_TWO_PPC_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_TWO_PPC_REG_IDX + _HRT_CSS_BE_OFFSET) 124 #define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG0_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG0_IDX + _HRT_CSS_BE_OFFSET) 125 #define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG1_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG1_IDX + _HRT_CSS_BE_OFFSET) 126 #define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG2_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG2_IDX + _HRT_CSS_BE_OFFSET) 127 #define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG3_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG3_IDX + _HRT_CSS_BE_OFFSET) 128 #define _HRT_CSS_RECEIVER_BE_SEL_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_SEL_REG_IDX + _HRT_CSS_BE_OFFSET) 129 #define _HRT_CSS_RECEIVER_BE_RAW16_CONFIG_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_RAW16_CONFIG_REG_IDX + _HRT_CSS_BE_OFFSET) 130 #define _HRT_CSS_RECEIVER_BE_RAW18_CONFIG_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_RAW18_CONFIG_REG_IDX + _HRT_CSS_BE_OFFSET) 131 #define _HRT_CSS_RECEIVER_BE_FORCE_RAW8_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_FORCE_RAW8_REG_IDX + _HRT_CSS_BE_OFFSET) 132 #define _HRT_CSS_RECEIVER_BE_IRQ_STATUS_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_IRQ_STATUS_REG_IDX + _HRT_CSS_BE_OFFSET) 133 #define _HRT_CSS_RECEIVER_BE_IRQ_CLEAR_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_IRQ_CLEAR_REG_IDX + _HRT_CSS_BE_OFFSET) 134 135 #define _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_BIT 136 #define _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_BIT 137 #define _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_BIT 138 #define _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_BIT 139 #define _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_BIT 140 #define _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_BIT 141 #define _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_BIT 142 #define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_BIT 143 #define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_BIT 144 #define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_BIT 145 #define _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT 146 #define _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_BIT 147 #define _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_BIT 148 #define _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_BIT 149 #define _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_BIT 150 #define _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_BIT 151 #define _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_BIT 152 153 #define _HRT_CSS_RECEIVER_FUNC_PROG_REG_IDX _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX 154 #define _HRT_CSS_RECEIVER_DATA_TIMEOUT_IDX _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX 155 #define _HRT_CSS_RECEIVER_DATA_TIMEOUT_BITS _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS 156 157 typedef enum { 158 MIPI_FORMAT_2400_RGB888 = 0, 159 MIPI_FORMAT_2400_RGB555, 160 MIPI_FORMAT_2400_RGB444, 161 MIPI_FORMAT_2400_RGB565, 162 MIPI_FORMAT_2400_RGB666, 163 MIPI_FORMAT_2400_RAW8, /* 5 */ 164 MIPI_FORMAT_2400_RAW10, 165 MIPI_FORMAT_2400_RAW6, 166 MIPI_FORMAT_2400_RAW7, 167 MIPI_FORMAT_2400_RAW12, 168 MIPI_FORMAT_2400_RAW14, /* 10 */ 169 MIPI_FORMAT_2400_YUV420_8, 170 MIPI_FORMAT_2400_YUV420_10, 171 MIPI_FORMAT_2400_YUV422_8, 172 MIPI_FORMAT_2400_YUV422_10, 173 MIPI_FORMAT_2400_CUSTOM0, /* 15 */ 174 MIPI_FORMAT_2400_YUV420_8_LEGACY, 175 MIPI_FORMAT_2400_EMBEDDED, 176 MIPI_FORMAT_2400_CUSTOM1, 177 MIPI_FORMAT_2400_CUSTOM2, 178 MIPI_FORMAT_2400_CUSTOM3, /* 20 */ 179 MIPI_FORMAT_2400_CUSTOM4, 180 MIPI_FORMAT_2400_CUSTOM5, 181 MIPI_FORMAT_2400_CUSTOM6, 182 MIPI_FORMAT_2400_CUSTOM7, 183 MIPI_FORMAT_2400_YUV420_8_SHIFT, /* 25 */ 184 MIPI_FORMAT_2400_YUV420_10_SHIFT, 185 MIPI_FORMAT_2400_RAW16, 186 MIPI_FORMAT_2400_RAW18, 187 N_MIPI_FORMAT_2400, 188 } mipi_format_2400_t; 189 190 #define N_MIPI_FORMAT_CUSTOM 8 191 192 /* The number of stores for compressed format types */ 193 #define N_MIPI_COMPRESSOR_CONTEXT (N_RX_CHANNEL_ID * N_MIPI_FORMAT_CUSTOM) 194 195 typedef enum { 196 RX_IRQ_INFO_BUFFER_OVERRUN = 1UL << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT, 197 RX_IRQ_INFO_INIT_TIMEOUT = 1UL << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT, 198 RX_IRQ_INFO_ENTER_SLEEP_MODE = 1UL << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT, 199 RX_IRQ_INFO_EXIT_SLEEP_MODE = 1UL << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT, 200 RX_IRQ_INFO_ECC_CORRECTED = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT, 201 RX_IRQ_INFO_ERR_SOT = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT, 202 RX_IRQ_INFO_ERR_SOT_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT, 203 RX_IRQ_INFO_ERR_CONTROL = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT, 204 RX_IRQ_INFO_ERR_ECC_DOUBLE = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT, 205 /* RX_IRQ_INFO_NO_ERR = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT, */ 206 RX_IRQ_INFO_ERR_CRC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT, 207 RX_IRQ_INFO_ERR_UNKNOWN_ID = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT, 208 RX_IRQ_INFO_ERR_FRAME_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT, 209 RX_IRQ_INFO_ERR_FRAME_DATA = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT, 210 RX_IRQ_INFO_ERR_DATA_TIMEOUT = 1UL << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT, 211 RX_IRQ_INFO_ERR_UNKNOWN_ESC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT, 212 RX_IRQ_INFO_ERR_LINE_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT, 213 } rx_irq_info_t; 214 215 /* NOTE: The base has already an offset of 0x0100 */ 216 static const hrt_address __maybe_unused MIPI_PORT_OFFSET[N_MIPI_PORT_ID] = { 217 0x00000000UL, 218 0x00000100UL, 219 0x00000200UL 220 }; 221 222 static const hrt_address __maybe_unused SUB_SYSTEM_OFFSET[N_SUB_SYSTEM_ID] = { 223 0x00001000UL, 224 0x00002000UL, 225 0x00003000UL, 226 0x00004000UL, 227 0x00005000UL, 228 0x00009000UL, 229 0x0000A000UL, 230 0x0000B000UL, 231 0x0000C000UL 232 }; 233 234 #endif /* __INPUT_SYSTEM_LOCAL_H_INCLUDED__ */ 235