1package xiangshan.backend.fu.vector 2 3import chisel3._ 4import xiangshan.backend.fu.vector.Bundles.VSew 5import yunsuan.OpType 6import yunsuan.encoding.{VdType, Vs1IntType, Vs2IntType} 7 8class VecSrcTypeModuleIO extends Bundle { 9 val in = Input(new Bundle { 10 val fuOpType : UInt = OpType() 11 val vsew : UInt = VSew() 12 val isReverse : Bool = Bool() // vrsub, vrdiv 13 val isExt : Bool = Bool() 14 val isDstMask : Bool = Bool() // vvm, vvvm, mmm 15 val isMove : Bool = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 16 }) 17 val out = Output(new Bundle { 18 val vs1Type : UInt = Vs1IntType() 19 val vs2Type : UInt = Vs2IntType() 20 val vdType : UInt = VdType() 21 val illegal : Bool = Bool() 22 }) 23} 24 25abstract class VecSrcTypeModule extends Module { 26 val io = IO(new VecSrcTypeModuleIO) 27 28 protected val fuOpType = io.in.fuOpType 29 protected val vsew = io.in.vsew 30 protected val isExt = io.in.isExt 31 protected val isDstMask = io.in.isDstMask 32} 33