1 /* 2 * Copyright (c) 2020-2021, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file encode_avc_huc_brc_update_packet.h 24 //! \brief Defines the implementation of avc huc update packet 25 //! 26 27 #ifndef __CODECHAL_AVC_HUC_BRC_UPDATE_PACKET_H__ 28 #define __CODECHAL_AVC_HUC_BRC_UPDATE_PACKET_H__ 29 30 #include "encode_huc.h" 31 #if _ENCODE_RESERVED 32 #include "encode_avc_huc_brc_update_packet_ext.h" 33 #endif // _ENCODE_RESERVED 34 35 namespace encode 36 { 37 38 class AvcBasicFeature; 39 class AvcEncodeBRC; 40 41 struct VdencAvcHucBrcUpdateDmem 42 { 43 uint8_t BRCFunc_U8; // =1 for Update, other values are reserved for future use 44 uint8_t RSVD[3]; 45 uint32_t UPD_TARGETSIZE_U32; // refer to AVC BRC for calculation 46 uint32_t UPD_FRAMENUM_U32; // frame number 47 uint32_t UPD_PeakTxBitsPerFrame_U32; // current global target bits - previous global target bits (global target bits += input bits per frame) 48 uint32_t UPD_FrameBudget_U32; // target time counter 49 uint32_t FrameByteCount; // PAK output via MMIO 50 uint32_t TimingBudgetOverflow; // PAK output via MMIO 51 uint32_t ImgStatusCtrl; // PAK output via MMIO 52 uint32_t IPCMNonConformant; // PAK output via MMIO 53 54 uint16_t UPD_startGAdjFrame_U16[4]; // 10, 50, 100, 150 55 uint16_t UPD_MBBudget_U16[52]; // MB bugdet for QP 0 - 51. 56 uint16_t UPD_SLCSZ_TARGETSLCSZ_U16; // target slice size 57 uint16_t UPD_SLCSZ_UPD_THRDELTAI_U16[42]; // slice size threshold delta for I frame 58 uint16_t UPD_SLCSZ_UPD_THRDELTAP_U16[42]; // slice size threshold delta for P frame 59 uint16_t UPD_NumOfFramesSkipped_U16; // Recording how many frames have been skipped. 60 uint16_t UPD_SkipFrameSize_U16; // Recording the skip frame size for one frame. =NumMBs * 1, assuming one bit per mb for skip frame. 61 uint16_t UPD_StaticRegionPct_U16; // One entry, recording the percentage of static region 62 uint8_t UPD_gRateRatioThreshold_U8[7]; // 80,95,99,101,105,125,160 63 uint8_t UPD_CurrFrameType_U8; // Use AvcBrcFrameType enum to specify frame type 64 uint8_t UPD_startGAdjMult_U8[5]; // 1, 1, 3, 2, 1 65 uint8_t UPD_startGAdjDiv_U8[5]; // 40, 5, 5, 3, 1 66 uint8_t UPD_gRateRatioThresholdQP_U8[8]; // 253,254,255,0,1,1,2,3 67 uint8_t UPD_PAKPassNum_U8; // current pak pass number 68 uint8_t UPD_MaxNumPass_U8; // 2 69 uint8_t UPD_SceneChgWidth_U8[2]; // set both to MIN((NumP + 1) / 5, 6) 70 uint8_t UPD_SceneChgDetectEn_U8; // Enable scene change detection 71 uint8_t UPD_SceneChgPrevIntraPctThreshold_U8; // =96. scene change previous intra percentage threshold 72 uint8_t UPD_SceneChgCurIntraPctThreshold_U8; // =192. scene change current intra percentage threshold 73 uint8_t UPD_IPAverageCoeff_U8; // lowdelay ? 0 : 128 74 uint8_t UPD_MinQpAdjustment_U8; // Minimum QP increase step 75 uint8_t UPD_TimingBudgetCheck_U8; // Flag indicating if kernel will check timing budget. 76 int8_t reserved_I8[4]; // must be zero 77 uint8_t UPD_CQP_QpValue_U8; // Application specified target QP in BRC_ICQ mode 78 uint8_t UPD_CQP_FracQp_U8; // Application specified fine position in BRC_ICQ mode 79 uint8_t UPD_HMEDetectionEnable_U8; // 0: default, 1: HuC BRC kernel requires information from HME detection kernel output 80 uint8_t UPD_HMECostEnable_U8; // 0: default, 1: driver provides HME cost table 81 uint8_t UPD_DisablePFrame8x8Transform_U8; // 0: enable, 1: disable 82 uint8_t RSVD3; // must be zero 83 uint8_t UPD_ROISource_U8; // =0: disable, 1: ROIMap from HME Static Region or from App dirty rectangle, 2: ROIMap from App 84 uint8_t RSVD4; // must be zero 85 uint16_t UPD_TargetSliceSize_U16; // default: 1498, max target slice size from app DDI 86 uint16_t UPD_MaxNumSliceAllowed_U16; // computed by driver based on level idc 87 uint16_t UPD_SLBB_Size_U16; // second level batch buffer (SLBB) size in bytes, the input buffer will contain two SLBBs A and B, A followed by B, A and B have the same structure. 88 uint16_t UPD_SLBB_B_Offset_U16; // offset in bytes from the beginning of the input buffer, it points to the start of SLBB B, set by driver for skip frame support 89 uint16_t UPD_AvcImgStateOffset_U16; // offset in bytes from the beginning of SLBB A 90 uint16_t reserved_u16; 91 uint32_t NumOfSlice; // PAK output via MMIO 92 93 // HME distortion based QP adjustment 94 uint16_t AveHmeDist_U16; // default: 0, in HME detection kernel output 95 uint8_t HmeDistAvailable_U8; // 0: disabled, 1: enabled 96 uint8_t DisableDMA; // default =0, use DMA data transfer; =1, use regular region read/write 97 uint16_t AdditionalFrameSize_U16; // for slice size control improvement 98 uint8_t AddNALHeaderSizeInternally_U8; 99 uint8_t UPD_RoiQpViaForceQp_U8; // HuC does not update StreamIn Buffer, 1: HuC updates StreamIn Buffer 100 uint32_t CABACZeroInsertionSize_U32; // PAK output via MMIO 101 uint32_t MiniFramePaddingSize_U32; // PAK output via MMIO 102 uint16_t UPD_WidthInMB_U16; // width in MB 103 uint16_t UPD_HeightInMB_U16; // height in MB 104 int8_t UPD_ROIQpDelta_I8[8]; // Application specified ROI QP Adjustment for Zone0, Zone1, Zone2 and Zone3, Zone4, Zone5, Zone6 and Zone7. 105 106 //HME--Offset values need to be a multiple of 4 in order to be aligned to the 4x4 HME block for downscaled 4X HME precision and HME--Offset range is [-128,127] 107 int8_t HME0XOffset_I8; // default = 32, Frame level X offset from the co-located (0, 0) location for HME0. 108 int8_t HME0YOffset_I8; // default = 24, Frame level Y offset from the co-located (0, 0) location for HME0. 109 int8_t HME1XOffset_I8; // default = -32, Frame level X offset from the co-located (0, 0) location for HME1. 110 int8_t HME1YOffset_I8; // default = -24, Frame level Y offset from the co-located (0, 0) location for HME1. 111 uint8_t MOTION_ADAPTIVE_G4; 112 uint8_t EnableLookAhead; 113 uint8_t UPD_LA_Data_Offset_U8; 114 uint8_t UPD_CQMEnabled_U8; // 0 indicates CQM is disabled for current frame; otherwise CQM is enabled. 115 uint32_t UPD_LA_TargetSize_U32; // target frame size in lookahead BRC (if EnableLookAhead == 1) or TCBRC mode. If zero, lookahead BRC or TCBRC is disabled. 116 uint32_t UPD_LA_TargetFulness_U32; // target VBV buffer fulness in lookahead BRC mode (if EnableLookAhead == 1). 117 uint8_t UPD_Delta_U8; // delta QP of pyramid 118 uint8_t UPD_ROM_CURRENT_U8; // ROM average of current frame 119 uint8_t UPD_ROM_ZERO_U8; // ROM zero percentage (255 is 100%) 120 uint8_t UPD_TCBRC_SCENARIO_U8; 121 uint8_t UPD_EnableFineGrainLA; 122 int8_t UPD_DeltaQpDcOffset; 123 uint16_t UPD_NumSlicesForRounding; 124 uint32_t UPD_UserMaxFramePB; // In Bytes 125 uint8_t UPD_ExtCurrFrameType; // correctly calculated FrameType for all cases (including hierarchy golden BGops) 126 uint8_t RSVD2[3]; 127 }; 128 129 struct VdencAvcHucBrcConstantData 130 { 131 uint8_t UPD_GlobalRateQPAdjTabI_U8[64]; 132 uint8_t UPD_GlobalRateQPAdjTabP_U8[64]; 133 uint8_t UPD_GlobalRateQPAdjTabB_U8[64]; 134 uint8_t UPD_DistThreshldI_U8[10]; 135 uint8_t UPD_DistThreshldP_U8[10]; 136 uint8_t UPD_DistThreshldB_U8[10]; 137 uint8_t UPD_DistQPAdjTabI_U8[81]; 138 uint8_t UPD_DistQPAdjTabP_U8[81]; 139 uint8_t UPD_DistQPAdjTabB_U8[81]; 140 int8_t UPD_BufRateAdjTabI_S8[72]; 141 int8_t UPD_BufRateAdjTabP_S8[72]; 142 int8_t UPD_BufRateAdjTabB_S8[72]; 143 uint8_t UPD_FrmSzMinTabP_U8[9]; 144 uint8_t UPD_FrmSzMinTabB_U8[9]; 145 uint8_t UPD_FrmSzMinTabI_U8[9]; 146 uint8_t UPD_FrmSzMaxTabP_U8[9]; 147 uint8_t UPD_FrmSzMaxTabB_U8[9]; 148 uint8_t UPD_FrmSzMaxTabI_U8[9]; 149 uint8_t UPD_FrmSzSCGTabP_U8[9]; 150 uint8_t UPD_FrmSzSCGTabB_U8[9]; 151 uint8_t UPD_FrmSzSCGTabI_U8[9]; 152 // Cost Table 14*42 = 588 bytes 153 uint8_t UPD_I_IntraNonPred[42]; 154 uint8_t UPD_I_Intra16x16[42]; 155 uint8_t UPD_I_Intra8x8[42]; 156 uint8_t UPD_I_Intra4x4[42]; 157 uint8_t UPD_I_IntraChroma[42]; 158 uint8_t UPD_P_IntraNonPred[42]; 159 uint8_t UPD_P_Intra16x16[42]; 160 uint8_t UPD_P_Intra8x8[42]; 161 uint8_t UPD_P_Intra4x4[42]; 162 uint8_t UPD_P_IntraChroma[42]; 163 uint8_t UPD_P_Inter16x8[42]; 164 uint8_t UPD_P_Inter8x8[42]; 165 uint8_t UPD_P_Inter16x16[42]; 166 uint8_t UPD_P_RefId[42]; 167 uint8_t VdencAvcHucBrcConstantData_0[8][42]; 168 uint8_t VdencAvcHucBrcConstantData_1[42]; 169 uint16_t VdencAvcHucBrcConstantData_2[42]; 170 uint16_t VdencAvcHucBrcConstantData_3[42]; 171 uint8_t VdencAvcHucBrcConstantData_4[42]; 172 uint8_t VdencAvcHucBrcConstantData_5[42]; 173 }; 174 175 class AvcHucBrcUpdatePkt : public EncodeHucPkt 176 { 177 public: AvcHucBrcUpdatePkt(MediaPipeline * pipeline,MediaTask * task,CodechalHwInterfaceNext * hwInterface)178 AvcHucBrcUpdatePkt(MediaPipeline *pipeline, MediaTask *task, CodechalHwInterfaceNext *hwInterface) : 179 EncodeHucPkt(pipeline, task, hwInterface) {} 180 ~AvcHucBrcUpdatePkt()181 virtual ~AvcHucBrcUpdatePkt() {} 182 183 virtual MOS_STATUS Init() override; 184 185 virtual MOS_STATUS Submit(MOS_COMMAND_BUFFER *commandBuffer, uint8_t packetPhase = otherPacket) override; 186 187 virtual MOS_STATUS Execute(PMOS_COMMAND_BUFFER cmdBuffer, bool storeHucStatus2Needed, bool prologNeeded, HuCFunction function = NONE_BRC) override; 188 189 //! 190 //! \brief Calculate Command Size 191 //! 192 //! \param [in, out] commandBufferSize 193 //! requested size 194 //! \param [in, out] requestedPatchListSize 195 //! requested size 196 //! \return MOS_STATUS 197 //! status 198 //! 199 MOS_STATUS CalculateCommandSize( 200 uint32_t &commandBufferSize, 201 uint32_t &requestedPatchListSize) override; 202 203 virtual MOS_STATUS DumpOutput() override; 204 205 //! 206 //! \brief Get Packet Name 207 //! \return std::string 208 //! GetPacketName()209 virtual std::string GetPacketName() override 210 { 211 return "BRCUPDATE_PASS" + std::to_string((uint32_t)m_pipeline->GetCurrentPass()); 212 } 213 214 protected: 215 virtual MOS_STATUS AllocateResources() override; 216 217 virtual MOS_STATUS SetDmemBuffer()const; 218 219 virtual MOS_STATUS SetConstDataHuCBrcUpdate()const; 220 221 virtual MOS_STATUS ConstructImageStateReadBuffer(PMOS_RESOURCE imageStateBuffer); 222 223 MHW_SETPAR_DECL_HDR(MFX_AVC_IMG_STATE); 224 MHW_SETPAR_DECL_HDR(HUC_IMEM_STATE); 225 MHW_SETPAR_DECL_HDR(HUC_DMEM_STATE); 226 MHW_SETPAR_DECL_HDR(HUC_VIRTUAL_ADDR_STATE); 227 228 #if USE_CODECHAL_DEBUG_TOOL 229 virtual MOS_STATUS DumpHucBrcUpdate(bool isInput); 230 PopulatePakParam(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_BATCH_BUFFER secondLevelBatchBuffer)231 virtual MOS_STATUS PopulatePakParam( 232 PMOS_COMMAND_BUFFER cmdBuffer, 233 PMHW_BATCH_BUFFER secondLevelBatchBuffer) { return MOS_STATUS_SUCCESS; } 234 PopulateEncParam(uint8_t meMethod,void * cmd)235 virtual MOS_STATUS PopulateEncParam(uint8_t meMethod, void *cmd) { return MOS_STATUS_SUCCESS; } 236 237 virtual MOS_STATUS DumpEncodeImgStats( 238 PMOS_COMMAND_BUFFER cmdbuffer); 239 #endif 240 241 uint32_t GetCurrConstDataBufIdx() const; 242 243 AvcBasicFeature *m_basicFeature = nullptr; //!< Avc Basic Feature used in each frame 244 AvcEncodeBRC *m_brcFeature = nullptr; //!< Avc Encode BRC Feature used in each frame 245 246 bool m_vdencStaticFrame = false; //!< Static Frame Indicator. 247 248 uint32_t m_vdencBrcUpdateDmemBufferSize = sizeof(VdencAvcHucBrcUpdateDmem); //!< Offset of BRC update DMEM buffer 249 uint32_t m_vdencBrcConstDataBufferSize = sizeof(VdencAvcHucBrcConstantData); //!< Offset of BRC const data buffer 250 251 PMOS_RESOURCE m_vdencBrcImageStatesReadBuffer[CODECHAL_ENCODE_RECYCLED_BUFFER_NUM] = {}; //!< Read-only VDENC+PAK IMG STATE buffer. 252 PMOS_RESOURCE m_vdencBrcUpdateDmemBuffer[CODECHAL_ENCODE_RECYCLED_BUFFER_NUM][VDENC_BRC_NUM_OF_PASSES] = {}; //!< Brc Update DMEM Buffer Array. 253 PMOS_RESOURCE m_vdencBrcConstDataBuffer[CODECHAL_ENCODE_VDENC_BRC_CONST_BUFFER_NUM] = {}; //!< BRC Const Data Buffer for each frame type. 254 255 PMOS_RESOURCE m_resPakOutputViaMmioBuffer = {}; //!< Buffer for PAK statistics output via MMIO 256 257 MEDIA_CLASS_DEFINE_END(encode__AvcHucBrcUpdatePkt) 258 }; 259 260 } // namespace encode 261 262 #endif // !__CODECHAL_AVC_HUC_BRC_UPDATE_PACKET_H__ 263