| /aosp_15_r20/external/flatbuffers/swift/Sources/FlatBuffers/ |
| H A D | Constants.swift | 38 public typealias VOffset = UInt16 typealias
|
| /aosp_15_r20/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCodeEmitter.cpp | 141 unsigned VOffset = 0; in EncodeSingleInstruction() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCodeEmitter.cpp | 722 unsigned VOffset = 0; in getMachineOpValue() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCodeEmitter.cpp | 736 unsigned VOffset = 0; in getMachineOpValue() local
|
| /aosp_15_r20/external/flatbuffers/src/ |
| H A D | binary_annotator.h | 35 VOffset = 3, enumerator
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 4274 Register VOffset, Register SOffset, in updateBufferMMO()
4417 Register VOffset = MI.getOperand(3 + OpOffset).getReg(); in legalizeBufferStore() local
4472 Register VIndex, Register VOffset, Register SOffset, in buildBufferLoad()
4528 Register VOffset = MI.getOperand(3 + OpOffset).getReg(); in legalizeBufferLoad() local
4734 Register VOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferAtomic() local
|
| H A D | AMDGPUInstructionSelector.cpp | 3084 Register VOffset = MI.getOperand(4 + OpOffset).getReg(); in selectBufferLoadLds() local
3207 Register VOffset; in selectGlobalLoadLds() local
4022 if (Register VOffset = matchZeroExtendFromS32(*MRI, PtrBaseOffset)) { in selectGlobalSAddr() local
4046 Register VOffset = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in selectGlobalSAddr() local
|
| H A D | SIRegisterInfo.cpp | 1365 int64_t VOffset) { in buildSpillLoadStore()
|
| H A D | AMDGPUISelDAGToDAG.cpp | 1646 SDValue &VOffset, in SelectGlobalSAddr()
|
| H A D | SIISelLowering.cpp | 7174 static void updateBufferMMO(MachineMemOperand *MMO, SDValue VOffset, in updateBufferMMO()
8290 SDValue VOffset = Op.getOperand(5 + OpOffset); in LowerINTRINSIC_VOID() local
8387 SDValue VOffset; in LowerINTRINSIC_VOID() local
|
| H A D | AMDGPURegisterBankInfo.cpp | 1369 Register VOffset; in applyMappingSBufferLoad() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 987 Register VOffset = MI.getOperand(3).getReg(); in selectStoreIntrinsic() local
|
| H A D | AMDGPURegisterBankInfo.cpp | 1380 Register VOffset = MI.getOperand(3).getReg(); in selectStoreIntrinsic() local
|
| H A D | SIISelLowering.cpp | 6115 static unsigned getBufferOffsetForMMO(SDValue VOffset, in getBufferOffsetForMMO()
|
| /aosp_15_r20/external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 25947 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4; in combineTargetShuffle() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 34859 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4; in combineTargetShuffle() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 41570 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4; in combineTargetShuffle() local
|