1 #ifndef STATE_3D_XML 2 #define STATE_3D_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://0x04.net/cgit/index.cgi/rules-ng-ng 8 git clone git://0x04.net/rules-ng-ng 9 10 The rules-ng-ng source files this header was generated from are: 11 - state.xml ( 30526 bytes, from 2024-06-12 08:52:00) 12 - common.xml ( 35664 bytes, from 2024-04-10 11:43:40) 13 - common_3d.xml ( 15069 bytes, from 2024-04-10 11:43:40) 14 - state_hi.xml ( 35854 bytes, from 2024-04-10 11:43:40) 15 - copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32) 16 - state_2d.xml ( 52271 bytes, from 2024-04-10 11:43:40) 17 - state_3d.xml ( 89522 bytes, from 2024-04-10 11:43:40) 18 - state_blt.xml ( 14592 bytes, from 2024-04-10 11:43:40) 19 - state_vg.xml ( 5975 bytes, from 2016-11-10 13:58:32) 20 21 Copyright (C) 2012-2024 by the following authors: 22 - Wladimir J. van der Laan <[email protected]> 23 - Christian Gmeiner <[email protected]> 24 - Lucas Stach <[email protected]> 25 - Russell King <[email protected]> 26 27 Permission is hereby granted, free of charge, to any person obtaining a 28 copy of this software and associated documentation files (the "Software"), 29 to deal in the Software without restriction, including without limitation 30 the rights to use, copy, modify, merge, publish, distribute, sub license, 31 and/or sell copies of the Software, and to permit persons to whom the 32 Software is furnished to do so, subject to the following conditions: 33 34 The above copyright notice and this permission notice (including the 35 next paragraph) shall be included in all copies or substantial portions 36 of the Software. 37 38 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 39 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 40 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 41 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 42 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 44 DEALINGS IN THE SOFTWARE. 45 */ 46 47 48 #define STENCIL_OP_KEEP 0x00000000 49 #define STENCIL_OP_ZERO 0x00000001 50 #define STENCIL_OP_REPLACE 0x00000002 51 #define STENCIL_OP_INCR 0x00000003 52 #define STENCIL_OP_DECR 0x00000004 53 #define STENCIL_OP_INVERT 0x00000005 54 #define STENCIL_OP_INCR_WRAP 0x00000006 55 #define STENCIL_OP_DECR_WRAP 0x00000007 56 #define BLEND_EQ_ADD 0x00000000 57 #define BLEND_EQ_SUBTRACT 0x00000001 58 #define BLEND_EQ_REVERSE_SUBTRACT 0x00000002 59 #define BLEND_EQ_MIN 0x00000003 60 #define BLEND_EQ_MAX 0x00000004 61 #define BLEND_FUNC_ZERO 0x00000000 62 #define BLEND_FUNC_ONE 0x00000001 63 #define BLEND_FUNC_SRC_COLOR 0x00000002 64 #define BLEND_FUNC_ONE_MINUS_SRC_COLOR 0x00000003 65 #define BLEND_FUNC_SRC_ALPHA 0x00000004 66 #define BLEND_FUNC_ONE_MINUS_SRC_ALPHA 0x00000005 67 #define BLEND_FUNC_DST_ALPHA 0x00000006 68 #define BLEND_FUNC_ONE_MINUS_DST_ALPHA 0x00000007 69 #define BLEND_FUNC_DST_COLOR 0x00000008 70 #define BLEND_FUNC_ONE_MINUS_DST_COLOR 0x00000009 71 #define BLEND_FUNC_SRC_ALPHA_SATURATE 0x0000000a 72 #define BLEND_FUNC_CONSTANT_ALPHA 0x0000000b 73 #define BLEND_FUNC_ONE_MINUS_CONSTANT_ALPHA 0x0000000c 74 #define BLEND_FUNC_CONSTANT_COLOR 0x0000000d 75 #define BLEND_FUNC_ONE_MINUS_CONSTANT_COLOR 0x0000000e 76 #define RS_FORMAT_X4R4G4B4 0x00000000 77 #define RS_FORMAT_A4R4G4B4 0x00000001 78 #define RS_FORMAT_X1R5G5B5 0x00000002 79 #define RS_FORMAT_A1R5G5B5 0x00000003 80 #define RS_FORMAT_R5G6B5 0x00000004 81 #define RS_FORMAT_X8R8G8B8 0x00000005 82 #define RS_FORMAT_A8R8G8B8 0x00000006 83 #define RS_FORMAT_YUY2 0x00000007 84 #define RS_FORMAT_64BPP_CLEAR 0x00000015 85 #define PE_FORMAT_X4R4G4B4 0x00000000 86 #define PE_FORMAT_A4R4G4B4 0x00000001 87 #define PE_FORMAT_X1R5G5B5 0x00000002 88 #define PE_FORMAT_A1R5G5B5 0x00000003 89 #define PE_FORMAT_R5G6B5 0x00000004 90 #define PE_FORMAT_X8R8G8B8 0x00000005 91 #define PE_FORMAT_A8R8G8B8 0x00000006 92 #define PE_FORMAT_YUY2 0x00000007 93 #define PE_FORMAT_A8 0x00000010 94 #define PE_FORMAT_R16F 0x00000011 95 #define PE_FORMAT_G16R16F 0x00000012 96 #define PE_FORMAT_A16B16G16R16F 0x00000013 97 #define PE_FORMAT_R32F 0x00000014 98 #define PE_FORMAT_G32R32F 0x00000015 99 #define PE_FORMAT_A2B10G10R10 0x00000016 100 #define PE_FORMAT_R8I 0x00000017 101 #define PE_FORMAT_G8R8I 0x00000018 102 #define PE_FORMAT_A8B8G8R8I 0x00000019 103 #define PE_FORMAT_R16I 0x0000001a 104 #define PE_FORMAT_G16R16I 0x0000001b 105 #define PE_FORMAT_A16B16G16R16I 0x0000001c 106 #define PE_FORMAT_B10G11R11F 0x0000001d 107 #define PE_FORMAT_A2B10G10R10UI 0x0000001e 108 #define PE_FORMAT_G8R8 0x0000001f 109 #define PE_FORMAT_R8 0x00000023 110 #define LOGIC_OP_CLEAR 0x00000000 111 #define LOGIC_OP_NOR 0x00000001 112 #define LOGIC_OP_AND_INVERTED 0x00000002 113 #define LOGIC_OP_COPY_INVERTED 0x00000003 114 #define LOGIC_OP_AND_REVERSE 0x00000004 115 #define LOGIC_OP_INVERT 0x00000005 116 #define LOGIC_OP_XOR 0x00000006 117 #define LOGIC_OP_NAND 0x00000007 118 #define LOGIC_OP_AND 0x00000008 119 #define LOGIC_OP_EQUIV 0x00000009 120 #define LOGIC_OP_NOOP 0x0000000a 121 #define LOGIC_OP_OR_INVERTED 0x0000000b 122 #define LOGIC_OP_COPY 0x0000000c 123 #define LOGIC_OP_OR_REVERSE 0x0000000d 124 #define LOGIC_OP_OR 0x0000000e 125 #define LOGIC_OP_SET 0x0000000f 126 #define COLOR_OUTPUT_MODE_NORMAL 0x00000000 127 #define COLOR_OUTPUT_MODE_A2B10G10R10UI 0x00000001 128 #define COLOR_OUTPUT_MODE_UIF32 0x00000002 129 #define COLOR_OUTPUT_MODE_U8 0x00000003 130 #define COLOR_OUTPUT_MODE_U16 0x00000004 131 #define COLOR_OUTPUT_MODE_I8 0x00000005 132 #define COLOR_OUTPUT_MODE_I16 0x00000006 133 #define RT_CONFIG_STRIDE__MASK 0x0000ffff 134 #define RT_CONFIG_STRIDE__SHIFT 0 135 #define RT_CONFIG_STRIDE(x) (((x) << RT_CONFIG_STRIDE__SHIFT) & RT_CONFIG_STRIDE__MASK) 136 #define RT_CONFIG_FORMAT__MASK 0x03f00000 137 #define RT_CONFIG_FORMAT__SHIFT 20 138 #define RT_CONFIG_FORMAT(x) (((x) << RT_CONFIG_FORMAT__SHIFT) & RT_CONFIG_FORMAT__MASK) 139 #define RT_CONFIG_TS_MODE__MASK 0x04000000 140 #define RT_CONFIG_TS_MODE__SHIFT 26 141 #define RT_CONFIG_TS_MODE(x) (((x) << RT_CONFIG_TS_MODE__SHIFT) & RT_CONFIG_TS_MODE__MASK) 142 #define RT_CONFIG_UNK27 0x08000000 143 #define RT_CONFIG_SUPER_TILED 0x10000000 144 #define RT_CONFIG_UNK29 0x20000000 145 #define VARYING_NUM_COMPONENTS_VAR0__MASK 0x00000007 146 #define VARYING_NUM_COMPONENTS_VAR0__SHIFT 0 147 #define VARYING_NUM_COMPONENTS_VAR0(x) (((x) << VARYING_NUM_COMPONENTS_VAR0__SHIFT) & VARYING_NUM_COMPONENTS_VAR0__MASK) 148 #define VARYING_NUM_COMPONENTS_VAR1__MASK 0x00000070 149 #define VARYING_NUM_COMPONENTS_VAR1__SHIFT 4 150 #define VARYING_NUM_COMPONENTS_VAR1(x) (((x) << VARYING_NUM_COMPONENTS_VAR1__SHIFT) & VARYING_NUM_COMPONENTS_VAR1__MASK) 151 #define VARYING_NUM_COMPONENTS_VAR2__MASK 0x00000700 152 #define VARYING_NUM_COMPONENTS_VAR2__SHIFT 8 153 #define VARYING_NUM_COMPONENTS_VAR2(x) (((x) << VARYING_NUM_COMPONENTS_VAR2__SHIFT) & VARYING_NUM_COMPONENTS_VAR2__MASK) 154 #define VARYING_NUM_COMPONENTS_VAR3__MASK 0x00007000 155 #define VARYING_NUM_COMPONENTS_VAR3__SHIFT 12 156 #define VARYING_NUM_COMPONENTS_VAR3(x) (((x) << VARYING_NUM_COMPONENTS_VAR3__SHIFT) & VARYING_NUM_COMPONENTS_VAR3__MASK) 157 #define VARYING_NUM_COMPONENTS_VAR4__MASK 0x00070000 158 #define VARYING_NUM_COMPONENTS_VAR4__SHIFT 16 159 #define VARYING_NUM_COMPONENTS_VAR4(x) (((x) << VARYING_NUM_COMPONENTS_VAR4__SHIFT) & VARYING_NUM_COMPONENTS_VAR4__MASK) 160 #define VARYING_NUM_COMPONENTS_VAR5__MASK 0x00700000 161 #define VARYING_NUM_COMPONENTS_VAR5__SHIFT 20 162 #define VARYING_NUM_COMPONENTS_VAR5(x) (((x) << VARYING_NUM_COMPONENTS_VAR5__SHIFT) & VARYING_NUM_COMPONENTS_VAR5__MASK) 163 #define VARYING_NUM_COMPONENTS_VAR6__MASK 0x07000000 164 #define VARYING_NUM_COMPONENTS_VAR6__SHIFT 24 165 #define VARYING_NUM_COMPONENTS_VAR6(x) (((x) << VARYING_NUM_COMPONENTS_VAR6__SHIFT) & VARYING_NUM_COMPONENTS_VAR6__MASK) 166 #define VARYING_NUM_COMPONENTS_VAR7__MASK 0x70000000 167 #define VARYING_NUM_COMPONENTS_VAR7__SHIFT 28 168 #define VARYING_NUM_COMPONENTS_VAR7(x) (((x) << VARYING_NUM_COMPONENTS_VAR7__SHIFT) & VARYING_NUM_COMPONENTS_VAR7__MASK) 169 #define VIVS_VS 0x00000000 170 171 #define VIVS_VS_END_PC 0x00000800 172 173 #define VIVS_VS_OUTPUT_COUNT 0x00000804 174 #define VIVS_VS_OUTPUT_COUNT_COUNT__MASK 0x000000ff 175 #define VIVS_VS_OUTPUT_COUNT_COUNT__SHIFT 0 176 #define VIVS_VS_OUTPUT_COUNT_COUNT(x) (((x) << VIVS_VS_OUTPUT_COUNT_COUNT__SHIFT) & VIVS_VS_OUTPUT_COUNT_COUNT__MASK) 177 #define VIVS_VS_OUTPUT_COUNT_OUTPUT16_REG__MASK 0x0000ff00 178 #define VIVS_VS_OUTPUT_COUNT_OUTPUT16_REG__SHIFT 8 179 #define VIVS_VS_OUTPUT_COUNT_OUTPUT16_REG(x) (((x) << VIVS_VS_OUTPUT_COUNT_OUTPUT16_REG__SHIFT) & VIVS_VS_OUTPUT_COUNT_OUTPUT16_REG__MASK) 180 #define VIVS_VS_OUTPUT_COUNT_OUTPUT17_REG__MASK 0x00ff0000 181 #define VIVS_VS_OUTPUT_COUNT_OUTPUT17_REG__SHIFT 16 182 #define VIVS_VS_OUTPUT_COUNT_OUTPUT17_REG(x) (((x) << VIVS_VS_OUTPUT_COUNT_OUTPUT17_REG__SHIFT) & VIVS_VS_OUTPUT_COUNT_OUTPUT17_REG__MASK) 183 184 #define VIVS_VS_INPUT_COUNT 0x00000808 185 #define VIVS_VS_INPUT_COUNT_COUNT__MASK 0x0000000f 186 #define VIVS_VS_INPUT_COUNT_COUNT__SHIFT 0 187 #define VIVS_VS_INPUT_COUNT_COUNT(x) (((x) << VIVS_VS_INPUT_COUNT_COUNT__SHIFT) & VIVS_VS_INPUT_COUNT_COUNT__MASK) 188 #define VIVS_VS_INPUT_COUNT_UNK8__MASK 0x00001f00 189 #define VIVS_VS_INPUT_COUNT_UNK8__SHIFT 8 190 #define VIVS_VS_INPUT_COUNT_UNK8(x) (((x) << VIVS_VS_INPUT_COUNT_UNK8__SHIFT) & VIVS_VS_INPUT_COUNT_UNK8__MASK) 191 #define VIVS_VS_INPUT_COUNT_ID_ENABLE 0x80000000 192 193 #define VIVS_VS_TEMP_REGISTER_CONTROL 0x0000080c 194 #define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK 0x0000003f 195 #define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT 0 196 #define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS(x) (((x) << VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT) & VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK) 197 198 #define VIVS_VS_OUTPUT(i0) (0x00000810 + 0x4*(i0)) 199 #define VIVS_VS_OUTPUT__ESIZE 0x00000004 200 #define VIVS_VS_OUTPUT__LEN 0x00000004 201 #define VIVS_VS_OUTPUT_O0__MASK 0x000000ff 202 #define VIVS_VS_OUTPUT_O0__SHIFT 0 203 #define VIVS_VS_OUTPUT_O0(x) (((x) << VIVS_VS_OUTPUT_O0__SHIFT) & VIVS_VS_OUTPUT_O0__MASK) 204 #define VIVS_VS_OUTPUT_O1__MASK 0x0000ff00 205 #define VIVS_VS_OUTPUT_O1__SHIFT 8 206 #define VIVS_VS_OUTPUT_O1(x) (((x) << VIVS_VS_OUTPUT_O1__SHIFT) & VIVS_VS_OUTPUT_O1__MASK) 207 #define VIVS_VS_OUTPUT_O2__MASK 0x00ff0000 208 #define VIVS_VS_OUTPUT_O2__SHIFT 16 209 #define VIVS_VS_OUTPUT_O2(x) (((x) << VIVS_VS_OUTPUT_O2__SHIFT) & VIVS_VS_OUTPUT_O2__MASK) 210 #define VIVS_VS_OUTPUT_O3__MASK 0xff000000 211 #define VIVS_VS_OUTPUT_O3__SHIFT 24 212 #define VIVS_VS_OUTPUT_O3(x) (((x) << VIVS_VS_OUTPUT_O3__SHIFT) & VIVS_VS_OUTPUT_O3__MASK) 213 214 #define VIVS_VS_INPUT(i0) (0x00000820 + 0x4*(i0)) 215 #define VIVS_VS_INPUT__ESIZE 0x00000004 216 #define VIVS_VS_INPUT__LEN 0x00000004 217 #define VIVS_VS_INPUT_I0__MASK 0x000000ff 218 #define VIVS_VS_INPUT_I0__SHIFT 0 219 #define VIVS_VS_INPUT_I0(x) (((x) << VIVS_VS_INPUT_I0__SHIFT) & VIVS_VS_INPUT_I0__MASK) 220 #define VIVS_VS_INPUT_I1__MASK 0x0000ff00 221 #define VIVS_VS_INPUT_I1__SHIFT 8 222 #define VIVS_VS_INPUT_I1(x) (((x) << VIVS_VS_INPUT_I1__SHIFT) & VIVS_VS_INPUT_I1__MASK) 223 #define VIVS_VS_INPUT_I2__MASK 0x00ff0000 224 #define VIVS_VS_INPUT_I2__SHIFT 16 225 #define VIVS_VS_INPUT_I2(x) (((x) << VIVS_VS_INPUT_I2__SHIFT) & VIVS_VS_INPUT_I2__MASK) 226 #define VIVS_VS_INPUT_I3__MASK 0xff000000 227 #define VIVS_VS_INPUT_I3__SHIFT 24 228 #define VIVS_VS_INPUT_I3(x) (((x) << VIVS_VS_INPUT_I3__SHIFT) & VIVS_VS_INPUT_I3__MASK) 229 230 #define VIVS_VS_LOAD_BALANCING 0x00000830 231 #define VIVS_VS_LOAD_BALANCING_A__MASK 0x000000ff 232 #define VIVS_VS_LOAD_BALANCING_A__SHIFT 0 233 #define VIVS_VS_LOAD_BALANCING_A(x) (((x) << VIVS_VS_LOAD_BALANCING_A__SHIFT) & VIVS_VS_LOAD_BALANCING_A__MASK) 234 #define VIVS_VS_LOAD_BALANCING_B__MASK 0x0000ff00 235 #define VIVS_VS_LOAD_BALANCING_B__SHIFT 8 236 #define VIVS_VS_LOAD_BALANCING_B(x) (((x) << VIVS_VS_LOAD_BALANCING_B__SHIFT) & VIVS_VS_LOAD_BALANCING_B__MASK) 237 #define VIVS_VS_LOAD_BALANCING_C__MASK 0x00ff0000 238 #define VIVS_VS_LOAD_BALANCING_C__SHIFT 16 239 #define VIVS_VS_LOAD_BALANCING_C(x) (((x) << VIVS_VS_LOAD_BALANCING_C__SHIFT) & VIVS_VS_LOAD_BALANCING_C__MASK) 240 #define VIVS_VS_LOAD_BALANCING_D__MASK 0xff000000 241 #define VIVS_VS_LOAD_BALANCING_D__SHIFT 24 242 #define VIVS_VS_LOAD_BALANCING_D(x) (((x) << VIVS_VS_LOAD_BALANCING_D__SHIFT) & VIVS_VS_LOAD_BALANCING_D__MASK) 243 244 #define VIVS_VS_PERF_COUNTER 0x00000834 245 246 #define VIVS_VS_START_PC 0x00000838 247 248 #define VIVS_VS_UNK00850 0x00000850 249 250 #define VIVS_VS_UNK00854 0x00000854 251 252 #define VIVS_VS_UNK00858 0x00000858 253 254 #define VIVS_VS_RANGE 0x0000085c 255 #define VIVS_VS_RANGE_LOW__MASK 0x0000ffff 256 #define VIVS_VS_RANGE_LOW__SHIFT 0 257 #define VIVS_VS_RANGE_LOW(x) (((x) << VIVS_VS_RANGE_LOW__SHIFT) & VIVS_VS_RANGE_LOW__MASK) 258 #define VIVS_VS_RANGE_HIGH__MASK 0xffff0000 259 #define VIVS_VS_RANGE_HIGH__SHIFT 16 260 #define VIVS_VS_RANGE_HIGH(x) (((x) << VIVS_VS_RANGE_HIGH__SHIFT) & VIVS_VS_RANGE_HIGH__MASK) 261 262 #define VIVS_VS_UNIFORM_CACHE 0x00000860 263 #define VIVS_VS_UNIFORM_CACHE_FLUSH 0x00000001 264 #define VIVS_VS_UNIFORM_CACHE_PS 0x00000010 265 #define VIVS_VS_UNIFORM_CACHE_RTNE_ROUNDING 0x00001000 266 267 #define VIVS_VS_UNIFORM_BASE 0x00000864 268 269 #define VIVS_VS_ICACHE_CONTROL 0x00000868 270 #define VIVS_VS_ICACHE_CONTROL_ENABLE 0x00000001 271 #define VIVS_VS_ICACHE_CONTROL_FLUSH_VS 0x00000010 272 #define VIVS_VS_ICACHE_CONTROL_FLUSH_PS 0x00000020 273 274 #define VIVS_VS_INST_ADDR 0x0000086c 275 276 #define VIVS_VS_HALTI5_OUTPUT_COUNT 0x00000870 277 #define VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT__MASK 0x000003ff 278 #define VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT__SHIFT 0 279 #define VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT(x) (((x) << VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT__SHIFT) & VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT__MASK) 280 #define VIVS_VS_HALTI5_OUTPUT_COUNT_B__MASK 0x0007ff00 281 #define VIVS_VS_HALTI5_OUTPUT_COUNT_B__SHIFT 8 282 #define VIVS_VS_HALTI5_OUTPUT_COUNT_B(x) (((x) << VIVS_VS_HALTI5_OUTPUT_COUNT_B__SHIFT) & VIVS_VS_HALTI5_OUTPUT_COUNT_B__MASK) 283 284 #define VIVS_VS_NEWRANGE_LOW 0x00000874 285 286 #define VIVS_VS_HALTI5_UNK00878 0x00000878 287 288 #define VIVS_VS_HALTI5_UNK00880 0x00000880 289 290 #define VIVS_VS_HALTI1_UNK00884 0x00000884 291 292 #define VIVS_VS_ICACHE_PREFETCH 0x0000088c 293 294 #define VIVS_VS_ICACHE_PREFETCH_INSTRUCTIONS 0x00000890 295 296 #define VIVS_VS_HALTI5_UNK00898(i0) (0x00000898 + 0x4*(i0)) 297 #define VIVS_VS_HALTI5_UNK00898__ESIZE 0x00000004 298 #define VIVS_VS_HALTI5_UNK00898__LEN 0x00000002 299 300 #define VIVS_VS_HALTI5_UNK008A0 0x000008a0 301 #define VIVS_VS_HALTI5_UNK008A0_A__MASK 0x0000003f 302 #define VIVS_VS_HALTI5_UNK008A0_A__SHIFT 0 303 #define VIVS_VS_HALTI5_UNK008A0_A(x) (((x) << VIVS_VS_HALTI5_UNK008A0_A__SHIFT) & VIVS_VS_HALTI5_UNK008A0_A__MASK) 304 #define VIVS_VS_HALTI5_UNK008A0_B__MASK 0x0007f000 305 #define VIVS_VS_HALTI5_UNK008A0_B__SHIFT 12 306 #define VIVS_VS_HALTI5_UNK008A0_B(x) (((x) << VIVS_VS_HALTI5_UNK008A0_B__SHIFT) & VIVS_VS_HALTI5_UNK008A0_B__MASK) 307 #define VIVS_VS_HALTI5_UNK008A0_C__MASK 0x1ff00000 308 #define VIVS_VS_HALTI5_UNK008A0_C__SHIFT 20 309 #define VIVS_VS_HALTI5_UNK008A0_C(x) (((x) << VIVS_VS_HALTI5_UNK008A0_C__SHIFT) & VIVS_VS_HALTI5_UNK008A0_C__MASK) 310 311 #define VIVS_VS_SAMPLER_BASE 0x000008a8 312 313 #define VIVS_VS_ICACHE_INVALIDATE 0x000008b0 314 #define VIVS_VS_ICACHE_INVALIDATE_UNK0 0x00000001 315 #define VIVS_VS_ICACHE_INVALIDATE_UNK1 0x00000002 316 #define VIVS_VS_ICACHE_INVALIDATE_UNK2 0x00000004 317 #define VIVS_VS_ICACHE_INVALIDATE_UNK3 0x00000008 318 #define VIVS_VS_ICACHE_INVALIDATE_UNK4 0x00000010 319 320 #define VIVS_VS_HALTI5_UNK008B8 0x000008b8 321 322 #define VIVS_VS_NEWRANGE_HIGH 0x000008bc 323 324 #define VIVS_VS_HALTI5_INPUT(i0) (0x000008c0 + 0x4*(i0)) 325 #define VIVS_VS_HALTI5_INPUT__ESIZE 0x00000004 326 #define VIVS_VS_HALTI5_INPUT__LEN 0x00000008 327 #define VIVS_VS_HALTI5_INPUT_I0__MASK 0x000000ff 328 #define VIVS_VS_HALTI5_INPUT_I0__SHIFT 0 329 #define VIVS_VS_HALTI5_INPUT_I0(x) (((x) << VIVS_VS_HALTI5_INPUT_I0__SHIFT) & VIVS_VS_HALTI5_INPUT_I0__MASK) 330 #define VIVS_VS_HALTI5_INPUT_I1__MASK 0x0000ff00 331 #define VIVS_VS_HALTI5_INPUT_I1__SHIFT 8 332 #define VIVS_VS_HALTI5_INPUT_I1(x) (((x) << VIVS_VS_HALTI5_INPUT_I1__SHIFT) & VIVS_VS_HALTI5_INPUT_I1__MASK) 333 #define VIVS_VS_HALTI5_INPUT_I2__MASK 0x00ff0000 334 #define VIVS_VS_HALTI5_INPUT_I2__SHIFT 16 335 #define VIVS_VS_HALTI5_INPUT_I2(x) (((x) << VIVS_VS_HALTI5_INPUT_I2__SHIFT) & VIVS_VS_HALTI5_INPUT_I2__MASK) 336 #define VIVS_VS_HALTI5_INPUT_I3__MASK 0xff000000 337 #define VIVS_VS_HALTI5_INPUT_I3__SHIFT 24 338 #define VIVS_VS_HALTI5_INPUT_I3(x) (((x) << VIVS_VS_HALTI5_INPUT_I3__SHIFT) & VIVS_VS_HALTI5_INPUT_I3__MASK) 339 340 #define VIVS_VS_HALTI5_OUTPUT(i0) (0x000008e0 + 0x4*(i0)) 341 #define VIVS_VS_HALTI5_OUTPUT__ESIZE 0x00000004 342 #define VIVS_VS_HALTI5_OUTPUT__LEN 0x00000008 343 #define VIVS_VS_HALTI5_OUTPUT_O0__MASK 0x000000ff 344 #define VIVS_VS_HALTI5_OUTPUT_O0__SHIFT 0 345 #define VIVS_VS_HALTI5_OUTPUT_O0(x) (((x) << VIVS_VS_HALTI5_OUTPUT_O0__SHIFT) & VIVS_VS_HALTI5_OUTPUT_O0__MASK) 346 #define VIVS_VS_HALTI5_OUTPUT_O1__MASK 0x0000ff00 347 #define VIVS_VS_HALTI5_OUTPUT_O1__SHIFT 8 348 #define VIVS_VS_HALTI5_OUTPUT_O1(x) (((x) << VIVS_VS_HALTI5_OUTPUT_O1__SHIFT) & VIVS_VS_HALTI5_OUTPUT_O1__MASK) 349 #define VIVS_VS_HALTI5_OUTPUT_O2__MASK 0x00ff0000 350 #define VIVS_VS_HALTI5_OUTPUT_O2__SHIFT 16 351 #define VIVS_VS_HALTI5_OUTPUT_O2(x) (((x) << VIVS_VS_HALTI5_OUTPUT_O2__SHIFT) & VIVS_VS_HALTI5_OUTPUT_O2__MASK) 352 #define VIVS_VS_HALTI5_OUTPUT_O3__MASK 0xff000000 353 #define VIVS_VS_HALTI5_OUTPUT_O3__SHIFT 24 354 #define VIVS_VS_HALTI5_OUTPUT_O3(x) (((x) << VIVS_VS_HALTI5_OUTPUT_O3__SHIFT) & VIVS_VS_HALTI5_OUTPUT_O3__MASK) 355 356 #define VIVS_VS_INST_MEM(i0) (0x00004000 + 0x4*(i0)) 357 #define VIVS_VS_INST_MEM__ESIZE 0x00000004 358 #define VIVS_VS_INST_MEM__LEN 0x00000400 359 360 #define VIVS_VS_UNIFORMS(i0) (0x00005000 + 0x4*(i0)) 361 #define VIVS_VS_UNIFORMS__ESIZE 0x00000004 362 #define VIVS_VS_UNIFORMS__LEN 0x00000400 363 364 #define VIVS_VS_ICACHE_COUNT 0x00015604 365 366 #define VIVS_VS_MULTI_CLUSTER_UNK15608 0x00015608 367 368 #define VIVS_CL 0x00000000 369 370 #define VIVS_CL_CONFIG 0x00000900 371 #define VIVS_CL_CONFIG_DIMENSIONS__MASK 0x00000003 372 #define VIVS_CL_CONFIG_DIMENSIONS__SHIFT 0 373 #define VIVS_CL_CONFIG_DIMENSIONS(x) (((x) << VIVS_CL_CONFIG_DIMENSIONS__SHIFT) & VIVS_CL_CONFIG_DIMENSIONS__MASK) 374 #define VIVS_CL_CONFIG_TRAVERSE_ORDER__MASK 0x00000070 375 #define VIVS_CL_CONFIG_TRAVERSE_ORDER__SHIFT 4 376 #define VIVS_CL_CONFIG_TRAVERSE_ORDER(x) (((x) << VIVS_CL_CONFIG_TRAVERSE_ORDER__SHIFT) & VIVS_CL_CONFIG_TRAVERSE_ORDER__MASK) 377 #define VIVS_CL_CONFIG_ENABLE_SWATH_X 0x00000100 378 #define VIVS_CL_CONFIG_ENABLE_SWATH_Y 0x00000200 379 #define VIVS_CL_CONFIG_ENABLE_SWATH_Z 0x00000400 380 #define VIVS_CL_CONFIG_SWATH_SIZE_X__MASK 0x0000f000 381 #define VIVS_CL_CONFIG_SWATH_SIZE_X__SHIFT 12 382 #define VIVS_CL_CONFIG_SWATH_SIZE_X(x) (((x) << VIVS_CL_CONFIG_SWATH_SIZE_X__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_X__MASK) 383 #define VIVS_CL_CONFIG_SWATH_SIZE_Y__MASK 0x000f0000 384 #define VIVS_CL_CONFIG_SWATH_SIZE_Y__SHIFT 16 385 #define VIVS_CL_CONFIG_SWATH_SIZE_Y(x) (((x) << VIVS_CL_CONFIG_SWATH_SIZE_Y__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_Y__MASK) 386 #define VIVS_CL_CONFIG_SWATH_SIZE_Z__MASK 0x00f00000 387 #define VIVS_CL_CONFIG_SWATH_SIZE_Z__SHIFT 20 388 #define VIVS_CL_CONFIG_SWATH_SIZE_Z(x) (((x) << VIVS_CL_CONFIG_SWATH_SIZE_Z__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_Z__MASK) 389 #define VIVS_CL_CONFIG_VALUE_ORDER__MASK 0x07000000 390 #define VIVS_CL_CONFIG_VALUE_ORDER__SHIFT 24 391 #define VIVS_CL_CONFIG_VALUE_ORDER(x) (((x) << VIVS_CL_CONFIG_VALUE_ORDER__SHIFT) & VIVS_CL_CONFIG_VALUE_ORDER__MASK) 392 393 #define VIVS_CL_GLOBAL_X 0x00000904 394 #define VIVS_CL_GLOBAL_X_SIZE__MASK 0x0000ffff 395 #define VIVS_CL_GLOBAL_X_SIZE__SHIFT 0 396 #define VIVS_CL_GLOBAL_X_SIZE(x) (((x) << VIVS_CL_GLOBAL_X_SIZE__SHIFT) & VIVS_CL_GLOBAL_X_SIZE__MASK) 397 #define VIVS_CL_GLOBAL_X_OFFSET__MASK 0xffff0000 398 #define VIVS_CL_GLOBAL_X_OFFSET__SHIFT 16 399 #define VIVS_CL_GLOBAL_X_OFFSET(x) (((x) << VIVS_CL_GLOBAL_X_OFFSET__SHIFT) & VIVS_CL_GLOBAL_X_OFFSET__MASK) 400 401 #define VIVS_CL_GLOBAL_Y 0x00000908 402 #define VIVS_CL_GLOBAL_Y_SIZE__MASK 0x0000ffff 403 #define VIVS_CL_GLOBAL_Y_SIZE__SHIFT 0 404 #define VIVS_CL_GLOBAL_Y_SIZE(x) (((x) << VIVS_CL_GLOBAL_Y_SIZE__SHIFT) & VIVS_CL_GLOBAL_Y_SIZE__MASK) 405 #define VIVS_CL_GLOBAL_Y_OFFSET__MASK 0xffff0000 406 #define VIVS_CL_GLOBAL_Y_OFFSET__SHIFT 16 407 #define VIVS_CL_GLOBAL_Y_OFFSET(x) (((x) << VIVS_CL_GLOBAL_Y_OFFSET__SHIFT) & VIVS_CL_GLOBAL_Y_OFFSET__MASK) 408 409 #define VIVS_CL_GLOBAL_Z 0x0000090c 410 #define VIVS_CL_GLOBAL_Z_SIZE__MASK 0x0000ffff 411 #define VIVS_CL_GLOBAL_Z_SIZE__SHIFT 0 412 #define VIVS_CL_GLOBAL_Z_SIZE(x) (((x) << VIVS_CL_GLOBAL_Z_SIZE__SHIFT) & VIVS_CL_GLOBAL_Z_SIZE__MASK) 413 #define VIVS_CL_GLOBAL_Z_OFFSET__MASK 0xffff0000 414 #define VIVS_CL_GLOBAL_Z_OFFSET__SHIFT 16 415 #define VIVS_CL_GLOBAL_Z_OFFSET(x) (((x) << VIVS_CL_GLOBAL_Z_OFFSET__SHIFT) & VIVS_CL_GLOBAL_Z_OFFSET__MASK) 416 417 #define VIVS_CL_WORKGROUP_X 0x00000910 418 #define VIVS_CL_WORKGROUP_X_SIZE__MASK 0x000003ff 419 #define VIVS_CL_WORKGROUP_X_SIZE__SHIFT 0 420 #define VIVS_CL_WORKGROUP_X_SIZE(x) (((x) << VIVS_CL_WORKGROUP_X_SIZE__SHIFT) & VIVS_CL_WORKGROUP_X_SIZE__MASK) 421 #define VIVS_CL_WORKGROUP_X_COUNT__MASK 0xffff0000 422 #define VIVS_CL_WORKGROUP_X_COUNT__SHIFT 16 423 #define VIVS_CL_WORKGROUP_X_COUNT(x) (((x) << VIVS_CL_WORKGROUP_X_COUNT__SHIFT) & VIVS_CL_WORKGROUP_X_COUNT__MASK) 424 425 #define VIVS_CL_WORKGROUP_Y 0x00000914 426 #define VIVS_CL_WORKGROUP_Y_SIZE__MASK 0x000003ff 427 #define VIVS_CL_WORKGROUP_Y_SIZE__SHIFT 0 428 #define VIVS_CL_WORKGROUP_Y_SIZE(x) (((x) << VIVS_CL_WORKGROUP_Y_SIZE__SHIFT) & VIVS_CL_WORKGROUP_Y_SIZE__MASK) 429 #define VIVS_CL_WORKGROUP_Y_COUNT__MASK 0xffff0000 430 #define VIVS_CL_WORKGROUP_Y_COUNT__SHIFT 16 431 #define VIVS_CL_WORKGROUP_Y_COUNT(x) (((x) << VIVS_CL_WORKGROUP_Y_COUNT__SHIFT) & VIVS_CL_WORKGROUP_Y_COUNT__MASK) 432 433 #define VIVS_CL_WORKGROUP_Z 0x00000918 434 #define VIVS_CL_WORKGROUP_Z_SIZE__MASK 0x000003ff 435 #define VIVS_CL_WORKGROUP_Z_SIZE__SHIFT 0 436 #define VIVS_CL_WORKGROUP_Z_SIZE(x) (((x) << VIVS_CL_WORKGROUP_Z_SIZE__SHIFT) & VIVS_CL_WORKGROUP_Z_SIZE__MASK) 437 #define VIVS_CL_WORKGROUP_Z_COUNT__MASK 0xffff0000 438 #define VIVS_CL_WORKGROUP_Z_COUNT__SHIFT 16 439 #define VIVS_CL_WORKGROUP_Z_COUNT(x) (((x) << VIVS_CL_WORKGROUP_Z_COUNT__SHIFT) & VIVS_CL_WORKGROUP_Z_COUNT__MASK) 440 441 #define VIVS_CL_THREAD_ALLOCATION 0x0000091c 442 443 #define VIVS_CL_KICKER 0x00000920 444 445 #define VIVS_CL_UNK00924 0x00000924 446 447 #define VIVS_CL_GLOBAL_WORK_OFFSET_X 0x0000092c 448 449 #define VIVS_CL_GLOBAL_WORK_OFFSET_Y 0x00000934 450 451 #define VIVS_CL_GLOBAL_WORK_OFFSET_Z 0x0000093c 452 453 #define VIVS_CL_WORKGROUP_COUNT_X 0x00000940 454 455 #define VIVS_CL_WORKGROUP_COUNT_Y 0x00000944 456 457 #define VIVS_CL_WORKGROUP_COUNT_Z 0x00000948 458 459 #define VIVS_CL_WORKGROUP_SIZE_X 0x0000094c 460 461 #define VIVS_CL_WORKGROUP_SIZE_Y 0x00000950 462 463 #define VIVS_CL_WORKGROUP_SIZE_Z 0x00000954 464 465 #define VIVS_CL_HALTI5_UNK00958 0x00000958 466 467 #define VIVS_CL_HALTI5_UNK0095C 0x0000095c 468 469 #define VIVS_CL_HALTI5_UNK00960 0x00000960 470 471 #define VIVS_PA 0x00000000 472 473 #define VIVS_PA_VIEWPORT_SCALE_X 0x00000a00 474 475 #define VIVS_PA_VIEWPORT_SCALE_Y 0x00000a04 476 477 #define VIVS_PA_VIEWPORT_SCALE_Z 0x00000a08 478 479 #define VIVS_PA_VIEWPORT_OFFSET_X 0x00000a0c 480 481 #define VIVS_PA_VIEWPORT_OFFSET_Y 0x00000a10 482 483 #define VIVS_PA_VIEWPORT_OFFSET_Z 0x00000a14 484 485 #define VIVS_PA_LINE_WIDTH 0x00000a18 486 487 #define VIVS_PA_POINT_SIZE 0x00000a1c 488 489 #define VIVS_PA_UNK00A24 0x00000a24 490 491 #define VIVS_PA_SYSTEM_MODE 0x00000a28 492 #define VIVS_PA_SYSTEM_MODE_PROVOKING_VERTEX_LAST 0x00000001 493 #define VIVS_PA_SYSTEM_MODE_HALF_PIXEL_CENTER 0x00000010 494 495 #define VIVS_PA_W_CLIP_LIMIT 0x00000a2c 496 497 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT 0x00000a30 498 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__MASK 0x000000ff 499 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__SHIFT 0 500 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0(x) (((x) << VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__SHIFT) & VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__MASK) 501 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__MASK 0x0000ff00 502 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__SHIFT 8 503 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT(x) (((x) << VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__SHIFT) & VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__MASK) 504 505 #define VIVS_PA_CONFIG 0x00000a34 506 #define VIVS_PA_CONFIG_POINT_SIZE_ENABLE 0x00000004 507 #define VIVS_PA_CONFIG_POINT_SIZE_ENABLE_MASK 0x00000008 508 #define VIVS_PA_CONFIG_POINT_SPRITE_ENABLE 0x00000010 509 #define VIVS_PA_CONFIG_POINT_SPRITE_ENABLE_MASK 0x00000020 510 #define VIVS_PA_CONFIG_CULL_FACE_MODE__MASK 0x00000300 511 #define VIVS_PA_CONFIG_CULL_FACE_MODE__SHIFT 8 512 #define VIVS_PA_CONFIG_CULL_FACE_MODE_OFF 0x00000000 513 #define VIVS_PA_CONFIG_CULL_FACE_MODE_CW 0x00000100 514 #define VIVS_PA_CONFIG_CULL_FACE_MODE_CCW 0x00000200 515 #define VIVS_PA_CONFIG_CULL_FACE_MODE_MASK 0x00000400 516 #define VIVS_PA_CONFIG_FILL_MODE__MASK 0x00003000 517 #define VIVS_PA_CONFIG_FILL_MODE__SHIFT 12 518 #define VIVS_PA_CONFIG_FILL_MODE_POINT 0x00000000 519 #define VIVS_PA_CONFIG_FILL_MODE_WIREFRAME 0x00001000 520 #define VIVS_PA_CONFIG_FILL_MODE_SOLID 0x00002000 521 #define VIVS_PA_CONFIG_FILL_MODE_MASK 0x00004000 522 #define VIVS_PA_CONFIG_SHADE_MODEL__MASK 0x00030000 523 #define VIVS_PA_CONFIG_SHADE_MODEL__SHIFT 16 524 #define VIVS_PA_CONFIG_SHADE_MODEL_FLAT 0x00000000 525 #define VIVS_PA_CONFIG_SHADE_MODEL_SMOOTH 0x00010000 526 #define VIVS_PA_CONFIG_SHADE_MODEL_MASK 0x00040000 527 #define VIVS_PA_CONFIG_WIDE_LINE 0x00400000 528 #define VIVS_PA_CONFIG_WIDE_LINE_MASK 0x00800000 529 530 #define VIVS_PA_WIDE_LINE_WIDTH0 0x00000a38 531 532 #define VIVS_PA_WIDE_LINE_WIDTH1 0x00000a3c 533 534 #define VIVS_PA_SHADER_ATTRIBUTES(i0) (0x00000a40 + 0x4*(i0)) 535 #define VIVS_PA_SHADER_ATTRIBUTES__ESIZE 0x00000004 536 #define VIVS_PA_SHADER_ATTRIBUTES__LEN 0x00000010 537 #define VIVS_PA_SHADER_ATTRIBUTES_BYPASS_FLAT 0x00000001 538 #define VIVS_PA_SHADER_ATTRIBUTES_UNK4__MASK 0x000000f0 539 #define VIVS_PA_SHADER_ATTRIBUTES_UNK4__SHIFT 4 540 #define VIVS_PA_SHADER_ATTRIBUTES_UNK4(x) (((x) << VIVS_PA_SHADER_ATTRIBUTES_UNK4__SHIFT) & VIVS_PA_SHADER_ATTRIBUTES_UNK4__MASK) 541 #define VIVS_PA_SHADER_ATTRIBUTES_UNK8__MASK 0x00000f00 542 #define VIVS_PA_SHADER_ATTRIBUTES_UNK8__SHIFT 8 543 #define VIVS_PA_SHADER_ATTRIBUTES_UNK8(x) (((x) << VIVS_PA_SHADER_ATTRIBUTES_UNK8__SHIFT) & VIVS_PA_SHADER_ATTRIBUTES_UNK8__MASK) 544 545 #define VIVS_PA_VIEWPORT_UNK00A80 0x00000a80 546 547 #define VIVS_PA_VIEWPORT_UNK00A84 0x00000a84 548 549 #define VIVS_PA_FLAGS 0x00000a88 550 #define VIVS_PA_FLAGS_UNK24 0x01000000 551 #define VIVS_PA_FLAGS_ZCONVERT_BYPASS 0x40000000 552 553 #define VIVS_PA_ZFARCLIPPING 0x00000a8c 554 555 #define VIVS_PA_VARYING_NUM_COMPONENTS(i0) (0x00000a90 + 0x4*(i0)) 556 #define VIVS_PA_VARYING_NUM_COMPONENTS__ESIZE 0x00000004 557 #define VIVS_PA_VARYING_NUM_COMPONENTS__LEN 0x00000004 558 559 #define VIVS_PA_VS_OUTPUT_COUNT 0x00000aa8 560 561 #define VIVS_PA_MULTI_CLUSTER_UNK00AAC 0x00000aac 562 563 #define VIVS_SE 0x00000000 564 565 #define VIVS_SE_SCISSOR_LEFT 0x00000c00 566 567 #define VIVS_SE_SCISSOR_TOP 0x00000c04 568 569 #define VIVS_SE_SCISSOR_RIGHT 0x00000c08 570 571 #define VIVS_SE_SCISSOR_BOTTOM 0x00000c0c 572 573 #define VIVS_SE_DEPTH_SCALE 0x00000c10 574 575 #define VIVS_SE_DEPTH_BIAS 0x00000c14 576 577 #define VIVS_SE_CONFIG 0x00000c18 578 #define VIVS_SE_CONFIG_LAST_PIXEL_ENABLE 0x00000001 579 580 #define VIVS_SE_UNK00C1C 0x00000c1c 581 582 #define VIVS_SE_CLIP_RIGHT 0x00000c20 583 584 #define VIVS_SE_CLIP_BOTTOM 0x00000c24 585 586 #define VIVS_RA 0x00000000 587 588 #define VIVS_RA_CONTROL 0x00000e00 589 #define VIVS_RA_CONTROL_UNK0 0x00000001 590 #define VIVS_RA_CONTROL_LAST_VARYING_2X 0x00000002 591 592 #define VIVS_RA_MULTISAMPLE_UNK00E04 0x00000e04 593 594 #define VIVS_RA_EARLY_DEPTH 0x00000e08 595 #define VIVS_RA_EARLY_DEPTH_TEST_ENABLE 0x00000001 596 #define VIVS_RA_EARLY_DEPTH_HDEPTH_DISABLE 0x01000000 597 #define VIVS_RA_EARLY_DEPTH_LATE_DEPTH_MSAA 0x02000000 598 #define VIVS_RA_EARLY_DEPTH_WRITE_DISABLE 0x10000000 599 600 #define VIVS_RA_UNK00E0C 0x00000e0c 601 602 #define VIVS_RA_MULTISAMPLE_UNK00E10(i0) (0x00000e10 + 0x4*(i0)) 603 #define VIVS_RA_MULTISAMPLE_UNK00E10__ESIZE 0x00000004 604 #define VIVS_RA_MULTISAMPLE_UNK00E10__LEN 0x00000004 605 606 #define VIVS_RA_HDEPTH_CONTROL 0x00000e20 607 #define VIVS_RA_HDEPTH_CONTROL_UNK0 0x00000001 608 #define VIVS_RA_HDEPTH_CONTROL_COMPARE__MASK 0x00007000 609 #define VIVS_RA_HDEPTH_CONTROL_COMPARE__SHIFT 12 610 #define VIVS_RA_HDEPTH_CONTROL_COMPARE(x) (((x) << VIVS_RA_HDEPTH_CONTROL_COMPARE__SHIFT) & VIVS_RA_HDEPTH_CONTROL_COMPARE__MASK) 611 612 #define VIVS_RA_UNK00E24 0x00000e24 613 614 #define VIVS_RA_HALTI5_UNK00E34 0x00000e34 615 616 #define VIVS_RA_CENTROID_TABLE(i0) (0x00000e40 + 0x4*(i0)) 617 #define VIVS_RA_CENTROID_TABLE__ESIZE 0x00000004 618 #define VIVS_RA_CENTROID_TABLE__LEN 0x00000010 619 620 #define VIVS_PS 0x00000000 621 622 #define VIVS_PS_END_PC 0x00001000 623 624 #define VIVS_PS_OUTPUT_REG 0x00001004 625 #define VIVS_PS_OUTPUT_REG_0__MASK 0x0000007f 626 #define VIVS_PS_OUTPUT_REG_0__SHIFT 0 627 #define VIVS_PS_OUTPUT_REG_0(x) (((x) << VIVS_PS_OUTPUT_REG_0__SHIFT) & VIVS_PS_OUTPUT_REG_0__MASK) 628 #define VIVS_PS_OUTPUT_REG_1__MASK 0x00007f00 629 #define VIVS_PS_OUTPUT_REG_1__SHIFT 8 630 #define VIVS_PS_OUTPUT_REG_1(x) (((x) << VIVS_PS_OUTPUT_REG_1__SHIFT) & VIVS_PS_OUTPUT_REG_1__MASK) 631 #define VIVS_PS_OUTPUT_REG_2__MASK 0x007f0000 632 #define VIVS_PS_OUTPUT_REG_2__SHIFT 16 633 #define VIVS_PS_OUTPUT_REG_2(x) (((x) << VIVS_PS_OUTPUT_REG_2__SHIFT) & VIVS_PS_OUTPUT_REG_2__MASK) 634 #define VIVS_PS_OUTPUT_REG_3__MASK 0x7f000000 635 #define VIVS_PS_OUTPUT_REG_3__SHIFT 24 636 #define VIVS_PS_OUTPUT_REG_3(x) (((x) << VIVS_PS_OUTPUT_REG_3__SHIFT) & VIVS_PS_OUTPUT_REG_3__MASK) 637 638 #define VIVS_PS_INPUT_COUNT 0x00001008 639 #define VIVS_PS_INPUT_COUNT_COUNT__MASK 0x0000001f 640 #define VIVS_PS_INPUT_COUNT_COUNT__SHIFT 0 641 #define VIVS_PS_INPUT_COUNT_COUNT(x) (((x) << VIVS_PS_INPUT_COUNT_COUNT__SHIFT) & VIVS_PS_INPUT_COUNT_COUNT__MASK) 642 #define VIVS_PS_INPUT_COUNT_UNK8__MASK 0x00001f00 643 #define VIVS_PS_INPUT_COUNT_UNK8__SHIFT 8 644 #define VIVS_PS_INPUT_COUNT_UNK8(x) (((x) << VIVS_PS_INPUT_COUNT_UNK8__SHIFT) & VIVS_PS_INPUT_COUNT_UNK8__MASK) 645 #define VIVS_PS_INPUT_COUNT_DUAL16 0x00010000 646 647 #define VIVS_PS_TEMP_REGISTER_CONTROL 0x0000100c 648 #define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK 0x0000003f 649 #define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT 0 650 #define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(x) (((x) << VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT) & VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK) 651 652 #define VIVS_PS_CONTROL 0x00001010 653 #define VIVS_PS_CONTROL_BYPASS 0x00000001 654 #define VIVS_PS_CONTROL_SATURATE_RT0 0x00000002 655 #define VIVS_PS_CONTROL_SATURATE_RT1 0x00000004 656 #define VIVS_PS_CONTROL_SATURATE_RT2 0x00000008 657 #define VIVS_PS_CONTROL_SATURATE_RT3 0x00000010 658 #define VIVS_PS_CONTROL_RT_COUNT__MASK 0x00000700 659 #define VIVS_PS_CONTROL_RT_COUNT__SHIFT 8 660 #define VIVS_PS_CONTROL_RT_COUNT(x) (((x) << VIVS_PS_CONTROL_RT_COUNT__SHIFT) & VIVS_PS_CONTROL_RT_COUNT__MASK) 661 662 #define VIVS_PS_PERF_COUNTER 0x00001014 663 664 #define VIVS_PS_START_PC 0x00001018 665 666 #define VIVS_PS_RANGE 0x0000101c 667 #define VIVS_PS_RANGE_LOW__MASK 0x0000ffff 668 #define VIVS_PS_RANGE_LOW__SHIFT 0 669 #define VIVS_PS_RANGE_LOW(x) (((x) << VIVS_PS_RANGE_LOW__SHIFT) & VIVS_PS_RANGE_LOW__MASK) 670 #define VIVS_PS_RANGE_HIGH__MASK 0xffff0000 671 #define VIVS_PS_RANGE_HIGH__SHIFT 16 672 #define VIVS_PS_RANGE_HIGH(x) (((x) << VIVS_PS_RANGE_HIGH__SHIFT) & VIVS_PS_RANGE_HIGH__MASK) 673 674 #define VIVS_PS_REG_COUNT 0x0000101e 675 676 #define VIVS_PS_UNIFORM_BASE 0x00001024 677 678 #define VIVS_PS_INST_ADDR 0x00001028 679 680 #define VIVS_PS_OUTPUT_REG2 0x0000102c 681 #define VIVS_PS_OUTPUT_REG2_4__MASK 0x0000007f 682 #define VIVS_PS_OUTPUT_REG2_4__SHIFT 0 683 #define VIVS_PS_OUTPUT_REG2_4(x) (((x) << VIVS_PS_OUTPUT_REG2_4__SHIFT) & VIVS_PS_OUTPUT_REG2_4__MASK) 684 #define VIVS_PS_OUTPUT_REG2_SATURATE_RT4 0x00000080 685 #define VIVS_PS_OUTPUT_REG2_5__MASK 0x00007f00 686 #define VIVS_PS_OUTPUT_REG2_5__SHIFT 8 687 #define VIVS_PS_OUTPUT_REG2_5(x) (((x) << VIVS_PS_OUTPUT_REG2_5__SHIFT) & VIVS_PS_OUTPUT_REG2_5__MASK) 688 #define VIVS_PS_OUTPUT_REG2_SATURATE_RT5 0x00008000 689 #define VIVS_PS_OUTPUT_REG2_6__MASK 0x007f0000 690 #define VIVS_PS_OUTPUT_REG2_6__SHIFT 16 691 #define VIVS_PS_OUTPUT_REG2_6(x) (((x) << VIVS_PS_OUTPUT_REG2_6__SHIFT) & VIVS_PS_OUTPUT_REG2_6__MASK) 692 #define VIVS_PS_OUTPUT_REG2_SATURATE_RT6 0x00800000 693 #define VIVS_PS_OUTPUT_REG2_7__MASK 0x7f000000 694 #define VIVS_PS_OUTPUT_REG2_7__SHIFT 24 695 #define VIVS_PS_OUTPUT_REG2_7(x) (((x) << VIVS_PS_OUTPUT_REG2_7__SHIFT) & VIVS_PS_OUTPUT_REG2_7__MASK) 696 #define VIVS_PS_OUTPUT_REG2_SATURATE_RT7 0x80000000 697 698 #define VIVS_PS_CONTROL_EXT 0x00001030 699 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__MASK 0x00000007 700 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__SHIFT 0 701 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE0(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE0__MASK) 702 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE1__MASK 0x00000070 703 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE1__SHIFT 4 704 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE1(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE1__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE1__MASK) 705 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE2__MASK 0x00000700 706 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE2__SHIFT 8 707 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE2(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE2__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE2__MASK) 708 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE3__MASK 0x00007000 709 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE3__SHIFT 12 710 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE3(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE3__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE3__MASK) 711 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE4__MASK 0x00070000 712 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE4__SHIFT 16 713 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE4(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE4__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE4__MASK) 714 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE5__MASK 0x00700000 715 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE5__SHIFT 20 716 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE5(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE5__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE5__MASK) 717 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE6__MASK 0x07000000 718 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE6__SHIFT 24 719 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE6(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE6__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE6__MASK) 720 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE7__MASK 0x70000000 721 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE7__SHIFT 28 722 #define VIVS_PS_CONTROL_EXT_OUTPUT_MODE7(x) (((x) << VIVS_PS_CONTROL_EXT_OUTPUT_MODE7__SHIFT) & VIVS_PS_CONTROL_EXT_OUTPUT_MODE7__MASK) 723 724 #define VIVS_PS_UNK01034 0x00001034 725 726 #define VIVS_PS_UNK01038 0x00001038 727 728 #define VIVS_PS_HALTI3_UNK0103C 0x0000103c 729 730 #define VIVS_PS_UNK01040(i0) (0x00001040 + 0x4*(i0)) 731 #define VIVS_PS_UNK01040__ESIZE 0x00000004 732 #define VIVS_PS_UNK01040__LEN 0x00000002 733 734 #define VIVS_PS_ICACHE_PREFETCH 0x00001048 735 736 #define VIVS_PS_ICACHE_PREFETCH_INSTRUCTIONS 0x0000104c 737 738 #define VIVS_PS_MSAA_CONFIG 0x00001054 739 740 #define VIVS_PS_SAMPLER_BASE 0x00001058 741 742 #define VIVS_PS_VARYING_NUM_COMPONENTS(i0) (0x00001080 + 0x4*(i0)) 743 #define VIVS_PS_VARYING_NUM_COMPONENTS__ESIZE 0x00000004 744 #define VIVS_PS_VARYING_NUM_COMPONENTS__LEN 0x00000004 745 746 #define VIVS_PS_NEWRANGE_LOW 0x0000087c 747 748 #define VIVS_PS_NEWRANGE_HIGH 0x00001090 749 750 #define VIVS_PS_ICACHE_COUNT 0x00001094 751 752 #define VIVS_PS_HALTI5_UNK01098 0x00001098 753 754 #define VIVS_PS_PSCS_THROTTLE 0x0000109c 755 756 #define VIVS_PS_NN_INST_ADDR 0x000010a0 757 758 #define VIVS_PS_UNK10A4 0x000010a4 759 760 #define VIVS_PS_MULTI_CLUSTER_UNK10A8 0x000010a8 761 762 #define VIVS_PS_TP_INST_ADDR 0x000010b8 763 764 #define VIVS_PS_INST_MEM(i0) (0x00006000 + 0x4*(i0)) 765 #define VIVS_PS_INST_MEM__ESIZE 0x00000004 766 #define VIVS_PS_INST_MEM__LEN 0x00000400 767 768 #define VIVS_PS_UNIFORMS(i0) (0x00007000 + 0x4*(i0)) 769 #define VIVS_PS_UNIFORMS__ESIZE 0x00000004 770 #define VIVS_PS_UNIFORMS__LEN 0x00000400 771 772 #define VIVS_GS 0x00000000 773 774 #define VIVS_GS_UNK01100 0x00001100 775 776 #define VIVS_GS_UNK01104 0x00001104 777 778 #define VIVS_GS_UNK01108 0x00001108 779 780 #define VIVS_GS_UNK0110C 0x0000110c 781 782 #define VIVS_GS_UNK01110 0x00001110 783 784 #define VIVS_GS_UNK01114 0x00001114 785 786 #define VIVS_GS_ICACHE_PREFETCH 0x00001118 787 788 #define VIVS_GS_UNK0111C 0x0000111c 789 790 #define VIVS_GS_UNK01120(i0) (0x00001120 + 0x4*(i0)) 791 #define VIVS_GS_UNK01120__ESIZE 0x00000004 792 #define VIVS_GS_UNK01120__LEN 0x00000008 793 794 #define VIVS_GS_UNK01140 0x00001140 795 796 #define VIVS_GS_UNK01144 0x00001144 797 798 #define VIVS_GS_UNK01148 0x00001148 799 800 #define VIVS_GS_UNK0114C 0x0000114c 801 802 #define VIVS_GS_UNK01154 0x00001154 803 804 #define VIVS_TCS 0x00000000 805 806 #define VIVS_TCS_UNK007C0 0x000007c0 807 808 #define VIVS_TCS_UNK14A00 0x00014a00 809 810 #define VIVS_TCS_UNK14A04 0x00014a04 811 812 #define VIVS_TCS_UNK14A08 0x00014a08 813 814 #define VIVS_TCS_ICACHE_PREFETCH 0x00014a0c 815 816 #define VIVS_TCS_UNK14A10 0x00014a10 817 818 #define VIVS_TCS_UNK14A14 0x00014a14 819 820 #define VIVS_TCS_UNK14A18 0x00014a18 821 822 #define VIVS_TCS_UNK14A1C 0x00014a1c 823 824 #define VIVS_TCS_UNK14A20(i0) (0x00014a20 + 0x4*(i0)) 825 #define VIVS_TCS_UNK14A20__ESIZE 0x00000004 826 #define VIVS_TCS_UNK14A20__LEN 0x00000008 827 828 #define VIVS_TCS_UNK14A40 0x00014a40 829 830 #define VIVS_TCS_UNK14A44 0x00014a44 831 832 #define VIVS_TCS_UNK14A4C 0x00014a4c 833 834 #define VIVS_TES 0x00000000 835 836 #define VIVS_TES_UNK14B00 0x00014b00 837 838 #define VIVS_TES_UNK14B04 0x00014b04 839 840 #define VIVS_TES_UNK14B08 0x00014b08 841 842 #define VIVS_TES_UNK14B0C 0x00014b0c 843 844 #define VIVS_TES_ICACHE_PREFETCH 0x00014b10 845 846 #define VIVS_TES_UNK14B14 0x00014b14 847 848 #define VIVS_TES_UNK14B18 0x00014b18 849 850 #define VIVS_TES_UNK14B1C 0x00014b1c 851 852 #define VIVS_TES_UNK14B20 0x00014b20 853 854 #define VIVS_TES_UNK14B24 0x00014b24 855 856 #define VIVS_TES_UNK14B2C 0x00014b2c 857 858 #define VIVS_TES_UNK14B34 0x00014b34 859 860 #define VIVS_TES_UNK14B40(i0) (0x00014b40 + 0x4*(i0)) 861 #define VIVS_TES_UNK14B40__ESIZE 0x00000004 862 #define VIVS_TES_UNK14B40__LEN 0x00000008 863 864 #define VIVS_TFB 0x00000000 865 866 #define VIVS_TFB_UNK1C000 0x0001c000 867 868 #define VIVS_TFB_UNK1C008 0x0001c008 869 870 #define VIVS_TFB_FLUSH 0x0001c00c 871 872 #define VIVS_TFB_UNK1C014 0x0001c014 873 874 #define VIVS_TFB_UNK1C040(i0) (0x0001c040 + 0x4*(i0)) 875 #define VIVS_TFB_UNK1C040__ESIZE 0x00000004 876 #define VIVS_TFB_UNK1C040__LEN 0x00000004 877 878 #define VIVS_TFB_UNK1C080(i0) (0x0001c080 + 0x4*(i0)) 879 #define VIVS_TFB_UNK1C080__ESIZE 0x00000004 880 #define VIVS_TFB_UNK1C080__LEN 0x00000004 881 882 #define VIVS_TFB_UNK1C0C0(i0) (0x0001c0c0 + 0x4*(i0)) 883 #define VIVS_TFB_UNK1C0C0__ESIZE 0x00000004 884 #define VIVS_TFB_UNK1C0C0__LEN 0x00000004 885 886 #define VIVS_TFB_UNK1C100(i0) (0x0001c100 + 0x4*(i0)) 887 #define VIVS_TFB_UNK1C100__ESIZE 0x00000004 888 #define VIVS_TFB_UNK1C100__LEN 0x00000004 889 890 #define VIVS_TFB_UNK1C800(i0) (0x0001c800 + 0x4*(i0)) 891 #define VIVS_TFB_UNK1C800__ESIZE 0x00000004 892 #define VIVS_TFB_UNK1C800__LEN 0x00000200 893 894 #define VIVS_PE 0x00000000 895 896 #define VIVS_PE_DEPTH_CONFIG 0x00001400 897 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE__MASK 0x00000003 898 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE__SHIFT 0 899 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE 0x00000000 900 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z 0x00000001 901 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_W 0x00000002 902 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_MASK 0x00000008 903 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT__MASK 0x00000010 904 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT__SHIFT 4 905 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16 0x00000000 906 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D24S8 0x00000010 907 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_MASK 0x00000020 908 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__MASK 0x00000700 909 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__SHIFT 8 910 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(x) (((x) << VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__SHIFT) & VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__MASK) 911 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC_MASK 0x00000800 912 #define VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE 0x00001000 913 #define VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE_MASK 0x00002000 914 #define VIVS_PE_DEPTH_CONFIG_EARLY_Z 0x00010000 915 #define VIVS_PE_DEPTH_CONFIG_EARLY_Z_MASK 0x00020000 916 #define VIVS_PE_DEPTH_CONFIG_UNK18 0x00040000 917 #define VIVS_PE_DEPTH_CONFIG_UNK18_MASK 0x00080000 918 #define VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH 0x00100000 919 #define VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH_MASK 0x00200000 920 #define VIVS_PE_DEPTH_CONFIG_DISABLE_ZS 0x01000000 921 #define VIVS_PE_DEPTH_CONFIG_DISABLE_ZS_MASK 0x02000000 922 #define VIVS_PE_DEPTH_CONFIG_SUPER_TILED 0x04000000 923 #define VIVS_PE_DEPTH_CONFIG_SUPER_TILED_MASK 0x08000000 924 925 #define VIVS_PE_DEPTH_NEAR 0x00001404 926 927 #define VIVS_PE_DEPTH_FAR 0x00001408 928 929 #define VIVS_PE_DEPTH_NORMALIZE 0x0000140c 930 931 #define VIVS_PE_DEPTH_ADDR 0x00001410 932 933 #define VIVS_PE_DEPTH_STRIDE 0x00001414 934 935 #define VIVS_PE_STENCIL_OP 0x00001418 936 #define VIVS_PE_STENCIL_OP_FUNC_FRONT__MASK 0x00000007 937 #define VIVS_PE_STENCIL_OP_FUNC_FRONT__SHIFT 0 938 #define VIVS_PE_STENCIL_OP_FUNC_FRONT(x) (((x) << VIVS_PE_STENCIL_OP_FUNC_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_FUNC_FRONT__MASK) 939 #define VIVS_PE_STENCIL_OP_FUNC_FRONT_MASK 0x00000008 940 #define VIVS_PE_STENCIL_OP_PASS_FRONT__MASK 0x00000070 941 #define VIVS_PE_STENCIL_OP_PASS_FRONT__SHIFT 4 942 #define VIVS_PE_STENCIL_OP_PASS_FRONT(x) (((x) << VIVS_PE_STENCIL_OP_PASS_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_PASS_FRONT__MASK) 943 #define VIVS_PE_STENCIL_OP_PASS_FRONT_MASK 0x00000080 944 #define VIVS_PE_STENCIL_OP_FAIL_FRONT__MASK 0x00000700 945 #define VIVS_PE_STENCIL_OP_FAIL_FRONT__SHIFT 8 946 #define VIVS_PE_STENCIL_OP_FAIL_FRONT(x) (((x) << VIVS_PE_STENCIL_OP_FAIL_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_FAIL_FRONT__MASK) 947 #define VIVS_PE_STENCIL_OP_FAIL_FRONT_MASK 0x00000800 948 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__MASK 0x00007000 949 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__SHIFT 12 950 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(x) (((x) << VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__MASK) 951 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT_MASK 0x00008000 952 #define VIVS_PE_STENCIL_OP_FUNC_BACK__MASK 0x00070000 953 #define VIVS_PE_STENCIL_OP_FUNC_BACK__SHIFT 16 954 #define VIVS_PE_STENCIL_OP_FUNC_BACK(x) (((x) << VIVS_PE_STENCIL_OP_FUNC_BACK__SHIFT) & VIVS_PE_STENCIL_OP_FUNC_BACK__MASK) 955 #define VIVS_PE_STENCIL_OP_FUNC_BACK_MASK 0x00080000 956 #define VIVS_PE_STENCIL_OP_PASS_BACK__MASK 0x00700000 957 #define VIVS_PE_STENCIL_OP_PASS_BACK__SHIFT 20 958 #define VIVS_PE_STENCIL_OP_PASS_BACK(x) (((x) << VIVS_PE_STENCIL_OP_PASS_BACK__SHIFT) & VIVS_PE_STENCIL_OP_PASS_BACK__MASK) 959 #define VIVS_PE_STENCIL_OP_PASS_BACK_MASK 0x00800000 960 #define VIVS_PE_STENCIL_OP_FAIL_BACK__MASK 0x07000000 961 #define VIVS_PE_STENCIL_OP_FAIL_BACK__SHIFT 24 962 #define VIVS_PE_STENCIL_OP_FAIL_BACK(x) (((x) << VIVS_PE_STENCIL_OP_FAIL_BACK__SHIFT) & VIVS_PE_STENCIL_OP_FAIL_BACK__MASK) 963 #define VIVS_PE_STENCIL_OP_FAIL_BACK_MASK 0x08000000 964 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__MASK 0x70000000 965 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__SHIFT 28 966 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(x) (((x) << VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__SHIFT) & VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__MASK) 967 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK_MASK 0x80000000 968 969 #define VIVS_PE_STENCIL_CONFIG 0x0000141c 970 #define VIVS_PE_STENCIL_CONFIG_MODE__MASK 0x00000003 971 #define VIVS_PE_STENCIL_CONFIG_MODE__SHIFT 0 972 #define VIVS_PE_STENCIL_CONFIG_MODE_DISABLED 0x00000000 973 #define VIVS_PE_STENCIL_CONFIG_MODE_ONE_SIDED 0x00000001 974 #define VIVS_PE_STENCIL_CONFIG_MODE_TWO_SIDED 0x00000002 975 #define VIVS_PE_STENCIL_CONFIG_MODE_MASK 0x00000010 976 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT_MASK 0x00000020 977 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT_MASK 0x00000040 978 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_MASK 0x00000080 979 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT__MASK 0x0000ff00 980 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT__SHIFT 8 981 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT(x) (((x) << VIVS_PE_STENCIL_CONFIG_REF_FRONT__SHIFT) & VIVS_PE_STENCIL_CONFIG_REF_FRONT__MASK) 982 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT__MASK 0x00ff0000 983 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT__SHIFT 16 984 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT(x) (((x) << VIVS_PE_STENCIL_CONFIG_MASK_FRONT__SHIFT) & VIVS_PE_STENCIL_CONFIG_MASK_FRONT__MASK) 985 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT__MASK 0xff000000 986 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT__SHIFT 24 987 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT(x) (((x) << VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT__SHIFT) & VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT__MASK) 988 989 #define VIVS_PE_ALPHA_OP 0x00001420 990 #define VIVS_PE_ALPHA_OP_ALPHA_TEST 0x00000001 991 #define VIVS_PE_ALPHA_OP_ALPHA_TEST_MASK 0x00000002 992 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC__MASK 0x00000070 993 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC__SHIFT 4 994 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC(x) (((x) << VIVS_PE_ALPHA_OP_ALPHA_FUNC__SHIFT) & VIVS_PE_ALPHA_OP_ALPHA_FUNC__MASK) 995 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC_MASK 0x00000080 996 #define VIVS_PE_ALPHA_OP_ALPHA_REF__MASK 0x0000ff00 997 #define VIVS_PE_ALPHA_OP_ALPHA_REF__SHIFT 8 998 #define VIVS_PE_ALPHA_OP_ALPHA_REF(x) (((x) << VIVS_PE_ALPHA_OP_ALPHA_REF__SHIFT) & VIVS_PE_ALPHA_OP_ALPHA_REF__MASK) 999 #define VIVS_PE_ALPHA_OP_ALPHA_REF_MASKFUNC_MASK 0x00010000 1000 1001 #define VIVS_PE_ALPHA_BLEND_COLOR 0x00001424 1002 #define VIVS_PE_ALPHA_BLEND_COLOR_B__MASK 0x000000ff 1003 #define VIVS_PE_ALPHA_BLEND_COLOR_B__SHIFT 0 1004 #define VIVS_PE_ALPHA_BLEND_COLOR_B(x) (((x) << VIVS_PE_ALPHA_BLEND_COLOR_B__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_B__MASK) 1005 #define VIVS_PE_ALPHA_BLEND_COLOR_G__MASK 0x0000ff00 1006 #define VIVS_PE_ALPHA_BLEND_COLOR_G__SHIFT 8 1007 #define VIVS_PE_ALPHA_BLEND_COLOR_G(x) (((x) << VIVS_PE_ALPHA_BLEND_COLOR_G__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_G__MASK) 1008 #define VIVS_PE_ALPHA_BLEND_COLOR_R__MASK 0x00ff0000 1009 #define VIVS_PE_ALPHA_BLEND_COLOR_R__SHIFT 16 1010 #define VIVS_PE_ALPHA_BLEND_COLOR_R(x) (((x) << VIVS_PE_ALPHA_BLEND_COLOR_R__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_R__MASK) 1011 #define VIVS_PE_ALPHA_BLEND_COLOR_A__MASK 0xff000000 1012 #define VIVS_PE_ALPHA_BLEND_COLOR_A__SHIFT 24 1013 #define VIVS_PE_ALPHA_BLEND_COLOR_A(x) (((x) << VIVS_PE_ALPHA_BLEND_COLOR_A__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_A__MASK) 1014 1015 #define VIVS_PE_ALPHA_CONFIG 0x00001428 1016 #define VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR 0x00000001 1017 #define VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR_MASK 0x00000002 1018 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR_MASK 0x00000004 1019 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR_MASK 0x00000008 1020 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__MASK 0x000000f0 1021 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__SHIFT 4 1022 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR(x) (((x) << VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__MASK) 1023 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__MASK 0x00000f00 1024 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__SHIFT 8 1025 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR(x) (((x) << VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__MASK) 1026 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR__MASK 0x00007000 1027 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR__SHIFT 12 1028 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR(x) (((x) << VIVS_PE_ALPHA_CONFIG_EQ_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_EQ_COLOR__MASK) 1029 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR_MASK 0x00008000 1030 #define VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA 0x00010000 1031 #define VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA_MASK 0x00020000 1032 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA_MASK 0x00040000 1033 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA_MASK 0x00080000 1034 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__MASK 0x00f00000 1035 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__SHIFT 20 1036 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA(x) (((x) << VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__MASK) 1037 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__MASK 0x0f000000 1038 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__SHIFT 24 1039 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA(x) (((x) << VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__MASK) 1040 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__MASK 0x70000000 1041 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__SHIFT 28 1042 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA(x) (((x) << VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__MASK) 1043 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA_MASK 0x80000000 1044 1045 #define VIVS_PE_COLOR_FORMAT 0x0000142c 1046 #define VIVS_PE_COLOR_FORMAT_FORMAT__MASK 0x0000000f 1047 #define VIVS_PE_COLOR_FORMAT_FORMAT__SHIFT 0 1048 #define VIVS_PE_COLOR_FORMAT_FORMAT(x) (((x) << VIVS_PE_COLOR_FORMAT_FORMAT__SHIFT) & VIVS_PE_COLOR_FORMAT_FORMAT__MASK) 1049 #define VIVS_PE_COLOR_FORMAT_FORMAT_MASK 0x00000010 1050 #define VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK 0x00000f00 1051 #define VIVS_PE_COLOR_FORMAT_COMPONENTS__SHIFT 8 1052 #define VIVS_PE_COLOR_FORMAT_COMPONENTS(x) (((x) << VIVS_PE_COLOR_FORMAT_COMPONENTS__SHIFT) & VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK) 1053 #define VIVS_PE_COLOR_FORMAT_COMPONENTS_MASK 0x00001000 1054 #define VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW 0x00002000 1055 #define VIVS_PE_COLOR_FORMAT_OVERWRITE 0x00010000 1056 #define VIVS_PE_COLOR_FORMAT_OVERWRITE_MASK 0x00020000 1057 #define VIVS_PE_COLOR_FORMAT_SUPER_TILED 0x00100000 1058 #define VIVS_PE_COLOR_FORMAT_SUPER_TILED_MASK 0x00200000 1059 #define VIVS_PE_COLOR_FORMAT_FORMAT_EXT__MASK 0x7f000000 1060 #define VIVS_PE_COLOR_FORMAT_FORMAT_EXT__SHIFT 24 1061 #define VIVS_PE_COLOR_FORMAT_FORMAT_EXT(x) (((x) << VIVS_PE_COLOR_FORMAT_FORMAT_EXT__SHIFT) & VIVS_PE_COLOR_FORMAT_FORMAT_EXT__MASK) 1062 #define VIVS_PE_COLOR_FORMAT_FORMAT_EXT_MASK 0x80000000 1063 1064 #define VIVS_PE_COLOR_ADDR 0x00001430 1065 1066 #define VIVS_PE_COLOR_STRIDE 0x00001434 1067 1068 #define VIVS_PE_HDEPTH_CONTROL 0x00001454 1069 #define VIVS_PE_HDEPTH_CONTROL_FORMAT__MASK 0x0000000f 1070 #define VIVS_PE_HDEPTH_CONTROL_FORMAT__SHIFT 0 1071 #define VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED 0x00000000 1072 #define VIVS_PE_HDEPTH_CONTROL_FORMAT_D16 0x00000005 1073 #define VIVS_PE_HDEPTH_CONTROL_FORMAT_D24S8 0x00000008 1074 1075 #define VIVS_PE_HDEPTH_ADDR 0x00001458 1076 1077 #define VIVS_PE_UNK0145C 0x0000145c 1078 1079 #define VIVS_PE_PIPE(i0) (0x00000000 + 0x4*(i0)) 1080 #define VIVS_PE_PIPE__ESIZE 0x00000004 1081 #define VIVS_PE_PIPE__LEN 0x00000008 1082 1083 #define VIVS_PE_PIPE_COLOR_ADDR(i0) (0x00001460 + 0x4*(i0)) 1084 1085 #define VIVS_PE_PIPE_DEPTH_ADDR(i0) (0x00001480 + 0x4*(i0)) 1086 1087 #define VIVS_PE_RT_ADDR_4(i0) (0x00000000 + 0x20*(i0)) 1088 #define VIVS_PE_RT_ADDR_4__ESIZE 0x00000020 1089 #define VIVS_PE_RT_ADDR_4__LEN 0x00000003 1090 1091 #define VIVS_PE_RT_ADDR_4_PIPE(i0, i1) (0x00001500 + 0x20*(i0) + 0x4*(i1)) 1092 #define VIVS_PE_RT_ADDR_4_PIPE__ESIZE 0x00000004 1093 #define VIVS_PE_RT_ADDR_4_PIPE__LEN 0x00000003 1094 1095 #define VIVS_PE_STENCIL_CONFIG_EXT 0x000014a0 1096 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__MASK 0x000000ff 1097 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__SHIFT 0 1098 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__MASK) 1099 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK_MASK 0x00000100 1100 #define VIVS_PE_STENCIL_CONFIG_EXT_UNK16_MASK 0x00000200 1101 #define VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF__MASK 0xffff0000 1102 #define VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF__SHIFT 16 1103 #define VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT_EXTRA_ALPHA_REF__MASK) 1104 1105 #define VIVS_PE_LOGIC_OP 0x000014a4 1106 #define VIVS_PE_LOGIC_OP_OP__MASK 0x0000000f 1107 #define VIVS_PE_LOGIC_OP_OP__SHIFT 0 1108 #define VIVS_PE_LOGIC_OP_OP(x) (((x) << VIVS_PE_LOGIC_OP_OP__SHIFT) & VIVS_PE_LOGIC_OP_OP__MASK) 1109 #define VIVS_PE_LOGIC_OP_OP_MASK 0x00000010 1110 #define VIVS_PE_LOGIC_OP_DITHER_MODE__MASK 0x00000060 1111 #define VIVS_PE_LOGIC_OP_DITHER_MODE__SHIFT 5 1112 #define VIVS_PE_LOGIC_OP_DITHER_MODE(x) (((x) << VIVS_PE_LOGIC_OP_DITHER_MODE__SHIFT) & VIVS_PE_LOGIC_OP_DITHER_MODE__MASK) 1113 #define VIVS_PE_LOGIC_OP_SINGLE_BUFFER_MASK 0x00000080 1114 #define VIVS_PE_LOGIC_OP_SINGLE_BUFFER__MASK 0x00000300 1115 #define VIVS_PE_LOGIC_OP_SINGLE_BUFFER__SHIFT 8 1116 #define VIVS_PE_LOGIC_OP_SINGLE_BUFFER(x) (((x) << VIVS_PE_LOGIC_OP_SINGLE_BUFFER__SHIFT) & VIVS_PE_LOGIC_OP_SINGLE_BUFFER__MASK) 1117 #define VIVS_PE_LOGIC_OP_DITHER_MODE_MASK 0x00000400 1118 #define VIVS_PE_LOGIC_OP_UNK11 0x00000800 1119 #define VIVS_PE_LOGIC_OP_UNK20__MASK 0x00300000 1120 #define VIVS_PE_LOGIC_OP_UNK20__SHIFT 20 1121 #define VIVS_PE_LOGIC_OP_UNK20(x) (((x) << VIVS_PE_LOGIC_OP_UNK20__SHIFT) & VIVS_PE_LOGIC_OP_UNK20__MASK) 1122 #define VIVS_PE_LOGIC_OP_UNK20_MASK 0x00800000 1123 #define VIVS_PE_LOGIC_OP_UNK24__MASK 0x07000000 1124 #define VIVS_PE_LOGIC_OP_UNK24__SHIFT 24 1125 #define VIVS_PE_LOGIC_OP_UNK24(x) (((x) << VIVS_PE_LOGIC_OP_UNK24__SHIFT) & VIVS_PE_LOGIC_OP_UNK24__MASK) 1126 #define VIVS_PE_LOGIC_OP_UNK24_MASK 0x08000000 1127 #define VIVS_PE_LOGIC_OP_SRGB_MASK 0x40000000 1128 #define VIVS_PE_LOGIC_OP_SRGB 0x80000000 1129 1130 #define VIVS_PE_DITHER(i0) (0x000014a8 + 0x4*(i0)) 1131 #define VIVS_PE_DITHER__ESIZE 0x00000004 1132 #define VIVS_PE_DITHER__LEN 0x00000002 1133 1134 #define VIVS_PE_ALPHA_COLOR_EXT0 0x000014b0 1135 #define VIVS_PE_ALPHA_COLOR_EXT0_B__MASK 0x0000ffff 1136 #define VIVS_PE_ALPHA_COLOR_EXT0_B__SHIFT 0 1137 #define VIVS_PE_ALPHA_COLOR_EXT0_B(x) (((x) << VIVS_PE_ALPHA_COLOR_EXT0_B__SHIFT) & VIVS_PE_ALPHA_COLOR_EXT0_B__MASK) 1138 #define VIVS_PE_ALPHA_COLOR_EXT0_G__MASK 0xffff0000 1139 #define VIVS_PE_ALPHA_COLOR_EXT0_G__SHIFT 16 1140 #define VIVS_PE_ALPHA_COLOR_EXT0_G(x) (((x) << VIVS_PE_ALPHA_COLOR_EXT0_G__SHIFT) & VIVS_PE_ALPHA_COLOR_EXT0_G__MASK) 1141 1142 #define VIVS_PE_ALPHA_COLOR_EXT1 0x000014b4 1143 #define VIVS_PE_ALPHA_COLOR_EXT1_R__MASK 0x0000ffff 1144 #define VIVS_PE_ALPHA_COLOR_EXT1_R__SHIFT 0 1145 #define VIVS_PE_ALPHA_COLOR_EXT1_R(x) (((x) << VIVS_PE_ALPHA_COLOR_EXT1_R__SHIFT) & VIVS_PE_ALPHA_COLOR_EXT1_R__MASK) 1146 #define VIVS_PE_ALPHA_COLOR_EXT1_A__MASK 0xffff0000 1147 #define VIVS_PE_ALPHA_COLOR_EXT1_A__SHIFT 16 1148 #define VIVS_PE_ALPHA_COLOR_EXT1_A(x) (((x) << VIVS_PE_ALPHA_COLOR_EXT1_A__SHIFT) & VIVS_PE_ALPHA_COLOR_EXT1_A__MASK) 1149 1150 #define VIVS_PE_STENCIL_CONFIG_EXT2 0x000014b8 1151 #define VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK__MASK 0x000000ff 1152 #define VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK__SHIFT 0 1153 #define VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK__MASK) 1154 #define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__MASK 0x0000ff00 1155 #define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__SHIFT 8 1156 #define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__MASK) 1157 1158 #define VIVS_PE_MEM_CONFIG 0x000014bc 1159 #define VIVS_PE_MEM_CONFIG_COLOR_TS_MODE__MASK 0x01000000 1160 #define VIVS_PE_MEM_CONFIG_COLOR_TS_MODE__SHIFT 24 1161 #define VIVS_PE_MEM_CONFIG_COLOR_TS_MODE(x) (((x) << VIVS_PE_MEM_CONFIG_COLOR_TS_MODE__SHIFT) & VIVS_PE_MEM_CONFIG_COLOR_TS_MODE__MASK) 1162 #define VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE__MASK 0x04000000 1163 #define VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE__SHIFT 26 1164 #define VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE(x) (((x) << VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE__SHIFT) & VIVS_PE_MEM_CONFIG_DEPTH_TS_MODE__MASK) 1165 1166 #define VIVS_PE_HALTI4_UNK014C0 0x000014c0 1167 1168 #define VIVS_PE_ROBUSTNESS_UNK014C4 0x000014c4 1169 1170 #define VIVS_PE_RT_CONFIG_4(i0) (0x00001580 + 0x4*(i0)) 1171 #define VIVS_PE_RT_CONFIG_4__ESIZE 0x00000004 1172 #define VIVS_PE_RT_CONFIG_4__LEN 0x00000003 1173 1174 #define VIVS_PE_RT_ADDR_8(i0) (0x00000000 + 0x20*(i0)) 1175 #define VIVS_PE_RT_ADDR_8__ESIZE 0x00000020 1176 #define VIVS_PE_RT_ADDR_8__LEN 0x00000008 1177 1178 #define VIVS_PE_RT_ADDR_8_PIPE(i0, i1) (0x00014800 + 0x20*(i0) + 0x4*(i1)) 1179 #define VIVS_PE_RT_ADDR_8_PIPE__ESIZE 0x00000004 1180 #define VIVS_PE_RT_ADDR_8_PIPE__LEN 0x00000008 1181 1182 #define VIVS_PE_RT_CONFIG_8(i0) (0x00014900 + 0x4*(i0)) 1183 #define VIVS_PE_RT_CONFIG_8__ESIZE 0x00000004 1184 #define VIVS_PE_RT_CONFIG_8__LEN 0x00000008 1185 1186 #define VIVS_PE_HALTI5_RT_COLORMASK(i0) (0x00014920 + 0x4*(i0)) 1187 #define VIVS_PE_HALTI5_RT_COLORMASK__ESIZE 0x00000004 1188 #define VIVS_PE_HALTI5_RT_COLORMASK__LEN 0x00000007 1189 #define VIVS_PE_HALTI5_RT_COLORMASK_COMPONENTS__MASK 0x000000f0 1190 #define VIVS_PE_HALTI5_RT_COLORMASK_COMPONENTS__SHIFT 4 1191 #define VIVS_PE_HALTI5_RT_COLORMASK_COMPONENTS(x) (((x) << VIVS_PE_HALTI5_RT_COLORMASK_COMPONENTS__SHIFT) & VIVS_PE_HALTI5_RT_COLORMASK_COMPONENTS__MASK) 1192 #define VIVS_PE_HALTI5_RT_COLORMASK_OVERWRITE 0x00000100 1193 1194 #define VIVS_PE_HALTI5_RT_ALPHA_OP(i0) (0x00014940 + 0x4*(i0)) 1195 #define VIVS_PE_HALTI5_RT_ALPHA_OP__ESIZE 0x00000004 1196 #define VIVS_PE_HALTI5_RT_ALPHA_OP__LEN 0x00000007 1197 #define VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_TEST 0x00000001 1198 #define VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_FUNC__MASK 0x00000070 1199 #define VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_FUNC__SHIFT 4 1200 #define VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_FUNC(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_FUNC__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_FUNC__MASK) 1201 #define VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_REF__MASK 0xffff0000 1202 #define VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_REF__SHIFT 16 1203 #define VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_REF(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_REF__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_OP_ALPHA_REF__MASK) 1204 1205 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG(i0) (0x00014960 + 0x4*(i0)) 1206 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG__ESIZE 0x00000004 1207 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG__LEN 0x00000007 1208 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_BLEND_ENABLE_COLOR 0x00000001 1209 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_BLEND_ENABLE_COLOR_MASK 0x00000002 1210 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_COLOR_MASK 0x00000004 1211 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_COLOR_MASK 0x00000008 1212 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_COLOR__MASK 0x000000f0 1213 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_COLOR__SHIFT 4 1214 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_COLOR(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_COLOR__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_COLOR__MASK) 1215 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_COLOR__MASK 0x00000f00 1216 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_COLOR__SHIFT 8 1217 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_COLOR(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_COLOR__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_COLOR__MASK) 1218 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_COLOR__MASK 0x00007000 1219 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_COLOR__SHIFT 12 1220 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_COLOR(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_COLOR__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_COLOR__MASK) 1221 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_COLOR_MASK 0x00008000 1222 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA 0x00010000 1223 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA_MASK 0x00020000 1224 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_ALPHA_MASK 0x00040000 1225 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_ALPHA_MASK 0x00080000 1226 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_ALPHA__MASK 0x00f00000 1227 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_ALPHA__SHIFT 20 1228 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_ALPHA(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_ALPHA__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_CONFIG_SRC_FUNC_ALPHA__MASK) 1229 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_ALPHA__MASK 0x0f000000 1230 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_ALPHA__SHIFT 24 1231 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_ALPHA(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_ALPHA__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_CONFIG_DST_FUNC_ALPHA__MASK) 1232 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_ALPHA__MASK 0x70000000 1233 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_ALPHA__SHIFT 28 1234 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_ALPHA(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_ALPHA__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_ALPHA__MASK) 1235 #define VIVS_PE_HALTI5_RT_ALPHA_CONFIG_EQ_ALPHA_MASK 0x80000000 1236 1237 #define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0(i0) (0x00014980 + 0x4*(i0)) 1238 #define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0__ESIZE 0x00000004 1239 #define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0__LEN 0x00000007 1240 #define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0_B__MASK 0x0000ffff 1241 #define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0_B__SHIFT 0 1242 #define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0_B(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0_B__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0_B__MASK) 1243 #define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0_G__MASK 0xffff0000 1244 #define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0_G__SHIFT 16 1245 #define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0_G(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0_G__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT0_G__MASK) 1246 1247 #define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1(i0) (0x000149a0 + 0x4*(i0)) 1248 #define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1__ESIZE 0x00000004 1249 #define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1__LEN 0x00000007 1250 #define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1_R__MASK 0x0000ffff 1251 #define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1_R__SHIFT 0 1252 #define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1_R(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1_R__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1_R__MASK) 1253 #define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1_A__MASK 0xffff0000 1254 #define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1_A__SHIFT 16 1255 #define VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1_A(x) (((x) << VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1_A__SHIFT) & VIVS_PE_HALTI5_RT_ALPHA_COLOR_EXT1_A__MASK) 1256 1257 #define VIVS_PE_ROBUSTNESS_UNK149C0(i0) (0x000149c0 + 0x4*(i0)) 1258 #define VIVS_PE_ROBUSTNESS_UNK149C0__ESIZE 0x00000004 1259 #define VIVS_PE_ROBUSTNESS_UNK149C0__LEN 0x00000008 1260 1261 #define VIVS_CO 0x00000000 1262 1263 #define VIVS_CO_UNK03008 0x00003008 1264 1265 #define VIVS_CO_KICKER 0x0000300c 1266 1267 #define VIVS_CO_UNK03010 0x00003010 1268 1269 #define VIVS_CO_UNK03014 0x00003014 1270 1271 #define VIVS_CO_UNK03018 0x00003018 1272 1273 #define VIVS_CO_UNK0301C 0x0000301c 1274 1275 #define VIVS_CO_UNK03020 0x00003020 1276 1277 #define VIVS_CO_UNK03024 0x00003024 1278 1279 #define VIVS_CO_UNK03040 0x00003040 1280 1281 #define VIVS_CO_UNK03044 0x00003044 1282 1283 #define VIVS_CO_UNK03048 0x00003048 1284 1285 #define VIVS_CO_ICACHE_UNK0304C 0x0000304c 1286 1287 #define VIVS_CO_SAMPLER(i0) (0x00000000 + 0x4*(i0)) 1288 #define VIVS_CO_SAMPLER__ESIZE 0x00000004 1289 #define VIVS_CO_SAMPLER__LEN 0x00000008 1290 1291 #define VIVS_CO_SAMPLER_UNK03060(i0) (0x00003060 + 0x4*(i0)) 1292 1293 #define VIVS_CO_SAMPLER_UNK03080(i0) (0x00003080 + 0x4*(i0)) 1294 1295 #define VIVS_CO_SAMPLER_UNK030A0(i0) (0x000030a0 + 0x4*(i0)) 1296 1297 #define VIVS_CO_SAMPLER_UNK030C0(i0) (0x000030c0 + 0x4*(i0)) 1298 1299 #define VIVS_CO_SAMPLER_UNK030E0(i0) (0x000030e0 + 0x4*(i0)) 1300 1301 #define VIVS_CO_SAMPLER_UNK03100(i0) (0x00003100 + 0x4*(i0)) 1302 1303 #define VIVS_CO_SAMPLER_UNK03120(i0) (0x00003120 + 0x4*(i0)) 1304 1305 #define VIVS_CO_SAMPLER_UNK03140(i0) (0x00003140 + 0x4*(i0)) 1306 1307 #define VIVS_CO_SAMPLER_UNK03160(i0) (0x00003160 + 0x4*(i0)) 1308 1309 #define VIVS_CO_SAMPLER_UNK03180(i0) (0x00003180 + 0x4*(i0)) 1310 1311 #define VIVS_CO_SAMPLER_UNK031A0(i0) (0x000031a0 + 0x4*(i0)) 1312 1313 #define VIVS_CO_SAMPLER_UNK031C0(i0) (0x000031c0 + 0x4*(i0)) 1314 1315 #define VIVS_CO_SAMPLER_UNK031E0(i0) (0x000031e0 + 0x4*(i0)) 1316 1317 #define VIVS_CO_ADDR_UNK03200(i0) (0x00003200 + 0x20*(i0)) 1318 #define VIVS_CO_ADDR_UNK03200__ESIZE 0x00000020 1319 #define VIVS_CO_ADDR_UNK03200__LEN 0x00000008 1320 1321 #define VIVS_CO_ADDR_UNK03200_PPIPE(i0, i1) (0x00003200 + 0x20*(i0) + 0x4*(i1)) 1322 #define VIVS_CO_ADDR_UNK03200_PPIPE__ESIZE 0x00000004 1323 #define VIVS_CO_ADDR_UNK03200_PPIPE__LEN 0x00000008 1324 1325 #define VIVS_RS 0x00000000 1326 1327 #define VIVS_RS_KICKER 0x00001600 1328 1329 #define VIVS_RS_CONFIG 0x00001604 1330 #define VIVS_RS_CONFIG_SOURCE_FORMAT__MASK 0x0000001f 1331 #define VIVS_RS_CONFIG_SOURCE_FORMAT__SHIFT 0 1332 #define VIVS_RS_CONFIG_SOURCE_FORMAT(x) (((x) << VIVS_RS_CONFIG_SOURCE_FORMAT__SHIFT) & VIVS_RS_CONFIG_SOURCE_FORMAT__MASK) 1333 #define VIVS_RS_CONFIG_DOWNSAMPLE_X 0x00000020 1334 #define VIVS_RS_CONFIG_DOWNSAMPLE_Y 0x00000040 1335 #define VIVS_RS_CONFIG_SOURCE_TILED 0x00000080 1336 #define VIVS_RS_CONFIG_DEST_FORMAT__MASK 0x00001f00 1337 #define VIVS_RS_CONFIG_DEST_FORMAT__SHIFT 8 1338 #define VIVS_RS_CONFIG_DEST_FORMAT(x) (((x) << VIVS_RS_CONFIG_DEST_FORMAT__SHIFT) & VIVS_RS_CONFIG_DEST_FORMAT__MASK) 1339 #define VIVS_RS_CONFIG_DEST_TILED 0x00004000 1340 #define VIVS_RS_CONFIG_SWAP_RB 0x20000000 1341 #define VIVS_RS_CONFIG_FLIP 0x40000000 1342 1343 #define VIVS_RS_SOURCE_ADDR 0x00001608 1344 1345 #define VIVS_RS_SOURCE_STRIDE 0x0000160c 1346 #define VIVS_RS_SOURCE_STRIDE_STRIDE__MASK 0x0003ffff 1347 #define VIVS_RS_SOURCE_STRIDE_STRIDE__SHIFT 0 1348 #define VIVS_RS_SOURCE_STRIDE_STRIDE(x) (((x) << VIVS_RS_SOURCE_STRIDE_STRIDE__SHIFT) & VIVS_RS_SOURCE_STRIDE_STRIDE__MASK) 1349 #define VIVS_RS_SOURCE_STRIDE_TS_MODE__MASK 0x20000000 1350 #define VIVS_RS_SOURCE_STRIDE_TS_MODE__SHIFT 29 1351 #define VIVS_RS_SOURCE_STRIDE_TS_MODE(x) (((x) << VIVS_RS_SOURCE_STRIDE_TS_MODE__SHIFT) & VIVS_RS_SOURCE_STRIDE_TS_MODE__MASK) 1352 #define VIVS_RS_SOURCE_STRIDE_SUPER_TILED_NEW 0x08000000 1353 #define VIVS_RS_SOURCE_STRIDE_MULTI 0x40000000 1354 #define VIVS_RS_SOURCE_STRIDE_TILING 0x80000000 1355 1356 #define VIVS_RS_DEST_ADDR 0x00001610 1357 1358 #define VIVS_RS_DEST_STRIDE 0x00001614 1359 #define VIVS_RS_DEST_STRIDE_STRIDE__MASK 0x0003ffff 1360 #define VIVS_RS_DEST_STRIDE_STRIDE__SHIFT 0 1361 #define VIVS_RS_DEST_STRIDE_STRIDE(x) (((x) << VIVS_RS_DEST_STRIDE_STRIDE__SHIFT) & VIVS_RS_DEST_STRIDE_STRIDE__MASK) 1362 #define VIVS_RS_DEST_STRIDE_SUPER_TILED_NEW 0x08000000 1363 #define VIVS_RS_DEST_STRIDE_MULTI 0x40000000 1364 #define VIVS_RS_DEST_STRIDE_TILING 0x80000000 1365 1366 #define VIVS_RS_WINDOW_SIZE 0x00001620 1367 #define VIVS_RS_WINDOW_SIZE_HEIGHT__MASK 0xffff0000 1368 #define VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT 16 1369 #define VIVS_RS_WINDOW_SIZE_HEIGHT(x) (((x) << VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT) & VIVS_RS_WINDOW_SIZE_HEIGHT__MASK) 1370 #define VIVS_RS_WINDOW_SIZE_WIDTH__MASK 0x0000ffff 1371 #define VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT 0 1372 #define VIVS_RS_WINDOW_SIZE_WIDTH(x) (((x) << VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT) & VIVS_RS_WINDOW_SIZE_WIDTH__MASK) 1373 1374 #define VIVS_RS_DITHER(i0) (0x00001630 + 0x4*(i0)) 1375 #define VIVS_RS_DITHER__ESIZE 0x00000004 1376 #define VIVS_RS_DITHER__LEN 0x00000002 1377 1378 #define VIVS_RS_CLEAR_CONTROL 0x0000163c 1379 #define VIVS_RS_CLEAR_CONTROL_BITS__MASK 0x0000ffff 1380 #define VIVS_RS_CLEAR_CONTROL_BITS__SHIFT 0 1381 #define VIVS_RS_CLEAR_CONTROL_BITS(x) (((x) << VIVS_RS_CLEAR_CONTROL_BITS__SHIFT) & VIVS_RS_CLEAR_CONTROL_BITS__MASK) 1382 #define VIVS_RS_CLEAR_CONTROL_MODE__MASK 0x00030000 1383 #define VIVS_RS_CLEAR_CONTROL_MODE__SHIFT 16 1384 #define VIVS_RS_CLEAR_CONTROL_MODE_DISABLED 0x00000000 1385 #define VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1 0x00010000 1386 #define VIVS_RS_CLEAR_CONTROL_MODE_ENABLED4 0x00020000 1387 #define VIVS_RS_CLEAR_CONTROL_MODE_ENABLED4_2 0x00030000 1388 1389 #define VIVS_RS_FILL_VALUE(i0) (0x00001640 + 0x4*(i0)) 1390 #define VIVS_RS_FILL_VALUE__ESIZE 0x00000004 1391 #define VIVS_RS_FILL_VALUE__LEN 0x00000004 1392 1393 #define VIVS_RS_EXTRA_CONFIG 0x000016a0 1394 #define VIVS_RS_EXTRA_CONFIG_AA__MASK 0x00000003 1395 #define VIVS_RS_EXTRA_CONFIG_AA__SHIFT 0 1396 #define VIVS_RS_EXTRA_CONFIG_AA(x) (((x) << VIVS_RS_EXTRA_CONFIG_AA__SHIFT) & VIVS_RS_EXTRA_CONFIG_AA__MASK) 1397 #define VIVS_RS_EXTRA_CONFIG_ENDIAN__MASK 0x00000300 1398 #define VIVS_RS_EXTRA_CONFIG_ENDIAN__SHIFT 8 1399 #define VIVS_RS_EXTRA_CONFIG_ENDIAN(x) (((x) << VIVS_RS_EXTRA_CONFIG_ENDIAN__SHIFT) & VIVS_RS_EXTRA_CONFIG_ENDIAN__MASK) 1400 #define VIVS_RS_EXTRA_CONFIG_UNK20 0x00100000 1401 #define VIVS_RS_EXTRA_CONFIG_TS_MODE__MASK 0x01000000 1402 #define VIVS_RS_EXTRA_CONFIG_TS_MODE__SHIFT 24 1403 #define VIVS_RS_EXTRA_CONFIG_TS_MODE(x) (((x) << VIVS_RS_EXTRA_CONFIG_TS_MODE__SHIFT) & VIVS_RS_EXTRA_CONFIG_TS_MODE__MASK) 1404 #define VIVS_RS_EXTRA_CONFIG_UNK28 0x10000000 1405 1406 #define VIVS_RS_KICKER_INPLACE 0x000016b0 1407 1408 #define VIVS_RS_UNK016B4 0x000016b4 1409 1410 #define VIVS_RS_SINGLE_BUFFER 0x000016b8 1411 #define VIVS_RS_SINGLE_BUFFER_ENABLE 0x00000001 1412 1413 #define VIVS_RS_PIPE(i0) (0x00000000 + 0x4*(i0)) 1414 #define VIVS_RS_PIPE__ESIZE 0x00000004 1415 #define VIVS_RS_PIPE__LEN 0x00000008 1416 1417 #define VIVS_RS_PIPE_SOURCE_ADDR(i0) (0x000016c0 + 0x4*(i0)) 1418 1419 #define VIVS_RS_PIPE_DEST_ADDR(i0) (0x000016e0 + 0x4*(i0)) 1420 1421 #define VIVS_RS_PIPE_OFFSET(i0) (0x00001700 + 0x4*(i0)) 1422 #define VIVS_RS_PIPE_OFFSET_X__MASK 0x0000ffff 1423 #define VIVS_RS_PIPE_OFFSET_X__SHIFT 0 1424 #define VIVS_RS_PIPE_OFFSET_X(x) (((x) << VIVS_RS_PIPE_OFFSET_X__SHIFT) & VIVS_RS_PIPE_OFFSET_X__MASK) 1425 #define VIVS_RS_PIPE_OFFSET_Y__MASK 0xffff0000 1426 #define VIVS_RS_PIPE_OFFSET_Y__SHIFT 16 1427 #define VIVS_RS_PIPE_OFFSET_Y(x) (((x) << VIVS_RS_PIPE_OFFSET_Y__SHIFT) & VIVS_RS_PIPE_OFFSET_Y__MASK) 1428 1429 #define VIVS_TS 0x00000000 1430 1431 #define VIVS_TS_FLUSH_CACHE 0x00001650 1432 #define VIVS_TS_FLUSH_CACHE_FLUSH 0x00000001 1433 1434 #define VIVS_TS_MEM_CONFIG 0x00001654 1435 #define VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR 0x00000001 1436 #define VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR 0x00000002 1437 #define VIVS_TS_MEM_CONFIG_DEPTH_16BPP 0x00000008 1438 #define VIVS_TS_MEM_CONFIG_DEPTH_AUTO_DISABLE 0x00000010 1439 #define VIVS_TS_MEM_CONFIG_COLOR_AUTO_DISABLE 0x00000020 1440 #define VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION 0x00000040 1441 #define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION 0x00000080 1442 #define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__MASK 0x00000f00 1443 #define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__SHIFT 8 1444 #define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(x) (((x) << VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__SHIFT) & VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__MASK) 1445 #define VIVS_TS_MEM_CONFIG_UNK12 0x00001000 1446 #define VIVS_TS_MEM_CONFIG_HDEPTH_AUTO_DISABLE 0x00002000 1447 #define VIVS_TS_MEM_CONFIG_STENCIL_ENABLE 0x00004000 1448 #define VIVS_TS_MEM_CONFIG_UNK21 0x00200000 1449 1450 #define VIVS_TS_COLOR_STATUS_BASE 0x00001658 1451 1452 #define VIVS_TS_COLOR_SURFACE_BASE 0x0000165c 1453 1454 #define VIVS_TS_COLOR_CLEAR_VALUE 0x00001660 1455 1456 #define VIVS_TS_DEPTH_STATUS_BASE 0x00001664 1457 1458 #define VIVS_TS_DEPTH_SURFACE_BASE 0x00001668 1459 1460 #define VIVS_TS_DEPTH_CLEAR_VALUE 0x0000166c 1461 1462 #define VIVS_TS_DEPTH_AUTO_DISABLE_COUNT 0x00001670 1463 1464 #define VIVS_TS_COLOR_AUTO_DISABLE_COUNT 0x00001674 1465 1466 #define VIVS_TS_HDEPTH_STATUS_BASE 0x000016a4 1467 1468 #define VIVS_TS_HDEPTH_CLEAR_VALUE 0x000016a8 1469 1470 #define VIVS_TS_HDEPTH_SIZE 0x000016ac 1471 1472 #define VIVS_TS_COLOR_CLEAR_VALUE_EXT 0x000016bc 1473 1474 #define VIVS_TS_SAMPLER(i0) (0x00000000 + 0x4*(i0)) 1475 #define VIVS_TS_SAMPLER__ESIZE 0x00000004 1476 #define VIVS_TS_SAMPLER__LEN 0x00000008 1477 1478 #define VIVS_TS_SAMPLER_CONFIG(i0) (0x00001720 + 0x4*(i0)) 1479 #define VIVS_TS_SAMPLER_CONFIG_ENABLE 0x00000001 1480 #define VIVS_TS_SAMPLER_CONFIG_COMPRESSION 0x00000002 1481 #define VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT__MASK 0x000000f0 1482 #define VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT__SHIFT 4 1483 #define VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT(x) (((x) << VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT__SHIFT) & VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT__MASK) 1484 #define VIVS_TS_SAMPLER_CONFIG_UNK11__MASK 0x00003800 1485 #define VIVS_TS_SAMPLER_CONFIG_UNK11__SHIFT 11 1486 #define VIVS_TS_SAMPLER_CONFIG_UNK11(x) (((x) << VIVS_TS_SAMPLER_CONFIG_UNK11__SHIFT) & VIVS_TS_SAMPLER_CONFIG_UNK11__MASK) 1487 1488 #define VIVS_TS_SAMPLER_STATUS_BASE(i0) (0x00001740 + 0x4*(i0)) 1489 1490 #define VIVS_TS_SAMPLER_CLEAR_VALUE(i0) (0x00001760 + 0x4*(i0)) 1491 1492 #define VIVS_TS_SAMPLER_CLEAR_VALUE2(i0) (0x00001780 + 0x4*(i0)) 1493 1494 #define VIVS_TS_SAMPLER_SURFACE_BASE(i0) (0x00001a80 + 0x4*(i0)) 1495 1496 #define VIVS_TS_RT(i0) (0x00000000 + 0x4*(i0)) 1497 #define VIVS_TS_RT__ESIZE 0x00000004 1498 #define VIVS_TS_RT__LEN 0x00000008 1499 1500 #define VIVS_TS_RT_CONFIG(i0) (0x000017a0 + 0x4*(i0)) 1501 #define VIVS_TS_RT_CONFIG_ENABLE 0x00000001 1502 #define VIVS_TS_RT_CONFIG_COLOR_AUTO_DISABLE 0x00000002 1503 #define VIVS_TS_RT_CONFIG_COMPRESSION 0x00000004 1504 #define VIVS_TS_RT_CONFIG_COMPRESSION_FORMAT__MASK 0x00000078 1505 #define VIVS_TS_RT_CONFIG_COMPRESSION_FORMAT__SHIFT 3 1506 #define VIVS_TS_RT_CONFIG_COMPRESSION_FORMAT(x) (((x) << VIVS_TS_RT_CONFIG_COMPRESSION_FORMAT__SHIFT) & VIVS_TS_RT_CONFIG_COMPRESSION_FORMAT__MASK) 1507 1508 #define VIVS_TS_RT_STATUS_BASE(i0) (0x000017c0 + 0x4*(i0)) 1509 1510 #define VIVS_TS_RT_SURFACE_BASE(i0) (0x000017e0 + 0x4*(i0)) 1511 1512 #define VIVS_TS_RT_CLEAR_VALUE(i0) (0x00001a00 + 0x4*(i0)) 1513 1514 #define VIVS_TS_RT_CLEAR_VALUE2(i0) (0x00001a20 + 0x4*(i0)) 1515 1516 #define VIVS_TS_RT_COLOR_AUTO_DISABLE_COUNT(i0) (0x00001a40 + 0x4*(i0)) 1517 1518 #define VIVS_YUV 0x00000000 1519 1520 #define VIVS_YUV_CONFIG 0x00001678 1521 #define VIVS_YUV_CONFIG_ENABLE 0x00000001 1522 #define VIVS_YUV_CONFIG_SOURCE_FORMAT__MASK 0x00000030 1523 #define VIVS_YUV_CONFIG_SOURCE_FORMAT__SHIFT 4 1524 #define VIVS_YUV_CONFIG_SOURCE_FORMAT(x) (((x) << VIVS_YUV_CONFIG_SOURCE_FORMAT__SHIFT) & VIVS_YUV_CONFIG_SOURCE_FORMAT__MASK) 1525 #define VIVS_YUV_CONFIG_UV_SWAP 0x00000100 1526 1527 #define VIVS_YUV_WINDOW_SIZE 0x0000167c 1528 #define VIVS_YUV_WINDOW_SIZE_HEIGHT__MASK 0xffff0000 1529 #define VIVS_YUV_WINDOW_SIZE_HEIGHT__SHIFT 16 1530 #define VIVS_YUV_WINDOW_SIZE_HEIGHT(x) (((x) << VIVS_YUV_WINDOW_SIZE_HEIGHT__SHIFT) & VIVS_YUV_WINDOW_SIZE_HEIGHT__MASK) 1531 #define VIVS_YUV_WINDOW_SIZE_WIDTH__MASK 0x0000ffff 1532 #define VIVS_YUV_WINDOW_SIZE_WIDTH__SHIFT 0 1533 #define VIVS_YUV_WINDOW_SIZE_WIDTH(x) (((x) << VIVS_YUV_WINDOW_SIZE_WIDTH__SHIFT) & VIVS_YUV_WINDOW_SIZE_WIDTH__MASK) 1534 1535 #define VIVS_YUV_Y_BASE 0x00001680 1536 1537 #define VIVS_YUV_Y_STRIDE 0x00001684 1538 1539 #define VIVS_YUV_U_BASE 0x00001688 1540 1541 #define VIVS_YUV_U_STRIDE 0x0000168c 1542 1543 #define VIVS_YUV_V_BASE 0x00001690 1544 1545 #define VIVS_YUV_V_STRIDE 0x00001694 1546 1547 #define VIVS_YUV_DEST_BASE 0x00001698 1548 1549 #define VIVS_YUV_DEST_STRIDE 0x0000169c 1550 1551 #define VIVS_TE 0x00000000 1552 1553 #define VIVS_TE_SAMPLER(i0) (0x00000000 + 0x4*(i0)) 1554 #define VIVS_TE_SAMPLER__ESIZE 0x00000004 1555 #define VIVS_TE_SAMPLER__LEN 0x0000000c 1556 1557 #define VIVS_TE_SAMPLER_CONFIG0(i0) (0x00002000 + 0x4*(i0)) 1558 #define VIVS_TE_SAMPLER_CONFIG0_TYPE__MASK 0x00000007 1559 #define VIVS_TE_SAMPLER_CONFIG0_TYPE__SHIFT 0 1560 #define VIVS_TE_SAMPLER_CONFIG0_TYPE(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_TYPE__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_TYPE__MASK) 1561 #define VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK 0x00000018 1562 #define VIVS_TE_SAMPLER_CONFIG0_UWRAP__SHIFT 3 1563 #define VIVS_TE_SAMPLER_CONFIG0_UWRAP(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_UWRAP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK) 1564 #define VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK 0x00000060 1565 #define VIVS_TE_SAMPLER_CONFIG0_VWRAP__SHIFT 5 1566 #define VIVS_TE_SAMPLER_CONFIG0_VWRAP(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_VWRAP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK) 1567 #define VIVS_TE_SAMPLER_CONFIG0_MIN__MASK 0x00000180 1568 #define VIVS_TE_SAMPLER_CONFIG0_MIN__SHIFT 7 1569 #define VIVS_TE_SAMPLER_CONFIG0_MIN(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_MIN__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MIN__MASK) 1570 #define VIVS_TE_SAMPLER_CONFIG0_MIP__MASK 0x00000600 1571 #define VIVS_TE_SAMPLER_CONFIG0_MIP__SHIFT 9 1572 #define VIVS_TE_SAMPLER_CONFIG0_MIP(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_MIP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MIP__MASK) 1573 #define VIVS_TE_SAMPLER_CONFIG0_MAG__MASK 0x00001800 1574 #define VIVS_TE_SAMPLER_CONFIG0_MAG__SHIFT 11 1575 #define VIVS_TE_SAMPLER_CONFIG0_MAG(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_MAG__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MAG__MASK) 1576 #define VIVS_TE_SAMPLER_CONFIG0_FORMAT__MASK 0x0003e000 1577 #define VIVS_TE_SAMPLER_CONFIG0_FORMAT__SHIFT 13 1578 #define VIVS_TE_SAMPLER_CONFIG0_FORMAT(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_FORMAT__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_FORMAT__MASK) 1579 #define VIVS_TE_SAMPLER_CONFIG0_ROUND_UV 0x00080000 1580 #define VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE__MASK 0x00300000 1581 #define VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE__SHIFT 20 1582 #define VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE__MASK) 1583 #define VIVS_TE_SAMPLER_CONFIG0_ENDIAN__MASK 0x00c00000 1584 #define VIVS_TE_SAMPLER_CONFIG0_ENDIAN__SHIFT 22 1585 #define VIVS_TE_SAMPLER_CONFIG0_ENDIAN(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_ENDIAN__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_ENDIAN__MASK) 1586 #define VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__MASK 0xff000000 1587 #define VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT 24 1588 #define VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__MASK) 1589 1590 #define VIVS_TE_SAMPLER_SIZE(i0) (0x00002040 + 0x4*(i0)) 1591 #define VIVS_TE_SAMPLER_SIZE_WIDTH__MASK 0x0000ffff 1592 #define VIVS_TE_SAMPLER_SIZE_WIDTH__SHIFT 0 1593 #define VIVS_TE_SAMPLER_SIZE_WIDTH(x) (((x) << VIVS_TE_SAMPLER_SIZE_WIDTH__SHIFT) & VIVS_TE_SAMPLER_SIZE_WIDTH__MASK) 1594 #define VIVS_TE_SAMPLER_SIZE_HEIGHT__MASK 0xffff0000 1595 #define VIVS_TE_SAMPLER_SIZE_HEIGHT__SHIFT 16 1596 #define VIVS_TE_SAMPLER_SIZE_HEIGHT(x) (((x) << VIVS_TE_SAMPLER_SIZE_HEIGHT__SHIFT) & VIVS_TE_SAMPLER_SIZE_HEIGHT__MASK) 1597 1598 #define VIVS_TE_SAMPLER_LOG_SIZE(i0) (0x00002080 + 0x4*(i0)) 1599 #define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__MASK 0x000003ff 1600 #define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__SHIFT 0 1601 #define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(x) (((x) << VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__SHIFT) & VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__MASK) 1602 #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__MASK 0x000ffc00 1603 #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT 10 1604 #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(x) (((x) << VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT) & VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__MASK) 1605 #define VIVS_TE_SAMPLER_LOG_SIZE_ASTC 0x10000000 1606 #define VIVS_TE_SAMPLER_LOG_SIZE_INT_FILTER 0x20000000 1607 #define VIVS_TE_SAMPLER_LOG_SIZE_SRGB 0x80000000 1608 1609 #define VIVS_TE_SAMPLER_LOD_CONFIG(i0) (0x000020c0 + 0x4*(i0)) 1610 #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE 0x00000001 1611 #define VIVS_TE_SAMPLER_LOD_CONFIG_MAX__MASK 0x000007fe 1612 #define VIVS_TE_SAMPLER_LOD_CONFIG_MAX__SHIFT 1 1613 #define VIVS_TE_SAMPLER_LOD_CONFIG_MAX(x) (((x) << VIVS_TE_SAMPLER_LOD_CONFIG_MAX__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_MAX__MASK) 1614 #define VIVS_TE_SAMPLER_LOD_CONFIG_MIN__MASK 0x001ff800 1615 #define VIVS_TE_SAMPLER_LOD_CONFIG_MIN__SHIFT 11 1616 #define VIVS_TE_SAMPLER_LOD_CONFIG_MIN(x) (((x) << VIVS_TE_SAMPLER_LOD_CONFIG_MIN__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_MIN__MASK) 1617 #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__MASK 0x7fe00000 1618 #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__SHIFT 21 1619 #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS(x) (((x) << VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__MASK) 1620 1621 #define VIVS_TE_SAMPLER_UNK02100(i0) (0x00002100 + 0x4*(i0)) 1622 1623 #define VIVS_TE_SAMPLER_UNK02140(i0) (0x00002140 + 0x4*(i0)) 1624 1625 #define VIVS_TE_SAMPLER_3D_CONFIG(i0) (0x00002180 + 0x4*(i0)) 1626 #define VIVS_TE_SAMPLER_3D_CONFIG_DEPTH__MASK 0x00003fff 1627 #define VIVS_TE_SAMPLER_3D_CONFIG_DEPTH__SHIFT 0 1628 #define VIVS_TE_SAMPLER_3D_CONFIG_DEPTH(x) (((x) << VIVS_TE_SAMPLER_3D_CONFIG_DEPTH__SHIFT) & VIVS_TE_SAMPLER_3D_CONFIG_DEPTH__MASK) 1629 #define VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK 0x03ff0000 1630 #define VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT 16 1631 #define VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH(x) (((x) << VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT) & VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK) 1632 #define VIVS_TE_SAMPLER_3D_CONFIG_WRAP__MASK 0x30000000 1633 #define VIVS_TE_SAMPLER_3D_CONFIG_WRAP__SHIFT 28 1634 #define VIVS_TE_SAMPLER_3D_CONFIG_WRAP(x) (((x) << VIVS_TE_SAMPLER_3D_CONFIG_WRAP__SHIFT) & VIVS_TE_SAMPLER_3D_CONFIG_WRAP__MASK) 1635 1636 #define VIVS_TE_SAMPLER_CONFIG1(i0) (0x000021c0 + 0x4*(i0)) 1637 #define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__MASK 0x0000003f 1638 #define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT 0 1639 #define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__MASK) 1640 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__MASK 0x00000700 1641 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT 8 1642 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__MASK) 1643 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__MASK 0x00007000 1644 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT 12 1645 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__MASK) 1646 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__MASK 0x00070000 1647 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT 16 1648 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__MASK) 1649 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK 0x00700000 1650 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT 20 1651 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK) 1652 #define VIVS_TE_SAMPLER_CONFIG1_TS_MODE__MASK 0x00800000 1653 #define VIVS_TE_SAMPLER_CONFIG1_TS_MODE__SHIFT 23 1654 #define VIVS_TE_SAMPLER_CONFIG1_TS_MODE(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_TS_MODE__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_TS_MODE__MASK) 1655 #define VIVS_TE_SAMPLER_CONFIG1_TEXTURE_ARRAY 0x01000000 1656 #define VIVS_TE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP 0x02000000 1657 #define VIVS_TE_SAMPLER_CONFIG1_HALIGN__MASK 0x1c000000 1658 #define VIVS_TE_SAMPLER_CONFIG1_HALIGN__SHIFT 26 1659 #define VIVS_TE_SAMPLER_CONFIG1_HALIGN(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_HALIGN__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_HALIGN__MASK) 1660 #define VIVS_TE_SAMPLER_CONFIG1_USE_TS 0x40000000 1661 1662 #define VIVS_TE_SAMPLER_UNK02200(i0) (0x00002200 + 0x4*(i0)) 1663 1664 #define VIVS_TE_SAMPLER_UNK02240(i0) (0x00002240 + 0x4*(i0)) 1665 1666 #define VIVS_TE_SAMPLER_ASTC0(i0) (0x00002280 + 0x4*(i0)) 1667 #define VIVS_TE_SAMPLER_ASTC0_ASTC_FORMAT__MASK 0x0000000f 1668 #define VIVS_TE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT 0 1669 #define VIVS_TE_SAMPLER_ASTC0_ASTC_FORMAT(x) (((x) << VIVS_TE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT) & VIVS_TE_SAMPLER_ASTC0_ASTC_FORMAT__MASK) 1670 #define VIVS_TE_SAMPLER_ASTC0_ASTC_SRGB 0x00000010 1671 #define VIVS_TE_SAMPLER_ASTC0_UNK8__MASK 0x0000ff00 1672 #define VIVS_TE_SAMPLER_ASTC0_UNK8__SHIFT 8 1673 #define VIVS_TE_SAMPLER_ASTC0_UNK8(x) (((x) << VIVS_TE_SAMPLER_ASTC0_UNK8__SHIFT) & VIVS_TE_SAMPLER_ASTC0_UNK8__MASK) 1674 #define VIVS_TE_SAMPLER_ASTC0_UNK16__MASK 0x00ff0000 1675 #define VIVS_TE_SAMPLER_ASTC0_UNK16__SHIFT 16 1676 #define VIVS_TE_SAMPLER_ASTC0_UNK16(x) (((x) << VIVS_TE_SAMPLER_ASTC0_UNK16__SHIFT) & VIVS_TE_SAMPLER_ASTC0_UNK16__MASK) 1677 #define VIVS_TE_SAMPLER_ASTC0_UNK24__MASK 0xff000000 1678 #define VIVS_TE_SAMPLER_ASTC0_UNK24__SHIFT 24 1679 #define VIVS_TE_SAMPLER_ASTC0_UNK24(x) (((x) << VIVS_TE_SAMPLER_ASTC0_UNK24__SHIFT) & VIVS_TE_SAMPLER_ASTC0_UNK24__MASK) 1680 1681 #define VIVS_TE_SAMPLER_ASTC1(i0) (0x00002300 + 0x4*(i0)) 1682 1683 #define VIVS_TE_SAMPLER_ASTC2(i0) (0x00002380 + 0x4*(i0)) 1684 1685 #define VIVS_TE_SAMPLER_ASTC3(i0) (0x00002340 + 0x4*(i0)) 1686 1687 #define VIVS_TE_SAMPLER_LOD_ADDR(i0, i1) (0x00002400 + 0x4*(i0) + 0x40*(i1)) 1688 #define VIVS_TE_SAMPLER_LOD_ADDR__ESIZE 0x00000040 1689 #define VIVS_TE_SAMPLER_LOD_ADDR__LEN 0x0000000e 1690 1691 #define VIVS_TE_SAMPLER_LINEAR_STRIDE(i0, i1) (0x00002c00 + 0x4*(i0) + 0x40*(i1)) 1692 #define VIVS_TE_SAMPLER_LINEAR_STRIDE__ESIZE 0x00000040 1693 #define VIVS_TE_SAMPLER_LINEAR_STRIDE__LEN 0x0000000e 1694 1695 #define VIVS_NTE 0x00000000 1696 1697 #define VIVS_NTE_SAMPLER(i0) (0x00000000 + 0x4*(i0)) 1698 #define VIVS_NTE_SAMPLER__ESIZE 0x00000004 1699 #define VIVS_NTE_SAMPLER__LEN 0x00000020 1700 1701 #define VIVS_NTE_SAMPLER_CONFIG0(i0) (0x00010000 + 0x4*(i0)) 1702 #define VIVS_NTE_SAMPLER_CONFIG0_TYPE__MASK 0x00000007 1703 #define VIVS_NTE_SAMPLER_CONFIG0_TYPE__SHIFT 0 1704 #define VIVS_NTE_SAMPLER_CONFIG0_TYPE(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_TYPE__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_TYPE__MASK) 1705 #define VIVS_NTE_SAMPLER_CONFIG0_UWRAP__MASK 0x00000018 1706 #define VIVS_NTE_SAMPLER_CONFIG0_UWRAP__SHIFT 3 1707 #define VIVS_NTE_SAMPLER_CONFIG0_UWRAP(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_UWRAP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_UWRAP__MASK) 1708 #define VIVS_NTE_SAMPLER_CONFIG0_VWRAP__MASK 0x00000060 1709 #define VIVS_NTE_SAMPLER_CONFIG0_VWRAP__SHIFT 5 1710 #define VIVS_NTE_SAMPLER_CONFIG0_VWRAP(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_VWRAP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_VWRAP__MASK) 1711 #define VIVS_NTE_SAMPLER_CONFIG0_MIN__MASK 0x00000180 1712 #define VIVS_NTE_SAMPLER_CONFIG0_MIN__SHIFT 7 1713 #define VIVS_NTE_SAMPLER_CONFIG0_MIN(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_MIN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MIN__MASK) 1714 #define VIVS_NTE_SAMPLER_CONFIG0_MIP__MASK 0x00000600 1715 #define VIVS_NTE_SAMPLER_CONFIG0_MIP__SHIFT 9 1716 #define VIVS_NTE_SAMPLER_CONFIG0_MIP(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_MIP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MIP__MASK) 1717 #define VIVS_NTE_SAMPLER_CONFIG0_MAG__MASK 0x00001800 1718 #define VIVS_NTE_SAMPLER_CONFIG0_MAG__SHIFT 11 1719 #define VIVS_NTE_SAMPLER_CONFIG0_MAG(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_MAG__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MAG__MASK) 1720 #define VIVS_NTE_SAMPLER_CONFIG0_FORMAT__MASK 0x0003e000 1721 #define VIVS_NTE_SAMPLER_CONFIG0_FORMAT__SHIFT 13 1722 #define VIVS_NTE_SAMPLER_CONFIG0_FORMAT(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_FORMAT__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_FORMAT__MASK) 1723 #define VIVS_NTE_SAMPLER_CONFIG0_ROUND_UV 0x00080000 1724 #define VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE__MASK 0x00300000 1725 #define VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE__SHIFT 20 1726 #define VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_ADDRESSING_MODE__MASK) 1727 #define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__MASK 0x00c00000 1728 #define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__SHIFT 22 1729 #define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__MASK) 1730 #define VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__MASK 0xff000000 1731 #define VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT 24 1732 #define VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__MASK) 1733 1734 #define VIVS_NTE_SAMPLER_SIZE(i0) (0x00010080 + 0x4*(i0)) 1735 #define VIVS_NTE_SAMPLER_SIZE_WIDTH__MASK 0x0000ffff 1736 #define VIVS_NTE_SAMPLER_SIZE_WIDTH__SHIFT 0 1737 #define VIVS_NTE_SAMPLER_SIZE_WIDTH(x) (((x) << VIVS_NTE_SAMPLER_SIZE_WIDTH__SHIFT) & VIVS_NTE_SAMPLER_SIZE_WIDTH__MASK) 1738 #define VIVS_NTE_SAMPLER_SIZE_HEIGHT__MASK 0xffff0000 1739 #define VIVS_NTE_SAMPLER_SIZE_HEIGHT__SHIFT 16 1740 #define VIVS_NTE_SAMPLER_SIZE_HEIGHT(x) (((x) << VIVS_NTE_SAMPLER_SIZE_HEIGHT__SHIFT) & VIVS_NTE_SAMPLER_SIZE_HEIGHT__MASK) 1741 1742 #define VIVS_NTE_SAMPLER_LOG_SIZE(i0) (0x00010100 + 0x4*(i0)) 1743 #define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__MASK 0x000003ff 1744 #define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__SHIFT 0 1745 #define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH(x) (((x) << VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__SHIFT) & VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__MASK) 1746 #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__MASK 0x000ffc00 1747 #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT 10 1748 #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT(x) (((x) << VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT) & VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__MASK) 1749 #define VIVS_NTE_SAMPLER_LOG_SIZE_ASTC 0x10000000 1750 #define VIVS_NTE_SAMPLER_LOG_SIZE_INT_FILTER 0x20000000 1751 #define VIVS_NTE_SAMPLER_LOG_SIZE_SRGB 0x80000000 1752 1753 #define VIVS_NTE_SAMPLER_LOD_CONFIG(i0) (0x00010180 + 0x4*(i0)) 1754 #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS_ENABLE 0x00000001 1755 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__MASK 0x000007fe 1756 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__SHIFT 1 1757 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX(x) (((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__MASK) 1758 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__MASK 0x001ff800 1759 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__SHIFT 11 1760 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN(x) (((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__MASK) 1761 #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__MASK 0x7fe00000 1762 #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__SHIFT 21 1763 #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS(x) (((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__MASK) 1764 1765 #define VIVS_NTE_SAMPLER_UNK10200(i0) (0x00010200 + 0x4*(i0)) 1766 1767 #define VIVS_NTE_SAMPLER_LINEAR_STRIDE(i0, i1) (0x00010280 + 0x4*(i0) + 0x4*(i1)) 1768 #define VIVS_NTE_SAMPLER_LINEAR_STRIDE__ESIZE 0x00000004 1769 #define VIVS_NTE_SAMPLER_LINEAR_STRIDE__LEN 0x00000020 1770 1771 #define VIVS_NTE_SAMPLER_3D_CONFIG(i0) (0x00010300 + 0x4*(i0)) 1772 #define VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__MASK 0x00003fff 1773 #define VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__SHIFT 0 1774 #define VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH(x) (((x) << VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__SHIFT) & VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__MASK) 1775 #define VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK 0x03ff0000 1776 #define VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT 16 1777 #define VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH(x) (((x) << VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT) & VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK) 1778 #define VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__MASK 0x30000000 1779 #define VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__SHIFT 28 1780 #define VIVS_NTE_SAMPLER_3D_CONFIG_WRAP(x) (((x) << VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__SHIFT) & VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__MASK) 1781 1782 #define VIVS_NTE_SAMPLER_CONFIG1(i0) (0x00010380 + 0x4*(i0)) 1783 #define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__MASK 0x0000003f 1784 #define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT 0 1785 #define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__MASK) 1786 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__MASK 0x00000700 1787 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT 8 1788 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__MASK) 1789 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__MASK 0x00007000 1790 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT 12 1791 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__MASK) 1792 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__MASK 0x00070000 1793 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT 16 1794 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__MASK) 1795 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK 0x00700000 1796 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT 20 1797 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK) 1798 #define VIVS_NTE_SAMPLER_CONFIG1_TS_MODE__MASK 0x00800000 1799 #define VIVS_NTE_SAMPLER_CONFIG1_TS_MODE__SHIFT 23 1800 #define VIVS_NTE_SAMPLER_CONFIG1_TS_MODE(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_TS_MODE__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_TS_MODE__MASK) 1801 #define VIVS_NTE_SAMPLER_CONFIG1_TEXTURE_ARRAY 0x01000000 1802 #define VIVS_NTE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP 0x02000000 1803 #define VIVS_NTE_SAMPLER_CONFIG1_HALIGN__MASK 0x1c000000 1804 #define VIVS_NTE_SAMPLER_CONFIG1_HALIGN__SHIFT 26 1805 #define VIVS_NTE_SAMPLER_CONFIG1_HALIGN(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_HALIGN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_HALIGN__MASK) 1806 #define VIVS_NTE_SAMPLER_CONFIG1_USE_TS 0x40000000 1807 1808 #define VIVS_NTE_SAMPLER_UNK10400(i0) (0x00010400 + 0x4*(i0)) 1809 1810 #define VIVS_NTE_SAMPLER_UNK10480(i0) (0x00010480 + 0x4*(i0)) 1811 1812 #define VIVS_NTE_SAMPLER_ASTC0(i0) (0x00010500 + 0x4*(i0)) 1813 #define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__MASK 0x0000000f 1814 #define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT 0 1815 #define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(x) (((x) << VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__MASK) 1816 #define VIVS_NTE_SAMPLER_ASTC0_ASTC_SRGB 0x00000010 1817 #define VIVS_NTE_SAMPLER_ASTC0_UNK8__MASK 0x0000ff00 1818 #define VIVS_NTE_SAMPLER_ASTC0_UNK8__SHIFT 8 1819 #define VIVS_NTE_SAMPLER_ASTC0_UNK8(x) (((x) << VIVS_NTE_SAMPLER_ASTC0_UNK8__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_UNK8__MASK) 1820 #define VIVS_NTE_SAMPLER_ASTC0_UNK16__MASK 0x00ff0000 1821 #define VIVS_NTE_SAMPLER_ASTC0_UNK16__SHIFT 16 1822 #define VIVS_NTE_SAMPLER_ASTC0_UNK16(x) (((x) << VIVS_NTE_SAMPLER_ASTC0_UNK16__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_UNK16__MASK) 1823 #define VIVS_NTE_SAMPLER_ASTC0_UNK24__MASK 0xff000000 1824 #define VIVS_NTE_SAMPLER_ASTC0_UNK24__SHIFT 24 1825 #define VIVS_NTE_SAMPLER_ASTC0_UNK24(x) (((x) << VIVS_NTE_SAMPLER_ASTC0_UNK24__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_UNK24__MASK) 1826 1827 #define VIVS_NTE_SAMPLER_ASTC1(i0) (0x00010580 + 0x4*(i0)) 1828 1829 #define VIVS_NTE_SAMPLER_ASTC2(i0) (0x00010600 + 0x4*(i0)) 1830 1831 #define VIVS_NTE_SAMPLER_ASTC3(i0) (0x00010680 + 0x4*(i0)) 1832 1833 #define VIVS_NTE_SAMPLER_BASELOD(i0) (0x00010700 + 0x4*(i0)) 1834 #define VIVS_NTE_SAMPLER_BASELOD_BASELOD__MASK 0x0000000f 1835 #define VIVS_NTE_SAMPLER_BASELOD_BASELOD__SHIFT 0 1836 #define VIVS_NTE_SAMPLER_BASELOD_BASELOD(x) (((x) << VIVS_NTE_SAMPLER_BASELOD_BASELOD__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_BASELOD__MASK) 1837 #define VIVS_NTE_SAMPLER_BASELOD_MAXLOD__MASK 0x00000f00 1838 #define VIVS_NTE_SAMPLER_BASELOD_MAXLOD__SHIFT 8 1839 #define VIVS_NTE_SAMPLER_BASELOD_MAXLOD(x) (((x) << VIVS_NTE_SAMPLER_BASELOD_MAXLOD__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_MAXLOD__MASK) 1840 #define VIVS_NTE_SAMPLER_BASELOD_COMPARE_ENABLE 0x00010000 1841 #define VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC__MASK 0x00700000 1842 #define VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC__SHIFT 20 1843 #define VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC(x) (((x) << VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC__MASK) 1844 #define VIVS_NTE_SAMPLER_BASELOD_BASELOD_ENABLE 0x00800000 1845 1846 #define VIVS_NTE_SAMPLER_UNK10780(i0) (0x00010780 + 0x4*(i0)) 1847 1848 #define VIVS_NTE_SAMPLER_FRAC_UNK11000(i0) (0x00011000 + 0x4*(i0)) 1849 1850 #define VIVS_NTE_SAMPLER_FRAC_UNK11080(i0) (0x00011080 + 0x4*(i0)) 1851 1852 #define VIVS_NTE_SAMPLER_FRAC_UNK11100(i0) (0x00011100 + 0x4*(i0)) 1853 1854 #define VIVS_NTE_SAMPLER_FRAC_UNK11180(i0) (0x00011180 + 0x4*(i0)) 1855 1856 #define VIVS_NTE_SAMPLER_HALTI4_UNK11200(i0) (0x00011200 + 0x4*(i0)) 1857 1858 #define VIVS_NTE_SAMPLER_HALTI4_UNK11280(i0) (0x00011280 + 0x4*(i0)) 1859 1860 #define VIVS_NTE_SAMPLER_FRAC_UNK11300(i0) (0x00011300 + 0x4*(i0)) 1861 1862 #define VIVS_NTE_SAMPLER_ADDR(i0) (0x00010800 + 0x40*(i0)) 1863 #define VIVS_NTE_SAMPLER_ADDR__ESIZE 0x00000040 1864 #define VIVS_NTE_SAMPLER_ADDR__LEN 0x00000020 1865 1866 #define VIVS_NTE_SAMPLER_ADDR_LOD(i0, i1) (0x00010800 + 0x40*(i0) + 0x4*(i1)) 1867 #define VIVS_NTE_SAMPLER_ADDR_LOD__ESIZE 0x00000004 1868 #define VIVS_NTE_SAMPLER_ADDR_LOD__LEN 0x0000000e 1869 1870 #define VIVS_NTE_UNK12000(i0) (0x00012000 + 0x4*(i0)) 1871 #define VIVS_NTE_UNK12000__ESIZE 0x00000004 1872 #define VIVS_NTE_UNK12000__LEN 0x00000100 1873 1874 #define VIVS_NTE_UNK12400(i0) (0x00012400 + 0x4*(i0)) 1875 #define VIVS_NTE_UNK12400__ESIZE 0x00000004 1876 #define VIVS_NTE_UNK12400__LEN 0x00000100 1877 1878 #define VIVS_NTE_HALTI3_UNK14C00(i0) (0x00014c00 + 0x4*(i0)) 1879 #define VIVS_NTE_HALTI3_UNK14C00__ESIZE 0x00000004 1880 #define VIVS_NTE_HALTI3_UNK14C00__LEN 0x00000010 1881 1882 #define VIVS_NTE_DESCRIPTOR_UNK14C40 0x00014c40 1883 #define VIVS_NTE_DESCRIPTOR_UNK14C40_UNK0 0x00000001 1884 1885 #define VIVS_NTE_DESCRIPTOR_FLUSH 0x00014c44 1886 #define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__MASK 0xf0000000 1887 #define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__SHIFT 28 1888 #define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28(x) (((x) << VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__SHIFT) & VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__MASK) 1889 1890 #define VIVS_NTE_DESCRIPTOR_INVALIDATE 0x00014c48 1891 #define VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__MASK 0x000001ff 1892 #define VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__SHIFT 0 1893 #define VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX(x) (((x) << VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__SHIFT) & VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__MASK) 1894 #define VIVS_NTE_DESCRIPTOR_INVALIDATE_UNK29 0x20000000 1895 1896 #define VIVS_NTE_DESCRIPTOR(i0) (0x00000000 + 0x4*(i0)) 1897 #define VIVS_NTE_DESCRIPTOR__ESIZE 0x00000004 1898 #define VIVS_NTE_DESCRIPTOR__LEN 0x00000080 1899 1900 #define VIVS_NTE_DESCRIPTOR_ADDR_MIRROR(i0) (0x00015800 + 0x4*(i0)) 1901 1902 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_MIRROR(i0) (0x00015a00 + 0x4*(i0)) 1903 1904 #define VIVS_NTE_DESCRIPTOR_ADDR(i0) (0x00015c00 + 0x4*(i0)) 1905 1906 #define VIVS_NTE_DESCRIPTOR_TX_CTRL(i0) (0x00015e00 + 0x4*(i0)) 1907 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE__MASK 0x00000001 1908 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE__SHIFT 0 1909 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE(x) (((x) << VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE__SHIFT) & VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_MODE__MASK) 1910 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE 0x00000002 1911 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__MASK 0x0000001c 1912 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__SHIFT 2 1913 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX(x) (((x) << VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__SHIFT) & VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__MASK) 1914 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_COMPRESSION 0x00000020 1915 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_128B_TILE 0x00000040 1916 1917 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIRROR(i0) (0x00016000 + 0x4*(i0)) 1918 1919 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_MIRROR(i0) (0x00016200 + 0x4*(i0)) 1920 1921 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIRROR(i0) (0x00016400 + 0x4*(i0)) 1922 1923 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_MIRROR(i0) (0x00016600 + 0x4*(i0)) 1924 1925 #define VIVS_NTE_DESCRIPTOR_SAMP_ANISOTROPY_MIRROR(i0) (0x00016800 + 0x4*(i0)) 1926 1927 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0(i0) (0x00016c00 + 0x4*(i0)) 1928 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__MASK 0x00000007 1929 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__SHIFT 0 1930 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__MASK) 1931 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__MASK 0x00000038 1932 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__SHIFT 3 1933 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__MASK) 1934 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__MASK 0x000001c0 1935 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__SHIFT 6 1936 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__MASK) 1937 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__MASK 0x00000600 1938 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__SHIFT 9 1939 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__MASK) 1940 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__MASK 0x00001800 1941 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__SHIFT 11 1942 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__MASK) 1943 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__MASK 0x00006000 1944 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__SHIFT 13 1945 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__MASK) 1946 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_ENABLE 0x00020000 1947 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__MASK 0x001c0000 1948 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__SHIFT 18 1949 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_COMPARE_FUNC__MASK) 1950 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UNK21 0x00200000 1951 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UNK22 0x00400000 1952 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_INT_FILTER 0x00800000 1953 1954 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1(i0) (0x00016e00 + 0x4*(i0)) 1955 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK1 0x00000002 1956 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_SRGB 0x00000004 1957 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK3 0x00000008 1958 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__MASK 0x00000030 1959 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__SHIFT 4 1960 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__MASK) 1961 1962 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX(i0) (0x00017000 + 0x4*(i0)) 1963 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__MASK 0x0000ffff 1964 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__SHIFT 0 1965 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__MASK) 1966 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__MASK 0xffff0000 1967 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__SHIFT 16 1968 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__MASK) 1969 1970 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS(i0) (0x00017200 + 0x4*(i0)) 1971 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__MASK 0x0000ffff 1972 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__SHIFT 0 1973 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS(x) (((x) << VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__MASK) 1974 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_ENABLE 0x00010000 1975 1976 #define VIVS_NTE_DESCRIPTOR_SAMP_ANISOTROPY(i0) (0x00017400 + 0x4*(i0)) 1977 1978 #define VIVS_SH 0x00000000 1979 1980 #define VIVS_SH_CONFIG 0x00015600 1981 #define VIVS_SH_CONFIG_RTNE_ROUNDING 0x00000002 1982 #define VIVS_SH_CONFIG_DUAL16 0x00000004 1983 1984 #define VIVS_SH_UNK20000(i0) (0x00020000 + 0x4*(i0)) 1985 #define VIVS_SH_UNK20000__ESIZE 0x00000004 1986 #define VIVS_SH_UNK20000__LEN 0x00002000 1987 1988 #define VIVS_SH_INST_MEM(i0) (0x0000c000 + 0x4*(i0)) 1989 #define VIVS_SH_INST_MEM__ESIZE 0x00000004 1990 #define VIVS_SH_INST_MEM__LEN 0x00001000 1991 1992 #define VIVS_SH_INST_MEM_MIRROR(i0) (0x00008000 + 0x4*(i0)) 1993 #define VIVS_SH_INST_MEM_MIRROR__ESIZE 0x00000004 1994 #define VIVS_SH_INST_MEM_MIRROR__LEN 0x00001000 1995 1996 #define VIVS_SH_UNIFORMS(i0) (0x00030000 + 0x4*(i0)) 1997 #define VIVS_SH_UNIFORMS__ESIZE 0x00000004 1998 #define VIVS_SH_UNIFORMS__LEN 0x00000800 1999 2000 #define VIVS_SH_HALTI5_UNIFORMS_MIRROR(i0) (0x00034000 + 0x4*(i0)) 2001 #define VIVS_SH_HALTI5_UNIFORMS_MIRROR__ESIZE 0x00000004 2002 #define VIVS_SH_HALTI5_UNIFORMS_MIRROR__LEN 0x00000800 2003 2004 #define VIVS_SH_HALTI5_UNIFORMS(i0) (0x00036000 + 0x4*(i0)) 2005 #define VIVS_SH_HALTI5_UNIFORMS__ESIZE 0x00000004 2006 #define VIVS_SH_HALTI5_UNIFORMS__LEN 0x00000800 2007 2008 2009 #endif /* STATE_3D_XML */ 2010