1 /** 2 * \file 3 * 4 * \brief SAMV70/SAMV71/SAME70/SAMS70-XULTRA board mpu config. 5 * 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 18 * 2. Redistributions in binary form must reproduce the above copyright notice, 19 * this list of conditions and the following disclaimer in the documentation 20 * and/or other materials provided with the distribution. 21 * 22 * 3. The name of Atmel may not be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * 4. This software may only be redistributed and used in connection with an 26 * Atmel microcontroller product. 27 * 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * \asf_license_stop 41 * 42 */ 43 /* 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> 45 */ 46 47 48 #ifndef _MPU_H_ 49 #define _MPU_H_ 50 51 #include "compiler.h" 52 53 /*---------------------------------------------------------------------------- 54 * Definitions 55 *----------------------------------------------------------------------------*/ 56 #define ARM_MODE_USR 0x10 57 58 #define PRIVILEGE_MODE 0 59 #define USER_MODE 1 60 61 #define MPU_DEFAULT_ITCM_REGION ( 1 ) 62 #define MPU_DEFAULT_IFLASH_REGION ( 2 ) 63 #define MPU_DEFAULT_DTCM_REGION ( 3 ) 64 #define MPU_DEFAULT_SRAM_REGION_1 ( 4 ) 65 #define MPU_DEFAULT_SRAM_REGION_2 ( 5 ) 66 #define MPU_PERIPHERALS_REGION ( 6 ) 67 #define MPU_EXT_EBI_REGION ( 7 ) 68 #define MPU_DEFAULT_SDRAM_REGION ( 8 ) 69 #define MPU_QSPIMEM_REGION ( 9 ) 70 #define MPU_USBHSRAM_REGION ( 10 ) 71 #if defined MPU_HAS_NOCACHE_REGION 72 #define MPU_NOCACHE_SRAM_REGION ( 11 ) 73 #endif 74 75 #define MPU_REGION_VALID ( 0x10 ) 76 #define MPU_REGION_ENABLE ( 0x01 ) 77 #define MPU_REGION_DISABLE ( 0x0 ) 78 79 #define MPU_ENABLE ( 0x1 << MPU_CTRL_ENABLE_Pos) 80 #define MPU_HFNMIENA ( 0x1 << MPU_CTRL_HFNMIENA_Pos ) 81 #define MPU_PRIVDEFENA ( 0x1 << MPU_CTRL_PRIVDEFENA_Pos ) 82 83 84 #define MPU_REGION_BUFFERABLE ( 0x01 << MPU_RASR_B_Pos ) 85 #define MPU_REGION_CACHEABLE ( 0x01 << MPU_RASR_C_Pos ) 86 #define MPU_REGION_SHAREABLE ( 0x01 << MPU_RASR_S_Pos ) 87 88 #define MPU_REGION_EXECUTE_NEVER ( 0x01 << MPU_RASR_XN_Pos ) 89 90 #define MPU_AP_NO_ACCESS ( 0x00 << MPU_RASR_AP_Pos ) 91 #define MPU_AP_PRIVILEGED_READ_WRITE ( 0x01 << MPU_RASR_AP_Pos ) 92 #define MPU_AP_UNPRIVILEGED_READONLY ( 0x02 << MPU_RASR_AP_Pos ) 93 #define MPU_AP_FULL_ACCESS ( 0x03 << MPU_RASR_AP_Pos ) 94 #define MPU_AP_RES ( 0x04 << MPU_RASR_AP_Pos ) 95 #define MPU_AP_PRIVILEGED_READONLY ( 0x05 << MPU_RASR_AP_Pos ) 96 #define MPU_AP_READONLY ( 0x06 << MPU_RASR_AP_Pos ) 97 #define MPU_AP_READONLY2 ( 0x07 << MPU_RASR_AP_Pos ) 98 99 #define MPU_TEX_B000 ( 0x01 << MPU_RASR_TEX_Pos ) 100 #define MPU_TEX_B001 ( 0x01 << MPU_RASR_TEX_Pos ) 101 #define MPU_TEX_B010 ( 0x01 << MPU_RASR_TEX_Pos ) 102 #define MPU_TEX_B011 ( 0x01 << MPU_RASR_TEX_Pos ) 103 #define MPU_TEX_B100 ( 0x01 << MPU_RASR_TEX_Pos ) 104 #define MPU_TEX_B101 ( 0x01 << MPU_RASR_TEX_Pos ) 105 #define MPU_TEX_B110 ( 0x01 << MPU_RASR_TEX_Pos ) 106 #define MPU_TEX_B111 ( 0x01 << MPU_RASR_TEX_Pos ) 107 108 #define SHAREABLE 1 109 #define NON_SHAREABLE 0 110 111 #define INNER_NORMAL_WB_RWA_TYPE(x) (( 0x04 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos )) 112 #define INNER_NORMAL_WB_NWA_TYPE(x) (( 0x04 << MPU_RASR_TEX_Pos ) | ( ENABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos )) 113 #define STRONGLY_ORDERED_SHAREABLE_TYPE (( 0x00 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( DISABLE << MPU_RASR_B_Pos )) // DO not care // 114 #define SHAREABLE_DEVICE_TYPE (( 0x00 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos )) // DO not care // 115 116 117 /* Default memory map 118 Address range Memory region Memory type Shareability Cache policy 119 0x00000000- 0x1FFFFFFF Code Normal Non-shareable WT 120 0x20000000- 0x3FFFFFFF SRAM Normal Non-shareable WBWA 121 0x40000000- 0x5FFFFFFF Peripheral Device Non-shareable - 122 0x60000000- 0x7FFFFFFF RAM Normal Non-shareable WBWA 123 0x80000000- 0x9FFFFFFF RAM Normal Non-shareable WT 124 0xA0000000- 0xBFFFFFFF Device Device Shareable 125 0xC0000000- 0xDFFFFFFF Device Device Non Shareable 126 0xE0000000- 0xFFFFFFFF System - - 127 */ 128 129 /********* IFLASH memory macros *********************/ 130 #define ITCM_START_ADDRESS 0x00000000UL 131 #define ITCM_END_ADDRESS 0x003FFFFFUL 132 #define IFLASH_START_ADDRESS 0x00400000UL 133 #define IFLASH_END_ADDRESS 0x005FFFFFUL 134 135 136 #define IFLASH_PRIVILEGE_START_ADDRESS (IFLASH_START_ADDRESS) 137 #define IFLASH_PRIVILEGE_END_ADDRESS (IFLASH_START_ADDRESS + 0xFFF) 138 139 #define IFLASH_UNPRIVILEGE_START_ADDRESS (IFLASH_PRIVILEGE_END_ADDRESS + 1) 140 #define IFLASH_UNPRIVILEGE_END_ADDRESS (IFLASH_END_ADDRESS) 141 142 /**************** DTCM *******************************/ 143 #define DTCM_START_ADDRESS 0x20000000UL 144 #define DTCM_END_ADDRESS 0x203FFFFFUL 145 146 147 /******* SRAM memory macros ***************************/ 148 149 #define SRAM_START_ADDRESS 0x20400000UL 150 #define SRAM_END_ADDRESS 0x2045FFFFUL 151 152 #if defined MPU_HAS_NOCACHE_REGION 153 #define NOCACHE_SRAM_REGION_SIZE 0x1000 154 #endif 155 156 /* Regions should be a 2^(N+1) where 4 < N < 31 */ 157 #define SRAM_FIRST_START_ADDRESS (SRAM_START_ADDRESS) 158 #define SRAM_FIRST_END_ADDRESS (SRAM_FIRST_START_ADDRESS + 0x3FFFF) // (2^18) 256 KB 159 160 #if defined MPU_HAS_NOCACHE_REGION 161 #define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS+1) 162 #define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS - NOCACHE_SRAM_REGION_SIZE ) // (2^17) 128 - 0x1000 KB 163 #define SRAM_NOCACHE_START_ADDRESS (SRAM_SECOND_END_ADDRESS + 1) 164 #define SRAM_NOCACHE_END_ADDRESS (SRAM_END_ADDRESS ) 165 #else 166 #define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS + 1) 167 #define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS) // (2^17) 128 KB 168 #endif 169 /************** Peripherals memory region macros ********/ 170 #define PERIPHERALS_START_ADDRESS 0x40000000UL 171 #define PERIPHERALS_END_ADDRESS 0x5FFFFFFFUL 172 173 /******* Ext EBI memory macros ***************************/ 174 #define EXT_EBI_START_ADDRESS 0x60000000UL 175 #define EXT_EBI_END_ADDRESS 0x6FFFFFFFUL 176 177 /******* Ext-SRAM memory macros ***************************/ 178 #define SDRAM_START_ADDRESS 0x70000000UL 179 #define SDRAM_END_ADDRESS 0x7FFFFFFFUL 180 181 /******* QSPI macros ***************************/ 182 #define QSPI_START_ADDRESS 0x80000000UL 183 #define QSPI_END_ADDRESS 0x9FFFFFFFUL 184 185 /************** USBHS_RAM region macros ******************/ 186 #define USBHSRAM_START_ADDRESS 0xA0100000UL 187 #define USBHSRAM_END_ADDRESS 0xA01FFFFFUL 188 189 /*---------------------------------------------------------------------------- 190 * Export functions 191 *----------------------------------------------------------------------------*/ 192 void mpu_enable(uint32_t dw_mpu_enable); 193 void mpu_set_region(uint32_t dw_region_base_addr, uint32_t dw_region_attr); 194 void mpu_set_region_num(uint32_t dw_region_num); 195 void mpu_disable_region(void); 196 uint32_t mpu_cal_mpu_region_size(uint32_t dw_actual_size_in_bytes); 197 void mpu_update_regions(uint32_t dw_region_num, uint32_t dw_region_base_addr, uint32_t dw_region_attr); 198 199 #endif /* #ifndef _MPU_H_ */