1 /*
2  * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
3  *
4  * Copyright (C) 2022-2023 Nuvoton Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 #ifndef __ASM_ARCH_UART_H_
10 #define __ASM_ARCH_UART_H_
11 
12 #ifndef __ASSEMBLY__
13 
14 struct npcmX50_uart {
15 	union {
16 		unsigned int rbr;
17 		unsigned int thr;
18 		unsigned int dll;
19 	};
20 	union {
21 		unsigned int ier;
22 		unsigned int dlm;
23 	};
24 	union {
25 		unsigned int iir;
26 		unsigned int fcr;
27 	};
28 	unsigned int lcr;
29 	unsigned int mcr;
30 	unsigned int lsr;
31 	unsigned int msr;
32 	unsigned int tor;
33 };
34 
35 typedef enum {
36 	/*
37 	 * UART0 is a general UART block without modem-I/O-control
38 	 * connection to external signals.
39 	 */
40 	UART0_DEV = 0,
41 	/*
42 	 * UART1-3 are each a general UART with modem-I/O-control
43 	 * connection to external signals.
44 	 */
45 	UART1_DEV,
46 	UART2_DEV,
47 	UART3_DEV,
48 } UART_DEV_T;
49 
50 typedef enum {
51 	/*
52 	 * 0 0 0: Mode 1:
53 	 * HSP1 connected to SI2,
54 	 * HSP2 connected to UART2,
55 	 * UART1 snoops HSP1,
56 	 * UART3 snoops SI2
57 	 */
58 	UART_MUX_MODE1 = 0,
59 	/*
60 	 * 0 0 1: Mode 2:
61 	 * HSP1 connected to UART1,
62 	 * HSP2 connected to SI2,
63 	 * UART2 snoops HSP2,
64 	 * UART3 snoops SI2
65 	 */
66 	UART_MUX_MODE2,
67 	/*
68 	 * 0 1 0: Mode 3:
69 	 * HSP1 connected to UART1,
70 	 * HSP2 connected to UART2,
71 	 * UART3 connected to SI2
72 	 */
73 	UART_MUX_MODE3,
74 	/*
75 	 * 0 1 1: Mode 4:
76 	 * HSP1 connected to SI1,
77 	 * HSP2 connected to SI2,
78 	 * UART1 snoops SI1,
79 	 * UART3 snoops SI2,
80 	 * UART2 snoops HSP1 (default)
81 	 */
82 	UART_MUX_MODE4,
83 	/*
84 	 * 1 0 0: Mode 5:
85 	 * HSP1 connected to SI1,
86 	 * HSP2 connected to UART2,
87 	 * UART1 snoops HSP1,
88 	 * UART3 snoops SI1
89 	 */
90 	UART_MUX_MODE5,
91 	/*
92 	 * 1 0 1: Mode 6:
93 	 * HSP1 connected to SI1,
94 	 * HSP2 connected to SI2,
95 	 * UART1 snoops SI1,
96 	 * UART3 snoops SI2,
97 	 * UART2 snoops HSP2
98 	 */
99 	UART_MUX_MODE6,
100 	/*
101 	 * 1 1 0: Mode 7:
102 	 * HSP1 connected to SI1,
103 	 * HSP2 connected to UART2,
104 	 * UART1 snoops HSP1,
105 	 * UART3 connected to SI2
106 	 */
107 	UART_MUX_MODE7,
108 	/* Skip UART mode configuration. */
109 	UART_MUX_RESERVED,
110 	/*
111 	 * A SW option to allow config of UART
112 	 * without touching the UART mux.
113 	 */
114 	UART_MUX_SKIP_CONFIG
115 } UART_MUX_T;
116 
117 /*---------------------------------------------------------------------------*/
118 /* Common baudrate definitions                                               */
119 /*---------------------------------------------------------------------------*/
120 typedef enum {
121 	UART_BAUDRATE_110 = 110,
122 	UART_BAUDRATE_300 = 300,
123 	UART_BAUDRATE_600 = 600,
124 	UART_BAUDRATE_1200 = 1200,
125 	UART_BAUDRATE_2400 = 2400,
126 	UART_BAUDRATE_4800 = 4800,
127 	UART_BAUDRATE_9600 = 9600,
128 	UART_BAUDRATE_14400 = 14400,
129 	UART_BAUDRATE_19200 = 19200,
130 	UART_BAUDRATE_38400 = 38400,
131 	UART_BAUDRATE_57600 = 57600,
132 	UART_BAUDRATE_115200 = 115200,
133 	UART_BAUDRATE_230400 = 230400,
134 	UART_BAUDRATE_380400 = 380400,
135 	UART_BAUDRATE_460800 = 460800,
136 } UART_BAUDRATE_T;
137 
138 /*---------------------------------------------------------------------------*/
139 /* UART parity types                                                         */
140 /*---------------------------------------------------------------------------*/
141 typedef enum {
142 	UART_PARITY_NONE = 0,
143 	UART_PARITY_EVEN,
144 	UART_PARITY_ODD,
145 } UART_PARITY_T;
146 
147 /*---------------------------------------------------------------------------*/
148 /* Uart stop bits                                                            */
149 /*---------------------------------------------------------------------------*/
150 typedef enum {
151 	UART_STOPBIT_1 = 0x00,
152 	UART_STOPBIT_DYNAMIC,
153 } UART_STOPBIT_T;
154 
155 enum FCR_RFITL_TYPE {
156 	FCR_RFITL_1B = 0x0,
157 	FCR_RFITL_4B = 0x4,
158 	FCR_RFITL_8B = 0x8,
159 	FCR_RFITL_14B = 0xC,
160 };
161 
162 enum LCR_WLS_TYPE {
163 	LCR_WLS_5bit = 0x0,
164 	LCR_WLS_6bit = 0x1,
165 	LCR_WLS_7bit = 0x2,
166 	LCR_WLS_8bit = 0x3,
167 };
168 
169 #define IER_DBGACK (1 << 4)
170 #define IER_MSIE (1 << 3)
171 #define IER_RLSE (1 << 2)
172 #define IER_THREIE (1 << 1)
173 #define IER_RDAIE (1 << 0)
174 
175 #define IIR_FMES (1 << 7)
176 #define IIR_RFTLS (1 << 5)
177 #define IIR_DMS (1 << 4)
178 #define IIR_IID (1 << 1)
179 #define IIR_NIP (1 << 0)
180 
181 #define FCR_RFITL_1B (0 << 4)
182 #define FCR_RFITL_4B (4 << 4)
183 #define FCR_RFITL_8B (8 << 4)
184 #define FCR_RFITL_14B (12 << 4)
185 #define FCR_DMS (1 << 3)
186 #define FCR_TFR (1 << 2)
187 #define FCR_RFR (1 << 1)
188 #define FCR_FME (1 << 0)
189 
190 #define LCR_DLAB (1 << 7)
191 #define LCR_BCB (1 << 6)
192 #define LCR_SPE (1 << 5)
193 #define LCR_EPS (1 << 4)
194 #define LCR_PBE (1 << 3)
195 #define LCR_NSB (1 << 2)
196 #define LCR_WLS_8b (3 << 0)
197 #define LCR_WLS_7b (2 << 0)
198 #define LCR_WLS_6b (1 << 0)
199 #define LCR_WLS_5b (0 << 0)
200 
201 #define MCR_LBME (1 << 4)
202 #define MCR_OUT2 (1 << 3)
203 #define MCR_RTS (1 << 1)
204 #define MCR_DTR (1 << 0)
205 
206 #define LSR_ERR_RX (1 << 7)
207 #define LSR_TE (1 << 6)
208 #define LSR_THRE (1 << 5)
209 #define LSR_BII (1 << 4)
210 #define LSR_FEI (1 << 3)
211 #define LSR_PEI (1 << 2)
212 #define LSR_OEI (1 << 1)
213 #define LSR_RFDR (1 << 0)
214 
215 #define MSR_DCD (1 << 7)
216 #define MSR_RI (1 << 6)
217 #define MSR_DSR (1 << 5)
218 #define MSR_CTS (1 << 4)
219 #define MSR_DDCD (1 << 3)
220 #define MSR_DRI (1 << 2)
221 #define MSR_DDSR (1 << 1)
222 #define MSR_DCTS (1 << 0)
223 
224 #endif /* __ASSEMBLY__ */
225 
226 uintptr_t npcm845x_get_base_uart(UART_DEV_T dev);
227 void CLK_ResetUART(void);
228 int UART_Init(UART_DEV_T devNum, UART_BAUDRATE_T baudRate);
229 
230 #endif /* __ASM_ARCH_UART_H_ */
231