1package xiangshan.backend.fu.NewCSR.CSREvents 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility.SignExt 7import xiangshan.ExceptionNO 8import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, OneFieldBundle, PrivState} 9import xiangshan.backend.fu.NewCSR.CSRConfig.{VaddrMaxWidth, XLEN} 10import xiangshan.backend.fu.NewCSR._ 11import xiangshan.AddrTransType 12 13class TrapEntryMNEventOutput extends Bundle with EventUpdatePrivStateOutput with EventOutputBase { 14 val mnstatus = ValidIO((new MnstatusBundle ).addInEvent(_.MNPP, _.MNPV, _.NMIE)) 15 val mnepc = ValidIO((new Epc ).addInEvent(_.epc)) 16 val mncause = ValidIO((new CauseBundle ).addInEvent(_.Interrupt, _.ExceptionCode)) 17 val targetPc = ValidIO(new TargetPCBundle) 18} 19 20class TrapEntryMNEventModule(implicit val p: Parameters) extends Module with CSREventBase { 21 val in = IO(new TrapEntryEventInput) 22 val out = IO(new TrapEntryMNEventOutput) 23 24 private val current = in 25 private val iMode = current.iMode 26 private val satp = current.satp 27 private val vsatp = current.vsatp 28 private val hgatp = current.hgatp 29 30 private val highPrioTrapNO = in.causeNO.ExceptionCode.asUInt 31 private val isInterrupt = in.causeNO.Interrupt.asBool 32 33 private val isFetchMalAddr = in.isFetchMalAddr 34 35 private val trapPC = genTrapVA( 36 iMode, 37 satp, 38 vsatp, 39 hgatp, 40 in.trapPc, 41 ) 42 out := DontCare 43 44 out.privState.valid := valid 45 out.mnstatus.valid := valid 46 out.mnepc.valid := valid 47 out.mncause.valid := valid 48 out.targetPc.valid := valid 49 50 out.privState.bits := PrivState.ModeM 51 out.mnstatus.bits.MNPP := current.privState.PRVM 52 out.mnstatus.bits.MNPV := current.privState.V 53 out.mnstatus.bits.NMIE := 0.U 54 out.mnepc.bits.epc := Mux(isFetchMalAddr, in.fetchMalTval(63, 1), trapPC(63, 1)) 55 out.mncause.bits.Interrupt := isInterrupt 56 out.mncause.bits.ExceptionCode := highPrioTrapNO 57 out.targetPc.bits.pc := in.pcFromXtvec 58 out.targetPc.bits.raiseIPF := false.B 59 out.targetPc.bits.raiseIAF := AddrTransType(bare = true).checkAccessFault(in.pcFromXtvec) 60 out.targetPc.bits.raiseIGPF := false.B 61 62} 63 64trait TrapEntryMNEventSinkBundle extends EventSinkBundle { self: CSRModule[_ <: CSRBundle] => 65 val trapToMN = IO(Flipped(new TrapEntryMNEventOutput)) 66 67 addUpdateBundleInCSREnumType(trapToMN.getBundleByName(self.modName.toLowerCase())) 68 69 reconnectReg() 70} 71