1 /*===================== begin_copyright_notice ================================== 2 3 * Copyright (c) 2024, Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included 13 * in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 23 ======================= end_copyright_notice ==================================*/ 24 //! 25 //! \file mhw_sfc_hwcmd_xe2_lpm_base_next.h 26 //! \brief Auto-generated constructors for MHW and states. 27 //! \details This file may not be included outside of xe2_lpm as other components 28 //! should use MHW interface to interact with MHW commands and states. 29 //! 30 31 // DO NOT EDIT 32 33 #ifndef __MHW_SFC_HWCMD_XE2_LPM_BASE_NEXT_H__ 34 #define __MHW_SFC_HWCMD_XE2_LPM_BASE_NEXT_H__ 35 36 #pragma once 37 #pragma pack(1) 38 39 #include <cstdint> 40 #include <cstddef> 41 #include "media_class_trace.h" 42 43 namespace mhw 44 { 45 namespace sfc 46 { 47 namespace xe2_lpm_base_next 48 { 49 class Cmd 50 { 51 public: 52 // Internal Macros 53 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 54 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 55 #define __CODEGEN_OP_LENGTH_BIAS 2 56 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 57 GetOpLength(uint32_t uiLength)58 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 59 60 //! 61 //! \brief SFC_AVS_STATE 62 //! \details 63 //! This command is sent from VDBOX/VEBOX to SFC pipeline at the start of 64 //! each frame once the lock request is granted. 65 //! 66 struct SFC_AVS_STATE_CMD 67 { 68 union 69 { 70 struct 71 { 72 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 73 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 74 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 75 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 76 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 77 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 78 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 79 }; 80 uint32_t Value; 81 } DW0; 82 union 83 { 84 struct 85 { 86 uint32_t TransitionAreaWith8Pixels : __CODEGEN_BITFIELD( 0, 2) ; //!< Transition Area with 8 Pixels 87 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 88 uint32_t TransitionAreaWith4Pixels : __CODEGEN_BITFIELD( 4, 6) ; //!< Transition Area with 4 Pixels 89 uint32_t Reserved39 : __CODEGEN_BITFIELD( 7, 23) ; //!< Reserved 90 uint32_t SharpnessLevel : __CODEGEN_BITFIELD(24, 31) ; //!< SHARPNESS_LEVEL 91 }; 92 uint32_t Value; 93 } DW1; 94 union 95 { 96 struct 97 { 98 uint32_t MaxDerivativePoint8 : __CODEGEN_BITFIELD( 0, 7) ; //!< MAX Derivative Point 8 99 uint32_t Reserved72 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 100 uint32_t MaxDerivative4Pixels : __CODEGEN_BITFIELD(16, 23) ; //!< Max Derivative 4 Pixels 101 uint32_t Reserved88 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 102 }; 103 uint32_t Value; 104 } DW2; 105 union 106 { 107 struct 108 { 109 uint32_t InputVerticalSitingSpecifiesTheVerticalSitingOfTheInput : __CODEGEN_BITFIELD( 0, 3) ; //!< INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT 110 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 7) ; //!< Reserved 111 uint32_t InputHorizontalSitingValueSpecifiesTheHorizontalSitingOfTheInput : __CODEGEN_BITFIELD( 8, 12) ; //!< Input Horizontal Siting Value - Specifies the horizontal siting of the input 112 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 113 }; 114 uint32_t Value; 115 } DW3; 116 117 //! \name Local enumerations 118 119 enum SUBOPCODEB 120 { 121 SUBOPCODEB_SFCAVSSTATE = 2, //!< No additional details 122 }; 123 124 enum SUBOPCODEA 125 { 126 SUBOPCODEA_COMMON = 0, //!< No additional details 127 }; 128 129 enum MEDIA_COMMAND_OPCODE 130 { 131 MEDIA_COMMAND_OPCODE_MEDIAHEVCSFCMODE = 9, //!< No additional details 132 MEDIA_COMMAND_OPCODE_MEDIAMISC = 10, //!< Media MFX/VEBOX+SFC Modegen 133 MEDIA_COMMAND_OPCODE_MEDIAAVPSFCMODE = 0xD, //!< No additional details 134 }; 135 136 enum PIPELINE 137 { 138 PIPELINE_MEDIA = 2, //!< No additional details 139 }; 140 141 enum COMMAND_TYPE 142 { 143 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 144 }; 145 146 //! \brief SHARPNESS_LEVEL 147 //! \details 148 //! When adaptive scaling is off, determines the balance between sharp and 149 //! smooth scalers. 150 enum SHARPNESS_LEVEL 151 { 152 SHARPNESS_LEVEL_UNNAMED0 = 0, //!< Contribute 1 from the smooth scalar 153 SHARPNESS_LEVEL_UNNAMED255 = 255, //!< Contribute 1 from the sharp scalar 154 }; 155 156 //! \brief INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT 157 //! \details 158 //! For 444 and 422 format, vertical chroma siting should be programmed to 159 //! zero. 160 enum INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT 161 { 162 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_0 = 0, //!< No additional details 163 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_18 = 1, //!< No additional details 164 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_28 = 2, //!< No additional details 165 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_38 = 3, //!< No additional details 166 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_48 = 4, //!< No additional details 167 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_58 = 5, //!< No additional details 168 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_68 = 6, //!< No additional details 169 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_78 = 7, //!< No additional details 170 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_88 = 8, //!< No additional details 171 }; 172 173 //! \name Initializations 174 175 //! \brief Explicit member initialization function 176 SFC_AVS_STATE_CMD(); 177 178 static const size_t dwSize = 4; 179 static const size_t byteSize = 16; 180 }; 181 182 //! 183 //! \brief SFC_IEF_STATE 184 //! \details 185 //! This command is sent from VDBOX/VEBOX to SFC pipeline at the start of 186 //! each frame once the lock request is granted. 187 //! 188 struct SFC_IEF_STATE_CMD 189 { 190 union 191 { 192 struct 193 { 194 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 195 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 196 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 197 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 198 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 199 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 200 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 201 }; 202 uint32_t Value; 203 } DW0; 204 union 205 { 206 struct 207 { 208 uint32_t GainFactor : __CODEGEN_BITFIELD( 0, 5) ; //!< GAIN_FACTOR 209 uint32_t WeakEdgeThreshold : __CODEGEN_BITFIELD( 6, 11) ; //!< WEAK_EDGE_THRESHOLD 210 uint32_t StrongEdgeThreshold : __CODEGEN_BITFIELD(12, 17) ; //!< STRONG_EDGE_THRESHOLD 211 uint32_t R3XCoefficient : __CODEGEN_BITFIELD(18, 22) ; //!< R3X_COEFFICIENT 212 uint32_t R3CCoefficient : __CODEGEN_BITFIELD(23, 27) ; //!< R3C_COEFFICIENT 213 uint32_t Reserved60 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 214 }; 215 uint32_t Value; 216 } DW1; 217 union 218 { 219 struct 220 { 221 uint32_t GlobalNoiseEstimation : __CODEGEN_BITFIELD( 0, 7) ; //!< GLOBAL_NOISE_ESTIMATION 222 uint32_t NonEdgeWeight : __CODEGEN_BITFIELD( 8, 10) ; //!< NON_EDGE_WEIGHT 223 uint32_t RegularWeight : __CODEGEN_BITFIELD(11, 13) ; //!< REGULAR_WEIGHT 224 uint32_t StrongEdgeWeight : __CODEGEN_BITFIELD(14, 16) ; //!< STRONG_EDGE_WEIGHT 225 uint32_t R5XCoefficient : __CODEGEN_BITFIELD(17, 21) ; //!< R5X_COEFFICIENT 226 uint32_t R5CxCoefficient : __CODEGEN_BITFIELD(22, 26) ; //!< R5CX_COEFFICIENT 227 uint32_t R5CCoefficient : __CODEGEN_BITFIELD(27, 31) ; //!< R5C_COEFFICIENT 228 }; 229 uint32_t Value; 230 } DW2; 231 union 232 { 233 struct 234 { 235 uint32_t StdSinAlpha : __CODEGEN_BITFIELD( 0, 7) ; //!< STD Sin(alpha) 236 uint32_t StdCosAlpha : __CODEGEN_BITFIELD( 8, 15) ; //!< STD Cos(alpha) 237 uint32_t SatMax : __CODEGEN_BITFIELD(16, 21) ; //!< SAT_MAX 238 uint32_t HueMax : __CODEGEN_BITFIELD(22, 27) ; //!< HUE_MAX 239 uint32_t Reserved124 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 240 }; 241 uint32_t Value; 242 } DW3; 243 union 244 { 245 struct 246 { 247 uint32_t S3U : __CODEGEN_BITFIELD( 0, 10) ; //!< S3U 248 uint32_t Reserved139 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 249 uint32_t DiamondMargin : __CODEGEN_BITFIELD(12, 14) ; //!< DIAMOND_MARGIN 250 uint32_t VyStdEnable : __CODEGEN_BITFIELD(15, 15) ; //!< VY_STD_Enable 251 uint32_t UMid : __CODEGEN_BITFIELD(16, 23) ; //!< U_MID 252 uint32_t VMid : __CODEGEN_BITFIELD(24, 31) ; //!< V_MID 253 }; 254 uint32_t Value; 255 } DW4; 256 union 257 { 258 struct 259 { 260 uint32_t DiamondDv : __CODEGEN_BITFIELD( 0, 6) ; //!< DIAMOND_DV 261 uint32_t DiamondTh : __CODEGEN_BITFIELD( 7, 12) ; //!< DIAMOND_TH 262 uint32_t DiamondAlpha : __CODEGEN_BITFIELD(13, 20) ; //!< Diamond_alpha 263 uint32_t HsMargin : __CODEGEN_BITFIELD(21, 23) ; //!< HS_MARGIN 264 uint32_t DiamondDu : __CODEGEN_BITFIELD(24, 30) ; //!< DIAMOND_DU 265 uint32_t SkinDetailFactor : __CODEGEN_BITFIELD(31, 31) ; //!< SKIN_DETAIL_FACTOR 266 }; 267 uint32_t Value; 268 } DW5; 269 union 270 { 271 struct 272 { 273 uint32_t YPoint1 : __CODEGEN_BITFIELD( 0, 7) ; //!< Y_POINT_1 274 uint32_t YPoint2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Y_POINT_2 275 uint32_t YPoint3 : __CODEGEN_BITFIELD(16, 23) ; //!< Y_POINT_3 276 uint32_t YPoint4 : __CODEGEN_BITFIELD(24, 31) ; //!< Y_POINT_4 277 }; 278 uint32_t Value; 279 } DW6; 280 union 281 { 282 struct 283 { 284 uint32_t InvMarginVyl : __CODEGEN_BITFIELD( 0, 15) ; //!< INV_Margin_VYL 285 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 286 }; 287 uint32_t Value; 288 } DW7; 289 union 290 { 291 struct 292 { 293 uint32_t InvMarginVyu : __CODEGEN_BITFIELD( 0, 15) ; //!< INV_Margin_VYU 294 uint32_t P0L : __CODEGEN_BITFIELD(16, 23) ; //!< P0L 295 uint32_t P1L : __CODEGEN_BITFIELD(24, 31) ; //!< P1L 296 }; 297 uint32_t Value; 298 } DW8; 299 union 300 { 301 struct 302 { 303 uint32_t P2L : __CODEGEN_BITFIELD( 0, 7) ; //!< P2L 304 uint32_t P3L : __CODEGEN_BITFIELD( 8, 15) ; //!< P3L 305 uint32_t B0L : __CODEGEN_BITFIELD(16, 23) ; //!< B0L 306 uint32_t B1L : __CODEGEN_BITFIELD(24, 31) ; //!< B1L 307 }; 308 uint32_t Value; 309 } DW9; 310 union 311 { 312 struct 313 { 314 uint32_t B2L : __CODEGEN_BITFIELD( 0, 7) ; //!< B2L 315 uint32_t B3L : __CODEGEN_BITFIELD( 8, 15) ; //!< B3L 316 uint32_t S0L : __CODEGEN_BITFIELD(16, 26) ; //!< S0L 317 uint32_t YSlope2 : __CODEGEN_BITFIELD(27, 31) ; //!< Y_Slope_2 318 }; 319 uint32_t Value; 320 } DW10; 321 union 322 { 323 struct 324 { 325 uint32_t S1L : __CODEGEN_BITFIELD( 0, 10) ; //!< S1L 326 uint32_t S2L : __CODEGEN_BITFIELD(11, 21) ; //!< S2L 327 uint32_t Reserved374 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 328 }; 329 uint32_t Value; 330 } DW11; 331 union 332 { 333 struct 334 { 335 uint32_t S3L : __CODEGEN_BITFIELD( 0, 10) ; //!< S3L 336 uint32_t P0U : __CODEGEN_BITFIELD(11, 18) ; //!< P0U 337 uint32_t P1U : __CODEGEN_BITFIELD(19, 26) ; //!< P1U 338 uint32_t YSlope1 : __CODEGEN_BITFIELD(27, 31) ; //!< Y_Slope1 339 }; 340 uint32_t Value; 341 } DW12; 342 union 343 { 344 struct 345 { 346 uint32_t P2U : __CODEGEN_BITFIELD( 0, 7) ; //!< P2U 347 uint32_t P3U : __CODEGEN_BITFIELD( 8, 15) ; //!< P3U 348 uint32_t B0U : __CODEGEN_BITFIELD(16, 23) ; //!< B0U 349 uint32_t B1U : __CODEGEN_BITFIELD(24, 31) ; //!< B1U 350 }; 351 uint32_t Value; 352 } DW13; 353 union 354 { 355 struct 356 { 357 uint32_t B2U : __CODEGEN_BITFIELD( 0, 7) ; //!< B2U 358 uint32_t B3U : __CODEGEN_BITFIELD( 8, 15) ; //!< B3U 359 uint32_t S0U : __CODEGEN_BITFIELD(16, 26) ; //!< S0U 360 uint32_t Reserved475 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 361 }; 362 uint32_t Value; 363 } DW14; 364 union 365 { 366 struct 367 { 368 uint32_t S1U : __CODEGEN_BITFIELD( 0, 10) ; //!< S1U 369 uint32_t S2U : __CODEGEN_BITFIELD(11, 21) ; //!< S2U 370 uint32_t Reserved502 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 371 }; 372 uint32_t Value; 373 } DW15; 374 union 375 { 376 struct 377 { 378 uint32_t TransformEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Transform Enable 379 uint32_t YuvChannelSwap : __CODEGEN_BITFIELD( 1, 1) ; //!< YUV Channel Swap 380 uint32_t Reserved514 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 381 uint32_t C0 : __CODEGEN_BITFIELD( 3, 15) ; //!< C0 382 uint32_t C1 : __CODEGEN_BITFIELD(16, 28) ; //!< C1 383 uint32_t Reserved541 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 384 }; 385 uint32_t Value; 386 } DW16; 387 union 388 { 389 struct 390 { 391 uint32_t C2 : __CODEGEN_BITFIELD( 0, 12) ; //!< C2 392 uint32_t C3 : __CODEGEN_BITFIELD(13, 25) ; //!< C3 393 uint32_t Reserved570 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 394 }; 395 uint32_t Value; 396 } DW17; 397 union 398 { 399 struct 400 { 401 uint32_t C4 : __CODEGEN_BITFIELD( 0, 12) ; //!< C4 402 uint32_t C5 : __CODEGEN_BITFIELD(13, 25) ; //!< C5 403 uint32_t Reserved602 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 404 }; 405 uint32_t Value; 406 } DW18; 407 union 408 { 409 struct 410 { 411 uint32_t C6 : __CODEGEN_BITFIELD( 0, 12) ; //!< C6 412 uint32_t C7 : __CODEGEN_BITFIELD(13, 25) ; //!< C7 413 uint32_t Reserved634 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 414 }; 415 uint32_t Value; 416 } DW19; 417 union 418 { 419 struct 420 { 421 uint32_t C8 : __CODEGEN_BITFIELD( 0, 12) ; //!< C8 422 uint32_t Reserved653 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 423 }; 424 uint32_t Value; 425 } DW20; 426 union 427 { 428 struct 429 { 430 uint32_t OffsetIn1 : __CODEGEN_BITFIELD( 0, 10) ; //!< OFFSET_IN_1 431 uint32_t OffsetOut1 : __CODEGEN_BITFIELD(11, 21) ; //!< OFFSET_OUT_1 432 uint32_t Reserved694 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 433 }; 434 uint32_t Value; 435 } DW21; 436 union 437 { 438 struct 439 { 440 uint32_t OffsetIn2 : __CODEGEN_BITFIELD( 0, 10) ; //!< OFFSET_IN_2 441 uint32_t OffsetOut2 : __CODEGEN_BITFIELD(11, 21) ; //!< OFFSET_OUT_2 442 uint32_t Reserved726 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 443 }; 444 uint32_t Value; 445 } DW22; 446 union 447 { 448 struct 449 { 450 uint32_t OffsetIn3 : __CODEGEN_BITFIELD( 0, 10) ; //!< OFFSET_IN_3 451 uint32_t OffsetOut3 : __CODEGEN_BITFIELD(11, 21) ; //!< OFFSET_OUT_3 452 uint32_t Reserved758 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 453 }; 454 uint32_t Value; 455 } DW23; 456 457 //! \name Local enumerations 458 459 enum SUBOPCODEB 460 { 461 SUBOPCODEB_SFCIEFSTATE = 3, //!< No additional details 462 }; 463 464 enum SUBOPCODEA 465 { 466 SUBOPCODEA_COMMON = 0, //!< No additional details 467 }; 468 469 enum MEDIA_COMMAND_OPCODE 470 { 471 MEDIA_COMMAND_OPCODE_MEDIAHEVCSFCMODE = 9, //!< No additional details 472 MEDIA_COMMAND_OPCODE_MEDIAMISC = 10, //!< Media MFX/VEBOX+SFC Mode 473 MEDIA_COMMAND_OPCODE_MEDIAAVPSFCMODE = 0xD, //!< No additional details 474 }; 475 476 enum PIPELINE 477 { 478 PIPELINE_MEDIA = 2, //!< No additional details 479 }; 480 481 enum COMMAND_TYPE 482 { 483 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 484 }; 485 486 //! \brief GAIN_FACTOR 487 //! \details 488 //! User control sharpening strength. 489 enum GAIN_FACTOR 490 { 491 GAIN_FACTOR_UNNAMED44 = 44, //!< No additional details 492 }; 493 494 //! \brief WEAK_EDGE_THRESHOLD 495 //! \details 496 //! If Strong Edge Threshold > EM > Weak Edge Threshold the basic VSA 497 //! detects a weak edge. 498 enum WEAK_EDGE_THRESHOLD 499 { 500 WEAK_EDGE_THRESHOLD_UNNAMED1 = 1, //!< No additional details 501 }; 502 503 //! \brief STRONG_EDGE_THRESHOLD 504 //! \details 505 //! If EM > Strong Edge Threshold the basic VSA detects a strong edge. 506 enum STRONG_EDGE_THRESHOLD 507 { 508 STRONG_EDGE_THRESHOLD_UNNAMED8 = 8, //!< No additional details 509 }; 510 511 //! \brief R3X_COEFFICIENT 512 //! \details 513 //! IEF smoothing coefficient, see IEF map. 514 enum R3X_COEFFICIENT 515 { 516 R3X_COEFFICIENT_UNNAMED5 = 5, //!< No additional details 517 }; 518 519 //! \brief R3C_COEFFICIENT 520 //! \details 521 //! IEF smoothing coefficient, see IEF map. 522 enum R3C_COEFFICIENT 523 { 524 R3C_COEFFICIENT_UNNAMED5 = 5, //!< No additional details 525 }; 526 527 //! \brief GLOBAL_NOISE_ESTIMATION 528 //! \details 529 //! Global noise estimation of previous frame. 530 enum GLOBAL_NOISE_ESTIMATION 531 { 532 GLOBAL_NOISE_ESTIMATION_UNNAMED255 = 255, //!< No additional details 533 }; 534 535 //! \brief NON_EDGE_WEIGHT 536 //! \details 537 //! . Sharpening strength when NO EDGE is found in basic VSA. 538 enum NON_EDGE_WEIGHT 539 { 540 NON_EDGE_WEIGHT_UNNAMED1 = 1, //!< No additional details 541 }; 542 543 //! \brief REGULAR_WEIGHT 544 //! \details 545 //! Sharpening strength when a WEAK edge is found in basic VSA. 546 enum REGULAR_WEIGHT 547 { 548 REGULAR_WEIGHT_UNNAMED2 = 2, //!< No additional details 549 }; 550 551 //! \brief STRONG_EDGE_WEIGHT 552 //! \details 553 //! Sharpening strength when a STRONG edge is found in basic VSA. 554 enum STRONG_EDGE_WEIGHT 555 { 556 STRONG_EDGE_WEIGHT_UNNAMED7 = 7, //!< No additional details 557 }; 558 559 //! \brief R5X_COEFFICIENT 560 //! \details 561 //! IEF smoothing coefficient, see IEF map. 562 enum R5X_COEFFICIENT 563 { 564 R5X_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 565 }; 566 567 //! \brief R5CX_COEFFICIENT 568 //! \details 569 //! IEF smoothing coefficient, see IEF map. 570 enum R5CX_COEFFICIENT 571 { 572 R5CX_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 573 }; 574 575 //! \brief R5C_COEFFICIENT 576 //! \details 577 //! IEF smoothing coefficient, see IEF map. 578 enum R5C_COEFFICIENT 579 { 580 R5C_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 581 }; 582 583 //! \brief SAT_MAX 584 //! \details 585 //! Rectangle half length. 586 enum SAT_MAX 587 { 588 SAT_MAX_UNNAMED31 = 31, //!< No additional details 589 }; 590 591 //! \brief HUE_MAX 592 //! \details 593 //! Rectangle half width. 594 enum HUE_MAX 595 { 596 HUE_MAX_UNNAMED14 = 14, //!< No additional details 597 }; 598 599 enum DIAMOND_MARGIN 600 { 601 DIAMOND_MARGIN_UNNAMED4 = 4, //!< No additional details 602 }; 603 604 //! \brief U_MID 605 //! \details 606 //! Rectangle middle-point U coordinate. 607 enum U_MID 608 { 609 U_MID_UNNAMED110 = 110, //!< No additional details 610 }; 611 612 //! \brief V_MID 613 //! \details 614 //! Rectangle middle-point V coordinate. 615 enum V_MID 616 { 617 V_MID_UNNAMED154 = 154, //!< No additional details 618 }; 619 620 //! \brief DIAMOND_DV 621 //! \details 622 //! Rhombus center shift in the hue-direction, relative to the rectangle 623 //! center. 624 enum DIAMOND_DV 625 { 626 DIAMOND_DV_UNNAMED0 = 0, //!< No additional details 627 }; 628 629 //! \brief DIAMOND_TH 630 //! \details 631 //! Half length of the rhombus axis in the sat-direction. 632 enum DIAMOND_TH 633 { 634 DIAMOND_TH_UNNAMED35 = 35, //!< No additional details 635 }; 636 637 //! \brief HS_MARGIN 638 //! \details 639 //! Defines rectangle margin. 640 enum HS_MARGIN 641 { 642 HS_MARGIN_UNNAMED3 = 3, //!< No additional details 643 }; 644 645 //! \brief DIAMOND_DU 646 //! \details 647 //! Rhombus center shift in the sat-direction, relative to the rectangle 648 //! center. 649 enum DIAMOND_DU 650 { 651 DIAMOND_DU_UNNAMED0 = 0, //!< No additional details 652 }; 653 654 //! \brief SKIN_DETAIL_FACTOR 655 //! \details 656 //! This flag bit is in operation only when one of the following conditions 657 //! exists:when the control bit SkinToneTunedIEF_Enable is 658 //! on. 659 //! When SkinDetailFactor is equal to 0, 660 //! sign(SkinDetailFactor) is equal to +1, and the content of the 661 //! detected skin tone area is detail revealed.</Li>When 662 //! SkinDetailFactor is equal to 1, sign(SkinDetailFactor) is 663 //! equal to -1, and the content of the detected skin tone area is not 664 //! detail revealed. 665 666 enum SKIN_DETAIL_FACTOR 667 { 668 SKIN_DETAIL_FACTOR_DETAILREVEALED = 0, //!< No additional details 669 SKIN_DETAIL_FACTOR_NOTDETAILREVEALED = 1, //!< No additional details 670 }; 671 672 //! \brief Y_POINT_1 673 //! \details 674 //! First point of the Y piecewise linear membership function. 675 enum Y_POINT_1 676 { 677 Y_POINT_1_UNNAMED46 = 46, //!< No additional details 678 }; 679 680 //! \brief Y_POINT_2 681 //! \details 682 //! Second point of the Y piecewise linear membership function. 683 enum Y_POINT_2 684 { 685 Y_POINT_2_UNNAMED47 = 47, //!< No additional details 686 }; 687 688 //! \brief Y_POINT_3 689 //! \details 690 //! Third point of the Y piecewise linear membership function. 691 enum Y_POINT_3 692 { 693 Y_POINT_3_UNNAMED254 = 254, //!< No additional details 694 }; 695 696 //! \brief Y_POINT_4 697 //! \details 698 //! Fourth point of the Y piecewise linear membership function. 699 enum Y_POINT_4 700 { 701 Y_POINT_4_UNNAMED255 = 255, //!< No additional details 702 }; 703 704 //! \brief P0L 705 //! \details 706 //! Y Point 0 of the lower part of the detection PWLF. 707 enum P0L 708 { 709 P0L_UNNAMED46 = 46, //!< No additional details 710 }; 711 712 //! \brief P1L 713 //! \details 714 //! Y Point 1 of the lower part of the detection PWLF. 715 enum P1L 716 { 717 P1L_UNNAMED216 = 216, //!< No additional details 718 }; 719 720 //! \brief P2L 721 //! \details 722 //! Y Point 2 of the lower part of the detection PWLF. 723 enum P2L 724 { 725 P2L_UNNAMED236 = 236, //!< No additional details 726 }; 727 728 //! \brief P3L 729 //! \details 730 //! Y Point 3 of the lower part of the detection PWLF. 731 enum P3L 732 { 733 P3L_UNNAMED236 = 236, //!< No additional details 734 }; 735 736 //! \brief B0L 737 //! \details 738 //! V Bias 0 of the lower part of the detection PWLF. 739 enum B0L 740 { 741 B0L_UNNAMED133 = 133, //!< No additional details 742 }; 743 744 //! \brief B1L 745 //! \details 746 //! V Bias 1 of the lower part of the detection PWLF. 747 enum B1L 748 { 749 B1L_UNNAMED130 = 130, //!< No additional details 750 }; 751 752 //! \brief B2L 753 //! \details 754 //! V Bias 2 of the lower part of the detection PWLF. 755 enum B2L 756 { 757 B2L_UNNAMED130 = 130, //!< No additional details 758 }; 759 760 //! \brief B3L 761 //! \details 762 //! V Bias 3 of the lower part of the detection PWLF. 763 enum B3L 764 { 765 B3L_UNNAMED130 = 130, //!< No additional details 766 }; 767 768 //! \brief P0U 769 //! \details 770 //! Y Point 0 of the upper part of the detection PWLF. 771 enum P0U 772 { 773 P0U_UNNAMED46 = 46, //!< No additional details 774 }; 775 776 //! \brief P1U 777 //! \details 778 //! Y Point 1 of the upper part of the detection PWLF. 779 enum P1U 780 { 781 P1U_UNNAMED66 = 66, //!< No additional details 782 }; 783 784 //! \brief P2U 785 //! \details 786 //! Y Point 2 of the upper part of the detection PWLF. 787 enum P2U 788 { 789 P2U_UNNAMED150 = 150, //!< No additional details 790 }; 791 792 //! \brief P3U 793 //! \details 794 //! Y Point 3 of the upper part of the detection PWLF. 795 enum P3U 796 { 797 P3U_UNNAMED236 = 236, //!< No additional details 798 }; 799 800 //! \brief B0U 801 //! \details 802 //! V Bias 0 of the upper part of the detection PWLF. 803 enum B0U 804 { 805 B0U_UNNAMED143 = 143, //!< No additional details 806 }; 807 808 //! \brief B1U 809 //! \details 810 //! V Bias 1 of the upper part of the detection PWLF. 811 enum B1U 812 { 813 B1U_UNNAMED163 = 163, //!< No additional details 814 }; 815 816 //! \brief B2U 817 //! \details 818 //! V Bias 2 of the upper part of the detection PWLF. 819 enum B2U 820 { 821 B2U_UNNAMED200 = 200, //!< No additional details 822 }; 823 824 //! \brief B3U 825 //! \details 826 //! V Bias 3 of the upper part of the detection PWLF. 827 enum B3U 828 { 829 B3U_UNNAMED140 = 140, //!< No additional details 830 }; 831 832 //! \brief C0 833 //! \details 834 //! Transform coefficient 835 enum C0 836 { 837 C0_UNNAMED1024 = 1024, //!< No additional details 838 }; 839 840 //! \brief C1 841 //! \details 842 //! Transform coefficient 843 enum C1 844 { 845 C1_UNNAMED0 = 0, //!< No additional details 846 }; 847 848 //! \brief C2 849 //! \details 850 //! Transform coefficient 851 enum C2 852 { 853 C2_UNNAMED0 = 0, //!< No additional details 854 }; 855 856 //! \brief C3 857 //! \details 858 //! Transform coefficient 859 enum C3 860 { 861 C3_UNNAMED0 = 0, //!< No additional details 862 }; 863 864 //! \brief C4 865 //! \details 866 //! Transform coefficient 867 enum C4 868 { 869 C4_UNNAMED1024 = 1024, //!< No additional details 870 }; 871 872 //! \brief C5 873 //! \details 874 //! Transform coefficient 875 enum C5 876 { 877 C5_UNNAMED0 = 0, //!< No additional details 878 }; 879 880 //! \brief C6 881 //! \details 882 //! Transform coefficient 883 enum C6 884 { 885 C6_UNNAMED0 = 0, //!< No additional details 886 }; 887 888 //! \brief C7 889 //! \details 890 //! Transform coefficient 891 enum C7 892 { 893 C7_UNNAMED0 = 0, //!< No additional details 894 }; 895 896 //! \brief C8 897 //! \details 898 //! Transform coefficient 899 enum C8 900 { 901 C8_UNNAMED1024 = 1024, //!< No additional details 902 }; 903 904 //! \brief OFFSET_IN_1 905 //! \details 906 //! Offset in for Y/R. 907 enum OFFSET_IN_1 908 { 909 OFFSET_IN_1_UNNAMED0 = 0, //!< No additional details 910 }; 911 912 //! \brief OFFSET_OUT_1 913 //! \details 914 //! Offset out for Y/R. 915 enum OFFSET_OUT_1 916 { 917 OFFSET_OUT_1_UNNAMED0 = 0, //!< No additional details 918 }; 919 920 //! \brief OFFSET_IN_2 921 //! \details 922 //! Offset in for U/G. 923 enum OFFSET_IN_2 924 { 925 OFFSET_IN_2_UNNAMED0 = 0, //!< No additional details 926 }; 927 928 //! \brief OFFSET_OUT_2 929 //! \details 930 //! Offset out for U/G. 931 enum OFFSET_OUT_2 932 { 933 OFFSET_OUT_2_UNNAMED0 = 0, //!< No additional details 934 }; 935 936 //! \brief OFFSET_IN_3 937 //! \details 938 //! Offset in for V/B. 939 enum OFFSET_IN_3 940 { 941 OFFSET_IN_3_UNNAMED0 = 0, //!< No additional details 942 }; 943 944 //! \brief OFFSET_OUT_3 945 //! \details 946 //! Offset out for V/B. 947 enum OFFSET_OUT_3 948 { 949 OFFSET_OUT_3_UNNAMED0 = 0, //!< No additional details 950 }; 951 952 //! \name Initializations 953 954 //! \brief Explicit member initialization function 955 SFC_IEF_STATE_CMD(); 956 957 static const size_t dwSize = 24; 958 static const size_t byteSize = 96; 959 }; 960 961 //! 962 //! \brief SFC_FRAME_START 963 //! \details 964 //! This command is sent from VDBOX/VEBOX to SFC pipeline at the start of 965 //! each frame once the lock request is granted. 966 //! 967 struct SFC_FRAME_START_CMD 968 { 969 union 970 { 971 struct 972 { 973 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 974 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 975 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 976 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 977 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 978 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 979 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 980 }; 981 uint32_t Value; 982 } DW0; 983 union 984 { 985 struct 986 { 987 uint32_t Reserved32 ; //!< Reserved 988 }; 989 uint32_t Value; 990 } DW1; 991 992 //! \name Local enumerations 993 994 enum SUBOPCODEB 995 { 996 SUBOPCODEB_SFCFRAMESTART = 4, //!< No additional details 997 }; 998 999 enum SUBOPCODEA 1000 { 1001 SUBOPCODEA_COMMON = 0, //!< No additional details 1002 }; 1003 1004 enum MEDIA_COMMAND_OPCODE 1005 { 1006 MEDIA_COMMAND_OPCODE_MEDIAHEVCSFCMODE = 9, //!< No additional details 1007 MEDIA_COMMAND_OPCODE_MEDIAMISC = 10, //!< Media MFX/VEBOX+SFC Mode 1008 MEDIA_COMMAND_OPCODE_MEDIAAVPSFCMODE = 0xD, //!< No additional details 1009 }; 1010 1011 enum PIPELINE 1012 { 1013 PIPELINE_MEDIA = 2, //!< No additional details 1014 }; 1015 1016 enum COMMAND_TYPE 1017 { 1018 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1019 }; 1020 1021 //! \name Initializations 1022 1023 //! \brief Explicit member initialization function 1024 SFC_FRAME_START_CMD(); 1025 1026 static const size_t dwSize = 2; 1027 static const size_t byteSize = 8; 1028 }; 1029 1030 //! 1031 //! \brief SFC_LOCK 1032 //! \details 1033 //! This command is used for VD/VE box to communicate with SFC before the 1034 //! start of any SFC workload. VD/VE uses this command to make sure that it 1035 //! has the ownership of SFC pipe before running workload with SFC since SFC 1036 //! is shared between VD/VE on a frame level. For VD(MFX)-SFC workload, 1037 //! only decoder mode is allowed. Encoder mode cannot use SFC. 1038 //! 1039 //! For VD(HCP)-SFC workload, only decoder mode is allowed. Encoder mode 1040 //! cannot use SFC 1041 //! 1042 struct SFC_LOCK_CMD 1043 { 1044 union 1045 { 1046 struct 1047 { 1048 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1049 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1050 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 1051 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 1052 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 1053 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1054 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1055 }; 1056 uint32_t Value; 1057 } DW0; 1058 union 1059 { 1060 struct 1061 { 1062 uint32_t VeSfcPipeSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< VE-SFC Pipe Select 1063 uint32_t PreScaledOutputSurfaceOutputEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< Pre-Scaled Output Surface Output Enable 1064 uint32_t SfcDisable : __CODEGEN_BITFIELD( 2, 2) ; //!< SFC_disable 1065 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 31) ; //!< Reserved 1066 }; 1067 uint32_t Value; 1068 } DW1; 1069 1070 //! \name Local enumerations 1071 1072 enum SUBOPCODEB 1073 { 1074 SUBOPCODEB_SFCLOCK = 0, //!< No additional details 1075 }; 1076 1077 enum SUBOPCODEA 1078 { 1079 SUBOPCODEA_COMMON = 0, //!< No additional details 1080 }; 1081 1082 enum MEDIA_COMMAND_OPCODE 1083 { 1084 MEDIA_COMMAND_OPCODE_MEDIAHEVCSFCMODE = 9, //!< No additional details 1085 MEDIA_COMMAND_OPCODE_MEDIAMISC = 10, //!< Media MFX/VEBOX+SFC Mode. For VD(MFX)+SFC mode, only decoder mode is allowed. Encoder mode cannot use SFC 1086 MEDIA_COMMAND_OPCODE_MEDIAAVPSFCMODE = 0xD, //!< No additional details 1087 }; 1088 1089 enum PIPELINE 1090 { 1091 PIPELINE_MEDIA = 2, //!< No additional details 1092 }; 1093 1094 enum COMMAND_TYPE 1095 { 1096 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1097 }; 1098 1099 //! \name Initializations 1100 1101 //! \brief Explicit member initialization function 1102 SFC_LOCK_CMD(); 1103 1104 static const size_t dwSize = 2; 1105 static const size_t byteSize = 8; 1106 }; 1107 1108 //! 1109 //! \brief SFC_STATE 1110 //! \details 1111 //! This command is sent from VDBOX/HCP/VEBOX to SFC pipeline at the start 1112 //! of each frame once the lock request is granted. 1113 //! 1114 struct SFC_STATE_CMD 1115 { 1116 union 1117 { 1118 struct 1119 { 1120 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1121 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1122 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 1123 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 1124 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 1125 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1126 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1127 }; 1128 uint32_t Value; 1129 } DW0; 1130 union 1131 { 1132 struct 1133 { 1134 uint32_t SfcPipeMode : __CODEGEN_BITFIELD( 0, 3) ; //!< SFC_PIPE_MODE 1135 uint32_t SfcInputChromaSubSampling : __CODEGEN_BITFIELD( 4, 7) ; //!< SFC_INPUT_CHROMA_SUB_SAMPLING 1136 uint32_t VdVeInputOrderingMode : __CODEGEN_BITFIELD( 8, 10) ; //!< VDVE_INPUT_ORDERING_MODE 1137 uint32_t Reserved43 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1138 uint32_t SfcEngineMode : __CODEGEN_BITFIELD(12, 13) ; //!< SFC_ENGINE_MODE 1139 uint32_t Reserved46 : __CODEGEN_BITFIELD(14, 17) ; //!< Reserved 1140 uint32_t InputFrameDataFormat : __CODEGEN_BITFIELD(18, 19) ; //!< INPUT_FRAME_DATA_FORMAT 1141 uint32_t OutputFrameDataFormat : __CODEGEN_BITFIELD(20, 21) ; //!< OUTPUT_FRAME_DATA_FORMAT 1142 uint32_t TopBottomField : __CODEGEN_BITFIELD(22, 22) ; //!< Top/Bottom field 1143 uint32_t TopBottomFieldFirst : __CODEGEN_BITFIELD(23, 23) ; //!< Top/Bottom field first 1144 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1145 }; 1146 uint32_t Value; 1147 } DW1; 1148 union 1149 { 1150 struct 1151 { 1152 uint32_t InputFrameResolutionWidth : __CODEGEN_BITFIELD( 0, 13) ; //!< Input Frame Resolution Width 1153 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1154 uint32_t InputFrameResolutionHeight : __CODEGEN_BITFIELD(16, 29) ; //!< Input Frame Resolution Height 1155 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1156 }; 1157 uint32_t Value; 1158 } DW2; 1159 union 1160 { 1161 struct 1162 { 1163 uint32_t OutputSurfaceFormatType : __CODEGEN_BITFIELD( 0, 3) ; //!< OUTPUT_SURFACE_FORMAT_TYPE 1164 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 4) ; //!< Reserved 1165 uint32_t ChannelSwapEnable : __CODEGEN_BITFIELD( 5, 5) ; //!< Channel_Swap Enable 1166 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 1167 uint32_t OutputChromaDownsamplingCoSitingPositionVerticalDirection : __CODEGEN_BITFIELD( 8, 11) ; //!< OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION 1168 uint32_t OutputChromaDownsamplingCoSitingPositionHorizontalDirection : __CODEGEN_BITFIELD(12, 15) ; //!< OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION 1169 uint32_t InputColorSpace0Yuv1Rgb : __CODEGEN_BITFIELD(16, 16) ; //!< INPUT_COLOR_SPACE_0_YUV1_RGB 1170 uint32_t DitherEnable : __CODEGEN_BITFIELD(17, 17) ; //!< Dither Enable 1171 uint32_t OutputCompressionFormat : __CODEGEN_BITFIELD(18, 21) ; //!< OUTPUT_COMPRESSION_FORMAT 1172 uint32_t Reserved103 : __CODEGEN_BITFIELD(22, 22) ; //!< Reserved 1173 uint32_t RgbPlanarMemoryFormatEnable : __CODEGEN_BITFIELD(23, 23) ; //!< RGB planar memory format enable 1174 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1175 }; 1176 uint32_t Value; 1177 } DW3; 1178 union 1179 { 1180 struct 1181 { 1182 uint32_t IefEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< IEF_ENABLE 1183 uint32_t SkinToneTunedIefEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< Skin Tone Tuned IEF_Enable 1184 uint32_t Ief4SmoothEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< IEF4SMOOTH_ENABLE_ 1185 uint32_t Enable8TapForChromaChannelsFiltering : __CODEGEN_BITFIELD( 3, 3) ; //!< Enable 8 tap for Chroma channels filtering 1186 uint32_t AvsFilterMode : __CODEGEN_BITFIELD( 4, 5) ; //!< AVS_FILTER_MODE 1187 uint32_t AdaptiveFilterForAllChannels : __CODEGEN_BITFIELD( 6, 6) ; //!< ADAPTIVE_FILTER_FOR_ALL_CHANNELS 1188 uint32_t AvsScalingEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< AVS_SCALING_ENABLE 1189 uint32_t BypassYAdaptiveFiltering : __CODEGEN_BITFIELD( 8, 8) ; //!< BYPASS_Y_ADAPTIVE_FILTERING 1190 uint32_t BypassXAdaptiveFiltering : __CODEGEN_BITFIELD( 9, 9) ; //!< BYPASS_X_ADAPTIVE_FILTERING 1191 uint32_t RgbAdaptive : __CODEGEN_BITFIELD(10, 10) ; //!< RGB Adaptive 1192 uint32_t Reserved139 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1193 uint32_t ChromaUpsamplingEnable : __CODEGEN_BITFIELD(12, 12) ; //!< Chroma Upsampling Enable 1194 uint32_t MirrorType : __CODEGEN_BITFIELD(13, 13) ; //!< MIRROR_TYPE 1195 uint32_t MirrorMode : __CODEGEN_BITFIELD(14, 14) ; //!< MIRROR_MODE 1196 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1197 uint32_t RotationMode : __CODEGEN_BITFIELD(16, 17) ; //!< ROTATION_MODE 1198 uint32_t ColorFillEnable : __CODEGEN_BITFIELD(18, 18) ; //!< Color Fill Enable 1199 uint32_t CscEnable : __CODEGEN_BITFIELD(19, 19) ; //!< CSC Enable 1200 uint32_t Bitdepth : __CODEGEN_BITFIELD(20, 21) ; //!< BITDEPTH 1201 uint32_t TileType : __CODEGEN_BITFIELD(22, 22) ; //!< Tile Type 1202 uint32_t HistogramStreamout : __CODEGEN_BITFIELD(23, 23) ; //!< Histogram Streamout 1203 uint32_t Reserved152 : __CODEGEN_BITFIELD(24, 30) ; //!< Reserved 1204 uint32_t SfdChickenBit : __CODEGEN_BITFIELD(31, 31) ; //!< SFD chicken bit 1205 }; 1206 uint32_t Value; 1207 } DW4; 1208 union 1209 { 1210 struct 1211 { 1212 uint32_t SourceRegionWidth : __CODEGEN_BITFIELD( 0, 13) ; //!< Source Region Width 1213 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1214 uint32_t SourceRegionHeight : __CODEGEN_BITFIELD(16, 29) ; //!< Source Region Height 1215 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1216 }; 1217 uint32_t Value; 1218 } DW5; 1219 union 1220 { 1221 struct 1222 { 1223 uint32_t SourceRegionHorizontalOffset : __CODEGEN_BITFIELD( 0, 13) ; //!< Source Region Horizontal Offset 1224 uint32_t Reserved206 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1225 uint32_t SourceRegionVerticalOffset : __CODEGEN_BITFIELD(16, 29) ; //!< Source Region Vertical Offset 1226 uint32_t Reserved222 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1227 }; 1228 uint32_t Value; 1229 } DW6; 1230 union 1231 { 1232 struct 1233 { 1234 uint32_t OutputFrameWidth : __CODEGEN_BITFIELD( 0, 13) ; //!< Output Frame Width 1235 uint32_t Reserved238 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1236 uint32_t OutputFrameHeight : __CODEGEN_BITFIELD(16, 29) ; //!< Output Frame Height 1237 uint32_t Reserved254 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1238 }; 1239 uint32_t Value; 1240 } DW7; 1241 union 1242 { 1243 struct 1244 { 1245 uint32_t ScaledRegionSizeWidth : __CODEGEN_BITFIELD( 0, 13) ; //!< Scaled Region Size Width 1246 uint32_t Reserved270 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1247 uint32_t ScaledRegionSizeHeight : __CODEGEN_BITFIELD(16, 29) ; //!< Scaled Region Size Height 1248 uint32_t Reserved286 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1249 }; 1250 uint32_t Value; 1251 } DW8; 1252 union 1253 { 1254 struct 1255 { 1256 uint32_t ScaledRegionHorizontalOffset : __CODEGEN_BITFIELD( 0, 14) ; //!< Scaled Region Horizontal Offset 1257 uint32_t Reserved303 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1258 uint32_t ScaledRegionVerticalOffset : __CODEGEN_BITFIELD(16, 30) ; //!< Scaled Region Vertical Offset 1259 uint32_t Reserved319 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 1260 }; 1261 uint32_t Value; 1262 } DW9; 1263 union 1264 { 1265 struct 1266 { 1267 uint32_t GrayBarPixelUG : __CODEGEN_BITFIELD( 0, 9) ; //!< Gray Bar Pixel - U/G 1268 uint32_t Reserved330 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1269 uint32_t GrayBarPixelYR : __CODEGEN_BITFIELD(16, 25) ; //!< Gray Bar Pixel - Y/R 1270 uint32_t Reserved346 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 1271 }; 1272 uint32_t Value; 1273 } DW10; 1274 union 1275 { 1276 struct 1277 { 1278 uint32_t GrayBarPixelA : __CODEGEN_BITFIELD( 0, 9) ; //!< Gray Bar Pixel - A 1279 uint32_t Reserved362 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1280 uint32_t GrayBarPixelVB : __CODEGEN_BITFIELD(16, 25) ; //!< Gray Bar Pixel - V/B 1281 uint32_t Reserved378 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 1282 }; 1283 uint32_t Value; 1284 } DW11; 1285 union 1286 { 1287 struct 1288 { 1289 uint32_t UvDefaultValueForUChannelForMonoInputSupport : __CODEGEN_BITFIELD( 0, 9) ; //!< UV Default value for U channel (For Mono Input Support) 1290 uint32_t Reserved394 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1291 uint32_t UvDefaultValueForVChannelForMonoInputSupport : __CODEGEN_BITFIELD(16, 25) ; //!< UV Default value for V channel (For Mono Input Support) 1292 uint32_t Reserved410 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 1293 }; 1294 uint32_t Value; 1295 } DW12; 1296 union 1297 { 1298 struct 1299 { 1300 uint32_t AlphaDefaultValue : __CODEGEN_BITFIELD( 0, 9) ; //!< Alpha Default Value 1301 uint32_t Reserved426 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 1302 }; 1303 uint32_t Value; 1304 } DW13; 1305 union 1306 { 1307 struct 1308 { 1309 uint32_t Reserved448 : __CODEGEN_BITFIELD( 0, 4) ; //!< Reserved 1310 uint32_t ScalingFactorHeight : __CODEGEN_BITFIELD( 5, 27) ; //!< Scaling Factor Height 1311 uint32_t Reserved476 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1312 }; 1313 uint32_t Value; 1314 } DW14; 1315 union 1316 { 1317 struct 1318 { 1319 uint32_t Reserved480 : __CODEGEN_BITFIELD( 0, 4) ; //!< Reserved 1320 uint32_t ScaleFactorWidth : __CODEGEN_BITFIELD( 5, 27) ; //!< Scale Factor Width 1321 uint32_t Reserved508 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1322 }; 1323 uint32_t Value; 1324 } DW15; 1325 union 1326 { 1327 struct 1328 { 1329 uint32_t Reserved512 ; //!< Reserved 1330 }; 1331 uint32_t Value; 1332 } DW16; 1333 union 1334 { 1335 struct 1336 { 1337 uint32_t Reserved544 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1338 uint32_t OutputFrameSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< Output Frame Surface Base Address 1339 }; 1340 uint32_t Value; 1341 } DW17; 1342 union 1343 { 1344 struct 1345 { 1346 uint32_t OutputFrameSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Output Frame Surface Base Address High 1347 uint32_t Reserved592 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1348 }; 1349 uint32_t Value; 1350 } DW18; 1351 union 1352 { 1353 struct 1354 { 1355 uint32_t Reserved608 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1356 uint32_t OutputFrameSurfaceBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Output Frame Surface Base Address - Index to Memory Object Control State (MOCS) Tables 1357 uint32_t OutputFrameSurfaceBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Output Frame Surface Base Address - Arbitration Priority Control 1358 uint32_t Reserved617 : __CODEGEN_BITFIELD( 9, 11) ; //!< Reserved 1359 uint32_t OutputFrameSurfaceBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< OUTPUT_FRAME_SURFACE_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1360 uint32_t Reserved621 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1361 }; 1362 uint32_t Value; 1363 } DW19; 1364 union 1365 { 1366 struct 1367 { 1368 uint32_t Reserved640 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1369 uint32_t AvsLineBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< AVS Line Buffer Surface Base Address 1370 }; 1371 uint32_t Value; 1372 } DW20; 1373 union 1374 { 1375 struct 1376 { 1377 uint32_t AvsLineBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< AVS Line Buffer Surface Base Address High 1378 uint32_t Reserved688 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1379 }; 1380 uint32_t Value; 1381 } DW21; 1382 union 1383 { 1384 struct 1385 { 1386 uint32_t Reserved704 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1387 uint32_t AvsLineBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< AVS Line Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1388 uint32_t AvsLineBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< AVS Line Buffer Base Address - Arbitration Priority Control 1389 uint32_t Reserved713 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 1390 uint32_t AvsLineBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< AVS_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 1391 uint32_t Reserved715 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1392 uint32_t AvsLineBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< AVS_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1393 uint32_t Reserved717 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1394 }; 1395 uint32_t Value; 1396 } DW22; 1397 union 1398 { 1399 struct 1400 { 1401 uint32_t Reserved736 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1402 uint32_t IefLineBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< IEF Line Buffer Surface Base Address 1403 }; 1404 uint32_t Value; 1405 } DW23; 1406 union 1407 { 1408 struct 1409 { 1410 uint32_t IefLineBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< IEF Line Buffer Surface Base Address High 1411 uint32_t Reserved784 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1412 }; 1413 uint32_t Value; 1414 } DW24; 1415 union 1416 { 1417 struct 1418 { 1419 uint32_t Reserved800 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1420 uint32_t IefLineBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< IEF Line Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1421 uint32_t IefLineBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< IEF Line Buffer Base Address - Arbitration Priority Control 1422 uint32_t Reserved809 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 1423 uint32_t IefLineBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< IEF_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 1424 uint32_t Reserved811 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1425 uint32_t IefLineBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< IEF_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1426 uint32_t Reserved813 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1427 }; 1428 uint32_t Value; 1429 } DW25; 1430 union 1431 { 1432 struct 1433 { 1434 uint32_t Reserved832 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1435 uint32_t SfdLineBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< SFD Line Buffer Surface Base Address 1436 }; 1437 uint32_t Value; 1438 } DW26; 1439 union 1440 { 1441 struct 1442 { 1443 uint32_t SfdLineBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< SFD Line Buffer Surface Base Address High 1444 uint32_t Reserved880 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1445 }; 1446 uint32_t Value; 1447 } DW27; 1448 union 1449 { 1450 struct 1451 { 1452 uint32_t Reserved896 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1453 uint32_t SfdLineBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< SFD Line Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1454 uint32_t SfdLineBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< SFD Line Buffer Base Address - Arbitration Priority Control 1455 uint32_t Reserved905 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 1456 uint32_t SfdLineBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< SFD_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 1457 uint32_t Reserved907 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1458 uint32_t SfdLineBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< SFD_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1459 uint32_t Reserved909 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1460 }; 1461 uint32_t Value; 1462 } DW28; 1463 union 1464 { 1465 struct 1466 { 1467 uint32_t TiledMode : __CODEGEN_BITFIELD( 0, 1) ; //!< TILED_MODE 1468 uint32_t OutputSurfaceHalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< Output Surface Half Pitch For Chroma 1469 uint32_t OutputSurfacePitch : __CODEGEN_BITFIELD( 3, 21) ; //!< Output Surface Pitch 1470 uint32_t Reserved950 : __CODEGEN_BITFIELD(22, 26) ; //!< Reserved 1471 uint32_t OutputSurfaceInterleaveChromaEnable : __CODEGEN_BITFIELD(27, 27) ; //!< Output Surface Interleave Chroma Enable 1472 uint32_t OutputSurfaceFormat : __CODEGEN_BITFIELD(28, 31) ; //!< Output Surface Format 1473 }; 1474 uint32_t Value; 1475 } DW29; 1476 union 1477 { 1478 struct 1479 { 1480 uint32_t OutputSurfaceYOffsetForU : __CODEGEN_BITFIELD( 0, 15) ; //!< Output Surface Y Offset For U 1481 uint32_t OutputSurfaceXOffsetForU : __CODEGEN_BITFIELD(16, 31) ; //!< Output Surface X Offset For U 1482 }; 1483 uint32_t Value; 1484 } DW30; 1485 union 1486 { 1487 struct 1488 { 1489 uint32_t OutputSurfaceYOffsetForV : __CODEGEN_BITFIELD( 0, 15) ; //!< Output Surface Y Offset For V 1490 uint32_t OutputSurfaceXOffsetForV : __CODEGEN_BITFIELD(16, 31) ; //!< Output Surface X Offset For V 1491 }; 1492 uint32_t Value; 1493 } DW31; 1494 union 1495 { 1496 struct 1497 { 1498 uint32_t Reserved1024 ; //!< Reserved 1499 }; 1500 uint32_t Value; 1501 } DW32; 1502 union 1503 { 1504 struct 1505 { 1506 uint32_t Av1TileColumnNumber : __CODEGEN_BITFIELD( 0, 7) ; //!< AV1 Tile column number 1507 uint32_t Av1TileRowNumber : __CODEGEN_BITFIELD( 8, 15) ; //!< AV1 Tile row number 1508 uint32_t Reserved1072 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1509 }; 1510 uint32_t Value; 1511 } DW33; 1512 union 1513 { 1514 struct 1515 { 1516 uint32_t Sourcestartx : __CODEGEN_BITFIELD( 0, 13) ; //!< SourceStartX 1517 uint32_t Reserved1102 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1518 uint32_t Sourceendx : __CODEGEN_BITFIELD(16, 29) ; //!< SourceEndX 1519 uint32_t Reserved1118 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1520 }; 1521 uint32_t Value; 1522 } DW34; 1523 union 1524 { 1525 struct 1526 { 1527 uint32_t Destinationstartx : __CODEGEN_BITFIELD( 0, 13) ; //!< DestinationStartX 1528 uint32_t Reserved1134 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1529 uint32_t Destinationendx : __CODEGEN_BITFIELD(16, 29) ; //!< DestinationEndX 1530 uint32_t Reserved1150 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1531 }; 1532 uint32_t Value; 1533 } DW35; 1534 union 1535 { 1536 struct 1537 { 1538 uint32_t Reserved1152 : __CODEGEN_BITFIELD( 0, 4) ; //!< Reserved 1539 uint32_t Xphaseshift : __CODEGEN_BITFIELD( 5, 28) ; //!< Xphaseshift 1540 uint32_t Reserved1181 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1541 }; 1542 uint32_t Value; 1543 } DW36; 1544 union 1545 { 1546 struct 1547 { 1548 uint32_t Reserved1184 : __CODEGEN_BITFIELD( 0, 4) ; //!< Reserved 1549 uint32_t Yphaseshift : __CODEGEN_BITFIELD( 5, 28) ; //!< Yphaseshift 1550 uint32_t Reserved1213 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1551 }; 1552 uint32_t Value; 1553 } DW37; 1554 union 1555 { 1556 struct 1557 { 1558 uint32_t Reserved1216 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1559 uint32_t AvsLineTileBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< AVS Line Tile Buffer Surface Base Address 1560 }; 1561 uint32_t Value; 1562 } DW38; 1563 union 1564 { 1565 struct 1566 { 1567 uint32_t AvsLineTileBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< AVS Line Tile Buffer Surface Base Address High 1568 uint32_t Reserved1264 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1569 }; 1570 uint32_t Value; 1571 } DW39; 1572 union 1573 { 1574 struct 1575 { 1576 uint32_t Reserved1280 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1577 uint32_t AvsLineTileBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< AVS Line Tile Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1578 uint32_t AvsLineTileBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< AVS Line Tile Buffer Base Address - Arbitration Priority Control 1579 uint32_t Reserved1289 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 1580 uint32_t AvsLineTileBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< AVS_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 1581 uint32_t Reserved1291 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1582 uint32_t AvsLineTileBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< AVS_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1583 uint32_t Reserved1293 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1584 }; 1585 uint32_t Value; 1586 } DW40; 1587 union 1588 { 1589 struct 1590 { 1591 uint32_t Reserved1312 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1592 uint32_t IefLineTileBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< IEF Line Tile Buffer Surface Base Address 1593 }; 1594 uint32_t Value; 1595 } DW41; 1596 union 1597 { 1598 struct 1599 { 1600 uint32_t IefLineTileBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< IEF Line Tile Buffer Surface Base Address High 1601 uint32_t Reserved1360 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1602 }; 1603 uint32_t Value; 1604 } DW42; 1605 union 1606 { 1607 struct 1608 { 1609 uint32_t Reserved1376 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1610 uint32_t IefLineTileBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< IEF Line Tile Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1611 uint32_t IefLineTileBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< IEF Line Tile Buffer Base Address - Arbitration Priority Control 1612 uint32_t Reserved1385 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 1613 uint32_t IefLineTileBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< IEF_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 1614 uint32_t Reserved1387 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1615 uint32_t IefLineTileBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< IEF_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1616 uint32_t Reserved1389 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1617 }; 1618 uint32_t Value; 1619 } DW43; 1620 union 1621 { 1622 struct 1623 { 1624 uint32_t Reserved1408 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1625 uint32_t SfdLineTileBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< SFD Line Tile Buffer Surface Base Address 1626 }; 1627 uint32_t Value; 1628 } DW44; 1629 union 1630 { 1631 struct 1632 { 1633 uint32_t SfdLineTileBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< SFD Line Tile Buffer Surface Base Address High 1634 uint32_t Reserved1456 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1635 }; 1636 uint32_t Value; 1637 } DW45; 1638 union 1639 { 1640 struct 1641 { 1642 uint32_t Reserved1472 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1643 uint32_t SfdLineTileBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< SFD Line Tile Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1644 uint32_t SfdLineTileBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< SFD Line Tile Buffer Base Address - Arbitration Priority Control 1645 uint32_t Reserved1481 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 1646 uint32_t SfdLineTileBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< SFD_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 1647 uint32_t Reserved1483 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1648 uint32_t SfdLineTileBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< SFD_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1649 uint32_t Reserved1485 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1650 }; 1651 uint32_t Value; 1652 } DW46; 1653 union 1654 { 1655 struct 1656 { 1657 uint32_t Reserved1504 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1658 uint32_t HistogramSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< Histogram Surface Base Address 1659 }; 1660 uint32_t Value; 1661 } DW47; 1662 union 1663 { 1664 struct 1665 { 1666 uint32_t HistogramSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Histogram Surface Base Address High 1667 uint32_t Reserved1552 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1668 }; 1669 uint32_t Value; 1670 } DW48; 1671 union 1672 { 1673 struct 1674 { 1675 uint32_t Reserved1568 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1676 uint32_t HisgotramBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Hisgotram Base Address - Index to Memory Object Control State (MOCS) Tables 1677 uint32_t HistogramBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Histogram Base Address - Arbitration Priority Control 1678 uint32_t Reserved1577 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 1679 uint32_t HistogramBaseAddressMemoryCompressionType : __CODEGEN_BITFIELD(10, 10) ; //!< HISTOGRAM_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE 1680 uint32_t Reserved1579 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1681 uint32_t HistogramBaseAddressCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< HISTOGRAM_BASE_ADDRESS_CACHE_SELECT 1682 uint32_t Reserved1581 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1683 }; 1684 uint32_t Value; 1685 } DW49; 1686 union 1687 { 1688 struct 1689 { 1690 uint32_t DitheringLutDelta12 : __CODEGEN_BITFIELD( 0, 2) ; //!< Dithering LUT delta 12 1691 uint32_t Reserved1603 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 1692 uint32_t DitheringLutDelta13 : __CODEGEN_BITFIELD( 8, 10) ; //!< Dithering LUT delta 13 1693 uint32_t Reserved1611 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1694 uint32_t DitheringLutDelta14 : __CODEGEN_BITFIELD(16, 18) ; //!< Dithering LUT delta 14 1695 uint32_t Reserved1619 : __CODEGEN_BITFIELD(19, 23) ; //!< Reserved 1696 uint32_t DitheringLutDelta15 : __CODEGEN_BITFIELD(24, 26) ; //!< Dithering LUT delta 15 1697 uint32_t Reserved1627 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1698 }; 1699 uint32_t Value; 1700 } DW50; 1701 union 1702 { 1703 struct 1704 { 1705 uint32_t DitheringLutDelta8 : __CODEGEN_BITFIELD( 0, 2) ; //!< Dithering LUT delta 8 1706 uint32_t Reserved1635 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 1707 uint32_t DitheringLutDelta9 : __CODEGEN_BITFIELD( 8, 10) ; //!< Dithering LUT delta 9 1708 uint32_t Reserved1643 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1709 uint32_t DitheringLutDelta10 : __CODEGEN_BITFIELD(16, 18) ; //!< Dithering LUT delta 10 1710 uint32_t Reserved1651 : __CODEGEN_BITFIELD(19, 23) ; //!< Reserved 1711 uint32_t DitheringLutDelta11 : __CODEGEN_BITFIELD(24, 26) ; //!< Dithering LUT delta 11 1712 uint32_t Reserved1659 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1713 }; 1714 uint32_t Value; 1715 } DW51; 1716 union 1717 { 1718 struct 1719 { 1720 uint32_t DitheringLutDelta4 : __CODEGEN_BITFIELD( 0, 2) ; //!< Dithering LUT delta 4 1721 uint32_t Reserved1667 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 1722 uint32_t DitheringLutDelta5 : __CODEGEN_BITFIELD( 8, 10) ; //!< Dithering LUT delta 5 1723 uint32_t Reserved1675 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1724 uint32_t DitheringLutDelta6 : __CODEGEN_BITFIELD(16, 18) ; //!< Dithering LUT delta 6 1725 uint32_t Reserved1683 : __CODEGEN_BITFIELD(19, 23) ; //!< Reserved 1726 uint32_t DitheringLutDelta7 : __CODEGEN_BITFIELD(24, 26) ; //!< Dithering LUT delta 7 1727 uint32_t Reserved1691 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1728 }; 1729 uint32_t Value; 1730 } DW52; 1731 union 1732 { 1733 struct 1734 { 1735 uint32_t DitheringLutDelta0 : __CODEGEN_BITFIELD( 0, 2) ; //!< Dithering LUT delta 0 1736 uint32_t Reserved1699 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 1737 uint32_t DitheringLutDelta1 : __CODEGEN_BITFIELD( 8, 10) ; //!< Dithering LUT delta 1 1738 uint32_t Reserved1707 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1739 uint32_t DitheringLutDelta2 : __CODEGEN_BITFIELD(16, 18) ; //!< Dithering LUT delta 2 1740 uint32_t Reserved1715 : __CODEGEN_BITFIELD(19, 23) ; //!< Reserved 1741 uint32_t DitheringLutDelta3 : __CODEGEN_BITFIELD(24, 26) ; //!< Dithering LUT delta 3 1742 uint32_t Reserved1723 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1743 }; 1744 uint32_t Value; 1745 } DW53; 1746 union 1747 { 1748 struct 1749 { 1750 uint32_t BottomFieldVerticalScalingOffset : __CODEGEN_BITFIELD( 0, 23) ; //!< Bottom field vertical scaling offset 1751 uint32_t Reserved1752 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1752 }; 1753 uint32_t Value; 1754 } DW54; 1755 union 1756 { 1757 struct 1758 { 1759 uint32_t Reserved1760 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1760 uint32_t BottomFieldBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< Bottom field base address 1761 }; 1762 uint32_t Value; 1763 } DW55; 1764 union 1765 { 1766 struct 1767 { 1768 uint32_t BottomFieldBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Bottom field base address high 1769 uint32_t Reserved1808 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1770 }; 1771 uint32_t Value; 1772 } DW56; 1773 union 1774 { 1775 struct 1776 { 1777 uint32_t Reserved1824 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1778 uint32_t BottomFieldSurfaceBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Bottom field Surface Base Address - Index to Memory Object Control State (MOCS) Tables 1779 uint32_t BottomFieldSurfaceBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Bottom field Surface Base Address - Arbitration Priority Control 1780 uint32_t Reserved1833 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 1781 uint32_t BottomFiledSurfaceBaseAddressMemoryCompressionType : __CODEGEN_BITFIELD(10, 10) ; //!< BOTTOM_FILED_SURFACE_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE 1782 uint32_t Reserved1835 : __CODEGEN_BITFIELD(11, 31) ; //!< Reserved 1783 }; 1784 uint32_t Value; 1785 } DW57; 1786 union 1787 { 1788 struct 1789 { 1790 uint32_t BottomFieldSurfaceTileWalk : __CODEGEN_BITFIELD( 0, 0) ; //!< BOTTOM_FIELD_SURFACE_TILE_WALK 1791 uint32_t BottomFieldSurfaceTiled : __CODEGEN_BITFIELD( 1, 1) ; //!< BOTTOM_FIELD_SURFACE_TILED 1792 uint32_t BottomFieldSurfaceHalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< Bottom field Surface Half Pitch For Chroma 1793 uint32_t BottomFieldSurfacePitch : __CODEGEN_BITFIELD( 3, 19) ; //!< Bottom field Surface Pitch 1794 uint32_t Reserved1878 : __CODEGEN_BITFIELD(22, 26) ; //!< Reserved 1795 uint32_t BottomFieldSurfaceInterleaveChromaEnable : __CODEGEN_BITFIELD(27, 27) ; //!< Bottom field Surface Interleave Chroma Enable 1796 uint32_t Reserved1884 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1797 }; 1798 uint32_t Value; 1799 } DW58; 1800 union 1801 { 1802 struct 1803 { 1804 uint32_t BottomFieldSurfaceYOffsetForU : __CODEGEN_BITFIELD( 0, 15) ; //!< Bottom field Surface Y Offset For U 1805 uint32_t BottomFieldSurfaceXOffsetForU : __CODEGEN_BITFIELD(16, 31) ; //!< Bottom field Surface X Offset For U 1806 }; 1807 uint32_t Value; 1808 } DW59; 1809 union 1810 { 1811 struct 1812 { 1813 uint32_t BottomFieldSurfaceYOffsetForV : __CODEGEN_BITFIELD( 0, 15) ; //!< Bottom field Surface Y Offset For V 1814 uint32_t BottomFieldSurfaceXOffsetForV : __CODEGEN_BITFIELD(16, 31) ; //!< Bottom field Surface X Offset For V 1815 }; 1816 uint32_t Value; 1817 } DW60; 1818 union 1819 { 1820 struct 1821 { 1822 uint32_t TargetRectangleStartHorizontalOffset : __CODEGEN_BITFIELD( 0, 13) ; //!< Target rectangle start Horizontal Offset 1823 uint32_t Reserved1966 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1824 uint32_t TargetRectangleStartVerticalOffset : __CODEGEN_BITFIELD(16, 29) ; //!< Target rectangle start Vertical Offset 1825 uint32_t Reserved1982 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1826 }; 1827 uint32_t Value; 1828 } DW61; 1829 union 1830 { 1831 struct 1832 { 1833 uint32_t TargetRectangleEndHorizontalOffset : __CODEGEN_BITFIELD( 0, 13) ; //!< Target rectangle end Horizontal Offset 1834 uint32_t Reserved1998 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1835 uint32_t TargetRectangleEndVerticalOffset : __CODEGEN_BITFIELD(16, 29) ; //!< Target rectangle end Vertical Offset 1836 uint32_t Reserved2014 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1837 }; 1838 uint32_t Value; 1839 } DW62; 1840 1841 //! \name Local enumerations 1842 1843 enum SUBOPCODEB 1844 { 1845 SUBOPCODEB_SFCSTATE = 1, //!< No additional details 1846 }; 1847 1848 enum SUBOPCODEA 1849 { 1850 SUBOPCODEA_COMMON = 0, //!< No additional details 1851 }; 1852 1853 enum MEDIA_COMMAND_OPCODE 1854 { 1855 MEDIA_COMMAND_OPCODE_MEDIAHCPSFCMODE = 9, //!< No additional details 1856 MEDIA_COMMAND_OPCODE_MEDIAMFXVEBOXSFCMODE = 10, //!< No additional details 1857 MEDIA_COMMAND_OPCODE_MEDIAAVPSFCMODE = 0xD, //!< No additional details 1858 }; 1859 1860 enum PIPELINE 1861 { 1862 PIPELINE_MEDIA = 2, //!< No additional details 1863 }; 1864 1865 enum COMMAND_TYPE 1866 { 1867 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1868 }; 1869 1870 //! \brief SFC_PIPE_MODE 1871 //! \details 1872 //! Note: for SFC Pipe mode set to VE-to-SFC AVS mode. IECP pipeline mode 1873 //! MUST be enabled. However, each sub-IECP feature can be turned on/off 1874 //! independently. 1875 enum SFC_PIPE_MODE 1876 { 1877 SFC_PIPE_MODE_UNNAMED0 = 0, //!< VD-to-SFC AVS 1878 SFC_PIPE_MODE_UNNAMED1 = 1, //!< VE-to-SFC AVS + IEF + Rotation 1879 SFC_PIPE_MODE_UNNAMED2 = 2, //!< HCP-to-SFC AVS 1880 SFC_PIPE_MODE_UNNAMED3 = 3, //!< Reserved 1881 SFC_PIPE_MODE_UNNAMED4 = 4, //!< VE-to-SFC Integral Image 1882 SFC_PIPE_MODE_UNNAMED5 = 5, //!< VD/AV1-to_SFC AVS 1883 }; 1884 1885 //! \brief SFC_INPUT_CHROMA_SUB_SAMPLING 1886 //! \details 1887 //! This field shall be programmed according to video modes used in VDBOX. 1888 //! NOTE: SFC supports progressive input and output only (Interlaced/MBAFF 1889 //! is not supported).<table border="1"><tbody><tr><td>Video 1890 //! Mode</td><td>Surface Format</td><td>SFC Input Chroma 1891 //! Sub-Sampling</td><td>VD/VE Input Ordering Mode</td></tr><tr><td>VC1 w/o 1892 //! LF and w/o OS Note: VC1 LF applies for either ILDB</td><td>420 1893 //! (NV12)</td><td>1</td><td>0</td></tr><tr><td>VC1 w/ LF or w/ OS or w/ 1894 //! both Note: VC1 LF applies for either ILDB</td><td /><td>INVALID with 1895 //! SFC</td><td>INVALID with SFC</td></tr><tr><td>AVC w/o 1896 //! LF</td><td>Monochrome</td><td>0</td><td>0</td></tr><tr><td>AVC w/o 1897 //! LF</td><td>420 (NV12)</td><td>1</td><td>0</td></tr><tr><td>AVC with 1898 //! LF</td><td>Monochrome</td><td>0</td><td>1</td></tr><tr><td>AVC/VP8 with 1899 //! LF</td><td>420 (NV12)</td><td>1</td><td>1</td></tr><tr><td>VP8 w/o 1900 //! LF</td><td>420 (NV12)</td><td>1</td><td>4</td></tr><tr><td>JPEG (YUV 1901 //! Interleaved)</td><td>Monochrome</td><td>0</td><td>2</td></tr><tr><td>JPEG 1902 //! (YUV Interleaved)</td><td>420</td><td>1</td><td>3</td></tr><tr><td>JPEG 1903 //! (YUV 1904 //! Interleaved)</td><td>422H_2Y</td><td>2</td><td>2</td></tr><tr><td>JPEG 1905 //! (YUV 1906 //! Interleaved)</td><td>422H_4Y</td><td>2</td><td>3</td></tr><tr><td>JPEG 1907 //! (YUV 1908 //! Interleaved)</td><td>444</td><td>4</td><td>2</td></tr></tbody></table>This 1909 //! field shall be programmed according to Image enhancement modes used in 1910 //! VEBOX.<table border="1"><tbody><tr><td>VEBOX MODE</td><td>Surface 1911 //! Format</td><td>SFC Input Chroma Sub Sampling</td><td>VD/VE Input 1912 //! Ordering Mode</td></tr><tr><td>Legacy DN/DI/IECP 1913 //! features</td><td>Monochrome</td><td>0</td><td>0</td></tr><tr><td>Legacy 1914 //! DN/DI/IECP features</td><td>420 1915 //! (NV12)</td><td>1</td><td>0</td></tr><tr><td>Legacy DN/DI/IECP 1916 //! features</td><td>422H</td><td>2</td><td>0</td></tr><tr><td>Legacy 1917 //! DN/DI/IECP 1918 //! features</td><td>444</td><td>4</td><td>0</td></tr><tr><td>Capture/Camera 1919 //! pipe 1920 //! enabled(Demosaic)</td><td>Monochrome</td><td>0</td><td>1</td></tr><tr><td>Capture/Camera 1921 //! pipe enabled(Demosaic)</td><td>420 1922 //! (NV12)</td><td>1</td><td>1</td></tr><tr><td>Capture/Camera pipe 1923 //! enabled(Demosaic)</td><td>422H</td><td>2</td><td>1</td></tr><tr><td>Capture/Camera 1924 //! pipe 1925 //! enabled(Demosaic)</td><td>444</td><td>4</td><td>1</td></tr></tbody></table> 1926 enum SFC_INPUT_CHROMA_SUB_SAMPLING 1927 { 1928 SFC_INPUT_CHROMA_SUB_SAMPLING_400 = 0, //!< SFC to insert UV channels 1929 SFC_INPUT_CHROMA_SUB_SAMPLING_420 = 1, //!< No additional details 1930 SFC_INPUT_CHROMA_SUB_SAMPLING_422HORIZONATAL = 2, //!< VD: 2:1:1 1931 SFC_INPUT_CHROMA_SUB_SAMPLING_444PROGRESSIVEINTERLEAVED = 4, //!< No additional details 1932 SFC_INPUT_CHROMA_SUB_SAMPLING_411 = 5, //!< No additional details 1933 }; 1934 1935 //! \brief VDVE_INPUT_ORDERING_MODE 1936 //! \details 1937 //! VD mode: (SFC pipe mode set as "0") 1938 1939 //! VE mode: (pipe mode set as "1 and 4") 1940 //! For 1941 //! values for each mode, please refer to the table below: 1942 enum VDVE_INPUT_ORDERING_MODE 1943 { 1944 VDVE_INPUT_ORDERING_MODE_UNNAMED0 = 0, //!< AV1 64x64 NonIBC (shifted) [Shifted by 8 pixels) 1945 VDVE_INPUT_ORDERING_MODE_UNNAMED1 = 1, //!< AV1 128x128 NonIBC (shifted)[Shifted by 8 pixels) 1946 VDVE_INPUT_ORDERING_MODE_UNNAMED2 = 2, //!< AV1 64x64 IBC (unshifted) 1947 VDVE_INPUT_ORDERING_MODE_UNNAMED3 = 3, //!< AV1 128x128 IBC (unshifted) 1948 VDVE_INPUT_ORDERING_MODE_UNNAMED4 = 4, //!< 16x16 block VP8 row-scan order - no shift 1949 }; 1950 1951 //! \brief SFC_ENGINE_MODE 1952 //! \details 1953 //! If SFC Pipe Mode is HCP-to-SFC and VE-to-SFC modes .Programmer need 1954 //! to ensure SFC Engine Mode bits programmed is the same as 1955 //! HCP_PIPE_MODE_SELECT command, Multi-Engine Modebits. For VE-SFC mode, 1956 //! this field has to be programmed according to the position of the 1957 //! split 1958 //! This Field is ignored for other SFC Pipe Mode. 1959 enum SFC_ENGINE_MODE 1960 { 1961 SFC_ENGINE_MODE_SINGLESFC = 0, //!< Single SFC mode. 1962 SFC_ENGINE_MODE_LEFTMOSTSFC = 1, //!< Left Most SFC in scalability/split-frame mode. 1963 SFC_ENGINE_MODE_RIGHTMOSTSFC = 2, //!< Right Most SFC in scalability/split-frame mode. 1964 SFC_ENGINE_MODE_MIDDLESFC = 3, //!< Middle SFC in scalability/split-frame mode. 1965 }; 1966 1967 //! \brief INPUT_FRAME_DATA_FORMAT 1968 //! \details 1969 //! This field specifies the format of Input frame according the 1970 //! following table. 1971 enum INPUT_FRAME_DATA_FORMAT 1972 { 1973 INPUT_FRAME_DATA_FORMAT_PROGRESSIVE = 0, //!< Progressive - Frame has progressive data.Valid in VD+SFC, VE+SFC and HCP+SFC engine modes. 1974 INPUT_FRAME_DATA_FORMAT_INTERLEAVED = 1, //!< Interleaved - Frame has top and bottom field data interleaved.Top and Bottom field are interleaved. Valid only in VE+SFC mode. 1975 INPUT_FRAME_DATA_FORMAT_FIELDMODE = 2, //!< Field mode - Frame has interlaced data where top field and bottom field are processed a separate frame.Valid in VD+SFC, VE+SFC and HCP+SFC engine modes. 1976 }; 1977 1978 //! \brief OUTPUT_FRAME_DATA_FORMAT 1979 //! \details 1980 //! This field specifies the format of Output Frame according the 1981 //! following table. 1982 enum OUTPUT_FRAME_DATA_FORMAT 1983 { 1984 OUTPUT_FRAME_DATA_FORMAT_PROGRESSIVE = 0, //!< Progressive - Frame has progressive data. 1985 OUTPUT_FRAME_DATA_FORMAT_INTERLEAVED = 1, //!< Interleaved - Frame has top and bottom field data interleaved. 1986 OUTPUT_FRAME_DATA_FORMAT_FIELDMODE = 2, //!< Field mode - Frame has interlaced data where top field and bottom field are processed as a separate frame. 1987 }; 1988 1989 //! \brief OUTPUT_SURFACE_FORMAT_TYPE 1990 //! \details 1991 //! SFC output surface format type. 1992 enum OUTPUT_SURFACE_FORMAT_TYPE 1993 { 1994 OUTPUT_SURFACE_FORMAT_TYPE_AYUV = 0, //!< AYUV 4:4:4 (8:8:8:8 MSB-A:Y:U:V) 1995 OUTPUT_SURFACE_FORMAT_TYPE_A8B8G8R8 = 1, //!< RGBA8 4:4:4:4 (8:8:8:8 MSB-A:B:G:R) 1996 OUTPUT_SURFACE_FORMAT_TYPE_A2R10G10B10 = 2, //!< RGBA10 10:10:10:2 (2:10:10:10 MSB-A:R:G:B) 1997 OUTPUT_SURFACE_FORMAT_TYPE_R5G6B5 = 3, //!< RGB 5:6:5 (5:6:5 MSB-R:G:B) 1998 OUTPUT_SURFACE_FORMAT_TYPE_NV12 = 4, //!< Planar NV12 4:2:0 8-bit 1999 OUTPUT_SURFACE_FORMAT_TYPE_YUYV = 5, //!< Packed YUYV 4:2:2 8-bit 2000 OUTPUT_SURFACE_FORMAT_TYPE_UYVY = 6, //!< Packed UYVY 4:2:2 8-bit 2001 OUTPUT_SURFACE_FORMAT_TYPE_INTEGRAL_32 = 7, //!< Packed RGB24 format 2002 OUTPUT_SURFACE_FORMAT_TYPE_INTEGRAL_64 = 8, //!< Packed integral Image 64-bit 2003 OUTPUT_SURFACE_FORMAT_TYPE_P016 = 9, //!< P016 format 2004 OUTPUT_SURFACE_FORMAT_TYPE_Y216 = 10, //!< Y210 / Y216 FormatBitDepth = 0 => Y210BitDepth = 1 => Y216 2005 OUTPUT_SURFACE_FORMAT_TYPE_Y416 = 11, //!< Y410 / Y416 FormatBitDepth = 0 => Y410BitDepth = 1 => Y416 2006 OUTPUT_SURFACE_FORMAT_TYPE_A8B8G8R83 = 13, //!< Y8_NORM 2007 OUTPUT_SURFACE_FORMAT_TYPE_A8B8G8R84 = 14, //!< Y16_NORM 2008 OUTPUT_SURFACE_FORMAT_TYPE_A8B8G8R85 = 15, //!< R16G16B16A16 2009 }; 2010 2011 //! \brief OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION 2012 //! \details 2013 //! This field specifies the fractional position of the bilinear filter for 2014 //! chroma downsampling. In the Y-axis. 2015 enum OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION 2016 { 2017 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_08_LEFTFULLPIXEL = 0, //!< 0 (fraction_in_integer) 2018 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_18 = 1, //!< 1 (fraction_in_integer) 2019 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_14_28 = 2, //!< 2 (fraction_in_integer) 2020 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_38 = 3, //!< 3 (fraction_in_integer) 2021 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_12_48 = 4, //!< 4 (fraction_in_integer) 2022 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_58 = 5, //!< 5 (fraction_in_integer) 2023 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_34_68 = 6, //!< 6 (fraction_in_integer) 2024 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_78 = 7, //!< 7 (fraction_in_integer) 2025 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_88 = 8, //!< No additional details 2026 }; 2027 2028 //! \brief OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION 2029 //! \details 2030 //! This field specifies the fractional position of the bilinear filter for 2031 //! chroma downsampling. In the X-axis. 2032 enum OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION 2033 { 2034 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_08_LEFTFULLPIXEL = 0, //!< 0 (fraction_in_integer) 2035 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_18 = 1, //!< 1 (fraction_in_integer) 2036 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_14_28 = 2, //!< 2 (fraction_in_integer) 2037 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_38 = 3, //!< 3 (fraction_in_integer) 2038 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_12_48 = 4, //!< 4 (fraction_in_integer) 2039 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_58 = 5, //!< 5 (fraction_in_integer) 2040 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_34_68 = 6, //!< 6 (fraction_in_integer) 2041 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_78 = 7, //!< 7 (fraction_in_integer) 2042 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_88 = 8, //!< No additional details 2043 }; 2044 2045 //! \brief INPUT_COLOR_SPACE_0_YUV1_RGB 2046 //! \details 2047 //! THis specifies the color space of the input format. RGB is valid only 2048 //! with the VE-SFC mode. 2049 enum INPUT_COLOR_SPACE_0_YUV1_RGB 2050 { 2051 INPUT_COLOR_SPACE_0_YUV1_RGB_YUVCOLORSPACE = 0, //!< No additional details 2052 INPUT_COLOR_SPACE_0_YUV1_RGB_RGBCOLORSPACE = 1, //!< No additional details 2053 }; 2054 2055 //! \brief OUTPUT_COMPRESSION_FORMAT 2056 //! \details 2057 //! Specifies the 5-bit compression format 2058 enum OUTPUT_COMPRESSION_FORMAT 2059 { 2060 OUTPUT_COMPRESSION_FORMAT_CMFR8 = 0, //!< Single 8bit channel format 2061 OUTPUT_COMPRESSION_FORMAT_CMFR8G8 = 1, //!< Two 8bit channel format 2062 OUTPUT_COMPRESSION_FORMAT_CMFR8G8B8A8 = 2, //!< Four 8bit channel format 2063 OUTPUT_COMPRESSION_FORMAT_CMFR10G10B10A2 = 3, //!< Three 10bit channels and One 2bit channel 2064 OUTPUT_COMPRESSION_FORMAT_CMFR11G11B10 = 4, //!< Two 11bit channels and One 10bit channel 2065 OUTPUT_COMPRESSION_FORMAT_CMFR16 = 5, //!< Single 16bit channel format 2066 OUTPUT_COMPRESSION_FORMAT_CMFR16G16 = 6, //!< Two 16bit channel format 2067 OUTPUT_COMPRESSION_FORMAT_CMFR16G16B16A16 = 7, //!< Four 16bit channels 2068 OUTPUT_COMPRESSION_FORMAT_CMFR32 = 8, //!< Single 32bit channel 2069 OUTPUT_COMPRESSION_FORMAT_CMFR32G32 = 9, //!< Two 32bit channels 2070 OUTPUT_COMPRESSION_FORMAT_CMFR32G32B32A32 = 10, //!< Four 32bit channels 2071 OUTPUT_COMPRESSION_FORMAT_CMFY16U16Y16V16 = 11, //!< Packed YUV 16/12/10 bit per channel 2072 OUTPUT_COMPRESSION_FORMAT_CMFML8 = 15, //!< Machine Learning format / Generic data 2073 }; 2074 2075 //! \brief IEF_ENABLE 2076 //! \details 2077 //! Restriction : For Integral Image Mode and VD Mode, this field is 2078 //! Reserved and MBZ. 2079 enum IEF_ENABLE 2080 { 2081 IEF_ENABLE_DISABLE = 0, //!< IEF Filter is Disabled 2082 IEF_ENABLE_ENABLE = 1, //!< IEF Filter is Enabled 2083 }; 2084 2085 //! \brief IEF4SMOOTH_ENABLE_ 2086 //! \details 2087 //! Restriction : For Integral Image Mode, this field is Reserved and MBZ. 2088 enum IEF4SMOOTH_ENABLE_ 2089 { 2090 IEF4SMOOTH_ENABLE_UNNAMED0 = 0, //!< IEF is operating as a content adaptive detail filter based on 5x5 region. 2091 IEF4SMOOTH_ENABLE_UNNAMED1 = 1, //!< IEF is operating as a content adaptive smooth filter based on 3x3 region 2092 }; 2093 2094 //! \brief AVS_FILTER_MODE 2095 //! \details 2096 //! In VD-to-SFC mode, value of 1 is not allowed. 2097 enum AVS_FILTER_MODE 2098 { 2099 AVS_FILTER_MODE_5X5POLY_PHASEFILTERBILINEAR_ADAPTIVE = 0, //!< No additional details 2100 AVS_FILTER_MODE_8X8POLY_PHASEFILTERBILINEAR_ADAPTIVE = 1, //!< No additional details 2101 AVS_FILTER_MODE_BILINEARFILTERONLY = 2, //!< No additional details 2102 }; 2103 2104 //! \brief ADAPTIVE_FILTER_FOR_ALL_CHANNELS 2105 //! \details 2106 //! The field can be enabled if 8-tap Adaptive filter mode is on. Else it 2107 //! should be disabled. 2108 enum ADAPTIVE_FILTER_FOR_ALL_CHANNELS 2109 { 2110 ADAPTIVE_FILTER_FOR_ALL_CHANNELS_DISABLEADAPTIVEFILTERONUVRBCHANNELS = 0, //!< No additional details 2111 ADAPTIVE_FILTER_FOR_ALL_CHANNELS_ENABLEADAPTIVEFILTERONUVRBCHANNELS = 1, //!< 8-tap Adaptive Filter Mode is on 2112 }; 2113 2114 enum AVS_SCALING_ENABLE 2115 { 2116 AVS_SCALING_ENABLE_DISABLE = 0, //!< The scaling factor is ignored and a scaling ratio of 1:1 is assumed. 2117 AVS_SCALING_ENABLE_ENABLE = 1, //!< No additional details 2118 }; 2119 2120 enum BYPASS_Y_ADAPTIVE_FILTERING 2121 { 2122 BYPASS_Y_ADAPTIVE_FILTERING_ENABLEYADAPTIVEFILTERING = 0, //!< No additional details 2123 BYPASS_Y_ADAPTIVE_FILTERING_DISABLEYADAPTIVEFILTERING = 1, //!< The Y direction will use Default Sharpness Level to blend between the smooth and sharp filters rather than the calculated value. 2124 }; 2125 2126 enum BYPASS_X_ADAPTIVE_FILTERING 2127 { 2128 BYPASS_X_ADAPTIVE_FILTERING_ENABLEXADAPTIVEFILTERING = 0, //!< No additional details 2129 BYPASS_X_ADAPTIVE_FILTERING_DISABLEXADAPTIVEFILTERING = 1, //!< The X direction will use Default Sharpness Level to blend between the smooth and sharp filters rather than the calculated value. 2130 }; 2131 2132 //! \brief MIRROR_TYPE 2133 //! \details 2134 //! 0 : Horizontal flip 1 : Vertical flip 2135 enum MIRROR_TYPE 2136 { 2137 MIRROR_TYPE_HORIZONTALFLIP = 0, //!< No additional details 2138 MIRROR_TYPE_VERTICALFLIP = 1, //!< No additional details 2139 }; 2140 2141 //! \brief MIRROR_MODE 2142 //! \details 2143 //! 0 : Mirror Mode disabled 1 : Mirror Mode enabled 2144 enum MIRROR_MODE 2145 { 2146 MIRROR_MODE_MIRRORMODEDISABLED = 0, //!< No additional details 2147 MIRROR_MODE_MIRRORMODEENABLED = 1, //!< No additional details 2148 }; 2149 2150 //! \brief ROTATION_MODE 2151 //! \details 2152 //! SFC rotation (90, 180 and 270) should be set only on VEBox input mode 2153 //! and SFC output set to TileY.Restriction: For Integral Image 2154 //! Mode, this field is Reserved and MBZ. 2155 //! For VDBox Mode, this field 2156 //! is Reserved and MBZ. 2157 //! For linear or TileX SFC output, this field 2158 //! is Reserved and MBZ. 2159 2160 enum ROTATION_MODE 2161 { 2162 ROTATION_MODE_0_DEGREES = 0, //!< No additional details 2163 ROTATION_MODE_90CLOCKWISE = 1, //!< No additional details 2164 ROTATION_MODE_180CLOCKWISE = 2, //!< No additional details 2165 ROTATION_MODE_270CLOCKWISE = 3, //!< No additional details 2166 }; 2167 2168 //! \brief BITDEPTH 2169 //! \details 2170 //! This field is valid only for output formats P016/Y216/Y416. This field 2171 //! is used to specify how many of the LSB bits have valid data. 2172 enum BITDEPTH 2173 { 2174 BITDEPTH_10BITFORMAT = 0, //!< Higher 10 bits are valid and lower 6 bits are 0 2175 }; 2176 2177 //! \brief OUTPUT_FRAME_SURFACE_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2178 //! \details 2179 //! This must be set to 0 2180 enum OUTPUT_FRAME_SURFACE_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2181 { 2182 OUTPUT_FRAME_SURFACE_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_DISABLE = 0, //!< This field must be programmed to 0 2183 }; 2184 2185 //! \brief AVS_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2186 //! \details 2187 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2188 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2189 //! vertical from horizontal compression. Please refer to vol1a? 2190 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2191 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2192 //! chapter - section style="color: rgb(35, 35, 35); 2193 //! font-family: Arial, sans-serif; font-size: 13.3333330154419px; 2194 //! line-height: normal;">?media Memory Compression for more details. 2195 enum AVS_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2196 { 2197 AVS_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< Memory compression is not supported for this surface. ?This bit just defaults to 0 2198 }; 2199 2200 //! \brief AVS_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2201 //! \details 2202 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2203 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2204 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2205 //! or to LLC. 2206 enum AVS_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2207 { 2208 AVS_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2209 }; 2210 2211 //! \brief IEF_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2212 //! \details 2213 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2214 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2215 //! vertical from horizontal compression. 2216 enum IEF_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2217 { 2218 IEF_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_UNNAMED0 = 0, //!< No additional details 2219 }; 2220 2221 //! \brief IEF_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2222 //! \details 2223 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2224 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2225 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2226 //! or to LLC. 2227 enum IEF_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2228 { 2229 IEF_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2230 }; 2231 2232 //! \brief SFD_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2233 //! \details 2234 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2235 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2236 //! vertical from horizontal compression. Please refer to vol1a 2237 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2238 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2239 //! chapter - section style="color: rgb(35, 35, 35); 2240 //! font-family: Arial, sans-serif; font-size: 13.3333330154419px; 2241 //! line-height: normal;"> media Memory Compression for more details. 2242 enum SFD_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2243 { 2244 SFD_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_UNNAMED0 = 0, //!< No additional details 2245 }; 2246 2247 //! \brief SFD_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2248 //! \details 2249 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2250 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2251 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2252 //! or to LLC. 2253 enum SFD_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2254 { 2255 SFD_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2256 SFD_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_MEDIASTORAGE = 1, //!< style="margin:0in 0in 8pt"> Data will first cache in Media Storage 2257 }; 2258 2259 //! \brief TILED_MODE 2260 //! \details 2261 //! Indicates the Tile Mode for the Surface. 2262 enum TILED_MODE 2263 { 2264 TILED_MODE_LINEAR = 0, //!< No additional details 2265 TILED_MODE_TILES_64K = 1, //!< No additional details 2266 TILED_MODE_XMAJOR = 2, //!< No additional details 2267 TILED_MODE_TILEF = 3, //!< No additional details 2268 }; 2269 2270 //! \brief AVS_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2271 //! \details 2272 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2273 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2274 //! vertical from horizontal compression. Please refer to vol1a 2275 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2276 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2277 //! chapter - section style="color: rgb(35, 35, 35); 2278 //! font-family: Arial, sans-serif; font-size: 13.3333330154419px; 2279 //! line-height: normal;"> media Memory Compression for more details. 2280 enum AVS_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2281 { 2282 AVS_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_UNNAMED0 = 0, //!< No additional details 2283 }; 2284 2285 //! \brief AVS_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2286 //! \details 2287 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2288 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2289 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2290 //! or to LLC. 2291 enum AVS_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2292 { 2293 AVS_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2294 }; 2295 2296 //! \brief IEF_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2297 //! \details 2298 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2299 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2300 //! vertical from horizontal compression. Please refer to vol1a 2301 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2302 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2303 //! chapter - section style="color: rgb(35, 35, 35); 2304 //! font-family: Arial, sans-serif; font-size: 13.3333330154419px; 2305 //! line-height: normal;"> media Memory Compression for more details. 2306 enum IEF_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2307 { 2308 IEF_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_UNNAMED0 = 0, //!< No additional details 2309 }; 2310 2311 //! \brief IEF_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2312 //! \details 2313 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2314 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2315 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2316 //! or to LLC. 2317 enum IEF_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2318 { 2319 IEF_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2320 }; 2321 2322 //! \brief SFD_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2323 //! \details 2324 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2325 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2326 //! vertical from horizontal compression. Please refer to vol1a 2327 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2328 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2329 //! chapter - section style="color: rgb(35, 35, 35); 2330 //! font-family: Arial, sans-serif; font-size: 13.3333330154419px; 2331 //! line-height: normal;"> media Memory Compression for more details. 2332 enum SFD_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2333 { 2334 SFD_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_UNNAMED0 = 0, //!< No additional details 2335 }; 2336 2337 //! \brief SFD_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2338 //! \details 2339 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2340 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2341 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2342 //! or to LLC. 2343 enum SFD_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2344 { 2345 SFD_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2346 }; 2347 2348 //! \brief HISTOGRAM_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE 2349 //! \details 2350 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2351 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes Media 2352 //! or 3D compression. style="color: rgb(35, 35, 35); 2353 //! font-family: Arial, sans-serif; font-size: 13.3333330154419px; 2354 //! line-height: normal;">Memory Data Formats chapter - section 2355 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2356 //! font-size: 13.3333330154419px; line-height: normal;"> media Memory 2357 //! Compression for more details. 2358 enum HISTOGRAM_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE 2359 { 2360 HISTOGRAM_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE_UNNAMED0 = 0, //!< No additional details 2361 }; 2362 2363 //! \brief HISTOGRAM_BASE_ADDRESS_CACHE_SELECT 2364 //! \details 2365 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2366 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2367 //! if the Histogram need to be cached in LLC or not. 2368 enum HISTOGRAM_BASE_ADDRESS_CACHE_SELECT 2369 { 2370 HISTOGRAM_BASE_ADDRESS_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2371 }; 2372 2373 //! \brief BOTTOM_FILED_SURFACE_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE 2374 //! \details 2375 //! This field is applicable only when memory compression is enabled 2376 enum BOTTOM_FILED_SURFACE_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE 2377 { 2378 BOTTOM_FILED_SURFACE_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE_MEDIACOMPRESSIONENABLED = 0, //!< No additional details 2379 BOTTOM_FILED_SURFACE_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE_RENDERCOMPRESSIONENABLED = 1, //!< No additional details 2380 }; 2381 2382 //! \brief BOTTOM_FIELD_SURFACE_TILE_WALK 2383 //! \details 2384 //! This field specifies the type of memory tiling (XMajor or YMajor) 2385 //! employed to tile this surface. See Memory Interface Functions for 2386 //! details on memory tiling and restrictions. 2387 enum BOTTOM_FIELD_SURFACE_TILE_WALK 2388 { 2389 BOTTOM_FIELD_SURFACE_TILE_WALK_TILEWALKXMAJOR = 0, //!< No additional details 2390 BOTTOM_FIELD_SURFACE_TILE_WALK_TILEWALKYMAJOR = 1, //!< No additional details 2391 }; 2392 2393 //! \brief BOTTOM_FIELD_SURFACE_TILED 2394 //! \details 2395 //! This field specifies whether the surface is tiled. 2396 enum BOTTOM_FIELD_SURFACE_TILED 2397 { 2398 BOTTOM_FIELD_SURFACE_TILED_FALSE = 0, //!< Linear 2399 BOTTOM_FIELD_SURFACE_TILED_TRUE = 1, //!< Tiled 2400 }; 2401 2402 //! \name Initializations 2403 2404 //! \brief Explicit member initialization function 2405 SFC_STATE_CMD(); 2406 2407 static const size_t dwSize = 63; 2408 static const size_t byteSize = 252; 2409 }; 2410 2411 //! 2412 //! \brief SFC_AVS_LUMA_Coeff_Table 2413 //! \details 2414 //! This command is sent from VDBOX/VEBOX to SFC pipeline at the start of 2415 //! each frame once the lock request is granted. 2416 //! 2417 struct SFC_AVS_LUMA_Coeff_Table_CMD 2418 { 2419 union 2420 { 2421 struct 2422 { 2423 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2424 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2425 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 2426 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 2427 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 2428 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2429 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2430 }; 2431 uint32_t Value; 2432 } DW0; 2433 union 2434 { 2435 struct 2436 { 2437 uint32_t Table0XFilterCoefficientN0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[[n],0] 2438 uint32_t Table0YFilterCoefficientN0 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[[n],0] 2439 uint32_t Table0XFilterCoefficientN1 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[[n],1] 2440 uint32_t Table0YFilterCoefficientN1 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[[n],1] 2441 }; 2442 uint32_t Value; 2443 } DW1; 2444 union 2445 { 2446 struct 2447 { 2448 uint32_t Table0XFilterCoefficientN2 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[[n],2] 2449 uint32_t Table0YFilterCoefficientN2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[[n],2] 2450 uint32_t Table0XFilterCoefficientN3 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[[n],3] 2451 uint32_t Table0YFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[[n],3] 2452 }; 2453 uint32_t Value; 2454 } DW2; 2455 union 2456 { 2457 struct 2458 { 2459 uint32_t Table0XFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[[n],4] 2460 uint32_t Table0YFilterCoefficientN4 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[[n],4] 2461 uint32_t Table0XFilterCoefficientN5 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[[n],5] 2462 uint32_t Table0YFilterCoefficientN5 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[[n],5] 2463 }; 2464 uint32_t Value; 2465 } DW3; 2466 union 2467 { 2468 struct 2469 { 2470 uint32_t Table0XFilterCoefficientN6 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[[n],6] 2471 uint32_t Table0YFilterCoefficientN6 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[[n],6] 2472 uint32_t Table0XFilterCoefficientN7 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[[n],7] 2473 uint32_t Table0YFilterCoefficientN7 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[[n],7] 2474 }; 2475 uint32_t Value; 2476 } DW4; 2477 uint32_t FilterCoefficients[124]; //!< Filter Coefficients 2478 2479 //! \name Local enumerations 2480 2481 enum SUBOPCODEB 2482 { 2483 SUBOPCODEB_SFCAVSLUMACOEFFTABLE = 5, //!< No additional details 2484 }; 2485 2486 enum SUBOPCODEA 2487 { 2488 SUBOPCODEA_COMMON = 0, //!< No additional details 2489 }; 2490 2491 enum MEDIA_COMMAND_OPCODE 2492 { 2493 MEDIA_COMMAND_OPCODE_MEDIAHEVCSFCMODE = 9, //!< No additional details 2494 MEDIA_COMMAND_OPCODE_MEDIAMISC = 10, //!< Media MFX/VEBOX+SFC Mode 2495 MEDIA_COMMAND_OPCODE_MEDIAAVPSFCMODE = 0xD, //!< No additional details 2496 }; 2497 2498 enum PIPELINE 2499 { 2500 PIPELINE_MEDIA = 2, //!< No additional details 2501 }; 2502 2503 enum COMMAND_TYPE 2504 { 2505 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2506 }; 2507 2508 //! \name Initializations 2509 2510 //! \brief Explicit member initialization function 2511 SFC_AVS_LUMA_Coeff_Table_CMD(); 2512 2513 static const size_t dwSize = 129; 2514 static const size_t byteSize = 516; 2515 }; 2516 2517 //! 2518 //! \brief SFC_AVS_CHROMA_Coeff_Table 2519 //! \details 2520 //! This command is sent from VDBOX/VEBOX to SFC pipeline at the start of 2521 //! each frame once the lock request is granted. 2522 //! 2523 struct SFC_AVS_CHROMA_Coeff_Table_CMD 2524 { 2525 union 2526 { 2527 struct 2528 { 2529 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2530 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2531 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 2532 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 2533 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 2534 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2535 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2536 }; 2537 uint32_t Value; 2538 } DW0; 2539 union 2540 { 2541 struct 2542 { 2543 uint32_t Table1XFilterCoefficientN2 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 1X Filter Coefficient[[n],2] 2544 uint32_t Table1YFilterCoefficientN2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 1Y Filter Coefficient[[n],2] 2545 uint32_t Table1XFilterCoefficientN3 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 1X Filter Coefficient[[n],3] 2546 uint32_t Table1YFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 1Y Filter Coefficient[[n],3] 2547 }; 2548 uint32_t Value; 2549 } DW1; 2550 union 2551 { 2552 struct 2553 { 2554 uint32_t Table1XFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 1X Filter Coefficient[[n],4] 2555 uint32_t Table1YFilterCoefficientN4 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 1Y Filter Coefficient[[n],4] 2556 uint32_t Table1XFilterCoefficientN5 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 1X Filter Coefficient[[n],5] 2557 uint32_t Table1YFilterCoefficientN5 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 1Y Filter Coefficient[[n],5] 2558 }; 2559 uint32_t Value; 2560 } DW2; 2561 uint32_t FilterCoefficients[62]; //!< Filter Coefficients 2562 2563 //! \name Local enumerations 2564 2565 enum SUBOPCODEB 2566 { 2567 SUBOPCODEB_SFCAVSCHROMACOEFFTABLE = 6, //!< No additional details 2568 }; 2569 2570 enum SUBOPCODEA 2571 { 2572 SUBOPCODEA_COMMON = 0, //!< No additional details 2573 }; 2574 2575 enum MEDIA_COMMAND_OPCODE 2576 { 2577 MEDIA_COMMAND_OPCODE_MEDIAHEVCSFCMODE = 9, //!< No additional details 2578 MEDIA_COMMAND_OPCODE_MEDIAMISC = 10, //!< Media MFX/VEBOX+SFC Mode 2579 MEDIA_COMMAND_OPCODE_MEDIAAVPSFCMODE = 0xD, //!< No additional details 2580 }; 2581 2582 enum PIPELINE 2583 { 2584 PIPELINE_MEDIA = 2, //!< No additional details 2585 }; 2586 2587 enum COMMAND_TYPE 2588 { 2589 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2590 }; 2591 2592 //! \name Initializations 2593 2594 //! \brief Explicit member initialization function 2595 SFC_AVS_CHROMA_Coeff_Table_CMD(); 2596 2597 static const size_t dwSize = 65; 2598 static const size_t byteSize = 260; 2599 }; 2600 MEDIA_CLASS_DEFINE_END(mhw__sfc__xe2_lpm_base_next__Cmd) 2601 }; 2602 } // namespace xe2_lpm_base_next 2603 } // namespace sfc 2604 } // namespace mhw 2605 #pragma pack() 2606 2607 #endif // __MHW_SFC_HWCMD_XE2_LPM_BASE_NEXT_H__ 2608