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Searched defs:SrcVec (Results 1 – 25 of 34) sorted by relevance

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/aosp_15_r20/external/swiftshader/third_party/subzero/src/
H A DIcePhiLoweringImpl.h65 auto *SrcVec = llvm::cast<VariableVecOn32>(Src); in prelowerPhis32Bit() local
H A DIceTargetLoweringMIPS32.cpp5429 auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(legalizeUndef(Src0)); in lowerRet() local
5445 auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(legalizeUndef(Src0)); in lowerRet() local
/aosp_15_r20/external/llvm/lib/IR/
H A DVerifier.cpp2318 bool SrcVec = SrcTy->isVectorTy(); in visitUIToFPInst() local
2341 bool SrcVec = SrcTy->isVectorTy(); in visitSIToFPInst() local
2364 bool SrcVec = SrcTy->isVectorTy(); in visitFPToUIInst() local
2387 bool SrcVec = SrcTy->isVectorTy(); in visitFPToSIInst() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp486 Register SrcVec = Left; in matchINS() local
504 Register DstVec, SrcVec; in applyINS() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp189 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector() local
H A DSIISelLowering.cpp3908 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in emitIndirectDst() local
7144 SDValue SrcVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, in LowerINTRINSIC_WO_CHAIN() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp205 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector() local
H A DSIISelLowering.cpp3495 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in emitIndirectDst() local
6094 SDValue SrcVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, in LowerINTRINSIC_WO_CHAIN() local
/aosp_15_r20/external/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp187 unsigned SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector() local
H A DSILowerControlFlow.cpp633 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in indirectSrc() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/IR/
H A DVerifier.cpp2662 bool SrcVec = SrcTy->isVectorTy(); in visitUIToFPInst() local
2685 bool SrcVec = SrcTy->isVectorTy(); in visitSIToFPInst() local
2708 bool SrcVec = SrcTy->isVectorTy(); in visitFPToUIInst() local
2731 bool SrcVec = SrcTy->isVectorTy(); in visitFPToSIInst() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/IR/
H A DVerifier.cpp3029 bool SrcVec = SrcTy->isVectorTy(); in visitUIToFPInst() local
3052 bool SrcVec = SrcTy->isVectorTy(); in visitSIToFPInst() local
3075 bool SrcVec = SrcTy->isVectorTy(); in visitFPToUIInst() local
3097 bool SrcVec = SrcTy->isVectorTy(); in visitFPToSIInst() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp2736 Register SrcVec = MI.getOperand(1).getReg(); in bitcastExtractVectorElt() local
2876 Register SrcVec = MI.getOperand(1).getReg(); in bitcastInsertVectorElt() local
3962 Register SrcVec = MI.getOperand(1).getReg(); in fewerElementsVectorExtractInsertVectorElt() local
6661 Register SrcVec = MI.getOperand(1).getReg(); in lowerExtractInsertVectorElt() local
6773 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; in lowerShuffleVector() local
H A DCombinerHelper.cpp3989 Register SrcVec = MI.getOperand(1).getReg(); in matchExtractVecEltBuildVec() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/
H A DInstCombineVectorOps.cpp320 Value *SrcVec = EI.getVectorOperand(); in visitExtractElementInst() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Transforms/Vectorize/
H A DVectorCombine.cpp629 Value *SrcVec; in foldInsExtFNeg() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp419 SmallVectorImpl<int> &SrcIdx) { in buildHvxVectorReg()
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp1553 GenericValue TempDst, TempSrc, SrcVec; in executeBitCastInst() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Transforms/InstCombine/
H A DInstCombineVectorOps.cpp396 Value *SrcVec = EI.getVectorOperand(); in visitExtractElementInst() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp1884 unsigned &Index) -> bool { in LowerConvertLow()
/aosp_15_r20/external/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp1501 GenericValue TempDst, TempSrc, SrcVec; in executeBitCastInst() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp1549 GenericValue TempDst, TempSrc, SrcVec; in executeBitCastInst() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp4239 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; in lowerShuffleVector() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp862 SmallVectorImpl<int> &SrcIdx) { in buildHvxVectorReg()
/aosp_15_r20/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp10351 SDValue SrcVec = Ext1.getOperand(0); in DAGCombineBuildVector() local

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