1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_INTEL_INTEGRATED_SOUTHCLUSTER 4 bool 5 help 6 Apollo Lake and Gemini Lake are single-chip platforms with a south 7 cluster instead of a PCH. Most of the IP blocks are the same as in 8 PCH platforms, but there are several differences that need to be 9 accounted for. 10 11config SOC_INTEL_COMMON_PCH_CLIENT 12 bool 13 select SOC_INTEL_COMMON_PCH_BASE 14 help 15 Selected by "Client" platforms, i.e. desktops, workstations, 16 laptops, tablets... This also includes uniprocessor servers 17 based on the same silicon as desktops and workstations. The 18 "Client" platforms include additional IP blocks that are of 19 little to no use on servers. 20 21config SOC_INTEL_COMMON_PCH_SERVER 22 bool 23 select SOC_INTEL_COMMON_PCH_BASE 24 help 25 Selected by "Server" platforms, i.e. multi-socket capable 26 platforms used in large servers and workstations, such as 27 those using the Lewisburg (C620) PCH. 28 29config SOC_INTEL_COMMON_PCH_BASE 30 bool 31 depends on SOC_INTEL_COMMON_BLOCK 32 help 33 This option is meant to be selected by the specific options above. 34 35if SOC_INTEL_COMMON_PCH_BASE 36 37source "src/soc/intel/common/pch/*/Kconfig" 38 39config PCH_SPECIFIC_BASE_OPTIONS 40 def_bool y 41 select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG 42 select SOC_INTEL_COMMON_BLOCK_CSE 43 select SOC_INTEL_COMMON_BLOCK_FAST_SPI 44 select SOC_INTEL_COMMON_BLOCK_GPIO 45 select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG 46 select SOC_INTEL_COMMON_BLOCK_ITSS 47 select SOC_INTEL_COMMON_BLOCK_LPC 48 select SOC_INTEL_COMMON_BLOCK_P2SB 49 select SOC_INTEL_COMMON_BLOCK_PCR 50 select SOC_INTEL_COMMON_BLOCK_PMC 51 select SOC_INTEL_COMMON_BLOCK_RTC 52 select SOC_INTEL_COMMON_BLOCK_SMBUS 53 select SOC_INTEL_COMMON_BLOCK_SPI 54 select SOC_INTEL_COMMON_BLOCK_TCO 55 select SOC_INTEL_COMMON_BLOCK_TIMER 56 select SOC_INTEL_COMMON_BLOCK_XHCI 57 select SOC_INTEL_COMMON_PCH_LOCKDOWN 58 select SOUTHBRIDGE_INTEL_COMMON_SMBUS 59 60config PCH_SPECIFIC_DISCRETE_OPTIONS 61 def_bool !SOC_INTEL_INTEGRATED_SOUTHCLUSTER 62 select SOC_INTEL_COMMON_BLOCK_GPMR 63 select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR 64 select SOC_INTEL_COMMON_BLOCK_SATA 65 select SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS 66 67config PCH_SPECIFIC_CLIENT_OPTIONS 68 def_bool SOC_INTEL_COMMON_PCH_CLIENT 69 select SOC_INTEL_COMMON_BLOCK_DSP 70 select SOC_INTEL_COMMON_BLOCK_GRAPHICS 71 select SOC_INTEL_COMMON_BLOCK_I2C 72 select SOC_INTEL_COMMON_BLOCK_LPSS 73 select SOC_INTEL_COMMON_BLOCK_PCIE 74 select SOC_INTEL_COMMON_BLOCK_UART 75 select SOC_INTEL_COMMON_BLOCK_XDCI 76 77endif # SOC_INTEL_COMMON_PCH_BASE 78 79config SOC_INTEL_COMMON_IBL_BASE 80 bool 81 depends on SOC_INTEL_COMMON_BLOCK 82 depends on !SOC_INTEL_COMMON_PCH_BASE 83 help 84 Common code blocks for integrated boot logic known as IBL. IBL is still 85 compatible with PCH interfaces, but with limited features/registers 86 exposed and certain revises. 87 88if SOC_INTEL_COMMON_IBL_BASE 89 90source "src/soc/intel/common/pch/*/Kconfig" 91 92config IBL_SPECIFIC_BASE_OPTIONS 93 def_bool y 94 select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG 95 select SOC_INTEL_COMMON_BLOCK_FAST_SPI 96 select SOC_INTEL_COMMON_BLOCK_GPIO 97 select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG 98 select SOC_INTEL_COMMON_BLOCK_ITSS 99 select SOC_INTEL_COMMON_BLOCK_LPC 100 select SOC_INTEL_COMMON_BLOCK_P2SB 101 select SOC_INTEL_COMMON_BLOCK_PCR 102 select SOC_INTEL_COMMON_BLOCK_PMC 103 select SOC_INTEL_COMMON_BLOCK_RTC 104 select SOC_INTEL_COMMON_BLOCK_SMBUS 105 select SOC_INTEL_COMMON_BLOCK_SPI 106 select SOC_INTEL_COMMON_BLOCK_TIMER 107 select SOC_INTEL_COMMON_PCH_LOCKDOWN 108 select SOUTHBRIDGE_INTEL_COMMON_SMBUS 109 110endif # SOC_INTEL_COMMON_IBL_BASE 111