1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Controller independent definitions 4 */ 5 #ifndef __COMMONLIB_SD_MMC_CTRLR_H__ 6 #define __COMMONLIB_SD_MMC_CTRLR_H__ 7 8 #include <stdint.h> 9 10 /* Error values returned by the storage drivers */ 11 #define CARD_UNUSABLE_ERR -17 /* Unusable Card */ 12 #define CARD_COMM_ERR -18 /* Communications Error */ 13 #define CARD_TIMEOUT -19 14 #define CARD_IN_PROGRESS -20 /* operation is in progress */ 15 16 /* MMC status in CBMEM_ID_MMC_STATUS */ 17 enum { 18 MMC_STATUS_NEED_RESET = 0, 19 MMC_STATUS_CMD1_READY_OR_IN_PROGRESS, 20 MMC_STATUS_CMD1_READY, /* Byte mode */ 21 MMC_STATUS_CMD1_IN_PROGRESS, 22 MMC_STATUS_CMD1_READY_HCS, /* Sector mode (High capacity support) */ 23 }; 24 25 struct mmc_command { 26 uint16_t cmdidx; 27 28 /* Common commands */ 29 #define MMC_CMD_GO_IDLE_STATE 0 30 #define MMC_CMD_SEND_OP_COND 1 31 #define MMC_CMD_ALL_SEND_CID 2 32 #define MMC_CMD_SET_DSR 4 33 #define MMC_CMD_SELECT_CARD 7 34 #define MMC_CMD_SEND_CSD 9 35 #define MMC_CMD_SEND_CID 10 36 #define MMC_CMD_STOP_TRANSMISSION 12 37 #define MMC_CMD_SEND_STATUS 13 38 #define MMC_CMD_SET_BLOCKLEN 16 39 #define MMC_CMD_READ_SINGLE_BLOCK 17 40 #define MMC_CMD_READ_MULTIPLE_BLOCK 18 41 #define MMC_CMD_WRITE_SINGLE_BLOCK 24 42 #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 43 #define MMC_CMD_APP_CMD 55 44 45 /* MMC specific commands */ 46 #define MMC_CMD_SET_RELATIVE_ADDR 3 47 #define MMC_CMD_SWITCH 6 48 #define MMC_CMD_SEND_EXT_CSD 8 49 #define MMC_CMD_AUTO_TUNING_SEQUENCE 21 50 #define MMC_CMD_ERASE_GROUP_START 35 51 #define MMC_CMD_ERASE_GROUP_END 36 52 #define MMC_CMD_ERASE 38 53 #define MMC_CMD_SPI_READ_OCR 58 54 #define MMC_CMD_SPI_CRC_ON_OFF 59 55 56 /* SD specific commands */ 57 #define SD_CMD_SEND_RELATIVE_ADDR 3 58 #define SD_CMD_SWITCH_FUNC 6 59 #define SD_CMD_SEND_IF_COND 8 60 #define SD_CMD_ERASE_WR_BLK_START 32 61 #define SD_CMD_ERASE_WR_BLK_END 33 62 63 /* SD specific APP commands */ 64 #define SD_CMD_APP_SET_BUS_WIDTH 6 65 #define SD_CMD_APP_SEND_OP_COND 41 66 #define SD_CMD_APP_SEND_SCR 51 67 68 uint32_t resp_type; 69 70 #define CARD_RSP_PRESENT (1 << 0) 71 #define CARD_RSP_136 (1 << 1) /* 136 bit response */ 72 #define CARD_RSP_CRC (1 << 2) /* expect valid crc */ 73 #define CARD_RSP_BUSY (1 << 3) /* card may send busy */ 74 #define CARD_RSP_OPCODE (1 << 4) /* response contains opcode */ 75 76 #define CARD_RSP_NONE (0) 77 #define CARD_RSP_R1 (CARD_RSP_PRESENT|CARD_RSP_CRC|CARD_RSP_OPCODE) 78 #define CARD_RSP_R1b (CARD_RSP_PRESENT|CARD_RSP_CRC|CARD_RSP_OPCODE| \ 79 CARD_RSP_BUSY) 80 #define CARD_RSP_R2 (CARD_RSP_PRESENT|CARD_RSP_136|CARD_RSP_CRC) 81 #define CARD_RSP_R3 (CARD_RSP_PRESENT) 82 #define CARD_RSP_R4 (CARD_RSP_PRESENT) 83 #define CARD_RSP_R5 (CARD_RSP_PRESENT|CARD_RSP_CRC|CARD_RSP_OPCODE) 84 #define CARD_RSP_R6 (CARD_RSP_PRESENT|CARD_RSP_CRC|CARD_RSP_OPCODE) 85 #define CARD_RSP_R7 (CARD_RSP_PRESENT|CARD_RSP_CRC|CARD_RSP_OPCODE) 86 87 uint32_t cmdarg; 88 89 #define MMC_TRIM_ARG 0x1 90 #define MMC_SECURE_ERASE_ARG 0x80000000 91 92 uint32_t response[4]; 93 uint32_t flags; 94 95 #define CMD_FLAG_IGNORE_INHIBIT 1 96 }; 97 98 #define SD_SWITCH_CHECK 0 99 #define SD_SWITCH_SWITCH 1 100 101 #define SD_DATA_4BIT 0x00040000 102 103 /* SCR definitions in different words */ 104 #define SD_HIGHSPEED_BUSY 0x00020000 105 #define SD_HIGHSPEED_SUPPORTED 0x00020000 106 107 struct mmc_data { 108 union { 109 char *dest; 110 const char *src; 111 }; 112 uint32_t flags; 113 114 #define DATA_FLAG_READ 1 115 #define DATA_FLAG_WRITE 2 116 117 uint32_t blocks; 118 uint32_t blocksize; 119 }; 120 121 struct sd_mmc_ctrlr { 122 int (*send_cmd)(struct sd_mmc_ctrlr *ctrlr, 123 struct mmc_command *cmd, struct mmc_data *data); 124 void (*set_ios)(struct sd_mmc_ctrlr *ctrlr); 125 void (*tuning_start)(struct sd_mmc_ctrlr *ctrlr, int retune); 126 int (*is_tuning_complete)(struct sd_mmc_ctrlr *ctrlr, int *successful); 127 128 int initialized; 129 unsigned int version; 130 uint32_t voltages; 131 132 #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ 133 #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ 134 #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ 135 #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ 136 #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ 137 #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ 138 #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ 139 #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ 140 #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ 141 #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ 142 #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ 143 #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ 144 #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ 145 #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ 146 #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ 147 #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ 148 #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ 149 150 #define MMC_VDD_165_195_SHIFT 7 151 152 uint32_t clock_base; /* Controller's base clock */ 153 uint32_t f_min; 154 uint32_t f_max; 155 uint32_t request_hz; /* Desired clock frequency */ 156 uint32_t bus_hz; /* Actual bus clock frequency */ 157 158 #define CLOCK_KHZ 1000 159 #define CLOCK_MHZ (1000 * CLOCK_KHZ) 160 #define CLOCK_20MHZ (20 * CLOCK_MHZ) 161 #define CLOCK_25MHZ (25 * CLOCK_MHZ) 162 #define CLOCK_26MHZ (26 * CLOCK_MHZ) 163 #define CLOCK_50MHZ (50 * CLOCK_MHZ) 164 #define CLOCK_52MHZ (52 * CLOCK_MHZ) 165 #define CLOCK_200MHZ (200 * CLOCK_MHZ) 166 167 uint32_t bus_width; 168 uint32_t caps; 169 170 /* Generic controller & driver capabilities. Controller specific capabilities 171 * start at 0x00010000 172 */ 173 #define DRVR_CAP_4BIT 0x00000001 174 #define DRVR_CAP_8BIT 0x00000002 175 #define DRVR_CAP_AUTO_CMD12 0x00000004 176 #define DRVR_CAP_HC 0x00000008 177 #define DRVR_CAP_HS 0x00000010 178 #define DRVR_CAP_HS52 0x00000020 179 #define DRVR_CAP_HS200 0x00000040 180 #define DRVR_CAP_HS400 0x00000080 181 #define DRVR_CAP_ENHANCED_STROBE 0x00000100 182 #define DRVR_CAP_REMOVABLE 0x00000200 183 #define DRVR_CAP_DMA_64BIT 0x00000400 184 #define DRVR_CAP_HS200_TUNING 0x00000800 185 186 uint32_t b_max; 187 uint32_t timing; 188 189 #define BUS_TIMING_LEGACY 0 190 #define BUS_TIMING_MMC_HS 1 191 #define BUS_TIMING_SD_HS 2 192 #define BUS_TIMING_UHS_SDR12 3 193 #define BUS_TIMING_UHS_SDR25 4 194 #define BUS_TIMING_UHS_SDR50 5 195 #define BUS_TIMING_UHS_SDR104 6 196 #define BUS_TIMING_UHS_DDR50 7 197 #define BUS_TIMING_MMC_DDR52 8 198 #define BUS_TIMING_MMC_HS200 9 199 #define BUS_TIMING_MMC_HS400 10 200 #define BUS_TIMING_MMC_HS400ES 11 201 202 uint32_t mdelay_before_cmd0; 203 uint32_t mdelay_after_cmd0; 204 uint32_t udelay_wait_after_cmd; 205 }; 206 207 /* SOC specific routine to override ctrlr->caps and .voltages 208 * 209 * Set/clear the necessary DRVR_CAP_xxx bits in ctrlr->caps to specify the 210 * controllers capabilities and driver workarounds. 211 * 212 * Set/clear the necessary MMC_VDD_xxx bits in ctrlr->voltages to specify the 213 * controllers power support. 214 */ 215 void soc_sd_mmc_controller_quirks(struct sd_mmc_ctrlr *ctrlr); 216 217 /* Optional routines to support logging */ 218 void sdhc_log_command(struct mmc_command *cmd); 219 void sdhc_log_command_issued(void); 220 void sdhc_log_response(uint32_t entries, uint32_t *response); 221 void sdhc_log_ret(int ret); 222 223 #endif /* __COMMONLIB_SD_MMC_CTRLR_H__ */ 224