1 //===----- HexagonMCChecker.cpp - Instruction bundle checking -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the checking of insns inside a bundle according to the
10 // packet constraint rules of the Hexagon ISA.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MCTargetDesc/HexagonMCChecker.h"
15 #include "MCTargetDesc/HexagonBaseInfo.h"
16 #include "MCTargetDesc/HexagonMCInstrInfo.h"
17 #include "MCTargetDesc/HexagonMCShuffler.h"
18 #include "MCTargetDesc/HexagonMCTargetDesc.h"
19 
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrDesc.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/SourceMgr.h"
28 #include <cassert>
29 
30 using namespace llvm;
31 
32 static cl::opt<bool>
33     RelaxNVChecks("relax-nv-checks", cl::Hidden,
34                   cl::desc("Relax checks of new-value validity"));
35 
36 const HexagonMCChecker::PredSense
37     HexagonMCChecker::Unconditional(Hexagon::NoRegister, false);
38 
init()39 void HexagonMCChecker::init() {
40   // Initialize read-only registers set.
41   ReadOnly.insert(Hexagon::PC);
42   ReadOnly.insert(Hexagon::C9_8);
43 
44   // Figure out the loop-registers definitions.
45   if (HexagonMCInstrInfo::isInnerLoop(MCB)) {
46     Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0?
47     Defs[Hexagon::LC0].insert(Unconditional);
48   }
49   if (HexagonMCInstrInfo::isOuterLoop(MCB)) {
50     Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0?
51     Defs[Hexagon::LC1].insert(Unconditional);
52   }
53 
54   if (HexagonMCInstrInfo::isBundle(MCB))
55     // Unfurl a bundle.
56     for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCB)) {
57       MCInst const &Inst = *I.getInst();
58       if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) {
59         init(*Inst.getOperand(0).getInst());
60         init(*Inst.getOperand(1).getInst());
61       } else
62         init(Inst);
63     }
64   else
65     init(MCB);
66 }
67 
initReg(MCInst const & MCI,unsigned R,unsigned & PredReg,bool & isTrue)68 void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg,
69                                bool &isTrue) {
70   if (HexagonMCInstrInfo::isPredicated(MCII, MCI) &&
71       HexagonMCInstrInfo::isPredReg(RI, R)) {
72     // Note an used predicate register.
73     PredReg = R;
74     isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI);
75 
76     // Note use of new predicate register.
77     if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
78       NewPreds.insert(PredReg);
79   } else
80     // Note register use.  Super-registers are not tracked directly,
81     // but their components.
82     for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());
83          SRI.isValid(); ++SRI)
84       if (!MCSubRegIterator(*SRI, &RI).isValid())
85         // Skip super-registers used indirectly.
86         Uses.insert(*SRI);
87 
88   if (HexagonMCInstrInfo::IsReverseVecRegPair(R))
89     ReversePairs.insert(R);
90 }
91 
init(MCInst const & MCI)92 void HexagonMCChecker::init(MCInst const &MCI) {
93   const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI);
94   unsigned PredReg = Hexagon::NoRegister;
95   bool isTrue = false;
96 
97   // Get used registers.
98   for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
99     if (MCI.getOperand(i).isReg())
100       initReg(MCI, MCI.getOperand(i).getReg(), PredReg, isTrue);
101   for (MCPhysReg ImpUse : MCID.implicit_uses())
102     initReg(MCI, ImpUse, PredReg, isTrue);
103 
104   const bool IgnoreTmpDst = (HexagonMCInstrInfo::hasTmpDst(MCII, MCI) ||
105                              HexagonMCInstrInfo::hasHvxTmp(MCII, MCI)) &&
106                             STI.getFeatureBits()[Hexagon::ArchV69];
107 
108   // Get implicit register definitions.
109   for (MCPhysReg R : MCID.implicit_defs()) {
110     if (Hexagon::R31 != R && MCID.isCall())
111       // Any register other than the LR and the PC are actually volatile ones
112       // as defined by the ABI, not modified implicitly by the call insn.
113       continue;
114     if (Hexagon::PC == R)
115       // Branches are the only insns that can change the PC,
116       // otherwise a read-only register.
117       continue;
118 
119     if (Hexagon::USR_OVF == R)
120       // Many insns change the USR implicitly, but only one or another flag.
121       // The instruction table models the USR.OVF flag, which can be
122       // implicitly modified more than once, but cannot be modified in the
123       // same packet with an instruction that modifies is explicitly. Deal
124       // with such situations individually.
125       SoftDefs.insert(R);
126     else if (HexagonMCInstrInfo::isPredReg(RI, R) &&
127              HexagonMCInstrInfo::isPredicateLate(MCII, MCI))
128       // Include implicit late predicates.
129       LatePreds.insert(R);
130     else if (!IgnoreTmpDst)
131       Defs[R].insert(PredSense(PredReg, isTrue));
132   }
133 
134   // Figure out explicit register definitions.
135   for (unsigned i = 0; i < MCID.getNumDefs(); ++i) {
136     unsigned R = MCI.getOperand(i).getReg(), S = Hexagon::NoRegister;
137     // USR has subregisters (while C8 does not for technical reasons), so
138     // reset R to USR, since we know how to handle multiple defs of USR,
139     // taking into account its subregisters.
140     if (R == Hexagon::C8)
141       R = Hexagon::USR;
142 
143     if (HexagonMCInstrInfo::IsReverseVecRegPair(R))
144       ReversePairs.insert(R);
145 
146     // Note register definitions, direct ones as well as indirect side-effects.
147     // Super-registers are not tracked directly, but their components.
148     for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());
149          SRI.isValid(); ++SRI) {
150       if (MCSubRegIterator(*SRI, &RI).isValid())
151         // Skip super-registers defined indirectly.
152         continue;
153 
154       if (R == *SRI) {
155         if (S == R)
156           // Avoid scoring the defined register multiple times.
157           continue;
158         else
159           // Note that the defined register has already been scored.
160           S = R;
161       }
162 
163       if (Hexagon::P3_0 != R && Hexagon::P3_0 == *SRI)
164         // P3:0 is a special case, since multiple predicate register definitions
165         // in a packet is allowed as the equivalent of their logical "and".
166         // Only an explicit definition of P3:0 is noted as such; if a
167         // side-effect, then note as a soft definition.
168         SoftDefs.insert(*SRI);
169       else if (HexagonMCInstrInfo::isPredicateLate(MCII, MCI) &&
170                HexagonMCInstrInfo::isPredReg(RI, *SRI))
171         // Some insns produce predicates too late to be used in the same packet.
172         LatePreds.insert(*SRI);
173       else if (i == 0 && HexagonMCInstrInfo::getType(MCII, MCI) ==
174                              HexagonII::TypeCVI_VM_TMP_LD)
175         // Temporary loads should be used in the same packet, but don't commit
176         // results, so it should be disregarded if another insn changes the same
177         // register.
178         // TODO: relies on the impossibility of a current and a temporary loads
179         // in the same packet.
180         TmpDefs.insert(*SRI);
181       else if (i <= 1 && HexagonMCInstrInfo::hasNewValue2(MCII, MCI))
182         // vshuff(Vx, Vy, Rx) <- Vx(0) and Vy(1) are both source and
183         // destination registers with this instruction. same for vdeal(Vx,Vy,Rx)
184         Uses.insert(*SRI);
185       else if (!IgnoreTmpDst)
186         Defs[*SRI].insert(PredSense(PredReg, isTrue));
187     }
188   }
189 
190   // Figure out definitions of new predicate registers.
191   if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI))
192     for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i)
193       if (MCI.getOperand(i).isReg()) {
194         unsigned P = MCI.getOperand(i).getReg();
195 
196         if (HexagonMCInstrInfo::isPredReg(RI, P))
197           NewPreds.insert(P);
198       }
199 }
200 
HexagonMCChecker(MCContext & Context,MCInstrInfo const & MCII,MCSubtargetInfo const & STI,MCInst & mcb,MCRegisterInfo const & ri,bool ReportErrors)201 HexagonMCChecker::HexagonMCChecker(MCContext &Context, MCInstrInfo const &MCII,
202                                    MCSubtargetInfo const &STI, MCInst &mcb,
203                                    MCRegisterInfo const &ri, bool ReportErrors)
204     : Context(Context), MCB(mcb), RI(ri), MCII(MCII), STI(STI),
205       ReportErrors(ReportErrors) {
206   init();
207 }
208 
HexagonMCChecker(HexagonMCChecker const & Other,MCSubtargetInfo const & STI,bool CopyReportErrors)209 HexagonMCChecker::HexagonMCChecker(HexagonMCChecker const &Other,
210                                    MCSubtargetInfo const &STI,
211                                    bool CopyReportErrors)
212     : Context(Other.Context), MCB(Other.MCB), RI(Other.RI), MCII(Other.MCII),
213       STI(STI), ReportErrors(CopyReportErrors ? Other.ReportErrors : false) {
214   init();
215 }
216 
check(bool FullCheck)217 bool HexagonMCChecker::check(bool FullCheck) {
218   bool chkP = checkPredicates();
219   bool chkNV = checkNewValues();
220   bool chkR = checkRegisters();
221   bool chkRRO = checkRegistersReadOnly();
222   checkRegisterCurDefs();
223   bool chkS = checkSolo();
224   bool chkSh = true;
225   if (FullCheck)
226     chkSh = checkShuffle();
227   bool chkSl = true;
228   if (FullCheck)
229     chkSl = checkSlots();
230   bool chkAXOK = checkAXOK();
231   bool chkCofMax1 = checkCOFMax1();
232   bool chkHWLoop = checkHWLoop();
233   bool chkValidTmpDst = FullCheck ? checkValidTmpDst() : true;
234   bool chkLegalVecRegPair = checkLegalVecRegPair();
235   bool ChkHVXAccum = checkHVXAccum();
236   bool chk = chkP && chkNV && chkR && chkRRO && chkS && chkSh && chkSl &&
237              chkAXOK && chkCofMax1 && chkHWLoop && chkValidTmpDst &&
238              chkLegalVecRegPair && ChkHVXAccum;
239 
240   return chk;
241 }
242 
isDuplexAGroup(unsigned Opcode)243 static bool isDuplexAGroup(unsigned Opcode) {
244   switch (Opcode) {
245   case Hexagon::SA1_addi:
246   case Hexagon::SA1_addrx:
247   case Hexagon::SA1_addsp:
248   case Hexagon::SA1_and1:
249   case Hexagon::SA1_clrf:
250   case Hexagon::SA1_clrfnew:
251   case Hexagon::SA1_clrt:
252   case Hexagon::SA1_clrtnew:
253   case Hexagon::SA1_cmpeqi:
254   case Hexagon::SA1_combine0i:
255   case Hexagon::SA1_combine1i:
256   case Hexagon::SA1_combine2i:
257   case Hexagon::SA1_combine3i:
258   case Hexagon::SA1_combinerz:
259   case Hexagon::SA1_combinezr:
260   case Hexagon::SA1_dec:
261   case Hexagon::SA1_inc:
262   case Hexagon::SA1_seti:
263   case Hexagon::SA1_setin1:
264   case Hexagon::SA1_sxtb:
265   case Hexagon::SA1_sxth:
266   case Hexagon::SA1_tfr:
267   case Hexagon::SA1_zxtb:
268   case Hexagon::SA1_zxth:
269     return true;
270     break;
271   default:
272     return false;
273   }
274 }
275 
isNeitherAnorX(MCInstrInfo const & MCII,MCInst const & ID)276 static bool isNeitherAnorX(MCInstrInfo const &MCII, MCInst const &ID) {
277   if (HexagonMCInstrInfo::isFloat(MCII, ID))
278     return true;
279   unsigned Type = HexagonMCInstrInfo::getType(MCII, ID);
280   switch (Type) {
281   case HexagonII::TypeALU32_2op:
282   case HexagonII::TypeALU32_3op:
283   case HexagonII::TypeALU32_ADDI:
284   case HexagonII::TypeS_2op:
285   case HexagonII::TypeS_3op:
286   case HexagonII::TypeEXTENDER:
287   case HexagonII::TypeM:
288   case HexagonII::TypeALU64:
289     return false;
290   case HexagonII::TypeSUBINSN: {
291     return !isDuplexAGroup(ID.getOpcode());
292   }
293   case HexagonII::TypeDUPLEX:
294     llvm_unreachable("unexpected duplex instruction");
295   default:
296     return true;
297   }
298 }
299 
checkAXOK()300 bool HexagonMCChecker::checkAXOK() {
301   MCInst const *HasSoloAXInst = nullptr;
302   for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
303     if (HexagonMCInstrInfo::isSoloAX(MCII, I)) {
304       HasSoloAXInst = &I;
305     }
306   }
307   if (!HasSoloAXInst)
308     return true;
309   for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
310     if (&I != HasSoloAXInst && isNeitherAnorX(MCII, I)) {
311       reportError(
312           HasSoloAXInst->getLoc(),
313           Twine("Instruction can only be in a packet with ALU or non-FPU XTYPE "
314                 "instructions"));
315       reportError(I.getLoc(),
316                   Twine("Not an ALU or non-FPU XTYPE instruction"));
317       return false;
318     }
319   }
320   return true;
321 }
322 
reportBranchErrors()323 void HexagonMCChecker::reportBranchErrors() {
324   for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
325     if (HexagonMCInstrInfo::IsABranchingInst(MCII, STI, I))
326       reportNote(I.getLoc(), "Branching instruction");
327   }
328 }
329 
checkHWLoop()330 bool HexagonMCChecker::checkHWLoop() {
331   if (!HexagonMCInstrInfo::isInnerLoop(MCB) &&
332       !HexagonMCInstrInfo::isOuterLoop(MCB))
333     return true;
334   for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
335     if (HexagonMCInstrInfo::IsABranchingInst(MCII, STI, I)) {
336       reportError(MCB.getLoc(),
337                   "Branches cannot be in a packet with hardware loops");
338       reportBranchErrors();
339       return false;
340     }
341   }
342   return true;
343 }
344 
checkCOFMax1()345 bool HexagonMCChecker::checkCOFMax1() {
346   SmallVector<MCInst const *, 2> BranchLocations;
347   for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
348     if (HexagonMCInstrInfo::IsABranchingInst(MCII, STI, I))
349       BranchLocations.push_back(&I);
350   }
351   for (unsigned J = 0, N = BranchLocations.size(); J < N; ++J) {
352     MCInst const &I = *BranchLocations[J];
353     if (HexagonMCInstrInfo::isCofMax1(MCII, I)) {
354       bool Relax1 = HexagonMCInstrInfo::isCofRelax1(MCII, I);
355       bool Relax2 = HexagonMCInstrInfo::isCofRelax2(MCII, I);
356       if (N > 1 && !Relax1 && !Relax2) {
357         reportError(I.getLoc(),
358                     "Instruction may not be in a packet with other branches");
359         reportBranchErrors();
360         return false;
361       }
362       if (N > 1 && J == 0 && !Relax1) {
363         reportError(I.getLoc(),
364                     "Instruction may not be the first branch in packet");
365         reportBranchErrors();
366         return false;
367       }
368       if (N > 1 && J == 1 && !Relax2) {
369         reportError(I.getLoc(),
370                     "Instruction may not be the second branch in packet");
371         reportBranchErrors();
372         return false;
373       }
374     }
375   }
376   return true;
377 }
378 
checkSlots()379 bool HexagonMCChecker::checkSlots() {
380   if (HexagonMCInstrInfo::slotsConsumed(MCII, STI, MCB) >
381       HexagonMCInstrInfo::packetSizeSlots(STI)) {
382     reportError("invalid instruction packet: out of slots");
383     return false;
384   }
385   return true;
386 }
387 
388 // Check legal use of predicate registers.
checkPredicates()389 bool HexagonMCChecker::checkPredicates() {
390   // Check for proper use of new predicate registers.
391   for (const auto &I : NewPreds) {
392     unsigned P = I;
393 
394     if (!Defs.count(P) || LatePreds.count(P) || Defs.count(Hexagon::P3_0)) {
395       // Error out if the new predicate register is not defined,
396       // or defined "late"
397       // (e.g., "{ if (p3.new)... ; p3 = sp1loop0(#r7:2, Rs) }").
398       reportErrorNewValue(P);
399       return false;
400     }
401   }
402 
403   // Check for proper use of auto-anded of predicate registers.
404   for (const auto &I : LatePreds) {
405     unsigned P = I;
406 
407     if (LatePreds.count(P) > 1 || Defs.count(P)) {
408       // Error out if predicate register defined "late" multiple times or
409       // defined late and regularly defined
410       // (e.g., "{ p3 = sp1loop0(...); p3 = cmp.eq(...) }".
411       reportErrorRegisters(P);
412       return false;
413     }
414   }
415 
416   return true;
417 }
418 
419 // Check legal use of new values.
checkNewValues()420 bool HexagonMCChecker::checkNewValues() {
421   for (auto const &ConsumerInst :
422        HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
423     if (!HexagonMCInstrInfo::isNewValue(MCII, ConsumerInst))
424       continue;
425 
426     const HexagonMCInstrInfo::PredicateInfo ConsumerPredInfo =
427         HexagonMCInstrInfo::predicateInfo(MCII, ConsumerInst);
428 
429     bool Branch = HexagonMCInstrInfo::getDesc(MCII, ConsumerInst).isBranch();
430     MCOperand const &Op =
431         HexagonMCInstrInfo::getNewValueOperand(MCII, ConsumerInst);
432     assert(Op.isReg());
433 
434     auto Producer = registerProducer(Op.getReg(), ConsumerPredInfo);
435     const MCInst *const ProducerInst = std::get<0>(Producer);
436     const HexagonMCInstrInfo::PredicateInfo ProducerPredInfo =
437         std::get<2>(Producer);
438 
439     if (ProducerInst == nullptr) {
440       reportError(ConsumerInst.getLoc(),
441                   "New value register consumer has no producer");
442       return false;
443     }
444     if (!RelaxNVChecks) {
445       // Checks that statically prove correct new value consumption
446       if (ProducerPredInfo.isPredicated() &&
447           (!ConsumerPredInfo.isPredicated() ||
448            llvm::HexagonMCInstrInfo::getType(MCII, ConsumerInst) ==
449                HexagonII::TypeNCJ)) {
450         reportNote(
451             ProducerInst->getLoc(),
452             "Register producer is predicated and consumer is unconditional");
453         reportError(ConsumerInst.getLoc(),
454                     "Instruction does not have a valid new register producer");
455         return false;
456       }
457       if (ProducerPredInfo.Register != Hexagon::NoRegister &&
458           ProducerPredInfo.Register != ConsumerPredInfo.Register) {
459         reportNote(ProducerInst->getLoc(),
460                    "Register producer does not use the same predicate "
461                    "register as the consumer");
462         reportError(ConsumerInst.getLoc(),
463                     "Instruction does not have a valid new register producer");
464         return false;
465       }
466     }
467     if (ProducerPredInfo.Register == ConsumerPredInfo.Register &&
468         ConsumerPredInfo.PredicatedTrue != ProducerPredInfo.PredicatedTrue) {
469       reportNote(
470           ProducerInst->getLoc(),
471           "Register producer has the opposite predicate sense as consumer");
472       reportError(ConsumerInst.getLoc(),
473                   "Instruction does not have a valid new register producer");
474       return false;
475     }
476 
477     MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, *ProducerInst);
478     const unsigned ProducerOpIndex = std::get<1>(Producer);
479 
480     if (Desc.operands()[ProducerOpIndex].RegClass ==
481         Hexagon::DoubleRegsRegClassID) {
482       reportNote(ProducerInst->getLoc(),
483                  "Double registers cannot be new-value producers");
484       reportError(ConsumerInst.getLoc(),
485                   "Instruction does not have a valid new register producer");
486       return false;
487     }
488 
489     // The ProducerOpIsMemIndex logic checks for the index of the producer
490     // register operand.  Z-reg load instructions have an implicit operand
491     // that's not encoded, so the producer won't appear as the 1-th def, it
492     // will be at the 0-th.
493     const unsigned ProducerOpSearchIndex =
494         (HexagonMCInstrInfo::getType(MCII, *ProducerInst) ==
495          HexagonII::TypeCVI_ZW)
496             ? 0
497             : 1;
498 
499     const bool ProducerOpIsMemIndex =
500         ((Desc.mayLoad() && ProducerOpIndex == ProducerOpSearchIndex) ||
501          (Desc.mayStore() && ProducerOpIndex == 0));
502 
503     if (ProducerOpIsMemIndex) {
504       unsigned Mode = HexagonMCInstrInfo::getAddrMode(MCII, *ProducerInst);
505 
506       StringRef ModeError;
507       if (Mode == HexagonII::AbsoluteSet)
508         ModeError = "Absolute-set";
509       if (Mode == HexagonII::PostInc)
510         ModeError = "Auto-increment";
511       if (!ModeError.empty()) {
512         reportNote(ProducerInst->getLoc(),
513                    ModeError + " registers cannot be a new-value "
514                                "producer");
515         reportError(ConsumerInst.getLoc(),
516                     "Instruction does not have a valid new register producer");
517         return false;
518       }
519     }
520     if (Branch && HexagonMCInstrInfo::isFloat(MCII, *ProducerInst)) {
521       reportNote(ProducerInst->getLoc(),
522                  "FPU instructions cannot be new-value producers for jumps");
523       reportError(ConsumerInst.getLoc(),
524                   "Instruction does not have a valid new register producer");
525       return false;
526     }
527   }
528   return true;
529 }
530 
checkRegistersReadOnly()531 bool HexagonMCChecker::checkRegistersReadOnly() {
532   for (auto I : HexagonMCInstrInfo::bundleInstructions(MCB)) {
533     MCInst const &Inst = *I.getInst();
534     unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs();
535     for (unsigned j = 0; j < Defs; ++j) {
536       MCOperand const &Operand = Inst.getOperand(j);
537       assert(Operand.isReg() && "Def is not a register");
538       unsigned Register = Operand.getReg();
539       if (ReadOnly.find(Register) != ReadOnly.end()) {
540         reportError(Inst.getLoc(), "Cannot write to read-only register `" +
541                                        Twine(RI.getName(Register)) + "'");
542         return false;
543       }
544     }
545   }
546   return true;
547 }
548 
registerUsed(unsigned Register)549 bool HexagonMCChecker::registerUsed(unsigned Register) {
550   for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB))
551     for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(),
552                   n = I.getNumOperands();
553          j < n; ++j) {
554       MCOperand const &Operand = I.getOperand(j);
555       if (Operand.isReg() && Operand.getReg() == Register)
556         return true;
557     }
558   return false;
559 }
560 
561 std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
registerProducer(unsigned Register,HexagonMCInstrInfo::PredicateInfo ConsumerPredicate)562 HexagonMCChecker::registerProducer(
563     unsigned Register, HexagonMCInstrInfo::PredicateInfo ConsumerPredicate) {
564   std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
565       WrongSense;
566 
567   for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
568     MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
569     auto ProducerPredicate = HexagonMCInstrInfo::predicateInfo(MCII, I);
570 
571     for (unsigned J = 0, N = Desc.getNumDefs(); J < N; ++J)
572       for (auto K = MCRegAliasIterator(I.getOperand(J).getReg(), &RI, true);
573            K.isValid(); ++K)
574         if (*K == Register) {
575           if (RelaxNVChecks ||
576               (ProducerPredicate.Register == ConsumerPredicate.Register &&
577                (ProducerPredicate.Register == Hexagon::NoRegister ||
578                 ProducerPredicate.PredicatedTrue ==
579                     ConsumerPredicate.PredicatedTrue)))
580             return std::make_tuple(&I, J, ProducerPredicate);
581           std::get<0>(WrongSense) = &I;
582           std::get<1>(WrongSense) = J;
583           std::get<2>(WrongSense) = ProducerPredicate;
584         }
585     if (Register == Hexagon::VTMP && HexagonMCInstrInfo::hasTmpDst(MCII, I))
586       return std::make_tuple(&I, 0, HexagonMCInstrInfo::PredicateInfo());
587   }
588   return WrongSense;
589 }
590 
checkRegisterCurDefs()591 void HexagonMCChecker::checkRegisterCurDefs() {
592   for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
593     if (HexagonMCInstrInfo::isCVINew(MCII, I) &&
594         HexagonMCInstrInfo::getDesc(MCII, I).mayLoad()) {
595       const unsigned RegDef = I.getOperand(0).getReg();
596 
597       bool HasRegDefUse = false;
598       for (MCRegAliasIterator Alias(RegDef, &RI, true); Alias.isValid();
599            ++Alias)
600         HasRegDefUse = HasRegDefUse || registerUsed(*Alias);
601 
602       if (!HasRegDefUse)
603         reportWarning("Register `" + Twine(RI.getName(RegDef)) +
604                       "' used with `.cur' "
605                       "but not used in the same packet");
606     }
607   }
608 }
609 
610 // Check for legal register uses and definitions.
checkRegisters()611 bool HexagonMCChecker::checkRegisters() {
612   // Check for proper register definitions.
613   for (const auto &I : Defs) {
614     unsigned R = I.first;
615 
616     if (isLoopRegister(R) && Defs.count(R) > 1 &&
617         (HexagonMCInstrInfo::isInnerLoop(MCB) ||
618          HexagonMCInstrInfo::isOuterLoop(MCB))) {
619       // Error out for definitions of loop registers at the end of a loop.
620       reportError("loop-setup and some branch instructions "
621                   "cannot be in the same packet");
622       return false;
623     }
624     if (SoftDefs.count(R)) {
625       // Error out for explicit changes to registers also weakly defined
626       // (e.g., "{ usr = r0; r0 = sfadd(...) }").
627       unsigned UsrR = Hexagon::USR; // Silence warning about mixed types in ?:.
628       unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;
629       reportErrorRegisters(BadR);
630       return false;
631     }
632     if (!HexagonMCInstrInfo::isPredReg(RI, R) && Defs[R].size() > 1) {
633       // Check for multiple register definitions.
634       PredSet &PM = Defs[R];
635 
636       // Check for multiple unconditional register definitions.
637       if (PM.count(Unconditional)) {
638         // Error out on an unconditional change when there are any other
639         // changes, conditional or not.
640         unsigned UsrR = Hexagon::USR;
641         unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;
642         reportErrorRegisters(BadR);
643         return false;
644       }
645       // Check for multiple conditional register definitions.
646       for (const auto &J : PM) {
647         PredSense P = J;
648 
649         // Check for multiple uses of the same condition.
650         if (PM.count(P) > 1) {
651           // Error out on conditional changes based on the same predicate
652           // (e.g., "{ if (!p0) r0 =...; if (!p0) r0 =... }").
653           reportErrorRegisters(R);
654           return false;
655         }
656         // Check for the use of the complementary condition.
657         P.second = !P.second;
658         if (PM.count(P) && PM.size() > 2) {
659           // Error out on conditional changes based on the same predicate
660           // multiple times
661           // (e.g., "if (p0) r0 =...; if (!p0) r0 =... }; if (!p0) r0 =...").
662           reportErrorRegisters(R);
663           return false;
664         }
665       }
666     }
667   }
668 
669   // Check for use of temporary definitions.
670   for (const auto &I : TmpDefs) {
671     unsigned R = I;
672 
673     if (!Uses.count(R)) {
674       // special case for vhist
675       bool vHistFound = false;
676       for (auto const &HMI : HexagonMCInstrInfo::bundleInstructions(MCB)) {
677         if (HexagonMCInstrInfo::getType(MCII, *HMI.getInst()) ==
678             HexagonII::TypeCVI_HIST) {
679           vHistFound = true; // vhist() implicitly uses ALL REGxx.tmp
680           break;
681         }
682       }
683       // Warn on an unused temporary definition.
684       if (!vHistFound) {
685         reportWarning("register `" + Twine(RI.getName(R)) +
686                       "' used with `.tmp' but not used in the same packet");
687         return true;
688       }
689     }
690   }
691 
692   return true;
693 }
694 
695 // Check for legal use of solo insns.
checkSolo()696 bool HexagonMCChecker::checkSolo() {
697   if (HexagonMCInstrInfo::bundleSize(MCB) > 1)
698     for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
699       if (HexagonMCInstrInfo::isSolo(MCII, I)) {
700         reportError(I.getLoc(), "Instruction is marked `isSolo' and "
701                                 "cannot have other instructions in "
702                                 "the same packet");
703         return false;
704       }
705     }
706 
707   return true;
708 }
709 
checkShuffle()710 bool HexagonMCChecker::checkShuffle() {
711   HexagonMCShuffler MCSDX(Context, ReportErrors, MCII, STI, MCB);
712   return MCSDX.check();
713 }
714 
checkValidTmpDst()715 bool HexagonMCChecker::checkValidTmpDst() {
716   if (!STI.getFeatureBits()[Hexagon::ArchV69]) {
717     return true;
718   }
719   auto HasTmp = [&](MCInst const &I) {
720     return HexagonMCInstrInfo::hasTmpDst(MCII, I) ||
721            HexagonMCInstrInfo::hasHvxTmp(MCII, I);
722   };
723   unsigned HasTmpCount =
724       llvm::count_if(HexagonMCInstrInfo::bundleInstructions(MCII, MCB), HasTmp);
725 
726   if (HasTmpCount > 1) {
727     reportError(
728         MCB.getLoc(),
729         "this packet has more than one HVX vtmp/.tmp destination instruction");
730 
731     for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB))
732       if (HasTmp(I))
733         reportNote(I.getLoc(),
734                    "this is an HVX vtmp/.tmp destination instruction");
735 
736     return false;
737   }
738   return true;
739 }
740 
compoundRegisterMap(unsigned & Register)741 void HexagonMCChecker::compoundRegisterMap(unsigned &Register) {
742   switch (Register) {
743   default:
744     break;
745   case Hexagon::R15:
746     Register = Hexagon::R23;
747     break;
748   case Hexagon::R14:
749     Register = Hexagon::R22;
750     break;
751   case Hexagon::R13:
752     Register = Hexagon::R21;
753     break;
754   case Hexagon::R12:
755     Register = Hexagon::R20;
756     break;
757   case Hexagon::R11:
758     Register = Hexagon::R19;
759     break;
760   case Hexagon::R10:
761     Register = Hexagon::R18;
762     break;
763   case Hexagon::R9:
764     Register = Hexagon::R17;
765     break;
766   case Hexagon::R8:
767     Register = Hexagon::R16;
768     break;
769   }
770 }
771 
reportErrorRegisters(unsigned Register)772 void HexagonMCChecker::reportErrorRegisters(unsigned Register) {
773   reportError("register `" + Twine(RI.getName(Register)) +
774               "' modified more than once");
775 }
776 
reportErrorNewValue(unsigned Register)777 void HexagonMCChecker::reportErrorNewValue(unsigned Register) {
778   reportError("register `" + Twine(RI.getName(Register)) +
779               "' used with `.new' "
780               "but not validly modified in the same packet");
781 }
782 
reportError(Twine const & Msg)783 void HexagonMCChecker::reportError(Twine const &Msg) {
784   reportError(MCB.getLoc(), Msg);
785 }
786 
reportError(SMLoc Loc,Twine const & Msg)787 void HexagonMCChecker::reportError(SMLoc Loc, Twine const &Msg) {
788   if (ReportErrors)
789     Context.reportError(Loc, Msg);
790 }
791 
reportNote(SMLoc Loc,llvm::Twine const & Msg)792 void HexagonMCChecker::reportNote(SMLoc Loc, llvm::Twine const &Msg) {
793   if (ReportErrors) {
794     auto SM = Context.getSourceManager();
795     if (SM)
796       SM->PrintMessage(Loc, SourceMgr::DK_Note, Msg);
797   }
798 }
799 
reportWarning(Twine const & Msg)800 void HexagonMCChecker::reportWarning(Twine const &Msg) {
801   if (ReportErrors)
802     Context.reportWarning(MCB.getLoc(), Msg);
803 }
804 
checkLegalVecRegPair()805 bool HexagonMCChecker::checkLegalVecRegPair() {
806   const bool IsPermitted = STI.getFeatureBits()[Hexagon::ArchV67];
807   const bool HasReversePairs = ReversePairs.size() != 0;
808 
809   if (!IsPermitted && HasReversePairs) {
810     for (auto R : ReversePairs)
811       reportError("register pair `" + Twine(RI.getName(R)) +
812                   "' is not permitted for this architecture");
813     return false;
814   }
815   return true;
816 }
817 
818 // Vd.tmp can't be accumulated
checkHVXAccum()819 bool HexagonMCChecker::checkHVXAccum()
820 {
821   for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) {
822     bool IsTarget =
823         HexagonMCInstrInfo::isAccumulator(MCII, I) && I.getOperand(0).isReg();
824     if (!IsTarget)
825       continue;
826     unsigned int R = I.getOperand(0).getReg();
827     TmpDefsIterator It = TmpDefs.find(R);
828     if (It != TmpDefs.end()) {
829       reportError("register `" + Twine(RI.getName(R)) + ".tmp" +
830                   "' is accumulated in this packet");
831       return false;
832     }
833   }
834   return true;
835 }
836