xref: /btstack/port/renesas-ek-ra6m4a-da14531/e2-project/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h (revision c30869498fb8e98c1408c9db0e7624f02f483b73) 
1 /***********************************************************************************************************************
2  * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates.  All Rights Reserved.
3  *
4  * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
5  * of Renesas Electronics Corp. and its affiliates ("Renesas").  No other uses are authorized.  Renesas products are
6  * sold pursuant to Renesas terms and conditions of sale.  Purchasers are solely responsible for the selection and use
7  * of Renesas products and Renesas assumes no liability.  No license, express or implied, to any intellectual property
8  * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
9  * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
10  * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
11  * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
12  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
13  * DOCUMENTATION.  RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.  TO THE MAXIMUM
14  * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
15  * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
16  * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
17  * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
18  * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
19  **********************************************************************************************************************/
20 
21 /* Ensure Renesas MCU variation definitions are included to ensure MCU
22  * specific register variations are handled correctly. */
23 #ifndef BSP_FEATURE_H
24  #error "INTERNAL ERROR: bsp_feature.h must be included before renesas.h."
25 #endif
26 
27 /** @addtogroup Renesas
28  * @{
29  */
30 
31 /** @addtogroup RA
32  * @{
33  */
34 
35 #ifndef RA_H
36  #define RA_H
37 
38  #ifdef __cplusplus
39 extern "C" {
40  #endif
41 
42  #include "cmsis_compiler.h"
43 
44 /** @addtogroup Configuration_of_CMSIS
45  * @{
46  */
47 
48 /* =========================================================================================================================== */
49 /* ================                                Interrupt Number Definition                                ================ */
50 /* =========================================================================================================================== */
51 /* IRQn_Type is provided in bsp_arm_exceptions.h. Vectors generated by the FSP Configuration tool are in vector_data.h */
52 
53 /** @} */ /* End of group Configuration_of_CMSIS */
54 
55 /* =========================================================================================================================== */
56 /* ================                           Processor and Core Peripheral Section                           ================ */
57 /* =========================================================================================================================== */
58 
59  #if   __ARM_ARCH_7EM__
60   #define RENESAS_CORTEX_M4
61  #elif __ARM_ARCH_6M__
62   #define RENESAS_CORTEX_M0PLUS
63  #elif __ARM_ARCH_8M_BASE__
64   #define RENESAS_CORTEX_M23
65  #elif __ARM_ARCH_8M_MAIN__
66   #define RENESAS_CORTEX_M33
67  #else
68   #warning Unsupported Architecture
69  #endif
70 
71 /* ----------------Configuration of the Cortex-M Processor and Core Peripherals---------------- */
72  #ifdef RENESAS_CORTEX_M4
73   #define __MPU_PRESENT             1  /*!< MPU present or not                                                    */
74   #define __NVIC_PRIO_BITS          4  /*!< Number of Bits used for Priority Levels                               */
75   #define __Vendor_SysTickConfig    0  /*!< Set to 1 if different SysTick Config is used                          */
76   #define __FPU_PRESENT             1  /*!< FPU present or not                                                    */
77   #include "core_cm4.h"                /*!< Cortex-M4 processor and core peripherals                              */
78  #elif defined(RENESAS_CORTEX_M0PLUS)
79   #define __MPU_PRESENT             1  /*!< MPU present or not                                                    */
80   #define __NVIC_PRIO_BITS          2  /*!< Number of Bits used for Priority Levels                               */
81   #define __Vendor_SysTickConfig    0  /*!< Set to 1 if different SysTick Config is used                          */
82   #define __FPU_PRESENT             0  /*!< FPU present or not                                                    */
83   #define __VTOR_PRESENT            1  /*!< Vector table VTOR register available or not                           */
84   #include "core_cm0plus.h"            /*!< Cortex-M0 processor and core peripherals                              */
85  #elif defined(RENESAS_CORTEX_M23)
86   #define __MPU_PRESENT             1  /*!< MPU present or not                                                    */
87   #define __NVIC_PRIO_BITS          2  /*!< Number of Bits used for Priority Levels                               */
88   #define __Vendor_SysTickConfig    0  /*!< Set to 1 if different SysTick Config is used                          */
89   #define __FPU_PRESENT             0  /*!< FPU present or not                                                    */
90   #define __VTOR_PRESENT            1  /*!< Vector table VTOR register available or not                           */
91   #include "core_cm23.h"               /*!< Cortex-M23 processor and core peripherals                             */
92  #elif defined(RENESAS_CORTEX_M33)
93   #define __MPU_PRESENT             1  /*!< MPU present or not                                                    */
94   #define __NVIC_PRIO_BITS          4  /*!< Number of Bits used for Priority Levels                               */
95   #define __Vendor_SysTickConfig    0  /*!< Set to 1 if different SysTick Config is used                          */
96   #define __FPU_PRESENT             1  /*!< FPU present or not                                                    */
97   #define __VTOR_PRESENT            1  /*!< Vector table VTOR register available or not                           */
98   #define __DSP_PRESENT             1  /*!< DSP present or not                                                    */
99   #include "core_cm33.h"               /*!< Cortex-M33 processor and core peripherals                             */
100  #endif
101 
102  #include "system.h"                   /*!< System                                                                */
103 
104  #ifndef __IM                          /*!< Fallback for older CMSIS versions                                         */
105   #define __IM     __I
106  #endif
107  #ifndef __OM                          /*!< Fallback for older CMSIS versions                                         */
108   #define __OM     __O
109  #endif
110  #ifndef __IOM                         /*!< Fallback for older CMSIS versions                                         */
111   #define __IOM    __IO
112  #endif
113 
114 /* ========================================  Start of section using anonymous unions  ======================================== */
115  #if defined(__CC_ARM)
116   #pragma push
117   #pragma anon_unions
118  #elif defined(__ICCARM__)
119   #pragma language=extended
120  #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
121   #pragma clang diagnostic push
122   #pragma clang diagnostic ignored "-Wc11-extensions"
123   #pragma clang diagnostic ignored "-Wreserved-id-macro"
124   #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
125   #pragma clang diagnostic ignored "-Wnested-anon-types"
126  #elif defined(__GNUC__)
127 
128 /* anonymous unions are enabled by default */
129  #elif defined(__TMS470__)
130 
131 /* anonymous unions are enabled by default */
132  #elif defined(__TASKING__)
133   #pragma warning 586
134  #elif defined(__CSMC__)
135 
136 /* anonymous unions are enabled by default */
137  #else
138   #warning Not supported compiler type
139  #endif
140 
141 /* =========================================================================================================================== */
142 /* ================                              Device Specific Cluster Section                              ================ */
143 /* =========================================================================================================================== */
144 
145 /** @addtogroup Device_Peripheral_clusters
146  * @{
147  */
148 
149 /**
150  * @brief R_BUS_CSa [CSa] (CS Registers)
151  */
152 typedef struct
153 {
154     __IM uint16_t RESERVED;
155 
156     union
157     {
158         __IOM uint16_t MOD;            /*!< (@ 0x00000002) Mode Register                                              */
159 
160         struct
161         {
162             __IOM uint16_t WRMOD : 1;  /*!< [0..0] Write Access Mode Select                                           */
163             uint16_t             : 2;
164             __IOM uint16_t EWENB : 1;  /*!< [3..3] External Wait Enable                                               */
165             uint16_t             : 4;
166             __IOM uint16_t PRENB : 1;  /*!< [8..8] Page Read Access Enable                                            */
167             __IOM uint16_t PWENB : 1;  /*!< [9..9] Page Write Access Enable                                           */
168             uint16_t             : 5;
169             __IOM uint16_t PRMOD : 1;  /*!< [15..15] Page Read Access Mode Select                                     */
170         } MOD_b;
171     };
172 
173     union
174     {
175         __IOM uint32_t WCR1;             /*!< (@ 0x00000004) Wait Control Register 1                                    */
176 
177         struct
178         {
179             __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value
180                                           *   is valid only when the PWENB bit in CSnMOD is set to 1.                   */
181             uint32_t                : 5;
182             __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value
183                                           *   is valid only when the PRENB bit in CSnMOD is set to 1.                   */
184             uint32_t               : 5;
185             __IOM uint32_t CSWWAIT : 5;  /*!< [20..16] Normal Write Cycle Wait Select                                   */
186             uint32_t               : 3;
187             __IOM uint32_t CSRWAIT : 5;  /*!< [28..24] Normal Read Cycle Wait Select                                    */
188             uint32_t               : 3;
189         } WCR1_b;
190     };
191 
192     union
193     {
194         __IOM uint32_t WCR2;           /*!< (@ 0x00000008) Wait Control Register 2                                    */
195 
196         struct
197         {
198             __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select                              */
199             uint32_t              : 1;
200             __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select                             */
201             uint32_t              : 1;
202             __IOM uint32_t WDOFF  : 3; /*!< [10..8] Write Data Output Extension Cycle Select                          */
203             uint32_t              : 1;
204             __IOM uint32_t AWAIT  : 2; /*!< [13..12] CS Assert Wait Select                                            */
205             uint32_t              : 2;
206             __IOM uint32_t RDON   : 3; /*!< [18..16] RD Assert Wait Select                                            */
207             uint32_t              : 1;
208             __IOM uint32_t WRON   : 3; /*!< [22..20] WR Assert Wait Select                                            */
209             uint32_t              : 1;
210             __IOM uint32_t WDON   : 3; /*!< [26..24] Write Data Output Wait Select                                    */
211             uint32_t              : 1;
212             __IOM uint32_t CSON   : 3; /*!< [30..28] CS Assert Wait Select                                            */
213             uint32_t              : 1;
214         } WCR2_b;
215     };
216     __IM uint32_t RESERVED1;
217 } R_BUS_CSa_Type;                      /*!< Size = 16 (0x10)                                                          */
218 
219 /**
220  * @brief R_BUS_CSb [CSb] (CS Registers)
221  */
222 typedef struct
223 {
224     __IM uint16_t RESERVED;
225 
226     union
227     {
228         __IOM uint16_t CR;             /*!< (@ 0x00000002) Control Register                                           */
229 
230         struct
231         {
232             __IOM uint16_t EXENB : 1;  /*!< [0..0] Operation Enable                                                   */
233             uint16_t             : 3;
234             __IOM uint16_t BSIZE : 2;  /*!< [5..4] External Bus Width Select                                          */
235             uint16_t             : 2;
236             __IOM uint16_t EMODE : 1;  /*!< [8..8] Endian Mode                                                        */
237             uint16_t             : 3;
238             __IOM uint16_t MPXEN : 1;  /*!< [12..12] Address/Data Multiplexed I/O Interface Select                    */
239             uint16_t             : 3;
240         } CR_b;
241     };
242     __IM uint16_t RESERVED1[3];
243 
244     union
245     {
246         __IOM uint16_t REC;            /*!< (@ 0x0000000A) Recovery Cycle Register                                    */
247 
248         struct
249         {
250             __IOM uint16_t RRCV : 4;   /*!< [3..0] Read Recovery                                                      */
251             uint16_t            : 4;
252             __IOM uint16_t WRCV : 4;   /*!< [11..8] Write Recovery                                                    */
253             uint16_t            : 4;
254         } REC_b;
255     };
256     __IM uint16_t RESERVED2[2];
257 } R_BUS_CSb_Type;                      /*!< Size = 16 (0x10)                                                          */
258 
259 /**
260  * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers)
261  */
262 typedef struct
263 {
264     union
265     {
266         __IOM uint8_t SDCCR;           /*!< (@ 0x00000000) SDC Control Register                                       */
267 
268         struct
269         {
270             __IOM uint8_t EXENB : 1;   /*!< [0..0] Operation Enable                                                   */
271             uint8_t             : 3;
272             __IOM uint8_t BSIZE : 2;   /*!< [5..4] SDRAM Bus Width Select                                             */
273             uint8_t             : 2;
274         } SDCCR_b;
275     };
276 
277     union
278     {
279         __IOM uint8_t SDCMOD;          /*!< (@ 0x00000001) SDC Mode Register                                          */
280 
281         struct
282         {
283             __IOM uint8_t EMODE : 1;   /*!< [0..0] Endian Mode                                                        */
284             uint8_t             : 7;
285         } SDCMOD_b;
286     };
287 
288     union
289     {
290         __IOM uint8_t SDAMOD;          /*!< (@ 0x00000002) SDRAM Access Mode Register                                 */
291 
292         struct
293         {
294             __IOM uint8_t BE : 1;      /*!< [0..0] Continuous Access Enable                                           */
295             uint8_t          : 7;
296         } SDAMOD_b;
297     };
298     __IM uint8_t  RESERVED;
299     __IM uint32_t RESERVED1[3];
300 
301     union
302     {
303         __IOM uint8_t SDSELF;          /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register                        */
304 
305         struct
306         {
307             __IOM uint8_t SFEN : 1;    /*!< [0..0] SDRAM Self-Refresh Enable                                          */
308             uint8_t            : 7;
309         } SDSELF_b;
310     };
311     __IM uint8_t  RESERVED2;
312     __IM uint16_t RESERVED3;
313 
314     union
315     {
316         __IOM uint16_t SDRFCR;         /*!< (@ 0x00000014) SDRAM Refresh Control Register                             */
317 
318         struct
319         {
320             __IOM uint16_t RFC  : 12;  /*!< [11..0] Auto-Refresh Request Interval Setting                             */
321             __IOM uint16_t REFW : 4;   /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count
322                                         *   Setting. ( REFW+1 Cycles )                                                */
323         } SDRFCR_b;
324     };
325 
326     union
327     {
328         __IOM uint8_t SDRFEN;          /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register                        */
329 
330         struct
331         {
332             __IOM uint8_t RFEN : 1;    /*!< [0..0] Auto-Refresh Operation Enable                                      */
333             uint8_t            : 7;
334         } SDRFEN_b;
335     };
336     __IM uint8_t  RESERVED4;
337     __IM uint32_t RESERVED5[2];
338 
339     union
340     {
341         __IOM uint8_t SDICR;           /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register             */
342 
343         struct
344         {
345             __IOM uint8_t INIRQ : 1;   /*!< [0..0] Initialization Sequence Start                                      */
346             uint8_t             : 7;
347         } SDICR_b;
348     };
349     __IM uint8_t  RESERVED6;
350     __IM uint16_t RESERVED7;
351 
352     union
353     {
354         __IOM uint16_t SDIR;           /*!< (@ 0x00000024) SDRAM Initialization Register                              */
355 
356         struct
357         {
358             __IOM uint16_t ARFI : 4;   /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles )              */
359             __IOM uint16_t ARFC : 4;   /*!< [7..4] Initialization Auto-Refresh Count                                  */
360             __IOM uint16_t PRC  : 3;   /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles
361                                         *   )                                                                         */
362             uint16_t : 5;
363         } SDIR_b;
364     };
365     __IM uint16_t RESERVED8;
366     __IM uint32_t RESERVED9[6];
367 
368     union
369     {
370         __IOM uint8_t SDADR;           /*!< (@ 0x00000040) SDRAM Address Register                                     */
371 
372         struct
373         {
374             __IOM uint8_t MXC : 2;     /*!< [1..0] Address Multiplex Select                                           */
375             uint8_t           : 6;
376         } SDADR_b;
377     };
378     __IM uint8_t  RESERVED10;
379     __IM uint16_t RESERVED11;
380 
381     union
382     {
383         __IOM uint32_t SDTR;           /*!< (@ 0x00000044) SDRAM Timing Register                                      */
384 
385         struct
386         {
387             __IOM uint32_t CL  : 3;    /*!< [2..0] SDRAMC Column Latency                                              */
388             uint32_t           : 5;
389             __IOM uint32_t WR  : 1;    /*!< [8..8] Write Recovery Interval                                            */
390             __IOM uint32_t RP  : 3;    /*!< [11..9] Row Precharge Interval ( RP+1 cycles )                            */
391             __IOM uint32_t RCD : 2;    /*!< [13..12] Row Column Latency ( RCD+1 cycles )                              */
392             uint32_t           : 2;
393             __IOM uint32_t RAS : 3;    /*!< [18..16] Row Active Interval                                              */
394             uint32_t           : 13;
395         } SDTR_b;
396     };
397 
398     union
399     {
400         __IOM uint16_t SDMOD;          /*!< (@ 0x00000048) SDRAM Mode Register                                        */
401 
402         struct
403         {
404             __IOM uint16_t MR : 15;    /*!< [14..0] Mode Register SettingWriting to these bits: Mode register
405                                         *   set command is issued.                                                    */
406             uint16_t : 1;
407         } SDMOD_b;
408     };
409     __IM uint16_t RESERVED12;
410     __IM uint32_t RESERVED13;
411 
412     union
413     {
414         __IM uint8_t SDSR;             /*!< (@ 0x00000050) SDRAM Status Register                                      */
415 
416         struct
417         {
418             __IM uint8_t MRSST : 1;    /*!< [0..0] Mode Register Setting Status                                       */
419             uint8_t            : 2;
420             __IM uint8_t INIST : 1;    /*!< [3..3] Initialization Status                                              */
421             __IM uint8_t SRFST : 1;    /*!< [4..4] Self-Refresh Transition/Recovery Status                            */
422             uint8_t            : 3;
423         } SDSR_b;
424     };
425     __IM uint8_t  RESERVED14;
426     __IM uint16_t RESERVED15;
427 } R_BUS_SDRAM_Type;                    /*!< Size = 84 (0x54)                                                          */
428 
429 /**
430  * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers)
431  */
432 typedef struct
433 {
434     union
435     {
436         __IM uint32_t ADD;             /*!< (@ 0x00000000) Bus Error Address Register                                 */
437 
438         struct
439         {
440             __IM uint32_t BERAD : 32;  /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores
441                                         *   an error address.                                                         */
442         } ADD_b;
443     };
444 
445     union
446     {
447         __IM uint8_t STAT;             /*!< (@ 0x00000004) Bus Error Status Register                                  */
448 
449         struct
450         {
451             __IM uint8_t ACCSTAT : 1;  /*!< [0..0] Error access statusThe status at the time of the error             */
452             uint8_t              : 6;
453             __IM uint8_t ERRSTAT : 1;  /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs.          */
454         } STAT_b;
455     };
456     __IM uint8_t  RESERVED;
457     __IM uint16_t RESERVED1;
458     __IM uint32_t RESERVED2[2];
459 } R_BUS_BUSERR_Type;                   /*!< Size = 16 (0x10)                                                          */
460 
461 /**
462  * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array)
463  */
464 typedef struct
465 {
466     union
467     {
468         __IOM uint16_t CNT;            /*!< (@ 0x00000000) Master Bus Control Register                                */
469 
470         struct
471         {
472             uint16_t             : 15;
473             __IOM uint16_t IERES : 1;  /*!< [15..15] Ignore Error Responses                                           */
474         } CNT_b;
475     };
476     __IM uint16_t RESERVED;
477 } R_BUS_BUSM_Type;                     /*!< Size = 4 (0x4)                                                            */
478 
479 /**
480  * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array)
481  */
482 typedef struct
483 {
484     union
485     {
486         __IOM uint16_t CNT;            /*!< (@ 0x00000000) Slave Bus Control Register                                 */
487 
488         struct
489         {
490             uint16_t              : 4;
491             __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups              */
492             uint16_t              : 10;
493         } CNT_b;
494     };
495     __IM uint16_t RESERVED;
496 } R_BUS_BUSS_Type;                     /*!< Size = 4 (0x4)                                                            */
497 
498 /**
499  * @brief R_CAN0_MB [MB] (Mailbox)
500  */
501 typedef struct
502 {
503     union
504     {
505         __IOM uint32_t ID;             /*!< (@ 0x00000000) Mailbox ID Register                                        */
506 
507         struct
508         {
509             __IOM uint32_t EID : 18;   /*!< [17..0] Extended ID                                                       */
510             __IOM uint32_t SID : 11;   /*!< [28..18] Standard ID                                                      */
511             uint32_t           : 1;
512             __IOM uint32_t RTR : 1;    /*!< [30..30] Remote Transmission Request                                      */
513             __IOM uint32_t IDE : 1;    /*!< [31..31] ID Extension                                                     */
514         } ID_b;
515     };
516 
517     union
518     {
519         __IOM uint16_t DL;             /*!< (@ 0x00000004) Mailbox DLC Register                                       */
520 
521         struct
522         {
523             __IOM uint16_t DLC : 4;    /*!< [3..0] Data Length Code                                                   */
524             uint16_t           : 12;
525         } DL_b;
526     };
527 
528     union
529     {
530         __IOM uint8_t D[8];            /*!< (@ 0x00000006) Mailbox Data Register                                      */
531 
532         struct
533         {
534             __IOM uint8_t DATA : 8;    /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN
535                                         *   message data. Transmission or reception starts from DATA0.
536                                         *   The bit order on the CAN bus is MSB-first, and transmission
537                                         *   or reception starts from bit 7                                            */
538         } D_b[8];
539     };
540 
541     union
542     {
543         __IOM uint16_t TS;             /*!< (@ 0x0000000E) Mailbox Timestamp Register                                 */
544 
545         struct
546         {
547             __IOM uint16_t TSL : 8;    /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter
548                                         *   value of the time stamp when received messages are stored
549                                         *   in the mailbox.                                                           */
550             __IOM uint16_t TSH : 8;    /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter
551                                         *   value of the time stamp when received messages are stored
552                                         *   in the mailbox.                                                           */
553         } TS_b;
554     };
555 } R_CAN0_MB_Type;                      /*!< Size = 16 (0x10)                                                          */
556 
557 /**
558  * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status)
559  */
560 typedef struct
561 {
562     union
563     {
564         __IOM uint32_t NCFG;            /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register             */
565 
566         struct
567         {
568             __IOM uint32_t NBRP   : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler                                */
569             __IOM uint32_t NSJW   : 7;  /*!< [16..10] Resynchronization Jump Width                                     */
570             __IOM uint32_t NTSEG1 : 8;  /*!< [24..17] Timing Segment 1                                                 */
571             __IOM uint32_t NTSEG2 : 7;  /*!< [31..25] Timing Segment 2                                                 */
572         } NCFG_b;
573     };
574 
575     union
576     {
577         __IOM uint32_t CTR;             /*!< (@ 0x00000004) Channel Control Registers                                  */
578 
579         struct
580         {
581             __IOM uint32_t CHMDC   : 2; /*!< [1..0] Channel Mode Control                                               */
582             __IOM uint32_t CSLPR   : 1; /*!< [2..2] Channel Sleep Request                                              */
583             __IOM uint32_t RTBO    : 1; /*!< [3..3] Return from Bus-Off                                                */
584             uint32_t               : 4;
585             __IOM uint32_t BEIE    : 1; /*!< [8..8] Bus Error Interrupt Enable                                         */
586             __IOM uint32_t EWIE    : 1; /*!< [9..9] Error Warning Interrupt Enable                                     */
587             __IOM uint32_t EPIE    : 1; /*!< [10..10] Error Passive Interrupt Enable                                   */
588             __IOM uint32_t BOEIE   : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable                                   */
589             __IOM uint32_t BORIE   : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable                                */
590             __IOM uint32_t OLIE    : 1; /*!< [13..13] Overload Interrupt Enable                                        */
591             __IOM uint32_t BLIE    : 1; /*!< [14..14] Bus Lock Interrupt Enable                                        */
592             __IOM uint32_t ALIE    : 1; /*!< [15..15] Arbitration Lost Interrupt Enable                                */
593             __IOM uint32_t TAIE    : 1; /*!< [16..16] Transmission abort Interrupt Enable                              */
594             __IOM uint32_t EOCOIE  : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable               */
595             __IOM uint32_t SOCOIE  : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable          */
596             __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt
597                                          *   enable                                                                    */
598             uint32_t            : 1;
599             __IOM uint32_t BOM  : 2;    /*!< [22..21] Channel Bus-Off Mode                                             */
600             __IOM uint32_t ERRD : 1;    /*!< [23..23] Channel Error Display                                            */
601             __IOM uint32_t CTME : 1;    /*!< [24..24] Channel Test Mode Enable                                         */
602             __IOM uint32_t CTMS : 2;    /*!< [26..25] Channel Test Mode Select                                         */
603             __IOM uint32_t TRWE : 1;    /*!< [27..27] TEC/REC Write Enable                                             */
604             __IOM uint32_t TRH  : 1;    /*!< [28..28] TEC/REC Hold                                                     */
605             __IOM uint32_t TRR  : 1;    /*!< [29..29] TEC/REC Reset                                                    */
606             __IOM uint32_t CRCT : 1;    /*!< [30..30] CRC Error Test                                                   */
607             __IOM uint32_t ROM  : 1;    /*!< [31..31] Restricted Operation Mode                                        */
608         } CTR_b;
609     };
610 
611     union
612     {
613         __IOM uint32_t STS;             /*!< (@ 0x00000008) Channel Status Registers                                   */
614 
615         struct
616         {
617             __IM uint32_t  CRSTSTS : 1; /*!< [0..0] Channel RESET Status                                               */
618             __IM uint32_t  CHLTSTS : 1; /*!< [1..1] Channel HALT Status                                                */
619             __IM uint32_t  CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status                                               */
620             __IM uint32_t  EPSTS   : 1; /*!< [3..3] Channel Error Passive Status                                       */
621             __IM uint32_t  BOSTS   : 1; /*!< [4..4] Channel Bus-Off Status                                             */
622             __IM uint32_t  TRMSTS  : 1; /*!< [5..5] Channel Transmit Status                                            */
623             __IM uint32_t  RECSTS  : 1; /*!< [6..6] Channel Receive Status                                             */
624             __IM uint32_t  COMSTS  : 1; /*!< [7..7] Channel Communication Status                                       */
625             __IOM uint32_t ESIF    : 1; /*!< [8..8] Error State Indication Flag                                        */
626             uint32_t               : 7;
627             __IM uint32_t  REC     : 8; /*!< [23..16] Reception Error Count                                            */
628             __IOM uint32_t TEC     : 8; /*!< [31..24] Transmission Error Count                                         */
629         } STS_b;
630     };
631 
632     union
633     {
634         __IOM uint32_t ERFL;           /*!< (@ 0x0000000C) Channel Error Flag Registers                               */
635 
636         struct
637         {
638             __IOM uint32_t BEF   : 1;  /*!< [0..0] Bus Error Flag                                                     */
639             __IOM uint32_t EWF   : 1;  /*!< [1..1] Error Warning Flag                                                 */
640             __IOM uint32_t EPF   : 1;  /*!< [2..2] Error Passive Flag                                                 */
641             __IOM uint32_t BOEF  : 1;  /*!< [3..3] Bus-Off Entry Flag                                                 */
642             __IOM uint32_t BORF  : 1;  /*!< [4..4] Bus-Off Recovery Flag                                              */
643             __IOM uint32_t OVLF  : 1;  /*!< [5..5] Overload Flag                                                      */
644             __IOM uint32_t BLF   : 1;  /*!< [6..6] Bus Lock Flag                                                      */
645             __IOM uint32_t ALF   : 1;  /*!< [7..7] Arbitration Lost Flag                                              */
646             __IOM uint32_t SERR  : 1;  /*!< [8..8] Stuff Error                                                        */
647             __IOM uint32_t FERR  : 1;  /*!< [9..9] Form Error                                                         */
648             __IOM uint32_t AERR  : 1;  /*!< [10..10] Acknowledge Error                                                */
649             __IOM uint32_t CERR  : 1;  /*!< [11..11] CRC Error                                                        */
650             __IOM uint32_t B1ERR : 1;  /*!< [12..12] Bit 1 Error                                                      */
651             __IOM uint32_t B0ERR : 1;  /*!< [13..13] Bit 0 Error                                                      */
652             __IOM uint32_t ADERR : 1;  /*!< [14..14] Acknowledge Delimiter Error                                      */
653             uint32_t             : 1;
654             __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value                                               */
655             uint32_t             : 1;
656         } ERFL_b;
657     };
658 } R_CANFD_CFDC_Type;                   /*!< Size = 16 (0x10)                                                          */
659 
660 /**
661  * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers)
662  */
663 typedef struct
664 {
665     union
666     {
667         __IOM uint32_t DCFG;           /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register                */
668 
669         struct
670         {
671             __IOM uint32_t DBRP   : 8; /*!< [7..0] Channel Data Baud Rate Prescaler                                   */
672             __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1                                                  */
673             uint32_t              : 3;
674             __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2                                                 */
675             uint32_t              : 4;
676             __IOM uint32_t DSJW   : 4; /*!< [27..24] Resynchronization Jump Width                                     */
677             uint32_t              : 4;
678         } DCFG_b;
679     };
680 
681     union
682     {
683         __IOM uint32_t FDCFG;          /*!< (@ 0x00000004) Channel CAN-FD Configuration Register                      */
684 
685         struct
686         {
687             __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration                             */
688             uint32_t              : 5;
689             __IOM uint32_t TDCOC  : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration                */
690             __IOM uint32_t TDCE   : 1; /*!< [9..9] Transceiver Delay Compensation Enable                              */
691             __IOM uint32_t ESIC   : 1; /*!< [10..10] Error State Indication Configuration                             */
692             uint32_t              : 5;
693             __IOM uint32_t TDCO   : 8; /*!< [23..16] Transceiver Delay Compensation Offset                            */
694             __IOM uint32_t GWEN   : 1; /*!< [24..24] CAN2.0, CAN-FD <> CAN2.0, CAN-FD Multi Gateway Enable            */
695             __IOM uint32_t GWFDF  : 1; /*!< [25..25] Gateway FDF configuration bit                                    */
696             __IOM uint32_t GWBRS  : 1; /*!< [26..26] Gateway BRS configuration bit                                    */
697             uint32_t              : 1;
698             __IOM uint32_t FDOE   : 1; /*!< [28..28] FD only enable                                                   */
699             __IOM uint32_t REFE   : 1; /*!< [29..29] RX edge filter enable                                            */
700             __IOM uint32_t CLOE   : 1; /*!< [30..30] Classical CAN only enable                                        */
701             __IOM uint32_t CFDTE  : 1; /*!< [31..31] CAN-FD frame Distinction enable                                  */
702         } FDCFG_b;
703     };
704 
705     union
706     {
707         __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) Channel CAN-FD Control Register                            */
708 
709         struct
710         {
711             __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear                                     */
712             __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear                                */
713             uint32_t              : 30;
714         } FDCTR_b;
715     };
716 
717     union
718     {
719         __IOM uint32_t FDSTS;          /*!< (@ 0x0000000C) Channel CAN-FD Status Register                             */
720 
721         struct
722         {
723             __IM uint32_t  TDCR  : 8;  /*!< [7..0] Transceiver Delay Compensation Result                              */
724             __IOM uint32_t EOCO  : 1;  /*!< [8..8] Error occurrence counter overflow                                  */
725             __IOM uint32_t SOCO  : 1;  /*!< [9..9] Successful occurrence counter overflow                             */
726             uint32_t             : 5;
727             __IOM uint32_t TDCVF : 1;  /*!< [15..15] Transceiver Delay Compensation Violation Flag                    */
728             __IM uint32_t  EOC   : 8;  /*!< [23..16] Error occurrence counter register                                */
729             __IM uint32_t  SOC   : 8;  /*!< [31..24] Successful occurrence counter register                           */
730         } FDSTS_b;
731     };
732 
733     union
734     {
735         __IOM uint32_t FDCRC;          /*!< (@ 0x00000010) Channel CAN-FD CRC Register                                */
736 
737         struct
738         {
739             __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value                                                */
740             uint32_t             : 3;
741             __IM uint32_t SCNT   : 4;  /*!< [27..24] Stuff bit count                                                  */
742             uint32_t             : 4;
743         } FDCRC_b;
744     };
745     __IM uint32_t RESERVED;
746 
747     union
748     {
749         __IOM uint32_t BLCT;           /*!< (@ 0x00000018) Channel Bus load Control Register                          */
750 
751         struct
752         {
753             __IOM uint32_t BLCE : 1;   /*!< [0..0] BUS Load counter Enable                                            */
754             uint32_t            : 7;
755             __OM uint32_t BLCLD : 1;   /*!< [8..8] BUS Load counter load                                              */
756             uint32_t            : 23;
757         } BLCT_b;
758     };
759 
760     union
761     {
762         __IOM uint32_t BLSTS;          /*!< (@ 0x0000001C) Channel Bus load Status Register                           */
763 
764         struct
765         {
766             uint32_t          : 3;
767             __IM uint32_t BLC : 29;    /*!< [31..3] BUS Load counter Status                                           */
768         } BLSTS_b;
769     };
770 } R_CANFD_CFDC2_Type;                  /*!< Size = 32 (0x20)                                                          */
771 
772 /**
773  * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers)
774  */
775 typedef struct
776 {
777     union
778     {
779         __IOM uint32_t ID;               /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers                 */
780 
781         struct
782         {
783             __IOM uint32_t GAFLID  : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field                      */
784             __IOM uint32_t GAFLLB  : 1;  /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration       */
785             __IOM uint32_t GAFLRTR : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Field                    */
786             __IOM uint32_t GAFLIDE : 1;  /*!< [31..31] Global Acceptance Filter List Entry IDE Field                    */
787         } ID_b;
788     };
789 
790     union
791     {
792         __IOM uint32_t M;                 /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers               */
793 
794         struct
795         {
796             __IOM uint32_t GAFLIDM  : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field                       */
797             __IOM uint32_t GAFLIFL1 : 1;  /*!< [29..29] Global Acceptance Filter List Information Label 1                */
798             __IOM uint32_t GAFLRTRM : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Mask                     */
799             __IOM uint32_t GAFLIDEM : 1;  /*!< [31..31] Global Acceptance Filter List IDE Mask                           */
800         } M_b;
801     };
802 
803     union
804     {
805         __IOM uint32_t P0;               /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers          */
806 
807         struct
808         {
809             __IOM uint32_t GAFLDLC  : 4; /*!< [3..0] Global Acceptance Filter List DLC Field                            */
810             __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing destination
811                                           *   0                                                                         */
812             __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing destination
813                                           *   1                                                                         */
814             __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing destination
815                                           *   2                                                                         */
816             __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0                  */
817             __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction
818                                           *   Pointer                                                                   */
819             uint32_t               : 2;
820             __IOM uint32_t GAFLRMV : 1;  /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid            */
821             __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field                      */
822         } P0_b;
823     };
824 
825     union
826     {
827         __IOM uint32_t P1;               /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers          */
828 
829         struct
830         {
831             __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer              */
832             uint32_t               : 18;
833         } P1_b;
834     };
835 } R_CANFD_CFDGAFL_Type;                  /*!< Size = 16 (0x10)                                                          */
836 
837 /**
838  * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List)
839  */
840 typedef struct
841 {
842     union
843     {
844         __IM uint32_t ACC0;            /*!< (@ 0x00000000) Channel TX History List Access Registers 0                 */
845 
846         struct
847         {
848             __IM uint32_t BT   : 3;    /*!< [2..0] Buffer Type                                                        */
849             __IM uint32_t BN   : 7;    /*!< [9..3] Buffer No.                                                         */
850             uint32_t           : 5;
851             __IM uint32_t TGW  : 1;    /*!< [15..15] Transmit Gateway Buffer indication                               */
852             __IM uint32_t TMTS : 16;   /*!< [31..16] Transmit Timestamp                                               */
853         } ACC0_b;
854     };
855 
856     union
857     {
858         __IOM uint32_t ACC1;           /*!< (@ 0x00000004) Channel TX History List Access Registers 1                 */
859 
860         struct
861         {
862             __IM uint32_t TID  : 16;   /*!< [15..0] Transmit ID                                                       */
863             __IM uint32_t TIFL : 2;    /*!< [17..16] Transmit Information Label                                       */
864             uint32_t           : 14;
865         } ACC1_b;
866     };
867 } R_CANFD_CFDTHL_Type;                 /*!< Size = 8 (0x8)                                                            */
868 
869 /**
870  * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers)
871  */
872 typedef struct
873 {
874     union
875     {
876         __IM uint32_t ID;              /*!< (@ 0x00000000) RX Message Buffer ID Register                              */
877 
878         struct
879         {
880             __IM uint32_t RMID  : 29;  /*!< [28..0] RX Message Buffer ID Field                                        */
881             uint32_t            : 1;
882             __IM uint32_t RMRTR : 1;   /*!< [30..30] RX Message Buffer RTR Frame                                      */
883             __IM uint32_t RMIDE : 1;   /*!< [31..31] RX Message Buffer IDE Bit                                        */
884         } ID_b;
885     };
886 
887     union
888     {
889         __IM uint32_t PTR;             /*!< (@ 0x00000004) RX Message Buffer Pointer Register                         */
890 
891         struct
892         {
893             __IM uint32_t RMTS  : 16;  /*!< [15..0] RX Message Buffer Timestamp Field                                 */
894             uint32_t            : 12;
895             __IM uint32_t RMDLC : 4;   /*!< [31..28] RX Message Buffer DLC Field                                      */
896         } PTR_b;
897     };
898 
899     union
900     {
901         __IM uint32_t FDSTS;           /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register                   */
902 
903         struct
904         {
905             __IM uint32_t RMESI : 1;   /*!< [0..0] Error State Indicator bit                                          */
906             __IM uint32_t RMBRS : 1;   /*!< [1..1] Bit Rate Switch bit                                                */
907             __IM uint32_t RMFDF : 1;   /*!< [2..2] CAN FD Format bit                                                  */
908             uint32_t            : 5;
909             __IM uint32_t RMIFL : 2;   /*!< [9..8] RX Message Buffer Information Label Field                          */
910             uint32_t            : 6;
911             __IM uint32_t RMPTR : 16;  /*!< [31..16] RX Message Buffer Pointer Field                                  */
912         } FDSTS_b;
913     };
914 
915     union
916     {
917         __IM uint8_t DF[64];           /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers                     */
918 
919         struct
920         {
921             __IM uint8_t RMDB : 8;     /*!< [7..0] RX Message Buffer Data Byte                                        */
922         } DF_b[64];
923     };
924     __IM uint32_t RESERVED[13];
925 } R_CANFD_CFDRM_Type;                  /*!< Size = 128 (0x80)                                                         */
926 
927 /**
928  * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers)
929  */
930 typedef struct
931 {
932     union
933     {
934         __IM uint32_t ID;              /*!< (@ 0x00000000) RX FIFO Access ID Register                                 */
935 
936         struct
937         {
938             __IM uint32_t RFID  : 29;  /*!< [28..0] RX FIFO Buffer ID Field                                           */
939             uint32_t            : 1;
940             __IM uint32_t RFRTR : 1;   /*!< [30..30] RX FIFO Buffer RTR Frame                                         */
941             __IM uint32_t RFIDE : 1;   /*!< [31..31] RX FIFO Buffer IDE Bit                                           */
942         } ID_b;
943     };
944 
945     union
946     {
947         __IM uint32_t PTR;             /*!< (@ 0x00000004) RX FIFO Access Pointer Register                            */
948 
949         struct
950         {
951             __IM uint32_t RFTS  : 16;  /*!< [15..0] RX FIFO Timestamp Field                                           */
952             uint32_t            : 12;
953             __IM uint32_t RFDLC : 4;   /*!< [31..28] RX FIFO Buffer DLC Field                                         */
954         } PTR_b;
955     };
956 
957     union
958     {
959         __IM uint32_t FDSTS;           /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register                      */
960 
961         struct
962         {
963             __IM uint32_t RFESI : 1;   /*!< [0..0] Error State Indicator bit                                          */
964             __IM uint32_t RFBRS : 1;   /*!< [1..1] Bit Rate Switch bit                                                */
965             __IM uint32_t RFFDF : 1;   /*!< [2..2] CAN FD Format bit                                                  */
966             uint32_t            : 5;
967             __IM uint32_t RFIFL : 2;   /*!< [9..8] RX FIFO Buffer Information Label Field                             */
968             uint32_t            : 6;
969             __IM uint32_t RFPTR : 16;  /*!< [31..16] RX FIFO Buffer Pointer Field                                     */
970         } FDSTS_b;
971     };
972 
973     union
974     {
975         __IM uint8_t DF[64];           /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers                        */
976 
977         struct
978         {
979             __IM uint8_t RFDB : 8;     /*!< [7..0] RX FIFO Buffer Data Byte                                           */
980         } DF_b[64];
981     };
982     __IM uint32_t RESERVED[13];
983 } R_CANFD_CFDRF_Type;                  /*!< Size = 128 (0x80)                                                         */
984 
985 /**
986  * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers)
987  */
988 typedef struct
989 {
990     union
991     {
992         __IOM uint32_t ID;             /*!< (@ 0x00000000) Common FIFO Access ID Register                             */
993 
994         struct
995         {
996             __IOM uint32_t CFID  : 29; /*!< [28..0] Common FIFO Buffer ID Field                                       */
997             uint32_t             : 1;
998             __IOM uint32_t CFRTR : 1;  /*!< [30..30] Common FIFO Buffer RTR Frame                                     */
999             __IOM uint32_t CFIDE : 1;  /*!< [31..31] Common FIFO Buffer IDE Bit                                       */
1000         } ID_b;
1001     };
1002 
1003     union
1004     {
1005         __IOM uint32_t PTR;            /*!< (@ 0x00000004) Common FIFO Access Pointer Register                        */
1006 
1007         struct
1008         {
1009             __IOM uint32_t CFTS  : 16; /*!< [15..0] Common FIFO Timestamp Field                                       */
1010             uint32_t             : 12;
1011             __IOM uint32_t CFDLC : 4;  /*!< [31..28] Common FIFO Buffer DLC Field                                     */
1012         } PTR_b;
1013     };
1014 
1015     union
1016     {
1017         __IOM uint32_t FDSTS;          /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register                  */
1018 
1019         struct
1020         {
1021             __IOM uint32_t CFESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
1022             __IOM uint32_t CFBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
1023             __IOM uint32_t CFFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
1024             uint32_t             : 5;
1025             __IOM uint32_t CFIFL : 2;  /*!< [9..8] Common FIFO Buffer Information Label Field                         */
1026             uint32_t             : 6;
1027             __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field                                 */
1028         } FDSTS_b;
1029     };
1030 
1031     union
1032     {
1033         __IOM uint8_t DF[64];          /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers                    */
1034 
1035         struct
1036         {
1037             __IOM uint8_t CFDB : 8;    /*!< [7..0] Common FIFO Buffer Data Byte                                       */
1038         } DF_b[64];
1039     };
1040     __IM uint32_t RESERVED[13];
1041 } R_CANFD_CFDCF_Type;                  /*!< Size = 128 (0x80)                                                         */
1042 
1043 /**
1044  * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers)
1045  */
1046 typedef struct
1047 {
1048     union
1049     {
1050         __IOM uint32_t ID;             /*!< (@ 0x00000000) TX Message Buffer ID Register                              */
1051 
1052         struct
1053         {
1054             __IOM uint32_t TMID  : 29; /*!< [28..0] TX Message Buffer ID Field                                        */
1055             uint32_t             : 1;
1056             __IOM uint32_t TMRTR : 1;  /*!< [30..30] TX Message Buffer RTR Frame                                      */
1057             __IOM uint32_t TMIDE : 1;  /*!< [31..31] TX Message Buffer IDE Bit                                        */
1058         } ID_b;
1059     };
1060 
1061     union
1062     {
1063         __IOM uint32_t PTR;            /*!< (@ 0x00000004) TX Message Buffer Pointer Register                         */
1064 
1065         struct
1066         {
1067             __IOM uint32_t TMTS  : 16; /*!< [15..0] TX Message Buffer Timestamp Field                                 */
1068             uint32_t             : 12;
1069             __IOM uint32_t TMDLC : 4;  /*!< [31..28] TX Message Buffer DLC Field                                      */
1070         } PTR_b;
1071     };
1072 
1073     union
1074     {
1075         __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register                  */
1076 
1077         struct
1078         {
1079             __IOM uint32_t TMESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
1080             __IOM uint32_t TMBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
1081             __IOM uint32_t TMFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
1082             uint32_t             : 5;
1083             __IOM uint32_t TMIFL : 2;  /*!< [9..8] TX Message Buffer Information Label Field                          */
1084             uint32_t             : 6;
1085             __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field                                  */
1086         } FDCTR_b;
1087     };
1088 
1089     union
1090     {
1091         __IOM uint8_t DF[64];          /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers                     */
1092 
1093         struct
1094         {
1095             __IOM uint8_t TMDB : 8;    /*!< [7..0] TX Message Buffer Data Byte                                        */
1096         } DF_b[64];
1097     };
1098     __IM uint32_t RESERVED[13];
1099 } R_CANFD_CFDTM_Type;                  /*!< Size = 128 (0x80)                                                         */
1100 
1101 /**
1102  * @brief R_CANFDL_CFDC [CFDC] (Channel Control/Status)
1103  */
1104 typedef struct
1105 {
1106     union
1107     {
1108         __IOM uint32_t NCFG;            /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register             */
1109 
1110         struct
1111         {
1112             __IOM uint32_t NBRP   : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler                                */
1113             __IOM uint32_t NSJW   : 7;  /*!< [16..10] Resynchronization Jump Width                                     */
1114             __IOM uint32_t NTSEG1 : 8;  /*!< [24..17] Timing Segment 1                                                 */
1115             __IOM uint32_t NTSEG2 : 7;  /*!< [31..25] Timing Segment 2                                                 */
1116         } NCFG_b;
1117     };
1118 
1119     union
1120     {
1121         __IOM uint32_t CTR;             /*!< (@ 0x00000004) Channel Control Registers                                  */
1122 
1123         struct
1124         {
1125             __IOM uint32_t CHMDC   : 2; /*!< [1..0] Channel Mode Control                                               */
1126             __IOM uint32_t CSLPR   : 1; /*!< [2..2] Channel Sleep Request                                              */
1127             __IOM uint32_t RTBO    : 1; /*!< [3..3] Return from Bus-Off                                                */
1128             uint32_t               : 4;
1129             __IOM uint32_t BEIE    : 1; /*!< [8..8] Bus Error Interrupt Enable                                         */
1130             __IOM uint32_t EWIE    : 1; /*!< [9..9] Error Warning Interrupt Enable                                     */
1131             __IOM uint32_t EPIE    : 1; /*!< [10..10] Error Passive Interrupt Enable                                   */
1132             __IOM uint32_t BOEIE   : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable                                   */
1133             __IOM uint32_t BORIE   : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable                                */
1134             __IOM uint32_t OLIE    : 1; /*!< [13..13] Overload Interrupt Enable                                        */
1135             __IOM uint32_t BLIE    : 1; /*!< [14..14] Bus Lock Interrupt Enable                                        */
1136             __IOM uint32_t ALIE    : 1; /*!< [15..15] Arbitration Lost Interrupt Enable                                */
1137             __IOM uint32_t TAIE    : 1; /*!< [16..16] Transmission abort Interrupt Enable                              */
1138             __IOM uint32_t EOCOIE  : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable               */
1139             __IOM uint32_t SOCOIE  : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable          */
1140             __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt
1141                                          *   enable                                                                    */
1142             uint32_t            : 1;
1143             __IOM uint32_t BOM  : 2;    /*!< [22..21] Channel Bus-Off Mode                                             */
1144             __IOM uint32_t ERRD : 1;    /*!< [23..23] Channel Error Display                                            */
1145             __IOM uint32_t CTME : 1;    /*!< [24..24] Channel Test Mode Enable                                         */
1146             __IOM uint32_t CTMS : 2;    /*!< [26..25] Channel Test Mode Select                                         */
1147             uint32_t            : 3;
1148             __IOM uint32_t CRCT : 1;    /*!< [30..30] CRC Error Test                                                   */
1149             __IOM uint32_t ROM  : 1;    /*!< [31..31] Restricted Operation Mode                                        */
1150         } CTR_b;
1151     };
1152 
1153     union
1154     {
1155         __IOM uint32_t STS;             /*!< (@ 0x00000008) Channel Status Registers                                   */
1156 
1157         struct
1158         {
1159             __IM uint32_t  CRSTSTS : 1; /*!< [0..0] Channel RESET Status                                               */
1160             __IM uint32_t  CHLTSTS : 1; /*!< [1..1] Channel HALT Status                                                */
1161             __IM uint32_t  CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status                                               */
1162             __IM uint32_t  EPSTS   : 1; /*!< [3..3] Channel Error Passive Status                                       */
1163             __IM uint32_t  BOSTS   : 1; /*!< [4..4] Channel Bus-Off Status                                             */
1164             __IM uint32_t  TRMSTS  : 1; /*!< [5..5] Channel Transmit Status                                            */
1165             __IM uint32_t  RECSTS  : 1; /*!< [6..6] Channel Receive Status                                             */
1166             __IM uint32_t  COMSTS  : 1; /*!< [7..7] Channel Communication Status                                       */
1167             __IOM uint32_t ESIF    : 1; /*!< [8..8] Error State Indication Flag                                        */
1168             uint32_t               : 7;
1169             __IM uint32_t  REC     : 8; /*!< [23..16] Reception Error Count                                            */
1170             __IOM uint32_t TEC     : 8; /*!< [31..24] Transmission Error Count                                         */
1171         } STS_b;
1172     };
1173 
1174     union
1175     {
1176         __IOM uint32_t ERFL;           /*!< (@ 0x0000000C) Channel Error Flag Registers                               */
1177 
1178         struct
1179         {
1180             __IOM uint32_t BEF   : 1;  /*!< [0..0] Bus Error Flag                                                     */
1181             __IOM uint32_t EWF   : 1;  /*!< [1..1] Error Warning Flag                                                 */
1182             __IOM uint32_t EPF   : 1;  /*!< [2..2] Error Passive Flag                                                 */
1183             __IOM uint32_t BOEF  : 1;  /*!< [3..3] Bus-Off Entry Flag                                                 */
1184             __IOM uint32_t BORF  : 1;  /*!< [4..4] Bus-Off Recovery Flag                                              */
1185             __IOM uint32_t OVLF  : 1;  /*!< [5..5] Overload Flag                                                      */
1186             __IOM uint32_t BLF   : 1;  /*!< [6..6] Bus Lock Flag                                                      */
1187             __IOM uint32_t ALF   : 1;  /*!< [7..7] Arbitration Lost Flag                                              */
1188             __IOM uint32_t SERR  : 1;  /*!< [8..8] Stuff Error                                                        */
1189             __IOM uint32_t FERR  : 1;  /*!< [9..9] Form Error                                                         */
1190             __IOM uint32_t AERR  : 1;  /*!< [10..10] Acknowledge Error                                                */
1191             __IOM uint32_t CERR  : 1;  /*!< [11..11] CRC Error                                                        */
1192             __IOM uint32_t B1ERR : 1;  /*!< [12..12] Bit 1 Error                                                      */
1193             __IOM uint32_t B0ERR : 1;  /*!< [13..13] Bit 0 Error                                                      */
1194             __IOM uint32_t ADERR : 1;  /*!< [14..14] Acknowledge Delimiter Error                                      */
1195             uint32_t             : 1;
1196             __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value                                               */
1197             uint32_t             : 1;
1198         } ERFL_b;
1199     };
1200 } R_CANFDL_CFDC_Type;                  /*!< Size = 16 (0x10)                                                          */
1201 
1202 /**
1203  * @brief R_CANFDL_CFDC2 [CFDC2] (Channel Configuration Registers)
1204  */
1205 typedef struct
1206 {
1207     union
1208     {
1209         __IOM uint32_t DCFG;           /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register                */
1210 
1211         struct
1212         {
1213             __IOM uint32_t DBRP   : 8; /*!< [7..0] Channel Data Baud Rate Prescaler                                   */
1214             __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1                                                  */
1215             uint32_t              : 3;
1216             __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2                                                 */
1217             uint32_t              : 4;
1218             __IOM uint32_t DSJW   : 4; /*!< [27..24] Resynchronization Jump Width                                     */
1219             uint32_t              : 4;
1220         } DCFG_b;
1221     };
1222 
1223     union
1224     {
1225         __IOM uint32_t FDCFG;          /*!< (@ 0x00000004) Channel CAN-FD Configuration Register                      */
1226 
1227         struct
1228         {
1229             __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration                             */
1230             uint32_t              : 5;
1231             __IOM uint32_t TDCOC  : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration                */
1232             __IOM uint32_t TDCE   : 1; /*!< [9..9] Transceiver Delay Compensation Enable                              */
1233             __IOM uint32_t ESIC   : 1; /*!< [10..10] Error State Indication Configuration                             */
1234             uint32_t              : 5;
1235             __IOM uint32_t TDCO   : 8; /*!< [23..16] Transceiver Delay Compensation Offset                            */
1236             uint32_t              : 4;
1237             __IOM uint32_t FDOE   : 1; /*!< [28..28] FD only enable                                                   */
1238             __IOM uint32_t REFE   : 1; /*!< [29..29] RX edge filter enable                                            */
1239             __IOM uint32_t CLOE   : 1; /*!< [30..30] Classical CAN only enable                                        */
1240             uint32_t              : 1;
1241         } FDCFG_b;
1242     };
1243 
1244     union
1245     {
1246         __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) Channel CAN-FD Control Register                            */
1247 
1248         struct
1249         {
1250             __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear                                     */
1251             __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear                                */
1252             uint32_t              : 30;
1253         } FDCTR_b;
1254     };
1255 
1256     union
1257     {
1258         __IOM uint32_t FDSTS;          /*!< (@ 0x0000000C) Channel CAN-FD Status Register                             */
1259 
1260         struct
1261         {
1262             __IM uint32_t  TDCR  : 8;  /*!< [7..0] Transceiver Delay Compensation Result                              */
1263             __IOM uint32_t EOCO  : 1;  /*!< [8..8] Error occurrence counter overflow                                  */
1264             __IOM uint32_t SOCO  : 1;  /*!< [9..9] Successful occurrence counter overflow                             */
1265             uint32_t             : 5;
1266             __IOM uint32_t TDCVF : 1;  /*!< [15..15] Transceiver Delay Compensation Violation Flag                    */
1267             __IM uint32_t  EOC   : 8;  /*!< [23..16] Error occurrence counter register                                */
1268             __IM uint32_t  SOC   : 8;  /*!< [31..24] Successful occurrence counter register                           */
1269         } FDSTS_b;
1270     };
1271 
1272     union
1273     {
1274         __IOM uint32_t FDCRC;          /*!< (@ 0x00000010) Channel CAN-FD CRC Register                                */
1275 
1276         struct
1277         {
1278             __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value                                                */
1279             uint32_t             : 3;
1280             __IM uint32_t SCNT   : 4;  /*!< [27..24] Stuff bit count                                                  */
1281             uint32_t             : 4;
1282         } FDCRC_b;
1283     };
1284     __IM uint32_t RESERVED[3];
1285 } R_CANFDL_CFDC2_Type;                 /*!< Size = 32 (0x20)                                                          */
1286 
1287 /**
1288  * @brief R_CANFDL_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers)
1289  */
1290 typedef struct
1291 {
1292     union
1293     {
1294         __IOM uint32_t ID;               /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers                 */
1295 
1296         struct
1297         {
1298             __IOM uint32_t GAFLID  : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field                      */
1299             __IOM uint32_t GAFLLB  : 1;  /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration       */
1300             __IOM uint32_t GAFLRTR : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Field                    */
1301             __IOM uint32_t GAFLIDE : 1;  /*!< [31..31] Global Acceptance Filter List Entry IDE Field                    */
1302         } ID_b;
1303     };
1304 
1305     union
1306     {
1307         __IOM uint32_t M;                 /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers               */
1308 
1309         struct
1310         {
1311             __IOM uint32_t GAFLIDM  : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field                       */
1312             __IOM uint32_t GAFLIFL1 : 1;  /*!< [29..29] Global Acceptance Filter List Information Label 1                */
1313             __IOM uint32_t GAFLRTRM : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Mask                     */
1314             __IOM uint32_t GAFLIDEM : 1;  /*!< [31..31] Global Acceptance Filter List IDE Mask                           */
1315         } M_b;
1316     };
1317 
1318     union
1319     {
1320         __IOM uint32_t P0;               /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers          */
1321 
1322         struct
1323         {
1324             __IOM uint32_t GAFLDLC  : 4; /*!< [3..0] Global Acceptance Filter List DLC Field                            */
1325             uint32_t                : 3;
1326             __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0                  */
1327             __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction
1328                                           *   Pointer                                                                   */
1329             uint32_t               : 2;
1330             __IOM uint32_t GAFLRMV : 1;  /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid            */
1331             __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field                      */
1332         } P0_b;
1333     };
1334 
1335     union
1336     {
1337         __IOM uint32_t P1;              /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers          */
1338 
1339         struct
1340         {
1341             __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer               */
1342             uint32_t               : 23;
1343         } P1_b;
1344     };
1345 } R_CANFDL_CFDGAFL_Type;                /*!< Size = 16 (0x10)                                                          */
1346 
1347 /**
1348  * @brief R_CANFDL_CFDTHL [CFDTHL] (Channel TX History List)
1349  */
1350 typedef struct
1351 {
1352     union
1353     {
1354         __IM uint32_t ACC0;            /*!< (@ 0x00000000) Channel TX History List Access Registers 0                 */
1355 
1356         struct
1357         {
1358             __IM uint32_t BT   : 3;    /*!< [2..0] Buffer Type                                                        */
1359             __IM uint32_t BN   : 7;    /*!< [9..3] Buffer No.                                                         */
1360             uint32_t           : 6;
1361             __IM uint32_t TMTS : 16;   /*!< [31..16] Transmit Timestamp                                               */
1362         } ACC0_b;
1363     };
1364 
1365     union
1366     {
1367         __IOM uint32_t ACC1;           /*!< (@ 0x00000004) Channel TX History List Access Registers 1                 */
1368 
1369         struct
1370         {
1371             __IM uint32_t TID  : 16;   /*!< [15..0] Transmit ID                                                       */
1372             __IM uint32_t TIFL : 2;    /*!< [17..16] Transmit Information Label                                       */
1373             uint32_t           : 14;
1374         } ACC1_b;
1375     };
1376 } R_CANFDL_CFDTHL_Type;                /*!< Size = 8 (0x8)                                                            */
1377 
1378 /**
1379  * @brief R_CANFDL_CFDRF [CFDRF] (RX FIFO Access Registers)
1380  */
1381 typedef struct
1382 {
1383     union
1384     {
1385         __IM uint32_t ID;              /*!< (@ 0x00000000) RX FIFO Access ID Register                                 */
1386 
1387         struct
1388         {
1389             __IM uint32_t RFID  : 29;  /*!< [28..0] RX FIFO Buffer ID Field                                           */
1390             uint32_t            : 1;
1391             __IM uint32_t RFRTR : 1;   /*!< [30..30] RX FIFO Buffer RTR Frame                                         */
1392             __IM uint32_t RFIDE : 1;   /*!< [31..31] RX FIFO Buffer IDE Bit                                           */
1393         } ID_b;
1394     };
1395 
1396     union
1397     {
1398         __IM uint32_t PTR;             /*!< (@ 0x00000004) RX FIFO Access Pointer Register                            */
1399 
1400         struct
1401         {
1402             __IM uint32_t RFTS  : 16;  /*!< [15..0] RX FIFO Timestamp Field                                           */
1403             uint32_t            : 12;
1404             __IM uint32_t RFDLC : 4;   /*!< [31..28] RX FIFO Buffer DLC Field                                         */
1405         } PTR_b;
1406     };
1407 
1408     union
1409     {
1410         __IM uint32_t FDSTS;           /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register                      */
1411 
1412         struct
1413         {
1414             __IM uint32_t RFESI : 1;   /*!< [0..0] Error State Indicator bit                                          */
1415             __IM uint32_t RFBRS : 1;   /*!< [1..1] Bit Rate Switch bit                                                */
1416             __IM uint32_t RFFDF : 1;   /*!< [2..2] CAN FD Format bit                                                  */
1417             uint32_t            : 5;
1418             __IM uint32_t RFIFL : 2;   /*!< [9..8] RX FIFO Buffer Information Label Field                             */
1419             uint32_t            : 6;
1420             __IM uint32_t RFPTR : 16;  /*!< [31..16] RX FIFO Buffer Pointer Field                                     */
1421         } FDSTS_b;
1422     };
1423 
1424     union
1425     {
1426         __IM uint8_t DF[64];           /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers                        */
1427 
1428         struct
1429         {
1430             __IM uint8_t RFDB : 8;     /*!< [7..0] RX FIFO Buffer Data Byte                                           */
1431         } DF_b[64];
1432     };
1433 } R_CANFDL_CFDRF_Type;                 /*!< Size = 76 (0x4c)                                                          */
1434 
1435 /**
1436  * @brief R_CANFDL_CFDCF [CFDCF] (Common FIFO Access Registers)
1437  */
1438 typedef struct
1439 {
1440     union
1441     {
1442         __IOM uint32_t ID;             /*!< (@ 0x00000000) Common FIFO Access ID Register                             */
1443 
1444         struct
1445         {
1446             __IOM uint32_t CFID  : 29; /*!< [28..0] Common FIFO Buffer ID Field                                       */
1447             uint32_t             : 1;
1448             __IOM uint32_t CFRTR : 1;  /*!< [30..30] Common FIFO Buffer RTR Frame                                     */
1449             __IOM uint32_t CFIDE : 1;  /*!< [31..31] Common FIFO Buffer IDE Bit                                       */
1450         } ID_b;
1451     };
1452 
1453     union
1454     {
1455         __IOM uint32_t PTR;            /*!< (@ 0x00000004) Common FIFO Access Pointer Register                        */
1456 
1457         struct
1458         {
1459             __IOM uint32_t CFTS  : 16; /*!< [15..0] Common FIFO Timestamp Field                                       */
1460             uint32_t             : 12;
1461             __IOM uint32_t CFDLC : 4;  /*!< [31..28] Common FIFO Buffer DLC Field                                     */
1462         } PTR_b;
1463     };
1464 
1465     union
1466     {
1467         __IOM uint32_t FDSTS;          /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register                  */
1468 
1469         struct
1470         {
1471             __IOM uint32_t CFESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
1472             __IOM uint32_t CFBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
1473             __IOM uint32_t CFFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
1474             uint32_t             : 5;
1475             __IOM uint32_t CFIFL : 2;  /*!< [9..8] Common FIFO Buffer Information Label Field                         */
1476             uint32_t             : 6;
1477             __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field                                 */
1478         } FDSTS_b;
1479     };
1480 
1481     union
1482     {
1483         __IOM uint8_t DF[64];          /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers                    */
1484 
1485         struct
1486         {
1487             __IOM uint8_t CFDB : 8;    /*!< [7..0] Common FIFO Buffer Data Byte                                       */
1488         } DF_b[64];
1489     };
1490 } R_CANFDL_CFDCF_Type;                 /*!< Size = 76 (0x4c)                                                          */
1491 
1492 /**
1493  * @brief R_CANFDL_CFDTM [CFDTM] (TX Message Buffer Access Registers)
1494  */
1495 typedef struct
1496 {
1497     union
1498     {
1499         __IOM uint32_t ID;             /*!< (@ 0x00000000) TX Message Buffer ID Register                              */
1500 
1501         struct
1502         {
1503             __IOM uint32_t TMID  : 29; /*!< [28..0] TX Message Buffer ID Field                                        */
1504             uint32_t             : 1;
1505             __IOM uint32_t TMRTR : 1;  /*!< [30..30] TX Message Buffer RTR Frame                                      */
1506             __IOM uint32_t TMIDE : 1;  /*!< [31..31] TX Message Buffer IDE Bit                                        */
1507         } ID_b;
1508     };
1509 
1510     union
1511     {
1512         __IOM uint32_t PTR;            /*!< (@ 0x00000004) TX Message Buffer Pointer Register                         */
1513 
1514         struct
1515         {
1516             __IOM uint32_t TMTS  : 16; /*!< [15..0] TX Message Buffer Timestamp Field                                 */
1517             uint32_t             : 12;
1518             __IOM uint32_t TMDLC : 4;  /*!< [31..28] TX Message Buffer DLC Field                                      */
1519         } PTR_b;
1520     };
1521 
1522     union
1523     {
1524         __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register                  */
1525 
1526         struct
1527         {
1528             __IOM uint32_t TMESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
1529             __IOM uint32_t TMBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
1530             __IOM uint32_t TMFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
1531             uint32_t             : 5;
1532             __IOM uint32_t TMIFL : 2;  /*!< [9..8] TX Message Buffer Information Label Field                          */
1533             uint32_t             : 6;
1534             __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field                                  */
1535         } FDCTR_b;
1536     };
1537 
1538     union
1539     {
1540         __IOM uint8_t DF[64];          /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers                     */
1541 
1542         struct
1543         {
1544             __IOM uint8_t TMDB : 8;    /*!< [7..0] TX Message Buffer Data Byte                                        */
1545         } DF_b[64];
1546     };
1547 } R_CANFDL_CFDTM_Type;                 /*!< Size = 76 (0x4c)                                                          */
1548 
1549 /**
1550  * @brief R_CANFDL_CFDRMC_RM [RM] (RX Message Buffer Access Registers)
1551  */
1552 typedef struct
1553 {
1554     union
1555     {
1556         __IM uint32_t ID;              /*!< (@ 0x00000000) RX Message Buffer ID Register                              */
1557 
1558         struct
1559         {
1560             __IM uint32_t RMID  : 29;  /*!< [28..0] RX Message Buffer ID Field                                        */
1561             uint32_t            : 1;
1562             __IM uint32_t RMRTR : 1;   /*!< [30..30] RX Message Buffer RTR Frame                                      */
1563             __IM uint32_t RMIDE : 1;   /*!< [31..31] RX Message Buffer IDE Bit                                        */
1564         } ID_b;
1565     };
1566 
1567     union
1568     {
1569         __IM uint32_t PTR;             /*!< (@ 0x00000004) RX Message Buffer Pointer Register                         */
1570 
1571         struct
1572         {
1573             __IM uint32_t RMTS  : 16;  /*!< [15..0] RX Message Buffer Timestamp Field                                 */
1574             uint32_t            : 12;
1575             __IM uint32_t RMDLC : 4;   /*!< [31..28] RX Message Buffer DLC Field                                      */
1576         } PTR_b;
1577     };
1578 
1579     union
1580     {
1581         __IM uint32_t FDSTS;           /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register                   */
1582 
1583         struct
1584         {
1585             __IM uint32_t RMESI : 1;   /*!< [0..0] Error State Indicator bit                                          */
1586             __IM uint32_t RMBRS : 1;   /*!< [1..1] Bit Rate Switch bit                                                */
1587             __IM uint32_t RMFDF : 1;   /*!< [2..2] CAN FD Format bit                                                  */
1588             uint32_t            : 5;
1589             __IM uint32_t RMIFL : 2;   /*!< [9..8] RX Message Buffer Information Label Field                          */
1590             uint32_t            : 6;
1591             __IM uint32_t RMPTR : 16;  /*!< [31..16] RX Message Buffer Pointer Field                                  */
1592         } FDSTS_b;
1593     };
1594 
1595     union
1596     {
1597         __IM uint8_t DF[64];           /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers                     */
1598 
1599         struct
1600         {
1601             __IM uint8_t RMDB : 8;     /*!< [7..0] RX Message Buffer Data Byte                                        */
1602         } DF_b[64];
1603     };
1604 } R_CANFDL_CFDRMC_RM_Type;             /*!< Size = 76 (0x4c)                                                          */
1605 
1606 /**
1607  * @brief R_CANFDL_CFDRMC [CFDRMC] (RX Message Buffer Access Clusters)
1608  */
1609 typedef struct
1610 {
1611     __IOM R_CANFDL_CFDRMC_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers                         */
1612     __IM uint32_t                 RESERVED[104];
1613 } R_CANFDL_CFDRMC_Type;                  /*!< Size = 1024 (0x400)                                                       */
1614 
1615 /**
1616  * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register)
1617  */
1618 typedef struct
1619 {
1620     union
1621     {
1622         __IOM uint8_t BY;              /*!< (@ 0x00000000) Event Link Software Event Generation Register              */
1623 
1624         struct
1625         {
1626             __OM uint8_t SEG : 1;      /*!< [0..0] Software Event Generation                                          */
1627             uint8_t          : 5;
1628             __IOM uint8_t WE : 1;      /*!< [6..6] SEG Bit Write Enable                                               */
1629             __OM uint8_t  WI : 1;      /*!< [7..7] ELSEGR Register Write Disable                                      */
1630         } BY_b;
1631     };
1632  #if (2U == BSP_FEATURE_ELC_VERSION)
1633     __IM uint8_t RESERVED[3];
1634  #else
1635     __IM uint8_t RESERVED;
1636  #endif
1637 } R_ELC_ELSEGR_Type;                   /*!< Size = 2 (0x2)                                                            */
1638 
1639 /**
1640  * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22])
1641  */
1642 typedef struct
1643 {
1644     union
1645     {
1646         __IOM uint16_t HA;             /*!< (@ 0x00000000) Event Link Setting Register                                */
1647 
1648         struct
1649         {
1650             __IOM uint16_t ELS : 9;    /*!< [8..0] Event Link Select                                                  */
1651             uint16_t           : 7;
1652         } HA_b;
1653     };
1654     __IM uint16_t RESERVED;
1655 } R_ELC_ELSR_Type;                     /*!< Size = 4 (0x4)                                                            */
1656 
1657 /**
1658  * @brief R_ETHERC_EPTPC_COMMON_TM [TM] (Timer Setting Registers)
1659  */
1660 typedef struct
1661 {
1662     union
1663     {
1664         __IOM uint32_t STTRU;            /*!< (@ 0x00000000) Timer Start Time Setting Register                          */
1665 
1666         struct
1667         {
1668             __IOM uint32_t TMSTTRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
1669                                           *   bits of the start time of the pulse output timer in nanoseconds.          */
1670         } STTRU_b;
1671     };
1672 
1673     union
1674     {
1675         __IOM uint32_t STTRL;            /*!< (@ 0x00000004) Timer Start Time Setting Register                          */
1676 
1677         struct
1678         {
1679             __IOM uint32_t TMSTTRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
1680                                           *   of the start time of the pulse output timer in nanoseconds.               */
1681         } STTRL_b;
1682     };
1683 
1684     union
1685     {
1686         __IOM uint32_t CYCR;            /*!< (@ 0x00000008) Timer Cycle Setting Registers                              */
1687 
1688         struct
1689         {
1690             __IOM uint32_t TMCYCR : 30; /*!< [29..0] These bits set the cycle of the pulse output timer in
1691                                          *   nanoseconds. Set a value that is equivalent to at least
1692                                          *   four cycles of the STCA clock.                                            */
1693             uint32_t : 2;
1694         } CYCR_b;
1695     };
1696 
1697     union
1698     {
1699         __IOM uint32_t PLSR;            /*!< (@ 0x0000000C) Timer Pulse Width Setting Register                         */
1700 
1701         struct
1702         {
1703             __IOM uint32_t TMPLSR : 29; /*!< [28..0] These bits set the width at high level of the pulse
1704                                          *   signal from the timer in nanoseconds. Set a value that
1705                                          *   is equivalent to at least two cycles of the STCA clock.                   */
1706             uint32_t : 3;
1707         } PLSR_b;
1708     };
1709 } R_ETHERC_EPTPC_COMMON_TM_Type;        /*!< Size = 16 (0x10)                                                          */
1710 
1711 /**
1712  * @brief R_ETHERC_EPTPC_COMMON_PR [PR] (Local MAC Address Registers)
1713  */
1714 typedef struct
1715 {
1716     union
1717     {
1718         __IOM uint32_t MACRU;            /*!< (@ 0x00000000) Channel Local MAC Address Register                         */
1719 
1720         struct
1721         {
1722             __IOM uint32_t PRMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24
1723                                           *   bits of the local MAC address for Ethernet port 0.                        */
1724             uint32_t : 8;
1725         } MACRU_b;
1726     };
1727 
1728     union
1729     {
1730         __IOM uint32_t MACRL;            /*!< (@ 0x00000004) Channel Local MAC Address Register                         */
1731 
1732         struct
1733         {
1734             __IOM uint32_t PRMACRL : 24; /*!< [23..0] These bits hold the setting for the higher-order 24
1735                                           *   bits of the local MAC address for Ethernet port 0.                        */
1736             uint32_t : 8;
1737         } MACRL_b;
1738     };
1739 } R_ETHERC_EPTPC_COMMON_PR_Type;         /*!< Size = 8 (0x8)                                                            */
1740 
1741 /**
1742  * @brief R_GLCDC_BG [BG] (Background Registers)
1743  */
1744 typedef struct
1745 {
1746     union
1747     {
1748         __IOM uint32_t EN;             /*!< (@ 0x00000000) Background Plane Setting Operation Control Register        */
1749 
1750         struct
1751         {
1752             __IOM uint32_t EN  : 1;    /*!< [0..0] Background plane generation module operation enable                */
1753             uint32_t           : 7;
1754             __IOM uint32_t VEN : 1;    /*!< [8..8] Control of LCDC internal register value reflection to
1755                                         *   internal operations                                                       */
1756             uint32_t             : 7;
1757             __IOM uint32_t SWRST : 1;  /*!< [16..16] Entire module SW reset control                                   */
1758             uint32_t             : 15;
1759         } EN_b;
1760     };
1761 
1762     union
1763     {
1764         __IOM uint32_t PERI;           /*!< (@ 0x00000004) Background Plane Setting Free-Running Period
1765                                         *                  Register                                                   */
1766 
1767         struct
1768         {
1769             __IOM uint32_t FH : 11;    /*!< [10..0] Background plane horizontal synchronization signal period
1770                                         *   on the basis of pixel clock (PXCLK).                                      */
1771             uint32_t          : 5;
1772             __IOM uint32_t FV : 11;    /*!< [26..16] Background plane vertical synchronization signal period
1773                                         *   on the basis of line.                                                     */
1774             uint32_t : 5;
1775         } PERI_b;
1776     };
1777 
1778     union
1779     {
1780         __IOM uint32_t SYNC;           /*!< (@ 0x00000008) Background Plane Setting Synchronization Position
1781                                         *                  Register                                                   */
1782 
1783         struct
1784         {
1785             __IOM uint32_t HP : 4;     /*!< [3..0] Background plane horizontal synchronization signal assertion
1786                                         *   position on the basis of pixel clock (PXCLK).                             */
1787             uint32_t          : 12;
1788             __IOM uint32_t VP : 4;     /*!< [19..16] Background plane vertical synchronization signal assertion
1789                                         *   position on the basis of line.                                            */
1790             uint32_t : 12;
1791         } SYNC_b;
1792     };
1793 
1794     union
1795     {
1796         __IOM uint32_t VSIZE;          /*!< (@ 0x0000000C) Background Plane Setting Full Image Vertical
1797                                         *                  Size Register                                              */
1798 
1799         struct
1800         {
1801             __IOM uint32_t VW : 11;    /*!< [10..0] Background plane vertical valid pixel width on the basis
1802                                         *   of line                                                                   */
1803             uint32_t          : 5;
1804             __IOM uint32_t VP : 11;    /*!< [26..16] Background plane vertical valid pixel start position
1805                                         *   on the basis of line                                                      */
1806             uint32_t : 5;
1807         } VSIZE_b;
1808     };
1809 
1810     union
1811     {
1812         __IOM uint32_t HSIZE;          /*!< (@ 0x00000010) Background Plane Setting Full Image Horizontal
1813                                         *                  Size Register                                              */
1814 
1815         struct
1816         {
1817             __IOM uint32_t HW : 11;    /*!< [10..0] Background plane horizontall valid pixel width on the
1818                                         *   basis of pixel clock (PXCLK) Note: When serial RGB is selected
1819                                         *   as the output format for the output control block, add
1820                                         *   two to the horizontal enable signal width and set the resulting
1821                                         *   value to this field.                                                      */
1822             uint32_t          : 5;
1823             __IOM uint32_t HP : 11;    /*!< [26..16] Background plane horizontal valid pixel start position
1824                                         *   on the basis of pixel clock (PXCLK).                                      */
1825             uint32_t : 5;
1826         } HSIZE_b;
1827     };
1828 
1829     union
1830     {
1831         __IOM uint32_t BGC;            /*!< (@ 0x00000014) Background Plane Setting Background Color Register         */
1832 
1833         struct
1834         {
1835             __IOM uint32_t B : 8;      /*!< [7..0] B value for background plane valid pixel area Unsigned;
1836                                         *   8-bit integer                                                             */
1837             __IOM uint32_t G : 8;      /*!< [15..8] G value for background plane valid pixel area Unsigned;
1838                                         *   8-bit integer                                                             */
1839             __IOM uint32_t R : 8;      /*!< [23..16] R value for background plane valid pixel area. Unsigned;
1840                                         *   8-bit integer.                                                            */
1841             uint32_t : 8;
1842         } BGC_b;
1843     };
1844 
1845     union
1846     {
1847         __IM uint32_t MON;             /*!< (@ 0x00000018) Background Plane Setting Status Monitor Register           */
1848 
1849         struct
1850         {
1851             __IM uint32_t EN  : 1;     /*!< [0..0] Background plane generation module operation state monitor.        */
1852             uint32_t          : 7;
1853             __IM uint32_t VEN : 1;     /*!< [8..8] Entire module internal operation reflection control signal
1854                                         *   monitor. The signal state for controlling reflection of
1855                                         *   the register values to the internal operations upon assertion
1856                                         *   of the vertical synchronization signal.                                   */
1857             uint32_t            : 7;
1858             __IM uint32_t SWRST : 1;   /*!< [16..16] Entire module SW reset state monitor.                            */
1859             uint32_t            : 15;
1860         } MON_b;
1861     };
1862 } R_GLCDC_BG_Type;                     /*!< Size = 28 (0x1c)                                                          */
1863 
1864 /**
1865  * @brief R_GLCDC_GR [GR] (Layer Registers)
1866  */
1867 typedef struct
1868 {
1869     union
1870     {
1871         __IOM uint32_t VEN;            /*!< (@ 0x00000000) Graphics Register Update Control Register                  */
1872 
1873         struct
1874         {
1875             __IOM uint32_t PVEN : 1;   /*!< [0..0] Control of graphics n module register value reflection
1876                                         *   to internal operations. Reflection of the register values
1877                                         *   to the internal operation at the assertion of the vertical
1878                                         *   synchronization signal (VS).                                              */
1879             uint32_t : 31;
1880         } VEN_b;
1881     };
1882 
1883     union
1884     {
1885         __IOM uint32_t FLMRD;          /*!< (@ 0x00000004) Graphics Frame Buffer Read Control Register                */
1886 
1887         struct
1888         {
1889             __IOM uint32_t RENB : 1;   /*!< [0..0] Graphics data (frame buffer data) read enable.                     */
1890             uint32_t            : 31;
1891         } FLMRD_b;
1892     };
1893 
1894     union
1895     {
1896         __IM uint32_t FLM1;            /*!< (@ 0x00000008) Graphics Frame Buffer Control Register 1                   */
1897 
1898         struct
1899         {
1900             __IM uint32_t BSTMD : 2;   /*!< [1..0] Burst transfer control for graphics data (frame buffer
1901                                         *   data) access                                                              */
1902             uint32_t : 30;
1903         } FLM1_b;
1904     };
1905 
1906     union
1907     {
1908         __IOM uint32_t FLM2;           /*!< (@ 0x0000000C) Graphics Frame Buffer Control Register 2                   */
1909 
1910         struct
1911         {
1912             __IOM uint32_t BASE : 32;  /*!< [31..0] Base address for accessing graphics data (frame buffer
1913                                         *   data) Set the head address in the frame buffer where graphics
1914                                         *   data is to be stored. GRn_FLM2.BASE[5:0] should be fixed
1915                                         *   to 0 during 64-byte burst transfer.                                       */
1916         } FLM2_b;
1917     };
1918 
1919     union
1920     {
1921         __IOM uint32_t FLM3;           /*!< (@ 0x00000010) Graphics Frame Buffer Control Register 3                   */
1922 
1923         struct
1924         {
1925             uint32_t             : 16;
1926             __IOM uint32_t LNOFF : 16; /*!< [31..16] Macro line offset address for accessing graphics data
1927                                         *   (frame buffer data) Signed; 16-bit integer                                */
1928         } FLM3_b;
1929     };
1930     __IM uint32_t RESERVED;
1931 
1932     union
1933     {
1934         __IOM uint32_t FLM5;             /*!< (@ 0x00000018) Graphics Frame Buffer Control Register 5                   */
1935 
1936         struct
1937         {
1938             __IOM uint32_t DATANUM : 16; /*!< [15..0] Number of data transfer times per line for accessing
1939                                           *   graphics data (frame buffer data), where one transfer is
1940                                           *   defined as 16-beat burst access (64-byte boundary)                        */
1941             __IOM uint32_t LNNUM : 11;   /*!< [26..16] Number of lines per frame for accessing graphics data
1942                                           *   (frame buffer data).                                                      */
1943             uint32_t : 5;
1944         } FLM5_b;
1945     };
1946 
1947     union
1948     {
1949         __IOM uint32_t FLM6;           /*!< (@ 0x0000001C) Graphics Frame Buffer Control Register 6                   */
1950 
1951         struct
1952         {
1953             uint32_t              : 28;
1954             __IOM uint32_t FORMAT : 3; /*!< [30..28] Data format for accessing graphics data (frame buffer
1955                                         *   data).                                                                    */
1956             uint32_t : 1;
1957         } FLM6_b;
1958     };
1959 
1960     union
1961     {
1962         __IOM uint32_t AB1;               /*!< (@ 0x00000020) Graphics Alpha Blending Control Register 1                 */
1963 
1964         struct
1965         {
1966             __IOM uint32_t DISPSEL   : 2; /*!< [1..0] Graphics display plane control.                                    */
1967             uint32_t                 : 2;
1968             __IOM uint32_t GRCDISPON : 1; /*!< [4..4] Graphics image area border display control.                        */
1969             uint32_t                 : 3;
1970             __IOM uint32_t ARCDISPON : 1; /*!< [8..8] Image area border display control for rectangular area
1971                                            *   alpha blending.                                                           */
1972             uint32_t             : 3;
1973             __IOM uint32_t ARCON : 1;     /*!< [12..12] Rectangular area alpha blending control.                         */
1974             uint32_t             : 19;
1975         } AB1_b;
1976     };
1977 
1978     union
1979     {
1980         __IOM uint32_t AB2;            /*!< (@ 0x00000024) Graphics Alpha Blending Control Register 2                 */
1981 
1982         struct
1983         {
1984             __IOM uint32_t GRCVW : 11; /*!< [10..0] Vertical width of graphics image area.                            */
1985             uint32_t             : 5;
1986             __IOM uint32_t GRCVS : 11; /*!< [26..16] Vertical start position of graphics image area.                  */
1987             uint32_t             : 5;
1988         } AB2_b;
1989     };
1990 
1991     union
1992     {
1993         __IOM uint32_t AB3;            /*!< (@ 0x00000028) Graphics Alpha Blending Control Register 3                 */
1994 
1995         struct
1996         {
1997             __IOM uint32_t GRCHW : 11; /*!< [10..0] Horizontal width of graphics image area.                          */
1998             uint32_t             : 5;
1999             __IOM uint32_t GRCHS : 11; /*!< [26..16] Horizontal start position of graphics image area.                */
2000             uint32_t             : 5;
2001         } AB3_b;
2002     };
2003 
2004     union
2005     {
2006         __IOM uint32_t AB4;            /*!< (@ 0x0000002C) Graphics Alpha Blending Control Register 4                 */
2007 
2008         struct
2009         {
2010             __IOM uint32_t ARCVW : 11; /*!< [10..0] Vertical width of rectangular area alpha blending image
2011                                         *   area.                                                                     */
2012             uint32_t             : 5;
2013             __IOM uint32_t ARCVS : 11; /*!< [26..16] Vertical start position of rectangular area alpha blending
2014                                         *   image area                                                                */
2015             uint32_t : 5;
2016         } AB4_b;
2017     };
2018 
2019     union
2020     {
2021         __IOM uint32_t AB5;            /*!< (@ 0x00000030) Graphics Alpha Blending Control Register 5                 */
2022 
2023         struct
2024         {
2025             __IOM uint32_t ARCHW : 11; /*!< [10..0] Horizontal width of rectangular area alpha blending
2026                                         *   image area.                                                               */
2027             uint32_t             : 5;
2028             __IOM uint32_t ARCHS : 11; /*!< [26..16] Horizontal start position of rectangular area alpha
2029                                         *   blending image area.                                                      */
2030             uint32_t : 5;
2031         } AB5_b;
2032     };
2033 
2034     union
2035     {
2036         __IOM uint32_t AB6;             /*!< (@ 0x00000034) Graphics Alpha Blending Control Register 6                 */
2037 
2038         struct
2039         {
2040             __IOM uint32_t ARCRATE : 8; /*!< [7..0] Frame rate for alpha blending in rectangular area.                 */
2041             uint32_t               : 8;
2042             __IOM uint32_t ARCCOEF : 9; /*!< [24..16] Alpha coefficient for alpha blending in rectangular
2043                                          *   area (-255 to 255). [8]: Sign (0: addition, 1: subtraction)
2044                                          *   [7:0]: Variation (absolute value)                                         */
2045             uint32_t : 7;
2046         } AB6_b;
2047     };
2048 
2049     union
2050     {
2051         __IOM uint32_t AB7;            /*!< (@ 0x00000038) Graphics Alpha Blending Control Register 7                 */
2052 
2053         struct
2054         {
2055             __IOM uint32_t CKON   : 1; /*!< [0..0] RGB-index chroma-key processing control.                           */
2056             uint32_t              : 15;
2057             __IOM uint32_t ARCDEF : 8; /*!< [23..16] Initial alpha value for alpha blending in rectangular
2058                                         *   area.                                                                     */
2059             uint32_t : 8;
2060         } AB7_b;
2061     };
2062 
2063     union
2064     {
2065         __IOM uint32_t AB8;            /*!< (@ 0x0000003C) Graphics Alpha Blending Control Register 8                 */
2066 
2067         struct
2068         {
2069             __IOM uint32_t CKKR : 8;   /*!< [7..0] R signal for RGB-index chroma-key processing Unsigned;
2070                                         *   8 bits.                                                                   */
2071             __IOM uint32_t CKKB : 8;   /*!< [15..8] B signal for RGB-index chroma-key processing Unsigned;
2072                                         *   8 bits.                                                                   */
2073             __IOM uint32_t CKKG : 8;   /*!< [23..16] G signal for RGB-index chroma-key processing Unsigned;
2074                                         *   8 bits.                                                                   */
2075             uint32_t : 8;
2076         } AB8_b;
2077     };
2078 
2079     union
2080     {
2081         __IOM uint32_t AB9;            /*!< (@ 0x00000040) Graphics Alpha Blending Control Register 9                 */
2082 
2083         struct
2084         {
2085             __IOM uint32_t CKR : 8;    /*!< [7..0] R value after RGB-index chroma-key processing replacement
2086                                         *   Unsigned; 8 bits.                                                         */
2087             __IOM uint32_t CKB : 8;    /*!< [15..8] B value after RGB-index chroma-key processing replacement
2088                                         *   Unsigned; 8 bits.                                                         */
2089             __IOM uint32_t CKG : 8;    /*!< [23..16] G value after RGB-index chroma-key processing replacement
2090                                         *   Unsigned; 8 bits.                                                         */
2091             __IOM uint32_t CKA : 8;    /*!< [31..24] A value after RGB-index chroma-key processing replacement.       */
2092         } AB9_b;
2093     };
2094     __IM uint32_t RESERVED1[2];
2095 
2096     union
2097     {
2098         __IOM uint32_t BASE;           /*!< (@ 0x0000004C) Graphics Background Color Control Register                 */
2099 
2100         struct
2101         {
2102             __IOM uint32_t R : 8;      /*!< [7..0] Background color R value Unsigned; 8 bits                          */
2103             __IOM uint32_t B : 8;      /*!< [15..8] Background color B value Unsigned; 8 bits                         */
2104             __IOM uint32_t G : 8;      /*!< [23..16] Background color G value Unsigned; 8 bits                        */
2105             uint32_t         : 8;
2106         } BASE_b;
2107     };
2108 
2109     union
2110     {
2111         __IOM uint32_t CLUTINT;        /*!< (@ 0x00000050) Graphics CLUT Table Interrupt Control Register             */
2112 
2113         struct
2114         {
2115             __IOM uint32_t LINE : 11;  /*!< [10..0] Number of detection lines                                         */
2116             uint32_t            : 5;
2117             __IOM uint32_t SEL  : 1;   /*!< [16..16] CLUT table control                                               */
2118             uint32_t            : 15;
2119         } CLUTINT_b;
2120     };
2121 
2122     union
2123     {
2124         __IM uint32_t MON;             /*!< (@ 0x00000054) Graphics Status Monitor Register                           */
2125 
2126         struct
2127         {
2128             __IM uint32_t ARCST   : 1; /*!< [0..0] Status monitor for alpha blending in rectangular area              */
2129             uint32_t              : 15;
2130             __IM uint32_t UNDFLST : 1; /*!< [16..16] Status monitor for underflow                                     */
2131             uint32_t              : 15;
2132         } MON_b;
2133     };
2134     __IM uint32_t RESERVED2[42];
2135 } R_GLCDC_GR_Type;                     /*!< Size = 256 (0x100)                                                        */
2136 
2137 /**
2138  * @brief R_GLCDC_GAM [GAM] (Gamma Settings)
2139  */
2140 typedef struct
2141 {
2142     union
2143     {
2144         __IOM uint32_t LATCH;          /*!< (@ 0x00000000) Gamma Register Update Control Register                     */
2145 
2146         struct
2147         {
2148             __IOM uint32_t VEN : 1;    /*!< [0..0] Control of gamma correction x module register value reflection
2149                                         *   to internal operations. The register values to be reflected
2150                                         *   to the internal operations at the assertion of the vertical
2151                                         *   synchronization signal (VS).                                              */
2152             uint32_t : 31;
2153         } LATCH_b;
2154     };
2155 
2156     union
2157     {
2158         __IOM uint32_t GAM_SW;         /*!< (@ 0x00000004) Gamma Correction Block Function Switch Register            */
2159 
2160         struct
2161         {
2162             __IOM uint32_t GAMON : 1;  /*!< [0..0] Gamma correction on/off control                                    */
2163             uint32_t             : 31;
2164         } GAM_SW_b;
2165     };
2166 
2167     union
2168     {
2169         __IOM uint32_t LUT[8];         /*!< (@ 0x00000008) Gamma Correction Block Table Setting Register              */
2170 
2171         struct
2172         {
2173             __IOM uint32_t _HIGH : 11; /*!< [10..0] Gain value of area 0. Unsigned 11-bit fixed point.                */
2174             uint32_t             : 5;
2175             __IOM uint32_t _LOW  : 11; /*!< [26..16] Gain value of area 0. Unsigned 11-bit fixed point.               */
2176             uint32_t             : 5;
2177         } LUT_b[8];
2178     };
2179 
2180     union
2181     {
2182         __IOM uint32_t AREA[5];        /*!< (@ 0x00000028) Gamma Correction Block Area Setting Register               */
2183 
2184         struct
2185         {
2186             __IOM uint32_t _HIGH : 10; /*!< [9..0] Start threshold of area 1 Unsigned 10-bit integer                  */
2187             __IOM uint32_t _MID  : 10; /*!< [19..10] Start threshold of area 1 Unsigned 10-bit integer                */
2188             __IOM uint32_t _LOW  : 10; /*!< [29..20] Start threshold of area 1 Unsigned 10-bit integer                */
2189             uint32_t             : 2;
2190         } AREA_b[5];
2191     };
2192     __IM uint32_t RESERVED;
2193 } R_GLCDC_GAM_Type;                    /*!< Size = 64 (0x40)                                                          */
2194 
2195 /**
2196  * @brief R_GLCDC_OUT [OUT] (Output Control Registers)
2197  */
2198 typedef struct
2199 {
2200     union
2201     {
2202         __IOM uint32_t VLATCH;         /*!< (@ 0x00000000) Output Control Block Register Update Control
2203                                         *                  Register                                                   */
2204 
2205         struct
2206         {
2207             __IOM uint32_t VEN : 1;    /*!< [0..0] Control of output control module register value reflection
2208                                         *   to internal operations. The register values to be reflected
2209                                         *   to the internal operations at the assertion of the vertical
2210                                         *   synchronization signal (VS).                                              */
2211             uint32_t : 31;
2212         } VLATCH_b;
2213     };
2214 
2215     union
2216     {
2217         __IOM uint32_t SET;              /*!< (@ 0x00000004) Output Control Block Output Interface Register             */
2218 
2219         struct
2220         {
2221             __IOM uint32_t PHASE    : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK)                  */
2222             uint32_t                : 2;
2223             __IOM uint32_t DIRSEL   : 1; /*!< [4..4] Invalid data position control in serial RGB format                 */
2224             uint32_t                : 3;
2225             __IOM uint32_t FRQSEL   : 2; /*!< [9..8] Clock frequency division control                                   */
2226             uint32_t                : 2;
2227             __IOM uint32_t FORMAT   : 2; /*!< [13..12] Output format select                                             */
2228             uint32_t                : 10;
2229             __IOM uint32_t SWAPON   : 1; /*!< [24..24] Pixel order control                                              */
2230             uint32_t                : 3;
2231             __IOM uint32_t ENDIANON : 1; /*!< [28..28] Bit endian change control                                        */
2232             uint32_t                : 3;
2233         } SET_b;
2234     };
2235 
2236     union
2237     {
2238         __IOM uint32_t BRIGHT1;        /*!< (@ 0x00000008) Output Control Block Brightness Correction Register
2239                                         *                  1                                                          */
2240 
2241         struct
2242         {
2243             __IOM uint32_t BRTG : 10;  /*!< [9..0] Brightness (DC) adjustment of G signal Unsigned; 10 bits;
2244                                         +512 with offset; integer                                                 */
2245             uint32_t : 22;
2246         } BRIGHT1_b;
2247     };
2248 
2249     union
2250     {
2251         __IOM uint32_t BRIGHT2;        /*!< (@ 0x0000000C) Output Control Block Brightness Correction Register
2252                                         *                  2                                                          */
2253 
2254         struct
2255         {
2256             __IOM uint32_t BRTR : 10;  /*!< [9..0] Brightness (DC) adjustment of R signal Unsigned; 10 bits;
2257                                         +512 with offset; integer                                                 */
2258             uint32_t            : 6;
2259             __IOM uint32_t BRTB : 10;  /*!< [25..16] Brightness (DC) adjustment of B signal Unsigned; 10
2260                                         *   bits; +512 with offset; integer                                           */
2261             uint32_t : 6;
2262         } BRIGHT2_b;
2263     };
2264 
2265     union
2266     {
2267         __IOM uint32_t CONTRAST;       /*!< (@ 0x00000010) Output Control Block Contrast Correction Register          */
2268 
2269         struct
2270         {
2271             __IOM uint32_t CONTR : 8;  /*!< [7..0] Contrast (GAIN) adjustment of R signal Unsigned; 8 bits
2272                                         *   fixed point                                                               */
2273             __IOM uint32_t CONTB : 8;  /*!< [15..8] Contrast (GAIN) adjustment of B signal Unsigned; 8 bits
2274                                         *   fixed point                                                               */
2275             __IOM uint32_t CONTG : 8;  /*!< [23..16] Contrast (GAIN) adjustment of G signal Unsigned; 8
2276                                         *   bits fixed point.                                                         */
2277             uint32_t : 8;
2278         } CONTRAST_b;
2279     };
2280 
2281     union
2282     {
2283         __IOM uint32_t PDTHA;          /*!< (@ 0x00000014) Output Control Block Panel Dither Correction
2284                                         *                  Register                                                   */
2285 
2286         struct
2287         {
2288             __IOM uint32_t PD : 2;     /*!< [1..0] Pattern value (D) of 2 x 2 pattern dither Unsigned 2-bit
2289                                         *   integer                                                                   */
2290             uint32_t          : 2;
2291             __IOM uint32_t PC : 2;     /*!< [5..4] Pattern value (C) of 2 x 2 pattern dither Unsigned 2-bit
2292                                         *   integer                                                                   */
2293             uint32_t          : 2;
2294             __IOM uint32_t PB : 2;     /*!< [9..8] Pattern value (B) of 2 x 2 pattern dither Unsigned 2-bit
2295                                         *   integer                                                                   */
2296             uint32_t          : 2;
2297             __IOM uint32_t PA : 2;     /*!< [13..12] Pattern value (A) of 2 x 2 pattern dither Unsigned
2298                                         *   2-bit integer                                                             */
2299             uint32_t            : 2;
2300             __IOM uint32_t FORM : 2;   /*!< [17..16] Output format select                                             */
2301             uint32_t            : 2;
2302             __IOM uint32_t SEL  : 2;   /*!< [21..20] Operation mode                                                   */
2303             uint32_t            : 10;
2304         } PDTHA_b;
2305     };
2306     __IM uint32_t RESERVED[3];
2307 
2308     union
2309     {
2310         __IOM uint32_t CLKPHASE;       /*!< (@ 0x00000024) Output Control Block Output Phase Control Register         */
2311 
2312         struct
2313         {
2314             uint32_t                 : 3;
2315             __IOM uint32_t TCON3EDGE : 1; /*!< [3..3] LCD_TCON3 Output Phase Control                                     */
2316             __IOM uint32_t TCON2EDGE : 1; /*!< [4..4] LCD_TCON2 Output Phase Control                                     */
2317             __IOM uint32_t TCON1EDGE : 1; /*!< [5..5] LCD_TCON1 Output Phase Control                                     */
2318             __IOM uint32_t TCON0EDGE : 1; /*!< [6..6] LCD_TCON0 Output Phase Control                                     */
2319             uint32_t                 : 1;
2320             __IOM uint32_t LCDEDGE   : 1; /*!< [8..8] LCD_DATA Output Phase Control                                      */
2321             uint32_t                 : 3;
2322             __IOM uint32_t FRONTGAM  : 1; /*!< [12..12] Correction control                                               */
2323             uint32_t                 : 19;
2324         } CLKPHASE_b;
2325     };
2326 } R_GLCDC_OUT_Type;                       /*!< Size = 40 (0x28)                                                          */
2327 
2328 /**
2329  * @brief R_GLCDC_TCON [TCON] (Timing Control Registers)
2330  */
2331 typedef struct
2332 {
2333     __IM uint32_t RESERVED;
2334 
2335     union
2336     {
2337         __IOM uint32_t TIM;             /*!< (@ 0x00000004) TCON Reference Timing Setting Register                     */
2338 
2339         struct
2340         {
2341             __IOM uint32_t OFFSET : 11; /*!< [10..0] Horizontal synchronization signal generation reference
2342                                          *   timing Sets the offset from the assertion of the internal
2343                                          *   horizontal synchronization signal in terms of pixels.                     */
2344             uint32_t            : 5;
2345             __IOM uint32_t HALF : 11;   /*!< [26..16] Vertical synchronization signal generation change timing
2346                                          *   Sets the delay from the assertion of the internal horizontal
2347                                          *   synchronization signal in terms of pixels.                                */
2348             uint32_t : 5;
2349         } TIM_b;
2350     };
2351 
2352     union
2353     {
2354         __IOM uint32_t STVA1;          /*!< (@ 0x00000008) TCON Vertical Timing Setting Register A1                   */
2355 
2356         struct
2357         {
2358             __IOM uint32_t VW : 11;    /*!< [10..0] STVx1 second change timing Sets the signal assertion
2359                                         *   width.                                                                    */
2360             uint32_t          : 5;
2361             __IOM uint32_t VS : 11;    /*!< [26..16] STVx1 first change timing                                        */
2362             uint32_t          : 5;
2363         } STVA1_b;
2364     };
2365 
2366     union
2367     {
2368         __IOM uint32_t STVA2;          /*!< (@ 0x0000000C) TCON Vertical Timing Setting Register A2                   */
2369 
2370         struct
2371         {
2372             __IOM uint32_t SEL : 3;    /*!< [2..0] Output signal select control for VSOUT (controlled by
2373                                         *   TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2
2374                                         *   register) pin                                                             */
2375             uint32_t           : 1;
2376             __IOM uint32_t INV : 1;    /*!< [4..4] STVx signal polarity inversion control                             */
2377             uint32_t           : 27;
2378         } STVA2_b;
2379     };
2380 
2381     union
2382     {
2383         __IOM uint32_t STVB1;          /*!< (@ 0x00000010) TCON Vertical Timing Setting Register B1                   */
2384 
2385         struct
2386         {
2387             __IOM uint32_t VW : 11;    /*!< [10..0] STVx1 second change timing Sets the signal assertion
2388                                         *   width.                                                                    */
2389             uint32_t          : 5;
2390             __IOM uint32_t VS : 11;    /*!< [26..16] STVx1 first change timing                                        */
2391             uint32_t          : 5;
2392         } STVB1_b;
2393     };
2394 
2395     union
2396     {
2397         __IOM uint32_t STVB2;          /*!< (@ 0x00000014) TCON Vertical Timing Setting Register B2                   */
2398 
2399         struct
2400         {
2401             __IOM uint32_t SEL : 3;    /*!< [2..0] Output signal select control for VSOUT (controlled by
2402                                         *   TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2
2403                                         *   register) pin                                                             */
2404             uint32_t           : 1;
2405             __IOM uint32_t INV : 1;    /*!< [4..4] STVx signal polarity inversion control                             */
2406             uint32_t           : 27;
2407         } STVB2_b;
2408     };
2409 
2410     union
2411     {
2412         __IOM uint32_t STHA1;          /*!< (@ 0x00000018) TCON Horizontal Timing Setting Register STHA1              */
2413 
2414         struct
2415         {
2416             __IOM uint32_t HW : 11;    /*!< [10..0] STHx1 second change timing. Sets the signal assertion
2417                                         *   width.                                                                    */
2418             uint32_t          : 5;
2419             __IOM uint32_t HS : 11;    /*!< [26..16] STHx1 first change timing                                        */
2420             uint32_t          : 5;
2421         } STHA1_b;
2422     };
2423 
2424     union
2425     {
2426         __IOM uint32_t STHA2;          /*!< (@ 0x0000001C) TCON Horizontal Timing Setting Register STHA2              */
2427 
2428         struct
2429         {
2430             __IOM uint32_t SEL : 3;    /*!< [2..0] Output signal select control for LCD_TCON2 (controlled
2431                                         *   by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2
2432                                         *   register) pin.                                                            */
2433             uint32_t             : 1;
2434             __IOM uint32_t INV   : 1;  /*!< [4..4] STVx signal polarity inversion control.                            */
2435             uint32_t             : 3;
2436             __IOM uint32_t HSSEL : 1;  /*!< [8..8] STHx signal generation reference timing control.                   */
2437             uint32_t             : 23;
2438         } STHA2_b;
2439     };
2440 
2441     union
2442     {
2443         __IOM uint32_t STHB1;          /*!< (@ 0x00000020) TCON Horizontal Timing Setting Register STHB1              */
2444 
2445         struct
2446         {
2447             __IOM uint32_t HW : 11;    /*!< [10..0] STHx1 second change timing. Sets the signal assertion
2448                                         *   width.                                                                    */
2449             uint32_t          : 5;
2450             __IOM uint32_t HS : 11;    /*!< [26..16] STHx1 first change timing                                        */
2451             uint32_t          : 5;
2452         } STHB1_b;
2453     };
2454 
2455     union
2456     {
2457         __IOM uint32_t STHB2;          /*!< (@ 0x00000024) TCON Horizontal Timing Setting Register STHB2              */
2458 
2459         struct
2460         {
2461             __IOM uint32_t SEL : 3;    /*!< [2..0] Output signal select control for LCD_TCON2 (controlled
2462                                         *   by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2
2463                                         *   register) pin.                                                            */
2464             uint32_t             : 1;
2465             __IOM uint32_t INV   : 1;  /*!< [4..4] STVx signal polarity inversion control.                            */
2466             uint32_t             : 3;
2467             __IOM uint32_t HSSEL : 1;  /*!< [8..8] STHx signal generation reference timing control.                   */
2468             uint32_t             : 23;
2469         } STHB2_b;
2470     };
2471 
2472     union
2473     {
2474         __IOM uint32_t DE;             /*!< (@ 0x00000028) TCON Data Enable Polarity Setting Register                 */
2475 
2476         struct
2477         {
2478             __IOM uint32_t INV : 1;    /*!< [0..0] DE signal polarity inversion control.                              */
2479             uint32_t           : 31;
2480         } DE_b;
2481     };
2482 } R_GLCDC_TCON_Type;                   /*!< Size = 44 (0x2c)                                                          */
2483 
2484 /**
2485  * @brief R_GLCDC_SYSCNT [SYSCNT] (GLCDC System Control Registers)
2486  */
2487 typedef struct
2488 {
2489     union
2490     {
2491         __IOM uint32_t DTCTEN;            /*!< (@ 0x00000000) System control block State Detection Control
2492                                            *                  Register                                                   */
2493 
2494         struct
2495         {
2496             __IOM uint32_t VPOSDTC   : 1; /*!< [0..0] Specified line detection control                                   */
2497             __IOM uint32_t L1UNDFDTC : 1; /*!< [1..1] Graphics 1 underflow detection control                             */
2498             __IOM uint32_t L2UNDFDTC : 1; /*!< [2..2] Graphics 2 underflow detection control                             */
2499             uint32_t                 : 29;
2500         } DTCTEN_b;
2501     };
2502 
2503     union
2504     {
2505         __IOM uint32_t INTEN;               /*!< (@ 0x00000004) System control block Interrupt Request Enable
2506                                              *                  Control Register                                           */
2507 
2508         struct
2509         {
2510             __IOM uint32_t VPOSINTEN   : 1; /*!< [0..0] Interrupt request signal GLCDC_VPOS enable control.                */
2511             __IOM uint32_t L1UNDFINTEN : 1; /*!< [1..1] Interrupt request signal GLCDC_L1UNDF enable control.              */
2512             __IOM uint32_t L2UNDFINTEN : 1; /*!< [2..2] Interrupt request signal GLCDC_L2UNDF enable control.              */
2513             uint32_t                   : 29;
2514         } INTEN_b;
2515     };
2516 
2517     union
2518     {
2519         __IOM uint32_t STCLR;             /*!< (@ 0x00000008) System control block Status Clear Register                 */
2520 
2521         struct
2522         {
2523             __IOM uint32_t VPOSCLR   : 1; /*!< [0..0] Graphics 2 specified line detection flag clear field               */
2524             __IOM uint32_t L1UNDFCLR : 1; /*!< [1..1] Graphics 1 underflow detection flag clear field                    */
2525             __IOM uint32_t L2UNDFCLR : 1; /*!< [2..2] Graphics 2 underflow detection flag clear field                    */
2526             uint32_t                 : 29;
2527         } STCLR_b;
2528     };
2529 
2530     union
2531     {
2532         __IM uint32_t STMON;           /*!< (@ 0x0000000C) System control block Status Monitor Register               */
2533 
2534         struct
2535         {
2536             __IM uint32_t VPOS   : 1;  /*!< [0..0] Graphics 2 specified line detection flag                           */
2537             __IM uint32_t L1UNDF : 1;  /*!< [1..1] Graphics 1 underflow detection flag                                */
2538             __IM uint32_t L2UNDF : 1;  /*!< [2..2] Graphics 2 underflow detection flag                                */
2539             uint32_t             : 29;
2540         } STMON_b;
2541     };
2542 
2543     union
2544     {
2545         __IOM uint32_t PANEL_CLK;      /*!< (@ 0x00000010) System control block Version and Panel Clock
2546                                         *                  Control Register                                           */
2547 
2548         struct
2549         {
2550             __IOM uint32_t DCDR : 6;   /*!< [5..0] Clock division ratio setting control Refer toTable 2.7.1
2551                                         *   for details about setting value. Note: Settings that are
2552                                         *   not listed in table 2.7.1 are prohibited.                                 */
2553             __IOM uint32_t CLKEN : 1;  /*!< [6..6] Panel clock output enable control Note: Before changing
2554                                         *   the PIXSEL,CLKSEL or DCDR bit, this bit must be set to
2555                                         *   0.                                                                        */
2556             uint32_t              : 1;
2557             __IOM uint32_t CLKSEL : 1; /*!< [8..8] Panel clock supply source select                                   */
2558             uint32_t              : 3;
2559             __IOM uint32_t PIXSEL : 1; /*!< [12..12] Pixel clock select control. Must be set to the same
2560                                         *   value as OUT_SET.FRQSEL[1].                                               */
2561             uint32_t          : 3;
2562             __IM uint32_t VER : 16;    /*!< [31..16] Version information Version information of the GLCDC             */
2563         } PANEL_CLK_b;
2564     };
2565 } R_GLCDC_SYSCNT_Type;                 /*!< Size = 20 (0x14)                                                          */
2566 
2567 /**
2568  * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING)
2569  */
2570 typedef struct
2571 {
2572     union
2573     {
2574         __IOM uint16_t A;              /*!< (@ 0x00000000) GTIOCA Output Delay Register                               */
2575 
2576         struct
2577         {
2578             __IOM uint16_t DLY : 5;    /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting                           */
2579             uint16_t           : 11;
2580         } A_b;
2581     };
2582 
2583     union
2584     {
2585         __IOM uint16_t B;              /*!< (@ 0x00000002) GTIOCB Output Delay Register                               */
2586 
2587         struct
2588         {
2589             __IOM uint16_t DLY : 5;    /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting                           */
2590             uint16_t           : 11;
2591         } B_b;
2592     };
2593 } R_GPT_ODC_GTDLYR_Type;               /*!< Size = 4 (0x4)                                                            */
2594 
2595 /**
2596  * @brief R_IIC0_SAR [SAR] (Slave Address Registers)
2597  */
2598 typedef struct
2599 {
2600     union
2601     {
2602         __IOM uint8_t L;               /*!< (@ 0x00000000) Slave Address Register L                                   */
2603 
2604         struct
2605         {
2606             __IOM uint8_t SVA : 8;     /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit
2607                                         *   Address = { SVA9,SVA8,SVA[7:0] }                                          */
2608         } L_b;
2609     };
2610 
2611     union
2612     {
2613         __IOM uint8_t U;               /*!< (@ 0x00000001) Slave Address Register U                                   */
2614 
2615         struct
2616         {
2617             __IOM uint8_t FS   : 1;    /*!< [0..0] 7-Bit/10-Bit Address Format Selection                              */
2618             __IOM uint8_t SVA8 : 1;    /*!< [1..1] 10-Bit Address(bit8)                                               */
2619             __IOM uint8_t SVA9 : 1;    /*!< [2..2] 10-Bit Address(bit9)                                               */
2620             uint8_t            : 5;
2621         } U_b;
2622     };
2623 } R_IIC0_SAR_Type;                     /*!< Size = 2 (0x2)                                                            */
2624 
2625 /**
2626  * @brief R_IIRFA_IIRCH [IIRCH] (Channel Registers)
2627  */
2628 typedef struct
2629 {
2630     __OM uint32_t INP;                  /*!< (@ 0x00000000) Channel Input Register                                     */
2631     __IM uint32_t OUT;                  /*!< (@ 0x00000004) Channel Output Register                                    */
2632 
2633     union
2634     {
2635         __IOM uint32_t CNT;             /*!< (@ 0x00000008) Channel Control Register                                   */
2636 
2637         struct
2638         {
2639             __IOM uint32_t STGSEL : 32; /*!< [31..0] Stage selection bit                                               */
2640         } CNT_b;
2641     };
2642 
2643     union
2644     {
2645         __IOM uint8_t INT;             /*!< (@ 0x0000000C) Channel Interrupt Enable Register                          */
2646 
2647         struct
2648         {
2649             uint8_t               : 1;
2650             __IOM uint8_t CPRCFIE : 1; /*!< [1..1] Channel processing completion interrupt enable bit                 */
2651             __IOM uint8_t ORDYIE  : 1; /*!< [2..2] Output data preparation completion interrupt enable bit            */
2652             __IOM uint8_t CERRIE  : 1; /*!< [3..3] Operation error interrupt enable bit                               */
2653             uint8_t               : 4;
2654         } INT_b;
2655     };
2656 
2657     union
2658     {
2659         __IM uint8_t STS;              /*!< (@ 0x0000000D) Channel Status Register                                    */
2660 
2661         struct
2662         {
2663             __IM uint8_t CPRCS  : 1;   /*!< [0..0] Channel processing status flag                                     */
2664             __IM uint8_t CPRCFF : 1;   /*!< [1..1] Channel processing completion flag                                 */
2665             __IM uint8_t ORDYF  : 1;   /*!< [2..2] Output data preparation completion flag                            */
2666             __IM uint8_t CERRF  : 1;   /*!< [3..3] Operation error flag                                               */
2667             uint8_t             : 4;
2668         } STS_b;
2669     };
2670 
2671     union
2672     {
2673         __OM uint8_t FCLR;             /*!< (@ 0x0000000E) Channel Flag Clear Register                                */
2674 
2675         struct
2676         {
2677             uint8_t                : 1;
2678             __OM uint8_t CPRCFFCLR : 1; /*!< [1..1] Channel processing completion flag clear bit                       */
2679             uint8_t                : 1;
2680             __OM uint8_t CERRFCLR  : 1; /*!< [3..3] Operation error flag clear bit                                     */
2681             uint8_t                : 4;
2682         } FCLR_b;
2683     };
2684     __IM uint8_t RESERVED;
2685 } R_IIRFA_IIRCH_Type;                  /*!< Size = 16 (0x10)                                                          */
2686 
2687 /**
2688  * @brief R_IIRFA_IIRSTG [IIRSTG] (Stage Registers)
2689  */
2690 typedef struct
2691 {
2692     __IOM uint32_t B0;                 /*!< (@ 0x00000000) Stage Coefficient b0 Register                              */
2693     __IOM uint32_t B1;                 /*!< (@ 0x00000004) Stage Coefficient b1 Register                              */
2694     __IOM uint32_t B2;                 /*!< (@ 0x00000008) Stage Coefficient b2 Register                              */
2695     __IOM uint32_t A1;                 /*!< (@ 0x0000000C) Stage Coefficient a1 Register                              */
2696     __IOM uint32_t A2;                 /*!< (@ 0x00000010) Stage Coefficient a2 Register                              */
2697     __IOM uint32_t D0;                 /*!< (@ 0x00000014) Stage Delay Data D0 Register                               */
2698     __IOM uint32_t D1;                 /*!< (@ 0x00000018) Stage Delay Data D1 Register                               */
2699     __IM uint32_t  RESERVED;
2700 } R_IIRFA_IIRSTG_Type;                 /*!< Size = 32 (0x20)                                                          */
2701 
2702 /**
2703  * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers)
2704  */
2705 typedef struct
2706 {
2707     union
2708     {
2709         __IOM uint16_t C;              /*!< (@ 0x00000000) Access Control Register                                    */
2710 
2711         struct
2712         {
2713             __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable                                                      */
2714             __IOM uint16_t RP     : 1; /*!< [1..1] Read protection                                                    */
2715             __IOM uint16_t WP     : 1; /*!< [2..2] Write protection                                                   */
2716             uint16_t              : 13;
2717         } C_b;
2718     };
2719     __IM uint16_t RESERVED;
2720 
2721     union
2722     {
2723         __IOM uint32_t S;                /*!< (@ 0x00000004) Start Address Register                                     */
2724 
2725         struct
2726         {
2727             __IOM uint32_t MMPUSmn : 32; /*!< [31..0] Address where the region starts, for use in region determination.NOTE:
2728                                           *   The low-order 2 bits are fixed to 0.                                      */
2729         } S_b;
2730     };
2731 
2732     union
2733     {
2734         __IOM uint32_t E;                /*!< (@ 0x00000008) End Address Register                                       */
2735 
2736         struct
2737         {
2738             __IOM uint32_t MMPUEmn : 32; /*!< [31..0] Region end address registerAddress where the region
2739                                           *   end, for use in region determination.NOTE: The low-order
2740                                           *   2 bits are fixed to 1.                                                    */
2741         } E_b;
2742     };
2743     __IM uint32_t RESERVED1;
2744 } R_MPU_MMPU_MMPU_REGION_Type;           /*!< Size = 16 (0x10)                                                          */
2745 
2746 /**
2747  * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers)
2748  */
2749 typedef struct
2750 {
2751     union
2752     {
2753         __IOM uint16_t CTL;            /*!< (@ 0x00000000) Bus Master MPU Control Register                            */
2754 
2755         struct
2756         {
2757             __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable                                                */
2758             __IOM uint16_t OAD    : 1; /*!< [1..1] Operation after detection                                          */
2759             uint16_t              : 6;
2760             __OM uint16_t KEY     : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2761                                         *   stored.                                                                   */
2762         } CTL_b;
2763     };
2764     __IM uint16_t RESERVED;
2765     __IM uint32_t RESERVED1[63];
2766     __IM uint16_t RESERVED2;
2767 
2768     union
2769     {
2770         __IOM uint16_t PT;                        /*!< (@ 0x00000102) Protection of Register                                     */
2771 
2772         struct
2773         {
2774             __IOM uint16_t PROTECT : 1;           /*!< [0..0] Protection of region register                                      */
2775             uint16_t               : 7;
2776             __OM uint16_t KEY      : 8;           /*!< [15..8] Write Keyword The data written to these bits are not
2777                                                    *   stored.                                                                   */
2778         } PT_b;
2779     };
2780     __IM uint32_t RESERVED3[63];
2781     __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers                                   */
2782 } R_MPU_MMPU_MMPU_Type;                           /*!< Size = 1024 (0x400)                                                       */
2783 
2784 /**
2785  * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU)
2786  */
2787 typedef struct
2788 {
2789     union
2790     {
2791         __IOM uint16_t R;              /*!< (@ 0x00000000) Access Control Register for MBIU                           */
2792 
2793         struct
2794         {
2795             uint16_t              : 2;
2796             __IOM uint16_t RPGRPA : 1;   /*!< [2..2] Master Group A Read protection                                     */
2797             __IOM uint16_t WPGRPA : 1;   /*!< [3..3] Master Group A Write protection                                    */
2798             __IOM uint16_t RPGRPB : 1;   /*!< [4..4] Master Group B Read protection                                     */
2799             __IOM uint16_t WPGRPB : 1;   /*!< [5..5] Master Group B Write protection                                    */
2800             __IOM uint16_t RPGRPC : 1;   /*!< [6..6] Master Group C Read protection                                     */
2801             __IOM uint16_t WPGRPC : 1;   /*!< [7..7] Master Group C Write protection                                    */
2802             uint16_t              : 4;
2803             __IOM uint16_t RPFLI  : 1;   /*!< [12..12] Code Flash Memory Read Protection                                */
2804             __IOM uint16_t WPFLI  : 1;   /*!< [13..13] Code Flash Memory Write Protection (Note: This bit
2805                                           *   is read as 1. The write value should be 1.)                               */
2806             __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection                                           */
2807             __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection                                          */
2808         } R_b;
2809     };
2810     __IM uint16_t RESERVED;
2811 } R_MPU_SMPU_SMPU_Type;                  /*!< Size = 4 (0x4)                                                            */
2812 
2813 /**
2814  * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor)
2815  */
2816 typedef struct
2817 {
2818     union
2819     {
2820         __IOM uint16_t OAD;            /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection
2821                                         *                  Register                                                   */
2822 
2823         struct
2824         {
2825             __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
2826             uint16_t           : 7;
2827             __OM uint16_t KEY  : 8;    /*!< [15..8] Write Keyword The data written to these bits are not
2828                                         *   stored.                                                                   */
2829         } OAD_b;
2830     };
2831     __IM uint16_t RESERVED;
2832 
2833     union
2834     {
2835         __IOM uint16_t CTL;            /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register              */
2836 
2837         struct
2838         {
2839             __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable                                       */
2840             uint16_t              : 7;
2841             __IOM uint16_t ERROR  : 1; /*!< [8..8] Stack Pointer Monitor Error Flag                                   */
2842             uint16_t              : 7;
2843         } CTL_b;
2844     };
2845 
2846     union
2847     {
2848         __IOM uint16_t PT;              /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register                  */
2849 
2850         struct
2851         {
2852             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE)           */
2853             uint16_t               : 7;
2854             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2855                                          *   stored.                                                                   */
2856         } PT_b;
2857     };
2858 
2859     union
2860     {
2861         __IOM uint32_t SA;                /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register               */
2862 
2863         struct
2864         {
2865             __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region
2866                                            *   starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF
2867                                            *   The low-order 2 bits are fixed to 0.                                      */
2868         } SA_b;
2869     };
2870 
2871     union
2872     {
2873         __IOM uint32_t EA;                /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register                 */
2874 
2875         struct
2876         {
2877             __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region
2878                                            *   starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF
2879                                            *   The low-order 2 bits are fixed to 1.                                      */
2880         } EA_b;
2881     };
2882 } R_MPU_SPMON_SP_Type;                    /*!< Size = 16 (0x10)                                                          */
2883 
2884 /**
2885  * @brief R_OPAMP_AMP [AMP] (Input and Output Selectors for Operational Amplifier [0..3])
2886  */
2887 typedef struct
2888 {
2889     __IOM uint8_t OS;                  /*!< (@ 0x00000000) Output Select Register                                     */
2890     __IOM uint8_t MS;                  /*!< (@ 0x00000001) Minus Input Select Register                                */
2891     __IOM uint8_t PS;                  /*!< (@ 0x00000002) Plus Input Select Register                                 */
2892 } R_OPAMP_AMP_Type;                    /*!< Size = 3 (0x3)                                                            */
2893 
2894 /**
2895  * @brief R_OPAMP_AMPOT [AMPOT] (Operational Amplifier n Offset Trimming Registers)
2896  */
2897 typedef struct
2898 {
2899     union
2900     {
2901         __IOM uint8_t P;               /*!< (@ 0x00000000) Operational Amplifier n Offset Trimming Pch Register       */
2902 
2903         struct
2904         {
2905             __IOM uint8_t TRMP : 5;    /*!< [4..0] AMPn input offset trimming Pch side                                */
2906             uint8_t            : 3;
2907         } P_b;
2908     };
2909 
2910     union
2911     {
2912         __IOM uint8_t N;               /*!< (@ 0x00000001) Operational Amplifier n Offset Trimming Nch Register       */
2913 
2914         struct
2915         {
2916             __IOM uint8_t TRMN : 5;    /*!< [4..0] AMPn input offset trimming Nch side                                */
2917             uint8_t            : 3;
2918         } N_b;
2919     };
2920 } R_OPAMP_AMPOT_Type;                  /*!< Size = 2 (0x2)                                                            */
2921 
2922 /**
2923  * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects)
2924  */
2925 typedef struct
2926 {
2927     union
2928     {
2929         union
2930         {
2931             __IOM uint32_t PmnPFS;        /*!< (@ 0x00000000) Pin Function Control Register                              */
2932 
2933             struct
2934             {
2935                 __IOM uint32_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
2936                 __IM uint32_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
2937                 __IOM uint32_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
2938                 uint32_t             : 1;
2939                 __IOM uint32_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
2940                 __IOM uint32_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
2941                 __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
2942                 uint32_t             : 3;
2943                 __IOM uint32_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
2944                 __IOM uint32_t EOFR  : 2; /*!< [13..12] Event on Falling/Rising                                          */
2945                 __IOM uint32_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
2946                 __IOM uint32_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
2947                 __IOM uint32_t PMR   : 1; /*!< [16..16] Port Mode Control                                                */
2948                 uint32_t             : 7;
2949                 __IOM uint32_t PSEL  : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral
2950                                            *   function. For individual pin functions, see the MPC table                 */
2951                 uint32_t : 3;
2952             } PmnPFS_b;
2953         };
2954 
2955         struct
2956         {
2957             union
2958             {
2959                 struct
2960                 {
2961                     __IM uint16_t RESERVED;
2962 
2963                     union
2964                     {
2965                         __IOM uint16_t PmnPFS_HA;     /*!< (@ 0x00000002) Pin Function Control Register                              */
2966 
2967                         struct
2968                         {
2969                             __IOM uint16_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
2970                             __IM uint16_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
2971                             __IOM uint16_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
2972                             uint16_t             : 1;
2973                             __IOM uint16_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
2974                             __IOM uint16_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
2975                             __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
2976                             uint16_t             : 3;
2977                             __IOM uint16_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
2978                             __IOM uint16_t EOFR  : 2; /*!< [13..12] Event on Falling/Rising                                          */
2979                             __IOM uint16_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
2980                             __IOM uint16_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
2981                         } PmnPFS_HA_b;
2982                     };
2983                 };
2984 
2985                 struct
2986                 {
2987                     __IM uint16_t RESERVED1;
2988                     __IM uint8_t  RESERVED2;
2989 
2990                     union
2991                     {
2992                         __IOM uint8_t PmnPFS_BY;     /*!< (@ 0x00000003) Pin Function Control Register                              */
2993 
2994                         struct
2995                         {
2996                             __IOM uint8_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
2997                             __IM uint8_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
2998                             __IOM uint8_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
2999                             uint8_t             : 1;
3000                             __IOM uint8_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
3001                             __IOM uint8_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
3002                             __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
3003                             uint8_t             : 1;
3004                         } PmnPFS_BY_b;
3005                     };
3006                 };
3007             };
3008         };
3009     };
3010 } R_PFS_PORT_PIN_Type;                 /*!< Size = 4 (0x4)                                                            */
3011 
3012 /**
3013  * @brief R_PFS_PORT [PORT] (Port [0..14])
3014  */
3015 typedef struct
3016 {
3017     __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects                                       */
3018 } R_PFS_PORT_Type;                     /*!< Size = 64 (0x40)                                                          */
3019 
3020 /**
3021  * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register)
3022  */
3023 typedef struct
3024 {
3025     __IOM uint16_t PMSAR;              /*!< (@ 0x00000000) Port Security Attribution Register                         */
3026 
3027  #if (2U == BSP_FEATURE_IOPORT_VERSION)
3028     __IM uint16_t RESERVED;
3029  #endif
3030 } R_PMISC_PMSAR_Type;                  /*!< Size = 2 (0x2)                                                            */
3031 
3032 /**
3033  * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register)
3034  */
3035 typedef struct
3036 {
3037     union
3038     {
3039         __IOM uint8_t RTCCR;           /*!< (@ 0x00000000) Time Capture Control Register                              */
3040 
3041         struct
3042         {
3043             __IOM uint8_t TCCT : 2;    /*!< [1..0] Time Capture Control                                               */
3044             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
3045             uint8_t            : 1;
3046             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
3047             uint8_t            : 2;
3048         } RTCCR_b;
3049     };
3050     __IM uint8_t RESERVED;
3051 } R_RTC_RTCCR_Type;                    /*!< Size = 2 (0x2)                                                            */
3052 
3053 /**
3054  * @brief R_RTC_CP [CP] (Capture registers)
3055  */
3056 typedef struct
3057 {
3058     __IM uint8_t RESERVED[2];
3059 
3060     union
3061     {
3062         union
3063         {
3064             __IM uint8_t RSEC;          /*!< (@ 0x00000002) Second Capture Register                                    */
3065 
3066             struct
3067             {
3068                 __IM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Capture Capture value for the ones place of
3069                                          *   seconds                                                                   */
3070                 __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of
3071                                          *   seconds                                                                   */
3072                 uint8_t : 1;
3073             } RSEC_b;
3074         };
3075 
3076         union
3077         {
3078             __IM uint8_t BCNT0;           /*!< (@ 0x00000002) BCNT0 Capture Register                                     */
3079 
3080             struct
3081             {
3082                 __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0
3083                                            *   value when a time capture event is detected.                              */
3084             } BCNT0_b;
3085         };
3086     };
3087     __IM uint8_t RESERVED1;
3088 
3089     union
3090     {
3091         union
3092         {
3093             __IM uint8_t RMIN;          /*!< (@ 0x00000004) Minute Capture Register                                    */
3094 
3095             struct
3096             {
3097                 __IM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
3098                                          *   minutes                                                                   */
3099                 __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of
3100                                          *   minutes                                                                   */
3101                 uint8_t : 1;
3102             } RMIN_b;
3103         };
3104 
3105         union
3106         {
3107             __IM uint8_t BCNT1;           /*!< (@ 0x00000004) BCNT1 Capture Register                                     */
3108 
3109             struct
3110             {
3111                 __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1
3112                                            *   value when a time capture event is detected.                              */
3113             } BCNT1_b;
3114         };
3115     };
3116     __IM uint8_t RESERVED2;
3117 
3118     union
3119     {
3120         union
3121         {
3122             __IM uint8_t RHR;          /*!< (@ 0x00000006) Hour Capture Register                                      */
3123 
3124             struct
3125             {
3126                 __IM uint8_t HR1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
3127                                         *   minutes                                                                   */
3128                 __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of
3129                                         *   minutes                                                                   */
3130                 __IM uint8_t PM : 1;   /*!< [6..6] A.m./p.m. select for time counter setting.                         */
3131                 uint8_t         : 1;
3132             } RHR_b;
3133         };
3134 
3135         union
3136         {
3137             __IM uint8_t BCNT2;           /*!< (@ 0x00000006) BCNT2 Capture Register                                     */
3138 
3139             struct
3140             {
3141                 __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2
3142                                            *   value when a time capture event is detected.                              */
3143             } BCNT2_b;
3144         };
3145     };
3146     __IM uint8_t RESERVED3[3];
3147 
3148     union
3149     {
3150         union
3151         {
3152             __IM uint8_t RDAY;           /*!< (@ 0x0000000A) Date Capture Register                                      */
3153 
3154             struct
3155             {
3156                 __IM uint8_t DATE1  : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes          */
3157                 __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes         */
3158                 uint8_t             : 2;
3159             } RDAY_b;
3160         };
3161 
3162         union
3163         {
3164             __IM uint8_t BCNT3;           /*!< (@ 0x0000000A) BCNT3 Capture Register                                     */
3165 
3166             struct
3167             {
3168                 __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3
3169                                            *   value when a time capture event is detected.                              */
3170             } BCNT3_b;
3171         };
3172     };
3173     __IM uint8_t RESERVED4;
3174 
3175     union
3176     {
3177         __IM uint8_t RMON;             /*!< (@ 0x0000000C) Month Capture Register                                     */
3178 
3179         struct
3180         {
3181             __IM uint8_t MON1  : 4;    /*!< [3..0] 1-Month Capture Capture value for the ones place of months         */
3182             __IM uint8_t MON10 : 1;    /*!< [4..4] 10-Month Capture Capture value for the tens place of
3183                                         *   months                                                                    */
3184             uint8_t : 3;
3185         } RMON_b;
3186     };
3187     __IM uint8_t RESERVED5[3];
3188 } R_RTC_CP_Type;                       /*!< Size = 16 (0x10)                                                          */
3189 
3190 /**
3191  * @brief R_BUS_B_CSa [CSa] (CS Registers)
3192  */
3193 typedef struct
3194 {
3195     __IM uint16_t RESERVED;
3196 
3197     union
3198     {
3199         __IOM uint16_t MOD;            /*!< (@ 0x00000002) Mode Register                                              */
3200 
3201         struct
3202         {
3203             __IOM uint16_t WRMOD : 1;  /*!< [0..0] Write Access Mode Select                                           */
3204             uint16_t             : 2;
3205             __IOM uint16_t EWENB : 1;  /*!< [3..3] External Wait Enable                                               */
3206             uint16_t             : 4;
3207             __IOM uint16_t PRENB : 1;  /*!< [8..8] Page Read Access Enable                                            */
3208             __IOM uint16_t PWENB : 1;  /*!< [9..9] Page Write Access Enable                                           */
3209             uint16_t             : 5;
3210             __IOM uint16_t PRMOD : 1;  /*!< [15..15] Page Read Access Mode Select                                     */
3211         } MOD_b;
3212     };
3213 
3214     union
3215     {
3216         __IOM uint32_t WCR1;             /*!< (@ 0x00000004) Wait Control Register 1                                    */
3217 
3218         struct
3219         {
3220             __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value
3221                                           *   is valid only when the PWENB bit in CSnMOD is set to 1.                   */
3222             uint32_t                : 5;
3223             __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value
3224                                           *   is valid only when the PRENB bit in CSnMOD is set to 1.                   */
3225             uint32_t               : 5;
3226             __IOM uint32_t CSWWAIT : 5;  /*!< [20..16] Normal Write Cycle Wait Select                                   */
3227             uint32_t               : 3;
3228             __IOM uint32_t CSRWAIT : 5;  /*!< [28..24] Normal Read Cycle Wait Select                                    */
3229             uint32_t               : 3;
3230         } WCR1_b;
3231     };
3232 
3233     union
3234     {
3235         __IOM uint32_t WCR2;           /*!< (@ 0x00000008) Wait Control Register 2                                    */
3236 
3237         struct
3238         {
3239             __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select                              */
3240             uint32_t              : 1;
3241             __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select                             */
3242             uint32_t              : 1;
3243             __IOM uint32_t WDOFF  : 3; /*!< [10..8] Write Data Output Extension Cycle Select                          */
3244             uint32_t              : 1;
3245             __IOM uint32_t AWAIT  : 2; /*!< [13..12] CS Assert Wait Select                                            */
3246             uint32_t              : 2;
3247             __IOM uint32_t RDON   : 3; /*!< [18..16] RD Assert Wait Select                                            */
3248             uint32_t              : 1;
3249             __IOM uint32_t WRON   : 3; /*!< [22..20] WR Assert Wait Select                                            */
3250             uint32_t              : 1;
3251             __IOM uint32_t WDON   : 3; /*!< [26..24] Write Data Output Wait Select                                    */
3252             uint32_t              : 1;
3253             __IOM uint32_t CSON   : 3; /*!< [30..28] CS Assert Wait Select                                            */
3254             uint32_t              : 1;
3255         } WCR2_b;
3256     };
3257     __IM uint32_t RESERVED1;
3258 } R_BUS_B_CSa_Type;                    /*!< Size = 16 (0x10)                                                          */
3259 
3260 /**
3261  * @brief R_BUS_B_CSb [CSb] (CS Registers)
3262  */
3263 typedef struct
3264 {
3265     __IM uint16_t RESERVED;
3266 
3267     union
3268     {
3269         __IOM uint16_t CR;             /*!< (@ 0x00000002) Control Register                                           */
3270 
3271         struct
3272         {
3273             __IOM uint16_t EXENB : 1;  /*!< [0..0] Operation Enable                                                   */
3274             uint16_t             : 3;
3275             __IOM uint16_t BSIZE : 2;  /*!< [5..4] External Bus Width Select                                          */
3276             uint16_t             : 2;
3277             __IOM uint16_t EMODE : 1;  /*!< [8..8] Endian Mode                                                        */
3278             uint16_t             : 3;
3279             __IOM uint16_t MPXEN : 1;  /*!< [12..12] Address/Data Multiplexed I/O Interface Select                    */
3280             uint16_t             : 3;
3281         } CR_b;
3282     };
3283     __IM uint16_t RESERVED1[3];
3284 
3285     union
3286     {
3287         __IOM uint16_t REC;            /*!< (@ 0x0000000A) Recovery Cycle Register                                    */
3288 
3289         struct
3290         {
3291             __IOM uint16_t RRCV : 4;   /*!< [3..0] Read Recovery                                                      */
3292             uint16_t            : 4;
3293             __IOM uint16_t WRCV : 4;   /*!< [11..8] Write Recovery                                                    */
3294             uint16_t            : 4;
3295         } REC_b;
3296     };
3297     __IM uint16_t RESERVED2[2];
3298 } R_BUS_B_CSb_Type;                    /*!< Size = 16 (0x10)                                                          */
3299 
3300 /**
3301  * @brief R_BUS_B_BUSERR [BUSERR] (Bus Error Registers)
3302  */
3303 typedef struct
3304 {
3305     union
3306     {
3307         __IM uint32_t ADD;             /*!< (@ 0x00000000) Bus Error Address Register                                 */
3308 
3309         struct
3310         {
3311             __IM uint32_t BERAD : 32;  /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores
3312                                         *   an error address.                                                         */
3313         } ADD_b;
3314     };
3315 
3316     union
3317     {
3318         __IM uint8_t ERRRW;            /*!< (@ 0x00000004) BUS Error Read Write Register                              */
3319 
3320         struct
3321         {
3322             __IM uint8_t RWSTAT : 1;   /*!< [0..0] Error access statusThe status at the time of the error             */
3323             uint8_t             : 7;
3324         } ERRRW_b;
3325     };
3326     __IM uint8_t  RESERVED;
3327     __IM uint16_t RESERVED1;
3328     __IM uint32_t RESERVED2[2];
3329 } R_BUS_B_BUSERR_Type;                 /*!< Size = 16 (0x10)                                                          */
3330 
3331 /**
3332  * @brief R_BUS_B_BUSTZFERR [BUSTZFERR] (Bus TZF Error Registers)
3333  */
3334 typedef struct
3335 {
3336     union
3337     {
3338         __IM uint32_t TZFADD;            /*!< (@ 0x00000000) Bus TZF Error Address Register                             */
3339 
3340         struct
3341         {
3342             __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error AddressWhen a bus error occurs,
3343                                           *   It stores an error address.                                               */
3344         } TZFADD_b;
3345     };
3346 
3347     union
3348     {
3349         __IM uint8_t TZFERRRW;         /*!< (@ 0x00000004) BUS TZF Error Read Write Register                          */
3350 
3351         struct
3352         {
3353             __IM uint8_t TRWSTAT : 1;  /*!< [0..0] TrustZone filter Error access statusThe status at the
3354                                         *   time of the error                                                         */
3355             uint8_t : 7;
3356         } TZFERRRW_b;
3357     };
3358     __IM uint8_t  RESERVED;
3359     __IM uint16_t RESERVED1;
3360     __IM uint32_t RESERVED2[2];
3361 } R_BUS_B_BUSTZFERR_Type;              /*!< Size = 16 (0x10)                                                          */
3362 
3363 /**
3364  * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
3365  */
3366 typedef struct
3367 {
3368     union
3369     {
3370         __IOM uint16_t E;              /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register                   */
3371 
3372         struct
3373         {
3374             uint16_t             : 8;
3375             __IOM uint16_t TRCLR : 1;  /*!< [8..8] Transaction Counter Clear                                          */
3376             __IOM uint16_t TRENB : 1;  /*!< [9..9] Transaction Counter Enable                                         */
3377             uint16_t             : 6;
3378         } E_b;
3379     };
3380 
3381     union
3382     {
3383         __IOM uint16_t N;               /*!< (@ 0x00000002) Pipe Transaction Counter Register                          */
3384 
3385         struct
3386         {
3387             __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter                                               */
3388         } N_b;
3389     };
3390 } R_USB_FS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
3391 
3392 /**
3393  * @brief USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
3394  */
3395 typedef struct
3396 {
3397     union
3398     {
3399         __IOM uint16_t E;              /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register                   */
3400 
3401         struct
3402         {
3403             uint16_t             : 8;
3404             __IOM uint16_t TRCLR : 1;  /*!< [8..8] Transaction Counter Clear                                          */
3405             __IOM uint16_t TRENB : 1;  /*!< [9..9] Transaction Counter Enable                                         */
3406         } E_b;
3407     };
3408 
3409     union
3410     {
3411         __IOM uint16_t N;               /*!< (@ 0x00000002) Pipe Transaction Counter Register                          */
3412 
3413         struct
3414         {
3415             __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter                                               */
3416         } N_b;
3417     };
3418 } R_USB_HS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                           */
3419 
3420 /** @} */ /* End of group Device_Peripheral_clusters */
3421 
3422 /* =========================================================================================================================== */
3423 /* ================                            Device Specific Peripheral Section                             ================ */
3424 /* =========================================================================================================================== */
3425 
3426 /** @addtogroup Device_Peripheral_peripherals
3427  * @{
3428  */
3429 
3430 /* =========================================================================================================================== */
3431 /* ================                                         R_ACMPHS0                                         ================ */
3432 /* =========================================================================================================================== */
3433 
3434 /**
3435  * @brief High-Speed Analog Comparator (R_ACMPHS0)
3436  */
3437 
3438 typedef struct                         /*!< (@ 0x40085000) R_ACMPHS0 Structure                                        */
3439 {
3440     union
3441     {
3442         __IOM uint8_t CMPCTL;          /*!< (@ 0x00000000) Comparator Control Register                                */
3443 
3444         struct
3445         {
3446             __IOM uint8_t CINV   : 1;  /*!< [0..0] Comparator output polarity selection                               */
3447             __IOM uint8_t COE    : 1;  /*!< [1..1] Comparator output enable                                           */
3448             __IOM uint8_t CSTEN  : 1;  /*!< [2..2] Interrupt Select                                                   */
3449             __IOM uint8_t CEG    : 2;  /*!< [4..3] Selection of valid edge (Edge selector)                            */
3450             __IOM uint8_t CDFS   : 2;  /*!< [6..5] Noise filter selection                                             */
3451             __IOM uint8_t HCMPON : 1;  /*!< [7..7] Comparator operation control                                       */
3452         } CMPCTL_b;
3453     };
3454     __IM uint8_t RESERVED[3];
3455 
3456     union
3457     {
3458         __IOM uint8_t CMPSEL0;         /*!< (@ 0x00000004) Comparator Input Select Register                           */
3459 
3460         struct
3461         {
3462             __IOM uint8_t CMPSEL : 4;  /*!< [3..0] Comparator Input Selection                                         */
3463             uint8_t              : 4;
3464         } CMPSEL0_b;
3465     };
3466     __IM uint8_t RESERVED1[3];
3467 
3468     union
3469     {
3470         __IOM uint8_t CMPSEL1;         /*!< (@ 0x00000008) Comparator Reference Voltage Select Register               */
3471 
3472         struct
3473         {
3474             __IOM uint8_t CRVS : 6;    /*!< [5..0] Reference Voltage Selection                                        */
3475             uint8_t            : 2;
3476         } CMPSEL1_b;
3477     };
3478     __IM uint8_t RESERVED2[3];
3479 
3480     union
3481     {
3482         __IM uint8_t CMPMON;           /*!< (@ 0x0000000C) Comparator Output Monitor Register                         */
3483 
3484         struct
3485         {
3486             __IM uint8_t CMPMON : 1;   /*!< [0..0] Comparator output monitor                                          */
3487             uint8_t             : 7;
3488         } CMPMON_b;
3489     };
3490     __IM uint8_t RESERVED3[3];
3491 
3492     union
3493     {
3494         __IOM uint8_t CPIOC;           /*!< (@ 0x00000010) Comparator Output Control Register                         */
3495 
3496         struct
3497         {
3498             __IOM uint8_t CPOE   : 1;  /*!< [0..0] Comparator output selection                                        */
3499             uint8_t              : 6;
3500             __IOM uint8_t VREFEN : 1;  /*!< [7..7] Internal Vref enable                                               */
3501         } CPIOC_b;
3502     };
3503 } R_ACMPHS0_Type;                      /*!< Size = 17 (0x11)                                                          */
3504 
3505 /* =========================================================================================================================== */
3506 /* ================                                         R_ACMPLP                                          ================ */
3507 /* =========================================================================================================================== */
3508 
3509 /**
3510  * @brief Low-Power Analog Comparator (R_ACMPLP)
3511  */
3512 
3513 typedef struct                         /*!< (@ 0x40085E00) R_ACMPLP Structure                                         */
3514 {
3515     union
3516     {
3517         __IOM uint8_t COMPMDR;         /*!< (@ 0x00000000) ACMPLP Mode Setting Register                               */
3518 
3519         struct
3520         {
3521             __IOM uint8_t C0ENB : 1;   /*!< [0..0] ACMPLP0 Operation Enable                                           */
3522             __IOM uint8_t C0WDE : 1;   /*!< [1..1] ACMPLP0 Window Function Mode Enable                                */
3523             __IOM uint8_t C0VRF : 1;   /*!< [2..2] ACMPLP0 Reference Voltage Selection                                */
3524             __IM uint8_t  C0MON : 1;   /*!< [3..3] ACMPLP0 Monitor Flag                                               */
3525             __IOM uint8_t C1ENB : 1;   /*!< [4..4] ACMPLP1 Operation Enable                                           */
3526             __IOM uint8_t C1WDE : 1;   /*!< [5..5] ACMPLP1 Window Function Mode Enable                                */
3527             __IOM uint8_t C1VRF : 1;   /*!< [6..6] ACMPLP1 Reference Voltage Selection                                */
3528             __IM uint8_t  C1MON : 1;   /*!< [7..7] ACMPLP1 Monitor Flag                                               */
3529         } COMPMDR_b;
3530     };
3531 
3532     union
3533     {
3534         __IOM uint8_t COMPFIR;         /*!< (@ 0x00000001) ACMPLP Filter Control Register                             */
3535 
3536         struct
3537         {
3538             __IOM uint8_t C0FCK : 2;   /*!< [1..0] ACMPLP0 Filter Select                                              */
3539             __IOM uint8_t C0EPO : 1;   /*!< [2..2] ACMPLP0 Edge Polarity Switching                                    */
3540             __IOM uint8_t C0EDG : 1;   /*!< [3..3] ACMPLP0 Edge Detection Selection                                   */
3541             __IOM uint8_t C1FCK : 2;   /*!< [5..4] ACMPLP1 Filter Select                                              */
3542             __IOM uint8_t C1EPO : 1;   /*!< [6..6] ACMPLP1 Edge Polarity Switching                                    */
3543             __IOM uint8_t C1EDG : 1;   /*!< [7..7] ACMPLP1 Edge Detection Selection                                   */
3544         } COMPFIR_b;
3545     };
3546 
3547     union
3548     {
3549         __IOM uint8_t COMPOCR;         /*!< (@ 0x00000002) ACMPLP Output Control Register                             */
3550 
3551         struct
3552         {
3553             uint8_t             : 1;
3554             __IOM uint8_t C0OE  : 1;   /*!< [1..1] ACMPLP0 VCOUT Pin Output Enable                                    */
3555             __IOM uint8_t C0OP  : 1;   /*!< [2..2] ACMPLP0 VCOUT Output Polarity Selection                            */
3556             uint8_t             : 2;
3557             __IOM uint8_t C1OE  : 1;   /*!< [5..5] ACMPLP1 VCOUT Pin Output Enable                                    */
3558             __IOM uint8_t C1OP  : 1;   /*!< [6..6] ACMPLP1 VCOUT Output Polarity Selection                            */
3559             __IOM uint8_t SPDMD : 1;   /*!< [7..7] ACMPLP0/ACMPLP1 Speed Selection                                    */
3560         } COMPOCR_b;
3561     };
3562     __IM uint8_t RESERVED;
3563 
3564     union
3565     {
3566         __IOM uint8_t COMPSEL0;        /*!< (@ 0x00000004) Comparator Input Select Register                           */
3567 
3568         struct
3569         {
3570             __IOM uint8_t IVCMP0 : 3;  /*!< [2..0] ACMPLP0 Input (IVCMP0) Selection                                   */
3571             uint8_t              : 1;
3572             __IOM uint8_t IVCMP1 : 3;  /*!< [6..4] ACMPLP1 Input (IVCMP1) Selection                                   */
3573             uint8_t              : 1;
3574         } COMPSEL0_b;
3575     };
3576 
3577     union
3578     {
3579         __IOM uint8_t COMPSEL1;        /*!< (@ 0x00000005) Comparator Reference voltage Select Register               */
3580 
3581         struct
3582         {
3583             __IOM uint8_t IVREF0 : 3;  /*!< [2..0] ACMPLP0 Reference Voltage (IVREF0) Selection                       */
3584             uint8_t              : 1;
3585             __IOM uint8_t IVREF1 : 3;  /*!< [6..4] ACMPLP1 Reference Voltage(IVREF1) Selection                        */
3586             __IOM uint8_t C1VRF2 : 1;  /*!< [7..7] ACMPLP1 Reference Voltage Selection                                */
3587         } COMPSEL1_b;
3588     };
3589 } R_ACMPLP_Type;                       /*!< Size = 6 (0x6)                                                            */
3590 
3591 /* =========================================================================================================================== */
3592 /* ================                                          R_ADC0                                           ================ */
3593 /* =========================================================================================================================== */
3594 
3595 /**
3596  * @brief A/D Converter (R_ADC0)
3597  */
3598 
3599 typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure                                           */
3600 {
3601     union
3602     {
3603         __IOM uint16_t ADCSR;          /*!< (@ 0x00000000) A/D Control Register                                       */
3604 
3605         struct
3606         {
3607             __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog
3608                                         *   input channel for double triggered operation. The setting
3609                                         *   is only effective while double trigger mode is selected.                  */
3610             uint16_t              : 1;
3611             __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable                                  */
3612             __IOM uint16_t DBLE   : 1; /*!< [7..7] Double Trigger Mode Select                                         */
3613             __IOM uint16_t EXTRG  : 1; /*!< [8..8] Trigger Select                                                     */
3614             __IOM uint16_t TRGE   : 1; /*!< [9..9] Trigger Start Enable                                               */
3615             __IOM uint16_t ADHSC  : 1; /*!< [10..10] A/D Conversion Operation Mode Select                             */
3616             uint16_t              : 1;
3617             __IOM uint16_t ADIE   : 1; /*!< [12..12] Scan End Interrupt Enable                                        */
3618             __IOM uint16_t ADCS   : 2; /*!< [14..13] Scan Mode Select                                                 */
3619             __IOM uint16_t ADST   : 1; /*!< [15..15] A/D Conversion Start                                             */
3620         } ADCSR_b;
3621     };
3622 
3623     union
3624     {
3625         __IOM uint8_t ADREF;           /*!< (@ 0x00000002) A/D status register                                        */
3626 
3627         struct
3628         {
3629             __IOM uint8_t ADF : 1;     /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes
3630                                         *   "1" while scanning.                                                       */
3631             uint8_t              : 6;
3632             __IM uint8_t ADSCACT : 1;  /*!< [7..7] Scanning status bit                                                */
3633         } ADREF_b;
3634     };
3635 
3636     union
3637     {
3638         __IOM uint8_t ADEXREF;         /*!< (@ 0x00000003) A/D enhancing status register                              */
3639 
3640         struct
3641         {
3642             __IOM uint8_t GBADF : 1;   /*!< [0..0] Group B scanning end flag bit.                                     */
3643             uint8_t             : 7;
3644         } ADEXREF_b;
3645     };
3646 
3647     union
3648     {
3649         __IOM uint16_t ADANSA[2];      /*!< (@ 0x00000004) A/D Channel Select Register                                */
3650 
3651         struct
3652         {
3653             __IOM uint16_t ANSA0  : 1; /*!< [0..0] AN Input Select                                                    */
3654             __IOM uint16_t ANSA1  : 1; /*!< [1..1] AN Input Select                                                    */
3655             __IOM uint16_t ANSA2  : 1; /*!< [2..2] AN Input Select                                                    */
3656             __IOM uint16_t ANSA3  : 1; /*!< [3..3] AN Input Select                                                    */
3657             __IOM uint16_t ANSA4  : 1; /*!< [4..4] AN Input Select                                                    */
3658             __IOM uint16_t ANSA5  : 1; /*!< [5..5] AN Input Select                                                    */
3659             __IOM uint16_t ANSA6  : 1; /*!< [6..6] AN Input Select                                                    */
3660             __IOM uint16_t ANSA7  : 1; /*!< [7..7] AN Input Select                                                    */
3661             __IOM uint16_t ANSA8  : 1; /*!< [8..8] AN Input Select                                                    */
3662             __IOM uint16_t ANSA9  : 1; /*!< [9..9] AN Input Select                                                    */
3663             __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select                                                  */
3664             __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select                                                  */
3665             __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select                                                  */
3666             __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select                                                  */
3667             __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select                                                  */
3668             __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select                                                  */
3669         } ADANSA_b[2];
3670     };
3671 
3672     union
3673     {
3674         __IOM uint16_t ADADS[2];       /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel
3675                                         *                  Select Register                                            */
3676 
3677         struct
3678         {
3679             __IOM uint16_t ADS0  : 1;  /*!< [0..0] A/D-Converted Value Addition/Average Channel Select                */
3680             __IOM uint16_t ADS1  : 1;  /*!< [1..1] A/D-Converted Value Addition/Average Channel Select                */
3681             __IOM uint16_t ADS2  : 1;  /*!< [2..2] A/D-Converted Value Addition/Average Channel Select                */
3682             __IOM uint16_t ADS3  : 1;  /*!< [3..3] A/D-Converted Value Addition/Average Channel Select                */
3683             __IOM uint16_t ADS4  : 1;  /*!< [4..4] A/D-Converted Value Addition/Average Channel Select                */
3684             __IOM uint16_t ADS5  : 1;  /*!< [5..5] A/D-Converted Value Addition/Average Channel Select                */
3685             __IOM uint16_t ADS6  : 1;  /*!< [6..6] A/D-Converted Value Addition/Average Channel Select                */
3686             __IOM uint16_t ADS7  : 1;  /*!< [7..7] A/D-Converted Value Addition/Average Channel Select                */
3687             __IOM uint16_t ADS8  : 1;  /*!< [8..8] A/D-Converted Value Addition/Average Channel Select                */
3688             __IOM uint16_t ADS9  : 1;  /*!< [9..9] A/D-Converted Value Addition/Average Channel Select                */
3689             __IOM uint16_t ADS10 : 1;  /*!< [10..10] A/D-Converted Value Addition/Average Channel Select              */
3690             __IOM uint16_t ADS11 : 1;  /*!< [11..11] A/D-Converted Value Addition/Average Channel Select              */
3691             __IOM uint16_t ADS12 : 1;  /*!< [12..12] A/D-Converted Value Addition/Average Channel Select              */
3692             __IOM uint16_t ADS13 : 1;  /*!< [13..13] A/D-Converted Value Addition/Average Channel Select              */
3693             __IOM uint16_t ADS14 : 1;  /*!< [14..14] A/D-Converted Value Addition/Average Channel Select              */
3694             __IOM uint16_t ADS15 : 1;  /*!< [15..15] A/D-Converted Value Addition/Average Channel Select              */
3695         } ADADS_b[2];
3696     };
3697 
3698     union
3699     {
3700         __IOM uint8_t ADADC;           /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select
3701                                         *                  Register                                                   */
3702 
3703         struct
3704         {
3705             __IOM uint8_t ADC : 3;     /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid
3706                                         *   at the only setting of ADC[2:0] bits = 001b or 011b. When
3707                                         *   average mode is selected by setting the ADADC.AVEE bit
3708                                         *   to 1, do not set the addition count to three times (ADADC.ADC[2:0]
3709                                         *   = 010b)                                                                   */
3710             uint8_t            : 4;
3711             __IOM uint8_t AVEE : 1;    /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected
3712                                         *   by setting the ADADC.AVEE bit to 0, set the addition count
3713                                         *   to 1, 2, 3, 4 or 16-time conversion. 16-time conversion
3714                                         *   can only be used with 12-bit accuracy selected. NOTE: AVEE
3715                                         *   bit is valid at the only setting of ADC[2:0] bits = 001b
3716                                         *   or 011b. When average mode is selected by setting the ADADC.AVEE
3717                                         *   bit to 1, do not set the addition count to three times
3718                                         *   (ADADC.ADC[2:0] = 010b)                                                   */
3719         } ADADC_b;
3720     };
3721     __IM uint8_t RESERVED;
3722 
3723     union
3724     {
3725         __IOM uint16_t ADCER;          /*!< (@ 0x0000000E) A/D Control Extended Register                              */
3726 
3727         struct
3728         {
3729             uint16_t               : 1;
3730             __IOM uint16_t ADPRC   : 2; /*!< [2..1] A/D Conversion Accuracy Specify                                    */
3731             uint16_t               : 1;
3732             __IOM uint16_t DCE     : 1; /*!< [4..4] Discharge Enable                                                   */
3733             __IOM uint16_t ACE     : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable                        */
3734             uint16_t               : 2;
3735             __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select                           */
3736             __IOM uint16_t DIAGLD  : 1; /*!< [10..10] Self-Diagnosis Mode Select                                       */
3737             __IOM uint16_t DIAGM   : 1; /*!< [11..11] Self-Diagnosis Enable                                            */
3738             uint16_t               : 2;
3739             __IOM uint16_t ADINV   : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select           */
3740             __IOM uint16_t ADRFMT  : 1; /*!< [15..15] A/D Data Register Format Select                                  */
3741         } ADCER_b;
3742     };
3743 
3744     union
3745     {
3746         __IOM uint16_t ADSTRGR;        /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register               */
3747 
3748         struct
3749         {
3750             __IOM uint16_t TRSB : 6;   /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect
3751                                         *   the A/D conversion start trigger for group B in group scan
3752                                         *   mode.                                                                     */
3753             uint16_t            : 2;
3754             __IOM uint16_t TRSA : 6;   /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion
3755                                         *   start trigger in single scan mode and continuous mode.
3756                                         *   In group scan mode, the A/D conversion start trigger for
3757                                         *   group A is selected.                                                      */
3758             uint16_t : 2;
3759         } ADSTRGR_b;
3760     };
3761 
3762     union
3763     {
3764         __IOM uint16_t ADEXICR;        /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register             */
3765 
3766         struct
3767         {
3768             __IOM uint16_t TSSAD : 1;  /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average
3769                                         *   Mode Select                                                               */
3770             __IOM uint16_t OCSAD : 1;  /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average
3771                                         *   Mode Select                                                               */
3772             uint16_t            : 6;
3773             __IOM uint16_t TSSA : 1;   /*!< [8..8] Temperature Sensor Output A/D Conversion Select                    */
3774             __IOM uint16_t OCSA : 1;   /*!< [9..9] Internal Reference Voltage A/D Conversion Select                   */
3775             __IOM uint16_t TSSB : 1;   /*!< [10..10] Temperature Sensor Output A/D Conversion Select for
3776                                         *   Group B in group scan mode.                                               */
3777             __IOM uint16_t OCSB : 1;   /*!< [11..11] Internal Reference Voltage A/D Conversion Select for
3778                                         *   Group B in group scan mode.                                               */
3779             uint16_t             : 2;
3780             __IOM uint16_t EXSEL : 1;  /*!< [14..14] Extended Analog Input Select                                     */
3781             __IOM uint16_t EXOEN : 1;  /*!< [15..15] Extended Analog Output Control                                   */
3782         } ADEXICR_b;
3783     };
3784 
3785     union
3786     {
3787         __IOM uint16_t ADANSB[2];      /*!< (@ 0x00000014) A/D Channel Select Register B                              */
3788 
3789         struct
3790         {
3791             __IOM uint16_t ANSB0  : 1; /*!< [0..0] AN Input Select                                                    */
3792             __IOM uint16_t ANSB1  : 1; /*!< [1..1] AN Input Select                                                    */
3793             __IOM uint16_t ANSB2  : 1; /*!< [2..2] AN Input Select                                                    */
3794             __IOM uint16_t ANSB3  : 1; /*!< [3..3] AN Input Select                                                    */
3795             __IOM uint16_t ANSB4  : 1; /*!< [4..4] AN Input Select                                                    */
3796             __IOM uint16_t ANSB5  : 1; /*!< [5..5] AN Input Select                                                    */
3797             __IOM uint16_t ANSB6  : 1; /*!< [6..6] AN Input Select                                                    */
3798             __IOM uint16_t ANSB7  : 1; /*!< [7..7] AN Input Select                                                    */
3799             __IOM uint16_t ANSB8  : 1; /*!< [8..8] AN Input Select                                                    */
3800             __IOM uint16_t ANSB9  : 1; /*!< [9..9] AN Input Select                                                    */
3801             __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select                                                  */
3802             __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select                                                  */
3803             __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select                                                  */
3804             __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select                                                  */
3805             __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select                                                  */
3806             __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select                                                  */
3807         } ADANSB_b[2];
3808     };
3809 
3810     union
3811     {
3812         __IM uint16_t ADDBLDR;          /*!< (@ 0x00000018) A/D Data Duplication Register                              */
3813 
3814         struct
3815         {
3816             __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
3817                                          *   result of A/D conversion in response to the second trigger
3818                                          *   in double trigger mode.                                                   */
3819         } ADDBLDR_b;
3820     };
3821 
3822     union
3823     {
3824         __IM uint16_t ADTSDR;          /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register                       */
3825 
3826         struct
3827         {
3828             __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
3829                                         *   A/D conversion result of temperature sensor output.                       */
3830         } ADTSDR_b;
3831     };
3832 
3833     union
3834     {
3835         __IM uint16_t ADOCDR;          /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register               */
3836 
3837         struct
3838         {
3839             __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
3840                                         *   A/D result of internal reference voltage.                                 */
3841         } ADOCDR_b;
3842     };
3843 
3844     union
3845     {
3846         union
3847         {
3848             __IM uint16_t ADRD_RIGHT;     /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified           */
3849 
3850             struct
3851             {
3852                 __IM uint16_t AD : 14;    /*!< [13..0] A/D-converted value (right-justified)The format for
3853                                            *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
3854                 __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status                                            */
3855             } ADRD_RIGHT_b;
3856         };
3857 
3858         union
3859         {
3860             __IM uint16_t ADRD_LEFT;       /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified            */
3861 
3862             struct
3863             {
3864                 __IM uint16_t DIAGST : 2;  /*!< [1..0] Self-Diagnosis Status                                              */
3865                 __IM uint16_t AD     : 14; /*!< [15..2] A/D-converted value (right-justified)The format for
3866                                             *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
3867             } ADRD_LEFT_b;
3868         };
3869     };
3870 
3871     union
3872     {
3873         __IM uint16_t ADDR[28];        /*!< (@ 0x00000020) A/D Data Register                                          */
3874 
3875         struct
3876         {
3877             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
3878                                         *   storing the result of A/D conversion.                                     */
3879         } ADDR_b[28];
3880     };
3881     __IM uint16_t RESERVED1[5];
3882 
3883     union
3884     {
3885         __IOM uint8_t ADAMPOFF;        /*!< (@ 0x00000062) A/D RRAMP off state register                               */
3886 
3887         struct
3888         {
3889             __IOM uint8_t OPOFF : 8;   /*!< [7..0] OPOFF                                                              */
3890         } ADAMPOFF_b;
3891     };
3892 
3893     union
3894     {
3895         __IOM uint8_t ADTSTPR;         /*!< (@ 0x00000063) A/D Test Protecting Release Register                       */
3896 
3897         struct
3898         {
3899             __IOM uint8_t PRO  : 1;    /*!< [0..0] Test register protecting bit.                                      */
3900             __IOM uint8_t B0WI : 1;    /*!< [1..1] Bit 0 writing permission bit.                                      */
3901             uint8_t            : 6;
3902         } ADTSTPR_b;
3903     };
3904 
3905     union
3906     {
3907         __IOM uint16_t ADDDACER;       /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register                        */
3908 
3909         struct
3910         {
3911             __IOM uint16_t WRION  : 5; /*!< [4..0] WRION                                                              */
3912             uint16_t              : 3;
3913             __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF                                                            */
3914             uint16_t              : 2;
3915             __IOM uint16_t ADHS   : 1; /*!< [15..15] ADHS                                                             */
3916         } ADDDACER_b;
3917     };
3918 
3919     union
3920     {
3921         __IOM uint16_t ADSHCR;         /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register               */
3922 
3923         struct
3924         {
3925             __IOM uint16_t SSTSH : 8;  /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time
3926                                         *   Setting Set the sampling time (4 to 255 states)                           */
3927             __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select                               */
3928             __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select                               */
3929             __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select                             */
3930             uint16_t              : 5;
3931         } ADSHCR_b;
3932     };
3933 
3934     union
3935     {
3936         __IOM uint16_t ADEXTSTR;       /*!< (@ 0x00000068) A/D Enhancing Test Register                                */
3937 
3938         struct
3939         {
3940             __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit
3941                                         *   only for channel.                                                         */
3942             uint16_t             : 1;
3943             __IOM uint16_t SWTST : 2;  /*!< [5..4] Test selection bit for pressure switch.                            */
3944             uint16_t             : 2;
3945             __IOM uint16_t SHTRM : 2;  /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit
3946                                         *   for adjustment to hardening of process.                                   */
3947             uint16_t              : 1;
3948             __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator
3949                                         *   power save bit for A/D hard macro to hardening of process.                */
3950             __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim
3951                                         *   bit for A/D hard macro to hardening of process.                           */
3952             __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim
3953                                         *   bit for A/D hard macro to hardening of process.                           */
3954         } ADEXTSTR_b;
3955     };
3956 
3957     union
3958     {
3959         __IOM uint16_t ADTSTRA;           /*!< (@ 0x0000006A) A/D Test Register A                                        */
3960 
3961         struct
3962         {
3963             __IOM uint16_t ATBUSSEL : 1;  /*!< [0..0] Analog test bus selection bit.                                     */
3964             __IOM uint16_t TSTSWREF : 3;  /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit
3965                                            *   amplifier test.Refreshing the pressure switch that opens
3966                                            *   for the DAC output voltage charge period when the amplifier
3967                                            *   of the S&H circuit is tested only for the channel is set.                 */
3968             uint16_t            : 1;
3969             __IOM uint16_t OCSW : 1;      /*!< [5..5] Internal reference voltage analog switch test control
3970                                            *   bit.                                                                      */
3971             __IOM uint16_t TSSW : 1;      /*!< [6..6] Temperature sensor output analogue switch test control
3972                                            *   bit                                                                       */
3973             uint16_t                 : 1;
3974             __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog
3975                                            *   module Details are described to the bit explanation.                      */
3976             __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the
3977                                            *   bit explanation.                                                          */
3978         } ADTSTRA_b;
3979     };
3980 
3981     union
3982     {
3983         __IOM uint16_t ADTSTRB;        /*!< (@ 0x0000006C) A/D Test Register B                                        */
3984 
3985         struct
3986         {
3987             __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It
3988                                         *   corresponds to ADVAL 14:0 input of A/D analog module.                     */
3989             uint16_t : 1;
3990         } ADTSTRB_b;
3991     };
3992 
3993     union
3994     {
3995         __IOM uint16_t ADTSTRC;         /*!< (@ 0x0000006E) A/D Test Register C                                        */
3996 
3997         struct
3998         {
3999             __IOM uint16_t ADMD : 8;    /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D
4000                                          *   analog module.                                                            */
4001             uint16_t               : 4;
4002             __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit.              */
4003             uint16_t               : 3;
4004         } ADTSTRC_b;
4005     };
4006 
4007     union
4008     {
4009         __IOM uint16_t ADTSTRD;         /*!< (@ 0x00000070) A/D Test Register D                                        */
4010 
4011         struct
4012         {
4013             __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It
4014                                          *   corresponds to ADVAL 16 input of A/D analog module.                       */
4015             uint16_t : 15;
4016         } ADTSTRD_b;
4017     };
4018 
4019     union
4020     {
4021         __IOM uint16_t ADSWTSTR0;      /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0                 */
4022 
4023         struct
4024         {
4025             __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit.                                   */
4026             __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit.                                   */
4027             __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit.                                   */
4028             __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit.                                   */
4029             __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit.                                   */
4030             __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit.                                   */
4031             uint16_t              : 10;
4032         } ADSWTSTR0_b;
4033     };
4034 
4035     union
4036     {
4037         __IOM uint16_t ADSWTSTR1;      /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1                 */
4038 
4039         struct
4040         {
4041             __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit.                                   */
4042             __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit.                                   */
4043             __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit.                                   */
4044             __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit.                                   */
4045             __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit.                                   */
4046             __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit.                                   */
4047             uint16_t              : 10;
4048         } ADSWTSTR1_b;
4049     };
4050 
4051     union
4052     {
4053         __IOM uint16_t ADSWTSTR2;        /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2                 */
4054 
4055         struct
4056         {
4057             __IOM uint16_t EX0SW : 1;    /*!< [0..0] Test control of 0 enhancing input channel switches bit
4058                                           *   (ANEX0 switch)                                                            */
4059             __IOM uint16_t EX1SW : 1;    /*!< [1..1] Test control of one enhancing input channel switch bit
4060                                           *   (ANEX1 switch).                                                           */
4061             uint16_t                : 2;
4062             __IOM uint16_t SHBYPS0  : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0.                          */
4063             __IOM uint16_t SHBYPS1  : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1.                          */
4064             __IOM uint16_t SHBYPS2  : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2.                          */
4065             uint16_t                : 1;
4066             __IOM uint16_t GRP0SW   : 1; /*!< [8..8] Test control of 0 group switches bit.                              */
4067             __IOM uint16_t GRP1SW   : 1; /*!< [9..9] Test control of one group switch bit.                              */
4068             __IOM uint16_t GRP2SW   : 1; /*!< [10..10] Test control of two group switches bit                           */
4069             __IOM uint16_t GRP3SW   : 1; /*!< [11..11] Test control of two group switches bit                           */
4070             __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1                */
4071             uint16_t                : 3;
4072         } ADSWTSTR2_b;
4073     };
4074     __IM uint16_t RESERVED2;
4075 
4076     union
4077     {
4078         __IOM uint8_t ADDISCR;         /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register               */
4079 
4080         struct
4081         {
4082             __IOM uint8_t ADNDIS : 4;  /*!< [3..0] The charging time                                                  */
4083             __IOM uint8_t CHARGE : 1;  /*!< [4..4] Selection of Precharge or Discharge                                */
4084             uint8_t              : 3;
4085         } ADDISCR_b;
4086     };
4087 
4088     union
4089     {
4090         __IOM uint8_t ADSWCR;          /*!< (@ 0x0000007B) A/D Pressure Switch Control Register                       */
4091 
4092         struct
4093         {
4094             __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing
4095                                         *   the pressure switch in A/D analog module is set.                          */
4096             uint8_t               : 1;
4097             __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting                          */
4098             uint8_t               : 1;
4099         } ADSWCR_b;
4100     };
4101 
4102     union
4103     {
4104         __IOM uint8_t ADSHMSR;         /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register         */
4105 
4106         struct
4107         {
4108             __IOM uint8_t SHMD : 1;    /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode
4109                                         *   Select                                                                    */
4110             uint8_t : 7;
4111         } ADSHMSR_b;
4112     };
4113 
4114     union
4115     {
4116         __IOM uint8_t ADICR;           /*!< (@ 0x0000007D) A/D Interrupt Control Register                             */
4117 
4118         struct
4119         {
4120             __IOM uint8_t ADIC : 2;    /*!< [1..0] A/D Interrupt Control                                              */
4121             uint8_t            : 6;
4122         } ADICR_b;
4123     };
4124 
4125     union
4126     {
4127         __IOM uint8_t ADACSR;          /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register              */
4128 
4129         struct
4130         {
4131             uint8_t             : 1;
4132             __IOM uint8_t ADSAC : 1;   /*!< [1..1] Successive Approximation Control Setting                           */
4133             uint8_t             : 6;
4134         } ADACSR_b;
4135     };
4136     __IM uint8_t RESERVED3;
4137 
4138     union
4139     {
4140         __IOM uint16_t ADGSPCR;         /*!< (@ 0x00000080) A/D Group Scan Priority Control Register                   */
4141 
4142         struct
4143         {
4144             __IOM uint16_t PGS : 1;     /*!< [0..0] Group A priority control setting bit.Note: When the PGS
4145                                          *   bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be
4146                                          *   set to 01b (group scan mode). If the bits are set to any
4147                                          *   other values, proper operation is not guaranteed.                         */
4148             __IOM uint16_t GBRSCN : 1;  /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved
4149                                          *   when PGS = 0.)                                                            */
4150             uint16_t               : 6;
4151             __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B.                        */
4152             uint16_t               : 6;
4153             __IOM uint16_t GBRP    : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when
4154                                          *   PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit
4155                                          *   has been set to 1, single scan is performed continuously
4156                                          *   for group B regardless of the setting of the GBRSCN bit.                  */
4157         } ADGSPCR_b;
4158     };
4159 
4160     union
4161     {
4162         __IM uint16_t ADGSCS;          /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group
4163                                         *                  Scan)                                                      */
4164 
4165         struct
4166         {
4167             __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan                                     */
4168             __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan                                    */
4169         } ADGSCS_b;
4170     };
4171 
4172     union
4173     {
4174         __IM uint16_t ADDBLDRA;          /*!< (@ 0x00000084) A/D Data Duplexing Register A                              */
4175 
4176         struct
4177         {
4178             __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
4179                                           *   the result of A/D conversion in response to the respective
4180                                           *   triggers during extended operation in double trigger mode.                */
4181         } ADDBLDRA_b;
4182     };
4183 
4184     union
4185     {
4186         __IM uint16_t ADDBLDRB;          /*!< (@ 0x00000086) A/D Data Duplexing Register B                              */
4187 
4188         struct
4189         {
4190             __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
4191                                           *   the result of A/D conversion in response to the respective
4192                                           *   triggers during extended operation in double trigger mode.                */
4193         } ADDBLDRB_b;
4194     };
4195 
4196     union
4197     {
4198         __IOM uint8_t ADSER;           /*!< (@ 0x00000088) A/D Sampling Extension Register                            */
4199 
4200         struct
4201         {
4202             uint8_t             : 7;
4203             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
4204         } ADSER_b;
4205     };
4206     __IM uint8_t RESERVED4;
4207 
4208     union
4209     {
4210         __IOM uint8_t ADHVREFCNT;      /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage
4211                                         *                  Control Register                                           */
4212 
4213         struct
4214         {
4215             __IOM uint8_t HVSEL : 2;   /*!< [1..0] High-Potential Reference Voltage Select                            */
4216             uint8_t             : 2;
4217             __IOM uint8_t LVSEL : 1;   /*!< [4..4] Low-Potential Reference Voltage Select                             */
4218             uint8_t             : 2;
4219             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
4220         } ADHVREFCNT_b;
4221     };
4222     __IM uint8_t RESERVED5;
4223 
4224     union
4225     {
4226         __IM uint8_t ADWINMON;         /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor
4227                                         *                  Register                                                   */
4228 
4229         struct
4230         {
4231             __IM uint8_t MONCOMB : 1;  /*!< [0..0] Combination result monitorThis bit indicates the combination
4232                                         *   result.This bit is valid when both window A operation and
4233                                         *   window B operation are enabled.                                           */
4234             uint8_t              : 3;
4235             __IM uint8_t MONCMPA : 1;  /*!< [4..4] Comparison Result Monitor A                                        */
4236             __IM uint8_t MONCMPB : 1;  /*!< [5..5] Comparison Result Monitor B                                        */
4237             uint8_t              : 2;
4238         } ADWINMON_b;
4239     };
4240     __IM uint8_t  RESERVED6;
4241     __IM uint16_t RESERVED7;
4242 
4243     union
4244     {
4245         __IOM uint16_t ADCMPCR;        /*!< (@ 0x00000090) A/D Compare Function Control Register                      */
4246 
4247         struct
4248         {
4249             __IOM uint16_t CMPAB : 2;  /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits
4250                                         *   are valid when both window A and window B are enabled (CMPAE
4251                                         *   = 1 and CMPBE = 1).                                                       */
4252             uint16_t              : 7;
4253             __IOM uint16_t CMPBE  : 1; /*!< [9..9] Compare Window B Operation Enable                                  */
4254             uint16_t              : 1;
4255             __IOM uint16_t CMPAE  : 1; /*!< [11..11] Compare Window A Operation Enable                                */
4256             uint16_t              : 1;
4257             __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable                                       */
4258             __IOM uint16_t WCMPE  : 1; /*!< [14..14] Window Function Setting                                          */
4259             __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable                                       */
4260         } ADCMPCR_b;
4261     };
4262 
4263     union
4264     {
4265         __IOM uint8_t ADCMPANSER;      /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input
4266                                         *                  Select Register                                            */
4267 
4268         struct
4269         {
4270             __IOM uint8_t CMPTSA : 1;  /*!< [0..0] Temperature sensor output Compare selection bit.                   */
4271             __IOM uint8_t CMPOCA : 1;  /*!< [1..1] Internal reference voltage Compare selection bit.                  */
4272             uint8_t              : 6;
4273         } ADCMPANSER_b;
4274     };
4275 
4276     union
4277     {
4278         __IOM uint8_t ADCMPLER;        /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input
4279                                         *                  Comparison Condition Setting Register                      */
4280 
4281         struct
4282         {
4283             __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison
4284                                         *   Condition Select                                                          */
4285             __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition
4286                                         *   Select                                                                    */
4287             uint8_t : 6;
4288         } ADCMPLER_b;
4289     };
4290 
4291     union
4292     {
4293         __IOM uint16_t ADCMPANSR[2];     /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select
4294                                           *                  Register                                                   */
4295 
4296         struct
4297         {
4298             __IOM uint16_t CMPCHA0  : 1; /*!< [0..0] AN Input Select                                                    */
4299             __IOM uint16_t CMPCHA1  : 1; /*!< [1..1] AN Input Select                                                    */
4300             __IOM uint16_t CMPCHA2  : 1; /*!< [2..2] AN Input Select                                                    */
4301             __IOM uint16_t CMPCHA3  : 1; /*!< [3..3] AN Input Select                                                    */
4302             __IOM uint16_t CMPCHA4  : 1; /*!< [4..4] AN Input Select                                                    */
4303             __IOM uint16_t CMPCHA5  : 1; /*!< [5..5] AN Input Select                                                    */
4304             __IOM uint16_t CMPCHA6  : 1; /*!< [6..6] AN Input Select                                                    */
4305             __IOM uint16_t CMPCHA7  : 1; /*!< [7..7] AN Input Select                                                    */
4306             __IOM uint16_t CMPCHA8  : 1; /*!< [8..8] AN Input Select                                                    */
4307             __IOM uint16_t CMPCHA9  : 1; /*!< [9..9] AN Input Select                                                    */
4308             __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select                                                  */
4309             __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select                                                  */
4310             __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select                                                  */
4311             __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select                                                  */
4312             __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select                                                  */
4313             __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select                                                  */
4314         } ADCMPANSR_b[2];
4315     };
4316 
4317     union
4318     {
4319         __IOM uint16_t ADCMPLR[2];        /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition
4320                                            *                  Setting Register                                           */
4321 
4322         struct
4323         {
4324             __IOM uint16_t CMPLCHA0  : 1; /*!< [0..0] Comparison condition of input                                      */
4325             __IOM uint16_t CMPLCHA1  : 1; /*!< [1..1] Comparison condition of input                                      */
4326             __IOM uint16_t CMPLCHA2  : 1; /*!< [2..2] Comparison condition of input                                      */
4327             __IOM uint16_t CMPLCHA3  : 1; /*!< [3..3] Comparison condition of input                                      */
4328             __IOM uint16_t CMPLCHA4  : 1; /*!< [4..4] Comparison condition of input                                      */
4329             __IOM uint16_t CMPLCHA5  : 1; /*!< [5..5] Comparison condition of input                                      */
4330             __IOM uint16_t CMPLCHA6  : 1; /*!< [6..6] Comparison condition of input                                      */
4331             __IOM uint16_t CMPLCHA7  : 1; /*!< [7..7] Comparison condition of input                                      */
4332             __IOM uint16_t CMPLCHA8  : 1; /*!< [8..8] Comparison condition of input                                      */
4333             __IOM uint16_t CMPLCHA9  : 1; /*!< [9..9] Comparison condition of input                                      */
4334             __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input                                    */
4335             __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input                                    */
4336             __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input                                    */
4337             __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input                                    */
4338             __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input                                    */
4339             __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input                                    */
4340         } ADCMPLR_b[2];
4341     };
4342 
4343     union
4344     {
4345         __IOM uint16_t ADCMPDR0;          /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level
4346                                            *                  Setting Register                                           */
4347 
4348         struct
4349         {
4350             __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the
4351                                            *   compare window A function is used. ADCMPDR0 sets the lower-side
4352                                            *   level of window A.                                                        */
4353         } ADCMPDR0_b;
4354     };
4355 
4356     union
4357     {
4358         __IOM uint16_t ADCMPDR1;          /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level
4359                                            *                  Setting Register                                           */
4360 
4361         struct
4362         {
4363             __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the
4364                                            *   compare window A function is used. ADCMPDR1 sets the upper-side
4365                                            *   level of window A..                                                       */
4366         } ADCMPDR1_b;
4367     };
4368 
4369     union
4370     {
4371         __IOM uint16_t ADCMPSR[2];         /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status
4372                                             *                  Register                                                   */
4373 
4374         struct
4375         {
4376             __IOM uint16_t CMPSTCHA0  : 1; /*!< [0..0] Compare window A flag of input                                     */
4377             __IOM uint16_t CMPSTCHA1  : 1; /*!< [1..1] Compare window A flag of input                                     */
4378             __IOM uint16_t CMPSTCHA2  : 1; /*!< [2..2] Compare window A flag of input                                     */
4379             __IOM uint16_t CMPSTCHA3  : 1; /*!< [3..3] Compare window A flag of input                                     */
4380             __IOM uint16_t CMPSTCHA4  : 1; /*!< [4..4] Compare window A flag of input                                     */
4381             __IOM uint16_t CMPSTCHA5  : 1; /*!< [5..5] Compare window A flag of input                                     */
4382             __IOM uint16_t CMPSTCHA6  : 1; /*!< [6..6] Compare window A flag of input                                     */
4383             __IOM uint16_t CMPSTCHA7  : 1; /*!< [7..7] Compare window A flag of input                                     */
4384             __IOM uint16_t CMPSTCHA8  : 1; /*!< [8..8] Compare window A flag of input                                     */
4385             __IOM uint16_t CMPSTCHA9  : 1; /*!< [9..9] Compare window A flag of input                                     */
4386             __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input                                   */
4387             __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input                                   */
4388             __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input                                   */
4389             __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input                                   */
4390             __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input                                   */
4391             __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input                                   */
4392         } ADCMPSR_b[2];
4393     };
4394 
4395     union
4396     {
4397         __IOM uint8_t ADCMPSER;         /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input
4398                                          *                  Channel Status Register                                    */
4399 
4400         struct
4401         {
4402             __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag
4403                                          *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
4404                                          *   this bit indicates the temperature sensor output comparison
4405                                          *   result. When window A operation is disabled (ADCMPCR.CMPAE
4406                                          *   = 0b), comparison conditions for CMPSTTSA are not met any
4407                                          *   time.                                                                     */
4408             __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag
4409                                          *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
4410                                          *   this bit indicates the temperature sensor output comparison
4411                                          *   result. When window A operation is disabled (ADCMPCR.CMPAE
4412                                          *   = 0b), comparison conditions for CMPSTTSA are not met any
4413                                          *   time.                                                                     */
4414             uint8_t : 6;
4415         } ADCMPSER_b;
4416     };
4417     __IM uint8_t RESERVED8;
4418 
4419     union
4420     {
4421         __IOM uint8_t ADCMPBNSR;       /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection
4422                                         *                  Register                                                   */
4423 
4424         struct
4425         {
4426             __IOM uint8_t CMPCHB : 6;  /*!< [5..0] Compare window B channel selection bit.The channel that
4427                                         *   compares it on the condition of compare window B is selected.             */
4428             uint8_t             : 1;
4429             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
4430         } ADCMPBNSR_b;
4431     };
4432     __IM uint8_t RESERVED9;
4433 
4434     union
4435     {
4436         __IOM uint16_t ADWINLLB;          /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level
4437                                            *                  Setting Register                                           */
4438 
4439         struct
4440         {
4441             __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is
4442                                            *   used to set the lower level of the window B.                              */
4443         } ADWINLLB_b;
4444     };
4445 
4446     union
4447     {
4448         __IOM uint16_t ADWINULB;          /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level
4449                                            *                  Setting Register                                           */
4450 
4451         struct
4452         {
4453             __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is
4454                                            *   used to set the higher level of the window B.                             */
4455         } ADWINULB_b;
4456     };
4457 
4458     union
4459     {
4460         __IOM uint8_t ADCMPBSR;        /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register              */
4461 
4462         struct
4463         {
4464             __IOM uint8_t CMPSTB : 1;  /*!< [0..0] Compare window B flag.It is a status flag that shows
4465                                         *   the comparative result of CH (AN000-AN027, temperature
4466                                         *   sensor, and internal reference voltage) made the object
4467                                         *   of window B relation condition.                                           */
4468             uint8_t : 7;
4469         } ADCMPBSR_b;
4470     };
4471     __IM uint8_t  RESERVED10;
4472     __IM uint16_t RESERVED11;
4473 
4474     union
4475     {
4476         __IM uint16_t ADBUF0;          /*!< (@ 0x000000B0) A/D Data Buffer Register 0                                 */
4477 
4478         struct
4479         {
4480             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4481                                         *   registers that sequentially store all A/D converted values.
4482                                         *   The automatic clear function is not applied to these registers.           */
4483         } ADBUF0_b;
4484     };
4485 
4486     union
4487     {
4488         __IM uint16_t ADBUF1;          /*!< (@ 0x000000B2) A/D Data Buffer Register 1                                 */
4489 
4490         struct
4491         {
4492             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4493                                         *   registers that sequentially store all A/D converted values.
4494                                         *   The automatic clear function is not applied to these registers.           */
4495         } ADBUF1_b;
4496     };
4497 
4498     union
4499     {
4500         __IM uint16_t ADBUF2;          /*!< (@ 0x000000B4) A/D Data Buffer Register 2                                 */
4501 
4502         struct
4503         {
4504             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4505                                         *   registers that sequentially store all A/D converted values.
4506                                         *   The automatic clear function is not applied to these registers.           */
4507         } ADBUF2_b;
4508     };
4509 
4510     union
4511     {
4512         __IM uint16_t ADBUF3;          /*!< (@ 0x000000B6) A/D Data Buffer Register 3                                 */
4513 
4514         struct
4515         {
4516             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4517                                         *   registers that sequentially store all A/D converted values.
4518                                         *   The automatic clear function is not applied to these registers.           */
4519         } ADBUF3_b;
4520     };
4521 
4522     union
4523     {
4524         __IM uint16_t ADBUF4;          /*!< (@ 0x000000B8) A/D Data Buffer Register 4                                 */
4525 
4526         struct
4527         {
4528             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4529                                         *   registers that sequentially store all A/D converted values.
4530                                         *   The automatic clear function is not applied to these registers.           */
4531         } ADBUF4_b;
4532     };
4533 
4534     union
4535     {
4536         __IM uint16_t ADBUF5;          /*!< (@ 0x000000BA) A/D Data Buffer Register 5                                 */
4537 
4538         struct
4539         {
4540             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4541                                         *   registers that sequentially store all A/D converted values.
4542                                         *   The automatic clear function is not applied to these registers.           */
4543         } ADBUF5_b;
4544     };
4545 
4546     union
4547     {
4548         __IM uint16_t ADBUF6;          /*!< (@ 0x000000BC) A/D Data Buffer Register 6                                 */
4549 
4550         struct
4551         {
4552             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4553                                         *   registers that sequentially store all A/D converted values.
4554                                         *   The automatic clear function is not applied to these registers.           */
4555         } ADBUF6_b;
4556     };
4557 
4558     union
4559     {
4560         __IM uint16_t ADBUF7;          /*!< (@ 0x000000BE) A/D Data Buffer Register 7                                 */
4561 
4562         struct
4563         {
4564             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4565                                         *   registers that sequentially store all A/D converted values.
4566                                         *   The automatic clear function is not applied to these registers.           */
4567         } ADBUF7_b;
4568     };
4569 
4570     union
4571     {
4572         __IM uint16_t ADBUF8;          /*!< (@ 0x000000C0) A/D Data Buffer Register 8                                 */
4573 
4574         struct
4575         {
4576             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4577                                         *   registers that sequentially store all A/D converted values.
4578                                         *   The automatic clear function is not applied to these registers.           */
4579         } ADBUF8_b;
4580     };
4581 
4582     union
4583     {
4584         __IM uint16_t ADBUF9;          /*!< (@ 0x000000C2) A/D Data Buffer Register 9                                 */
4585 
4586         struct
4587         {
4588             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4589                                         *   registers that sequentially store all A/D converted values.
4590                                         *   The automatic clear function is not applied to these registers.           */
4591         } ADBUF9_b;
4592     };
4593 
4594     union
4595     {
4596         __IM uint16_t ADBUF10;         /*!< (@ 0x000000C4) A/D Data Buffer Register 10                                */
4597 
4598         struct
4599         {
4600             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4601                                         *   registers that sequentially store all A/D converted values.
4602                                         *   The automatic clear function is not applied to these registers.           */
4603         } ADBUF10_b;
4604     };
4605 
4606     union
4607     {
4608         __IM uint16_t ADBUF11;         /*!< (@ 0x000000C6) A/D Data Buffer Register 11                                */
4609 
4610         struct
4611         {
4612             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4613                                         *   registers that sequentially store all A/D converted values.
4614                                         *   The automatic clear function is not applied to these registers.           */
4615         } ADBUF11_b;
4616     };
4617 
4618     union
4619     {
4620         __IM uint16_t ADBUF12;         /*!< (@ 0x000000C8) A/D Data Buffer Register 12                                */
4621 
4622         struct
4623         {
4624             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4625                                         *   registers that sequentially store all A/D converted values.
4626                                         *   The automatic clear function is not applied to these registers.           */
4627         } ADBUF12_b;
4628     };
4629 
4630     union
4631     {
4632         __IM uint16_t ADBUF13;         /*!< (@ 0x000000CA) A/D Data Buffer Register 13                                */
4633 
4634         struct
4635         {
4636             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4637                                         *   registers that sequentially store all A/D converted values.
4638                                         *   The automatic clear function is not applied to these registers.           */
4639         } ADBUF13_b;
4640     };
4641 
4642     union
4643     {
4644         __IM uint16_t ADBUF14;         /*!< (@ 0x000000CC) A/D Data Buffer Register 14                                */
4645 
4646         struct
4647         {
4648             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4649                                         *   registers that sequentially store all A/D converted values.
4650                                         *   The automatic clear function is not applied to these registers.           */
4651         } ADBUF14_b;
4652     };
4653 
4654     union
4655     {
4656         __IM uint16_t ADBUF15;         /*!< (@ 0x000000CE) A/D Data Buffer Register 15                                */
4657 
4658         struct
4659         {
4660             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4661                                         *   registers that sequentially store all A/D converted values.
4662                                         *   The automatic clear function is not applied to these registers.           */
4663         } ADBUF15_b;
4664     };
4665 
4666     union
4667     {
4668         __IOM uint8_t ADBUFEN;         /*!< (@ 0x000000D0) A/D Data Buffer Enable Register                            */
4669 
4670         struct
4671         {
4672             __IOM uint8_t BUFEN : 1;   /*!< [0..0] Data Buffer Enable                                                 */
4673             uint8_t             : 7;
4674         } ADBUFEN_b;
4675     };
4676     __IM uint8_t RESERVED12;
4677 
4678     union
4679     {
4680         __IOM uint8_t ADBUFPTR;        /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register                           */
4681 
4682         struct
4683         {
4684             __IM uint8_t BUFPTR : 4;   /*!< [3..0] Data Buffer PointerThese bits indicate the number of
4685                                         *   data buffer to which the next A/D converted data is transferred.          */
4686             __IM uint8_t PTROVF : 1;   /*!< [4..4] Pointer Overflow Flag                                              */
4687             uint8_t             : 3;
4688         } ADBUFPTR_b;
4689     };
4690     __IM uint8_t  RESERVED13;
4691     __IM uint16_t RESERVED14[4];
4692     __IM uint8_t  RESERVED15;
4693 
4694     union
4695     {
4696         __IOM uint8_t ADSSTRL;         /*!< (@ 0x000000DD) A/D Sampling State Register L                              */
4697 
4698         struct
4699         {
4700             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (AN016-AN027)                                */
4701         } ADSSTRL_b;
4702     };
4703 
4704     union
4705     {
4706         __IOM uint8_t ADSSTRT;         /*!< (@ 0x000000DE) A/D Sampling State Register T                              */
4707 
4708         struct
4709         {
4710             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (temperature sensor output)                  */
4711         } ADSSTRT_b;
4712     };
4713 
4714     union
4715     {
4716         __IOM uint8_t ADSSTRO;         /*!< (@ 0x000000DF) A/D Sampling State Register O                              */
4717 
4718         struct
4719         {
4720             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (Internal reference voltage)                 */
4721         } ADSSTRO_b;
4722     };
4723 
4724     union
4725     {
4726         __IOM uint8_t ADSSTR[16];      /*!< (@ 0x000000E0) A/D Sampling State Registers                               */
4727 
4728         struct
4729         {
4730             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling time setting                                              */
4731         } ADSSTR_b[16];
4732     };
4733 
4734     union
4735     {
4736         __IOM uint16_t ADANIM;         /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register                     */
4737 
4738         struct
4739         {
4740             __IOM uint16_t ANIM0 : 1;  /*!< [0..0] Analog Channel Input Mode Select                                   */
4741             __IOM uint16_t ANIM1 : 1;  /*!< [1..1] Analog Channel Input Mode Select                                   */
4742             __IOM uint16_t ANIM2 : 1;  /*!< [2..2] Analog Channel Input Mode Select                                   */
4743             __IOM uint16_t ANIM3 : 1;  /*!< [3..3] Analog Channel Input Mode Select                                   */
4744             uint16_t             : 12;
4745         } ADANIM_b;
4746     };
4747 
4748     union
4749     {
4750         __IOM uint8_t ADCALEXE;        /*!< (@ 0x000000F2) A/D Calibration Execution Register                         */
4751 
4752         struct
4753         {
4754             uint8_t              : 6;
4755             __IM uint8_t  CALMON : 1;  /*!< [6..6] Calibration Status Flag                                            */
4756             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
4757         } ADCALEXE_b;
4758     };
4759     __IM uint8_t RESERVED16;
4760 
4761     union
4762     {
4763         __IOM uint8_t VREFAMPCNT;        /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control
4764                                           *                  Register                                                   */
4765 
4766         struct
4767         {
4768             __IOM uint8_t OLDETEN   : 1; /*!< [0..0] OLDET Enable                                                       */
4769             __IOM uint8_t VREFADCG  : 2; /*!< [2..1] VREFADC Output Voltage Control                                     */
4770             __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable                                                    */
4771             __IOM uint8_t BGREN     : 1; /*!< [4..4] BGR Enable                                                         */
4772             uint8_t                 : 2;
4773             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
4774         } VREFAMPCNT_b;
4775     };
4776     __IM uint8_t  RESERVED17;
4777     __IM uint16_t RESERVED18;
4778 
4779     union
4780     {
4781         __IOM uint16_t ADRD;           /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register                           */
4782 
4783         struct
4784         {
4785             __IM uint16_t AD : 16;     /*!< [15..0] Converted Value 15 to 0                                           */
4786         } ADRD_b;
4787     };
4788 
4789     union
4790     {
4791         __IM uint8_t ADRST;            /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register                        */
4792 
4793         struct
4794         {
4795             __IM uint8_t DIAGST : 2;   /*!< [1..0] Self-Diagnosis Status                                              */
4796             uint8_t             : 6;
4797         } ADRST_b;
4798     };
4799     __IM uint8_t  RESERVED19;
4800     __IM uint16_t RESERVED20[82];
4801 
4802     union
4803     {
4804         __IOM uint16_t ADPGACR;           /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register           */
4805 
4806         struct
4807         {
4808             __IOM uint16_t P000SEL0  : 1; /*!< [0..0] A through amplifier is enable for PGA P000                         */
4809             __IOM uint16_t P000SEL1  : 1; /*!< [1..1] The amplifier passing is enable for PGA P000                       */
4810             __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000                                  */
4811             __IOM uint16_t P000GEN   : 1; /*!< [3..3] PGA P000 gain setting and enable bit                               */
4812             __IOM uint16_t P001SEL0  : 1; /*!< [4..4] A through amplifier is enable for PGA P001                         */
4813             __IOM uint16_t P001SEL1  : 1; /*!< [5..5] The amplifier passing is enable for PGA P001                       */
4814             __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001                                  */
4815             __IOM uint16_t P001GEN   : 1; /*!< [7..7] PGA P001 gain setting and enable bit                               */
4816             __IOM uint16_t P002SEL0  : 1; /*!< [8..8] A through amplifier is enable for PGA P002                         */
4817             __IOM uint16_t P002SEL1  : 1; /*!< [9..9] The amplifier passing is enable for PGA P002                       */
4818             __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002                                */
4819             __IOM uint16_t P002GEN   : 1; /*!< [11..11] PGA P002 gain setting and enable bit                             */
4820             __IOM uint16_t P003SEL0  : 1; /*!< [12..12] A through amplifier is enable for PGA P003                       */
4821             __IOM uint16_t P003SEL1  : 1; /*!< [13..13] The amplifier passing is enable for PGA P003                     */
4822             __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003                                */
4823             __IOM uint16_t P003GEN   : 1; /*!< [15..15] PGA P003 gain setting and enable bit                             */
4824         } ADPGACR_b;
4825     };
4826 
4827     union
4828     {
4829         __IOM uint16_t ADPGAGS0;         /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting
4830                                           *                  Register 0                                                 */
4831 
4832         struct
4833         {
4834             __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=
4835                                           *   b) when the shingle end is input and each PGA P000 is set.
4836                                           *   When the differential motion is input, (ADPGSDCR0.P000GEN=1b)
4837                                           *   sets the gain magnification when the differential motion
4838                                           *   is input by the combination with ADPGSDCR0.P000DG 1:0.                    */
4839             __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=
4840                                           *   b) when the shingle end is input and each PGA P001 is set.
4841                                           *   When the differential motion is input, (ADPGSDCR0.P001GEN=1b)
4842                                           *   sets the gain magnification when the differential motion
4843                                           *   is input by the combination with ADPGSDCR0.P001DG 1:0.                    */
4844             __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of
4845                                           *   (ADPGSDCR0.P002GEN=0b) when the shingle end is input and
4846                                           *   each PGA P002 is set. When the differential motion is input,
4847                                           *   (ADPGSDCR0.P002GEN=1b) sets the gain magnification when
4848                                           *   the differential motion is input by the combination with
4849                                           *   ADPGSDCR0.P002DG 1:0.                                                     */
4850             __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of
4851                                           *   (ADPGSDCR0.P003GEN=0b) when the shingle end is input and
4852                                           *   each PGA P003 is set. When the differential motion is input,
4853                                           *   (ADPGSDCR0.P003GEN=1b) sets the gain magnification when
4854                                           *   the differential motion is input by the combination with
4855                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
4856         } ADPGAGS0_b;
4857     };
4858     __IM uint16_t RESERVED21[6];
4859 
4860     union
4861     {
4862         __IOM uint16_t ADPGADCR0;       /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential
4863                                          *                  Input Control Register                                     */
4864 
4865         struct
4866         {
4867             __IOM uint16_t P000DG : 2;  /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these
4868                                          *   bits are used, set {P000DEN, P000GEN} to 11b.                             */
4869             uint16_t               : 1;
4870             __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable                                     */
4871             __IOM uint16_t P001DG  : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these
4872                                          *   bits are used, set {P001DEN, P001GEN} to 11b.                             */
4873             uint16_t               : 1;
4874             __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable                                     */
4875             __IOM uint16_t P002DG  : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these
4876                                          *   bits are used, set {P002DEN, P002GEN} to 11b.                             */
4877             uint16_t               : 1;
4878             __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable                                   */
4879             __IOM uint16_t P003DG  : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these
4880                                          *   bits are used, set {P003DEN, P003GEN} to 11b.                             */
4881             uint16_t               : 1;
4882             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
4883         } ADPGADCR0_b;
4884     };
4885     __IM uint16_t RESERVED22;
4886 
4887     union
4888     {
4889         __IOM uint8_t ADPGADBS0;       /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential
4890                                         *                  Input Bias Select Register 0                               */
4891 
4892         struct
4893         {
4894             __IOM uint8_t P0BIAS : 1;  /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage
4895                                         *   SelectNOTE: This bit selects the input bias voltage value
4896                                         *   when differential inputs are used.                                        */
4897             uint8_t : 7;
4898         } ADPGADBS0_b;
4899     };
4900 
4901     union
4902     {
4903         __IOM uint8_t ADPGADBS1;       /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential
4904                                         *                  Input Bias Select Register 1                               */
4905 
4906         struct
4907         {
4908             __IOM uint8_t P3BIAS : 1;  /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE:
4909                                         *   This bit selects the input bias voltage value when differential
4910                                         *   inputs are used.                                                          */
4911             uint8_t : 7;
4912         } ADPGADBS1_b;
4913     };
4914     __IM uint16_t RESERVED23[21];
4915 
4916     union
4917     {
4918         __IOM uint8_t ADREFMON;        /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register            */
4919 
4920         struct
4921         {
4922             __IOM uint8_t PGAMON : 3;  /*!< [2..0] PGA Monitor Output Enable                                          */
4923             uint8_t              : 5;
4924         } ADREFMON_b;
4925     };
4926     __IM uint8_t  RESERVED24;
4927     __IM uint16_t RESERVED25;
4928 } R_ADC0_Type;                         /*!< Size = 484 (0x1e4)                                                        */
4929 
4930 /* =========================================================================================================================== */
4931 /* ================                                          R_PSCU                                           ================ */
4932 /* =========================================================================================================================== */
4933 
4934 /**
4935  * @brief Peripheral Security Control Unit (R_PSCU)
4936  */
4937 
4938 typedef struct                         /*!< (@ 0x400E0000) R_PSCU Structure                                           */
4939 {
4940     __IM uint32_t RESERVED;
4941 
4942     union
4943     {
4944         __IOM uint32_t PSARB;          /*!< (@ 0x00000004) Peripheral Security Attribution Register B                 */
4945 
4946         struct
4947         {
4948             uint32_t               : 1;
4949             __IOM uint32_t PSARB1  : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution               */
4950             __IOM uint32_t PSARB2  : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution               */
4951             __IOM uint32_t PSARB3  : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution                */
4952             uint32_t               : 2;
4953             __IM uint32_t  PSARB6  : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution               */
4954             __IOM uint32_t PSARB7  : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution               */
4955             __IOM uint32_t PSARB8  : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution               */
4956             __IOM uint32_t PSARB9  : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution               */
4957             uint32_t               : 1;
4958             __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution           */
4959             __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution           */
4960             uint32_t               : 2;
4961             __IM uint32_t PSARB15  : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0
4962                                          *   bit security attribution                                                  */
4963             __IM uint32_t PSARB16  : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution            */
4964             uint32_t               : 1;
4965             __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution           */
4966             __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution           */
4967             uint32_t               : 2;
4968             __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution            */
4969             __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution            */
4970             __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution            */
4971             __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution            */
4972             __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution            */
4973             __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution            */
4974             __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution            */
4975             __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution            */
4976             __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution            */
4977             __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution            */
4978         } PSARB_b;
4979     };
4980 
4981     union
4982     {
4983         __IOM uint32_t PSARC;           /*!< (@ 0x00000008) Peripheral Security Attribution Register C                 */
4984 
4985         struct
4986         {
4987             __IOM uint32_t PSARC0  : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution                */
4988             __IOM uint32_t PSARC1  : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution                */
4989             uint32_t               : 1;
4990             __IOM uint32_t PSARC3  : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution               */
4991             uint32_t               : 4;
4992             __IOM uint32_t PSARC8  : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution              */
4993             uint32_t               : 3;
4994             __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution           */
4995             __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution             */
4996             uint32_t               : 6;
4997             __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution             */
4998             uint32_t               : 6;
4999             __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution          */
5000             uint32_t               : 3;
5001             __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution            */
5002         } PSARC_b;
5003     };
5004 
5005     union
5006     {
5007         __IOM uint32_t PSARD;           /*!< (@ 0x0000000C) Peripheral Security Attribution Register D                 */
5008 
5009         struct
5010         {
5011             __IOM uint32_t PSARD0  : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution               */
5012             __IOM uint32_t PSARD1  : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution               */
5013             __IOM uint32_t PSARD2  : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution               */
5014             __IOM uint32_t PSARD3  : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution               */
5015             uint32_t               : 7;
5016             __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution            */
5017             __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution            */
5018             __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution            */
5019             __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution            */
5020             __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution            */
5021             __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution            */
5022             uint32_t               : 2;
5023             __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution          */
5024             __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution          */
5025             uint32_t               : 1;
5026             __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution             */
5027             uint32_t               : 2;
5028             __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution         */
5029             __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution         */
5030             __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution         */
5031             __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution         */
5032             uint32_t               : 3;
5033         } PSARD_b;
5034     };
5035 
5036     union
5037     {
5038         __IOM uint32_t PSARE;           /*!< (@ 0x00000010) Peripheral Security Attribution Register E                 */
5039 
5040         struct
5041         {
5042             __IOM uint32_t PSARE0  : 1; /*!< [0..0] WDT security attribution                                           */
5043             __IOM uint32_t PSARE1  : 1; /*!< [1..1] IWDT security attribution                                          */
5044             __IOM uint32_t PSARE2  : 1; /*!< [2..2] RTC security attribution                                           */
5045             uint32_t               : 11;
5046             __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution            */
5047             __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution            */
5048             uint32_t               : 6;
5049             __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution            */
5050             __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution            */
5051             __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution            */
5052             __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution            */
5053             __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution            */
5054             __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution            */
5055             __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution            */
5056             __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution            */
5057             __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution            */
5058             __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution            */
5059         } PSARE_b;
5060     };
5061 
5062     union
5063     {
5064         __IOM uint32_t MSSAR;          /*!< (@ 0x00000014) Module Stop Security Attribution Register                  */
5065 
5066         struct
5067         {
5068             __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution                       */
5069             __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution                       */
5070             __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution                        */
5071             __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution                        */
5072             uint32_t              : 28;
5073         } MSSAR_b;
5074     };
5075 
5076     union
5077     {
5078         __IM uint32_t CFSAMONA;        /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
5079                                         *                  A                                                          */
5080 
5081         struct
5082         {
5083             uint32_t           : 15;
5084             __IM uint32_t CFS2 : 9;    /*!< [23..15] Code Flash Secure area 2                                         */
5085             uint32_t           : 8;
5086         } CFSAMONA_b;
5087     };
5088 
5089     union
5090     {
5091         __IM uint32_t CFSAMONB;        /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
5092                                         *                  B                                                          */
5093 
5094         struct
5095         {
5096             uint32_t           : 10;
5097             __IM uint32_t CFS1 : 14;   /*!< [23..10] Code Flash Secure area 1                                         */
5098             uint32_t           : 8;
5099         } CFSAMONB_b;
5100     };
5101 
5102     union
5103     {
5104         __IM uint32_t DFSAMON;         /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register           */
5105 
5106         struct
5107         {
5108             uint32_t          : 10;
5109             __IM uint32_t DFS : 6;     /*!< [15..10] Data flash Secure area                                           */
5110             uint32_t          : 16;
5111         } DFSAMON_b;
5112     };
5113 
5114     union
5115     {
5116         __IM uint32_t SSAMONA;         /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A               */
5117 
5118         struct
5119         {
5120             uint32_t          : 13;
5121             __IM uint32_t SS2 : 8;     /*!< [20..13] SRAM Secure area 2                                               */
5122             uint32_t          : 11;
5123         } SSAMONA_b;
5124     };
5125 
5126     union
5127     {
5128         __IM uint32_t SSAMONB;         /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B               */
5129 
5130         struct
5131         {
5132             uint32_t          : 10;
5133             __IM uint32_t SS1 : 11;    /*!< [20..10] SRAM secure area 1                                               */
5134             uint32_t          : 11;
5135         } SSAMONB_b;
5136     };
5137 
5138     union
5139     {
5140         __IM uint32_t DLMMON;          /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register         */
5141 
5142         struct
5143         {
5144             __IM uint32_t DLMMON : 4;  /*!< [3..0] Device Lifecycle Management State Monitor                          */
5145             uint32_t             : 28;
5146         } DLMMON_b;
5147     };
5148 } R_PSCU_Type;                         /*!< Size = 48 (0x30)                                                          */
5149 
5150 /* =========================================================================================================================== */
5151 /* ================                                          R_AGT0                                           ================ */
5152 /* =========================================================================================================================== */
5153 
5154 /**
5155  * @brief Asynchronous General Purpose Timer (R_AGT0)
5156  */
5157 
5158 typedef struct                         /*!< (@ 0x40084000) R_AGT0 Structure                                           */
5159 {
5160     union
5161     {
5162         __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
5163 
5164         struct
5165         {
5166             __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written
5167                                         *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
5168                                         *   is forcibly stopped and set to FFFFH.                                     */
5169         } AGT_b;
5170     };
5171 
5172     union
5173     {
5174         __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
5175 
5176         struct
5177         {
5178             __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
5179                                          *   written to the TSTOP bit in the AGTCRn register, set to
5180                                          *   FFFFH                                                                     */
5181         } AGTCMA_b;
5182     };
5183 
5184     union
5185     {
5186         __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
5187 
5188         struct
5189         {
5190             __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
5191                                          *   written to the TSTOP bit in the AGTCR register, set to
5192                                          *   FFFFH                                                                     */
5193         } AGTCMB_b;
5194     };
5195     __IM uint16_t RESERVED;
5196 
5197     union
5198     {
5199         __IOM uint8_t AGTCR;           /*!< (@ 0x00000008) AGT Control Register                                       */
5200 
5201         struct
5202         {
5203             __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
5204             __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
5205             __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
5206             uint8_t              : 1;
5207             __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
5208             __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
5209             __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
5210             __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
5211         } AGTCR_b;
5212     };
5213 
5214     union
5215     {
5216         __IOM uint8_t AGTMR1;          /*!< (@ 0x00000009) AGT Mode Register 1                                        */
5217 
5218         struct
5219         {
5220             __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
5221             __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
5222             __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
5223             uint8_t              : 1;
5224         } AGTMR1_b;
5225     };
5226 
5227     union
5228     {
5229         __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000A) AGT Mode Register 2                                        */
5230 
5231         struct
5232         {
5233             __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
5234                                         *   ratio                                                                     */
5235             uint8_t           : 4;
5236             __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
5237         } AGTMR2_b;
5238     };
5239     __IM uint8_t RESERVED1;
5240 
5241     union
5242     {
5243         __IOM uint8_t AGTIOC;          /*!< (@ 0x0000000C) AGT I/O Control Register                                   */
5244 
5245         struct
5246         {
5247             __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
5248                                         *   mode.                                                                     */
5249             uint8_t             : 1;
5250             __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
5251             uint8_t             : 1;
5252             __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
5253             __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
5254         } AGTIOC_b;
5255     };
5256 
5257     union
5258     {
5259         __IOM uint8_t AGTISR;          /*!< (@ 0x0000000D) AGT Event Pin Select Register                              */
5260 
5261         struct
5262         {
5263             uint8_t            : 2;
5264             __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
5265             uint8_t            : 5;
5266         } AGTISR_b;
5267     };
5268 
5269     union
5270     {
5271         __IOM uint8_t AGTCMSR;         /*!< (@ 0x0000000E) AGT Compare Match Function Select Register                 */
5272 
5273         struct
5274         {
5275             __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
5276             __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
5277             __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
5278             uint8_t              : 1;
5279             __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
5280             __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
5281             __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
5282             uint8_t              : 1;
5283         } AGTCMSR_b;
5284     };
5285 
5286     union
5287     {
5288         __IOM uint8_t AGTIOSEL;        /*!< (@ 0x0000000F) AGT Pin Select Register                                    */
5289 
5290         struct
5291         {
5292             __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
5293             uint8_t            : 2;
5294             __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
5295             uint8_t            : 3;
5296         } AGTIOSEL_b;
5297     };
5298 } R_AGT0_Type;                         /*!< Size = 16 (0x10)                                                          */
5299 
5300 /* =========================================================================================================================== */
5301 /* ================                                          R_AGTW0                                          ================ */
5302 /* =========================================================================================================================== */
5303 
5304 /**
5305  * @brief Asynchronous General Purpose Timer (R_AGTW0)
5306  */
5307 
5308  #ifndef BSP_OVERRIDE_REG_R_AGTW0_TYPE
5309 
5310 typedef struct                         /*!< (@ 0x40084000) R_AGTW0 Structure                                          */
5311 {
5312     union
5313     {
5314         __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
5315 
5316         struct
5317         {
5318             __IOM uint32_t AGT : 32;   /*!< [31..0] 16bit counter and reload registerNOTE : When 1 is written
5319                                         *   to the TSTOP bit in the AGTCRn register, the 16-bit counter
5320                                         *   is forcibly stopped and set to FFFFH.                                     */
5321         } AGT_b;
5322     };
5323 
5324     union
5325     {
5326         __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
5327 
5328         struct
5329         {
5330             __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
5331                                          *   written to the TSTOP bit in the AGTCRn register, set to
5332                                          *   FFFFH                                                                     */
5333         } AGTCMA_b;
5334     };
5335 
5336     union
5337     {
5338         __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
5339 
5340         struct
5341         {
5342             __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
5343                                          *   written to the TSTOP bit in the AGTCR register, set to
5344                                          *   FFFFH                                                                     */
5345         } AGTCMB_b;
5346     };
5347 
5348     union
5349     {
5350         __IOM uint8_t AGTCR;           /*!< (@ 0x0000000C) AGT Control Register                                       */
5351 
5352         struct
5353         {
5354             __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
5355             __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
5356             __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
5357             uint8_t              : 1;
5358             __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
5359             __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
5360             __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
5361             __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
5362         } AGTCR_b;
5363     };
5364 
5365     union
5366     {
5367         __IOM uint8_t AGTMR1;          /*!< (@ 0x0000000D) AGT Mode Register 1                                        */
5368 
5369         struct
5370         {
5371             __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
5372             __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
5373             __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
5374             uint8_t              : 1;
5375         } AGTMR1_b;
5376     };
5377 
5378     union
5379     {
5380         __IOM uint8_t AGTMR2;          /*!< (@ 0x0000000E) AGT Mode Register 2                                        */
5381 
5382         struct
5383         {
5384             __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
5385                                         *   ratio                                                                     */
5386             uint8_t           : 4;
5387             __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
5388         } AGTMR2_b;
5389     };
5390 
5391     union
5392     {
5393         __IOM uint8_t AGTIOSEL;        /*!< (@ 0x0000000F) AGT Pin Select Register                                    */
5394 
5395         struct
5396         {
5397             uint8_t            : 4;
5398             __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
5399             uint8_t            : 3;
5400         } AGTIOSEL_b;
5401     };
5402 
5403     union
5404     {
5405         __IOM uint8_t AGTIOC;          /*!< (@ 0x00000010) AGT I/O Control Register                                   */
5406 
5407         struct
5408         {
5409             __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
5410                                         *   mode.                                                                     */
5411             uint8_t             : 1;
5412             __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
5413             uint8_t             : 1;
5414             __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
5415             __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
5416         } AGTIOC_b;
5417     };
5418 
5419     union
5420     {
5421         __IOM uint8_t AGTISR;          /*!< (@ 0x00000011) AGT Event Pin Select Register                              */
5422 
5423         struct
5424         {
5425             uint8_t            : 2;
5426             __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
5427             uint8_t            : 5;
5428         } AGTISR_b;
5429     };
5430 
5431     union
5432     {
5433         __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000012) AGT Compare Match Function Select Register                 */
5434 
5435         struct
5436         {
5437             __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
5438             __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
5439             __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
5440             uint8_t              : 1;
5441             __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
5442             __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
5443             __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
5444             uint8_t              : 1;
5445         } AGTCMSR_b;
5446     };
5447     __IM uint8_t RESERVED;
5448 } R_AGTW0_Type;                        /*!< Size = 20 (0x14)                                                          */
5449 
5450  #endif
5451 
5452 /* =========================================================================================================================== */
5453 /* ================                                           R_BUS                                           ================ */
5454 /* =========================================================================================================================== */
5455 
5456 /**
5457  * @brief Bus Interface (R_BUS)
5458  */
5459 
5460 typedef struct                          /*!< (@ 0x40003000) R_BUS Structure                                            */
5461 {
5462     __IOM R_BUS_CSa_Type CSa[8];        /*!< (@ 0x00000000) CS Registers                                               */
5463     __IM uint32_t        RESERVED[480];
5464     __IOM R_BUS_CSb_Type CSb[8];        /*!< (@ 0x00000800) CS Registers                                               */
5465 
5466     union
5467     {
5468         __IOM uint16_t CSRECEN;         /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register                */
5469 
5470         struct
5471         {
5472             __IOM uint16_t RCVEN0  : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable                       */
5473             __IOM uint16_t RCVEN1  : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable                       */
5474             __IOM uint16_t RCVEN2  : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable                       */
5475             __IOM uint16_t RCVEN3  : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable                       */
5476             __IOM uint16_t RCVEN4  : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable                       */
5477             __IOM uint16_t RCVEN5  : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable                       */
5478             __IOM uint16_t RCVEN6  : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable                       */
5479             __IOM uint16_t RCVEN7  : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable                       */
5480             __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable                    */
5481             __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable                    */
5482             __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable                  */
5483             __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable                  */
5484             __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable                  */
5485             __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable                  */
5486             __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable                  */
5487             __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable                  */
5488         } CSRECEN_b;
5489     };
5490     __IM uint16_t           RESERVED1;
5491     __IM uint32_t           RESERVED2[223];
5492     __IOM R_BUS_SDRAM_Type  SDRAM;      /*!< (@ 0x00000C00) SDRAM Registers                                            */
5493     __IM uint32_t           RESERVED3[235];
5494     __IOM R_BUS_BUSM_Type   BUSM[6];    /*!< (@ 0x00001000) Master Bus Control Register Array                          */
5495     __IM uint32_t           RESERVED4[58];
5496     __IOM R_BUS_BUSS_Type   BUSS[16];   /*!< (@ 0x00001100) Slave Bus Control Register Array                           */
5497     __IM uint32_t           RESERVED5[432];
5498     __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers                                        */
5499 } R_BUS_Type;                           /*!< Size = 6320 (0x18b0)                                                      */
5500 
5501 /* =========================================================================================================================== */
5502 /* ================                                           R_CAC                                           ================ */
5503 /* =========================================================================================================================== */
5504 
5505 /**
5506  * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC)
5507  */
5508 
5509 typedef struct                         /*!< (@ 0x40044600) R_CAC Structure                                            */
5510 {
5511     union
5512     {
5513         __IOM uint8_t CACR0;           /*!< (@ 0x00000000) CAC Control Register 0                                     */
5514 
5515         struct
5516         {
5517             __IOM uint8_t CFME : 1;    /*!< [0..0] Clock Frequency Measurement Enable.                                */
5518             uint8_t            : 7;
5519         } CACR0_b;
5520     };
5521 
5522     union
5523     {
5524         __IOM uint8_t CACR1;           /*!< (@ 0x00000001) CAC Control Register 1                                     */
5525 
5526         struct
5527         {
5528             __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable                                            */
5529             __IOM uint8_t FMCS    : 3; /*!< [3..1] Measurement Target Clock Select                                    */
5530             __IOM uint8_t TCSS    : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select           */
5531             __IOM uint8_t EDGES   : 2; /*!< [7..6] Valid Edge Select                                                  */
5532         } CACR1_b;
5533     };
5534 
5535     union
5536     {
5537         __IOM uint8_t CACR2;           /*!< (@ 0x00000002) CAC Control Register 2                                     */
5538 
5539         struct
5540         {
5541             __IOM uint8_t RPS  : 1;    /*!< [0..0] Reference Signal Select                                            */
5542             __IOM uint8_t RSCS : 3;    /*!< [3..1] Measurement Reference Clock Select                                 */
5543             __IOM uint8_t RCDS : 2;    /*!< [5..4] Measurement Reference Clock Frequency Division Ratio
5544                                         *   Select                                                                    */
5545             __IOM uint8_t DFS : 2;     /*!< [7..6] Digital Filter Selection                                           */
5546         } CACR2_b;
5547     };
5548 
5549     union
5550     {
5551         __IOM uint8_t CAICR;           /*!< (@ 0x00000003) CAC Interrupt Control Register                             */
5552 
5553         struct
5554         {
5555             __IOM uint8_t FERRIE : 1;  /*!< [0..0] Frequency Error Interrupt Request Enable                           */
5556             __IOM uint8_t MENDIE : 1;  /*!< [1..1] Measurement End Interrupt Request Enable                           */
5557             __IOM uint8_t OVFIE  : 1;  /*!< [2..2] Overflow Interrupt Request Enable                                  */
5558             uint8_t              : 1;
5559             __OM uint8_t FERRFCL : 1;  /*!< [4..4] FERRF Clear                                                        */
5560             __OM uint8_t MENDFCL : 1;  /*!< [5..5] MENDF Clear                                                        */
5561             __OM uint8_t OVFFCL  : 1;  /*!< [6..6] OVFF Clear                                                         */
5562             uint8_t              : 1;
5563         } CAICR_b;
5564     };
5565 
5566     union
5567     {
5568         __IM uint8_t CASTR;            /*!< (@ 0x00000004) CAC Status Register                                        */
5569 
5570         struct
5571         {
5572             __IM uint8_t FERRF : 1;    /*!< [0..0] Frequency Error Flag                                               */
5573             __IM uint8_t MENDF : 1;    /*!< [1..1] Measurement End Flag                                               */
5574             __IM uint8_t OVFF  : 1;    /*!< [2..2] Counter Overflow Flag                                              */
5575             uint8_t            : 5;
5576         } CASTR_b;
5577     };
5578     __IM uint8_t RESERVED;
5579 
5580     union
5581     {
5582         __IOM uint16_t CAULVR;          /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register                     */
5583 
5584         struct
5585         {
5586             __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores
5587                                          *   the upper-limit value of the frequency.                                   */
5588         } CAULVR_b;
5589     };
5590 
5591     union
5592     {
5593         __IOM uint16_t CALLVR;          /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register                     */
5594 
5595         struct
5596         {
5597             __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores
5598                                          *   the lower-limit value of the frequency.                                   */
5599         } CALLVR_b;
5600     };
5601 
5602     union
5603     {
5604         __IM uint16_t CACNTBR;          /*!< (@ 0x0000000A) CAC Counter Buffer Register                                */
5605 
5606         struct
5607         {
5608             __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains
5609                                          *   the counter value at the time a valid reference signal
5610                                          *   edge is input                                                             */
5611         } CACNTBR_b;
5612     };
5613 } R_CAC_Type;                           /*!< Size = 12 (0xc)                                                           */
5614 
5615 /* =========================================================================================================================== */
5616 /* ================                                          R_CAN0                                           ================ */
5617 /* =========================================================================================================================== */
5618 
5619 /**
5620  * @brief Controller Area Network (CAN) Module (R_CAN0)
5621  */
5622 
5623 typedef struct                         /*!< (@ 0x40050000) R_CAN0 Structure                                           */
5624 {
5625     __IM uint32_t        RESERVED[128];
5626     __IOM R_CAN0_MB_Type MB[32];       /*!< (@ 0x00000200) Mailbox                                                    */
5627 
5628     union
5629     {
5630         __IOM uint32_t MKR[8];         /*!< (@ 0x00000400) Mask Register                                              */
5631 
5632         struct
5633         {
5634             __IOM uint32_t EID : 18;   /*!< [17..0] Extended ID                                                       */
5635             __IOM uint32_t SID : 11;   /*!< [28..18] Standard ID                                                      */
5636             uint32_t           : 3;
5637         } MKR_b[8];
5638     };
5639 
5640     union
5641     {
5642         __IOM uint32_t FIDCR[2];       /*!< (@ 0x00000420) FIFO Received ID Compare Registers                         */
5643 
5644         struct
5645         {
5646             __IOM uint32_t EID : 18;   /*!< [17..0] Extended ID                                                       */
5647             __IOM uint32_t SID : 11;   /*!< [28..18] Standard ID                                                      */
5648             uint32_t           : 1;
5649             __IOM uint32_t RTR : 1;    /*!< [30..30] Remote Transmission Request                                      */
5650             __IOM uint32_t IDE : 1;    /*!< [31..31] ID Extension                                                     */
5651         } FIDCR_b[2];
5652     };
5653 
5654     union
5655     {
5656         __IOM uint32_t MKIVLR;         /*!< (@ 0x00000428) Mask Invalid Register                                      */
5657 
5658         struct
5659         {
5660             __IOM uint32_t MB0  : 1;   /*!< [0..0] mailbox 0 Mask Invalid                                             */
5661             __IOM uint32_t MB1  : 1;   /*!< [1..1] mailbox 1 Mask Invalid                                             */
5662             __IOM uint32_t MB2  : 1;   /*!< [2..2] mailbox 2 Mask Invalid                                             */
5663             __IOM uint32_t MB3  : 1;   /*!< [3..3] mailbox 3 Mask Invalid                                             */
5664             __IOM uint32_t MB4  : 1;   /*!< [4..4] mailbox 4 Mask Invalid                                             */
5665             __IOM uint32_t MB5  : 1;   /*!< [5..5] mailbox 5 Mask Invalid                                             */
5666             __IOM uint32_t MB6  : 1;   /*!< [6..6] mailbox 6 Mask Invalid                                             */
5667             __IOM uint32_t MB7  : 1;   /*!< [7..7] mailbox 7 Mask Invalid                                             */
5668             __IOM uint32_t MB8  : 1;   /*!< [8..8] mailbox 8 Mask Invalid                                             */
5669             __IOM uint32_t MB9  : 1;   /*!< [9..9] mailbox 9 Mask Invalid                                             */
5670             __IOM uint32_t MB10 : 1;   /*!< [10..10] mailbox 10 Mask Invalid                                          */
5671             __IOM uint32_t MB11 : 1;   /*!< [11..11] mailbox 11 Mask Invalid                                          */
5672             __IOM uint32_t MB12 : 1;   /*!< [12..12] mailbox 12 Mask Invalid                                          */
5673             __IOM uint32_t MB13 : 1;   /*!< [13..13] mailbox 13 Mask Invalid                                          */
5674             __IOM uint32_t MB14 : 1;   /*!< [14..14] mailbox 14 Mask Invalid                                          */
5675             __IOM uint32_t MB15 : 1;   /*!< [15..15] mailbox 15 Mask Invalid                                          */
5676             __IOM uint32_t MB16 : 1;   /*!< [16..16] mailbox 16 Mask Invalid                                          */
5677             __IOM uint32_t MB17 : 1;   /*!< [17..17] mailbox 17 Mask Invalid                                          */
5678             __IOM uint32_t MB18 : 1;   /*!< [18..18] mailbox 18 Mask Invalid                                          */
5679             __IOM uint32_t MB19 : 1;   /*!< [19..19] mailbox 19 Mask Invalid                                          */
5680             __IOM uint32_t MB20 : 1;   /*!< [20..20] mailbox 20 Mask Invalid                                          */
5681             __IOM uint32_t MB21 : 1;   /*!< [21..21] mailbox 21 Mask Invalid                                          */
5682             __IOM uint32_t MB22 : 1;   /*!< [22..22] mailbox 22 Mask Invalid                                          */
5683             __IOM uint32_t MB23 : 1;   /*!< [23..23] mailbox 23 Mask Invalid                                          */
5684             __IOM uint32_t MB24 : 1;   /*!< [24..24] mailbox 24 Mask Invalid                                          */
5685             __IOM uint32_t MB25 : 1;   /*!< [25..25] mailbox 25 Mask Invalid                                          */
5686             __IOM uint32_t MB26 : 1;   /*!< [26..26] mailbox 26 Mask Invalid                                          */
5687             __IOM uint32_t MB27 : 1;   /*!< [27..27] mailbox 27 Mask Invalid                                          */
5688             __IOM uint32_t MB28 : 1;   /*!< [28..28] mailbox 28 Mask Invalid                                          */
5689             __IOM uint32_t MB29 : 1;   /*!< [29..29] mailbox 29 Mask Invalid                                          */
5690             __IOM uint32_t MB30 : 1;   /*!< [30..30] mailbox 30 Mask Invalid                                          */
5691             __IOM uint32_t MB31 : 1;   /*!< [31..31] mailbox 31 Mask Invalid                                          */
5692         } MKIVLR_b;
5693     };
5694 
5695     union
5696     {
5697         union
5698         {
5699             __IOM uint32_t MIER;         /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register                          */
5700 
5701             struct
5702             {
5703                 __IOM uint32_t MB0  : 1; /*!< [0..0] mailbox 0 Interrupt Enable                                         */
5704                 __IOM uint32_t MB1  : 1; /*!< [1..1] mailbox 1 Interrupt Enable                                         */
5705                 __IOM uint32_t MB2  : 1; /*!< [2..2] mailbox 2 Interrupt Enable                                         */
5706                 __IOM uint32_t MB3  : 1; /*!< [3..3] mailbox 3 Interrupt Enable                                         */
5707                 __IOM uint32_t MB4  : 1; /*!< [4..4] mailbox 4 Interrupt Enable                                         */
5708                 __IOM uint32_t MB5  : 1; /*!< [5..5] mailbox 5 Interrupt Enable                                         */
5709                 __IOM uint32_t MB6  : 1; /*!< [6..6] mailbox 6 Interrupt Enable                                         */
5710                 __IOM uint32_t MB7  : 1; /*!< [7..7] mailbox 7 Interrupt Enable                                         */
5711                 __IOM uint32_t MB8  : 1; /*!< [8..8] mailbox 8 Interrupt Enable                                         */
5712                 __IOM uint32_t MB9  : 1; /*!< [9..9] mailbox 9 Interrupt Enable                                         */
5713                 __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable                                      */
5714                 __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable                                      */
5715                 __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable                                      */
5716                 __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable                                      */
5717                 __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable                                      */
5718                 __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable                                      */
5719                 __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable                                      */
5720                 __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable                                      */
5721                 __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable                                      */
5722                 __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable                                      */
5723                 __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable                                      */
5724                 __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable                                      */
5725                 __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable                                      */
5726                 __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable                                      */
5727                 __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable                                      */
5728                 __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable                                      */
5729                 __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable                                      */
5730                 __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable                                      */
5731                 __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable                                      */
5732                 __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable                                      */
5733                 __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable                                      */
5734                 __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable                                      */
5735             } MIER_b;
5736         };
5737 
5738         union
5739         {
5740             __IOM uint32_t MIER_FIFO;    /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox
5741                                           *                  Mode                                                       */
5742 
5743             struct
5744             {
5745                 __IOM uint32_t MB0  : 1; /*!< [0..0] mailbox 0 Interrupt Enable                                         */
5746                 __IOM uint32_t MB1  : 1; /*!< [1..1] mailbox 1 Interrupt Enable                                         */
5747                 __IOM uint32_t MB2  : 1; /*!< [2..2] mailbox 2 Interrupt Enable                                         */
5748                 __IOM uint32_t MB3  : 1; /*!< [3..3] mailbox 3 Interrupt Enable                                         */
5749                 __IOM uint32_t MB4  : 1; /*!< [4..4] mailbox 4 Interrupt Enable                                         */
5750                 __IOM uint32_t MB5  : 1; /*!< [5..5] mailbox 5 Interrupt Enable                                         */
5751                 __IOM uint32_t MB6  : 1; /*!< [6..6] mailbox 6 Interrupt Enable                                         */
5752                 __IOM uint32_t MB7  : 1; /*!< [7..7] mailbox 7 Interrupt Enable                                         */
5753                 __IOM uint32_t MB8  : 1; /*!< [8..8] mailbox 8 Interrupt Enable                                         */
5754                 __IOM uint32_t MB9  : 1; /*!< [9..9] mailbox 9 Interrupt Enable                                         */
5755                 __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable                                      */
5756                 __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable                                      */
5757                 __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable                                      */
5758                 __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable                                      */
5759                 __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable                                      */
5760                 __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable                                      */
5761                 __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable                                      */
5762                 __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable                                      */
5763                 __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable                                      */
5764                 __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable                                      */
5765                 __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable                                      */
5766                 __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable                                      */
5767                 __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable                                      */
5768                 __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable                                      */
5769                 __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable                                   */
5770                 __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control                */
5771                 uint32_t            : 2;
5772                 __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable                                    */
5773                 __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control                 */
5774                 uint32_t            : 2;
5775             } MIER_FIFO_b;
5776         };
5777     };
5778     __IM uint32_t RESERVED1[252];
5779 
5780     union
5781     {
5782         union
5783         {
5784             __IOM uint8_t MCTL_TX[32];       /*!< (@ 0x00000820) Message Control Register for Transmit                      */
5785 
5786             struct
5787             {
5788                 __IOM uint8_t SENTDATA  : 1; /*!< [0..0] Transmission Complete Flag                                         */
5789                 __IM uint8_t  TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox
5790                                               *   setting enabled)                                                          */
5791                 __IOM uint8_t TRMABT : 1;    /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting
5792                                               *   enabled)                                                                  */
5793                 uint8_t               : 1;
5794                 __IOM uint8_t ONESHOT : 1;   /*!< [4..4] One-Shot Enable                                                    */
5795                 uint8_t               : 1;
5796                 __IOM uint8_t RECREQ  : 1;   /*!< [6..6] Receive Mailbox Request                                            */
5797                 __IOM uint8_t TRMREQ  : 1;   /*!< [7..7] Transmit Mailbox Request                                           */
5798             } MCTL_TX_b[32];
5799         };
5800 
5801         union
5802         {
5803             __IOM uint8_t MCTL_RX[32];       /*!< (@ 0x00000820) Message Control Register for Receive                       */
5804 
5805             struct
5806             {
5807                 __IOM uint8_t NEWDATA   : 1; /*!< [0..0] Reception Complete Flag                                            */
5808                 __IM uint8_t  INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting
5809                                               *   enabled)                                                                  */
5810                 __IOM uint8_t MSGLOST : 1;   /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled)                 */
5811                 uint8_t               : 1;
5812                 __IOM uint8_t ONESHOT : 1;   /*!< [4..4] One-Shot Enable                                                    */
5813                 uint8_t               : 1;
5814                 __IOM uint8_t RECREQ  : 1;   /*!< [6..6] Receive Mailbox Request                                            */
5815                 __IOM uint8_t TRMREQ  : 1;   /*!< [7..7] Transmit Mailbox Request                                           */
5816             } MCTL_RX_b[32];
5817         };
5818     };
5819 
5820     union
5821     {
5822         __IOM uint16_t CTLR;           /*!< (@ 0x00000840) Control Register                                           */
5823 
5824         struct
5825         {
5826             __IOM uint16_t MBM  : 1;   /*!< [0..0] CAN Mailbox Mode Select                                            */
5827             __IOM uint16_t IDFM : 2;   /*!< [2..1] ID Format Mode Select                                              */
5828             __IOM uint16_t MLM  : 1;   /*!< [3..3] Message Lost Mode Select                                           */
5829             __IOM uint16_t TPM  : 1;   /*!< [4..4] Transmission Priority Mode Select                                  */
5830             __IOM uint16_t TSRC : 1;   /*!< [5..5] Time Stamp Counter Reset Command                                   */
5831             __IOM uint16_t TSPS : 2;   /*!< [7..6] Time Stamp Prescaler Select                                        */
5832             __IOM uint16_t CANM : 2;   /*!< [9..8] CAN Operating Mode Select                                          */
5833             __IOM uint16_t SLPM : 1;   /*!< [10..10] CAN Sleep Mode                                                   */
5834             __IOM uint16_t BOM  : 2;   /*!< [12..11] Bus-Off Recovery Mode by a program request                       */
5835             __IOM uint16_t RBOC : 1;   /*!< [13..13] Forcible Return From Bus-Off                                     */
5836             uint16_t            : 2;
5837         } CTLR_b;
5838     };
5839 
5840     union
5841     {
5842         __IM uint16_t STR;             /*!< (@ 0x00000842) Status Register                                            */
5843 
5844         struct
5845         {
5846             __IM uint16_t NDST  : 1;   /*!< [0..0] NEWDATA Status Flag                                                */
5847             __IM uint16_t SDST  : 1;   /*!< [1..1] SENTDATA Status Flag                                               */
5848             __IM uint16_t RFST  : 1;   /*!< [2..2] Receive FIFO Status Flag                                           */
5849             __IM uint16_t TFST  : 1;   /*!< [3..3] Transmit FIFO Status Flag                                          */
5850             __IM uint16_t NMLST : 1;   /*!< [4..4] Normal Mailbox Message Lost Status Flag                            */
5851             __IM uint16_t FMLST : 1;   /*!< [5..5] FIFO Mailbox Message Lost Status Flag                              */
5852             __IM uint16_t TABST : 1;   /*!< [6..6] Transmission Abort Status Flag                                     */
5853             __IM uint16_t EST   : 1;   /*!< [7..7] Error Status Flag                                                  */
5854             __IM uint16_t RSTST : 1;   /*!< [8..8] CAN Reset Status Flag                                              */
5855             __IM uint16_t HLTST : 1;   /*!< [9..9] CAN Halt Status Flag                                               */
5856             __IM uint16_t SLPST : 1;   /*!< [10..10] CAN Sleep Status Flag                                            */
5857             __IM uint16_t EPST  : 1;   /*!< [11..11] Error-Passive Status Flag                                        */
5858             __IM uint16_t BOST  : 1;   /*!< [12..12] Bus-Off Status Flag                                              */
5859             __IM uint16_t TRMST : 1;   /*!< [13..13] Transmit Status Flag (transmitter)                               */
5860             __IM uint16_t RECST : 1;   /*!< [14..14] Receive Status Flag (receiver)                                   */
5861             uint16_t            : 1;
5862         } STR_b;
5863     };
5864 
5865     union
5866     {
5867         __IOM uint32_t BCR;            /*!< (@ 0x00000844) Bit Configuration Register                                 */
5868 
5869         struct
5870         {
5871             __IOM uint32_t CCLKS : 1;  /*!< [0..0] CAN Clock Source Selection                                         */
5872             uint32_t             : 7;
5873             __IOM uint32_t TSEG2 : 3;  /*!< [10..8] Time Segment 2 Control                                            */
5874             uint32_t             : 1;
5875             __IOM uint32_t SJW   : 2;  /*!< [13..12] Resynchronization Jump Width Control                             */
5876             uint32_t             : 2;
5877             __IOM uint32_t BRP   : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the
5878                                         *   frequency of the CAN communication clock (fCANCLK).                       */
5879             uint32_t             : 2;
5880             __IOM uint32_t TSEG1 : 4;  /*!< [31..28] Time Segment 1 Control                                           */
5881         } BCR_b;
5882     };
5883 
5884     union
5885     {
5886         __IOM uint8_t RFCR;            /*!< (@ 0x00000848) Receive FIFO Control Register                              */
5887 
5888         struct
5889         {
5890             __IOM uint8_t RFE   : 1;   /*!< [0..0] Receive FIFO Enable                                                */
5891             __IM uint8_t  RFUST : 3;   /*!< [3..1] Receive FIFO Unread Message Number Status                          */
5892             __IOM uint8_t RFMLF : 1;   /*!< [4..4] Receive FIFO Message Lost Flag                                     */
5893             __IM uint8_t  RFFST : 1;   /*!< [5..5] Receive FIFO Full Status Flag                                      */
5894             __IM uint8_t  RFWST : 1;   /*!< [6..6] Receive FIFO Buffer Warning Status Flag                            */
5895             __IM uint8_t  RFEST : 1;   /*!< [7..7] Receive FIFO Empty Status Flag                                     */
5896         } RFCR_b;
5897     };
5898 
5899     union
5900     {
5901         __OM uint8_t RFPCR;            /*!< (@ 0x00000849) Receive FIFO Pointer Control Register                      */
5902 
5903         struct
5904         {
5905             __OM uint8_t RFPCR : 8;    /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented
5906                                         *   by writing FFh to RFPCR.                                                  */
5907         } RFPCR_b;
5908     };
5909 
5910     union
5911     {
5912         __IOM uint8_t TFCR;            /*!< (@ 0x0000084A) Transmit FIFO Control Register                             */
5913 
5914         struct
5915         {
5916             __IOM uint8_t TFE   : 1;   /*!< [0..0] Transmit FIFO Enable                                               */
5917             __IM uint8_t  TFUST : 3;   /*!< [3..1] Transmit FIFO Unsent Message Number Status                         */
5918             uint8_t             : 2;
5919             __IM uint8_t TFFST  : 1;   /*!< [6..6] Transmit FIFO Full Status                                          */
5920             __IM uint8_t TFEST  : 1;   /*!< [7..7] Transmit FIFO Empty Status                                         */
5921         } TFCR_b;
5922     };
5923 
5924     union
5925     {
5926         __OM uint8_t TFPCR;            /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register                     */
5927 
5928         struct
5929         {
5930             __OM uint8_t TFPCR : 8;    /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented
5931                                         *   by writing FFh to TFPCR.                                                  */
5932         } TFPCR_b;
5933     };
5934 
5935     union
5936     {
5937         __IOM uint8_t EIER;            /*!< (@ 0x0000084C) Error Interrupt Enable Register                            */
5938 
5939         struct
5940         {
5941             __IOM uint8_t BEIE  : 1;   /*!< [0..0] Bus Error Interrupt Enable                                         */
5942             __IOM uint8_t EWIE  : 1;   /*!< [1..1] Error-Warning Interrupt Enable                                     */
5943             __IOM uint8_t EPIE  : 1;   /*!< [2..2] Error-Passive Interrupt Enable                                     */
5944             __IOM uint8_t BOEIE : 1;   /*!< [3..3] Bus-Off Entry Interrupt Enable                                     */
5945             __IOM uint8_t BORIE : 1;   /*!< [4..4] Bus-Off Recovery Interrupt Enable                                  */
5946             __IOM uint8_t ORIE  : 1;   /*!< [5..5] Overrun Interrupt Enable                                           */
5947             __IOM uint8_t OLIE  : 1;   /*!< [6..6] Overload Frame Transmit Interrupt Enable                           */
5948             __IOM uint8_t BLIE  : 1;   /*!< [7..7] Bus Lock Interrupt Enable                                          */
5949         } EIER_b;
5950     };
5951 
5952     union
5953     {
5954         __IOM uint8_t EIFR;            /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register                      */
5955 
5956         struct
5957         {
5958             __IOM uint8_t BEIF  : 1;   /*!< [0..0] Bus Error Detect Flag                                              */
5959             __IOM uint8_t EWIF  : 1;   /*!< [1..1] Error-Warning Detect Flag                                          */
5960             __IOM uint8_t EPIF  : 1;   /*!< [2..2] Error-Passive Detect Flag                                          */
5961             __IOM uint8_t BOEIF : 1;   /*!< [3..3] Bus-Off Entry Detect Flag                                          */
5962             __IOM uint8_t BORIF : 1;   /*!< [4..4] Bus-Off Recovery Detect Flag                                       */
5963             __IOM uint8_t ORIF  : 1;   /*!< [5..5] Receive Overrun Detect Flag                                        */
5964             __IOM uint8_t OLIF  : 1;   /*!< [6..6] Overload Frame Transmission Detect Flag                            */
5965             __IOM uint8_t BLIF  : 1;   /*!< [7..7] Bus Lock Detect Flag                                               */
5966         } EIFR_b;
5967     };
5968 
5969     union
5970     {
5971         __IM uint8_t RECR;             /*!< (@ 0x0000084E) Receive Error Count Register                               */
5972 
5973         struct
5974         {
5975             __IM uint8_t RECR : 8;     /*!< [7..0] Receive error count functionRECR increments or decrements
5976                                         *   the counter value according to the error status of the
5977                                         *   CAN module during reception.                                              */
5978         } RECR_b;
5979     };
5980 
5981     union
5982     {
5983         __IM uint8_t TECR;             /*!< (@ 0x0000084F) Transmit Error Count Register                              */
5984 
5985         struct
5986         {
5987             __IM uint8_t TECR : 8;     /*!< [7..0] Transmit error count functionTECR increments or decrements
5988                                         *   the counter value according to the error status of the
5989                                         *   CAN module during transmission.                                           */
5990         } TECR_b;
5991     };
5992 
5993     union
5994     {
5995         __IOM uint8_t ECSR;            /*!< (@ 0x00000850) Error Code Store Register                                  */
5996 
5997         struct
5998         {
5999             __IOM uint8_t SEF  : 1;    /*!< [0..0] Stuff Error Flag                                                   */
6000             __IOM uint8_t FEF  : 1;    /*!< [1..1] Form Error Flag                                                    */
6001             __IOM uint8_t AEF  : 1;    /*!< [2..2] ACK Error Flag                                                     */
6002             __IOM uint8_t CEF  : 1;    /*!< [3..3] CRC Error Flag                                                     */
6003             __IOM uint8_t BE1F : 1;    /*!< [4..4] Bit Error (recessive) Flag                                         */
6004             __IOM uint8_t BE0F : 1;    /*!< [5..5] Bit Error (dominant) Flag                                          */
6005             __IOM uint8_t ADEF : 1;    /*!< [6..6] ACK Delimiter Error Flag                                           */
6006             __IOM uint8_t EDPM : 1;    /*!< [7..7] Error Display Mode Select                                          */
6007         } ECSR_b;
6008     };
6009 
6010     union
6011     {
6012         __IOM uint8_t CSSR;            /*!< (@ 0x00000851) Channel Search Support Register                            */
6013 
6014         struct
6015         {
6016             __IOM uint8_t CSSR : 8;    /*!< [7..0] When the value for the channel search is input, the channel
6017                                         *   number is output to MSSR.                                                 */
6018         } CSSR_b;
6019     };
6020 
6021     union
6022     {
6023         __IM uint8_t MSSR;             /*!< (@ 0x00000852) Mailbox Search Status Register                             */
6024 
6025         struct
6026         {
6027             __IM uint8_t MBNST : 5;    /*!< [4..0] Search Result Mailbox Number Status These bits output
6028                                         *   the smallest mailbox number that is searched in each mode
6029                                         *   of MSMR.                                                                  */
6030             uint8_t           : 2;
6031             __IM uint8_t SEST : 1;     /*!< [7..7] Search Result Status                                               */
6032         } MSSR_b;
6033     };
6034 
6035     union
6036     {
6037         __IOM uint8_t MSMR;            /*!< (@ 0x00000853) Mailbox Search Mode Register                               */
6038 
6039         struct
6040         {
6041             __IOM uint8_t MBSM : 2;    /*!< [1..0] Mailbox Search Mode Select                                         */
6042             uint8_t            : 6;
6043         } MSMR_b;
6044     };
6045 
6046     union
6047     {
6048         __IM uint16_t TSR;             /*!< (@ 0x00000854) Time Stamp Register                                        */
6049 
6050         struct
6051         {
6052             __IM uint16_t TSR : 16;    /*!< [15..0] Free-running counter value for the time stamp function            */
6053         } TSR_b;
6054     };
6055 
6056     union
6057     {
6058         __IOM uint16_t AFSR;           /*!< (@ 0x00000856) Acceptance Filter Support Register                         */
6059 
6060         struct
6061         {
6062             __IOM uint16_t AFSR : 16;  /*!< [15..0] After the standard ID of a received message is written,
6063                                         *   the value converted for data table search can be read.                    */
6064         } AFSR_b;
6065     };
6066 
6067     union
6068     {
6069         __IOM uint8_t TCR;             /*!< (@ 0x00000858) Test Control Register                                      */
6070 
6071         struct
6072         {
6073             __IOM uint8_t TSTE : 1;    /*!< [0..0] CAN Test Mode Enable                                               */
6074             __IOM uint8_t TSTM : 2;    /*!< [2..1] CAN Test Mode Select                                               */
6075             uint8_t            : 5;
6076         } TCR_b;
6077     };
6078     __IM uint8_t  RESERVED2;
6079     __IM uint16_t RESERVED3;
6080 } R_CAN0_Type;                         /*!< Size = 2140 (0x85c)                                                       */
6081 
6082 /* =========================================================================================================================== */
6083 /* ================                                          R_CANFD                                          ================ */
6084 /* =========================================================================================================================== */
6085 
6086 /**
6087  * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD)
6088  */
6089 
6090 typedef struct                         /*!< (@ 0x400B0000) R_CANFD Structure                                          */
6091 {
6092     __IOM R_CANFD_CFDC_Type CFDC[2];   /*!< (@ 0x00000000) Channel Control/Status                                     */
6093     __IM uint32_t           RESERVED[25];
6094 
6095     union
6096     {
6097         __IOM uint32_t CFDGCFG;         /*!< (@ 0x00000084) Global Configuration Register                              */
6098 
6099         struct
6100         {
6101             __IOM uint32_t TPRI   : 1;  /*!< [0..0] Transmission Priority                                              */
6102             __IOM uint32_t DCE    : 1;  /*!< [1..1] DLC Check Enable                                                   */
6103             __IOM uint32_t DRE    : 1;  /*!< [2..2] DLC Replacement Enable                                             */
6104             __IOM uint32_t MME    : 1;  /*!< [3..3] Mirror Mode Enable                                                 */
6105             __IOM uint32_t DCS    : 1;  /*!< [4..4] Data Link Controller Clock Select                                  */
6106             __IOM uint32_t CMPOC  : 1;  /*!< [5..5] CAN-FD message Payload overflow configuration                      */
6107             uint32_t              : 2;
6108             __IOM uint32_t TSP    : 4;  /*!< [11..8] Timestamp Prescaler                                               */
6109             __IOM uint32_t TSSS   : 1;  /*!< [12..12] Timestamp Source Select                                          */
6110             __IOM uint32_t TSBTCS : 3;  /*!< [15..13] Timestamp Bit Time Channel Select                                */
6111             __IOM uint32_t ITRCP  : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler                         */
6112         } CFDGCFG_b;
6113     };
6114 
6115     union
6116     {
6117         __IOM uint32_t CFDGCTR;         /*!< (@ 0x00000088) Global Control Register                                    */
6118 
6119         struct
6120         {
6121             __IOM uint32_t GMDC    : 2; /*!< [1..0] Global Mode Control                                                */
6122             __IOM uint32_t GSLPR   : 1; /*!< [2..2] Global Sleep Request                                               */
6123             uint32_t               : 5;
6124             __IOM uint32_t DEIE    : 1; /*!< [8..8] DLC check Interrupt Enable                                         */
6125             __IOM uint32_t MEIE    : 1; /*!< [9..9] Message lost Error Interrupt Enable                                */
6126             __IOM uint32_t THLEIE  : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable                      */
6127             __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable            */
6128             uint32_t               : 2;
6129             __IOM uint32_t QMEIE   : 1; /*!< [14..14] TXQ Message lost Error Interrupt Enable                          */
6130             __IOM uint32_t MOWEIE  : 1; /*!< [15..15] GW FIFO Message overwrite Error Interrupt Enable                 */
6131             __IOM uint32_t TSRST   : 1; /*!< [16..16] Timestamp Reset                                                  */
6132             __IOM uint32_t TSWR    : 1; /*!< [17..17] Timestamp Write                                                  */
6133             uint32_t               : 14;
6134         } CFDGCTR_b;
6135     };
6136 
6137     union
6138     {
6139         __IOM uint32_t CFDGSTS;         /*!< (@ 0x0000008C) Global Status Register                                     */
6140 
6141         struct
6142         {
6143             __IM uint32_t GRSTSTS  : 1; /*!< [0..0] Global Reset Status                                                */
6144             __IM uint32_t GHLTSTS  : 1; /*!< [1..1] Global Halt Status                                                 */
6145             __IM uint32_t GSLPSTS  : 1; /*!< [2..2] Global Sleep Status                                                */
6146             __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation                                          */
6147             uint32_t               : 28;
6148         } CFDGSTS_b;
6149     };
6150 
6151     union
6152     {
6153         __IOM uint32_t CFDGERFL;          /*!< (@ 0x00000090) Global Error Flag Register                                 */
6154 
6155         struct
6156         {
6157             __IOM uint32_t DEF       : 1; /*!< [0..0] DLC Error Flag                                                     */
6158             __IM uint32_t  MES       : 1; /*!< [1..1] Message Lost Error Status                                          */
6159             __IM uint32_t  THLES     : 1; /*!< [2..2] TX History List Entry Lost Error Status                            */
6160             __IOM uint32_t CMPOF     : 1; /*!< [3..3] CAN-FD message payload overflow Flag                               */
6161             __IM uint32_t  QOWES     : 1; /*!< [4..4] TXQ Message overwrite Error Status                                 */
6162             __IM uint32_t  OTBMLTSTS : 1; /*!< [5..5] OTB FIFO Message Lost Status                                       */
6163             __IM uint32_t  QMES      : 1; /*!< [6..6] TXQ Message Lost Error Status                                      */
6164             uint32_t                 : 1;
6165             __IOM uint32_t RXSFAIL0  : 1; /*!< [8..8] RX Scan Fail of Channel 0                                          */
6166             __IOM uint32_t RXSFAIL1  : 1; /*!< [9..9] RX Scan Fail of Channel 1                                          */
6167             uint32_t                 : 6;
6168             __IOM uint32_t EEF0      : 1; /*!< [16..16] ECC Error Flag for Channel 0                                     */
6169             __IOM uint32_t EEF1      : 1; /*!< [17..17] ECC Error Flag for Channel 1                                     */
6170             uint32_t                 : 14;
6171         } CFDGERFL_b;
6172     };
6173 
6174     union
6175     {
6176         __IOM uint32_t CFDGTSC;        /*!< (@ 0x00000094) Global Timestamp Counter Register                          */
6177 
6178         struct
6179         {
6180             __IM uint32_t TS : 16;     /*!< [15..0] Timestamp Value                                                   */
6181             uint32_t         : 16;
6182         } CFDGTSC_b;
6183     };
6184 
6185     union
6186     {
6187         __IOM uint32_t CFDGAFLECTR;    /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register       */
6188 
6189         struct
6190         {
6191             __IOM uint32_t AFLPN  : 4; /*!< [3..0] Acceptance Filter List Page Number                                 */
6192             uint32_t              : 4;
6193             __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable                          */
6194             uint32_t              : 23;
6195         } CFDGAFLECTR_b;
6196     };
6197 
6198     union
6199     {
6200         __IOM uint32_t CFDGAFLCFG0;    /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register
6201                                         *                  0                                                          */
6202 
6203         struct
6204         {
6205             __IOM uint32_t RNC1 : 9;   /*!< [8..0] Rule Number for Channel 1                                          */
6206             uint32_t            : 7;
6207             __IOM uint32_t RNC0 : 9;   /*!< [24..16] Rule Number for Channel 0                                        */
6208             uint32_t            : 7;
6209         } CFDGAFLCFG0_b;
6210     };
6211     __IM uint32_t RESERVED1[3];
6212 
6213     union
6214     {
6215         __IOM uint32_t CFDRMNB;        /*!< (@ 0x000000AC) RX Message Buffer Number Register                          */
6216 
6217         struct
6218         {
6219             __IOM uint32_t NRXMB : 8;  /*!< [7..0] Number of RX Message Buffers                                       */
6220             __IOM uint32_t RMPLS : 3;  /*!< [10..8] Reception Message Buffer Payload Data Size                        */
6221             uint32_t             : 21;
6222         } CFDRMNB_b;
6223     };
6224 
6225     union
6226     {
6227         __IOM uint32_t CFDRMND0;       /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0                      */
6228 
6229         struct
6230         {
6231             __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status                                 */
6232         } CFDRMND0_b;
6233     };
6234     __IM uint32_t RESERVED2[3];
6235 
6236     union
6237     {
6238         __IOM uint32_t CFDRFCC[8];     /*!< (@ 0x000000C0) RX FIFO Configuration / Control Registers                  */
6239 
6240         struct
6241         {
6242             __IOM uint32_t RFE    : 1; /*!< [0..0] RX FIFO Enable                                                     */
6243             __IOM uint32_t RFIE   : 1; /*!< [1..1] RX FIFO Interrupt Enable                                           */
6244             uint32_t              : 2;
6245             __IOM uint32_t RFPLS  : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration                            */
6246             uint32_t              : 1;
6247             __IOM uint32_t RFDC   : 3; /*!< [10..8] RX FIFO Depth Configuration                                       */
6248             uint32_t              : 1;
6249             __IOM uint32_t RFIM   : 1; /*!< [12..12] RX FIFO Interrupt Mode                                           */
6250             __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value                       */
6251             __IOM uint32_t RFFIE  : 1; /*!< [16..16] RX FIFO Full interrupt Enable                                    */
6252             uint32_t              : 15;
6253         } CFDRFCC_b[8];
6254     };
6255 
6256     union
6257     {
6258         __IOM uint32_t CFDRFSTS[8];    /*!< (@ 0x000000E0) RX FIFO Status Registers                                   */
6259 
6260         struct
6261         {
6262             __IM uint32_t  RFEMP : 1;  /*!< [0..0] RX FIFO Empty                                                      */
6263             __IM uint32_t  RFFLL : 1;  /*!< [1..1] RX FIFO Full                                                       */
6264             __IOM uint32_t RFMLT : 1;  /*!< [2..2] RX FIFO Message Lost                                               */
6265             __IOM uint32_t RFIF  : 1;  /*!< [3..3] RX FIFO Interrupt Flag                                             */
6266             uint32_t             : 4;
6267             __IM uint32_t  RFMC  : 8;  /*!< [15..8] RX FIFO Message Count                                             */
6268             __IOM uint32_t RFFIF : 1;  /*!< [16..16] RX FIFO Full Interrupt Flag                                      */
6269             uint32_t             : 15;
6270         } CFDRFSTS_b[8];
6271     };
6272 
6273     union
6274     {
6275         __IOM uint32_t CFDRFPCTR[8];   /*!< (@ 0x00000100) RX FIFO Pointer Control Registers                          */
6276 
6277         struct
6278         {
6279             __OM uint32_t RFPC : 8;    /*!< [7..0] RX FIFO Pointer Control                                            */
6280             uint32_t           : 24;
6281         } CFDRFPCTR_b[8];
6282     };
6283 
6284     union
6285     {
6286         __IOM uint32_t CFDCFCC[6];     /*!< (@ 0x00000120) Common FIFO Configuration / Control Registers              */
6287 
6288         struct
6289         {
6290             __IOM uint32_t CFE    : 1; /*!< [0..0] Common FIFO Enable                                                 */
6291             __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable                                    */
6292             __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable                                    */
6293             uint32_t              : 1;
6294             __IOM uint32_t CFPLS  : 3; /*!< [6..4] Common FIFO Payload Data size configuration                        */
6295             uint32_t              : 1;
6296             __IOM uint32_t CFM    : 2; /*!< [9..8] Common FIFO Mode                                                   */
6297             __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select                         */
6298             __IOM uint32_t CFITR  : 1; /*!< [11..11] Common FIFO Interval Timer Resolution                            */
6299             __IOM uint32_t CFIM   : 1; /*!< [12..12] Common FIFO Interrupt Mode                                       */
6300             __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value                   */
6301             __IOM uint32_t CFTML  : 5; /*!< [20..16] Common FIFO TX Message Buffer Link                               */
6302             __IOM uint32_t CFDC   : 3; /*!< [23..21] Common FIFO Depth Configuration                                  */
6303             __IOM uint32_t CFITT  : 8; /*!< [31..24] Common FIFO Interval Transmission Time                           */
6304         } CFDCFCC_b[6];
6305     };
6306     __IM uint32_t RESERVED3[18];
6307 
6308     union
6309     {
6310         __IOM uint32_t CFDCFCCE[6];      /*!< (@ 0x00000180) Common FIFO Configuration / Control Enhancement
6311                                           *                  Registers                                                  */
6312 
6313         struct
6314         {
6315             __IOM uint32_t CFFIE    : 1; /*!< [0..0] Common FIFO Full interrupt Enable                                  */
6316             __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable                   */
6317             __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable                */
6318             uint32_t                : 5;
6319             __IOM uint32_t CFMOWM   : 1; /*!< [8..8] Common FIFO message overwrite mode                                 */
6320             uint32_t                : 7;
6321             __IOM uint32_t CFBME    : 1; /*!< [16..16] Common FIFO Buffering Mode Enable                                */
6322             uint32_t                : 15;
6323         } CFDCFCCE_b[6];
6324     };
6325     __IM uint32_t RESERVED4[18];
6326 
6327     union
6328     {
6329         __IOM uint32_t CFDCFSTS[6];      /*!< (@ 0x000001E0) Common FIFO Status Registers                               */
6330 
6331         struct
6332         {
6333             __IM uint32_t  CFEMP    : 1; /*!< [0..0] Common FIFO Empty                                                  */
6334             __IM uint32_t  CFFLL    : 1; /*!< [1..1] Common FIFO Full                                                   */
6335             __IOM uint32_t CFMLT    : 1; /*!< [2..2] Common FIFO Message Lost                                           */
6336             __IOM uint32_t CFRXIF   : 1; /*!< [3..3] Common RX FIFO Interrupt Flag                                      */
6337             __IOM uint32_t CFTXIF   : 1; /*!< [4..4] Common TX FIFO Interrupt Flag                                      */
6338             uint32_t                : 3;
6339             __IM uint32_t  CFMC     : 8; /*!< [15..8] Common FIFO Message Count                                         */
6340             __IOM uint32_t CFFIF    : 1; /*!< [16..16] Common FIFO Full Interrupt Flag                                  */
6341             __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag                   */
6342             __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag                */
6343             uint32_t                : 5;
6344             __IOM uint32_t CFMOW    : 1; /*!< [24..24] Common FIFO message overwrite                                    */
6345             uint32_t                : 7;
6346         } CFDCFSTS_b[6];
6347     };
6348     __IM uint32_t RESERVED5[18];
6349 
6350     union
6351     {
6352         __IOM uint32_t CFDCFPCTR[6];   /*!< (@ 0x00000240) Common FIFO Pointer Control Registers                      */
6353 
6354         struct
6355         {
6356             __OM uint32_t CFPC : 8;    /*!< [7..0] Common FIFO Pointer Control                                        */
6357             uint32_t           : 24;
6358         } CFDCFPCTR_b[6];
6359     };
6360     __IM uint32_t RESERVED6[18];
6361 
6362     union
6363     {
6364         __IM uint32_t CFDFESTS;        /*!< (@ 0x000002A0) FIFO Empty Status Register                                 */
6365 
6366         struct
6367         {
6368             __IM uint32_t RFXEMP : 8;  /*!< [7..0] RX FIF0 Empty Status                                               */
6369             __IM uint32_t CFXEMP : 6;  /*!< [13..8] Common FIF0 Empty Status                                          */
6370             uint32_t             : 18;
6371         } CFDFESTS_b;
6372     };
6373 
6374     union
6375     {
6376         __IM uint32_t CFDFFSTS;        /*!< (@ 0x000002A4) FIFO Full Status Register                                  */
6377 
6378         struct
6379         {
6380             __IM uint32_t RFXFLL : 8;  /*!< [7..0] RX FIF0 Full Status                                                */
6381             __IM uint32_t CFXFLL : 6;  /*!< [13..8] Common FIF0 Full Status                                           */
6382             uint32_t             : 18;
6383         } CFDFFSTS_b;
6384     };
6385 
6386     union
6387     {
6388         __IM uint32_t CFDFMSTS;        /*!< (@ 0x000002A8) FIFO Message Lost Status Register                          */
6389 
6390         struct
6391         {
6392             __IM uint32_t RFXMLT : 8;  /*!< [7..0] RX FIFO Msg Lost Status                                            */
6393             __IM uint32_t CFXMLT : 6;  /*!< [13..8] Common FIFO Msg Lost Status                                       */
6394             uint32_t             : 18;
6395         } CFDFMSTS_b;
6396     };
6397 
6398     union
6399     {
6400         __IOM uint32_t CFDRFISTS;      /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register                     */
6401 
6402         struct
6403         {
6404             __IM uint32_t RFXIF   : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status                                   */
6405             uint32_t              : 8;
6406             __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status                            */
6407             uint32_t              : 8;
6408         } CFDRFISTS_b;
6409     };
6410 
6411     union
6412     {
6413         __IOM uint32_t CFDCFRISTS;     /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register              */
6414 
6415         struct
6416         {
6417             __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO [x] RX Interrupt Flag Status                           */
6418             uint32_t              : 26;
6419         } CFDCFRISTS_b;
6420     };
6421 
6422     union
6423     {
6424         __IOM uint32_t CFDCFTISTS;     /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register              */
6425 
6426         struct
6427         {
6428             __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO [x] TX Interrupt Flag Status                           */
6429             uint32_t              : 26;
6430         } CFDCFTISTS_b;
6431     };
6432 
6433     union
6434     {
6435         __IM uint32_t CFDCFOFRISTS;      /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status
6436                                           *                  Register                                                   */
6437 
6438         struct
6439         {
6440             __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO [x] One Frame RX Interrupt Flag Status                 */
6441             uint32_t                : 26;
6442         } CFDCFOFRISTS_b;
6443     };
6444 
6445     union
6446     {
6447         __IM uint32_t CFDCFOFTISTS;      /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status
6448                                           *                  Register                                                   */
6449 
6450         struct
6451         {
6452             __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO [x] One Frame TX Interrupt Flag Status                 */
6453             uint32_t                : 26;
6454         } CFDCFOFTISTS_b;
6455     };
6456 
6457     union
6458     {
6459         __IM uint32_t CFDCFMOWSTS;     /*!< (@ 0x000002C0) Common FIFO Message Over Write Status Register             */
6460 
6461         struct
6462         {
6463             __IM uint32_t CFXMOW : 6;  /*!< [5..0] Common FIFO [x] Massage overwrite status                           */
6464             uint32_t             : 26;
6465         } CFDCFMOWSTS_b;
6466     };
6467 
6468     union
6469     {
6470         __IM uint32_t CFDFFFSTS;       /*!< (@ 0x000002C4) FIFO FDC Full Status Register                              */
6471 
6472         struct
6473         {
6474             __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC level full Status                                      */
6475             __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC level full Status                                 */
6476             uint32_t              : 18;
6477         } CFDFFFSTS_b;
6478     };
6479     __IM uint32_t RESERVED7[2];
6480 
6481     union
6482     {
6483         __IOM uint8_t CFDTMC[128];     /*!< (@ 0x000002D0) TX Message Buffer Control Registers                        */
6484 
6485         struct
6486         {
6487             __IOM uint8_t TMTR  : 1;   /*!< [0..0] TX Message Buffer Transmission Request                             */
6488             __IOM uint8_t TMTAR : 1;   /*!< [1..1] TX Message Buffer Transmission abort Request                       */
6489             __IOM uint8_t TMOM  : 1;   /*!< [2..2] TX Message Buffer One-shot Mode                                    */
6490             uint8_t             : 5;
6491         } CFDTMC_b[128];
6492     };
6493     __IM uint32_t RESERVED8[288];
6494 
6495     union
6496     {
6497         __IOM uint8_t CFDTMSTS[128];   /*!< (@ 0x000007D0) TX Message Buffer Status Registers                         */
6498 
6499         struct
6500         {
6501             __IM uint8_t  TMTSTS : 1;  /*!< [0..0] TX Message Buffer Transmission Status                              */
6502             __IOM uint8_t TMTRF  : 2;  /*!< [2..1] TX Message Buffer Transmission Result Flag                         */
6503             __IM uint8_t  TMTRM  : 1;  /*!< [3..3] TX Message Buffer Transmission Request Mirrored                    */
6504             __IM uint8_t  TMTARM : 1;  /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored              */
6505             uint8_t              : 3;
6506         } CFDTMSTS_b[128];
6507     };
6508     __IM uint32_t RESERVED9[288];
6509 
6510     union
6511     {
6512         __IM uint32_t CFDTMTRSTS[4];       /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status
6513                                             *                  Register                                                   */
6514 
6515         struct
6516         {
6517             __IM uint32_t CFDTMTRSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Request Status                      */
6518             uint32_t                  : 24;
6519         } CFDTMTRSTS_b[4];
6520     };
6521     __IM uint32_t RESERVED10[36];
6522 
6523     union
6524     {
6525         __IM uint32_t CFDTMTARSTS[4];       /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request
6526                                              *                  Status Register                                            */
6527 
6528         struct
6529         {
6530             __IM uint32_t CFDTMTARSTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Request Status                */
6531             uint32_t                   : 24;
6532         } CFDTMTARSTS_b[4];
6533     };
6534     __IM uint32_t RESERVED11[36];
6535 
6536     union
6537     {
6538         __IM uint32_t CFDTMTCSTS[4];       /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status
6539                                             *                  Register                                                   */
6540 
6541         struct
6542         {
6543             __IM uint32_t CFDTMTCSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Completion Status                   */
6544             uint32_t                  : 24;
6545         } CFDTMTCSTS_b[4];
6546     };
6547     __IM uint32_t RESERVED12[36];
6548 
6549     union
6550     {
6551         __IM uint32_t CFDTMTASTS[4];       /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register       */
6552 
6553         struct
6554         {
6555             __IM uint32_t CFDTMTASTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Status                        */
6556             uint32_t                  : 24;
6557         } CFDTMTASTS_b[4];
6558     };
6559     __IM uint32_t RESERVED13[36];
6560 
6561     union
6562     {
6563         __IOM uint32_t CFDTMIEC[4];    /*!< (@ 0x00000F50) TX Message Buffer Interrupt Enable Configuration
6564                                         *                  Register                                                   */
6565 
6566         struct
6567         {
6568             __IOM uint32_t TMIEg : 8;  /*!< [7..0] TX Message Buffer Interrupt Enable                                 */
6569             uint32_t             : 24;
6570         } CFDTMIEC_b[4];
6571     };
6572     __IM uint32_t RESERVED14[40];
6573 
6574     union
6575     {
6576         __IOM uint32_t CFDTXQCC0[2];      /*!< (@ 0x00001000) TX Queue Configuration / Control Registers 0               */
6577 
6578         struct
6579         {
6580             __IOM uint32_t TXQE      : 1; /*!< [0..0] TX Queue Enable                                                    */
6581             __IOM uint32_t TXQGWE    : 1; /*!< [1..1] TX Queue Gateway Mode Enable                                       */
6582             uint32_t                 : 3;
6583             __IOM uint32_t TXQTXIE   : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
6584             uint32_t                 : 1;
6585             __IOM uint32_t TXQIM     : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
6586             __IOM uint32_t TXQDC     : 5; /*!< [12..8] TX Queue Depth Configuration                                      */
6587             uint32_t                 : 3;
6588             __IOM uint32_t TXQFIE    : 1; /*!< [16..16] TXQ Full interrupt Enable                                        */
6589             __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable                         */
6590             __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable                      */
6591             uint32_t                 : 13;
6592         } CFDTXQCC0_b[2];
6593     };
6594     __IM uint32_t RESERVED15[6];
6595 
6596     union
6597     {
6598         __IOM uint32_t CFDTXQSTS0[2];     /*!< (@ 0x00001020) TX Queue Status Registers 0                                */
6599 
6600         struct
6601         {
6602             __IM uint32_t  TXQEMP    : 1; /*!< [0..0] TX Queue Empty                                                     */
6603             __IM uint32_t  TXQFLL    : 1; /*!< [1..1] TX Queue Full                                                      */
6604             __IOM uint32_t TXQTXIF   : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
6605             uint32_t                 : 5;
6606             __IM uint32_t TXQMC      : 6; /*!< [13..8] TX Queue Message Count                                            */
6607             uint32_t                 : 2;
6608             __IOM uint32_t TXQFIF    : 1; /*!< [16..16] TXQ Full Interrupt Flag                                          */
6609             __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag                           */
6610             __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag                        */
6611             __IOM uint32_t TXQMLT    : 1; /*!< [19..19] TXQ Message Lost                                                 */
6612             uint32_t                 : 12;
6613         } CFDTXQSTS0_b[2];
6614     };
6615     __IM uint32_t RESERVED16[6];
6616 
6617     union
6618     {
6619         __IOM uint32_t CFDTXQPCTR0[2]; /*!< (@ 0x00001040) TX Queue Pointer Control Registers 0                       */
6620 
6621         struct
6622         {
6623             __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
6624             uint32_t            : 24;
6625         } CFDTXQPCTR0_b[2];
6626     };
6627     __IM uint32_t RESERVED17[6];
6628 
6629     union
6630     {
6631         __IOM uint32_t CFDTXQCC1[2];      /*!< (@ 0x00001060) TX Queue Configuration / Control Registers 1               */
6632 
6633         struct
6634         {
6635             __IOM uint32_t TXQE      : 1; /*!< [0..0] TX Queue Enable                                                    */
6636             __IOM uint32_t TXQGWE    : 1; /*!< [1..1] TX Queue Gateway Mode Enable                                       */
6637             uint32_t                 : 3;
6638             __IOM uint32_t TXQTXIE   : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
6639             uint32_t                 : 1;
6640             __IOM uint32_t TXQIM     : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
6641             __IOM uint32_t TXQDC     : 5; /*!< [12..8] TX Queue Depth Configuration                                      */
6642             uint32_t                 : 3;
6643             __IOM uint32_t TXQFIE    : 1; /*!< [16..16] TXQ Full Interrupt Enable                                        */
6644             __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable                         */
6645             __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable                      */
6646             uint32_t                 : 13;
6647         } CFDTXQCC1_b[2];
6648     };
6649     __IM uint32_t RESERVED18[6];
6650 
6651     union
6652     {
6653         __IOM uint32_t CFDTXQSTS1[2];     /*!< (@ 0x00001080) TX Queue Status Registers 1                                */
6654 
6655         struct
6656         {
6657             __IM uint32_t  TXQEMP    : 1; /*!< [0..0] TX Queue Empty                                                     */
6658             __IM uint32_t  TXQFLL    : 1; /*!< [1..1] TX Queue Full                                                      */
6659             __IOM uint32_t TXQTXIF   : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
6660             uint32_t                 : 5;
6661             __IM uint32_t TXQMC      : 6; /*!< [13..8] TX Queue Message Count                                            */
6662             uint32_t                 : 2;
6663             __IOM uint32_t TXQFIF    : 1; /*!< [16..16] TXQ Full Interrupt Flag                                          */
6664             __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag                           */
6665             __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag                        */
6666             __IOM uint32_t TXQMLT    : 1; /*!< [19..19] TXQ Message Lost                                                 */
6667             uint32_t                 : 12;
6668         } CFDTXQSTS1_b[2];
6669     };
6670     __IM uint32_t RESERVED19[6];
6671 
6672     union
6673     {
6674         __IOM uint32_t CFDTXQPCTR1[2]; /*!< (@ 0x000010A0) TX Queue Pointer Control Registers 1                       */
6675 
6676         struct
6677         {
6678             __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
6679             uint32_t            : 24;
6680         } CFDTXQPCTR1_b[2];
6681     };
6682     __IM uint32_t RESERVED20[6];
6683 
6684     union
6685     {
6686         __IOM uint32_t CFDTXQCC2[2];      /*!< (@ 0x000010C0) TX Queue Configuration / Control Registers 2               */
6687 
6688         struct
6689         {
6690             __IOM uint32_t TXQE      : 1; /*!< [0..0] TX Queue Enable                                                    */
6691             __IOM uint32_t TXQGWE    : 1; /*!< [1..1] TX Queue Gateway Mode Enable                                       */
6692             uint32_t                 : 3;
6693             __IOM uint32_t TXQTXIE   : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
6694             uint32_t                 : 1;
6695             __IOM uint32_t TXQIM     : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
6696             __IOM uint32_t TXQDC     : 5; /*!< [12..8] TX Queue Depth Configuration                                      */
6697             uint32_t                 : 3;
6698             __IOM uint32_t TXQFIE    : 1; /*!< [16..16] TXQ Full interrupt Enable                                        */
6699             __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable                         */
6700             __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable                      */
6701             uint32_t                 : 13;
6702         } CFDTXQCC2_b[2];
6703     };
6704     __IM uint32_t RESERVED21[6];
6705 
6706     union
6707     {
6708         __IOM uint32_t CFDTXQSTS2[2];     /*!< (@ 0x000010E0) TX Queue Status Registers 2                                */
6709 
6710         struct
6711         {
6712             __IM uint32_t  TXQEMP    : 1; /*!< [0..0] TX Queue Empty                                                     */
6713             __IM uint32_t  TXQFLL    : 1; /*!< [1..1] TX Queue Full                                                      */
6714             __IOM uint32_t TXQTXIF   : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
6715             uint32_t                 : 5;
6716             __IM uint32_t TXQMC      : 6; /*!< [13..8] TX Queue Message Count                                            */
6717             uint32_t                 : 2;
6718             __IOM uint32_t TXQFIF    : 1; /*!< [16..16] TXQ Full Interrupt Flag                                          */
6719             __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag                           */
6720             __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag                        */
6721             __IOM uint32_t TXQMLT    : 1; /*!< [19..19] TXQ Message Lost                                                 */
6722             uint32_t                 : 12;
6723         } CFDTXQSTS2_b[2];
6724     };
6725     __IM uint32_t RESERVED22[6];
6726 
6727     union
6728     {
6729         __IOM uint32_t CFDTXQPCTR2[2]; /*!< (@ 0x00001100) TX Queue Pointer Control Registers 2                       */
6730 
6731         struct
6732         {
6733             __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
6734             uint32_t            : 24;
6735         } CFDTXQPCTR2_b[2];
6736     };
6737     __IM uint32_t RESERVED23[6];
6738 
6739     union
6740     {
6741         __IOM uint32_t CFDTXQCC3[2];      /*!< (@ 0x00001120) TX Queue Configuration / Control Registers 3               */
6742 
6743         struct
6744         {
6745             __IOM uint32_t TXQE      : 1; /*!< [0..0] TX Queue Enable                                                    */
6746             uint32_t                 : 4;
6747             __IOM uint32_t TXQTXIE   : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
6748             uint32_t                 : 1;
6749             __IOM uint32_t TXQIM     : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
6750             __IOM uint32_t TXQDC     : 5; /*!< [12..8] TX Queue Depth Configuration                                      */
6751             uint32_t                 : 5;
6752             __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable                      */
6753             uint32_t                 : 13;
6754         } CFDTXQCC3_b[2];
6755     };
6756     __IM uint32_t RESERVED24[6];
6757 
6758     union
6759     {
6760         __IOM uint32_t CFDTXQSTS3[2];     /*!< (@ 0x00001140) TX Queue Status Registers 3                                */
6761 
6762         struct
6763         {
6764             __IM uint32_t  TXQEMP    : 1; /*!< [0..0] TX Queue Empty                                                     */
6765             __IM uint32_t  TXQFLL    : 1; /*!< [1..1] TX Queue Full                                                      */
6766             __IOM uint32_t TXQTXIF   : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
6767             uint32_t                 : 5;
6768             __IM uint32_t TXQMC      : 6; /*!< [13..8] TX Queue Message Count                                            */
6769             uint32_t                 : 4;
6770             __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag                        */
6771             uint32_t                 : 13;
6772         } CFDTXQSTS3_b[2];
6773     };
6774     __IM uint32_t RESERVED25[6];
6775 
6776     union
6777     {
6778         __IOM uint32_t CFDTXQPCTR3[2]; /*!< (@ 0x00001160) TX Queue Pointer Control Registers 3                       */
6779 
6780         struct
6781         {
6782             __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
6783             uint32_t            : 24;
6784         } CFDTXQPCTR3_b[2];
6785     };
6786     __IM uint32_t RESERVED26[6];
6787 
6788     union
6789     {
6790         __IM uint32_t CFDTXQESTS;      /*!< (@ 0x00001180) TX Queue Empty Status Register                             */
6791 
6792         struct
6793         {
6794             __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ empty Status                                                   */
6795             uint32_t              : 24;
6796         } CFDTXQESTS_b;
6797     };
6798 
6799     union
6800     {
6801         __IOM uint32_t CFDTXQFISTS;     /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register                    */
6802 
6803         struct
6804         {
6805             __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status for channel 0                            */
6806             uint32_t               : 1;
6807             __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status for channel 1                            */
6808             uint32_t               : 25;
6809         } CFDTXQFISTS_b;
6810     };
6811 
6812     union
6813     {
6814         __IOM uint32_t CFDTXQMSTS;     /*!< (@ 0x00001188) TX Queue Message Lost Status Register                      */
6815 
6816         struct
6817         {
6818             __IM uint32_t TXQ0ML : 3;  /*!< [2..0] TXQ message lost Status for channel 0                              */
6819             uint32_t             : 1;
6820             __IM uint32_t TXQ1ML : 3;  /*!< [6..4] TXQ message lost Status for channel 1                              */
6821             uint32_t             : 25;
6822         } CFDTXQMSTS_b;
6823     };
6824     __IM uint32_t RESERVED27;
6825 
6826     union
6827     {
6828         __IOM uint32_t CFDTXQISTS;     /*!< (@ 0x00001190) TX Queue Interrupt Status Register                         */
6829 
6830         struct
6831         {
6832             __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for channel 0                            */
6833             __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for channel 1                            */
6834             uint32_t              : 24;
6835         } CFDTXQISTS_b;
6836     };
6837 
6838     union
6839     {
6840         __IOM uint32_t CFDTXQOFTISTS;     /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register            */
6841 
6842         struct
6843         {
6844             __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for channel 0               */
6845             __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for channel 1               */
6846             uint32_t                 : 24;
6847         } CFDTXQOFTISTS_b;
6848     };
6849 
6850     union
6851     {
6852         __IOM uint32_t CFDTXQOFRISTS;     /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register            */
6853 
6854         struct
6855         {
6856             __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag                             */
6857             uint32_t                 : 1;
6858             __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag                             */
6859             uint32_t                 : 25;
6860         } CFDTXQOFRISTS_b;
6861     };
6862 
6863     union
6864     {
6865         __IM uint32_t CFDTXQFSTS;      /*!< (@ 0x0000119C) TX Queue Full Status Register                              */
6866 
6867         struct
6868         {
6869             __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for channel 0                                 */
6870             __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for channel 1                                 */
6871             uint32_t              : 24;
6872         } CFDTXQFSTS_b;
6873     };
6874     __IM uint32_t RESERVED28[24];
6875 
6876     union
6877     {
6878         __IOM uint32_t CFDTHLCC[2];    /*!< (@ 0x00001200) TX History List Configuration / Control Register           */
6879 
6880         struct
6881         {
6882             __IOM uint32_t THLE   : 1; /*!< [0..0] TX History List Enable                                             */
6883             uint32_t              : 7;
6884             __IOM uint32_t THLIE  : 1; /*!< [8..8] TX History List Interrupt Enable                                   */
6885             __IOM uint32_t THLIM  : 1; /*!< [9..9] TX History List Interrupt Mode                                     */
6886             __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable                              */
6887             __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated GW Enable                              */
6888             uint32_t              : 20;
6889         } CFDTHLCC_b[2];
6890     };
6891     __IM uint32_t RESERVED29[6];
6892 
6893     union
6894     {
6895         __IOM uint32_t CFDTHLSTS[2];   /*!< (@ 0x00001220) TX History List Status Register                            */
6896 
6897         struct
6898         {
6899             __IM uint32_t  THLEMP : 1; /*!< [0..0] TX History List Empty                                              */
6900             __IM uint32_t  THLFLL : 1; /*!< [1..1] TX History List Full                                               */
6901             __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost                                         */
6902             __IOM uint32_t THLIF  : 1; /*!< [3..3] TX History List Interrupt Flag                                     */
6903             uint32_t              : 4;
6904             __IM uint32_t THLMC   : 6; /*!< [13..8] TX History List Message Count                                     */
6905             uint32_t              : 18;
6906         } CFDTHLSTS_b[2];
6907     };
6908     __IM uint32_t RESERVED30[6];
6909 
6910     union
6911     {
6912         __IOM uint32_t CFDTHLPCTR[2];  /*!< (@ 0x00001240) TX History List Pointer Control Registers                  */
6913 
6914         struct
6915         {
6916             __OM uint32_t THLPC : 8;   /*!< [7..0] TX History List Pointer Control                                    */
6917             uint32_t            : 24;
6918         } CFDTHLPCTR_b[2];
6919     };
6920     __IM uint32_t RESERVED31[46];
6921 
6922     union
6923     {
6924         __IOM uint32_t CFDGTINTSTS0;   /*!< (@ 0x00001300) Global TX Interrupt Status Register 0                      */
6925 
6926         struct
6927         {
6928             __IM uint32_t TSIF0   : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0                             */
6929             __IM uint32_t TAIF0   : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0                                  */
6930             __IM uint32_t TQIF0   : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0                                  */
6931             __IM uint32_t CFTIF0  : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0                       */
6932             __IM uint32_t THIF0   : 1; /*!< [4..4] TX History List Interrupt Channel 0                                */
6933             __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel
6934                                         *   0                                                                         */
6935             __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel
6936                                         *   0                                                                         */
6937             uint32_t              : 1;
6938             __IM uint32_t TSIF1   : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1                             */
6939             __IM uint32_t TAIF1   : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1                                  */
6940             __IM uint32_t TQIF1   : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1                                */
6941             __IM uint32_t CFTIF1  : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1                     */
6942             __IM uint32_t THIF1   : 1; /*!< [12..12] TX History List Interrupt Channel 1                              */
6943             __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel
6944                                         *   1                                                                         */
6945             __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel
6946                                         *   1                                                                         */
6947             uint32_t : 17;
6948         } CFDGTINTSTS0_b;
6949     };
6950     __IM uint32_t RESERVED32;
6951 
6952     union
6953     {
6954         __IOM uint32_t CFDGTSTCFG;     /*!< (@ 0x00001308) Global Test Configuration Register                         */
6955 
6956         struct
6957         {
6958             __IOM uint32_t ICBCE : 2;  /*!< [1..0] Channel n Internal CAN Bus Communication Test Mode Enable          */
6959             uint32_t             : 14;
6960             __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select                                        */
6961             uint32_t             : 6;
6962         } CFDGTSTCFG_b;
6963     };
6964 
6965     union
6966     {
6967         __IOM uint32_t CFDGTSTCTR;      /*!< (@ 0x0000130C) Global Test Control Register                               */
6968 
6969         struct
6970         {
6971             __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable                    */
6972             uint32_t               : 1;
6973             __IOM uint32_t RTME    : 1; /*!< [2..2] RAM Test Mode Enable                                               */
6974             uint32_t               : 29;
6975         } CFDGTSTCTR_b;
6976     };
6977     __IM uint32_t RESERVED33;
6978 
6979     union
6980     {
6981         __IOM uint32_t CFDGFDCFG;      /*!< (@ 0x00001314) Global FD Configuration register                           */
6982 
6983         struct
6984         {
6985             __IOM uint32_t RPED   : 1; /*!< [0..0] RES bit Protocol exception disable                                 */
6986             uint32_t              : 7;
6987             __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration                                    */
6988             uint32_t              : 22;
6989         } CFDGFDCFG_b;
6990     };
6991 
6992     union
6993     {
6994         __IOM uint32_t CFDGCRCCFG;     /*!< (@ 0x00001318) Global FD CRC Configuration register                       */
6995 
6996         struct
6997         {
6998             __IOM uint32_t NIE : 1;    /*!< [0..0] Non ISO enable                                                     */
6999             uint32_t           : 31;
7000         } CFDGCRCCFG_b;
7001     };
7002 
7003     union
7004     {
7005         __IOM uint32_t CFDGLOCKK;      /*!< (@ 0x0000131C) Global Lock Key Register                                   */
7006 
7007         struct
7008         {
7009             __OM uint32_t LOCK : 16;   /*!< [15..0] Lock Key                                                          */
7010             uint32_t           : 16;
7011         } CFDGLOCKK_b;
7012     };
7013 
7014     union
7015     {
7016         __IOM uint32_t CFDGLOTB;       /*!< (@ 0x00001320) Global OTB FIFO Configuration / Status Register            */
7017 
7018         struct
7019         {
7020             __IOM uint32_t OTBFE  : 1; /*!< [0..0] OTB FIFO Enable                                                    */
7021             uint32_t              : 7;
7022             __IM uint32_t  OTBEMP : 1; /*!< [8..8] OTB FIFO Empty                                                     */
7023             __IM uint32_t  OTBFLL : 1; /*!< [9..9] OTB FIFO Full                                                      */
7024             __IOM uint32_t OTBMLT : 1; /*!< [10..10] OTB FIFO Message Lost                                            */
7025             __IM uint32_t  OTBMC  : 5; /*!< [15..11] OTB FIFO Message Count                                           */
7026             uint32_t              : 16;
7027         } CFDGLOTB_b;
7028     };
7029 
7030     union
7031     {
7032         __IOM uint32_t CFDGAFLIGNENT;  /*!< (@ 0x00001324) Global AFL Ignore Entry Register                           */
7033 
7034         struct
7035         {
7036             __IOM uint32_t IRN : 9;    /*!< [8..0] Ignore Rule Number                                                 */
7037             uint32_t           : 7;
7038             __IOM uint32_t ICN : 3;    /*!< [18..16] Ignore Channel Number                                            */
7039             uint32_t           : 13;
7040         } CFDGAFLIGNENT_b;
7041     };
7042 
7043     union
7044     {
7045         __IOM uint32_t CFDGAFLIGNCTR;  /*!< (@ 0x00001328) Global AFL Ignore Control Register                         */
7046 
7047         struct
7048         {
7049             __IOM uint32_t IREN : 1;   /*!< [0..0] Ignore Rule Enable                                                 */
7050             uint32_t            : 7;
7051             __OM uint32_t KEY   : 8;   /*!< [15..8] Key code                                                          */
7052             uint32_t            : 16;
7053         } CFDGAFLIGNCTR_b;
7054     };
7055     __IM uint32_t RESERVED34;
7056 
7057     union
7058     {
7059         __IOM uint32_t CFDCDTCT;        /*!< (@ 0x00001330) DMA Transfer Control Register                              */
7060 
7061         struct
7062         {
7063             __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0                                   */
7064             __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1                                   */
7065             __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RXFIFO 2                                   */
7066             __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RXFIFO 3                                   */
7067             __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RXFIFO 4                                   */
7068             __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RXFIFO 5                                   */
7069             __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RXFIFO 6                                   */
7070             __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RXFIFO 7                                   */
7071             __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0                 */
7072             __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of channel 1                 */
7073             uint32_t               : 22;
7074         } CFDCDTCT_b;
7075     };
7076 
7077     union
7078     {
7079         __IM uint32_t CFDCDTSTS;         /*!< (@ 0x00001334) DMA Transfer Status Register                               */
7080 
7081         struct
7082         {
7083             __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0                                  */
7084             __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1                                  */
7085             __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2                                  */
7086             __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3                                  */
7087             __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4                                  */
7088             __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5                                  */
7089             __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6                                  */
7090             __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7                                  */
7091             __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel
7092                                           *   0                                                                         */
7093             __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of channel
7094                                           *   1                                                                         */
7095             uint32_t : 22;
7096         } CFDCDTSTS_b;
7097     };
7098     __IM uint32_t RESERVED35[2];
7099 
7100     union
7101     {
7102         __IOM uint32_t CFDCDTTCT;        /*!< (@ 0x00001340) DMA TX Transfer Control Register                           */
7103 
7104         struct
7105         {
7106             __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of channel 0                      */
7107             __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of channel 1                      */
7108             uint32_t                : 6;
7109             __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of channel 0                      */
7110             __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of channel 1                      */
7111             uint32_t                : 6;
7112             __IOM uint32_t CFDMAE0  : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of channel
7113                                           *   0                                                                         */
7114             __IOM uint32_t CFDMAE1 : 1;  /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of channel
7115                                           *   1                                                                         */
7116             uint32_t : 14;
7117         } CFDCDTTCT_b;
7118     };
7119 
7120     union
7121     {
7122         __IOM uint32_t CFDCDTTSTS;        /*!< (@ 0x00001344) DMA TX Transfer Status Register                            */
7123 
7124         struct
7125         {
7126             __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of channel 0                       */
7127             __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of channel 1                       */
7128             uint32_t                 : 6;
7129             __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of channel 0                       */
7130             __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of channel 1                       */
7131             uint32_t                 : 6;
7132             __IM uint32_t CFDMASTS0  : 1; /*!< [16..16] DMA TX Transfer Status only for Common FIFO 2 of channel
7133                                            *   0                                                                         */
7134             __IM uint32_t CFDMASTS1 : 1;  /*!< [17..17] DMA TX Transfer Status only for Common FIFO 2 of channel
7135                                            *   1                                                                         */
7136             uint32_t : 14;
7137         } CFDCDTTSTS_b;
7138     };
7139     __IM uint32_t RESERVED36[2];
7140 
7141     union
7142     {
7143         __IOM uint32_t CFDGRINTSTS[2]; /*!< (@ 0x00001350) Global RX Interrupt Status Register                        */
7144 
7145         struct
7146         {
7147             __IM uint32_t QFIF    : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n                                  */
7148             uint32_t              : 5;
7149             __IM uint32_t QOFRIF  : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n                         */
7150             uint32_t              : 5;
7151             __IM uint32_t CFRIF   : 3; /*!< [18..16] Common FIFO RX Interrupt Flag Channel n                          */
7152             uint32_t              : 5;
7153             __IM uint32_t CFRFIF  : 3; /*!< [26..24] Common FIFO FDC level Full Interrupt Flag Channel n              */
7154             uint32_t              : 1;
7155             __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n                */
7156             uint32_t              : 1;
7157         } CFDGRINTSTS_b[2];
7158     };
7159     __IM uint32_t RESERVED37[10];
7160 
7161     union
7162     {
7163         __IOM uint32_t CFDGRSTC;       /*!< (@ 0x00001380) Global SW reset Register                                   */
7164 
7165         struct
7166         {
7167             __IOM uint32_t SRST : 1;   /*!< [0..0] SW reset                                                           */
7168             uint32_t            : 7;
7169             __OM uint32_t KEY   : 8;   /*!< [15..8] Key code                                                          */
7170             uint32_t            : 16;
7171         } CFDGRSTC_b;
7172     };
7173     __IM uint32_t              RESERVED38[31];
7174     __IOM R_CANFD_CFDC2_Type   CFDC2[2];    /*!< (@ 0x00001400) Channel Configuration Registers                            */
7175     __IM uint32_t              RESERVED39[240];
7176     __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers                    */
7177     __IM uint32_t              RESERVED40[448];
7178     __IOM R_CANFD_CFDRM_Type   CFDRM[32];   /*!< (@ 0x00002000) RX Message Buffer Access Registers                         */
7179     __IM uint32_t              RESERVED41[3072];
7180     __IOM R_CANFD_CFDRF_Type   CFDRF[8];    /*!< (@ 0x00006000) RX FIFO Access Registers                                   */
7181     __IOM R_CANFD_CFDCF_Type   CFDCF[6];    /*!< (@ 0x00006400) Common FIFO Access Registers                               */
7182     __IM uint32_t              RESERVED42[1600];
7183     __IOM R_CANFD_CFDTHL_Type  CFDTHL[2];   /*!< (@ 0x00008000) Channel TX History List                                    */
7184     __IM uint32_t              RESERVED43[252];
7185 
7186     union
7187     {
7188         __IOM uint32_t CFDRPGACC[64];    /*!< (@ 0x00008400) RAM Test Page Access Registers                             */
7189 
7190         struct
7191         {
7192             __IOM uint32_t RDTA : 32;    /*!< [31..0] RAM Data Test Access                                              */
7193         } CFDRPGACC_b[64];
7194     };
7195     __IM uint32_t            RESERVED44[7872];
7196     __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Access Registers                         */
7197 } R_CANFD_Type;                          /*!< Size = 81920 (0x14000)                                                    */
7198 
7199 /* =========================================================================================================================== */
7200 /* ================                                         R_CANFDL                                          ================ */
7201 /* =========================================================================================================================== */
7202 
7203 /**
7204  * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFDL)
7205  */
7206 
7207 typedef struct                         /*!< (@ 0x400B0000) R_CANFDL Structure                                         */
7208 {
7209     __IOM R_CANFDL_CFDC_Type CFDC[1];  /*!< (@ 0x00000000) Channel Control/Status                                     */
7210     __IM uint32_t            RESERVED;
7211 
7212     union
7213     {
7214         __IOM uint32_t CFDGCFG;        /*!< (@ 0x00000014) Global Configuration Register                              */
7215 
7216         struct
7217         {
7218             __IOM uint32_t TPRI  : 1;  /*!< [0..0] Transmission Priority                                              */
7219             __IOM uint32_t DCE   : 1;  /*!< [1..1] DLC Check Enable                                                   */
7220             __IOM uint32_t DRE   : 1;  /*!< [2..2] DLC Replacement Enable                                             */
7221             __IOM uint32_t MME   : 1;  /*!< [3..3] Mirror Mode Enable                                                 */
7222             __IOM uint32_t DCS   : 1;  /*!< [4..4] Data Link Controller Clock Select                                  */
7223             __IOM uint32_t CMPOC : 1;  /*!< [5..5] CAN-FD message Payload overflow configuration                      */
7224             uint32_t             : 2;
7225             __IOM uint32_t TSP   : 4;  /*!< [11..8] Timestamp Prescaler                                               */
7226             __IOM uint32_t TSSS  : 1;  /*!< [12..12] Timestamp Source Select                                          */
7227             uint32_t             : 3;
7228             __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler                         */
7229         } CFDGCFG_b;
7230     };
7231 
7232     union
7233     {
7234         __IOM uint32_t CFDGCTR;         /*!< (@ 0x00000018) Global Control Register                                    */
7235 
7236         struct
7237         {
7238             __IOM uint32_t GMDC    : 2; /*!< [1..0] Global Mode Control                                                */
7239             __IOM uint32_t GSLPR   : 1; /*!< [2..2] Global Sleep Request                                               */
7240             uint32_t               : 5;
7241             __IOM uint32_t DEIE    : 1; /*!< [8..8] DLC check Interrupt Enable                                         */
7242             __IOM uint32_t MEIE    : 1; /*!< [9..9] Message lost Error Interrupt Enable                                */
7243             __IOM uint32_t THLEIE  : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable                      */
7244             __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable            */
7245             uint32_t               : 4;
7246             __IOM uint32_t TSRST   : 1; /*!< [16..16] Timestamp Reset                                                  */
7247             uint32_t               : 15;
7248         } CFDGCTR_b;
7249     };
7250 
7251     union
7252     {
7253         __IOM uint32_t CFDGSTS;         /*!< (@ 0x0000001C) Global Status Register                                     */
7254 
7255         struct
7256         {
7257             __IM uint32_t GRSTSTS  : 1; /*!< [0..0] Global Reset Status                                                */
7258             __IM uint32_t GHLTSTS  : 1; /*!< [1..1] Global Halt Status                                                 */
7259             __IM uint32_t GSLPSTS  : 1; /*!< [2..2] Global Sleep Status                                                */
7260             __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation                                          */
7261             uint32_t               : 28;
7262         } CFDGSTS_b;
7263     };
7264 
7265     union
7266     {
7267         __IOM uint32_t CFDGERFL;       /*!< (@ 0x00000020) Global Error Flag Register                                 */
7268 
7269         struct
7270         {
7271             __IOM uint32_t DEF   : 1;  /*!< [0..0] DLC Error Flag                                                     */
7272             __IM uint32_t  MES   : 1;  /*!< [1..1] Message Lost Error Status                                          */
7273             __IM uint32_t  THLES : 1;  /*!< [2..2] TX History List Entry Lost Error Status                            */
7274             __IOM uint32_t CMPOF : 1;  /*!< [3..3] CAN-FD message payload overflow Flag                               */
7275             uint32_t             : 12;
7276             __IOM uint32_t EEF0  : 1;  /*!< [16..16] ECC Error Flag for Channel 0                                     */
7277             uint32_t             : 15;
7278         } CFDGERFL_b;
7279     };
7280 
7281     union
7282     {
7283         __IOM uint32_t CFDGTSC;        /*!< (@ 0x00000024) Global Timestamp Counter Register                          */
7284 
7285         struct
7286         {
7287             __IM uint32_t TS : 16;     /*!< [15..0] Timestamp Value                                                   */
7288             uint32_t         : 16;
7289         } CFDGTSC_b;
7290     };
7291 
7292     union
7293     {
7294         __IOM uint32_t CFDGAFLECTR;    /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register       */
7295 
7296         struct
7297         {
7298             __IOM uint32_t AFLPN  : 4; /*!< [3..0] Acceptance Filter List Page Number                                 */
7299             uint32_t              : 4;
7300             __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable                          */
7301             uint32_t              : 23;
7302         } CFDGAFLECTR_b;
7303     };
7304 
7305     union
7306     {
7307         __IOM uint32_t CFDGAFLCFG0;    /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register
7308                                         *                  0                                                          */
7309 
7310         struct
7311         {
7312             __IOM uint32_t RNC1 : 9;   /*!< [8..0] Rule Number for Channel 1                                          */
7313             uint32_t            : 7;
7314             __IOM uint32_t RNC0 : 9;   /*!< [24..16] Rule Number for Channel 0                                        */
7315             uint32_t            : 7;
7316         } CFDGAFLCFG0_b;
7317     };
7318 
7319     union
7320     {
7321         __IOM uint32_t CFDRMNB;        /*!< (@ 0x00000030) RX Message Buffer Number Register                          */
7322 
7323         struct
7324         {
7325             __IOM uint32_t NRXMB : 8;  /*!< [7..0] Number of RX Message Buffers                                       */
7326             __IOM uint32_t RMPLS : 3;  /*!< [10..8] Reception Message Buffer Payload Data Size                        */
7327             uint32_t             : 21;
7328         } CFDRMNB_b;
7329     };
7330 
7331     union
7332     {
7333         __IOM uint32_t CFDRMND0;       /*!< (@ 0x00000034) RX Message Buffer New Data Register 0                      */
7334 
7335         struct
7336         {
7337             __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status                                 */
7338         } CFDRMND0_b;
7339     };
7340 
7341     union
7342     {
7343         __IOM uint32_t CFDRMIEC;       /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration
7344                                         *                  Register                                                   */
7345 
7346         struct
7347         {
7348             __IOM uint32_t RMIE : 32;  /*!< [31..0] RX Message Buffer Interrupt Enable                                */
7349         } CFDRMIEC_b;
7350     };
7351 
7352     union
7353     {
7354         __IOM uint32_t CFDRFCC[2];     /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers                  */
7355 
7356         struct
7357         {
7358             __IOM uint32_t RFE    : 1; /*!< [0..0] RX FIFO Enable                                                     */
7359             __IOM uint32_t RFIE   : 1; /*!< [1..1] RX FIFO Interrupt Enable                                           */
7360             uint32_t              : 2;
7361             __IOM uint32_t RFPLS  : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration                            */
7362             uint32_t              : 1;
7363             __IOM uint32_t RFDC   : 3; /*!< [10..8] RX FIFO Depth Configuration                                       */
7364             uint32_t              : 1;
7365             __IOM uint32_t RFIM   : 1; /*!< [12..12] RX FIFO Interrupt Mode                                           */
7366             __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value                       */
7367             uint32_t              : 16;
7368         } CFDRFCC_b[2];
7369     };
7370 
7371     union
7372     {
7373         __IOM uint32_t CFDRFSTS[2];    /*!< (@ 0x00000044) RX FIFO Status Registers                                   */
7374 
7375         struct
7376         {
7377             __IM uint32_t  RFEMP : 1;  /*!< [0..0] RX FIFO Empty                                                      */
7378             __IM uint32_t  RFFLL : 1;  /*!< [1..1] RX FIFO Full                                                       */
7379             __IOM uint32_t RFMLT : 1;  /*!< [2..2] RX FIFO Message Lost                                               */
7380             __IOM uint32_t RFIF  : 1;  /*!< [3..3] RX FIFO Interrupt Flag                                             */
7381             uint32_t             : 4;
7382             __IM uint32_t RFMC   : 8;  /*!< [15..8] RX FIFO Message Count                                             */
7383             uint32_t             : 16;
7384         } CFDRFSTS_b[2];
7385     };
7386 
7387     union
7388     {
7389         __IOM uint32_t CFDRFPCTR[2];   /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers                          */
7390 
7391         struct
7392         {
7393             __OM uint32_t RFPC : 8;    /*!< [7..0] RX FIFO Pointer Control                                            */
7394             uint32_t           : 24;
7395         } CFDRFPCTR_b[2];
7396     };
7397 
7398     union
7399     {
7400         __IOM uint32_t CFDCFCC[1];     /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers              */
7401 
7402         struct
7403         {
7404             __IOM uint32_t CFE    : 1; /*!< [0..0] Common FIFO Enable                                                 */
7405             __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable                                    */
7406             __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable                                    */
7407             uint32_t              : 1;
7408             __IOM uint32_t CFPLS  : 3; /*!< [6..4] Common FIFO Payload Data size configuration                        */
7409             uint32_t              : 1;
7410             __IOM uint32_t CFM    : 2; /*!< [9..8] Common FIFO Mode                                                   */
7411             __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select                         */
7412             __IOM uint32_t CFITR  : 1; /*!< [11..11] Common FIFO Interval Timer Resolution                            */
7413             __IOM uint32_t CFIM   : 1; /*!< [12..12] Common FIFO Interrupt Mode                                       */
7414             __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value                   */
7415             __IOM uint32_t CFTML  : 5; /*!< [20..16] Common FIFO TX Message Buffer Link                               */
7416             __IOM uint32_t CFDC   : 3; /*!< [23..21] Common FIFO Depth Configuration                                  */
7417             __IOM uint32_t CFITT  : 8; /*!< [31..24] Common FIFO Interval Transmission Time                           */
7418         } CFDCFCC_b[1];
7419     };
7420 
7421     union
7422     {
7423         __IOM uint32_t CFDCFSTS[1];    /*!< (@ 0x00000058) Common FIFO Status Registers                               */
7424 
7425         struct
7426         {
7427             __IM uint32_t  CFEMP  : 1; /*!< [0..0] Common FIFO Empty                                                  */
7428             __IM uint32_t  CFFLL  : 1; /*!< [1..1] Common FIFO Full                                                   */
7429             __IOM uint32_t CFMLT  : 1; /*!< [2..2] Common FIFO Message Lost                                           */
7430             __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag                                      */
7431             __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag                                      */
7432             uint32_t              : 3;
7433             __IM uint32_t CFMC    : 8; /*!< [15..8] Common FIFO Message Count                                         */
7434             uint32_t              : 16;
7435         } CFDCFSTS_b[1];
7436     };
7437 
7438     union
7439     {
7440         __IOM uint32_t CFDCFPCTR[1];   /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers                      */
7441 
7442         struct
7443         {
7444             __OM uint32_t CFPC : 8;    /*!< [7..0] Common FIFO Pointer Control                                        */
7445             uint32_t           : 24;
7446         } CFDCFPCTR_b[1];
7447     };
7448 
7449     union
7450     {
7451         __IM uint32_t CFDFESTS;        /*!< (@ 0x00000060) FIFO Empty Status Register                                 */
7452 
7453         struct
7454         {
7455             __IM uint32_t RFXEMP : 2;  /*!< [1..0] RX FIF0 Empty Status                                               */
7456             uint32_t             : 6;
7457             __IM uint32_t CFXEMP : 1;  /*!< [8..8] Common FIF0 Empty Status                                           */
7458             uint32_t             : 23;
7459         } CFDFESTS_b;
7460     };
7461 
7462     union
7463     {
7464         __IM uint32_t CFDFFSTS;        /*!< (@ 0x00000064) FIFO Full Status Register                                  */
7465 
7466         struct
7467         {
7468             __IM uint32_t RFXFLL : 2;  /*!< [1..0] RX FIF0 Full Status                                                */
7469             uint32_t             : 6;
7470             __IM uint32_t CFXFLL : 1;  /*!< [8..8] Common FIF0 Full Status                                            */
7471             uint32_t             : 23;
7472         } CFDFFSTS_b;
7473     };
7474 
7475     union
7476     {
7477         __IM uint32_t CFDFMSTS;        /*!< (@ 0x00000068) FIFO Message Lost Status Register                          */
7478 
7479         struct
7480         {
7481             __IM uint32_t RFXMLT : 2;  /*!< [1..0] RX FIFO Msg Lost Status                                            */
7482             uint32_t             : 6;
7483             __IM uint32_t CFXMLT : 1;  /*!< [8..8] Common FIFO Msg Lost Status                                        */
7484             uint32_t             : 23;
7485         } CFDFMSTS_b;
7486     };
7487 
7488     union
7489     {
7490         __IOM uint32_t CFDRFISTS;      /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register                     */
7491 
7492         struct
7493         {
7494             __IM uint32_t RFXIF : 1;   /*!< [0..0] RX FIFO[x] Interrupt Flag Status                                   */
7495             uint32_t            : 31;
7496         } CFDRFISTS_b;
7497     };
7498 
7499     union
7500     {
7501         __IOM uint8_t CFDTMC[4];       /*!< (@ 0x00000070) TX Message Buffer Control Registers                        */
7502 
7503         struct
7504         {
7505             __IOM uint8_t TMTR  : 1;   /*!< [0..0] TX Message Buffer Transmission Request                             */
7506             __IOM uint8_t TMTAR : 1;   /*!< [1..1] TX Message Buffer Transmission abort Request                       */
7507             __IOM uint8_t TMOM  : 1;   /*!< [2..2] TX Message Buffer One-shot Mode                                    */
7508             uint8_t             : 5;
7509         } CFDTMC_b[4];
7510     };
7511 
7512     union
7513     {
7514         __IOM uint8_t CFDTMSTS[4];     /*!< (@ 0x00000074) TX Message Buffer Status Registers                         */
7515 
7516         struct
7517         {
7518             __IM uint8_t  TMTSTS : 1;  /*!< [0..0] TX Message Buffer Transmission Status                              */
7519             __IOM uint8_t TMTRF  : 2;  /*!< [2..1] TX Message Buffer Transmission Result Flag                         */
7520             __IM uint8_t  TMTRM  : 1;  /*!< [3..3] TX Message Buffer Transmission Request Mirrored                    */
7521             __IM uint8_t  TMTARM : 1;  /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored              */
7522             uint8_t              : 3;
7523         } CFDTMSTS_b[4];
7524     };
7525 
7526     union
7527     {
7528         __IM uint32_t CFDTMTRSTS[1];       /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status
7529                                             *                  Register                                                   */
7530 
7531         struct
7532         {
7533             __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status                      */
7534             uint32_t                  : 28;
7535         } CFDTMTRSTS_b[1];
7536     };
7537 
7538     union
7539     {
7540         __IM uint32_t CFDTMTARSTS[1];       /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request
7541                                              *                  Status Register                                            */
7542 
7543         struct
7544         {
7545             __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status                */
7546             uint32_t                   : 28;
7547         } CFDTMTARSTS_b[1];
7548     };
7549 
7550     union
7551     {
7552         __IM uint32_t CFDTMTCSTS[1];       /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status
7553                                             *                  Register                                                   */
7554 
7555         struct
7556         {
7557             __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status                   */
7558             uint32_t                  : 28;
7559         } CFDTMTCSTS_b[1];
7560     };
7561 
7562     union
7563     {
7564         __IM uint32_t CFDTMTASTS[1];       /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register       */
7565 
7566         struct
7567         {
7568             __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status                        */
7569             uint32_t                  : 28;
7570         } CFDTMTASTS_b[1];
7571     };
7572 
7573     union
7574     {
7575         __IOM uint32_t CFDTMIEC[1];    /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration
7576                                         *                  Register                                                   */
7577 
7578         struct
7579         {
7580             __IOM uint32_t TMIEg : 4;  /*!< [3..0] TX Message Buffer Interrupt Enable                                 */
7581             uint32_t             : 28;
7582         } CFDTMIEC_b[1];
7583     };
7584 
7585     union
7586     {
7587         __IOM uint32_t CFDTXQCC0[1];    /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0               */
7588 
7589         struct
7590         {
7591             __IOM uint32_t TXQE    : 1; /*!< [0..0] TX Queue Enable                                                    */
7592             uint32_t               : 4;
7593             __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
7594             uint32_t               : 1;
7595             __IOM uint32_t TXQIM   : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
7596             __IOM uint32_t TXQDC   : 2; /*!< [9..8] TX Queue Depth Configuration                                       */
7597             uint32_t               : 22;
7598         } CFDTXQCC0_b[1];
7599     };
7600 
7601     union
7602     {
7603         __IOM uint32_t CFDTXQSTS0[1];   /*!< (@ 0x00000090) TX Queue Status Registers 0                                */
7604 
7605         struct
7606         {
7607             __IM uint32_t  TXQEMP  : 1; /*!< [0..0] TX Queue Empty                                                     */
7608             __IM uint32_t  TXQFLL  : 1; /*!< [1..1] TX Queue Full                                                      */
7609             __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
7610             uint32_t               : 5;
7611             __IM uint32_t TXQMC    : 6; /*!< [13..8] TX Queue Message Count                                            */
7612             uint32_t               : 18;
7613         } CFDTXQSTS0_b[1];
7614     };
7615 
7616     union
7617     {
7618         __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0                       */
7619 
7620         struct
7621         {
7622             __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
7623             uint32_t            : 24;
7624         } CFDTXQPCTR0_b[1];
7625     };
7626 
7627     union
7628     {
7629         __IOM uint32_t CFDTHLCC[1];    /*!< (@ 0x00000098) TX History List Configuration / Control Register           */
7630 
7631         struct
7632         {
7633             __IOM uint32_t THLE   : 1; /*!< [0..0] TX History List Enable                                             */
7634             uint32_t              : 7;
7635             __IOM uint32_t THLIE  : 1; /*!< [8..8] TX History List Interrupt Enable                                   */
7636             __IOM uint32_t THLIM  : 1; /*!< [9..9] TX History List Interrupt Mode                                     */
7637             __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable                              */
7638             uint32_t              : 21;
7639         } CFDTHLCC_b[1];
7640     };
7641 
7642     union
7643     {
7644         __IOM uint32_t CFDTHLSTS[1];   /*!< (@ 0x0000009C) TX History List Status Register                            */
7645 
7646         struct
7647         {
7648             __IM uint32_t  THLEMP : 1; /*!< [0..0] TX History List Empty                                              */
7649             __IM uint32_t  THLFLL : 1; /*!< [1..1] TX History List Full                                               */
7650             __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost                                         */
7651             __IOM uint32_t THLIF  : 1; /*!< [3..3] TX History List Interrupt Flag                                     */
7652             uint32_t              : 4;
7653             __IM uint32_t THLMC   : 6; /*!< [13..8] TX History List Message Count                                     */
7654             uint32_t              : 18;
7655         } CFDTHLSTS_b[1];
7656     };
7657 
7658     union
7659     {
7660         __IOM uint32_t CFDTHLPCTR[1];  /*!< (@ 0x000000A0) TX History List Pointer Control Registers                  */
7661 
7662         struct
7663         {
7664             __OM uint32_t THLPC : 8;   /*!< [7..0] TX History List Pointer Control                                    */
7665             uint32_t            : 24;
7666         } CFDTHLPCTR_b[1];
7667     };
7668 
7669     union
7670     {
7671         __IOM uint32_t CFDGTINTSTS0;   /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0                      */
7672 
7673         struct
7674         {
7675             __IM uint32_t TSIF0  : 1;  /*!< [0..0] TX Successful Interrupt Flag Channel 0                             */
7676             __IM uint32_t TAIF0  : 1;  /*!< [1..1] TX Abort Interrupt Flag Channel 0                                  */
7677             __IM uint32_t TQIF0  : 1;  /*!< [2..2] TX Queue Interrupt Flag Channel 0                                  */
7678             __IM uint32_t CFTIF0 : 1;  /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0                       */
7679             __IM uint32_t THIF0  : 1;  /*!< [4..4] TX History List Interrupt Channel 0                                */
7680             uint32_t             : 27;
7681         } CFDGTINTSTS0_b;
7682     };
7683 
7684     union
7685     {
7686         __IOM uint32_t CFDGTSTCFG;     /*!< (@ 0x000000A8) Global Test Configuration Register                         */
7687 
7688         struct
7689         {
7690             uint32_t             : 16;
7691             __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select                                        */
7692             uint32_t             : 6;
7693         } CFDGTSTCFG_b;
7694     };
7695 
7696     union
7697     {
7698         __IOM uint32_t CFDGTSTCTR;     /*!< (@ 0x000000AC) Global Test Control Register                               */
7699 
7700         struct
7701         {
7702             uint32_t            : 2;
7703             __IOM uint32_t RTME : 1;   /*!< [2..2] RAM Test Mode Enable                                               */
7704             uint32_t            : 29;
7705         } CFDGTSTCTR_b;
7706     };
7707 
7708     union
7709     {
7710         __IOM uint32_t CFDGFDCFG;      /*!< (@ 0x000000B0) Global FD Configuration register                           */
7711 
7712         struct
7713         {
7714             __IOM uint32_t RPED   : 1; /*!< [0..0] RES bit Protocol exception disable                                 */
7715             uint32_t              : 7;
7716             __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration                                    */
7717             uint32_t              : 22;
7718         } CFDGFDCFG_b;
7719     };
7720     __IM uint32_t RESERVED1;
7721 
7722     union
7723     {
7724         __IOM uint32_t CFDGLOCKK;      /*!< (@ 0x000000B8) Global Lock Key Register                                   */
7725 
7726         struct
7727         {
7728             __OM uint32_t LOCK : 16;   /*!< [15..0] Lock Key                                                          */
7729             uint32_t           : 16;
7730         } CFDGLOCKK_b;
7731     };
7732     __IM uint32_t RESERVED2;
7733 
7734     union
7735     {
7736         __IOM uint32_t CFDGAFLIGNENT;  /*!< (@ 0x000000C0) Global AFL Ignore Entry Register                           */
7737 
7738         struct
7739         {
7740             __IOM uint32_t IRN : 5;    /*!< [4..0] Ignore Rule Number                                                 */
7741             uint32_t           : 27;
7742         } CFDGAFLIGNENT_b;
7743     };
7744 
7745     union
7746     {
7747         __IOM uint32_t CFDGAFLIGNCTR;  /*!< (@ 0x000000C4) Global AFL Ignore Control Register                         */
7748 
7749         struct
7750         {
7751             __IOM uint32_t IREN : 1;   /*!< [0..0] Ignore Rule Enable                                                 */
7752             uint32_t            : 7;
7753             __OM uint32_t KEY   : 8;   /*!< [15..8] Key code                                                          */
7754             uint32_t            : 16;
7755         } CFDGAFLIGNCTR_b;
7756     };
7757 
7758     union
7759     {
7760         __IOM uint32_t CFDCDTCT;        /*!< (@ 0x000000C8) DMA Transfer Control Register                              */
7761 
7762         struct
7763         {
7764             __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0                                   */
7765             __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1                                   */
7766             uint32_t               : 6;
7767             __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0                 */
7768             uint32_t               : 23;
7769         } CFDCDTCT_b;
7770     };
7771 
7772     union
7773     {
7774         __IM uint32_t CFDCDTSTS;         /*!< (@ 0x000000CC) DMA Transfer Status Register                               */
7775 
7776         struct
7777         {
7778             __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0                                  */
7779             __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1                                  */
7780             uint32_t                : 6;
7781             __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel
7782                                           *   0                                                                         */
7783             uint32_t : 23;
7784         } CFDCDTSTS_b;
7785     };
7786     __IM uint32_t RESERVED3[2];
7787 
7788     union
7789     {
7790         __IOM uint32_t CFDGRSTC;       /*!< (@ 0x000000D8) Global SW reset Register                                   */
7791 
7792         struct
7793         {
7794             __IOM uint32_t SRST : 1;   /*!< [0..0] SW reset                                                           */
7795             uint32_t            : 7;
7796             __OM uint32_t KEY   : 8;   /*!< [15..8] Key code                                                          */
7797             uint32_t            : 16;
7798         } CFDGRSTC_b;
7799     };
7800     __IM uint32_t               RESERVED4[9];
7801     __IOM R_CANFDL_CFDC2_Type   CFDC2[1];    /*!< (@ 0x00000100) Channel Configuration Registers                            */
7802     __IOM R_CANFDL_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers                    */
7803     __IM uint32_t               RESERVED5[24];
7804 
7805     union
7806     {
7807         __IOM uint32_t CFDRPGACC[64];     /*!< (@ 0x00000280) RAM Test Page Access Registers                             */
7808 
7809         struct
7810         {
7811             __IOM uint32_t RDTA : 32;     /*!< [31..0] RAM Data Test Access                                              */
7812         } CFDRPGACC_b[64];
7813     };
7814     __IM uint32_t              RESERVED6[104];
7815     __IOM R_CANFDL_CFDRF_Type  CFDRF[2];  /*!< (@ 0x00000520) RX FIFO Access Registers                                   */
7816     __IOM R_CANFDL_CFDCF_Type  CFDCF[1];  /*!< (@ 0x000005B8) Common FIFO Access Registers                               */
7817     __IOM R_CANFDL_CFDTM_Type  CFDTM[4];  /*!< (@ 0x00000604) TX Message Buffer Access Registers                         */
7818     __IM uint32_t              RESERVED7[3];
7819     __IOM R_CANFDL_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List                                    */
7820     __IM uint32_t              RESERVED8[118];
7821     __IOM R_CANFDL_CFDRMC_Type CFDRMC[4]; /*!< (@ 0x00000920) RX Message Buffer Access Clusters                          */
7822 } R_CANFDL_Type;                          /*!< Size = 6432 (0x1920)                                                      */
7823 
7824 /* =========================================================================================================================== */
7825 /* ================                                           R_CRC                                           ================ */
7826 /* =========================================================================================================================== */
7827 
7828 /**
7829  * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC)
7830  */
7831 
7832 typedef struct                         /*!< (@ 0x40074000) R_CRC Structure                                            */
7833 {
7834     union
7835     {
7836         __IOM uint8_t CRCCR0;          /*!< (@ 0x00000000) CRC Control Register0                                      */
7837 
7838         struct
7839         {
7840             __IOM uint8_t GPS    : 3;  /*!< [2..0] CRC Generating Polynomial Switching                                */
7841             uint8_t              : 3;
7842             __IOM uint8_t LMS    : 1;  /*!< [6..6] CRC Calculation Switching                                          */
7843             __OM uint8_t  DORCLR : 1;  /*!< [7..7] CRCDOR Register Clear                                              */
7844         } CRCCR0_b;
7845     };
7846 
7847     union
7848     {
7849         __IOM uint8_t CRCCR1;          /*!< (@ 0x00000001) CRC Control Register1                                      */
7850 
7851         struct
7852         {
7853             uint8_t              : 6;
7854             __IOM uint8_t CRCSWR : 1;  /*!< [6..6] Snoop-on-write/read switch bit                                     */
7855             __IOM uint8_t CRCSEN : 1;  /*!< [7..7] Snoop enable bit                                                   */
7856         } CRCCR1_b;
7857     };
7858     __IM uint16_t RESERVED;
7859 
7860     union
7861     {
7862         union
7863         {
7864             __IOM uint32_t CRCDIR;          /*!< (@ 0x00000004) CRC Data Input Register                                    */
7865 
7866             struct
7867             {
7868                 __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C )                 */
7869             } CRCDIR_b;
7870         };
7871 
7872         union
7873         {
7874             __IOM uint8_t CRCDIR_BY;         /*!< (@ 0x00000004) CRC Data Input Register (byte access)                      */
7875 
7876             struct
7877             {
7878                 __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT
7879                                               *   )                                                                         */
7880             } CRCDIR_BY_b;
7881         };
7882     };
7883 
7884     union
7885     {
7886         union
7887         {
7888             __IOM uint32_t CRCDOR;          /*!< (@ 0x00000008) CRC Data Output Register                                   */
7889 
7890             struct
7891             {
7892                 __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C )                */
7893             } CRCDOR_b;
7894         };
7895 
7896         union
7897         {
7898             __IOM uint16_t CRCDOR_HA;          /*!< (@ 0x00000008) CRC Data Output Register (halfword access)                 */
7899 
7900             struct
7901             {
7902                 __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT
7903                                                 *   )                                                                         */
7904             } CRCDOR_HA_b;
7905         };
7906 
7907         union
7908         {
7909             __IOM uint8_t CRCDOR_BY;         /*!< (@ 0x00000008) CRC Data Output Register(byte access)                      */
7910 
7911             struct
7912             {
7913                 __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 )                           */
7914             } CRCDOR_BY_b;
7915         };
7916     };
7917 
7918     union
7919     {
7920         __IOM uint16_t CRCSAR;         /*!< (@ 0x0000000C) Snoop Address Register                                     */
7921 
7922         struct
7923         {
7924             __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop            */
7925             uint16_t             : 2;
7926         } CRCSAR_b;
7927     };
7928     __IM uint16_t RESERVED1;
7929 } R_CRC_Type;                          /*!< Size = 16 (0x10)                                                          */
7930 
7931 /* =========================================================================================================================== */
7932 /* ================                                          R_CTSU                                           ================ */
7933 /* =========================================================================================================================== */
7934 
7935 /**
7936  * @brief Capacitive Touch Sensing Unit (R_CTSU)
7937  */
7938 
7939 typedef struct                            /*!< (@ 0x40081000) R_CTSU Structure                                           */
7940 {
7941     union
7942     {
7943         __IOM uint8_t CTSUCR0;            /*!< (@ 0x00000000) CTSU Control Register 0                                    */
7944 
7945         struct
7946         {
7947             __IOM uint8_t CTSUSTRT   : 1; /*!< [0..0] CTSU Measurement Operation Start                                   */
7948             __IOM uint8_t CTSUCAP    : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select                    */
7949             __IOM uint8_t CTSUSNZ    : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable                                */
7950             __IOM uint8_t CTSUIOC    : 1; /*!< [3..3] CTSU Transmit Pin Control                                          */
7951             __IOM uint8_t CTSUINIT   : 1; /*!< [4..4] CTSU Control Block Initialization                                  */
7952             uint8_t                  : 2;
7953             __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection                           */
7954         } CTSUCR0_b;
7955     };
7956 
7957     union
7958     {
7959         __IOM uint8_t CTSUCR1;            /*!< (@ 0x00000001) CTSU Control Register 1                                    */
7960 
7961         struct
7962         {
7963             __IOM uint8_t CTSUPON    : 1; /*!< [0..0] CTSU Power Supply Enable                                           */
7964             __IOM uint8_t CTSUCSW    : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control                              */
7965             __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting                           */
7966             __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment                              */
7967             __IOM uint8_t CTSUCLK    : 2; /*!< [5..4] CTSU Operating Clock Select                                        */
7968             __IOM uint8_t CTSUMD     : 2; /*!< [7..6] CTSU Measurement Mode Select                                       */
7969         } CTSUCR1_b;
7970     };
7971 
7972     union
7973     {
7974         __IOM uint8_t CTSUSDPRS;           /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register          */
7975 
7976         struct
7977         {
7978             __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended
7979                                             *   setting: 3 (0011b)                                                        */
7980             __IOM uint8_t CTSUPRMODE : 2;  /*!< [5..4] CTSU Base Period and Pulse Count Setting                           */
7981             __IOM uint8_t CTSUSOFF   : 1;  /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting                */
7982             uint8_t                  : 1;
7983         } CTSUSDPRS_b;
7984     };
7985 
7986     union
7987     {
7988         __IOM uint8_t CTSUSST;         /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register            */
7989 
7990         struct
7991         {
7992             __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value
7993                                         *   of these bits should be fixed to 00010000b.                               */
7994         } CTSUSST_b;
7995     };
7996 
7997     union
7998     {
7999         __IOM uint8_t CTSUMCH0;         /*!< (@ 0x00000004) CTSU Measurement Channel Register 0                        */
8000 
8001         struct
8002         {
8003             __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits
8004                                          *   is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0]
8005                                          *   bits = 00b).Note2: If the value of CTSUMCH0 was set to
8006                                          *   b'111111 in mode other than self-capacitor single scan
8007                                          *   mode, the measurement is stopped.                                         */
8008             uint8_t : 2;
8009         } CTSUMCH0_b;
8010     };
8011 
8012     union
8013     {
8014         __IOM uint8_t CTSUMCH1;        /*!< (@ 0x00000005) CTSU Measurement Channel Register 1                        */
8015 
8016         struct
8017         {
8018             __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1
8019                                         *   was set to b'111111, the measurement is stopped.                          */
8020             uint8_t : 2;
8021         } CTSUMCH1_b;
8022     };
8023 
8024     union
8025     {
8026         __IOM uint8_t CTSUCHAC[5];     /*!< (@ 0x00000006) CTSU Channel Enable Control Register                       */
8027 
8028         struct
8029         {
8030             __IOM uint8_t TS0 : 1;     /*!< [0..0] CTSU Channel Enable Control                                        */
8031             __IOM uint8_t TS1 : 1;     /*!< [1..1] CTSU Channel Enable Control                                        */
8032             __IOM uint8_t TS2 : 1;     /*!< [2..2] CTSU Channel Enable Control                                        */
8033             __IOM uint8_t TS3 : 1;     /*!< [3..3] CTSU Channel Enable Control                                        */
8034             __IOM uint8_t TS4 : 1;     /*!< [4..4] CTSU Channel Enable Control                                        */
8035             __IOM uint8_t TS5 : 1;     /*!< [5..5] CTSU Channel Enable Control                                        */
8036             __IOM uint8_t TS6 : 1;     /*!< [6..6] CTSU Channel Enable Control                                        */
8037             __IOM uint8_t TS7 : 1;     /*!< [7..7] CTSU Channel Enable Control                                        */
8038         } CTSUCHAC_b[5];
8039     };
8040 
8041     union
8042     {
8043         __IOM uint8_t CTSUCHTRC[5];    /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register             */
8044 
8045         struct
8046         {
8047             __IOM uint8_t TS0 : 1;     /*!< [0..0] CTSU Channel Transmit/Receive Control                              */
8048             __IOM uint8_t TS1 : 1;     /*!< [1..1] CTSU Channel Transmit/Receive Control                              */
8049             __IOM uint8_t TS2 : 1;     /*!< [2..2] CTSU Channel Transmit/Receive Control                              */
8050             __IOM uint8_t TS3 : 1;     /*!< [3..3] CTSU Channel Transmit/Receive Control                              */
8051             __IOM uint8_t TS4 : 1;     /*!< [4..4] CTSU Channel Transmit/Receive Control                              */
8052             __IOM uint8_t TS5 : 1;     /*!< [5..5] CTSU Channel Transmit/Receive Control                              */
8053             __IOM uint8_t TS6 : 1;     /*!< [6..6] CTSU Channel Transmit/Receive Control                              */
8054             __IOM uint8_t TS7 : 1;     /*!< [7..7] CTSU Channel Transmit/Receive Control                              */
8055         } CTSUCHTRC_b[5];
8056     };
8057 
8058     union
8059     {
8060         __IOM uint8_t CTSUDCLKC;         /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register            */
8061 
8062         struct
8063         {
8064             __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should
8065                                           *   be set to 00b.                                                            */
8066             uint8_t                 : 2;
8067             __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should
8068                                           *   be set to 11b.                                                            */
8069             uint8_t : 2;
8070         } CTSUDCLKC_b;
8071     };
8072 
8073     union
8074     {
8075         __IOM uint8_t CTSUST;           /*!< (@ 0x00000011) CTSU Status Register                                       */
8076 
8077         struct
8078         {
8079             __IM uint8_t CTSUSTC   : 3; /*!< [2..0] CTSU Measurement Status Counter                                    */
8080             uint8_t                : 1;
8081             __IM uint8_t  CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag                                     */
8082             __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag                                  */
8083             __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag                               */
8084             __IM uint8_t  CTSUPS   : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag                                */
8085         } CTSUST_b;
8086     };
8087 
8088     union
8089     {
8090         __IOM uint16_t CTSUSSC;        /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion
8091                                         *                  Control Register                                           */
8092 
8093         struct
8094         {
8095             uint16_t                 : 8;
8096             __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting                */
8097             uint16_t                 : 4;
8098         } CTSUSSC_b;
8099     };
8100 
8101     union
8102     {
8103         __IOM uint16_t CTSUSO0;          /*!< (@ 0x00000014) CTSU Sensor Offset Register 0                              */
8104 
8105         struct
8106         {
8107             __IOM uint16_t CTSUSO : 10;  /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is
8108                                           *   CTSUSO ( 0 to 1023 )                                                      */
8109             __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting                                   */
8110         } CTSUSO0_b;
8111     };
8112 
8113     union
8114     {
8115         __IOM uint16_t CTSUSO1;           /*!< (@ 0x00000016) CTSU Sensor Offset Register 1                              */
8116 
8117         struct
8118         {
8119             __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount
8120                                            *   is CTSUSO ( 0 to 255 )                                                    */
8121             __IOM uint16_t CTSUSDPA : 5;  /*!< [12..8] CTSU Base Clock SettingOperating clock divided by (
8122                                            *   CTSUSDPA + 1 ) x 2                                                        */
8123             __IOM uint16_t CTSUICOG : 2;  /*!< [14..13] CTSU ICO Gain Adjustment                                         */
8124             uint16_t                : 1;
8125         } CTSUSO1_b;
8126     };
8127 
8128     union
8129     {
8130         __IM uint16_t CTSUSC;          /*!< (@ 0x00000018) CTSU Sensor Counter                                        */
8131 
8132         struct
8133         {
8134             __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement
8135                                         *   result of the CTSU. These bits indicate FFFFh when an overflow
8136                                         *   occurs.                                                                   */
8137         } CTSUSC_b;
8138     };
8139 
8140     union
8141     {
8142         __IM uint16_t CTSURC;          /*!< (@ 0x0000001A) CTSU Reference Counter                                     */
8143 
8144         struct
8145         {
8146             __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement
8147                                         *   result of the reference ICO.These bits indicate FFFFh when
8148                                         *   an overflow occurs.                                                       */
8149         } CTSURC_b;
8150     };
8151 
8152     union
8153     {
8154         __IM uint16_t CTSUERRS;             /*!< (@ 0x0000001C) CTSU Error Status Register                                 */
8155 
8156         struct
8157         {
8158             __IOM uint16_t CTSUSPMD    : 2; /*!< [1..0] Calibration Mode                                                   */
8159             __IOM uint16_t CTSUTSOD    : 1; /*!< [2..2] TS Pin Fixed Output                                                */
8160             __IOM uint16_t CTSUDRV     : 1; /*!< [3..3] Calibration Setting 1                                              */
8161             uint16_t                   : 2;
8162             __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3                                              */
8163             __IOM uint16_t CTSUTSOC    : 1; /*!< [7..7] Calibration Setting 2                                              */
8164             uint16_t                   : 7;
8165             __IM uint16_t CTSUICOMP    : 1; /*!< [15..15] TSCAP Voltage Error Monitor                                      */
8166         } CTSUERRS_b;
8167     };
8168     __IM uint16_t RESERVED;
8169     __IOM uint8_t CTSUTRMR;                 /*!< (@ 0x00000020) CTSU Reference Current Calibration Register                */
8170     __IM uint8_t  RESERVED1;
8171     __IM uint16_t RESERVED2;
8172 } R_CTSU_Type;                              /*!< Size = 36 (0x24)                                                          */
8173 
8174 /* =========================================================================================================================== */
8175 /* ================                                          R_CTSU2                                          ================ */
8176 /* =========================================================================================================================== */
8177 
8178 /**
8179  * @brief Capacitive Touch Sensing Unit (R_CTSU2)
8180  */
8181 
8182 typedef struct                         /*!< (@ 0x40082000) R_CTSU2 Structure                                          */
8183 {
8184     union
8185     {
8186         union
8187         {
8188             __IOM uint32_t CTSUCRA;        /*!< (@ 0x00000000) CTSU Control Register A                                    */
8189 
8190             struct
8191             {
8192                 __IOM uint32_t STRT   : 1; /*!< [0..0] CTSU Measurement Operation Start                                   */
8193                 __IOM uint32_t CAP    : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select                    */
8194                 __IOM uint32_t SNZ    : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable                                */
8195                 __IOM uint32_t CFCON  : 1; /*!< [3..3] CTSU CFC Power on Control                                          */
8196                 __OM uint32_t  INIT   : 1; /*!< [4..4] CTSU Control Block Initialization                                  */
8197                 __IOM uint32_t PUMPON : 1; /*!< [5..5] CTSU Boost Circuit Control                                         */
8198                 __IOM uint32_t TXVSEL : 2; /*!< [7..6] CTSU Transmission Power Supply Selection                           */
8199                 __IOM uint32_t PON    : 1; /*!< [8..8] CTSU Power On Control                                              */
8200                 __IOM uint32_t CSW    : 1; /*!< [9..9] TSCAP Pin Enable                                                   */
8201                 __IOM uint32_t ATUNE0 : 1; /*!< [10..10] CTSU Power Supply Operating Mode Setting                         */
8202                 __IOM uint32_t ATUNE1 : 1; /*!< [11..11] CTSU Current Range Adjustment                                    */
8203                 __IOM uint32_t CLK    : 2; /*!< [13..12] CTSU Operating Clock Select                                      */
8204                 __IOM uint32_t MD0    : 1; /*!< [14..14] CTSU Measurement Mode Select 0                                   */
8205                 __IOM uint32_t MD1    : 1; /*!< [15..15] CTSU Measurement Mode Select 1                                   */
8206                 __IOM uint32_t MD2    : 1; /*!< [16..16] CTSU Measurement Mode Select 2                                   */
8207                 __IOM uint32_t ATUNE2 : 1; /*!< [17..17] CTSU Current Range Adjustment                                    */
8208                 __IOM uint32_t LOAD   : 2; /*!< [19..18] CTSU Load Control During Measurement                             */
8209                 __IOM uint32_t POSEL  : 2; /*!< [21..20] CTSU Non-measured Channel Output Select                          */
8210                 __IOM uint32_t SDPSEL : 1; /*!< [22..22] CTSU Sensor Drive Pulse Select                                   */
8211                 __IOM uint32_t PCSEL  : 1; /*!< [23..23] CTSU Boost Circuit Clock Select                                  */
8212                 __IOM uint32_t STCLK  : 6; /*!< [29..24] CTSU STCLK Select                                                */
8213                 __IOM uint32_t DCMODE : 1; /*!< [30..30] CTSU Current Measurement Mode Select                             */
8214                 __IOM uint32_t DCBACK : 1; /*!< [31..31] CTSU Current Measurement Feedback Select                         */
8215             } CTSUCRA_b;
8216         };
8217 
8218         struct
8219         {
8220             union
8221             {
8222                 __IOM uint16_t CTSUCRAL;   /*!< (@ 0x00000000) CTSU Control Register A                                    */
8223 
8224                 struct
8225                 {
8226                     __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register A                                    */
8227                     __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register A                                    */
8228                 };
8229             };
8230 
8231             union
8232             {
8233                 __IOM uint16_t CTSUCRAH;   /*!< (@ 0x00000002) CTSU Control Register A                                    */
8234 
8235                 struct
8236                 {
8237                     __IOM uint8_t CTSUCR2; /*!< (@ 0x00000002) CTSU Control Register A                                    */
8238                     __IOM uint8_t CTSUCR3; /*!< (@ 0x00000003) CTSU Control Register A                                    */
8239                 };
8240             };
8241         };
8242     };
8243 
8244     union
8245     {
8246         union
8247         {
8248             __IOM uint32_t CTSUCRB;         /*!< (@ 0x00000004) CTSU Control Register B                                    */
8249 
8250             struct
8251             {
8252                 __IOM uint32_t PRRATIO : 4; /*!< [3..0] Frequency of Drive Pulse Phase Control                             */
8253                 __IOM uint32_t PRMODE  : 2; /*!< [5..4] Phase Control Period                                               */
8254                 __IOM uint32_t SOFF    : 1; /*!< [6..6] High-Pass Noise Reduction Function Disable                         */
8255                 __IOM uint32_t PROFF   : 1; /*!< [7..7] Drive Pulse Phase Control                                          */
8256                 __IOM uint32_t SST     : 8; /*!< [15..8] Wait Time Sensor Stabilization                                    */
8257                 uint32_t               : 8;
8258                 __IOM uint32_t SSMOD   : 3; /*!< [26..24] Spread Spectrum Modulation Frequency                             */
8259                 uint32_t               : 1;
8260                 __IOM uint32_t SSCNT   : 2; /*!< [29..28] Adjusting the SUCLK frequency                                    */
8261                 uint32_t               : 2;
8262             } CTSUCRB_b;
8263         };
8264 
8265         struct
8266         {
8267             union
8268             {
8269                 __IOM uint16_t CTSUCRBL;     /*!< (@ 0x00000004) CTSU Control Register B                                    */
8270 
8271                 struct
8272                 {
8273                     __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000004) CTSU Control Register B                                    */
8274                     __IOM uint8_t CTSUSST;   /*!< (@ 0x00000005) CTSU Control Register B                                    */
8275                 };
8276             };
8277 
8278             union
8279             {
8280                 __IOM uint16_t CTSUCRBH; /*!< (@ 0x00000006) CTSU Control Register B                                    */
8281 
8282                 struct
8283                 {
8284                     __IM uint8_t  RESERVED;
8285                     __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000007) CTSU Control Register B                                    */
8286                 };
8287             };
8288         };
8289     };
8290 
8291     union
8292     {
8293         union
8294         {
8295             __IOM uint32_t CTSUMCH;      /*!< (@ 0x00000008) CTSU Measurement Channel Register                          */
8296 
8297             struct
8298             {
8299                 __IOM uint32_t MCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0                                         */
8300                 uint32_t            : 2;
8301                 __IOM uint32_t MCH1 : 6; /*!< [13..8] CTSU Measurement Channel 1                                        */
8302                 uint32_t            : 2;
8303                 __IOM uint32_t MCA0 : 1; /*!< [16..16] CTSU Multiple Valid Clock Control                                */
8304                 __IOM uint32_t MCA1 : 1; /*!< [17..17] CTSU Multiple Valid Clock Control                                */
8305                 __IOM uint32_t MCA2 : 1; /*!< [18..18] CTSU Multiple Valid Clock Control                                */
8306                 __IOM uint32_t MCA3 : 1; /*!< [19..19] CTSU Multiple Valid Clock Control                                */
8307                 uint32_t            : 12;
8308             } CTSUMCH_b;
8309         };
8310 
8311         struct
8312         {
8313             union
8314             {
8315                 __IOM uint16_t CTSUMCHL;    /*!< (@ 0x00000008) CTSU Measurement Channel Register                          */
8316 
8317                 struct
8318                 {
8319                     __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000008) CTSU Measurement Channel Register                          */
8320                     __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000009) CTSU Measurement Channel Register                          */
8321                 };
8322             };
8323 
8324             union
8325             {
8326                 __IOM uint16_t CTSUMCHH; /*!< (@ 0x0000000A) CTSU Measurement Channel Register                          */
8327                 __IOM uint8_t  CTSUMFAF; /*!< (@ 0x0000000A) CTSU Measurement Channel Register                          */
8328             };
8329         };
8330     };
8331 
8332     union
8333     {
8334         union
8335         {
8336             __IOM uint32_t CTSUCHACA;      /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A                     */
8337 
8338             struct
8339             {
8340                 __IOM uint32_t CHAC00 : 1; /*!< [0..0] CTSU Channel Enable Control A                                      */
8341                 uint32_t              : 1;
8342                 __IOM uint32_t CHAC02 : 1; /*!< [2..2] CTSU Channel Enable Control A                                      */
8343                 uint32_t              : 1;
8344                 __IOM uint32_t CHAC04 : 1; /*!< [4..4] CTSU Channel Enable Control A                                      */
8345                 __IOM uint32_t CHAC05 : 1; /*!< [5..5] CTSU Channel Enable Control A                                      */
8346                 __IOM uint32_t CHAC06 : 1; /*!< [6..6] CTSU Channel Enable Control A                                      */
8347                 __IOM uint32_t CHAC07 : 1; /*!< [7..7] CTSU Channel Enable Control A                                      */
8348                 __IOM uint32_t CHAC08 : 1; /*!< [8..8] CTSU Channel Enable Control A                                      */
8349                 __IOM uint32_t CHAC09 : 1; /*!< [9..9] CTSU Channel Enable Control A                                      */
8350                 __IOM uint32_t CHAC10 : 1; /*!< [10..10] CTSU Channel Enable Control A                                    */
8351                 __IOM uint32_t CHAC11 : 1; /*!< [11..11] CTSU Channel Enable Control A                                    */
8352                 __IOM uint32_t CHAC12 : 1; /*!< [12..12] CTSU Channel Enable Control A                                    */
8353                 __IOM uint32_t CHAC13 : 1; /*!< [13..13] CTSU Channel Enable Control A                                    */
8354                 __IOM uint32_t CHAC14 : 1; /*!< [14..14] CTSU Channel Enable Control A                                    */
8355                 __IOM uint32_t CHAC15 : 1; /*!< [15..15] CTSU Channel Enable Control A                                    */
8356                 __IOM uint32_t CHAC16 : 1; /*!< [16..16] CTSU Channel Enable Control A                                    */
8357                 __IOM uint32_t CHAC17 : 1; /*!< [17..17] CTSU Channel Enable Control A                                    */
8358                 __IOM uint32_t CHAC18 : 1; /*!< [18..18] CTSU Channel Enable Control A                                    */
8359                 uint32_t              : 2;
8360                 __IOM uint32_t CHAC21 : 1; /*!< [21..21] CTSU Channel Enable Control A                                    */
8361                 __IOM uint32_t CHAC22 : 1; /*!< [22..22] CTSU Channel Enable Control A                                    */
8362                 __IOM uint32_t CHAC23 : 1; /*!< [23..23] CTSU Channel Enable Control A                                    */
8363                 __IOM uint32_t CHAC24 : 1; /*!< [24..24] CTSU Channel Enable Control A                                    */
8364                 __IOM uint32_t CHAC25 : 1; /*!< [25..25] CTSU Channel Enable Control A                                    */
8365                 __IOM uint32_t CHAC26 : 1; /*!< [26..26] CTSU Channel Enable Control A                                    */
8366                 __IOM uint32_t CHAC27 : 1; /*!< [27..27] CTSU Channel Enable Control A                                    */
8367                 __IOM uint32_t CHAC28 : 1; /*!< [28..28] CTSU Channel Enable Control A                                    */
8368                 __IOM uint32_t CHAC29 : 1; /*!< [29..29] CTSU Channel Enable Control A                                    */
8369                 __IOM uint32_t CHAC30 : 1; /*!< [30..30] CTSU Channel Enable Control A                                    */
8370                 __IOM uint32_t CHAC31 : 1; /*!< [31..31] CTSU Channel Enable Control A                                    */
8371             } CTSUCHACA_b;
8372         };
8373 
8374         struct
8375         {
8376             union
8377             {
8378                 __IOM uint16_t CTSUCHACAL;   /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A                     */
8379 
8380                 struct
8381                 {
8382                     __IOM uint8_t CTSUCHAC0; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A                     */
8383                     __IOM uint8_t CTSUCHAC1; /*!< (@ 0x0000000D) CTSU Channel Enable Control Register A                     */
8384                 };
8385             };
8386 
8387             union
8388             {
8389                 __IOM uint16_t CTSUCHACAH;   /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A                     */
8390 
8391                 struct
8392                 {
8393                     __IOM uint8_t CTSUCHAC2; /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A                     */
8394                     __IOM uint8_t CTSUCHAC3; /*!< (@ 0x0000000F) CTSU Channel Enable Control Register A                     */
8395                 };
8396             };
8397         };
8398     };
8399 
8400     union
8401     {
8402         union
8403         {
8404             __IOM uint32_t CTSUCHACB;      /*!< (@ 0x00000010) CTSU Channel Enable Control Register B                     */
8405 
8406             struct
8407             {
8408                 __IOM uint32_t CHAC32 : 1; /*!< [0..0] CTSU Channel Enable Control B                                      */
8409                 __IOM uint32_t CHAC33 : 1; /*!< [1..1] CTSU Channel Enable Control B                                      */
8410                 __IOM uint32_t CHAC34 : 1; /*!< [2..2] CTSU Channel Enable Control B                                      */
8411                 __IOM uint32_t CHAC35 : 1; /*!< [3..3] CTSU Channel Enable Control B                                      */
8412                 uint32_t              : 28;
8413             } CTSUCHACB_b;
8414         };
8415         __IOM uint16_t CTSUCHACBL;         /*!< (@ 0x00000010) CTSU Channel Enable Control Register B                     */
8416         __IOM uint8_t  CTSUCHAC4;          /*!< (@ 0x00000010) CTSU Channel Enable Control Register B                     */
8417     };
8418 
8419     union
8420     {
8421         union
8422         {
8423             __IOM uint32_t CTSUCHTRCA;      /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register
8424                                              *                  A                                                          */
8425 
8426             struct
8427             {
8428                 __IOM uint32_t CHTRC   : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control A                            */
8429                 uint32_t               : 1;
8430                 __IOM uint32_t CHTRC02 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control A                            */
8431                 uint32_t               : 1;
8432                 __IOM uint32_t CHTRC04 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control A                            */
8433                 __IOM uint32_t CHTRC05 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control A                            */
8434                 __IOM uint32_t CHTRC06 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control A                            */
8435                 __IOM uint32_t CHTRC07 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control A                            */
8436                 __IOM uint32_t CHTRC08 : 1; /*!< [8..8] CTSU Channel Transmit/Receive Control A                            */
8437                 __IOM uint32_t CHTRC09 : 1; /*!< [9..9] CTSU Channel Transmit/Receive Control A                            */
8438                 __IOM uint32_t CHTRC10 : 1; /*!< [10..10] CTSU Channel Transmit/Receive Control A                          */
8439                 __IOM uint32_t CHTRC11 : 1; /*!< [11..11] CTSU Channel Transmit/Receive Control A                          */
8440                 __IOM uint32_t CHTRC12 : 1; /*!< [12..12] CTSU Channel Transmit/Receive Control A                          */
8441                 __IOM uint32_t CHTRC13 : 1; /*!< [13..13] CTSU Channel Transmit/Receive Control A                          */
8442                 __IOM uint32_t CHTRC14 : 1; /*!< [14..14] CTSU Channel Transmit/Receive Control A                          */
8443                 __IOM uint32_t CHTRC15 : 1; /*!< [15..15] CTSU Channel Transmit/Receive Control A                          */
8444                 __IOM uint32_t CHTRC16 : 1; /*!< [16..16] CTSU Channel Transmit/Receive Control A                          */
8445                 __IOM uint32_t CHTRC17 : 1; /*!< [17..17] CTSU Channel Transmit/Receive Control A                          */
8446                 __IOM uint32_t CHTRC18 : 1; /*!< [18..18] CTSU Channel Transmit/Receive Control A                          */
8447                 uint32_t               : 2;
8448                 __IOM uint32_t CHTRC21 : 1; /*!< [21..21] CTSU Channel Transmit/Receive Control A                          */
8449                 __IOM uint32_t CHTRC22 : 1; /*!< [22..22] CTSU Channel Transmit/Receive Control A                          */
8450                 __IOM uint32_t CHTRC23 : 1; /*!< [23..23] CTSU Channel Transmit/Receive Control A                          */
8451                 __IOM uint32_t CHTRC24 : 1; /*!< [24..24] CTSU Channel Transmit/Receive Control A                          */
8452                 __IOM uint32_t CHTRC25 : 1; /*!< [25..25] CTSU Channel Transmit/Receive Control A                          */
8453                 __IOM uint32_t CHTRC26 : 1; /*!< [26..26] CTSU Channel Transmit/Receive Control A                          */
8454                 __IOM uint32_t CHTRC27 : 1; /*!< [27..27] CTSU Channel Transmit/Receive Control A                          */
8455                 __IOM uint32_t CHTRC28 : 1; /*!< [28..28] CTSU Channel Transmit/Receive Control A                          */
8456                 __IOM uint32_t CHTRC29 : 1; /*!< [29..29] CTSU Channel Transmit/Receive Control A                          */
8457                 __IOM uint32_t CHTRC30 : 1; /*!< [30..30] CTSU Channel Transmit/Receive Control A                          */
8458                 __IOM uint32_t CHTRC31 : 1; /*!< [31..31] CTSU Channel Transmit/Receive Control A                          */
8459             } CTSUCHTRCA_b;
8460         };
8461 
8462         struct
8463         {
8464             union
8465             {
8466                 __IOM uint16_t CTSUCHTRCAL;   /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register
8467                                                *                  A                                                          */
8468 
8469                 struct
8470                 {
8471                     __IOM uint8_t CTSUCHTRC0; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register
8472                                                *                  A                                                          */
8473                     __IOM uint8_t CTSUCHTRC1; /*!< (@ 0x00000015) CTSU Channel Transmit/Receive Control Register
8474                                                *                  A                                                          */
8475                 };
8476             };
8477 
8478             union
8479             {
8480                 __IOM uint16_t CTSUCHTRCAH;   /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register
8481                                                *                  A                                                          */
8482 
8483                 struct
8484                 {
8485                     __IOM uint8_t CTSUCHTRC2; /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register
8486                                                *                  A                                                          */
8487                     __IOM uint8_t CTSUCHTRC3; /*!< (@ 0x00000017) CTSU Channel Transmit/Receive Control Register
8488                                                *                  A                                                          */
8489                 };
8490             };
8491         };
8492     };
8493 
8494     union
8495     {
8496         union
8497         {
8498             __IOM uint32_t CTSUCHTRCB;      /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register
8499                                              *                  B                                                          */
8500 
8501             struct
8502             {
8503                 __IOM uint32_t CHTRC32 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control B                            */
8504                 __IOM uint32_t CHTRC33 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control B                            */
8505                 __IOM uint32_t CHTRC34 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control B                            */
8506                 __IOM uint32_t CHTRC35 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control B                            */
8507                 uint32_t               : 28;
8508             } CTSUCHTRCB_b;
8509         };
8510         __IOM uint16_t CTSUCHTRCBL;         /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register
8511                                              *                  B                                                          */
8512         __IOM uint8_t CTSUCHTRC4;           /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register
8513                                              *                  B                                                          */
8514     };
8515 
8516     union
8517     {
8518         union
8519         {
8520             __IOM uint32_t CTSUSR;          /*!< (@ 0x0000001C) CTSU Status Register                                       */
8521 
8522             struct
8523             {
8524                 __IOM uint32_t MFC     : 2; /*!< [1..0] CTSU Multi-clock Counter                                           */
8525                 uint32_t               : 3;
8526                 __OM uint32_t ICOMPRST : 1; /*!< [5..5] CTSU CTSUICOMP1 Flag Reset                                         */
8527                 __IM uint32_t ICOMP1   : 1; /*!< [6..6] CTSU Sense Current Error Monitor                                   */
8528                 __IM uint32_t ICOMP0   : 1; /*!< [7..7] TSCAP Voltage Error Monitor                                        */
8529                 __IM uint32_t STC      : 3; /*!< [10..8] CTSU Measurement Status Counter                                   */
8530                 uint32_t               : 1;
8531                 __IM uint32_t  DTSR    : 1; /*!< [12..12] CTSU Data Transfer Status Flag                                   */
8532                 __IOM uint32_t SENSOVF : 1; /*!< [13..13] CTSU Sensor Counter Overflow Flag                                */
8533                 __IOM uint32_t SUOVF   : 1; /*!< [14..14] CTSU SUCLK Counter Overflow Flag                                 */
8534                 __IM uint32_t  PS      : 1; /*!< [15..15] CTSU Mutual Capacitance Status Flag                              */
8535                 __IOM uint32_t CFCRDCH : 6; /*!< [21..16] CTSU CFC Read Channel Select                                     */
8536                 uint32_t               : 10;
8537             } CTSUSR_b;
8538         };
8539 
8540         struct
8541         {
8542             union
8543             {
8544                 __IOM uint16_t CTSUSRL;    /*!< (@ 0x0000001C) CTSU Status Register                                       */
8545 
8546                 struct
8547                 {
8548                     __IOM uint8_t CTSUSR0; /*!< (@ 0x0000001C) CTSU Status Register                                       */
8549                     __IOM uint8_t CTSUST;  /*!< (@ 0x0000001D) CTSU Status Register                                       */
8550                 };
8551             };
8552 
8553             union
8554             {
8555                 __IOM uint16_t CTSUSRH; /*!< (@ 0x0000001E) CTSU Status Register                                       */
8556                 __IOM uint8_t  CTSUSR2; /*!< (@ 0x0000001E) CTSU Status Register                                       */
8557             };
8558         };
8559     };
8560 
8561     union
8562     {
8563         union
8564         {
8565             __IOM uint32_t CTSUSO;         /*!< (@ 0x00000020) CTSU Sensor Offset Register                                */
8566 
8567             struct
8568             {
8569                 __IOM uint32_t SO    : 10; /*!< [9..0] CTSU Sensor Offset Adjustment                                      */
8570                 __IOM uint32_t SNUM  : 8;  /*!< [17..10] CTSU Measurement Count Setting                                   */
8571                 uint32_t             : 2;
8572                 __IOM uint32_t SSDIV : 4;  /*!< [23..20] Spread Spectrum Frequency                                        */
8573                 __IOM uint32_t SDPA  : 8;  /*!< [31..24] CTSU Base Clock Setting                                          */
8574             } CTSUSO_b;
8575         };
8576 
8577         struct
8578         {
8579             __IOM uint16_t CTSUSO0;    /*!< (@ 0x00000020) CTSU Sensor Offset Register                                */
8580             __IOM uint16_t CTSUSO1;    /*!< (@ 0x00000022) CTSU Sensor Offset Register                                */
8581         };
8582     };
8583 
8584     union
8585     {
8586         union
8587         {
8588             __IM uint32_t CTSUSCNT;         /*!< (@ 0x00000024) CTSU Sensor Counter Register                               */
8589 
8590             struct
8591             {
8592                 __IM uint32_t SENSCNT : 16; /*!< [15..0] CTSU Sensor Counter                                               */
8593                 __IM uint32_t SUCKCNT : 16; /*!< [31..16] CTSU SUCLK Counter                                               */
8594             } CTSUSCNT_b;
8595         };
8596         __IM uint16_t CTSUSC;               /*!< (@ 0x00000024) CTSU Sensor Counter Register                               */
8597     };
8598 
8599     union
8600     {
8601         union
8602         {
8603             __IOM uint32_t CTSUCALIB;  /*!< (@ 0x00000028) CTSU Calibration Register                                  */
8604 
8605             struct
8606             {
8607                 uint32_t                : 2;
8608                 __IOM uint32_t TSOD     : 1; /*!< [2..2] TS Pins Fixed Output                                               */
8609                 __IOM uint32_t DRV      : 1; /*!< [3..3] Power Supply Calibration Select                                    */
8610                 __IOM uint32_t CLKSEL   : 2; /*!< [5..4] Observation Clock Select                                           */
8611                 __IOM uint32_t SUCLKEN  : 1; /*!< [6..6] SUCLK Forced Oscillation Control                                   */
8612                 __IOM uint32_t TSOC     : 1; /*!< [7..7] Switched Capacitor Operation Calibration Select Bit                */
8613                 __IOM uint32_t CNTRDSEL : 1; /*!< [8..8] Read Count Select of Sensor Counter                                */
8614                 __IOM uint32_t IOC      : 1; /*!< [9..9] TS Pin Fixed Output Value Set                                      */
8615                 __IOM uint32_t CFCRDMD  : 1; /*!< [10..10] CFC Counter Read Mode Select                                     */
8616                 __IOM uint32_t DCOFF    : 1; /*!< [11..11] Down Converter Control                                           */
8617                 uint32_t                : 4;
8618                 __IOM uint32_t CFCSEL   : 6; /*!< [21..16] Observation CFC Clock Select                                     */
8619                 __IOM uint32_t CFCMODE  : 1; /*!< [22..22] CFC Oscillator Calibration Mode Select                           */
8620                 uint32_t                : 1;
8621                 __IOM uint32_t DACMSEL  : 1; /*!< [24..24] Current Offset DAC Current Matrix Calibration Select             */
8622                 __IOM uint32_t DACCARRY : 1; /*!< [25..25] Offset Current Adjustment for Calibration                        */
8623                 __IOM uint32_t SUMSEL   : 1; /*!< [26..26] Current Control Oscillator Input Current Matrix Calibration
8624                                               *   Select                                                                    */
8625                 __IOM uint32_t SUCARRY : 1;  /*!< [27..27] Current Control Oscillator Input Current Adjustment
8626                                               *   for SUCLK                                                                 */
8627                 __IOM uint32_t DACCLK : 1;   /*!< [28..28] Modulation Clock Select for Offset Current Circuits              */
8628                 __IOM uint32_t CCOCLK : 1;   /*!< [29..29] Modulation Clock Select for Current Controlled Oscillator
8629                                               *   Input Current of SUCLK                                                    */
8630                 __IOM uint32_t CCOCALIB : 1; /*!< [30..30] Calibration Selection of Current Controlled Oscillator
8631                                               *   for Measurement                                                           */
8632                 __IOM uint32_t TXREV : 1;    /*!< [31..31] Transmit Pin Inverted Output                                     */
8633             } CTSUCALIB_b;
8634         };
8635 
8636         struct
8637         {
8638             __IOM uint16_t CTSUDBGR0;  /*!< (@ 0x00000028) CTSU Calibration Register                                  */
8639             __IOM uint16_t CTSUDBGR1;  /*!< (@ 0x0000002A) CTSU Calibration Register                                  */
8640         };
8641     };
8642 
8643     union
8644     {
8645         union
8646         {
8647             __IOM uint32_t CTSUSUCLKA;       /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A                  */
8648 
8649             struct
8650             {
8651                 __IOM uint32_t SUADJ0   : 8; /*!< [7..0] CTSU SUCLK Frequency Adjustment                                    */
8652                 __IOM uint32_t SUMULTI0 : 8; /*!< [15..8] CTSU SUCLK Multiplier Rate Setting                                */
8653                 __IOM uint32_t SUADJ1   : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment                                  */
8654                 __IOM uint32_t SUMULTI1 : 8; /*!< [31..24] CTSU SUCLK Multiplier Rate Setting                               */
8655             } CTSUSUCLKA_b;
8656         };
8657 
8658         struct
8659         {
8660             __IOM uint16_t CTSUSUCLK0; /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A                  */
8661             __IOM uint16_t CTSUSUCLK1; /*!< (@ 0x0000002E) CTSU Sensor Unit Clock Control Register A                  */
8662         };
8663     };
8664 
8665     union
8666     {
8667         union
8668         {
8669             __IOM uint32_t CTSUSUCLKB;       /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B                  */
8670 
8671             struct
8672             {
8673                 __IOM uint32_t SUADJ2   : 8; /*!< [7..0] CTSU SUCLK Frequency Adjustment                                    */
8674                 __IOM uint32_t SUMULTI2 : 8; /*!< [15..8] CTSU SUCLK Multiplier Rate Setting                                */
8675                 __IOM uint32_t SUADJ3   : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment                                  */
8676                 __IOM uint32_t SUMULTI3 : 8; /*!< [31..24] CTSU SUCLK Multiplier Rate Setting                               */
8677             } CTSUSUCLKB_b;
8678         };
8679 
8680         struct
8681         {
8682             __IOM uint16_t CTSUSUCLK2; /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B                  */
8683             __IOM uint16_t CTSUSUCLK3; /*!< (@ 0x00000032) CTSU Sensor Unit Clock Control Register B                  */
8684         };
8685     };
8686 
8687     union
8688     {
8689         union
8690         {
8691             __IM uint32_t CTSUCFCCNT;      /*!< (@ 0x00000034) CTSU CFC Counter Register                                  */
8692 
8693             struct
8694             {
8695                 __IM uint32_t CFCCNT : 16; /*!< [15..0] CTSU CFC Counter                                                  */
8696                 uint32_t             : 16;
8697             } CTSUCFCCNT_b;
8698         };
8699         __IM uint16_t CTSUCFCCNTL;         /*!< (@ 0x00000034) CTSU CFC Counter Register                                  */
8700     };
8701 } R_CTSU2_Type;                            /*!< Size = 56 (0x38)                                                          */
8702 
8703 /* =========================================================================================================================== */
8704 /* ================                                           R_DAC                                           ================ */
8705 /* =========================================================================================================================== */
8706 
8707 /**
8708  * @brief D/A Converter (R_DAC)
8709  */
8710 
8711 typedef struct                         /*!< (@ 0x4005E000) R_DAC Structure                                            */
8712 {
8713     union
8714     {
8715         __IOM uint16_t DADR[2];        /*!< (@ 0x00000000) D/A Data Register                                          */
8716 
8717         struct
8718         {
8719             __IOM uint16_t DADR : 16;  /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order
8720                                         *   4 bits are fixed to 0: right justified format. When DADPR.DPSEL
8721                                         *   = 1, the low-order 4 bits are fixed to 0: left justified
8722                                         *   format.                                                                   */
8723         } DADR_b[2];
8724     };
8725 
8726     union
8727     {
8728         __IOM uint8_t DACR;            /*!< (@ 0x00000004) D/A Control Register                                       */
8729 
8730         struct
8731         {
8732             uint8_t             : 5;
8733             __IOM uint8_t DAE   : 1;   /*!< [5..5] D/A Enable                                                         */
8734             __IOM uint8_t DAOE0 : 1;   /*!< [6..6] D/A Output Enable 0                                                */
8735             __IOM uint8_t DAOE1 : 1;   /*!< [7..7] D/A Output Enable 0                                                */
8736         } DACR_b;
8737     };
8738 
8739     union
8740     {
8741         __IOM uint8_t DADPR;           /*!< (@ 0x00000005) DADR0 Format Select Register                               */
8742 
8743         struct
8744         {
8745             uint8_t             : 7;
8746             __IOM uint8_t DPSEL : 1;   /*!< [7..7] DADRm Format Select                                                */
8747         } DADPR_b;
8748     };
8749 
8750     union
8751     {
8752         __IOM uint8_t DAADSCR;         /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register                 */
8753 
8754         struct
8755         {
8756             uint8_t              : 7;
8757             __IOM uint8_t DAADST : 1;  /*!< [7..7] D/A-A/D Synchronous Conversion                                     */
8758         } DAADSCR_b;
8759     };
8760 
8761     union
8762     {
8763         __IOM uint8_t DAVREFCR;        /*!< (@ 0x00000007) D/A VREF Control Register                                  */
8764 
8765         struct
8766         {
8767             __IOM uint8_t REF : 3;     /*!< [2..0] D/A Reference Voltage Select                                       */
8768             uint8_t           : 5;
8769         } DAVREFCR_b;
8770     };
8771 
8772     union
8773     {
8774         __IOM uint8_t DAAMPCR;         /*!< (@ 0x00000008) D/A Output Amplifier Control Register                      */
8775 
8776         struct
8777         {
8778             uint8_t              : 6;
8779             __IOM uint8_t DAAMP0 : 1;  /*!< [6..6] Amplifier Control                                                  */
8780             __IOM uint8_t DAAMP1 : 1;  /*!< [7..7] Amplifier Control                                                  */
8781         } DAAMPCR_b;
8782     };
8783 
8784     union
8785     {
8786         __IOM uint8_t DAPC;            /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register                    */
8787 
8788         struct
8789         {
8790             __IOM uint8_t PUMPEN : 1;  /*!< [0..0] Charge Pump Enable                                                 */
8791             uint8_t              : 7;
8792         } DAPC_b;
8793     };
8794     __IM uint16_t RESERVED[9];
8795 
8796     union
8797     {
8798         __IOM uint8_t DAASWCR;         /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register          */
8799 
8800         struct
8801         {
8802             uint8_t              : 6;
8803             __IOM uint8_t DAASW0 : 1;  /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure
8804                                         *   to wait for stabilization of the output amplifier of D/A
8805                                         *   channel 0. When DAASW0 is set to 1, D/A conversion operates,
8806                                         *   but the conversion result D/A is not output from channel
8807                                         *   0. When the DAASW0 bit is 0, the stabilization wait time
8808                                         *   stops, and the D/A conversion result of channel 0 is output
8809                                         *   through the output amplifier.                                             */
8810             __IOM uint8_t DAASW1 : 1;  /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure
8811                                         *   to wait for stabilization of the output amplifier of D/A
8812                                         *   channel 1. When DAASW1 is set to 1, D/A conversion operates,
8813                                         *   but the conversion result D/A is not output from channel
8814                                         *   1. When the DAASW1 bit is 0, the stabilization wait time
8815                                         *   stops, and the D/A conversion result of channel 1 is output
8816                                         *   through the output amplifier.                                             */
8817         } DAASWCR_b;
8818     };
8819     __IM uint8_t  RESERVED1;
8820     __IM uint16_t RESERVED2[2129];
8821 
8822     union
8823     {
8824         __IOM uint8_t DAADUSR;         /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register                   */
8825 
8826         struct
8827         {
8828             uint8_t                : 6;
8829             __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for
8830                                          *   D/A and A/D synchronous conversions. Set bit [1] to 1 to
8831                                          *   select unit 1 as the target synchronous unit for the MCU.
8832                                          *   When setting the DAADSCR.DAADST bit to 1 for synchronous
8833                                          *   conversions, select the target unit in this register in
8834                                          *   advance. Only set the DAADUSR register while the ADCSR.ADST
8835                                          *   bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
8836                                          *   is set to 0.                                                              */
8837             uint8_t : 1;
8838         } DAADUSR_b;
8839     };
8840     __IM uint8_t  RESERVED3;
8841     __IM uint16_t RESERVED4;
8842 } R_DAC_Type;                          /*!< Size = 4292 (0x10c4)                                                      */
8843 
8844 /* =========================================================================================================================== */
8845 /* ================                                          R_DAC8                                           ================ */
8846 /* =========================================================================================================================== */
8847 
8848 /**
8849  * @brief 8-Bit D/A Converter (R_DAC8)
8850  */
8851 
8852 typedef struct                         /*!< (@ 0x4009E000) R_DAC8 Structure                                           */
8853 {
8854     union
8855     {
8856         __IOM uint8_t DACS[2];         /*!< (@ 0x00000000) D/A Conversion Value Setting Register [0..1]               */
8857 
8858         struct
8859         {
8860             __IOM uint8_t DACS : 8;    /*!< [7..0] DACS D/A conversion store data                                     */
8861         } DACS_b[2];
8862     };
8863     __IM uint8_t RESERVED;
8864 
8865     union
8866     {
8867         __IOM uint8_t DAM;             /*!< (@ 0x00000003) D/A Converter Mode Register                                */
8868 
8869         struct
8870         {
8871             __IOM uint8_t DAMD0 : 1;   /*!< [0..0] D/A operation mode select 0                                        */
8872             __IOM uint8_t DAMD1 : 1;   /*!< [1..1] D/A operation mode select 1                                        */
8873             uint8_t             : 2;
8874             __IOM uint8_t DACE0 : 1;   /*!< [4..4] D/A operation enable 0                                             */
8875             __IOM uint8_t DACE1 : 1;   /*!< [5..5] D/A operation enable 1                                             */
8876             uint8_t             : 2;
8877         } DAM_b;
8878     };
8879     __IM uint8_t RESERVED1[2];
8880 
8881     union
8882     {
8883         __IOM uint8_t DACADSCR;        /*!< (@ 0x00000006) D/A A/D Synchronous Start Control Register                 */
8884 
8885         struct
8886         {
8887             __IOM uint8_t DACADST : 1; /*!< [0..0] D/A A/D Synchronous Conversion                                     */
8888             uint8_t               : 7;
8889         } DACADSCR_b;
8890     };
8891 
8892     union
8893     {
8894         __IOM uint8_t DACPC;           /*!< (@ 0x00000007) D/A SW Charge Pump Control Register                        */
8895 
8896         struct
8897         {
8898             __IOM uint8_t PUMPEN : 1;  /*!< [0..0] Charge pump enable                                                 */
8899             uint8_t              : 7;
8900         } DACPC_b;
8901     };
8902 } R_DAC8_Type;                         /*!< Size = 8 (0x8)                                                            */
8903 
8904 /* =========================================================================================================================== */
8905 /* ================                                          R_DALI0                                          ================ */
8906 /* =========================================================================================================================== */
8907 
8908 /**
8909  * @brief Digital Addressable Lighting Interface (R_DALI0)
8910  */
8911 
8912 typedef struct                         /*!< (@ 0x4008F000) R_DALI0 Structure                                          */
8913 {
8914     union
8915     {
8916         __IOM uint16_t BTVTHR1;        /*!< (@ 0x00000000) DALI Bit Timing Violation Threshold Register
8917                                         *                  1                                                          */
8918 
8919         struct
8920         {
8921             __IOM uint16_t BTV1 : 7;   /*!< [6..0] Bit Timing Violation Threshold 1Specifies the bit timing
8922                                         *   violation threshold value 1.Note 1. These bits must be
8923                                         *   modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE
8924                                         *   bit is 0.                                                                 */
8925             uint16_t            : 1;
8926             __IOM uint16_t BTV2 : 8;   /*!< [15..8] Bit Timing Violation Threshold 2Specifies the bit timing
8927                                         *   violation threshold value 2.Note 1. These bits must be
8928                                         *   modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE
8929                                         *   bit is 0.                                                                 */
8930         } BTVTHR1_b;
8931     };
8932 
8933     union
8934     {
8935         __IOM uint16_t BTVTHR2;        /*!< (@ 0x00000002) DALI Bit Timing Violation Threshold Register
8936                                         *                  2                                                          */
8937 
8938         struct
8939         {
8940             __IOM uint16_t BTV3 : 8;   /*!< [7..0] Bit Timing Violation Threshold 3Specifies the bit timing
8941                                         *   violation threshold value 3.Note 1. These bits must be
8942                                         *   modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE
8943                                         *   bit is 0.                                                                 */
8944             __IOM uint16_t BTV4 : 8;   /*!< [15..8] Bit Timing Violation Threshold 4Specifies the bit timing
8945                                         *   violation threshold value 4.Note 1. These bits must be
8946                                         *   modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE
8947                                         *   bit is 0.                                                                 */
8948         } BTVTHR2_b;
8949     };
8950 
8951     union
8952     {
8953         __IOM uint16_t BTVTHR3;        /*!< (@ 0x00000004) DALI Bit Timing Violation Threshold Register
8954                                         *                  3                                                          */
8955 
8956         struct
8957         {
8958             __IOM uint16_t BTV5 : 8;   /*!< [7..0] Bit Timing Violation Threshold 5Specifies the bit timing
8959                                         *   violation threshold value 5.Note 1. These bits must be
8960                                         *   modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE
8961                                         *   bit is 0.                                                                 */
8962             uint16_t : 8;
8963         } BTVTHR3_b;
8964     };
8965 
8966     union
8967     {
8968         __IOM uint16_t BTVTHR4;        /*!< (@ 0x00000006) DALI Bit Timing Violation Threshold Register
8969                                         *                  4                                                          */
8970 
8971         struct
8972         {
8973             __IOM uint16_t BTV6 : 9;   /*!< [8..0] Bit Timing Violation Threshold 6Specifies the bit timing
8974                                         *   violation threshold value 6.Note 1. These bits must be
8975                                         *   modified when the DALI0.CTR1.RE bit is 0 and the DALI0.CTR1.TE
8976                                         *   bit is 0.                                                                 */
8977             uint16_t : 7;
8978         } BTVTHR4_b;
8979     };
8980 
8981     union
8982     {
8983         __IOM uint16_t COLTHR1;        /*!< (@ 0x00000008) DALI Collision Threshold Register 1                        */
8984 
8985         struct
8986         {
8987             __IOM uint16_t COL1 : 6;   /*!< [5..0] Collision Threshold 1Specifies the collision threshold
8988                                         *   value 1.Note 1. These bits must be modified when the DALI0.CTR1.RE
8989                                         *   bit is 0 and the DALI0.CTR1.TE bit is 0.                                  */
8990             uint16_t            : 2;
8991             __IOM uint16_t COL2 : 6;   /*!< [13..8] Collision Threshold 2Specifies the collision threshold
8992                                         *   value 2.Note 1. These bits must be modified when the DALI0.CTR1.RE
8993                                         *   bit is 0 and the DALI0.CTR1.TE bit is 0.                                  */
8994             uint16_t : 2;
8995         } COLTHR1_b;
8996     };
8997 
8998     union
8999     {
9000         __IOM uint16_t COLTHR2;        /*!< (@ 0x0000000A) DALI Collision Threshold Register 2                        */
9001 
9002         struct
9003         {
9004             __IOM uint16_t COL3 : 7;   /*!< [6..0] Collision Threshold 3Specifies the collision threshold
9005                                         *   value 3.Note 1. These bits must be modified when the DALI0.CTR1.RE
9006                                         *   bit is 0 and the DALI0.CTR1.TE bit is 0.                                  */
9007             uint16_t            : 1;
9008             __IOM uint16_t COL4 : 7;   /*!< [14..8] Collision Threshold 4Specifies the collision threshold
9009                                         *   value 4.Note 1. These bits must be modified when the DALI0.CTR1.RE
9010                                         *   bit is 0 and the DALI0.CTR1.TE bit is 0.                                  */
9011             uint16_t : 1;
9012         } COLTHR2_b;
9013     };
9014 
9015     union
9016     {
9017         __IOM uint16_t COLTHR3;        /*!< (@ 0x0000000C) DALI Collision Threshold Register 3                        */
9018 
9019         struct
9020         {
9021             __IOM uint16_t COL5 : 7;   /*!< [6..0] Collision Threshold 5Specifies the collision threshold
9022                                         *   value 5.Note 1. These bits must be modified when the DALI0.CTR1.RE
9023                                         *   bit is 0 and the DALI0.CTR1.TE bit is 0.                                  */
9024             uint16_t            : 1;
9025             __IOM uint16_t COL6 : 7;   /*!< [14..8] Collision Threshold 6Specifies the collision threshold
9026                                         *   value 6.Note 1. These bits must be modified when the DALI0.CTR1.RE
9027                                         *   bit is 0 and the DALI0.CTR1.TE bit is 0.                                  */
9028             uint16_t : 1;
9029         } COLTHR3_b;
9030     };
9031 
9032     union
9033     {
9034         __IOM uint16_t COLTHR4;        /*!< (@ 0x0000000E) DALI Collision Threshold Register 4                        */
9035 
9036         struct
9037         {
9038             __IOM uint16_t COL7 : 8;   /*!< [7..0] Collision Threshold 7Specifies the collision threshold
9039                                         *   value 7.Note 1. These bits must be modified when the DALI0.CTR1.RE
9040                                         *   bit is 0 and the DALI0.CTR1.TE bit is 0.                                  */
9041             __IOM uint16_t COL8 : 8;   /*!< [15..8] Collision Threshold 8Specifies the collision threshold
9042                                         *   value 8.Note 1. These bits must be modified when the DALI0.CTR1.RE
9043                                         *   bit is 0 and the DALI0.CTR1.TE bit is 0.                                  */
9044         } COLTHR4_b;
9045     };
9046 
9047     union
9048     {
9049         __IOM uint16_t COLTHR5;        /*!< (@ 0x00000010) DALI Collision Threshold Register 5                        */
9050 
9051         struct
9052         {
9053             __IOM uint16_t COL9 : 8;   /*!< [7..0] Collision Threshold 9Specifies the collision threshold
9054                                         *   value 9.Note 1. These bits must be modified when the DALI0.CTR1.RE
9055                                         *   bit is 0 and the DALI0.CTR1.TE bit is 0.                                  */
9056             uint16_t : 8;
9057         } COLTHR5_b;
9058     };
9059 
9060     union
9061     {
9062         __IOM uint16_t CNFR1;          /*!< (@ 0x00000012) DALI Configuration Register 1                              */
9063 
9064         struct
9065         {
9066             __IOM uint16_t BR  : 8;    /*!< [7..0] Clock SelectBit rate setting example is shown in Table             */
9067             __IOM uint16_t CKS : 2;    /*!< [9..8] Clock Select                                                       */
9068             uint16_t           : 2;
9069             __IOM uint16_t CHL : 3;    /*!< [14..12] Character Length                                                 */
9070             uint16_t           : 1;
9071         } CNFR1_b;
9072     };
9073 
9074     union
9075     {
9076         __IOM uint16_t CNFR2;          /*!< (@ 0x00000014) DALI Configuration Register 2                              */
9077 
9078         struct
9079         {
9080             __IOM uint16_t BTVE : 1;   /*!< [0..0] Bit Timing Violation EnableNote: The bit must be modified
9081                                         *   only when the DALI0.STR1.BBF bit is 0.                                    */
9082             __IOM uint16_t BTVM : 1;   /*!< [1..1] Bit Timing Violation ModeNote: The bit must be modified
9083                                         *   only when the DALI0.STR1.BBF bit is 0.                                    */
9084             __IOM uint16_t SGA : 1;    /*!< [2..2] Save an Edge of Gray Area ModeNote: The bit must be modified
9085                                         *   only when the DALI0.STR1.BBF bit is 0.                                    */
9086             __IOM uint16_t TXWE : 1;   /*!< [3..3] DTX Width Modulation EnableNote: The bit must be modified
9087                                         *   only when the DALI0.STR1.BBF bit is 0.                                    */
9088             __IOM uint16_t CDE : 1;    /*!< [4..4] Collision Detect EnableNote: The bit must be modified
9089                                         *   only when the DALI0.STR1.BBF bit is 0.                                    */
9090             __IOM uint16_t CDM0 : 1;   /*!< [5..5] Collision Detect ModeNote: The bit must be modified only
9091                                         *   when the DALI0.STR1.BBF bit is 0.                                         */
9092             uint16_t : 10;
9093         } CNFR2_b;
9094     };
9095 
9096     union
9097     {
9098         __IOM uint16_t TXWR1;          /*!< (@ 0x00000016) DALI DTX Width Register 1                                  */
9099 
9100         struct
9101         {
9102             __IOM uint16_t TXLW : 7;   /*!< [6..0] DTX Low WidthDTX0 pin low level width                              */
9103             uint16_t            : 9;
9104         } TXWR1_b;
9105     };
9106     __IM uint16_t RESERVED[3];
9107 
9108     union
9109     {
9110         __IOM uint16_t TDR1H;          /*!< (@ 0x0000001E) DALI Transmit Data Register 1H                             */
9111 
9112         struct
9113         {
9114             __IOM uint16_t DTDR : 16;  /*!< [15..0] Upper 16-bit DALI transmit data                                   */
9115         } TDR1H_b;
9116     };
9117 
9118     union
9119     {
9120         __IOM uint16_t TDR1L;          /*!< (@ 0x00000020) DALI Transmit Data Register 1L                             */
9121 
9122         struct
9123         {
9124             __IOM uint16_t DTDR : 16;  /*!< [15..0] Lower 16-bit DALI transmit data                                   */
9125         } TDR1L_b;
9126     };
9127 
9128     union
9129     {
9130         __OM uint16_t TRSTR1;          /*!< (@ 0x00000022) DALI Transmit Control Register 1                           */
9131 
9132         struct
9133         {
9134             __OM uint16_t TRST : 1;    /*!< [0..0] Transmission Start Trigger                                         */
9135             uint16_t           : 15;
9136         } TRSTR1_b;
9137     };
9138     __IM uint16_t RESERVED1;
9139 
9140     union
9141     {
9142         __IOM uint16_t CTR1;           /*!< (@ 0x00000026) DALI Control Register 1                                    */
9143 
9144         struct
9145         {
9146             __IOM uint16_t TE   : 1;   /*!< [0..0] Transmit Enabling                                                  */
9147             __IOM uint16_t RE   : 1;   /*!< [1..1] Receive Enabling                                                   */
9148             uint16_t            : 6;
9149             __IOM uint16_t SDIE : 1;   /*!< [8..8] DALI_SDI Output Enabling                                           */
9150             __IOM uint16_t DEIE : 1;   /*!< [9..9] DALI_DEI Output Enabling                                           */
9151             __IOM uint16_t CLIE : 1;   /*!< [10..10] DALI_CLI Output Enabling                                         */
9152             __IOM uint16_t BPIE : 1;   /*!< [11..11] DALI_BPI Output Enabling                                         */
9153             __IOM uint16_t FEIE : 1;   /*!< [12..12] DALI_FEI Output Enabling                                         */
9154             uint16_t            : 3;
9155         } CTR1_b;
9156     };
9157 
9158     union
9159     {
9160         __IOM uint16_t TXDCTR1;        /*!< (@ 0x00000028) DALI DTX Control Register 1                                */
9161 
9162         struct
9163         {
9164             __IOM uint16_t TXAS : 1;   /*!< [0..0] DTX Assert LevelNote 1. The bit must be modified only
9165                                         *   when the DALI0.CTR1.TE bit is 0.                                          */
9166             __IOM uint16_t TXASE : 1;  /*!< [1..1] DTX Assert EnablingNote 1. The bit must be modified only
9167                                         *   when the DALI0.CTR1.TE bit is 0.                                          */
9168             uint16_t : 14;
9169         } TXDCTR1_b;
9170     };
9171     __IM uint16_t RESERVED2[2];
9172 
9173     union
9174     {
9175         __IM uint16_t RDR1H;           /*!< (@ 0x0000002E) DALI Reception Data Register 1H                            */
9176 
9177         struct
9178         {
9179             __IM uint16_t DRDR : 16;   /*!< [15..0] Upper 16-bit of DALI receive data                                 */
9180         } RDR1H_b;
9181     };
9182 
9183     union
9184     {
9185         __IM uint16_t RDR1L;           /*!< (@ 0x00000030) DALI Reception Data Register 1L                            */
9186 
9187         struct
9188         {
9189             __IM uint16_t DRDR : 16;   /*!< [15..0] Lower 16-bit of DALI receive data                                 */
9190         } RDR1L_b;
9191     };
9192 
9193     union
9194     {
9195         __IM uint16_t STR1;            /*!< (@ 0x00000032) DALI Status Register 1                                     */
9196 
9197         struct
9198         {
9199             __IM uint16_t MFEF  : 1;   /*!< [0..0] Manchester Flaming Error Flag                                      */
9200             __IM uint16_t OVF   : 1;   /*!< [1..1] Overrun Error Flag                                                 */
9201             __IM uint16_t BTVF  : 1;   /*!< [2..2] Bit Timing Violation Flag                                          */
9202             __IM uint16_t RDRF  : 1;   /*!< [3..3] Receive Data Register Full Flag                                    */
9203             __IM uint16_t TENDF : 1;   /*!< [4..4] Transmit End Flag                                                  */
9204             __IM uint16_t BBF   : 1;   /*!< [5..5] Bus BUSY Flag                                                      */
9205             __IM uint16_t BPDF  : 1;   /*!< [6..6] Bus Power Down Flag                                                */
9206             __IM uint16_t O32F  : 1;   /*!< [7..7] Over 32-Bit Data Reception Flag                                    */
9207             __IM uint16_t CDF   : 1;   /*!< [8..8] Collision Detect Flag                                              */
9208             __IM uint16_t DAF   : 1;   /*!< [9..9] Destroy Area Flag                                                  */
9209             __IM uint16_t RDBL  : 6;   /*!< [15..10] Receive Data Bit LengthThese bits store the bit length
9210                                         *   for data received successfully                                            */
9211         } STR1_b;
9212     };
9213     __IM uint16_t RESERVED3;
9214 
9215     union
9216     {
9217         __IM uint16_t COLR1;           /*!< (@ 0x00000036) DALI Collision Register 1                                  */
9218 
9219         struct
9220         {
9221             __IM uint16_t CFTF2  : 4;  /*!< [3..0] Collision Detect Timing Flag 2                                     */
9222             __IM uint16_t CDTF1  : 1;  /*!< [4..4] Collision Detect Timing Flag 1                                     */
9223             uint16_t             : 5;
9224             __IM uint16_t CLDAF  : 1;  /*!< [10..10] Collision Last Destroy Area Flag                                 */
9225             __IM uint16_t RXDMON : 1;  /*!< [11..11] DRX MonitorThis bit monitors the DRX0 pin value after
9226                                         *   the DRX0 pin is synchronized                                              */
9227             __IM uint16_t RXDCEG : 1;  /*!< [12..12] DRX Collision Edge                                               */
9228             __IM uint16_t TXDCV  : 1;  /*!< [13..13] DTX Collision Value                                              */
9229             uint16_t             : 2;
9230         } COLR1_b;
9231     };
9232     __IM uint16_t RESERVED4;
9233 
9234     union
9235     {
9236         __OM uint16_t FECR1;           /*!< (@ 0x0000003A) DALI Flag Error Clear Register 1                           */
9237 
9238         struct
9239         {
9240             __OM uint16_t MFEFC  : 1;  /*!< [0..0] Manchester Flaming Error Flag Clear                                */
9241             __OM uint16_t OVFC   : 1;  /*!< [1..1] Overrun Error Flag Clear                                           */
9242             __OM uint16_t BTVFC  : 1;  /*!< [2..2] Bit Timing Violation Flag Clear                                    */
9243             __OM uint16_t RDRFC  : 1;  /*!< [3..3] Receive Data Register Full Flag Clear                              */
9244             __OM uint16_t TENDFC : 1;  /*!< [4..4] Transmit End Flag Clear                                            */
9245             __OM uint16_t BBFC   : 1;  /*!< [5..5] Bus BUSY Flag ClearNote1: Do not clear DALI0.STR1.BBF
9246                                         *   bit when DALI0.CTR1.TE bit or DALI0.CTR1.RE bit is 1.                     */
9247             __OM uint16_t BPDFC : 1;   /*!< [6..6] Bus Power Down Flag Clear                                          */
9248             __OM uint16_t O32FC : 1;   /*!< [7..7] Over 32-Bit Data Reception Flag Clear                              */
9249             __OM uint16_t CDFC  : 1;   /*!< [8..8] Collision Detect Flag Clear                                        */
9250             __OM uint16_t DAFC  : 1;   /*!< [9..9] Destroy Area Flag Clear                                            */
9251             uint16_t            : 6;
9252         } FECR1_b;
9253     };
9254 
9255     union
9256     {
9257         __OM uint16_t SWRR1;           /*!< (@ 0x0000003C) DALI Software Reset Register 1                             */
9258 
9259         struct
9260         {
9261             __OM uint16_t SWR : 1;     /*!< [0..0] Software ResetWriting 1 to this bit causes a software
9262                                         *   reset.                                                                    */
9263             uint16_t : 15;
9264         } SWRR1_b;
9265     };
9266 } R_DALI0_Type;                        /*!< Size = 62 (0x3e)                                                          */
9267 
9268 /* =========================================================================================================================== */
9269 /* ================                                          R_DEBUG                                          ================ */
9270 /* =========================================================================================================================== */
9271 
9272 /**
9273  * @brief Debug Function (R_DEBUG)
9274  */
9275 
9276 typedef struct                         /*!< (@ 0x4001B000) R_DEBUG Structure                                          */
9277 {
9278     union
9279     {
9280         __IM uint32_t DBGSTR;          /*!< (@ 0x00000000) Debug Status Register                                      */
9281 
9282         struct
9283         {
9284             uint32_t                   : 28;
9285             __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request                                           */
9286             __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge                                       */
9287             uint32_t                   : 2;
9288         } DBGSTR_b;
9289     };
9290     __IM uint32_t RESERVED[3];
9291 
9292     union
9293     {
9294         __IOM uint32_t DBGSTOPCR;             /*!< (@ 0x00000010) Debug Stop Control Register                                */
9295 
9296         struct
9297         {
9298             __IOM uint32_t DBGSTOP_IWDT  : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt                                  */
9299             __IOM uint32_t DBGSTOP_WDT   : 1; /*!< [1..1] Mask bit for WDT reset/interrupt                                   */
9300             uint32_t                     : 14;
9301             __IOM uint32_t DBGSTOP_LVD0  : 1; /*!< [16..16] Mask bit for LVD reset/interupt                                  */
9302             __IOM uint32_t DBGSTOP_LVD1  : 1; /*!< [17..17] Mask bit for LVD reset/interupt                                  */
9303             __IOM uint32_t DBGSTOP_LVD2  : 1; /*!< [18..18] Mask bit for LVD reset/interupt                                  */
9304             uint32_t                     : 5;
9305             __IOM uint32_t DBGSTOP_RPER  : 1; /*!< [24..24] Mask bit for SRAM parity error                                   */
9306             __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error                                      */
9307             uint32_t                     : 5;
9308             __IOM uint32_t DBGSTOP_CPER  : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt             */
9309         } DBGSTOPCR_b;
9310     };
9311 } R_DEBUG_Type;                               /*!< Size = 20 (0x14)                                                          */
9312 
9313 /* =========================================================================================================================== */
9314 /* ================                                           R_DMA                                           ================ */
9315 /* =========================================================================================================================== */
9316 
9317 /**
9318  * @brief DMA Controller Common (R_DMA)
9319  */
9320 
9321 typedef struct                         /*!< (@ 0x40005200) R_DMA Structure                                            */
9322 {
9323     union
9324     {
9325         __IOM uint8_t DMAST;           /*!< (@ 0x00000000) DMAC Module Activation Register                            */
9326 
9327         struct
9328         {
9329             __IOM uint8_t DMST : 1;    /*!< [0..0] DMAC Operation Enable                                              */
9330             uint8_t            : 7;
9331         } DMAST_b;
9332     };
9333     __IM uint8_t  RESERVED;
9334     __IM uint16_t RESERVED1;
9335     __IM uint32_t RESERVED2[15];
9336 
9337     union
9338     {
9339         __IOM uint32_t DMECHR;          /*!< (@ 0x00000040) DMAC Error Channel Register                                */
9340 
9341         struct
9342         {
9343             __IM uint32_t DMECH    : 3; /*!< [2..0] DMAC Error channel                                                 */
9344             uint32_t               : 5;
9345             __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor                    */
9346             uint32_t               : 7;
9347             __IOM uint32_t DMESTA  : 1; /*!< [16..16] DMAC Error Status                                                */
9348             uint32_t               : 15;
9349         } DMECHR_b;
9350     };
9351 } R_DMA_Type;                           /*!< Size = 68 (0x44)                                                          */
9352 
9353 /* =========================================================================================================================== */
9354 /* ================                                          R_DMAC0                                          ================ */
9355 /* =========================================================================================================================== */
9356 
9357 /**
9358  * @brief DMA Controller (R_DMAC0)
9359  */
9360 
9361 typedef struct                         /*!< (@ 0x40005000) R_DMAC0 Structure                                          */
9362 {
9363     union
9364     {
9365         __IOM uint32_t DMSAR;          /*!< (@ 0x00000000) DMA Source Address Register                                */
9366 
9367         struct
9368         {
9369             __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address.                      */
9370         } DMSAR_b;
9371     };
9372 
9373     union
9374     {
9375         __IOM uint32_t DMDAR;          /*!< (@ 0x00000004) DMA Destination Address Register                           */
9376 
9377         struct
9378         {
9379             __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address.                 */
9380         } DMDAR_b;
9381     };
9382 
9383     union
9384     {
9385         __IOM uint32_t DMCRA;           /*!< (@ 0x00000008) DMA Transfer Count Register                                */
9386 
9387         struct
9388         {
9389             __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count                                      */
9390             __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count                                     */
9391             uint32_t              : 6;
9392         } DMCRA_b;
9393     };
9394 
9395     union
9396     {
9397         __IOM uint16_t DMCRB;          /*!< (@ 0x0000000C) DMA Block Transfer Count Register                          */
9398 
9399         struct
9400         {
9401             __IOM uint16_t DMCRB : 16; /*!< [15..0] Specifies the number of block transfer operations or
9402                                         *   repeat transfer operations.                                               */
9403         } DMCRB_b;
9404     };
9405     __IM uint16_t RESERVED;
9406 
9407     union
9408     {
9409         __IOM uint16_t DMTMD;          /*!< (@ 0x00000010) DMA Transfer Mode Register                                 */
9410 
9411         struct
9412         {
9413             __IOM uint16_t DCTG : 2;   /*!< [1..0] Transfer Request Source Select                                     */
9414             uint16_t            : 6;
9415             __IOM uint16_t SZ   : 2;   /*!< [9..8] Transfer Data Size Select                                          */
9416             __IOM uint16_t TKP  : 1;   /*!< [10..10] Transfer Keeping                                                 */
9417             uint16_t            : 1;
9418             __IOM uint16_t DTS  : 2;   /*!< [13..12] Repeat Area Select                                               */
9419             __IOM uint16_t MD   : 2;   /*!< [15..14] Transfer Mode Select                                             */
9420         } DMTMD_b;
9421     };
9422     __IM uint8_t RESERVED1;
9423 
9424     union
9425     {
9426         __IOM uint8_t DMINT;           /*!< (@ 0x00000013) DMA Interrupt Setting Register                             */
9427 
9428         struct
9429         {
9430             __IOM uint8_t DARIE : 1;   /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt
9431                                         *   Enable                                                                    */
9432             __IOM uint8_t SARIE : 1;   /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt
9433                                         *   Enable                                                                    */
9434             __IOM uint8_t RPTIE : 1;   /*!< [2..2] Repeat Size End Interrupt Enable                                   */
9435             __IOM uint8_t ESIE  : 1;   /*!< [3..3] Transfer Escape End Interrupt Enable                               */
9436             __IOM uint8_t DTIE  : 1;   /*!< [4..4] Transfer End Interrupt Enable                                      */
9437             uint8_t             : 3;
9438         } DMINT_b;
9439     };
9440 
9441     union
9442     {
9443         __IOM uint16_t DMAMD;          /*!< (@ 0x00000014) DMA Address Mode Register                                  */
9444 
9445         struct
9446         {
9447             __IOM uint16_t DARA : 5;   /*!< [4..0] Destination Address Extended Repeat Area Specifies the
9448                                         *   extended repeat area on the destination address. For details
9449                                         *   on the settings.                                                          */
9450             __IOM uint16_t DADR : 1;   /*!< [5..5] Destination Address Update Select After Reload                     */
9451             __IOM uint16_t DM   : 2;   /*!< [7..6] Destination Address Update Mode                                    */
9452             __IOM uint16_t SARA : 5;   /*!< [12..8] Source Address Extended Repeat Area Specifies the extended
9453                                         *   repeat area on the source address. For details on the settings.           */
9454             __IOM uint16_t SADR : 1;   /*!< [13..13] Source Address Update Select After Reload                        */
9455             __IOM uint16_t SM   : 2;   /*!< [15..14] Source Address Update Mode                                       */
9456         } DMAMD_b;
9457     };
9458     __IM uint16_t RESERVED2;
9459 
9460     union
9461     {
9462         __IOM uint32_t DMOFR;          /*!< (@ 0x00000018) DMA Offset Register                                        */
9463 
9464         struct
9465         {
9466             __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected
9467                                         *   as the address update mode for transfer source or destination.            */
9468         } DMOFR_b;
9469     };
9470 
9471     union
9472     {
9473         __IOM uint8_t DMCNT;           /*!< (@ 0x0000001C) DMA Transfer Enable Register                               */
9474 
9475         struct
9476         {
9477             __IOM uint8_t DTE : 1;     /*!< [0..0] DMA Transfer Enable                                                */
9478             uint8_t           : 7;
9479         } DMCNT_b;
9480     };
9481 
9482     union
9483     {
9484         __IOM uint8_t DMREQ;           /*!< (@ 0x0000001D) DMA Software Start Register                                */
9485 
9486         struct
9487         {
9488             __IOM uint8_t SWREQ : 1;   /*!< [0..0] DMA Software Start                                                 */
9489             uint8_t             : 3;
9490             __IOM uint8_t CLRS  : 1;   /*!< [4..4] DMA Software Start Bit Auto Clear Select                           */
9491             uint8_t             : 3;
9492         } DMREQ_b;
9493     };
9494 
9495     union
9496     {
9497         __IOM uint8_t DMSTS;            /*!< (@ 0x0000001E) DMA Status Register                                        */
9498 
9499         struct
9500         {
9501             __IOM uint8_t ESIF : 1;     /*!< [0..0] Transfer Escape End Interrupt Flag                                 */
9502             uint8_t            : 3;
9503             __IOM uint8_t DTIF : 1;     /*!< [4..4] Transfer End Interrupt Flag                                        */
9504             uint8_t            : 2;
9505             __IM uint8_t ACT   : 1;     /*!< [7..7] DMA Active Flag                                                    */
9506         } DMSTS_b;
9507     };
9508     __IM uint8_t   RESERVED3;
9509     __IOM uint32_t DMSRR;               /*!< (@ 0x00000020) DMA Source Reload Address Register                         */
9510     __IOM uint32_t DMDRR;               /*!< (@ 0x00000024) DMA Destination Reload Address Register                    */
9511 
9512     union
9513     {
9514         __IOM uint32_t DMSBS;           /*!< (@ 0x00000028) DMA Source Buffer Size Register                            */
9515 
9516         struct
9517         {
9518             __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
9519                                          *   mode                                                                      */
9520             __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
9521                                          *   mode                                                                      */
9522         } DMSBS_b;
9523     };
9524 
9525     union
9526     {
9527         __IOM uint32_t DMDBS;           /*!< (@ 0x0000002C) DMA Destination Buffer Size Register                       */
9528 
9529         struct
9530         {
9531             __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
9532                                          *   mode                                                                      */
9533             __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
9534                                          *   mode                                                                      */
9535         } DMDBS_b;
9536     };
9537 
9538     union
9539     {
9540         __IOM uint8_t DMBWR;           /*!< (@ 0x00000030) DMA Bufferable Write Enable Register                       */
9541 
9542         struct
9543         {
9544             __IOM uint8_t BWE : 1;     /*!< [0..0] Bufferable Write Enable                                            */
9545             uint8_t           : 7;
9546         } DMBWR_b;
9547     };
9548     __IM uint8_t  RESERVED4;
9549     __IM uint16_t RESERVED5;
9550 } R_DMAC0_Type;                        /*!< Size = 52 (0x34)                                                          */
9551 
9552 /* =========================================================================================================================== */
9553 /* ================                                           R_DOC                                           ================ */
9554 /* =========================================================================================================================== */
9555 
9556 /**
9557  * @brief Data Operation Circuit (R_DOC)
9558  */
9559 
9560 typedef struct                         /*!< (@ 0x40054100) R_DOC Structure                                            */
9561 {
9562     union
9563     {
9564         __IOM uint8_t DOCR;            /*!< (@ 0x00000000) DOC Control Register                                       */
9565 
9566         struct
9567         {
9568             __IOM uint8_t OMS     : 2; /*!< [1..0] Operating Mode Select                                              */
9569             __IOM uint8_t DCSEL   : 1; /*!< [2..2] Detection Condition Select                                         */
9570             uint8_t               : 2;
9571             __IM uint8_t  DOPCF   : 1; /*!< [5..5] Data Operation Circuit Flag                                        */
9572             __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear                                                        */
9573             uint8_t               : 1;
9574         } DOCR_b;
9575     };
9576     __IM uint8_t RESERVED;
9577 
9578     union
9579     {
9580         __IOM uint16_t DODIR;          /*!< (@ 0x00000002) DOC Data Input Register                                    */
9581 
9582         struct
9583         {
9584             __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for
9585                                         *   use in the operations are stored.                                         */
9586         } DODIR_b;
9587     };
9588 
9589     union
9590     {
9591         __IOM uint16_t DODSR;          /*!< (@ 0x00000004) DOC Data Setting Register                                  */
9592 
9593         struct
9594         {
9595             __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference
9596                                         *   in data comparison mode. This register also stores the
9597                                         *   results of operations in data addition and data subtraction
9598                                         *   modes.                                                                    */
9599         } DODSR_b;
9600     };
9601 } R_DOC_Type;                          /*!< Size = 6 (0x6)                                                            */
9602 
9603 /* =========================================================================================================================== */
9604 /* ================                                           R_DRW                                           ================ */
9605 /* =========================================================================================================================== */
9606 
9607 /**
9608  * @brief 2D Drawing Engine (R_DRW)
9609  */
9610 
9611 typedef struct                         /*!< (@ 0x400E4000) R_DRW Structure                                            */
9612 {
9613     union
9614     {
9615         union
9616         {
9617             __OM uint32_t CONTROL;               /*!< (@ 0x00000000) Geometry Control Register                                  */
9618 
9619             struct
9620             {
9621                 __OM uint32_t LIM1ENABLE    : 1; /*!< [0..0] Enable limiter 1                                                   */
9622                 __OM uint32_t LIM2ENABLE    : 1; /*!< [1..1] Enable limiter 2                                                   */
9623                 __OM uint32_t LIM3ENABLE    : 1; /*!< [2..2] Enable limiter 3                                                   */
9624                 __OM uint32_t LIM4ENABLE    : 1; /*!< [3..3] Enable limiter 4                                                   */
9625                 __OM uint32_t LIM5ENABLE    : 1; /*!< [4..4] Enable limiter 5                                                   */
9626                 __OM uint32_t LIM6ENABLE    : 1; /*!< [5..5] Enable limiter 6                                                   */
9627                 __OM uint32_t QUAD1ENABLE   : 1; /*!< [6..6] Enable quadratic coupling of limiters 1 and 2                      */
9628                 __OM uint32_t QUAD2ENABLE   : 1; /*!< [7..7] Enable quadratic coupling of limiters 3 and 4                      */
9629                 __OM uint32_t QUAD3ENABLE   : 1; /*!< [8..8] Enable quadratic coupling of limiters 5 and 6                      */
9630                 __OM uint32_t LIM1THRESHOLD : 1; /*!< [9..9] Enable limiter 1 threshold mode                                    */
9631                 __OM uint32_t LIM2THRESHOLD : 1; /*!< [10..10] Enable limiter 2 threshold mode                                  */
9632                 __OM uint32_t LIM3THRESHOLD : 1; /*!< [11..11] Enable limiter 3 threshold mode                                  */
9633                 __OM uint32_t LIM4THRESHOLD : 1; /*!< [12..12] Enable limiter 4 threshold mode                                  */
9634                 __OM uint32_t LIM5THRESHOLD : 1; /*!< [13..13] Enable limiter 5 threshold mode                                  */
9635                 __OM uint32_t LIM6THRESHOLD : 1; /*!< [14..14] Enable limiter 6 threshold mode                                  */
9636                 __OM uint32_t BAND1ENABLE   : 1; /*!< [15..15] Enable band postprocess for limiter 1 (see L1BAND)               */
9637                 __OM uint32_t BAND2ENABLE   : 1; /*!< [16..16] Enable band postprocess for limiter 1 (see L1BAND)               */
9638                 __OM uint32_t UNION12       : 1; /*!< [17..17] Combine limter 1 & 2 as union (output is called A)               */
9639                 __OM uint32_t UNION34       : 1; /*!< [18..18] Combine limter 3 & 4 as union (output is called B)               */
9640                 __OM uint32_t UNION56       : 1; /*!< [19..19] Combine limter 5 & 6 as union (output is called D)               */
9641                 __OM uint32_t UNIONAB       : 1; /*!< [20..20] Combine outputs A & B as union (output is called C)              */
9642                 __OM uint32_t UNIONCD       : 1; /*!< [21..21] Combine outputs C & D as union (output is final)                 */
9643                 __OM uint32_t SPANABORT     : 1; /*!< [22..22] Shape is horizontally convex, only a single span per
9644                                                   *   scanline                                                                  */
9645                 __OM uint32_t SPANSTORE : 1;     /*!< [23..23] Nextline span start is always equal or left to current-line
9646                                                   *   span start                                                                */
9647                 uint32_t : 8;
9648             } CONTROL_b;
9649         };
9650 
9651         union
9652         {
9653             __IM uint32_t STATUS;               /*!< (@ 0x00000000) Status Control Register                                    */
9654 
9655             struct
9656             {
9657                 __IM uint32_t BUSYENUM     : 1; /*!< [0..0] Enumeration unit status                                            */
9658                 __IM uint32_t BUSYWRITE    : 1; /*!< [1..1] Framebuffer writeback status                                       */
9659                 __IM uint32_t CACHEDIRTY   : 1; /*!< [2..2] Framebuffer cache status                                           */
9660                 __IM uint32_t DLISTACTIVE  : 1; /*!< [3..3] Display list reader status                                         */
9661                 __IM uint32_t ENUMIRQ      : 1; /*!< [4..4] enumeration finished interrupt triggered                           */
9662                 __IM uint32_t DLISTIRQ     : 1; /*!< [5..5] display list finished interrupt triggered                          */
9663                 __IM uint32_t BUSIRQ       : 1; /*!< [6..6] bus error interrupt triggered                                      */
9664                 uint32_t                   : 1;
9665                 __IM uint32_t BUSERRMFB    : 1; /*!< [8..8] framebuffer bus error interrupt triggered                          */
9666                 __IM uint32_t BUSERRMTXMRL : 1; /*!< [9..9] texture bus error interrupt triggered                              */
9667                 __IM uint32_t BUSERRMDL    : 1; /*!< [10..10] display list bus error interrupt triggered                       */
9668                 uint32_t                   : 21;
9669             } STATUS_b;
9670         };
9671     };
9672 
9673     union
9674     {
9675         union
9676         {
9677             __OM uint32_t CONTROL2;                /*!< (@ 0x00000004) Surface Control Register                                   */
9678 
9679             struct
9680             {
9681                 __OM uint32_t PATTERNENABLE : 1;   /*!< [0..0] Pixel source is a pattern color (blend of COLOR1 and
9682                                                     *   COLOR2 depending on PATTERN and pattern index)                            */
9683                 __OM uint32_t TEXTUREENABLE : 1;   /*!< [1..1] Pixel source is read from texture and used as an alpha
9684                                                     *   to blend between COLOR1 and COLOR2                                        */
9685                 __OM uint32_t PATTERNSOURCEL5 : 1; /*!< [2..2] Limiter 5 is used as pattern index instead of the default
9686                                                     *   U limiter.Limiter 5 can be combined with limiter 6 to form
9687                                                     *   a quadratic limiter which can be used to make quadratic
9688                                                     *   pattern functions to draw radial patterns.                                */
9689                 __OM uint32_t USEACB       : 1;    /*!< [3..3] Alpha blend mode                                                   */
9690                 __OM uint32_t READFORMAT32 : 2;    /*!< [5..4] Bit 4 and 3 of the texture buffer format.See READFORMAT
9691                                                     *   above for description                                                     */
9692                 __OM uint32_t BSFA : 1;            /*!< [6..6] Blend source factor for alpha channel in alpha channel
9693                                                     *   blending mode (USEACB = 1)                                                */
9694                 __OM uint32_t BDFA : 1;            /*!< [7..7] Blend destinetion factor for alpha channel in alpha channel
9695                                                     *   blending mode (USEACB = 1)                                                */
9696                 __OM uint32_t WRITEFORMAT2 : 1;    /*!< [8..8] Bit 3 of framebuffer pixel formatSee WRITEFORMAT above
9697                                                     *   description.                                                              */
9698                 __OM uint32_t BSF : 1;             /*!< [9..9] Blend source factorsrc factor is alpha (factor is 1 per
9699                                                     *   default)                                                                  */
9700                 __OM uint32_t BDF : 1;             /*!< [10..10] Blend destination factordst factor is alpha (factor
9701                                                     *   is 1 per default)                                                         */
9702                 __OM uint32_t BSI : 1;             /*!< [11..11] Blend source factor is invertedsrc factor will be inverted
9703                                                     *   (meaning 1-a or 1-1 depending on BSF)                                     */
9704                 __OM uint32_t BDI : 1;             /*!< [12..12] Blend destination factor is inverteddst factor will
9705                                                     *   be inverted (meaning 1-a or 1-1 depending on BDF)                         */
9706                 __OM uint32_t BC2           : 1;   /*!< [13..13] Blend color 2 instead of framebuffer pixel                       */
9707                 __OM uint32_t TEXTURECLAMPX : 1;   /*!< [14..14] Calculating U limiter outside use textureThe bit describes
9708                                                     *   what happens if the U limiter (x direction in texture space)
9709                                                     *   calculates a U value outside of the used texture                          */
9710                 __OM uint32_t TEXTURECLAMPY : 1;   /*!< [15..15] Calculating V limiter outside use textureThe bit describes
9711                                                     *   what happens if the V limiter (y direction in texture space)
9712                                                     *   calculates a V value outside of the used texture                          */
9713                 __OM uint32_t TEXTUREFILTERX : 1;  /*!< [16..16] Linear filtering on texture U axis                               */
9714                 __OM uint32_t TEXTUREFILTERY : 1;  /*!< [17..17] Linear filtering on texture V axis                               */
9715                 __OM uint32_t READFORMAT10   : 2;  /*!< [19..18] Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000:
9716                                                     *   8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011:
9717                                                     *   16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44)
9718                                                     *   4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8),
9719                                                     *   8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4),
9720                                                     *   4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2),
9721                                                     *   2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1),
9722                                                     *   1 bit indexed color/luminance                                             */
9723                 __OM uint32_t WRITEFORMAT10 : 2;   /*!< [21..20] Pixel format of the framebuffer                                  */
9724                 __OM uint32_t WRITEALPHA    : 2;   /*!< [23..22] Writeback alpha source for framebufferSet the 'alpha
9725                                                     *   source' for the framebuffer(USEACB = 0)Blend alpha in color
9726                                                     *   2 instead of framebuffer alpha((USEACB = 1))In not alpha
9727                                                     *   channel blending mode (USEACB = 0):Set the 'alpha source'
9728                                                     *   for the framebuffer.In alpha channel blending mode (USEACB
9729                                                     *   = 1):Blend alpha in color 2 instead of framebuffer alpha00B:
9730                                                     *   BC2A = 1: use alpha from framebuffer as destination (DST_A)else:
9731                                                     *   BC2A = 0: use alpha in color 2 as destination (DST_A)                     */
9732                 __OM uint32_t RLEENABLE    : 1;    /*!< [24..24] RLE enable                                                       */
9733                 __OM uint32_t CLUTENABLE   : 1;    /*!< [25..25] CLUT enable                                                      */
9734                 __OM uint32_t COLKEYENABLE : 1;    /*!< [26..26] color keying enable                                              */
9735                 __OM uint32_t CLUTFORMAT   : 1;    /*!< [27..27] Format of the CLUT                                               */
9736                 __OM uint32_t BSIA         : 1;    /*!< [28..28] Blend source factor inverted in alpha channel (USEACB
9737                                                     *   = 1)                                                                      */
9738                 __OM uint32_t BDIA : 1;            /*!< [29..29] Blend destination factor inverted in alpha channel
9739                                                     *   (USEACB = 1)                                                              */
9740                 __OM uint32_t RLEPIXELWIDTH : 2;   /*!< [31..30] Texel width for RLE unit                                         */
9741             } CONTROL2_b;
9742         };
9743 
9744         union
9745         {
9746             __IM uint32_t HWREVISION;          /*!< (@ 0x00000004) Hardware Version and Feature Set ID Register               */
9747 
9748             struct
9749             {
9750                 __IM uint32_t REV        : 12; /*!< [11..0] Revision number                                                   */
9751                 uint32_t                 : 5;
9752                 __IM uint32_t DLR        : 1;  /*!< [17..17] Display list reader feature                                      */
9753                 __IM uint32_t FBCACHE    : 1;  /*!< [18..18] Framebuffer cache feature                                        */
9754                 __IM uint32_t TXCACHE    : 1;  /*!< [19..19] Texture cache feature                                            */
9755                 __IM uint32_t PERFCOUNT  : 1;  /*!< [20..20] Two performance counter feature                                  */
9756                 __IM uint32_t TEXCLU     : 1;  /*!< [21..21] Texture CLUT with 16 or 256 entries feature                      */
9757                 uint32_t                 : 1;
9758                 __IM uint32_t RLEUNIT    : 1;  /*!< [23..23] RLE unit feature                                                 */
9759                 __IM uint32_t TEXCLUT256 : 1;  /*!< [24..24] Texture CLUT feature                                             */
9760                 __IM uint32_t COLORKEY   : 1;  /*!< [25..25] Colorkey feature                                                 */
9761                 uint32_t                 : 1;
9762                 __IM uint32_t ACBLEND    : 1;  /*!< [27..27] Alpha channel blending feature                                   */
9763                 uint32_t                 : 4;
9764             } HWREVISION_b;
9765         };
9766     };
9767     __IM uint32_t RESERVED[2];
9768 
9769     union
9770     {
9771         __OM uint32_t L1START;         /*!< (@ 0x00000010) Limiter 1 Start Value Register                             */
9772 
9773         struct
9774         {
9775             __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
9776         } L1START_b;
9777     };
9778 
9779     union
9780     {
9781         __OM uint32_t L2START;         /*!< (@ 0x00000014) Limiter 2 Start Value Register                             */
9782 
9783         struct
9784         {
9785             __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
9786         } L2START_b;
9787     };
9788 
9789     union
9790     {
9791         __OM uint32_t L3START;         /*!< (@ 0x00000018) Limiter 3 Start Value Register                             */
9792 
9793         struct
9794         {
9795             __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
9796         } L3START_b;
9797     };
9798 
9799     union
9800     {
9801         __OM uint32_t L4START;         /*!< (@ 0x0000001C) Limiter 4 Start Value Register                             */
9802 
9803         struct
9804         {
9805             __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
9806         } L4START_b;
9807     };
9808 
9809     union
9810     {
9811         __OM uint32_t L5START;         /*!< (@ 0x00000020) Limiter 5 Start Value Register                             */
9812 
9813         struct
9814         {
9815             __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
9816         } L5START_b;
9817     };
9818 
9819     union
9820     {
9821         __OM uint32_t L6START;         /*!< (@ 0x00000024) Limiter 6 Start Value Register                             */
9822 
9823         struct
9824         {
9825             __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
9826         } L6START_b;
9827     };
9828 
9829     union
9830     {
9831         __OM uint32_t L1XADD;          /*!< (@ 0x00000028) Limiter 1 X-Axis Increment Register                        */
9832 
9833         struct
9834         {
9835             __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
9836         } L1XADD_b;
9837     };
9838 
9839     union
9840     {
9841         __OM uint32_t L2XADD;          /*!< (@ 0x0000002C) Limiter 2 X-Axis Increment Register                        */
9842 
9843         struct
9844         {
9845             __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
9846         } L2XADD_b;
9847     };
9848 
9849     union
9850     {
9851         __OM uint32_t L3XADD;          /*!< (@ 0x00000030) Limiter 3 X-Axis Increment Register                        */
9852 
9853         struct
9854         {
9855             __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
9856         } L3XADD_b;
9857     };
9858 
9859     union
9860     {
9861         __OM uint32_t L4XADD;          /*!< (@ 0x00000034) Limiter 4 X-Axis Increment Register                        */
9862 
9863         struct
9864         {
9865             __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
9866         } L4XADD_b;
9867     };
9868 
9869     union
9870     {
9871         __OM uint32_t L5XADD;          /*!< (@ 0x00000038) Limiter 5 X-Axis Increment Register                        */
9872 
9873         struct
9874         {
9875             __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
9876         } L5XADD_b;
9877     };
9878 
9879     union
9880     {
9881         __OM uint32_t L6XADD;          /*!< (@ 0x0000003C) Limiter 6 X-Axis Increment Register                        */
9882 
9883         struct
9884         {
9885             __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
9886         } L6XADD_b;
9887     };
9888 
9889     union
9890     {
9891         __OM uint32_t L1YADD;          /*!< (@ 0x00000040) Limiter 1 Y-Axis Increment Register                        */
9892 
9893         struct
9894         {
9895             __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
9896         } L1YADD_b;
9897     };
9898 
9899     union
9900     {
9901         __OM uint32_t L2YADD;          /*!< (@ 0x00000044) Limiter 2 Y-Axis Increment Register                        */
9902 
9903         struct
9904         {
9905             __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
9906         } L2YADD_b;
9907     };
9908 
9909     union
9910     {
9911         __OM uint32_t L3YADD;          /*!< (@ 0x00000048) Limiter 3 Y-Axis Increment Register                        */
9912 
9913         struct
9914         {
9915             __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
9916         } L3YADD_b;
9917     };
9918 
9919     union
9920     {
9921         __OM uint32_t L4YADD;          /*!< (@ 0x0000004C) Limiter 4 Y-Axis Increment Register                        */
9922 
9923         struct
9924         {
9925             __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
9926         } L4YADD_b;
9927     };
9928 
9929     union
9930     {
9931         __OM uint32_t L5YADD;          /*!< (@ 0x00000050) Limiter 5 Y-Axis Increment Register                        */
9932 
9933         struct
9934         {
9935             __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
9936         } L5YADD_b;
9937     };
9938 
9939     union
9940     {
9941         __OM uint32_t L6YADD;          /*!< (@ 0x00000054) Limiter 6 Y-Axis Increment Register                        */
9942 
9943         struct
9944         {
9945             __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
9946         } L6YADD_b;
9947     };
9948 
9949     union
9950     {
9951         __OM uint32_t L1BAND;          /*!< (@ 0x00000058) Limiter 1 Band Width Parameter Register                    */
9952 
9953         struct
9954         {
9955             __OM uint32_t LBAND : 32;  /*!< [31..0] Limiter m band width parameter                                    */
9956         } L1BAND_b;
9957     };
9958 
9959     union
9960     {
9961         __OM uint32_t L2BAND;          /*!< (@ 0x0000005C) Limiter 2 Band Width Parameter Register                    */
9962 
9963         struct
9964         {
9965             __OM uint32_t LBAND : 32;  /*!< [31..0] Limiter m band width parameter                                    */
9966         } L2BAND_b;
9967     };
9968     __IM uint32_t RESERVED1;
9969 
9970     union
9971     {
9972         __OM uint32_t COLOR1;          /*!< (@ 0x00000064) Base Color Register                                        */
9973 
9974         struct
9975         {
9976             __OM uint32_t COLOR1B : 8; /*!< [7..0] Blue channel of color 1                                            */
9977             __OM uint32_t COLOR1G : 8; /*!< [15..8] Green channel of color 1                                          */
9978             __OM uint32_t COLOR1R : 8; /*!< [23..16] Red channel of color 1                                           */
9979             __OM uint32_t COLOR1A : 8; /*!< [31..24] Alpha channel of color 1(0x00: transparent. . . 0xFF:
9980                                         *   opaque)                                                                   */
9981         } COLOR1_b;
9982     };
9983 
9984     union
9985     {
9986         __OM uint32_t COLOR2;          /*!< (@ 0x00000068) Secondary Color Register                                   */
9987 
9988         struct
9989         {
9990             __OM uint32_t COLOR2B : 8; /*!< [7..0] Blue channel of color 2                                            */
9991             __OM uint32_t COLOR2G : 8; /*!< [15..8] Green channel of color 2                                          */
9992             __OM uint32_t COLOR2R : 8; /*!< [23..16] Red channel of color 2                                           */
9993             __OM uint32_t COLOR2A : 8; /*!< [31..24] Alpha channel of color 2(0x00: transparent. . . 0xFF:
9994                                         *   opaque)                                                                   */
9995         } COLOR2_b;
9996     };
9997     __IM uint32_t RESERVED2[2];
9998 
9999     union
10000     {
10001         __OM uint32_t PATTERN;         /*!< (@ 0x00000074) Pattern Register                                           */
10002 
10003         struct
10004         {
10005             __OM uint32_t PATTERN : 8; /*!< [7..0] Bitmap of the pattern                                              */
10006             uint32_t              : 24;
10007         } PATTERN_b;
10008     };
10009 
10010     union
10011     {
10012         __OM uint32_t SIZE;            /*!< (@ 0x00000078) Bounding Box Dimension Register                            */
10013 
10014         struct
10015         {
10016             __OM uint32_t SIZEX : 16;  /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to
10017                                         *   1024                                                                      */
10018             __OM uint32_t SIZEY : 16;  /*!< [31..16] Height of the bounding box in pixelsvalid range: 0
10019                                         *   to 1024                                                                   */
10020         } SIZE_b;
10021     };
10022 
10023     union
10024     {
10025         __OM uint32_t PITCH;           /*!< (@ 0x0000007C) Framebuffer Pitch And Spanstore Delay Register             */
10026 
10027         struct
10028         {
10029             __OM uint32_t PITCH : 16;  /*!< [15..0] pitch of the framebuffer. A negative width can be used
10030                                         *   to render bottom-up instead of top-down                                   */
10031             __OM uint32_t SSD : 16;    /*!< [31..16] Spanstore delay                                                  */
10032         } PITCH_b;
10033     };
10034 
10035     union
10036     {
10037         __OM uint32_t ORIGIN;          /*!< (@ 0x00000080) Framebuffer Base Address Register                          */
10038 
10039         struct
10040         {
10041             __OM uint32_t ORIGIN : 32; /*!< [31..0] Address of the first pixel in framebuffer                         */
10042         } ORIGIN_b;
10043     };
10044     __IM uint32_t RESERVED3[3];
10045 
10046     union
10047     {
10048         __OM uint32_t LUSTART;          /*!< (@ 0x00000090) U Limiter Start Value Register                             */
10049 
10050         struct
10051         {
10052             __OM uint32_t LUSTART : 32; /*!< [31..0] U limiter start value                                             */
10053         } LUSTART_b;
10054     };
10055 
10056     union
10057     {
10058         __OM uint32_t LUXADD;          /*!< (@ 0x00000094) U Limiter X-Axis Increment Register                        */
10059 
10060         struct
10061         {
10062             __OM uint32_t LUXADD : 32; /*!< [31..0] U limiter x-axis increment                                        */
10063         } LUXADD_b;
10064     };
10065 
10066     union
10067     {
10068         __OM uint32_t LUYADD;          /*!< (@ 0x00000098) U Limiter Y-Axis Increment Register                        */
10069 
10070         struct
10071         {
10072             __OM uint32_t LUYADD : 32; /*!< [31..0] U limiter y-axis increment                                        */
10073         } LUYADD_b;
10074     };
10075 
10076     union
10077     {
10078         __OM uint32_t LVSTARTI;          /*!< (@ 0x0000009C) V Limiter Start Value Integer Part Register                */
10079 
10080         struct
10081         {
10082             __OM uint32_t LVSTARTI : 32; /*!< [31..0] V limiter start value integer part                                */
10083         } LVSTARTI_b;
10084     };
10085 
10086     union
10087     {
10088         __OM uint32_t LVSTARTF;          /*!< (@ 0x000000A0) V Limiter Start Value Fractional Part Register             */
10089 
10090         struct
10091         {
10092             __OM uint32_t LVSTARTF : 16; /*!< [15..0] V limiter start value fractional part                             */
10093             uint32_t               : 16;
10094         } LVSTARTF_b;
10095     };
10096 
10097     union
10098     {
10099         __OM uint32_t LVXADDI;          /*!< (@ 0x000000A4) V Limiter X-Axis Increment Integer Part Register           */
10100 
10101         struct
10102         {
10103             __OM uint32_t LVXADDI : 32; /*!< [31..0] V limiter x-axis increment integer part                           */
10104         } LVXADDI_b;
10105     };
10106 
10107     union
10108     {
10109         __OM uint32_t LVYADDI;          /*!< (@ 0x000000A8) V Limiter Y-Axis Increment Integer Part Register           */
10110 
10111         struct
10112         {
10113             __OM uint32_t LVYADDI : 32; /*!< [31..0] V limiter y-axis increment integer part                           */
10114         } LVYADDI_b;
10115     };
10116 
10117     union
10118     {
10119         __OM uint32_t LVYXADDF;         /*!< (@ 0x000000AC) V Limiter Increment Fractional Parts Register              */
10120 
10121         struct
10122         {
10123             __OM uint32_t LVXADDF : 16; /*!< [15..0] V xlimiter increment fractional part                              */
10124             __OM uint32_t LVYADDF : 16; /*!< [31..16] V y limiter increment fractional part                            */
10125         } LVYXADDF_b;
10126     };
10127     __IM uint32_t RESERVED4;
10128 
10129     union
10130     {
10131         __OM uint32_t TEXPITCH;          /*!< (@ 0x000000B4) Texels Per Texture Line Register                           */
10132 
10133         struct
10134         {
10135             __OM uint32_t TEXPITCH : 32; /*!< [31..0] Texels per texture linevalid range: 0 to 2048                     */
10136         } TEXPITCH_b;
10137     };
10138 
10139     union
10140     {
10141         __OM uint32_t TEXMASK;           /*!< (@ 0x000000B8) Texture Size or Texture Address Mask Register              */
10142 
10143         struct
10144         {
10145             __OM uint32_t TEXUMASK : 11; /*!< [10..0] U maskSet TEXUMASK[10:0] = texture_width -1In texture
10146                                           *   wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width
10147                                           *   must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX
10148                                           *   = 1):all widths up to 2048 are allowed.                                   */
10149             __OM uint32_t TEXVMASK : 21; /*!< [31..11] V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height
10150                                           *   - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY =
10151                                           *   0): texture_height must be a power of 2In texture clamping
10152                                           *   mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024
10153                                           *   are allowed.                                                              */
10154         } TEXMASK_b;
10155     };
10156 
10157     union
10158     {
10159         __OM uint32_t TEXORIGIN;          /*!< (@ 0x000000BC) Texture Base Address Register                              */
10160 
10161         struct
10162         {
10163             __OM uint32_t TEXORIGIN : 32; /*!< [31..0] Texture base address                                              */
10164         } TEXORIGIN_b;
10165     };
10166 
10167     union
10168     {
10169         __OM uint32_t IRQCTL;              /*!< (@ 0x000000C0) Interrupt Control Register                                 */
10170 
10171         struct
10172         {
10173             __OM uint32_t ENUMIRQEN   : 1; /*!< [0..0] ENUMIRQ interrupt mask enable                                      */
10174             __OM uint32_t DLISTIRQEN  : 1; /*!< [1..1] DLISTIRQ interrupt mask enable                                     */
10175             __OM uint32_t ENUMIRQCLR  : 1; /*!< [2..2] Clear enumeration interrupt ENUMIRQ                                */
10176             __OM uint32_t DLISTIRQCLR : 1; /*!< [3..3] Clear display list interrupt DLISTIRQ                              */
10177             __OM uint32_t BUSIRQEN    : 1; /*!< [4..4] BUSIRQ interrupt mask enable                                       */
10178             __OM uint32_t BUSIRQCLR   : 1; /*!< [5..5] Clear bus error interrupt BUSIRQ                                   */
10179             uint32_t                  : 26;
10180         } IRQCTL_b;
10181     };
10182 
10183     union
10184     {
10185         __OM uint32_t CACHECTL;          /*!< (@ 0x000000C4) Cache Control Register                                     */
10186 
10187         struct
10188         {
10189             __OM uint32_t CENABLEFX : 1; /*!< [0..0] Framebuffer cache enable                                           */
10190             __OM uint32_t CFLUSHFX  : 1; /*!< [1..1] Flush framebuffer cache                                            */
10191             __OM uint32_t CENABLETX : 1; /*!< [2..2] Texture cache enable                                               */
10192             __OM uint32_t CFLUSHTX  : 1; /*!< [3..3] Flush texture cache                                                */
10193             uint32_t                : 28;
10194         } CACHECTL_b;
10195     };
10196 
10197     union
10198     {
10199         __OM uint32_t DLISTSTART;          /*!< (@ 0x000000C8) Display List Start Address Register                        */
10200 
10201         struct
10202         {
10203             __OM uint32_t DLISTSTART : 32; /*!< [31..0] Display list start address                                        */
10204         } DLISTSTART_b;
10205     };
10206 
10207     union
10208     {
10209         __IOM uint32_t PERFCOUNT1;         /*!< (@ 0x000000CC) Performance Counter 1                                      */
10210 
10211         struct
10212         {
10213             __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT
10214                                             *   = 0000 0000H.                                                             */
10215         } PERFCOUNT1_b;
10216     };
10217 
10218     union
10219     {
10220         __IOM uint32_t PERFCOUNT2;         /*!< (@ 0x000000D0) Performance Counter 2                                      */
10221 
10222         struct
10223         {
10224             __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT
10225                                             *   = 0000 0000H.                                                             */
10226         } PERFCOUNT2_b;
10227     };
10228 
10229     union
10230     {
10231         __OM uint32_t PERFTRIGGER;           /*!< (@ 0x000000D4) Performance Counters Control Register                      */
10232 
10233         struct
10234         {
10235             __OM uint32_t PERFTRIGGER1 : 16; /*!< [15..0] Selects the internal event that will increment PERFCOUNT1
10236                                               *   register.                                                                 */
10237             __OM uint32_t PERFTRIGGER2 : 16; /*!< [31..16] Selects the internal event that will increment PERFCOUNT2
10238                                               *   register                                                                  */
10239         } PERFTRIGGER_b;
10240     };
10241     __IM uint32_t RESERVED5;
10242 
10243     union
10244     {
10245         __OM uint32_t TEXCLADDR;       /*!< (@ 0x000000DC) CLUT Start Address Register                                */
10246 
10247         struct
10248         {
10249             __OM uint32_t CLADDR : 8;  /*!< [7..0] Texture CLUT start address for indexed texture format              */
10250             uint32_t             : 24;
10251         } TEXCLADDR_b;
10252     };
10253 
10254     union
10255     {
10256         __OM uint32_t TEXCLDATA;       /*!< (@ 0x000000E0) CLUT Data Register                                         */
10257 
10258         struct
10259         {
10260             __OM uint32_t CLDATA : 32; /*!< [31..0] Texture CLUT data for Indexed texture format                      */
10261         } TEXCLDATA_b;
10262     };
10263 
10264     union
10265     {
10266         __OM uint32_t TEXCLOFFSET;      /*!< (@ 0x000000E4) CLUT Offset Register                                       */
10267 
10268         struct
10269         {
10270             __OM uint32_t CLOFFSET : 8; /*!< [7..0] Texture CLUT offset for Indexed texture format. CLOFFSET[7:0]
10271                                          *   is or'ed with the original index                                          */
10272             uint32_t : 24;
10273         } TEXCLOFFSET_b;
10274     };
10275 
10276     union
10277     {
10278         __OM uint32_t COLKEY;          /*!< (@ 0x000000E8) Color Key Register                                         */
10279 
10280         struct
10281         {
10282             __OM uint32_t COLKEYB : 8; /*!< [7..0] Blue channel of color key                                          */
10283             __OM uint32_t COLKEYG : 8; /*!< [15..8] Green channel of color key                                        */
10284             __OM uint32_t COLKEYR : 8; /*!< [23..16] Red channel of color key                                         */
10285             uint32_t              : 8;
10286         } COLKEY_b;
10287     };
10288 } R_DRW_Type;                          /*!< Size = 236 (0xec)                                                         */
10289 
10290 /* =========================================================================================================================== */
10291 /* ================                                           R_DTC                                           ================ */
10292 /* =========================================================================================================================== */
10293 
10294 /**
10295  * @brief Data Transfer Controller (R_DTC)
10296  */
10297 
10298 typedef struct                         /*!< (@ 0x40005400) R_DTC Structure                                            */
10299 {
10300     union
10301     {
10302         __IOM uint8_t DTCCR;           /*!< (@ 0x00000000) DTC Control Register                                       */
10303 
10304         struct
10305         {
10306             uint8_t           : 4;
10307             __IOM uint8_t RRS : 1;     /*!< [4..4] DTC Transfer Information Read Skip Enable.                         */
10308             uint8_t           : 3;
10309         } DTCCR_b;
10310     };
10311     __IM uint8_t  RESERVED;
10312     __IM uint16_t RESERVED1;
10313 
10314     union
10315     {
10316         __IOM uint32_t DTCVBR;          /*!< (@ 0x00000004) DTC Vector Base Register                                   */
10317 
10318         struct
10319         {
10320             __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set
10321                                          *   in the lower-order 10 bits. These bits are fixed to 0.                    */
10322         } DTCVBR_b;
10323     };
10324     __IM uint32_t RESERVED2;
10325 
10326     union
10327     {
10328         __IOM uint8_t DTCST;           /*!< (@ 0x0000000C) DTC Module Start Register                                  */
10329 
10330         struct
10331         {
10332             __IOM uint8_t DTCST : 1;   /*!< [0..0] DTC Module Start                                                   */
10333             uint8_t             : 7;
10334         } DTCST_b;
10335     };
10336     __IM uint8_t RESERVED3;
10337 
10338     union
10339     {
10340         __IM uint16_t DTCSTS;          /*!< (@ 0x0000000E) DTC Status Register                                        */
10341 
10342         struct
10343         {
10344             __IM uint16_t VECN : 8;    /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate
10345                                         *   the vector number for the activating source when DTC transfer
10346                                         *   is in progress.The value is only valid if DTC transfer
10347                                         *   is in progress (the value of the ACT flag is 1)                           */
10348             uint16_t          : 7;
10349             __IM uint16_t ACT : 1;     /*!< [15..15] DTC Active Flag                                                  */
10350         } DTCSTS_b;
10351     };
10352 
10353     union
10354     {
10355         __IOM uint8_t DTCCR_SEC;       /*!< (@ 0x00000010) DTC Control Register for secure Region                     */
10356 
10357         struct
10358         {
10359             uint8_t            : 4;
10360             __IOM uint8_t RRSS : 1;    /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure               */
10361             uint8_t            : 3;
10362         } DTCCR_SEC_b;
10363     };
10364     __IM uint8_t   RESERVED4;
10365     __IM uint16_t  RESERVED5;
10366     __IOM uint32_t DTCVBR_SEC;         /*!< (@ 0x00000014) DTC Vector Base Register for secure Region                 */
10367     __IM uint32_t  RESERVED6[2];
10368 
10369     union
10370     {
10371         __IOM uint32_t DTEVR;          /*!< (@ 0x00000020) DTC Error Vector Register                                  */
10372 
10373         struct
10374         {
10375             __IM uint32_t DTEV    : 8; /*!< [7..0] DTC Error Vector Number                                            */
10376             __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor                                 */
10377             uint32_t              : 7;
10378             __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag                                            */
10379             uint32_t              : 15;
10380         } DTEVR_b;
10381     };
10382 } R_DTC_Type;                          /*!< Size = 36 (0x24)                                                          */
10383 
10384 /* =========================================================================================================================== */
10385 /* ================                                           R_ELC                                           ================ */
10386 /* =========================================================================================================================== */
10387 
10388 /**
10389  * @brief Event Link Controller (R_ELC)
10390  */
10391 
10392  #ifndef BSP_OVERRIDE_REG_R_ELC_TYPE
10393 
10394 typedef struct                         /*!< (@ 0x40041000) R_ELC Structure                                            */
10395 {
10396     union
10397     {
10398         __IOM uint8_t ELCR;            /*!< (@ 0x00000000) Event Link Controller Register                             */
10399 
10400         struct
10401         {
10402             uint8_t             : 7;
10403             __IOM uint8_t ELCON : 1;   /*!< [7..7] All Event Link Enable                                              */
10404         } ELCR_b;
10405     };
10406     __IM uint8_t            RESERVED;
10407     __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register              */
10408     __IM uint16_t           RESERVED1[5];
10409     __IOM R_ELC_ELSR_Type   ELSR[23];  /*!< (@ 0x00000010) Event Link Setting Register [0..22]                        */
10410     __IM uint16_t           RESERVED2[4];
10411 
10412     union
10413     {
10414         __IOM uint16_t ELCSARA;         /*!< (@ 0x00000074) Event Link Controller Security Attribution Register
10415                                          *                  A                                                          */
10416 
10417         struct
10418         {
10419             __IOM uint16_t ELCR    : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution                 */
10420             __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security
10421                                          *   Attribution                                                               */
10422             __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security
10423                                          *   Attribution                                                               */
10424             uint16_t : 13;
10425         } ELCSARA_b;
10426     };
10427     __IM uint16_t RESERVED3;
10428 
10429     union
10430     {
10431         __IOM uint16_t ELCSARB;        /*!< (@ 0x00000078) Event Link Controller Security Attribution Register
10432                                         *                  B                                                          */
10433 
10434         struct
10435         {
10436             __IOM uint16_t ELSR0  : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution                  */
10437             __IOM uint16_t ELSR1  : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution                  */
10438             __IOM uint16_t ELSR2  : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution                  */
10439             __IOM uint16_t ELSR3  : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution                  */
10440             __IOM uint16_t ELSR4  : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution                  */
10441             __IOM uint16_t ELSR5  : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution                  */
10442             __IOM uint16_t ELSR6  : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution                  */
10443             __IOM uint16_t ELSR7  : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution                  */
10444             __IOM uint16_t ELSR8  : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution                  */
10445             __IOM uint16_t ELSR9  : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution                  */
10446             __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution               */
10447             __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution               */
10448             __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution               */
10449             __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution               */
10450             __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution               */
10451             __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution               */
10452         } ELCSARB_b;
10453     };
10454     __IM uint16_t RESERVED4;
10455 
10456     union
10457     {
10458         __IOM uint16_t ELCSARC;        /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register
10459                                         *                  C                                                          */
10460 
10461         struct
10462         {
10463             __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution                 */
10464             __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution                 */
10465             __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution                 */
10466             uint16_t              : 13;
10467         } ELCSARC_b;
10468     };
10469 } R_ELC_Type;                          /*!< Size = 126 (0x7e)                                                         */
10470 
10471  #endif
10472 
10473 /* =========================================================================================================================== */
10474 /* ================                                         R_ETHERC0                                         ================ */
10475 /* =========================================================================================================================== */
10476 
10477 /**
10478  * @brief Ethernet MAC Controller (R_ETHERC0)
10479  */
10480 
10481 typedef struct                         /*!< (@ 0x40064100) R_ETHERC0 Structure                                        */
10482 {
10483     union
10484     {
10485         __IOM uint32_t ECMR;           /*!< (@ 0x00000000) ETHERC Mode Register                                       */
10486 
10487         struct
10488         {
10489             __IOM uint32_t PRM   : 1;  /*!< [0..0] Promiscuous Mode                                                   */
10490             __IOM uint32_t DM    : 1;  /*!< [1..1] Duplex Mode                                                        */
10491             __IOM uint32_t RTM   : 1;  /*!< [2..2] Bit Rate                                                           */
10492             __IOM uint32_t ILB   : 1;  /*!< [3..3] Internal Loopback Mode                                             */
10493             uint32_t             : 1;
10494             __IOM uint32_t TE    : 1;  /*!< [5..5] Transmission Enable                                                */
10495             __IOM uint32_t RE    : 1;  /*!< [6..6] Reception Enable                                                   */
10496             uint32_t             : 2;
10497             __IOM uint32_t MPDE  : 1;  /*!< [9..9] Magic Packet Detection Enable                                      */
10498             uint32_t             : 2;
10499             __IOM uint32_t PRCEF : 1;  /*!< [12..12] CRC Error Frame Receive Mode                                     */
10500             uint32_t             : 3;
10501             __IOM uint32_t TXF   : 1;  /*!< [16..16] Transmit Flow Control Operating Mode                             */
10502             __IOM uint32_t RXF   : 1;  /*!< [17..17] Receive Flow Control Operating Mode                              */
10503             __IOM uint32_t PFR   : 1;  /*!< [18..18] PAUSE Frame Receive Mode                                         */
10504             __IOM uint32_t ZPF   : 1;  /*!< [19..19] 0 Time PAUSE Frame Enable                                        */
10505             __IOM uint32_t TPC   : 1;  /*!< [20..20] PAUSE Frame Transmit                                             */
10506             uint32_t             : 11;
10507         } ECMR_b;
10508     };
10509     __IM uint32_t RESERVED;
10510 
10511     union
10512     {
10513         __IOM uint32_t RFLR;           /*!< (@ 0x00000008) Receive Frame Maximum Length Register                      */
10514 
10515         struct
10516         {
10517             __IOM uint32_t RFL : 12;   /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the
10518                                         *   maximum frame length. The minimum value that can be set
10519                                         *   is 1,518 bytes, and the maximum value that can be set is
10520                                         *   2,048 bytes. Values that are less than 1,518 bytes are
10521                                         *   regarded as 1,518 bytes, and values larger than 2,048 bytes
10522                                         *   are regarded as 2,048 bytes.                                              */
10523             uint32_t : 20;
10524         } RFLR_b;
10525     };
10526     __IM uint32_t RESERVED1;
10527 
10528     union
10529     {
10530         __IOM uint32_t ECSR;           /*!< (@ 0x00000010) ETHERC Status Register                                     */
10531 
10532         struct
10533         {
10534             __IOM uint32_t ICD   : 1;  /*!< [0..0] False Carrier Detect Flag                                          */
10535             __IOM uint32_t MPD   : 1;  /*!< [1..1] Magic Packet Detect Flag                                           */
10536             __IOM uint32_t LCHNG : 1;  /*!< [2..2] LCHNG Link Signal Change Flag                                      */
10537             uint32_t             : 1;
10538             __IOM uint32_t PSRTO : 1;  /*!< [4..4] PAUSE Frame Retransmit Over Flag                                   */
10539             __IOM uint32_t BFR   : 1;  /*!< [5..5] Continuous Broadcast Frame Reception Flag                          */
10540             uint32_t             : 26;
10541         } ECSR_b;
10542     };
10543     __IM uint32_t RESERVED2;
10544 
10545     union
10546     {
10547         __IOM uint32_t ECSIPR;          /*!< (@ 0x00000018) ETHERC Interrupt Enable Register                           */
10548 
10549         struct
10550         {
10551             __IOM uint32_t ICDIP   : 1; /*!< [0..0] False Carrier Detect Interrupt Enable                              */
10552             __IOM uint32_t MPDIP   : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable                               */
10553             __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable                                */
10554             uint32_t               : 1;
10555             __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable                       */
10556             __IOM uint32_t BFSIPR  : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable              */
10557             uint32_t               : 26;
10558         } ECSIPR_b;
10559     };
10560     __IM uint32_t RESERVED3;
10561 
10562     union
10563     {
10564         __IOM uint32_t PIR;            /*!< (@ 0x00000020) PHY Interface Register                                     */
10565 
10566         struct
10567         {
10568             __IOM uint32_t MDC : 1;    /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output
10569                                         *   from the ETn_MDC pin to supply the management data clock
10570                                         *   to the MII or RMII.                                                       */
10571             __IOM uint32_t MMD : 1;    /*!< [1..1] MII/RMII Management Mode                                           */
10572             __IOM uint32_t MDO : 1;    /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output
10573                                         *   from the ETn_MDIO pin when the MMD bit is 1 (write). The
10574                                         *   value is not output when the MMD bit is 0 (read).                         */
10575             __IM uint32_t MDI : 1;     /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level
10576                                         *   of the ETn_MDIO pin. The write value should be 0.                         */
10577             uint32_t : 28;
10578         } PIR_b;
10579     };
10580     __IM uint32_t RESERVED4;
10581 
10582     union
10583     {
10584         __IM uint32_t PSR;             /*!< (@ 0x00000028) PHY Status Register                                        */
10585 
10586         struct
10587         {
10588             __IM uint32_t LMON : 1;    /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read
10589                                         *   by connecting the link signal output from the PHY-LSI to
10590                                         *   the ETn_LINKSTA pin. For details on the polarity, refer
10591                                         *   to the specifications of the connected PHY-LSI.                           */
10592             uint32_t : 31;
10593         } PSR_b;
10594     };
10595     __IM uint32_t RESERVED5[5];
10596 
10597     union
10598     {
10599         __IOM uint32_t RDMLR;          /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit
10600                                         *                  Setting Register                                           */
10601 
10602         struct
10603         {
10604             __IOM uint32_t RMD : 20;   /*!< [19..0] Random Number Generation Counter                                  */
10605             uint32_t           : 12;
10606         } RDMLR_b;
10607     };
10608     __IM uint32_t RESERVED6[3];
10609 
10610     union
10611     {
10612         __IOM uint32_t IPGR;           /*!< (@ 0x00000050) IPG Register                                               */
10613 
10614         struct
10615         {
10616             __IOM uint32_t IPG : 5;    /*!< [4..0] Interpacket Gap Range:"16bit time(0x00)"-"140bit time(0x1F)"       */
10617             uint32_t           : 27;
10618         } IPGR_b;
10619     };
10620 
10621     union
10622     {
10623         __IOM uint32_t APR;            /*!< (@ 0x00000054) Automatic PAUSE Frame Register                             */
10624 
10625         struct
10626         {
10627             __IOM uint32_t AP : 16;    /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value
10628                                         *   of the pause_time parameter for a PAUSE frame that is automatically
10629                                         *   transmitted. Transmission is not performed until the set
10630                                         *   value multiplied by 512 bit time has elapsed.                             */
10631             uint32_t : 16;
10632         } APR_b;
10633     };
10634 
10635     union
10636     {
10637         __OM uint32_t MPR;             /*!< (@ 0x00000058) Manual PAUSE Frame Register                                */
10638 
10639         struct
10640         {
10641             __OM uint32_t MP : 16;     /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of
10642                                         *   the pause_time parameter for a PAUSE frame that is manually
10643                                         *   transmitted. Transmission is not performed until the set
10644                                         *   value multiplied by 512 bit time has elapsed. The read
10645                                         *   value is undefined.                                                       */
10646             uint32_t : 16;
10647         } MPR_b;
10648     };
10649     __IM uint32_t RESERVED7;
10650 
10651     union
10652     {
10653         __IM uint32_t RFCF;            /*!< (@ 0x00000060) Received PAUSE Frame Counter                               */
10654 
10655         struct
10656         {
10657             __IM uint32_t RPAUSE : 8;  /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames          */
10658             uint32_t             : 24;
10659         } RFCF_b;
10660     };
10661 
10662     union
10663     {
10664         __IOM uint32_t TPAUSER;         /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register              */
10665 
10666         struct
10667         {
10668             __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting                          */
10669             uint32_t              : 16;
10670         } TPAUSER_b;
10671     };
10672     __IM uint32_t TPAUSECR;             /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter                             */
10673 
10674     union
10675     {
10676         __IOM uint32_t BCFRR;           /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register             */
10677 
10678         struct
10679         {
10680             __IOM uint32_t BCF : 16;    /*!< [15..0] Broadcast Frame Continuous Receive Count Setting                  */
10681             uint32_t           : 16;
10682         } BCFRR_b;
10683     };
10684     __IM uint32_t RESERVED8[20];
10685 
10686     union
10687     {
10688         __IOM uint32_t MAHR;           /*!< (@ 0x000000C0) MAC Address Upper Bit Register                             */
10689 
10690         struct
10691         {
10692             __IOM uint32_t MAHR : 32;  /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets
10693                                         *   the upper 32 bits (b47 to b16) of the 48-bit MAC address.                 */
10694         } MAHR_b;
10695     };
10696     __IM uint32_t RESERVED9;
10697 
10698     union
10699     {
10700         __IOM uint32_t MALR;           /*!< (@ 0x000000C8) MAC Address Lower Bit Register                             */
10701 
10702         struct
10703         {
10704             __IOM uint32_t MALR : 16;  /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets
10705                                         *   the lower 16 bits of the 48-bit MAC address.                              */
10706             uint32_t : 16;
10707         } MALR_b;
10708     };
10709     __IM uint32_t RESERVED10;
10710 
10711     union
10712     {
10713         __IOM uint32_t TROCR;          /*!< (@ 0x000000D0) Transmit Retry Over Counter Register                       */
10714 
10715         struct
10716         {
10717             __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register
10718                                         *   is a counter indicating the number of frames that fail
10719                                         *   to be retransmitted.                                                      */
10720         } TROCR_b;
10721     };
10722     __IOM uint32_t CDCR;               /*!< (@ 0x000000D4) Late Collision Detect Counter Register                     */
10723 
10724     union
10725     {
10726         __IOM uint32_t LCCR;           /*!< (@ 0x000000D8) Lost Carrier Counter Register                              */
10727 
10728         struct
10729         {
10730             __IOM uint32_t LCCR : 32;  /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a
10731                                         *   counter indicating the number of times a loss of carrier
10732                                         *   is detected during frame transmission.                                    */
10733         } LCCR_b;
10734     };
10735 
10736     union
10737     {
10738         __IOM uint32_t CNDCR;          /*!< (@ 0x000000DC) Carrier Not Detect Counter Register                        */
10739 
10740         struct
10741         {
10742             __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register
10743                                         *   is a counter indicating the number of times a carrier is
10744                                         *   not detected during preamble transmission.                                */
10745         } CNDCR_b;
10746     };
10747     __IM uint32_t RESERVED11;
10748 
10749     union
10750     {
10751         __IOM uint32_t CEFCR;          /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register                   */
10752 
10753         struct
10754         {
10755             __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register
10756                                         *   is a counter indicating the number of received frames where
10757                                         *   a CRC error has been detected.                                            */
10758         } CEFCR_b;
10759     };
10760 
10761     union
10762     {
10763         __IOM uint32_t FRECR;          /*!< (@ 0x000000E8) Frame Receive Error Counter Register                       */
10764 
10765         struct
10766         {
10767             __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register
10768                                         *   is a counter indicating the number of times a frame receive
10769                                         *   error has occurred.                                                       */
10770         } FRECR_b;
10771     };
10772 
10773     union
10774     {
10775         __IOM uint32_t TSFRCR;          /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register                   */
10776 
10777         struct
10778         {
10779             __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register
10780                                          *   is a counter indicating the number of times a short frame
10781                                          *   that is shorter than 64 bytes has been received.                          */
10782         } TSFRCR_b;
10783     };
10784 
10785     union
10786     {
10787         __IOM uint32_t TLFRCR;          /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register                    */
10788 
10789         struct
10790         {
10791             __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register
10792                                          *   is a counter indicating the number of times a long frame
10793                                          *   that is longer than the RFLR register value has been received.            */
10794         } TLFRCR_b;
10795     };
10796 
10797     union
10798     {
10799         __IOM uint32_t RFCR;           /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register            */
10800 
10801         struct
10802         {
10803             __IOM uint32_t RFCR : 32;  /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR
10804                                         *   register is a counter indicating the number of times a
10805                                         *   frame has been received with the alignment error (frame
10806                                         *   is not an integral number of octets).                                     */
10807         } RFCR_b;
10808     };
10809 
10810     union
10811     {
10812         __IOM uint32_t MAFCR;          /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register           */
10813 
10814         struct
10815         {
10816             __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe
10817                                         *   MAFCR register is a counter indicating the number of times
10818                                         *   a frame where the multicast address is set has been received.             */
10819         } MAFCR_b;
10820     };
10821 } R_ETHERC0_Type;                      /*!< Size = 252 (0xfc)                                                         */
10822 
10823 /* =========================================================================================================================== */
10824 /* ================                                      R_ETHERC_EDMAC                                       ================ */
10825 /* =========================================================================================================================== */
10826 
10827 /**
10828  * @brief Ethernet DMA Controller (R_ETHERC_EDMAC)
10829  */
10830 
10831 typedef struct                         /*!< (@ 0x40064000) R_ETHERC_EDMAC Structure                                   */
10832 {
10833     union
10834     {
10835         __IOM uint32_t EDMR;           /*!< (@ 0x00000000) EDMAC Mode Register                                        */
10836 
10837         struct
10838         {
10839             __OM uint32_t SWR : 1;     /*!< [0..0] Software Reset                                                     */
10840             uint32_t          : 3;
10841             __IOM uint32_t DL : 2;     /*!< [5..4] Transmit/Receive DescriptorLength                                  */
10842             __IOM uint32_t DE : 1;     /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting
10843                                         *   applies to data for the transmit/receive buffer. It does
10844                                         *   not apply to transmit/receive descriptors and registers.                  */
10845             uint32_t : 25;
10846         } EDMR_b;
10847     };
10848     __IM uint32_t RESERVED;
10849 
10850     union
10851     {
10852         __IOM uint32_t EDTRR;          /*!< (@ 0x00000008) EDMAC Transmit Request Register                            */
10853 
10854         struct
10855         {
10856             __OM uint32_t TR : 1;      /*!< [0..0] Transmit Request                                                   */
10857             uint32_t         : 31;
10858         } EDTRR_b;
10859     };
10860     __IM uint32_t RESERVED1;
10861 
10862     union
10863     {
10864         __IOM uint32_t EDRRR;          /*!< (@ 0x00000010) EDMAC Receive Request Register                             */
10865 
10866         struct
10867         {
10868             __IOM uint32_t RR : 1;     /*!< [0..0] Receive Request                                                    */
10869             uint32_t          : 31;
10870         } EDRRR_b;
10871     };
10872     __IM uint32_t RESERVED2;
10873 
10874     union
10875     {
10876         __IOM uint32_t TDLAR;          /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register            */
10877 
10878         struct
10879         {
10880             __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is
10881                                         *   set. Set the start address according to the descriptor
10882                                         *   length selected by the EDMR.DL[1:0] bits.16-byte boundary:
10883                                         *   Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte
10884                                         *   boundary: Lower 6 bits = 000000b                                          */
10885         } TDLAR_b;
10886     };
10887     __IM uint32_t RESERVED3;
10888 
10889     union
10890     {
10891         __IOM uint32_t RDLAR;          /*!< (@ 0x00000020) Receive Descriptor List Start Address Register             */
10892 
10893         struct
10894         {
10895             __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is
10896                                         *   set. Set the start address according to the descriptor
10897                                         *   length selected by the EDMR.DL[1:0] bits.16-byte boundary:
10898                                         *   Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte
10899                                         *   boundary: Lower 6 bits = 000000b                                          */
10900         } RDLAR_b;
10901     };
10902     __IM uint32_t RESERVED4;
10903 
10904     union
10905     {
10906         __IOM uint32_t EESR;           /*!< (@ 0x00000028) ETHERC/EDMAC Status Register                               */
10907 
10908         struct
10909         {
10910             __IOM uint32_t CERF : 1;   /*!< [0..0] CRC Error Flag                                                     */
10911             __IOM uint32_t PRE  : 1;   /*!< [1..1] PHY-LSI Receive Error Flag                                         */
10912             __IOM uint32_t RTSF : 1;   /*!< [2..2] Frame-Too-Short Error Flag                                         */
10913             __IOM uint32_t RTLF : 1;   /*!< [3..3] Frame-Too-Long Error Flag                                          */
10914             __IOM uint32_t RRF  : 1;   /*!< [4..4] Alignment Error Flag                                               */
10915             uint32_t            : 2;
10916             __IOM uint32_t RMAF : 1;   /*!< [7..7] Multicast Address Frame Receive Flag                               */
10917             __IOM uint32_t TRO  : 1;   /*!< [8..8] Transmit Retry Over Flag                                           */
10918             __IOM uint32_t CD   : 1;   /*!< [9..9] Late Collision Detect Flag                                         */
10919             __IOM uint32_t DLC  : 1;   /*!< [10..10] Loss of Carrier Detect Flag                                      */
10920             __IOM uint32_t CND  : 1;   /*!< [11..11] Carrier Not Detect Flag                                          */
10921             uint32_t            : 4;
10922             __IOM uint32_t RFOF : 1;   /*!< [16..16] Receive FIFO Overflow Flag                                       */
10923             __IOM uint32_t RDE  : 1;   /*!< [17..17] Receive Descriptor Empty Flag                                    */
10924             __IOM uint32_t FR   : 1;   /*!< [18..18] Frame Receive Flag                                               */
10925             __IOM uint32_t TFUF : 1;   /*!< [19..19] Transmit FIFO Underflow Flag                                     */
10926             __IOM uint32_t TDE  : 1;   /*!< [20..20] Transmit Descriptor Empty Flag                                   */
10927             __IOM uint32_t TC   : 1;   /*!< [21..21] Frame Transfer Complete Flag                                     */
10928             __IM uint32_t  ECI  : 1;   /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source
10929                                         *   in the ETHERCn.ECSR register is cleared, the ECI flag is
10930                                         *   also cleared.                                                             */
10931             __IOM uint32_t ADE   : 1;  /*!< [23..23] Address Error Flag                                               */
10932             __IOM uint32_t RFCOF : 1;  /*!< [24..24] Receive Frame Counter Overflow Flag                              */
10933             __IOM uint32_t RABT  : 1;  /*!< [25..25] Receive Abort Detect Flag                                        */
10934             __IOM uint32_t TABT  : 1;  /*!< [26..26] Transmit Abort Detect Flag                                       */
10935             uint32_t             : 3;
10936             __IOM uint32_t TWB   : 1;  /*!< [30..30] Write-Back Complete Flag                                         */
10937             uint32_t             : 1;
10938         } EESR_b;
10939     };
10940     __IM uint32_t RESERVED5;
10941 
10942     union
10943     {
10944         __IOM uint32_t EESIPR;          /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register              */
10945 
10946         struct
10947         {
10948             __IOM uint32_t CERFIP  : 1; /*!< [0..0] CRC Error Interrupt Request Enable                                 */
10949             __IOM uint32_t PREIP   : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable                     */
10950             __IOM uint32_t RTSFIP  : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable                     */
10951             __IOM uint32_t RTLFIP  : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable                      */
10952             __IOM uint32_t RRFIP   : 1; /*!< [4..4] Alignment Error Interrupt Request Enable                           */
10953             uint32_t               : 2;
10954             __IOM uint32_t RMAFIP  : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable           */
10955             __IOM uint32_t TROIP   : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable                       */
10956             __IOM uint32_t CDIP    : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable                     */
10957             __IOM uint32_t DLCIP   : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable                  */
10958             __IOM uint32_t CNDIP   : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable                      */
10959             uint32_t               : 4;
10960             __IOM uint32_t RFOFIP  : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable                   */
10961             __IOM uint32_t RDEIP   : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable                */
10962             __IOM uint32_t FRIP    : 1; /*!< [18..18] Frame Receive Interrupt Request Enable                           */
10963             __IOM uint32_t TFUFIP  : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable                 */
10964             __IOM uint32_t TDEIP   : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable               */
10965             __IOM uint32_t TCIP    : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable                 */
10966             __IOM uint32_t ECIIP   : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable           */
10967             __IOM uint32_t ADEIP   : 1; /*!< [23..23] Address Error Interrupt Request Enable                           */
10968             __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable          */
10969             __IOM uint32_t RABTIP  : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable                    */
10970             __IOM uint32_t TABTIP  : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable                   */
10971             uint32_t               : 3;
10972             __IOM uint32_t TWBIP   : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable                     */
10973             uint32_t               : 1;
10974         } EESIPR_b;
10975     };
10976     __IM uint32_t RESERVED6;
10977 
10978     union
10979     {
10980         __IOM uint32_t TRSCER;         /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable
10981                                         *                  Register                                                   */
10982 
10983         struct
10984         {
10985             uint32_t              : 4;
10986             __IOM uint32_t RRFCE  : 1; /*!< [4..4] RRF Flag Copy Enable                                               */
10987             uint32_t              : 2;
10988             __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable                                              */
10989             uint32_t              : 24;
10990         } TRSCER_b;
10991     };
10992     __IM uint32_t RESERVED7;
10993 
10994     union
10995     {
10996         __IOM uint32_t RMFCR;          /*!< (@ 0x00000040) Missed-Frame Counter Register                              */
10997 
10998         struct
10999         {
11000             __IOM uint32_t MFC : 16;   /*!< [15..0] Missed-Frame CounterThese bits indicate the number of
11001                                         *   frames that are discarded and not transferred to the receive
11002                                         *   buffer during reception.                                                  */
11003             uint32_t : 16;
11004         } RMFCR_b;
11005     };
11006     __IM uint32_t RESERVED8;
11007 
11008     union
11009     {
11010         __IOM uint32_t TFTR;           /*!< (@ 0x00000048) Transmit FIFO Threshold Register                           */
11011 
11012         struct
11013         {
11014             __IOM uint32_t TFT : 11;   /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is
11015                                         *   the set value multiplied by 4. Example: 00Dh: 52 bytes
11016                                         *   040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes                         */
11017             uint32_t : 21;
11018         } TFTR_b;
11019     };
11020     __IM uint32_t RESERVED9;
11021 
11022     union
11023     {
11024         __IOM uint32_t FDR;            /*!< (@ 0x00000050) Transmit FIFO Threshold Register                           */
11025 
11026         struct
11027         {
11028             __IOM uint32_t RFD : 5;    /*!< [4..0] Transmit FIFO Depth                                                */
11029             uint32_t           : 3;
11030             __IOM uint32_t TFD : 5;    /*!< [12..8] Receive FIFO Depth                                                */
11031             uint32_t           : 19;
11032         } FDR_b;
11033     };
11034     __IM uint32_t RESERVED10;
11035 
11036     union
11037     {
11038         __IOM uint32_t RMCR;           /*!< (@ 0x00000058) Receive Method Control Register                            */
11039 
11040         struct
11041         {
11042             __IOM uint32_t RNR : 1;    /*!< [0..0] Receive Request Reset                                              */
11043             uint32_t           : 31;
11044         } RMCR_b;
11045     };
11046     __IM uint32_t RESERVED11[2];
11047 
11048     union
11049     {
11050         __IOM uint32_t TFUCR;          /*!< (@ 0x00000064) Transmit FIFO Underflow Counter                            */
11051 
11052         struct
11053         {
11054             __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how
11055                                         *   many times the transmit FIFO has underflowed. The counter
11056                                         *   stops when the counter value reaches FFFFh.                               */
11057             uint32_t : 16;
11058         } TFUCR_b;
11059     };
11060 
11061     union
11062     {
11063         __IOM uint32_t RFOCR;          /*!< (@ 0x00000068) Receive FIFO Overflow Counter                              */
11064 
11065         struct
11066         {
11067             __IOM uint32_t OVER : 16;  /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many
11068                                         *   times the receive FIFO has overflowed. The counter stops
11069                                         *   when the counter value reaches FFFFh.                                     */
11070             uint32_t : 16;
11071         } RFOCR_b;
11072     };
11073 
11074     union
11075     {
11076         __IOM uint32_t IOSR;           /*!< (@ 0x0000006C) Independent Output Signal Setting Register                 */
11077 
11078         struct
11079         {
11080             __IOM uint32_t ELB : 1;    /*!< [0..0] External Loopback Mode                                             */
11081             uint32_t           : 31;
11082         } IOSR_b;
11083     };
11084 
11085     union
11086     {
11087         __IOM uint32_t FCFTR;          /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register         */
11088 
11089         struct
11090         {
11091             __IOM uint32_t RFDO : 3;   /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32
11092                                         *   bytes of data is stored in the receive FIFO.)                             */
11093             uint32_t            : 13;
11094             __IOM uint32_t RFFO : 3;   /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2)
11095                                         *   receive frames have been stored in the receive FIFO.)                     */
11096             uint32_t : 13;
11097         } FCFTR_b;
11098     };
11099     __IM uint32_t RESERVED12;
11100 
11101     union
11102     {
11103         __IOM uint32_t RPADIR;         /*!< (@ 0x00000078) Receive Data Padding Insert Register                       */
11104 
11105         struct
11106         {
11107             __IOM uint32_t PADR : 6;   /*!< [5..0] Padding Slot                                                       */
11108             uint32_t            : 10;
11109             __IOM uint32_t PADS : 2;   /*!< [17..16] Padding Size                                                     */
11110             uint32_t            : 14;
11111         } RPADIR_b;
11112     };
11113 
11114     union
11115     {
11116         __IOM uint32_t TRIMD;          /*!< (@ 0x0000007C) Transmit Interrupt Setting Register                        */
11117 
11118         struct
11119         {
11120             __IOM uint32_t TIS : 1;    /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in
11121                                         *   the mode selected by the TIM bit to notify an interrupt.                  */
11122             uint32_t           : 3;
11123             __IOM uint32_t TIM : 1;    /*!< [4..4] Transmit Interrupt Mode                                            */
11124             uint32_t           : 27;
11125         } TRIMD_b;
11126     };
11127     __IM uint32_t RESERVED13[18];
11128 
11129     union
11130     {
11131         __IOM uint32_t RBWAR;          /*!< (@ 0x000000C8) Receive Buffer Write Address Register                      */
11132 
11133         struct
11134         {
11135             __IM uint32_t RBWAR : 32;  /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register
11136                                         *   indicates the last address that the EDMAC has written data
11137                                         *   to when writing to the receive buffer.Refer to the address
11138                                         *   indicated by the RBWAR register to recognize which address
11139                                         *   in the receive buffer the EDMAC is writing data to. Note
11140                                         *   that the address that the EDMAC is outputting to the receive
11141                                         *   buffer may not match the read value of the RBWAR register
11142                                         *   during data reception.                                                    */
11143         } RBWAR_b;
11144     };
11145 
11146     union
11147     {
11148         __IOM uint32_t RDFAR;          /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register                  */
11149 
11150         struct
11151         {
11152             __IM uint32_t RDFAR : 32;  /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register
11153                                         *   indicates the start address of the last fetched receive
11154                                         *   descriptor when the EDMAC fetches descriptor information
11155                                         *   from the receive descriptor.Refer to the address indicated
11156                                         *   by the RDFAR register to recognize which receive descriptor
11157                                         *   information the EDMAC is using for the current processing.
11158                                         *   Note that the address of the receive descriptor that the
11159                                         *   EDMAC fetches may not match the read value of the RDFAR
11160                                         *   register during data reception.                                           */
11161         } RDFAR_b;
11162     };
11163     __IM uint32_t RESERVED14;
11164 
11165     union
11166     {
11167         __IOM uint32_t TBRAR;          /*!< (@ 0x000000D4) Transmit Buffer Read Address Register                      */
11168 
11169         struct
11170         {
11171             __IM uint32_t TBRAR : 32;  /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register
11172                                         *   indicates the last address that the EDMAC has read data
11173                                         *   from when reading data from the transmit buffer.Refer to
11174                                         *   the address indicated by the TBRAR register to recognize
11175                                         *   which address in the transmit buffer the EDMAC is reading
11176                                         *   from. Note that the address that the EDMAC is outputting
11177                                         *   to the transmit buffer may not match the read value of
11178                                         *   the TBRAR register.                                                       */
11179         } TBRAR_b;
11180     };
11181 
11182     union
11183     {
11184         __IM uint32_t TDFAR;           /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register                 */
11185 
11186         struct
11187         {
11188             __IM uint32_t TDFAR : 32;  /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR
11189                                         *   register indicates the start address of the last fetched
11190                                         *   transmit descriptor when the EDMAC fetches descriptor information
11191                                         *   from the transmit descriptor.Refer to the address indicated
11192                                         *   by the TDFAR register to recognize which transmit descriptor
11193                                         *   information the EDMAC is using for the current processing.
11194                                         *   Note that the address of the transmit descriptor that the
11195                                         *   EDMAC fetches may not match the read value of the TDFAR
11196                                         *   register.                                                                 */
11197         } TDFAR_b;
11198     };
11199 } R_ETHERC_EDMAC_Type;                 /*!< Size = 220 (0xdc)                                                         */
11200 
11201 /* =========================================================================================================================== */
11202 /* ================                                      R_ETHERC_EPTPC                                       ================ */
11203 /* =========================================================================================================================== */
11204 
11205 /**
11206  * @brief Ethernet PTP Controller (R_ETHERC_EPTPC)
11207  */
11208 
11209 typedef struct                         /*!< (@ 0x40065800) R_ETHERC_EPTPC Structure                                   */
11210 {
11211     union
11212     {
11213         __IOM uint32_t SYSR;           /*!< (@ 0x00000000) SYNFP Status Register                                      */
11214 
11215         struct
11216         {
11217             __IOM uint32_t OFMUD  : 1; /*!< [0..0] offsetFromMaster Value Update Flag                                 */
11218             __IOM uint32_t INTCHG : 1; /*!< [1..1] Receive logMessageInterval Value Change Detection Flag             */
11219             __IOM uint32_t MPDUD  : 1; /*!< [2..2] meanPathDelay Value Update Flag                                    */
11220             uint32_t              : 1;
11221             __IOM uint32_t DRPTO  : 1; /*!< [4..4] Delay_Resp/Pdelay_Resp Reception Timeout Detection Flag            */
11222             __IOM uint32_t INTDEV : 1; /*!< [5..5] Receive logMessageInterval Value Out-of-Range Flag                 */
11223             __IOM uint32_t DRQOVR : 1; /*!< [6..6] Delay_Req Reception FIFO Overflow Detection Flag                   */
11224             uint32_t              : 5;
11225             __IOM uint32_t RECLP  : 1; /*!< [12..12] Loop Reception Detection Flag                                    */
11226             uint32_t              : 1;
11227             __IOM uint32_t INFABT : 1; /*!< [14..14] Control Information Abnormality Detection Flag                   */
11228             uint32_t              : 1;
11229             __IOM uint32_t RESDN  : 1; /*!< [16..16] Response Stop Completion Detection Flag                          */
11230             __IOM uint32_t GENDN  : 1; /*!< [17..17] Generation Stop Completion Detection Flag                        */
11231             uint32_t              : 14;
11232         } SYSR_b;
11233     };
11234 
11235     union
11236     {
11237         __IOM uint32_t SYIPR;          /*!< (@ 0x00000004) SYNFP Status Notification Permission Register              */
11238 
11239         struct
11240         {
11241             __IOM uint32_t OFMUD  : 1; /*!< [0..0] SYSR.OFMUD Status Notification Permission                          */
11242             __IOM uint32_t INTCHG : 1; /*!< [1..1] SYSR.INTCHG Status Notification Permission                         */
11243             __IOM uint32_t MPDUD  : 1; /*!< [2..2] SYSR.MPDUD Status Notification Permission                          */
11244             uint32_t              : 1;
11245             __IOM uint32_t DRPTO  : 1; /*!< [4..4] SYSR.DRPTO Status Notification Permission                          */
11246             __IOM uint32_t INTDEV : 1; /*!< [5..5] SYSR.INTDEV Status Notification Permission                         */
11247             __IOM uint32_t DRQOVR : 1; /*!< [6..6] SYSR.DRQOVR Status Notification Permission                         */
11248             uint32_t              : 5;
11249             __IOM uint32_t RECLP  : 1; /*!< [12..12] SYSR.RECLP Status Notification Permission                        */
11250             uint32_t              : 1;
11251             __IOM uint32_t INFABT : 1; /*!< [14..14] SYSR.INFABT Status Notification Permission                       */
11252             uint32_t              : 1;
11253             __IOM uint32_t RESDN  : 1; /*!< [16..16] SYSR.RESDN Status Notification Permission                        */
11254             __IOM uint32_t GENDN  : 1; /*!< [17..17] SYSR.GENDN Status Notification Permission                        */
11255             uint32_t              : 14;
11256         } SYIPR_b;
11257     };
11258     __IM uint32_t RESERVED[2];
11259 
11260     union
11261     {
11262         __IOM uint32_t SYMACRU;          /*!< (@ 0x00000010) SYNFP MAC Address Registers                                */
11263 
11264         struct
11265         {
11266             __IOM uint32_t SYMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24
11267                                           *   bits of the local MAC address.                                            */
11268             uint32_t : 8;
11269         } SYMACRU_b;
11270     };
11271 
11272     union
11273     {
11274         __IOM uint32_t SYMACRL;          /*!< (@ 0x00000014) SYNFP MAC Address Registers                                */
11275 
11276         struct
11277         {
11278             __IOM uint32_t SYMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits
11279                                           *   of the local MAC address.                                                 */
11280             uint32_t : 8;
11281         } SYMACRL_b;
11282     };
11283 
11284     union
11285     {
11286         __IOM uint32_t SYLLCCTLR;      /*!< (@ 0x00000018) SYNFP LLC-CTL Value Register                               */
11287 
11288         struct
11289         {
11290             __IOM uint32_t CTL : 8;    /*!< [7..0] LLC-CTL FieldThese bits specify the value used for the
11291                                         *   control field in the LLC sublayer when generating IEEE802.3
11292                                         *   frames.                                                                   */
11293             uint32_t : 24;
11294         } SYLLCCTLR_b;
11295     };
11296 
11297     union
11298     {
11299         __IOM uint32_t SYIPADDRR;          /*!< (@ 0x0000001C) SYNFP Local IP Address Register                            */
11300 
11301         struct
11302         {
11303             __IOM uint32_t SYIPADDRR : 32; /*!< [31..0] These bits hold the setting for the local IP address.             */
11304         } SYIPADDRR_b;
11305     };
11306     __IM uint32_t RESERVED1[8];
11307 
11308     union
11309     {
11310         __IOM uint32_t SYSPVRR;        /*!< (@ 0x00000040) SYNFP Specification Version Setting Register               */
11311 
11312         struct
11313         {
11314             __IOM uint32_t VER : 4;    /*!< [3..0] versionPTP Field ValueThese bits are used to set the
11315                                         *   versionPTP field value of the PTP v2 header.When a message
11316                                         *   is received, this value is compared with the versionPTP
11317                                         *   field of the received frame.In generating messages, the
11318                                         *   value is used for the versionPTP field of the frame for
11319                                         *   transmission.Set these bits to 0010b (PTP v2).                            */
11320             __IOM uint32_t TRSP : 4;   /*!< [7..4] transportSpecific Field ValueThese bits are used to set
11321                                         *   the transportSpecific field value of the PTP v2 header.When
11322                                         *   a message is received, this value is compared with the
11323                                         *   transportSpecific field of the received frame.In generating
11324                                         *   messages, the value is used for the transportSpecific field
11325                                         *   of the frame for transmission.Set these bits to 0000b (IEEE
11326                                         *   1588).                                                                    */
11327             uint32_t : 24;
11328         } SYSPVRR_b;
11329     };
11330 
11331     union
11332     {
11333         __IOM uint32_t SYDOMR;         /*!< (@ 0x00000044) SYNFP Domain Number Setting Register                       */
11334 
11335         struct
11336         {
11337             __IOM uint32_t DNUM : 8;   /*!< [7..0] domainNumber Field Value SettingThese bits are used to
11338                                         *   set the domainNumber field value of the PTP v2 header.When
11339                                         *   a message is received, this value is compared with the
11340                                         *   domainNumber field of the received frame as a condition
11341                                         *   for PTP reception processing.In generating messages, the
11342                                         *   value is used for the domainNumber field of the frame for
11343                                         *   transmission.                                                             */
11344             uint32_t : 24;
11345         } SYDOMR_b;
11346     };
11347     __IM uint32_t RESERVED2[2];
11348 
11349     union
11350     {
11351         __IOM uint32_t ANFR;           /*!< (@ 0x00000050) Announce Message Flag Field Setting Register               */
11352 
11353         struct
11354         {
11355             __IOM uint32_t FLAG0 : 1;  /*!< [0..0] leap61This bit is used to set the logical value of the
11356                                         *   leap61 member of timePropertiesDS.                                        */
11357             __IOM uint32_t FLAG1 : 1;  /*!< [1..1] leap59This bit is used to set the logical value of the
11358                                         *   leap59 member of timePropertiesDS.                                        */
11359             __IOM uint32_t FLAG2 : 1;  /*!< [2..2] currentUtcOffsetValidThis bit is used to set the logical
11360                                         *   value of the currentUtcOffsetValid member of timePropertiesDS.            */
11361             __IOM uint32_t FLAG3 : 1;  /*!< [3..3] ptpTimescaleThis bit is used to set the logical value
11362                                         *   of the ptpTimescale member of timePropertiesDS.                           */
11363             __IOM uint32_t FLAG4 : 1;  /*!< [4..4] timeTraceableThis bit is used to set the logical value
11364                                         *   of the timeTraceable member of timePropertiesDS.                          */
11365             __IOM uint32_t FLAG5 : 1;  /*!< [5..5] frequencyTraceableThis bit is used to set the logical
11366                                         *   value of the frequencyTraceable member of timePropertiesDS.               */
11367             uint32_t              : 2;
11368             __IOM uint32_t FLAG8  : 1; /*!< [8..8] alternateMasterFlag                                                */
11369             uint32_t              : 1;
11370             __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag                                                      */
11371             uint32_t              : 2;
11372             __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1                                           */
11373             __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2                                           */
11374             uint32_t              : 17;
11375         } ANFR_b;
11376     };
11377 
11378     union
11379     {
11380         __IOM uint32_t SYNFR;          /*!< (@ 0x00000054) Sync Message Flag Field Setting Register                   */
11381 
11382         struct
11383         {
11384             uint32_t              : 8;
11385             __IOM uint32_t FLAG8  : 1; /*!< [8..8] alternateMasterFlag                                                */
11386             __IOM uint32_t FLAG9  : 1; /*!< [9..9] twoStepFlag                                                        */
11387             __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag                                                      */
11388             uint32_t              : 2;
11389             __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1                                           */
11390             __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2                                           */
11391             uint32_t              : 17;
11392         } SYNFR_b;
11393     };
11394 
11395     union
11396     {
11397         __IOM uint32_t DYRQFR;         /*!< (@ 0x00000058) Delay_Req Message Flag Field Setting Register              */
11398 
11399         struct
11400         {
11401             uint32_t              : 10;
11402             __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag                                                      */
11403             uint32_t              : 2;
11404             __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1                                           */
11405             __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2                                           */
11406             uint32_t              : 17;
11407         } DYRQFR_b;
11408     };
11409 
11410     union
11411     {
11412         __IOM uint32_t DYRPFR;         /*!< (@ 0x0000005C) Delay_Resp Message Flag Field Setting Register             */
11413 
11414         struct
11415         {
11416             uint32_t              : 8;
11417             __IOM uint32_t FLAG8  : 1; /*!< [8..8] alternateMasterFlag                                                */
11418             __IOM uint32_t FLAG9  : 1; /*!< [9..9] woStepFlag                                                         */
11419             __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag                                                      */
11420             uint32_t              : 2;
11421             __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1                                           */
11422             __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2                                           */
11423             uint32_t              : 17;
11424         } DYRPFR_b;
11425     };
11426 
11427     union
11428     {
11429         __IOM uint32_t SYCIDRU;          /*!< (@ 0x00000060) SYNFP Local Clock ID Registers                             */
11430 
11431         struct
11432         {
11433             __IOM uint32_t SYCIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
11434                                           *   bits of the clock-ID of your port.                                        */
11435         } SYCIDRU_b;
11436     };
11437 
11438     union
11439     {
11440         __IOM uint32_t SYCIDRL;          /*!< (@ 0x00000064) SYNFP Local Clock ID Registers                             */
11441 
11442         struct
11443         {
11444             __IOM uint32_t SYCIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
11445                                           *   of the clock-ID of your port.                                             */
11446         } SYCIDRL_b;
11447     };
11448 
11449     union
11450     {
11451         __IOM uint32_t SYPNUMR;        /*!< (@ 0x00000068) SYNFP Local Port Number Register                           */
11452 
11453         struct
11454         {
11455             __IOM uint32_t PNUM : 16;  /*!< [15..0] Local Port Number SettingThese bits hold the setting
11456                                         *   for the port number of the local port.                                    */
11457             uint32_t : 16;
11458         } SYPNUMR_b;
11459     };
11460     __IM uint32_t RESERVED3[5];
11461 
11462     union
11463     {
11464         __OM uint32_t SYRVLDR;         /*!< (@ 0x00000080) SYNFP Register Value Load Directive Register               */
11465 
11466         struct
11467         {
11468             __OM uint32_t BMUP : 1;    /*!< [0..0] BMC Update                                                         */
11469             __OM uint32_t STUP : 1;    /*!< [1..1] State Update                                                       */
11470             __OM uint32_t ANUP : 1;    /*!< [2..2] Announce Message Generation Information Update                     */
11471             uint32_t           : 29;
11472         } SYRVLDR_b;
11473     };
11474     __IM uint32_t RESERVED4[3];
11475 
11476     union
11477     {
11478         __IOM uint32_t SYRFL1R;        /*!< (@ 0x00000090) SYNFP Reception Filter Register 1                          */
11479 
11480         struct
11481         {
11482             __IOM uint32_t ANCE0  : 1; /*!< [0..0] Announce Message Processing                                        */
11483             __IOM uint32_t ANCE1  : 1; /*!< [1..1] Announce Message Processing                                        */
11484             uint32_t              : 2;
11485             __IOM uint32_t SYNC0  : 1; /*!< [4..4] Sync Message Processing                                            */
11486             __IOM uint32_t SYNC1  : 1; /*!< [5..5] Sync Message Processing                                            */
11487             __IOM uint32_t SYNC2  : 1; /*!< [6..6] Sync Message Processing                                            */
11488             uint32_t              : 1;
11489             __IOM uint32_t FUP0   : 1; /*!< [8..8] Follow_Up Message Processing                                       */
11490             __IOM uint32_t FUP1   : 1; /*!< [9..9] Follow_Up Message Processing                                       */
11491             __IOM uint32_t FUP2   : 1; /*!< [10..10] Follow_Up Message Processing                                     */
11492             uint32_t              : 1;
11493             __IOM uint32_t DRQ0   : 1; /*!< [12..12] Delay_Req Message Processing                                     */
11494             __IOM uint32_t DRQ1   : 1; /*!< [13..13] Delay_Req Message Processing                                     */
11495             __IOM uint32_t DRQ2   : 1; /*!< [14..14] Delay_Req Message Processing                                     */
11496             uint32_t              : 1;
11497             __IOM uint32_t DRP0   : 1; /*!< [16..16] Delay_Resp Message Processing                                    */
11498             __IOM uint32_t DRP1   : 1; /*!< [17..17] Delay_Resp Message Processing                                    */
11499             __IOM uint32_t DRP2   : 1; /*!< [18..18] Delay_Resp Message Processing                                    */
11500             uint32_t              : 1;
11501             __IOM uint32_t PDRQ0  : 1; /*!< [20..20] Pdelay_Req Message Processing                                    */
11502             __IOM uint32_t PDRQ1  : 1; /*!< [21..21] Pdelay_Req Message Processing                                    */
11503             __IOM uint32_t PDRQ2  : 1; /*!< [22..22] Pdelay_Req Message Processing                                    */
11504             uint32_t              : 1;
11505             __IOM uint32_t PDRP0  : 1; /*!< [24..24] Pdelay_Resp Message Processing                                   */
11506             __IOM uint32_t PDRP1  : 1; /*!< [25..25] Pdelay_Resp Message Processing                                   */
11507             __IOM uint32_t PDRP2  : 1; /*!< [26..26] Pdelay_Resp Message Processing                                   */
11508             uint32_t              : 1;
11509             __IOM uint32_t PDFUP0 : 1; /*!< [28..28] Pdelay_Resp_Follow_Up Message Processing                         */
11510             __IOM uint32_t PDFUP1 : 1; /*!< [29..29] Pdelay_Resp_Follow_Up Message Processing                         */
11511             __IOM uint32_t PDFUP2 : 1; /*!< [30..30] Pdelay_Resp_Follow_Up Message Processing                         */
11512             uint32_t              : 1;
11513         } SYRFL1R_b;
11514     };
11515 
11516     union
11517     {
11518         __IOM uint32_t SYRFL2R;        /*!< (@ 0x00000094) SYNFP Reception Filter Register 2                          */
11519 
11520         struct
11521         {
11522             __IOM uint32_t MAN0 : 1;   /*!< [0..0] Management Message Processing Setting                              */
11523             __IOM uint32_t MAN1 : 1;   /*!< [1..1] Management Message Processing Setting                              */
11524             uint32_t            : 2;
11525             __IOM uint32_t SIG0 : 1;   /*!< [4..4] Signaling Message Processing Setting                               */
11526             __IOM uint32_t SIG1 : 1;   /*!< [5..5] Signaling Message Processing Setting                               */
11527             uint32_t            : 22;
11528             __IOM uint32_t ILL0 : 1;   /*!< [28..28] Illegal Message Processing Setting                               */
11529             __IOM uint32_t ILL1 : 1;   /*!< [29..29] Illegal Message Processing Setting                               */
11530             uint32_t            : 2;
11531         } SYRFL2R_b;
11532     };
11533 
11534     union
11535     {
11536         __IOM uint32_t SYTRENR;        /*!< (@ 0x00000098) SYNFP Transmission Enable Register                         */
11537 
11538         struct
11539         {
11540             __IOM uint32_t ANCE : 1;   /*!< [0..0] Announce Message Transmission Enable                               */
11541             uint32_t            : 3;
11542             __IOM uint32_t SYNC : 1;   /*!< [4..4] Sync Message Transmission Enable                                   */
11543             uint32_t            : 3;
11544             __IOM uint32_t DRQ  : 1;   /*!< [8..8] Delay_Req Message Transmission Enable                              */
11545             uint32_t            : 3;
11546             __IOM uint32_t PDRQ : 1;   /*!< [12..12] Pdelay_Req Message Transmission Enable                           */
11547             uint32_t            : 19;
11548         } SYTRENR_b;
11549     };
11550     __IM uint32_t RESERVED5;
11551 
11552     union
11553     {
11554         __IOM uint32_t MTCIDU;          /*!< (@ 0x000000A0) Master Clock ID Registers                                  */
11555 
11556         struct
11557         {
11558             __IOM uint32_t MTCIDU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
11559                                          *   bits of the clock-ID of the master clock.                                 */
11560         } MTCIDU_b;
11561     };
11562 
11563     union
11564     {
11565         __IOM uint32_t MTCIDL;          /*!< (@ 0x000000A4) Master Clock ID Registers                                  */
11566 
11567         struct
11568         {
11569             __IOM uint32_t MTCIDL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
11570                                          *   of the clock-ID of the master clock.                                      */
11571         } MTCIDL_b;
11572     };
11573 
11574     union
11575     {
11576         __IOM uint32_t MTPID;          /*!< (@ 0x000000A8) Master clock port number register                          */
11577 
11578         struct
11579         {
11580             __IOM uint32_t PNUM : 16;  /*!< [15..0] Master Clock Port Number SettingThese bits hold the
11581                                         *   setting for the port number of the master clock.                          */
11582             uint32_t : 16;
11583         } MTPID_b;
11584     };
11585     __IM uint32_t RESERVED6[5];
11586 
11587     union
11588     {
11589         __IOM uint32_t SYTLIR;         /*!< (@ 0x000000C0) SYNFP Transmission Interval Setting Register               */
11590 
11591         struct
11592         {
11593             __IOM uint32_t ANCE : 8;   /*!< [7..0] Announce Message Transmission Interval SettingThese bits
11594                                         *   set the interval for the transmission of Announce messages.               */
11595             __IOM uint32_t SYNC : 8;   /*!< [15..8] Sync Message Transmission Interval SettingThese bits
11596                                         *   set the interval for the transmission of Sync messages.
11597                                         *   The setting is also placed in the logMessageInterval field
11598                                         *   of transmitted Sync messages.                                             */
11599             __IOM uint32_t DREQ : 8;   /*!< [23..16] Delay_Req Transmission Interval Average Value/ Pdelay_Req
11600                                         *   Transmission Interval SettingThe bits set the average interval
11601                                         *   for the transmission of Delay_Req messages and the interval
11602                                         *   for the transmission of Pdelay_Req messages.The setting
11603                                         *   is also placed in the logMessageInterval field of Delay_Resp
11604                                         *   messages.                                                                 */
11605             uint32_t : 8;
11606         } SYTLIR_b;
11607     };
11608 
11609     union
11610     {
11611         __IM uint32_t SYRLIR;          /*!< (@ 0x000000C4) SYNFP Received logMessageInterval Value Indication
11612                                         *                  Register                                                   */
11613 
11614         struct
11615         {
11616             __IM uint32_t ANCE : 8;    /*!< [7..0] Announce Message logMessageInterval Field IndicationThese
11617                                         *   bits indicate the logMessageInterval field value of a received
11618                                         *   Announce message.                                                         */
11619             __IM uint32_t SYNC : 8;    /*!< [15..8] Sync Message logMessageInterval Field IndicationThese
11620                                         *   bits indicate the logMessageInterval field value of a received
11621                                         *   Sync message.                                                             */
11622             __IM uint32_t DRESP : 8;   /*!< [23..16] Delay_Resp Message logMessageInterval Field IndicationThese
11623                                         *   bits indicate the logMessageInterval field value of a received
11624                                         *   Delay_Resp message.                                                       */
11625             uint32_t : 8;
11626         } SYRLIR_b;
11627     };
11628 
11629     union
11630     {
11631         __IM uint32_t OFMRU;           /*!< (@ 0x000000C8) offsetFromMaster Value Registers                           */
11632 
11633         struct
11634         {
11635             __IM uint32_t OFMRU : 32;  /*!< [31..0] These bits indicate the higher-order 32 bits of the
11636                                         *   calculated offsetFromMaster value.                                        */
11637         } OFMRU_b;
11638     };
11639 
11640     union
11641     {
11642         __IM uint32_t OFMRL;           /*!< (@ 0x000000CC) offsetFromMaster Value Registers                           */
11643 
11644         struct
11645         {
11646             __IM uint32_t OFMRL : 32;  /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated
11647                                         *   offsetFromMaster value.                                                   */
11648         } OFMRL_b;
11649     };
11650 
11651     union
11652     {
11653         __IM uint32_t MPDRU;           /*!< (@ 0x000000D0) meanPathDelay Value Registers                              */
11654 
11655         struct
11656         {
11657             __IM uint32_t MPDRU : 32;  /*!< [31..0] These bits indicate the higher-order 32 bits of the
11658                                         *   calculated meanPathDelay value.                                           */
11659         } MPDRU_b;
11660     };
11661 
11662     union
11663     {
11664         __IM uint32_t MPDRL;           /*!< (@ 0x000000D4) meanPathDelay Value Registers                              */
11665 
11666         struct
11667         {
11668             __IM uint32_t MPDRL : 32;  /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated
11669                                         *   meanPathDelay value.                                                      */
11670         } MPDRL_b;
11671     };
11672     __IM uint32_t RESERVED7[2];
11673 
11674     union
11675     {
11676         __IOM uint32_t GMPR;           /*!< (@ 0x000000E0) grandmasterPriority Field Setting Register                 */
11677 
11678         struct
11679         {
11680             __IOM uint32_t GMPR2 : 8;  /*!< [7..0] grandmasterPriority2 Field Value SettingThese bits are
11681                                         *   used to set the value of the grandmasterPriority2 fields
11682                                         *   of Announce messages.                                                     */
11683             uint32_t             : 8;
11684             __IOM uint32_t GMPR1 : 8;  /*!< [23..16] grandmasterPriority1 Field Value SettingThese bits
11685                                         *   are used to set the value of the grandmasterPriority1 fields
11686                                         *   of Announce messages.                                                     */
11687             uint32_t : 8;
11688         } GMPR_b;
11689     };
11690 
11691     union
11692     {
11693         __IOM uint32_t GMCQR;          /*!< (@ 0x000000E4) grandmasterClockQuality Field Setting Register             */
11694 
11695         struct
11696         {
11697             __IOM uint32_t GMCQR : 32; /*!< [31..0] These bits are used to set the value of the grandmasterClockQuality
11698                                         *   fields of Announce messages. The correspondence between
11699                                         *   bits and the grandmasterClockQuality fields is as listed
11700                                         *   below.b31 to b24: clockClassb23 to b16: clockAccuracyb15
11701                                         *   to b0: offsetScaledLogVariance                                            */
11702         } GMCQR_b;
11703     };
11704 
11705     union
11706     {
11707         __IOM uint32_t GMIDRU;          /*!< (@ 0x000000E8) grandmasterIdentity Field Setting Registers                */
11708 
11709         struct
11710         {
11711             __IOM uint32_t GMIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
11712                                          *   bits of the value of the grandmasterIdentity fields of
11713                                          *   Announce messages.                                                        */
11714         } GMIDRU_b;
11715     };
11716 
11717     union
11718     {
11719         __IOM uint32_t GMIDRL;          /*!< (@ 0x000000EC) grandmasterIdentity Field Setting Registers                */
11720 
11721         struct
11722         {
11723             __IOM uint32_t GMIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
11724                                          *   of the value of the grandmasterIdentity fields of Announce
11725                                          *   messages.                                                                 */
11726         } GMIDRL_b;
11727     };
11728 
11729     union
11730     {
11731         __IOM uint32_t CUOTSR;         /*!< (@ 0x000000F0) currentUtcOffset/timeSource Field Setting Register         */
11732 
11733         struct
11734         {
11735             __IOM uint32_t TSRC : 8;   /*!< [7..0] timeSource Field SettingThese bits set the value of the
11736                                         *   timeSource fields of Announce messages.                                   */
11737             uint32_t            : 8;
11738             __IOM uint32_t CUTO : 16;  /*!< [31..16] currentUtcOffset Field SettingThese bits set the value
11739                                         *   of the currentUtcOffset fields of Announce messages.                      */
11740         } CUOTSR_b;
11741     };
11742 
11743     union
11744     {
11745         __IOM uint32_t SRR;            /*!< (@ 0x000000F4) stepsRemoved Field Setting Register                        */
11746 
11747         struct
11748         {
11749             __IOM uint32_t SRMV : 16;  /*!< [15..0] stepsRemoved Field Value SettingThese bits set the value
11750                                         *   of the stepsRemoved fields of Announce messages.                          */
11751             uint32_t : 16;
11752         } SRR_b;
11753     };
11754     __IM uint32_t RESERVED8[2];
11755 
11756     union
11757     {
11758         __IOM uint32_t PPMACRU;          /*!< (@ 0x00000100) PTP-primary Message Destination MAC Address Setting
11759                                           *                  Registers                                                  */
11760 
11761         struct
11762         {
11763             __IOM uint32_t PPMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24
11764                                           *   bits of the destination MAC address for PTP-primary messages.             */
11765             uint32_t : 8;
11766         } PPMACRU_b;
11767     };
11768 
11769     union
11770     {
11771         __IOM uint32_t PPMACRL;          /*!< (@ 0x00000104) PTP-primary Message Destination MAC Address Setting
11772                                           *                  Registers                                                  */
11773 
11774         struct
11775         {
11776             __IOM uint32_t PPMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits
11777                                           *   of the destination MAC address for PTP-primary messages.                  */
11778             uint32_t : 8;
11779         } PPMACRL_b;
11780     };
11781 
11782     union
11783     {
11784         __IOM uint32_t PDMACRU;          /*!< (@ 0x00000108) PTP-pdelay Message MAC Address Setting Registers           */
11785 
11786         struct
11787         {
11788             __IOM uint32_t PDMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24
11789                                           *   bits of the destination MAC address for PTP-pdelay messages.              */
11790             uint32_t : 8;
11791         } PDMACRU_b;
11792     };
11793 
11794     union
11795     {
11796         __IOM uint32_t PDMACRL;          /*!< (@ 0x0000010C) PTP-pdelay Message MAC Address Setting Registers           */
11797 
11798         struct
11799         {
11800             __IOM uint32_t PDMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits
11801                                           *   of the destination MAC address for PTP-pdelay messages.                   */
11802             uint32_t : 8;
11803         } PDMACRL_b;
11804     };
11805 
11806     union
11807     {
11808         __IOM uint32_t PETYPER;        /*!< (@ 0x00000110) PTP Message EtherType Setting Register                     */
11809 
11810         struct
11811         {
11812             __IOM uint32_t TYPE : 16;  /*!< [15..0] PTP Message EtherType Value SettingThese bits hold the
11813                                         *   setting for the EtherType field value for frames in the
11814                                         *   Ethernet II format.                                                       */
11815             uint32_t : 16;
11816         } PETYPER_b;
11817     };
11818     __IM uint32_t RESERVED9[3];
11819 
11820     union
11821     {
11822         __IOM uint32_t PPIPR;          /*!< (@ 0x00000120) PTP-primary Message Destination IP Address Setting
11823                                         *                  Register                                                   */
11824 
11825         struct
11826         {
11827             __IOM uint32_t PPIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address
11828                                         *   for PTPprimary messages.                                                  */
11829         } PPIPR_b;
11830     };
11831 
11832     union
11833     {
11834         __IOM uint32_t PDIPR;          /*!< (@ 0x00000124) PTP-pdelay Message Destination IP Address Setting
11835                                         *                  Register                                                   */
11836 
11837         struct
11838         {
11839             __IOM uint32_t PDIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address
11840                                         *   for PTPpdelay messages.                                                   */
11841         } PDIPR_b;
11842     };
11843 
11844     union
11845     {
11846         __IOM uint32_t PETOSR;         /*!< (@ 0x00000128) PTP Event Message TOS Setting Register                     */
11847 
11848         struct
11849         {
11850             __IOM uint32_t EVTO : 8;   /*!< [7..0] PTP Event Message TOS Field Value SettingThese bits hold
11851                                         *   the setting for the value of the TOS field within the IPv4
11852                                         *   headers of PTP event messages.                                            */
11853             uint32_t : 24;
11854         } PETOSR_b;
11855     };
11856 
11857     union
11858     {
11859         __IOM uint32_t PGTOSR;         /*!< (@ 0x0000012C) PTP general Message TOS Setting Register                   */
11860 
11861         struct
11862         {
11863             __IOM uint32_t GETO : 8;   /*!< [7..0] PTP general Message TOS Field Value SettingThese bits
11864                                         *   hold the setting for the value of the TOS field within
11865                                         *   the IPv4 headers of PTP general messages.                                 */
11866             uint32_t : 24;
11867         } PGTOSR_b;
11868     };
11869 
11870     union
11871     {
11872         __IOM uint32_t PPTTLR;         /*!< (@ 0x00000130) PTP-primary Message TTL Setting Register                   */
11873 
11874         struct
11875         {
11876             __IOM uint32_t PRTL : 8;   /*!< [7..0] PTP-primary Message TTL Field Value SettingThese bits
11877                                         *   hold the setting for the value of the TTL field within
11878                                         *   the IPv4 headers of PTP-primary messages.                                 */
11879             uint32_t : 24;
11880         } PPTTLR_b;
11881     };
11882 
11883     union
11884     {
11885         __IOM uint32_t PDTTLR;         /*!< (@ 0x00000134) PTP-pdelay Message TTL Setting Register                    */
11886 
11887         struct
11888         {
11889             __IOM uint32_t PDTL : 8;   /*!< [7..0] PTP-pdelay Message TTL Field ValueThese bits hold the
11890                                         *   setting for the value of the TTL field within the IPv4
11891                                         *   headers of PTP-pdelay messages.                                           */
11892             uint32_t : 24;
11893         } PDTTLR_b;
11894     };
11895 
11896     union
11897     {
11898         __IOM uint32_t PEUDPR;         /*!< (@ 0x00000138) PTP Event Message UDP Destination Port Number
11899                                         *                  Setting Register                                           */
11900 
11901         struct
11902         {
11903             __IOM uint32_t EVUPT : 16; /*!< [15..0] PTP Event Message Destination Port Number SettingThese
11904                                         *   bits hold the setting for the value of the destination
11905                                         *   port number field within the UDP headers of PTP event messages.           */
11906             uint32_t : 16;
11907         } PEUDPR_b;
11908     };
11909 
11910     union
11911     {
11912         __IOM uint32_t PGUDPR;         /*!< (@ 0x0000013C) PTP general Message UDP Destination Port Number
11913                                         *                  Setting Register                                           */
11914 
11915         struct
11916         {
11917             __IOM uint32_t GEUPT : 16; /*!< [15..0] PTP general Message Destination Port NumberThese bits
11918                                         *   hold the setting for the value of the destination port
11919                                         *   number field within the UDP headers of PTP general messages.              */
11920             uint32_t : 16;
11921         } PGUDPR_b;
11922     };
11923 
11924     union
11925     {
11926         __IOM uint32_t FFLTR;          /*!< (@ 0x00000140) Frame Reception Filter Setting Register                    */
11927 
11928         struct
11929         {
11930             __IOM uint32_t SEL : 1;    /*!< [0..0] Receive MAC Address SelectNOTE: The setting of these
11931                                         *   bits is only effective when EXTPRM=0, ENB=1and RPT=1.                     */
11932             __IOM uint32_t PRT : 1;    /*!< [1..1] Frame Reception EnableNOTE: The setting of these bits
11933                                         *   is only effective when EXTPRM=0 and ENB=1.                                */
11934             __IOM uint32_t ENB : 1;    /*!< [2..2] Reception Filter EnableNOTE: The setting of these bits
11935                                         *   is only effective when EXTPRM=0.                                          */
11936             uint32_t              : 13;
11937             __IOM uint32_t EXTPRM : 1; /*!< [16..16] Extended Promiscuous ModeSetting                                 */
11938             uint32_t              : 15;
11939         } FFLTR_b;
11940     };
11941     __IM uint32_t RESERVED10[7];
11942 
11943     union
11944     {
11945         __IOM uint32_t FMAC0RU;          /*!< (@ 0x00000160) Frame Reception Filter MAC Address 0 Setting
11946                                           *                  Register Upper                                             */
11947 
11948         struct
11949         {
11950             __IOM uint32_t FMAC0RU : 24; /*!< [23..0] These bits specify the upper-order 24 bits of the destination
11951                                           *   MAC address for received multicast frames.                                */
11952             uint32_t : 8;
11953         } FMAC0RU_b;
11954     };
11955 
11956     union
11957     {
11958         __IOM uint32_t FMAC0RL;          /*!< (@ 0x00000164) Frame Reception Filter MAC Address 0 Setting
11959                                           *                  Register Lower                                             */
11960 
11961         struct
11962         {
11963             __IOM uint32_t FMAC0RL : 24; /*!< [23..0] These bits specify the lower-order 24 bits of the destination
11964                                           *   MAC address for received multicast frames.                                */
11965             uint32_t : 8;
11966         } FMAC0RL_b;
11967     };
11968 
11969     union
11970     {
11971         __IOM uint32_t FMAC1RU;          /*!< (@ 0x00000168) Frame Reception Filter MAC Address 1 Setting
11972                                           *                  Register Upper                                             */
11973 
11974         struct
11975         {
11976             __IOM uint32_t FMAC1RU : 24; /*!< [23..0] These bits specify the upper-order 24 bits of the destination
11977                                           *   MAC address for received multicast frames.                                */
11978             uint32_t : 8;
11979         } FMAC1RU_b;
11980     };
11981 
11982     union
11983     {
11984         __IOM uint32_t FMAC1RL;          /*!< (@ 0x0000016C) Frame Reception Filter MAC Address 1 Setting
11985                                           *                  Register Lower                                             */
11986 
11987         struct
11988         {
11989             __IOM uint32_t FMAC1RL : 24; /*!< [23..0] These bits specify the lower-order 24 bits of the destination
11990                                           *   MAC address for received multicast frames.                                */
11991             uint32_t : 8;
11992         } FMAC1RL_b;
11993     };
11994     __IM uint32_t RESERVED11[20];
11995 
11996     union
11997     {
11998         __IOM uint32_t DASYMRU;          /*!< (@ 0x000001C0) Asymmetric Delay Setting Registers                         */
11999 
12000         struct
12001         {
12002             __IOM uint32_t DASYMRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16
12003                                           *   bits of the asymmetric delay value.                                       */
12004             uint32_t : 16;
12005         } DASYMRU_b;
12006     };
12007 
12008     union
12009     {
12010         __IOM uint32_t DASYMRL;          /*!< (@ 0x000001C4) Asymmetric Delay Setting Registers                         */
12011 
12012         struct
12013         {
12014             __IOM uint32_t DASYMRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
12015                                           *   of the asymmetric delay value.                                            */
12016         } DASYMRL_b;
12017     };
12018 
12019     union
12020     {
12021         __IOM uint32_t TSLATR;         /*!< (@ 0x000001C8) Timestamp Latency Setting Register                         */
12022 
12023         struct
12024         {
12025             __IOM uint32_t EGP : 16;   /*!< [15..0] Input Port Timestamp Latency SettingThese bits hold
12026                                         *   the setting for the time stamp latency (ns) for the input
12027                                         *   ports.                                                                    */
12028             __IOM uint32_t INGP : 16;  /*!< [31..16] Output Port Timestamp Latency SettingThese bits hold
12029                                         *   the setting for the time stamp latency (ns) for the output
12030                                         *   ports.                                                                    */
12031         } TSLATR_b;
12032     };
12033 
12034     union
12035     {
12036         __IOM uint32_t SYCONFR;        /*!< (@ 0x000001CC) SYNFP Operation Setting Register                           */
12037 
12038         struct
12039         {
12040             __IOM uint32_t TCYC : 8;   /*!< [7..0] PTP Message Transmission Interval SettingThese bits are
12041                                         *   used to set the time from the completion of one transmission
12042                                         *   to the start of the next in cycles of the transmission
12043                                         *   clock. A value n in these bits means that a transmission
12044                                         *   interval of n cycles will be secured.No interval is secured
12045                                         *   if the setting is 00h.We recommend the setting 28h (40
12046                                         *   cycles).                                                                  */
12047             uint32_t              : 4;
12048             __IOM uint32_t SBDIS  : 1; /*!< [12..12] Sync Message Transmission Bandwidth Securing Disable             */
12049             uint32_t              : 3;
12050             __IOM uint32_t FILDIS : 1; /*!< [16..16] Receive Message domainNumber Filter Disable                      */
12051             uint32_t              : 3;
12052             __IOM uint32_t TCMOD  : 1; /*!< [20..20] TC Mode Setting                                                  */
12053             uint32_t              : 11;
12054         } SYCONFR_b;
12055     };
12056 
12057     union
12058     {
12059         __IOM uint32_t SYFORMR;        /*!< (@ 0x000001D0) SYNFP Frame Format Setting Register                        */
12060 
12061         struct
12062         {
12063             __IOM uint32_t FORM0 : 1;  /*!< [0..0] Ethernet/UDP Encapsulation                                         */
12064             __IOM uint32_t FORM1 : 1;  /*!< [1..1] Ethernet Frame Format Setting                                      */
12065             uint32_t             : 30;
12066         } SYFORMR_b;
12067     };
12068 
12069     union
12070     {
12071         __IOM uint32_t RSTOUTR;          /*!< (@ 0x000001D4) Response Message Reception Timeout Register                */
12072 
12073         struct
12074         {
12075             __IOM uint32_t RSTOUTR : 32; /*!< [31..0] Response Message Reception Timeout Time SettingA response
12076                                           *   message not being received within n x 1024 (ns), where
12077                                           *   n is the setting, is judged to represent a timeout.                       */
12078         } RSTOUTR_b;
12079     };
12080 } R_ETHERC_EPTPC_Type;                   /*!< Size = 472 (0x1d8)                                                        */
12081 
12082 /* =========================================================================================================================== */
12083 /* ================                                    R_ETHERC_EPTPC_CFG                                     ================ */
12084 /* =========================================================================================================================== */
12085 
12086 /**
12087  * @brief Ethernet PTP Configuration (R_ETHERC_EPTPC_CFG)
12088  */
12089 
12090 typedef struct                         /*!< (@ 0x40064500) R_ETHERC_EPTPC_CFG Structure                               */
12091 {
12092     union
12093     {
12094         __IOM uint32_t PTRSTR;         /*!< (@ 0x00000000) EPTPC Reset Register                                       */
12095 
12096         struct
12097         {
12098             __IOM uint32_t RESET : 1;  /*!< [0..0] EPTPC Software Reset                                               */
12099             uint32_t             : 31;
12100         } PTRSTR_b;
12101     };
12102 
12103     union
12104     {
12105         __IOM uint32_t STCSELR;         /*!< (@ 0x00000004) STCA Clock Select Register                                 */
12106 
12107         struct
12108         {
12109             __IOM uint32_t SCLKDIV : 3; /*!< [2..0] PCLKA Clock Frequency Division                                     */
12110             uint32_t               : 5;
12111             __IOM uint32_t SCLKSEL : 3; /*!< [10..8] STCA Clock Select                                                 */
12112             uint32_t               : 21;
12113         } STCSELR_b;
12114     };
12115 
12116     union
12117     {
12118         __IOM uint32_t BYPASS;          /*!< (@ 0x00000008) Bypass 1588 module Register                                */
12119 
12120         struct
12121         {
12122             __IOM uint32_t BYPASS0 : 1; /*!< [0..0] Bypass 1588 module for Ether 0ch                                   */
12123             uint32_t               : 15;
12124             __IOM uint32_t BYPASS1 : 1; /*!< [16..16] Bypass 1588 module for Ether 1ch                                 */
12125             uint32_t               : 15;
12126         } BYPASS_b;
12127     };
12128 } R_ETHERC_EPTPC_CFG_Type;              /*!< Size = 12 (0xc)                                                           */
12129 
12130 /* =========================================================================================================================== */
12131 /* ================                                   R_ETHERC_EPTPC_COMMON                                   ================ */
12132 /* =========================================================================================================================== */
12133 
12134 /**
12135  * @brief Ethernet PTP Controller Common (R_ETHERC_EPTPC_COMMON)
12136  */
12137 
12138 typedef struct                         /*!< (@ 0x40065000) R_ETHERC_EPTPC_COMMON Structure                            */
12139 {
12140     union
12141     {
12142         __IOM uint32_t MIESR;          /*!< (@ 0x00000000) MINT Interrupt Source Status Register                      */
12143 
12144         struct
12145         {
12146             __IM uint32_t ST    : 1;   /*!< [0..0] STCA Status Flag                                                   */
12147             __IM uint32_t SY0   : 1;   /*!< [1..1] SYNFP0 Status Flag                                                 */
12148             __IM uint32_t SY1   : 1;   /*!< [2..2] SYNFP1 Status Flag                                                 */
12149             __IM uint32_t PRC   : 1;   /*!< [3..3] PRC-TC Status Flag                                                 */
12150             uint32_t            : 12;
12151             __IOM uint32_t CYC0 : 1;   /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Flag                  */
12152             __IOM uint32_t CYC1 : 1;   /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Flag                  */
12153             __IOM uint32_t CYC2 : 1;   /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Flag                  */
12154             __IOM uint32_t CYC3 : 1;   /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Flag                  */
12155             __IOM uint32_t CYC4 : 1;   /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Flag                  */
12156             __IOM uint32_t CYC5 : 1;   /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Flag                  */
12157             uint32_t            : 10;
12158         } MIESR_b;
12159     };
12160 
12161     union
12162     {
12163         __IOM uint32_t MIEIPR;         /*!< (@ 0x00000004) MINT Interrupt Request Permission Register                 */
12164 
12165         struct
12166         {
12167             __IOM uint32_t ST   : 1;   /*!< [0..0] STCA Status Interrupt Request Permission                           */
12168             __IOM uint32_t SY0  : 1;   /*!< [1..1] SYNFP0 Status Interrupt Request Permission                         */
12169             __IOM uint32_t SY1  : 1;   /*!< [2..2] SYNFP1 Status Interrupt Request Permission                         */
12170             __IOM uint32_t PRC  : 1;   /*!< [3..3] PRC-TC Status Interrupt Request Permission                         */
12171             uint32_t            : 12;
12172             __IOM uint32_t CYC0 : 1;   /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Interrupt
12173                                         *   Request Permission                                                        */
12174             __IOM uint32_t CYC1 : 1;   /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Interrupt
12175                                         *   Request Permission                                                        */
12176             __IOM uint32_t CYC2 : 1;   /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Interrupt
12177                                         *   Request Permission                                                        */
12178             __IOM uint32_t CYC3 : 1;   /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Interrupt
12179                                         *   Request Permission                                                        */
12180             __IOM uint32_t CYC4 : 1;   /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Interrupt
12181                                         *   Request Permission                                                        */
12182             __IOM uint32_t CYC5 : 1;   /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Interrupt
12183                                         *   Request Permission                                                        */
12184             uint32_t : 10;
12185         } MIEIPR_b;
12186     };
12187     __IM uint32_t RESERVED[2];
12188 
12189     union
12190     {
12191         __IOM uint32_t ELIPPR;         /*!< (@ 0x00000010) ELC Output/ETHER_IPLS Interrupt Request Permission
12192                                         *                  Register                                                   */
12193 
12194         struct
12195         {
12196             __IOM uint32_t CYCP0 : 1;  /*!< [0..0] Pulse Output Timer 0 Rising Edge Detection Event Output
12197                                         *   Enable                                                                    */
12198             __IOM uint32_t CYCP1 : 1;  /*!< [1..1] Pulse Output Timer 1 Rising Edge Detection Event Output
12199                                         *   Enable                                                                    */
12200             __IOM uint32_t CYCP2 : 1;  /*!< [2..2] Pulse Output Timer 2 Rising Edge Detection Event Output
12201                                         *   Enable                                                                    */
12202             __IOM uint32_t CYCP3 : 1;  /*!< [3..3] Pulse Output Timer 3 Rising Edge Detection Event Output
12203                                         *   Enable                                                                    */
12204             __IOM uint32_t CYCP4 : 1;  /*!< [4..4] Pulse Output Timer 4 Rising Edge Detection Event Output
12205                                         *   Enable                                                                    */
12206             __IOM uint32_t CYCP5 : 1;  /*!< [5..5] Pulse Output Timer 5 Rising Edge Detection Event Output
12207                                         *   Enable                                                                    */
12208             uint32_t             : 2;
12209             __IOM uint32_t CYCN0 : 1;  /*!< [8..8] Pulse Output Timer 0 Falling Edge Detection Event Output
12210                                         *   Enable                                                                    */
12211             __IOM uint32_t CYCN1 : 1;  /*!< [9..9] Pulse Output Timer 1 Falling Edge Detection Event Output
12212                                         *   Enable                                                                    */
12213             __IOM uint32_t CYCN2 : 1;  /*!< [10..10] Pulse Output Timer 2 Falling Edge Detection Event Output
12214                                         *   Enable                                                                    */
12215             __IOM uint32_t CYCN3 : 1;  /*!< [11..11] Pulse Output Timer 3 Falling Edge Detection Event Output
12216                                         *   Enable                                                                    */
12217             __IOM uint32_t CYCN4 : 1;  /*!< [12..12] Pulse Output Timer 4 Falling Edge Detection Event Output
12218                                         *   Enable                                                                    */
12219             __IOM uint32_t CYCN5 : 1;  /*!< [13..13] Pulse Output Timer 5 Falling Edge Detection Event Output
12220                                         *   Enable                                                                    */
12221             uint32_t            : 2;
12222             __IOM uint32_t PLSP : 1;   /*!< [16..16] Pulse Output Timer Rising Edge Detection IPLS Interrupt
12223                                         *   Request Permission                                                        */
12224             uint32_t            : 7;
12225             __IOM uint32_t PLSN : 1;   /*!< [24..24] Pulse Output Timer Falling Edge Detection IPLS Interrupt
12226                                         *   Request Permission                                                        */
12227             uint32_t : 7;
12228         } ELIPPR_b;
12229     };
12230 
12231     union
12232     {
12233         __IOM uint32_t ELIPACR;        /*!< (@ 0x00000014) ELC Output/IPLS Interrupt Permission Automatic
12234                                         *                  Clearing Register                                          */
12235 
12236         struct
12237         {
12238             __IOM uint32_t CYCP0 : 1;  /*!< [0..0] ELIPPR.CYCP0 Bit Automatic Clearing                                */
12239             __IOM uint32_t CYCP1 : 1;  /*!< [1..1] ELIPPR.CYCP1 Bit Automatic Clearing                                */
12240             __IOM uint32_t CYCP2 : 1;  /*!< [2..2] ELIPPR.CYCP2 Bit Automatic Clearing                                */
12241             __IOM uint32_t CYCP3 : 1;  /*!< [3..3] ELIPPR.CYCP3 Bit Automatic Clearing                                */
12242             __IOM uint32_t CYCP4 : 1;  /*!< [4..4] ELIPPR.CYCP4 Bit Automatic Clearing                                */
12243             __IOM uint32_t CYCP5 : 1;  /*!< [5..5] ELIPPR.CYCP5 Bit Automatic Clearing                                */
12244             uint32_t             : 2;
12245             __IOM uint32_t CYCN0 : 1;  /*!< [8..8] ELIPPR.CYCN0 Bit Automatic Clearing                                */
12246             __IOM uint32_t CYCN1 : 1;  /*!< [9..9] ELIPPR.CYCN1 Bit Automatic Clearing                                */
12247             __IOM uint32_t CYCN2 : 1;  /*!< [10..10] ELIPPR.CYCN2 Bit Automatic Clearing                              */
12248             __IOM uint32_t CYCN3 : 1;  /*!< [11..11] ELIPPR.CYCN3 Bit Automatic Clearing                              */
12249             __IOM uint32_t CYCN4 : 1;  /*!< [12..12] ELIPPR.CYCN4 Bit Automatic Clearing                              */
12250             __IOM uint32_t CYCN5 : 1;  /*!< [13..13] ELIPPR.CYCN5 Bit Automatic Clearing                              */
12251             uint32_t             : 2;
12252             __IOM uint32_t PLSP  : 1;  /*!< [16..16] ELIPPR.PLSP Bit Automatic Clearing                               */
12253             uint32_t             : 7;
12254             __IOM uint32_t PLSN  : 1;  /*!< [24..24] ELIPPR.PLSN Bit Automatic Clearing                               */
12255             uint32_t             : 7;
12256         } ELIPACR_b;
12257     };
12258     __IM uint32_t RESERVED1[10];
12259 
12260     union
12261     {
12262         __IOM uint32_t STSR;            /*!< (@ 0x00000040) STCA Status Register                                       */
12263 
12264         struct
12265         {
12266             __IOM uint32_t SYNC    : 1; /*!< [0..0] Synchronized State Detection Flag                                  */
12267             __IOM uint32_t SYNCOUT : 1; /*!< [1..1] Synchronization Loss Detection Flag                                */
12268             uint32_t               : 1;
12269             __IOM uint32_t SYNTOUT : 1; /*!< [3..3] Sync Message Reception Timeout Detection Flag                      */
12270             __IOM uint32_t W10D    : 1; /*!< [4..4] Worst 10 Acquisition Completion Flag                               */
12271             uint32_t               : 27;
12272         } STSR_b;
12273     };
12274 
12275     union
12276     {
12277         __IOM uint32_t STIPR;           /*!< (@ 0x00000044) STCA Status Notification Permission Register               */
12278 
12279         struct
12280         {
12281             __IOM uint32_t SYNC    : 1; /*!< [0..0] SYNC Status Notification Enable                                    */
12282             __IOM uint32_t SYNCOUT : 1; /*!< [1..1] SYNCOUT Status Notification Enable                                 */
12283             uint32_t               : 1;
12284             __IOM uint32_t SYNTOUT : 1; /*!< [3..3] SYNTOUT Status Notification Enable                                 */
12285             __IOM uint32_t W10D    : 1; /*!< [4..4] W10D Status Notification Enable                                    */
12286             uint32_t               : 27;
12287         } STIPR_b;
12288     };
12289     __IM uint32_t RESERVED2[2];
12290 
12291     union
12292     {
12293         __IOM uint32_t STCFR;          /*!< (@ 0x00000050) STCA Clock Frequency Setting Register                      */
12294 
12295         struct
12296         {
12297             __IOM uint32_t STCF : 2;   /*!< [1..0] STCA Clock Frequency                                               */
12298             uint32_t            : 30;
12299         } STCFR_b;
12300     };
12301 
12302     union
12303     {
12304         __IOM uint32_t STMR;           /*!< (@ 0x00000054) STCA Operating Mode Register                               */
12305 
12306         struct
12307         {
12308             __IOM uint32_t WINT  : 8;  /*!< [7..0] Worst 10 Acquisition Time                                          */
12309             uint32_t             : 5;
12310             __IOM uint32_t CMOD  : 1;  /*!< [13..13] Time Synchronization Correction Mode                             */
12311             uint32_t             : 1;
12312             __IOM uint32_t W10S  : 1;  /*!< [15..15] Worst 10 Acquisition Control Select                              */
12313             __IOM uint32_t SYTH  : 4;  /*!< [19..16] Synchronized State Detection Threshold Setting                   */
12314             __IOM uint32_t DVTH  : 4;  /*!< [23..20] Synchronization Loss Detection Threshold Setting                 */
12315             uint32_t             : 4;
12316             __IOM uint32_t ALEN0 : 1;  /*!< [28..28] Alarm Detection Enable 0                                         */
12317             __IOM uint32_t ALEN1 : 1;  /*!< [29..29] Alarm Detection Enable 1                                         */
12318             uint32_t             : 2;
12319         } STMR_b;
12320     };
12321 
12322     union
12323     {
12324         __IOM uint32_t SYNTOR;          /*!< (@ 0x00000058) Sync Message Reception Timeout Register                    */
12325 
12326         struct
12327         {
12328             __IOM uint32_t SYNTOR : 32; /*!< [31..0] A Sync message not being received within 1024 x n (ns),
12329                                          *   where n is the setting, leads to a timeout for reception
12330                                          *   of Sync messages, leading to the STSR.SYNTOUT flag being
12331                                          *   set to 1.                                                                 */
12332         } SYNTOR_b;
12333     };
12334     __IM uint32_t RESERVED3;
12335 
12336     union
12337     {
12338         __IOM uint32_t IPTSELR;         /*!< (@ 0x00000060) IPLS Interrupt Request Timer Select Register               */
12339 
12340         struct
12341         {
12342             __IOM uint32_t IPTSEL0 : 1; /*!< [0..0] Pulse Output Timer 0 Select                                        */
12343             __IOM uint32_t IPTSEL1 : 1; /*!< [1..1] Pulse Output Timer 1 Select                                        */
12344             __IOM uint32_t IPTSEL2 : 1; /*!< [2..2] Pulse Output Timer 2 Select                                        */
12345             __IOM uint32_t IPTSEL3 : 1; /*!< [3..3] Pulse Output Timer 3 Select                                        */
12346             __IOM uint32_t IPTSEL4 : 1; /*!< [4..4] Pulse Output Timer 4 Select                                        */
12347             __IOM uint32_t IPTSEL5 : 1; /*!< [5..5] Pulse Output Timer 5 Select                                        */
12348             uint32_t               : 26;
12349         } IPTSELR_b;
12350     };
12351 
12352     union
12353     {
12354         __IOM uint32_t MITSELR;         /*!< (@ 0x00000064) MINT Interrupt Request Timer Select Register               */
12355 
12356         struct
12357         {
12358             __IOM uint32_t MINTEN0 : 1; /*!< [0..0] Pulse Output Timer 0 MINT Interrupt Output Enable                  */
12359             __IOM uint32_t MINTEN1 : 1; /*!< [1..1] Pulse Output Timer 1 MINT Interrupt Output Enable                  */
12360             __IOM uint32_t MINTEN2 : 1; /*!< [2..2] Pulse Output Timer 2 MINT Interrupt Output Enable                  */
12361             __IOM uint32_t MINTEN3 : 1; /*!< [3..3] Pulse Output Timer 3 MINT Interrupt Output Enable                  */
12362             __IOM uint32_t MINTEN4 : 1; /*!< [4..4] Pulse Output Timer 4 MINT Interrupt Output Enable                  */
12363             __IOM uint32_t MINTEN5 : 1; /*!< [5..5] Pulse Output Timer 5 MINT Interrupt Output Enable                  */
12364             uint32_t               : 26;
12365         } MITSELR_b;
12366     };
12367 
12368     union
12369     {
12370         __IOM uint32_t ELTSELR;         /*!< (@ 0x00000068) ELC Output Timer Select Register                           */
12371 
12372         struct
12373         {
12374             __IOM uint32_t ELTDIS0 : 1; /*!< [0..0] Pulse Output Timer 0 Event Generation Disable                      */
12375             __IOM uint32_t ELTDIS1 : 1; /*!< [1..1] Pulse Output Timer 1 Event Generation Disable                      */
12376             __IOM uint32_t ELTDIS2 : 1; /*!< [2..2] Pulse Output Timer 2 Event Generation Disable                      */
12377             __IOM uint32_t ELTDIS3 : 1; /*!< [3..3] Pulse Output Timer 3 Event Generation Disable                      */
12378             __IOM uint32_t ELTDIS4 : 1; /*!< [4..4] Pulse Output Timer 4 Event Generation Disable                      */
12379             __IOM uint32_t ELTDIS5 : 1; /*!< [5..5] Pulse Output Timer 5 Event Generation Disable                      */
12380             uint32_t               : 26;
12381         } ELTSELR_b;
12382     };
12383 
12384     union
12385     {
12386         __IOM uint32_t STCHSELR;       /*!< (@ 0x0000006C) Time Synchronization Channel Select Register               */
12387 
12388         struct
12389         {
12390             __IOM uint32_t SYSEL : 1;  /*!< [0..0] Timer Information Input SelectNOTE: Do not change the
12391                                         *   value of this bit while the SYNSTARTR.STR bit is 1.                       */
12392             uint32_t : 31;
12393         } STCHSELR_b;
12394     };
12395     __IM uint32_t RESERVED4[4];
12396 
12397     union
12398     {
12399         __IOM uint32_t SYNSTARTR;      /*!< (@ 0x00000080) Slave Time Synchronization Start Register                  */
12400 
12401         struct
12402         {
12403             __IOM uint32_t STR : 1;    /*!< [0..0] Slave Time Synchronization Control                                 */
12404             uint32_t           : 31;
12405         } SYNSTARTR_b;
12406     };
12407 
12408     union
12409     {
12410         __OM uint32_t LCIVLDR;         /*!< (@ 0x00000084) Local Time Counter Initial Value Load Directive
12411                                         *                  Register                                                   */
12412 
12413         struct
12414         {
12415             __OM uint32_t LOAD : 1;    /*!< [0..0] Local Time Counter Initial Value Load Directive                    */
12416             uint32_t           : 31;
12417         } LCIVLDR_b;
12418     };
12419     __IM uint32_t RESERVED5[2];
12420 
12421     union
12422     {
12423         __IOM uint32_t SYNTDARU;          /*!< (@ 0x00000090) Synchronization Loss Detection Threshold Registers         */
12424 
12425         struct
12426         {
12427             __IOM uint32_t SYNTDARU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
12428                                            *   bits of the threshold for detection of loss of synchronization.           */
12429         } SYNTDARU_b;
12430     };
12431 
12432     union
12433     {
12434         __IOM uint32_t SYNTDARL;          /*!< (@ 0x00000094) Synchronization Loss Detection Threshold Registers         */
12435 
12436         struct
12437         {
12438             __IOM uint32_t SYNTDARL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
12439                                            *   of the threshold for detection of loss of synchronization.                */
12440         } SYNTDARL_b;
12441     };
12442 
12443     union
12444     {
12445         __IOM uint32_t SYNTDBRU;          /*!< (@ 0x00000098) Synchronization Detection Threshold Registers              */
12446 
12447         struct
12448         {
12449             __IOM uint32_t SYNTDBRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32
12450                                            *   bits of the threshold for detection of synchronization.                   */
12451         } SYNTDBRU_b;
12452     };
12453 
12454     union
12455     {
12456         __IOM uint32_t SYNTDBRL;          /*!< (@ 0x0000009C) Synchronization Detection Threshold Registers              */
12457 
12458         struct
12459         {
12460             __IOM uint32_t SYNTDBRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
12461                                            *   of the threshold for detection of synchronization.                        */
12462         } SYNTDBRL_b;
12463     };
12464     __IM uint32_t RESERVED6[4];
12465 
12466     union
12467     {
12468         __IOM uint32_t LCIVRU;          /*!< (@ 0x000000B0) Local Time Counter Initial Value Registers                 */
12469 
12470         struct
12471         {
12472             __IOM uint32_t LCIVRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16
12473                                          *   bits of the integer portion of the initial value for the
12474                                          *   local timer counter.                                                      */
12475             uint32_t : 16;
12476         } LCIVRU_b;
12477     };
12478 
12479     union
12480     {
12481         __IOM uint32_t LCIVRM;          /*!< (@ 0x000000B4) Local Time Counter Initial Value Registers                 */
12482 
12483         struct
12484         {
12485             __IOM uint32_t LCIVRM : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
12486                                          *   of the integer portion of the initial value for the local
12487                                          *   timer counter.                                                            */
12488         } LCIVRM_b;
12489     };
12490 
12491     union
12492     {
12493         __IOM uint32_t LCIVRL;          /*!< (@ 0x000000B8) Local Time Counter Initial Value Registers                 */
12494 
12495         struct
12496         {
12497             __IOM uint32_t LCIVRL : 32; /*!< [31..0] These bits hold the setting for the fractional portion
12498                                          *   of the initial value of the local timer counter in nanoseconds.           */
12499         } LCIVRL_b;
12500     };
12501     __IM uint32_t RESERVED7[26];
12502 
12503     union
12504     {
12505         __IOM uint32_t GETW10R;        /*!< (@ 0x00000124) Worst 10 Acquisition Directive Register                    */
12506 
12507         struct
12508         {
12509             __IOM uint32_t GW10 : 1;   /*!< [0..0] Worst 10 Acquisition Directive                                     */
12510             uint32_t            : 31;
12511         } GETW10R_b;
12512     };
12513 
12514     union
12515     {
12516         __IOM uint32_t PLIMITRU;          /*!< (@ 0x00000128) Positive Gradient Limit Registers                          */
12517 
12518         struct
12519         {
12520             __IOM uint32_t PLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31
12521                                            *   bits of the limit for the positive gradient.                              */
12522             uint32_t : 1;
12523         } PLIMITRU_b;
12524     };
12525 
12526     union
12527     {
12528         __IOM uint32_t PLIMITRM;          /*!< (@ 0x0000012C) Positive Gradient Limit Registers                          */
12529 
12530         struct
12531         {
12532             __IOM uint32_t PLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32
12533                                            *   bits of the limit for the positive gradient.                              */
12534         } PLIMITRM_b;
12535     };
12536 
12537     union
12538     {
12539         __IOM uint32_t PLIMITRL;          /*!< (@ 0x00000130) Positive Gradient Limit Registers                          */
12540 
12541         struct
12542         {
12543             __IOM uint32_t PLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
12544                                            *   of the limit for the positive gradient.                                   */
12545         } PLIMITRL_b;
12546     };
12547 
12548     union
12549     {
12550         __IOM uint32_t MLIMITRU;          /*!< (@ 0x00000134) Negative Gradient Limit Registers                          */
12551 
12552         struct
12553         {
12554             __IOM uint32_t MLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31
12555                                            *   bits of the limit for the negative gradient.                              */
12556             uint32_t : 1;
12557         } MLIMITRU_b;
12558     };
12559 
12560     union
12561     {
12562         __IOM uint32_t MLIMITRM;          /*!< (@ 0x00000138) Negative Gradient Limit Registers                          */
12563 
12564         struct
12565         {
12566             __IOM uint32_t MLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32
12567                                            *   bits of the limit for the negative gradient.                              */
12568         } MLIMITRM_b;
12569     };
12570 
12571     union
12572     {
12573         __IOM uint32_t MLIMITRL;          /*!< (@ 0x0000013C) Negative Gradient Limit Registers                          */
12574 
12575         struct
12576         {
12577             __IOM uint32_t MLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits
12578                                            *   of the limit for the negative gradient.                                   */
12579         } MLIMITRL_b;
12580     };
12581 
12582     union
12583     {
12584         __IOM uint32_t GETINFOR;       /*!< (@ 0x00000140) Statistical Information Retention Control Register         */
12585 
12586         struct
12587         {
12588             __IOM uint32_t INFO : 1;   /*!< [0..0] Information Retention ControlNOTE: Once information fetching
12589                                         *   is directed, values of various statistical information
12590                                         *   read before completion of information fetching are not
12591                                         *   guaranteed.                                                               */
12592             uint32_t : 31;
12593         } GETINFOR_b;
12594     };
12595     __IM uint32_t RESERVED8[11];
12596 
12597     union
12598     {
12599         __IM uint32_t LCCVRU;          /*!< (@ 0x00000170) Local Time Counters                                        */
12600 
12601         struct
12602         {
12603             __IM uint32_t LCCVRU : 16; /*!< [15..0] These bits are for reading the higher-order 16 bits
12604                                         *   of the integer portion of the local timer counter's value.                */
12605             uint32_t : 16;
12606         } LCCVRU_b;
12607     };
12608 
12609     union
12610     {
12611         __IM uint32_t LCCVRM;          /*!< (@ 0x00000174) Local Time Counters                                        */
12612 
12613         struct
12614         {
12615             __IM uint32_t LCCVRM : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of
12616                                         *   the integer portion of the local timer counter's value.                   */
12617         } LCCVRM_b;
12618     };
12619 
12620     union
12621     {
12622         __IM uint32_t LCCVRL;          /*!< (@ 0x00000178) Local Time Counters                                        */
12623 
12624         struct
12625         {
12626             __IM uint32_t LCCVRL : 32; /*!< [31..0] These bits are for reading the fractional portion of
12627                                         *   the local timer counter's value (in nanoseconds).                         */
12628         } LCCVRL_b;
12629     };
12630     __IM uint32_t RESERVED9[37];
12631 
12632     union
12633     {
12634         __IM uint32_t PW10VRU;          /*!< (@ 0x00000210) Positive Gradient Worst 10 Value Registers                 */
12635 
12636         struct
12637         {
12638             __IM uint32_t PW10VRU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits
12639                                          *   of the positive gradient value.                                           */
12640         } PW10VRU_b;
12641     };
12642 
12643     union
12644     {
12645         __IM uint32_t PW10VRM;          /*!< (@ 0x00000214) Positive Gradient Worst 10 Value Registers                 */
12646 
12647         struct
12648         {
12649             __IM uint32_t PW10VRM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits
12650                                          *   of the positive gradient value.                                           */
12651         } PW10VRM_b;
12652     };
12653 
12654     union
12655     {
12656         __IM uint32_t PW10VRL;          /*!< (@ 0x00000218) Positive Gradient Worst 10 Value Registers                 */
12657 
12658         struct
12659         {
12660             __IM uint32_t PW10VRL : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of
12661                                          *   the positive gradient value.                                              */
12662         } PW10VRL_b;
12663     };
12664     __IM uint32_t RESERVED10[45];
12665 
12666     union
12667     {
12668         __IM uint32_t MW10RU;          /*!< (@ 0x000002D0) Negative Gradient Worst 10 Value Registers                 */
12669 
12670         struct
12671         {
12672             __IM uint32_t MW10RU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits
12673                                         *   of the negative gradient value.                                           */
12674         } MW10RU_b;
12675     };
12676 
12677     union
12678     {
12679         __IM uint32_t MW10RM;          /*!< (@ 0x000002D4) Negative Gradient Worst 10 Value Registers                 */
12680 
12681         struct
12682         {
12683             __IM uint32_t MW10RM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits
12684                                         *   of the negative gradient value.                                           */
12685         } MW10RM_b;
12686     };
12687 
12688     union
12689     {
12690         __IM uint32_t MW10RL;                  /*!< (@ 0x000002D8) Negative Gradient Worst 10 Value Registers                 */
12691 
12692         struct
12693         {
12694             __IM uint32_t MW10RL : 32;         /*!< [31..0] These bits are for reading the lower-order 32 bits of
12695                                                 *   the negative gradient value.                                              */
12696         } MW10RL_b;
12697     };
12698     __IM uint32_t RESERVED11[9];
12699     __IOM R_ETHERC_EPTPC_COMMON_TM_Type TM[6]; /*!< (@ 0x00000300) Timer Setting Registers                                    */
12700     __IM uint32_t RESERVED12[7];
12701 
12702     union
12703     {
12704         __IOM uint32_t TMSTARTR;       /*!< (@ 0x0000037C) Timer Start Register                                       */
12705 
12706         struct
12707         {
12708             __IOM uint32_t EN0 : 1;    /*!< [0..0] Pulse Output Timer 0 Start                                         */
12709             __IOM uint32_t EN1 : 1;    /*!< [1..1] Pulse Output Timer 1 Start                                         */
12710             __IOM uint32_t EN2 : 1;    /*!< [2..2] Pulse Output Timer 2 Start                                         */
12711             __IOM uint32_t EN3 : 1;    /*!< [3..3] Pulse Output Timer 3 Start                                         */
12712             __IOM uint32_t EN4 : 1;    /*!< [4..4] Pulse Output Timer 4 Start                                         */
12713             __IOM uint32_t EN5 : 1;    /*!< [5..5] Pulse Output Timer 5 Start                                         */
12714             uint32_t           : 26;
12715         } TMSTARTR_b;
12716     };
12717     __IM uint32_t RESERVED13[32];
12718 
12719     union
12720     {
12721         __IOM uint32_t PRSR;           /*!< (@ 0x00000400) PRC-TC Status Register                                     */
12722 
12723         struct
12724         {
12725             __IOM uint32_t OVRE0 : 1;  /*!< [0..0] Relay Packet Overflow Detection Flag 0                             */
12726             __IOM uint32_t OVRE1 : 1;  /*!< [1..1] Relay Packet Overflow Detection Flag 1                             */
12727             __IOM uint32_t OVRE2 : 1;  /*!< [2..2] Relay Packet Overflow Detection Flag 2                             */
12728             __IOM uint32_t OVRE3 : 1;  /*!< [3..3] Relay Packet Overflow Detection Flag 3                             */
12729             uint32_t             : 4;
12730             __IOM uint32_t MACE  : 1;  /*!< [8..8] Originating MAC Address Mismatch Detection Flag                    */
12731             uint32_t             : 19;
12732             __IOM uint32_t URE0  : 1;  /*!< [28..28] Relay Packet Underflow Detection Flag 0                          */
12733             __IOM uint32_t URE1  : 1;  /*!< [29..29] Relay Packet Underflow Detection Flag 1                          */
12734             uint32_t             : 2;
12735         } PRSR_b;
12736     };
12737 
12738     union
12739     {
12740         __IOM uint32_t PRIPR;          /*!< (@ 0x00000404) PRC-TC Status Notification Permission Register             */
12741 
12742         struct
12743         {
12744             __IOM uint32_t OVRE0 : 1;  /*!< [0..0] PRSR.OVRE0 Status Notification Permission                          */
12745             __IOM uint32_t OVRE1 : 1;  /*!< [1..1] PRSR.OVRE1 Status Notification Permission                          */
12746             __IOM uint32_t OVRE2 : 1;  /*!< [2..2] PRSR.OVRE2 Status Notification Permission                          */
12747             __IOM uint32_t OVRE3 : 1;  /*!< [3..3] PRSR.OVRE3 Status Notification Permission                          */
12748             uint32_t             : 4;
12749             __IOM uint32_t MACE  : 1;  /*!< [8..8] PRSR.MACE Status Notification Permission                           */
12750             uint32_t             : 19;
12751             __IOM uint32_t URE0  : 1;  /*!< [28..28] PRSR.URE0 Status Notification Permission                         */
12752             __IOM uint32_t URE1  : 1;  /*!< [29..29] PRSR.URE1 Status Notification Permission                         */
12753             uint32_t             : 2;
12754         } PRIPR_b;
12755     };
12756     __IM uint32_t RESERVED14[2];
12757     __IOM R_ETHERC_EPTPC_COMMON_PR_Type PR[2]; /*!< (@ 0x00000410) Local MAC Address Registers                                */
12758 
12759     union
12760     {
12761         __IOM uint32_t TRNDISR;                /*!< (@ 0x00000420) Packet Transmission Control Register                       */
12762 
12763         struct
12764         {
12765             __IOM uint32_t TDIS : 2;           /*!< [1..0] Packet Transmission Control                                        */
12766             uint32_t            : 30;
12767         } TRNDISR_b;
12768     };
12769     __IM uint32_t RESERVED15[3];
12770 
12771     union
12772     {
12773         __IOM uint32_t TRNMR;          /*!< (@ 0x00000430) Relay Mode Register                                        */
12774 
12775         struct
12776         {
12777             __IOM uint32_t MOD  : 1;   /*!< [0..0] Cut-Through Mode                                                   */
12778             uint32_t            : 7;
12779             __IOM uint32_t FWD0 : 1;   /*!< [8..8] Channel 0 Relay Enable                                             */
12780             __IOM uint32_t FWD1 : 1;   /*!< [9..9] Channel 1 Relay Enable                                             */
12781             uint32_t            : 22;
12782         } TRNMR_b;
12783     };
12784 
12785     union
12786     {
12787         __IOM uint32_t TRNCTTDR;       /*!< (@ 0x00000434) Cut-Through Transfer Start Threshold Register              */
12788 
12789         struct
12790         {
12791             __IOM uint32_t THVAL : 11; /*!< [10..0] FIFO Read Start ThresholdThreshold for starting to read
12792                                         *   data from the relay FIFO in cut-through mode (specified
12793                                         *   as the number of bytes)NOTE1: A value cannot be set in
12794                                         *   the lower-order 2 bits. These bits are fixed to 0.NOTE2:
12795                                         *   A value of less than 96 bytes cannot be set.                              */
12796             uint32_t : 21;
12797         } TRNCTTDR_b;
12798     };
12799 } R_ETHERC_EPTPC_COMMON_Type;          /*!< Size = 1080 (0x438)                                                       */
12800 
12801 /* =========================================================================================================================== */
12802 /* ================                                       R_FACI_HP_CMD                                       ================ */
12803 /* =========================================================================================================================== */
12804 
12805 /**
12806  * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD)
12807  */
12808 
12809 typedef struct                         /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure                                    */
12810 {
12811     union
12812     {
12813         __IOM uint16_t FACI_CMD16;     /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access)                */
12814         __IOM uint8_t  FACI_CMD8;      /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access)                */
12815     };
12816 } R_FACI_HP_CMD_Type;                  /*!< Size = 2 (0x2)                                                            */
12817 
12818 /* =========================================================================================================================== */
12819 /* ================                                         R_FACI_HP                                         ================ */
12820 /* =========================================================================================================================== */
12821 
12822 /**
12823  * @brief Flash Application Command Interface (R_FACI_HP)
12824  */
12825 
12826 typedef struct                         /*!< (@ 0x407FE000) R_FACI_HP Structure                                        */
12827 {
12828     __IM uint32_t RESERVED[4];
12829 
12830     union
12831     {
12832         __IOM uint8_t FASTAT;          /*!< (@ 0x00000010) Flash Access Status                                        */
12833 
12834         struct
12835         {
12836             __IM uint8_t ECRCT  : 1;   /*!< [0..0] ECRCT                                                              */
12837             uint8_t             : 2;
12838             __IOM uint8_t DFAE  : 1;   /*!< [3..3] Data Flash Access Error                                            */
12839             __IM uint8_t  CMDLK : 1;   /*!< [4..4] Command Lock                                                       */
12840             uint8_t             : 2;
12841             __IOM uint8_t CFAE  : 1;   /*!< [7..7] Code Flash Access Error                                            */
12842         } FASTAT_b;
12843     };
12844     __IM uint8_t  RESERVED1;
12845     __IM uint16_t RESERVED2;
12846 
12847     union
12848     {
12849         __IOM uint8_t FAEINT;          /*!< (@ 0x00000014) Flash Access Error Interrupt Enable                        */
12850 
12851         struct
12852         {
12853             __IOM uint8_t ECRCTIE : 1; /*!< [0..0] Error Correct Interrupt Enable                                     */
12854             uint8_t               : 2;
12855             __IOM uint8_t DFAEIE  : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable                           */
12856             __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable                                      */
12857             uint8_t               : 2;
12858             __IOM uint8_t CFAEIE  : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable                           */
12859         } FAEINT_b;
12860     };
12861     __IM uint8_t  RESERVED3;
12862     __IM uint16_t RESERVED4;
12863 
12864     union
12865     {
12866         __IOM uint8_t FRDYIE;          /*!< (@ 0x00000018) Flash Ready Interrupt Enable                               */
12867 
12868         struct
12869         {
12870             __IOM uint8_t FRDYIE : 1;  /*!< [0..0] FRDY Interrupt Enable                                              */
12871             uint8_t              : 7;
12872         } FRDYIE_b;
12873     };
12874     __IM uint8_t  RESERVED5;
12875     __IM uint16_t RESERVED6;
12876     __IM uint32_t RESERVED7[5];
12877 
12878     union
12879     {
12880         __IOM uint32_t FSADDR;         /*!< (@ 0x00000030) Flash Start Address                                        */
12881 
12882         struct
12883         {
12884             __IOM uint32_t FSA : 32;   /*!< [31..0] Start Address of Flash Sequencer Command Target Area
12885                                         *   These bits can be written when FRDY bit of FSTATR register
12886                                         *   is "1". Writing to these bits in FRDY = "0" is ignored.                   */
12887         } FSADDR_b;
12888     };
12889 
12890     union
12891     {
12892         __IOM uint32_t FEADDR;         /*!< (@ 0x00000034) Flash End Address                                          */
12893 
12894         struct
12895         {
12896             __IOM uint32_t FEA : 32;   /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies
12897                                         *   end address of target area in "Blank Check" command. These
12898                                         *   bits can be written when FRDY bit of FSTATR register is
12899                                         *   "1". Writing to these bits in FRDY = "0" is ignored.                      */
12900         } FEADDR_b;
12901     };
12902     __IM uint32_t RESERVED8[3];
12903 
12904     union
12905     {
12906         __IOM uint16_t FMEPROT;        /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register                   */
12907 
12908         struct
12909         {
12910             __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit
12911                                         *   is only possible when the FRDY bit in the FSTATR register
12912                                         *   is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing
12913                                         *   to this bit is only possible when 16 bits are written and
12914                                         *   the value written to the KEY bits is D9h.Written values
12915                                         *   are not retained by these bits (always read as 0x00).Only
12916                                         *   secure access can write to this register. Both secure access
12917                                         *   and non-secure read access are allowed. Non-secure writeaccess
12918                                         *   is denied, but TrustZo                                                    */
12919             uint16_t          : 7;
12920             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
12921         } FMEPROT_b;
12922     };
12923     __IM uint16_t RESERVED9;
12924     __IM uint32_t RESERVED10[12];
12925 
12926     union
12927     {
12928         __IOM uint16_t FBPROT0;        /*!< (@ 0x00000078) Flash Block Protection Register                            */
12929 
12930         struct
12931         {
12932             __IOM uint16_t BPCN0 : 1;  /*!< [0..0] Block Protection for Non-secure CancelThis bit can be
12933                                         *   written when the FRDY bit in the FSTATR register is 1.
12934                                         *   Writing to this bit is ignored when the FRDY bit is 0.Writing
12935                                         *   to this bit is only possible when 16 bits are written and
12936                                         *   the value written to the KEY[7:0] bits is 0x78.Written
12937                                         *   values are not retained by these bits (always read as 0x00).              */
12938             uint16_t          : 7;
12939             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
12940         } FBPROT0_b;
12941     };
12942     __IM uint16_t RESERVED11;
12943 
12944     union
12945     {
12946         __IOM uint16_t FBPROT1;        /*!< (@ 0x0000007C) Flash Block Protection for Secure Register                 */
12947 
12948         struct
12949         {
12950             __IOM uint16_t BPCN1 : 1;  /*!< [0..0] Block Protection for Secure CancelWriting to this bit
12951                                         *   is only possible when the FRDY bit in the FSTATR register
12952                                         *   is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing
12953                                         *   to this bit is only possible when 16 bits are written and
12954                                         *   the value written to the KEY[7:0] bits is 0xB1.Written
12955                                         *   values are not retained by these bits (always read as 0x00).              */
12956             uint16_t          : 7;
12957             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
12958         } FBPROT1_b;
12959     };
12960     __IM uint16_t RESERVED12;
12961 
12962     union
12963     {
12964         __IM uint32_t FSTATR;          /*!< (@ 0x00000080) Flash Status                                               */
12965 
12966         struct
12967         {
12968             uint32_t                 : 6;
12969             __IM uint32_t FLWEERR    : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag                               */
12970             uint32_t                 : 1;
12971             __IM uint32_t PRGSPD     : 1; /*!< [8..8] Programming-Suspended Status                                       */
12972             __IM uint32_t ERSSPD     : 1; /*!< [9..9] Erasure-Suspended Status                                           */
12973             __IM uint32_t DBFULL     : 1; /*!< [10..10] Data Buffer Full                                                 */
12974             __IM uint32_t SUSRDY     : 1; /*!< [11..11] Suspend Ready                                                    */
12975             __IM uint32_t PRGERR     : 1; /*!< [12..12] Programming Error                                                */
12976             __IM uint32_t ERSERR     : 1; /*!< [13..13] Erasure Error                                                    */
12977             __IM uint32_t ILGLERR    : 1; /*!< [14..14] Illegal Command Error                                            */
12978             __IM uint32_t FRDY       : 1; /*!< [15..15] Flash Ready                                                      */
12979             uint32_t                 : 4;
12980             __IM uint32_t  OTERR     : 1; /*!< [20..20] Other Error                                                      */
12981             __IOM uint32_t SECERR    : 1; /*!< [21..21] Security Error                                                   */
12982             __IM uint32_t  FESETERR  : 1; /*!< [22..22] FENTRY Setting Error                                             */
12983             __IM uint32_t  ILGCOMERR : 1; /*!< [23..23] Illegal Command Error                                            */
12984             uint32_t                 : 8;
12985         } FSTATR_b;
12986     };
12987 
12988     union
12989     {
12990         __IOM uint16_t FENTRYR;         /*!< (@ 0x00000084) Program/Erase Mode Entry                                   */
12991 
12992         struct
12993         {
12994             __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when
12995                                          *   FRDY bit in FSTATR register is "1". Writing to this bit
12996                                          *   in FRDY = "0" is ignored. Writing to these bits is enabled
12997                                          *   only when this register is accessed in 16-bit size and
12998                                          *   H'AA is written to KEY bits                                               */
12999             uint16_t               : 6;
13000             __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when
13001                                          *   FRDY bit in FSTATR register is "1". Writing to this bit
13002                                          *   in FRDY = "0" is ignored. Writing to these bits is enabled
13003                                          *   only when this register is accessed in 16-bit size and
13004                                          *   H'AA is written to KEY bits.                                              */
13005             __OM uint16_t KEY : 8;      /*!< [15..8] KEY Code                                                          */
13006         } FENTRYR_b;
13007     };
13008     __IM uint16_t RESERVED13;
13009     __IM uint32_t RESERVED14;
13010 
13011     union
13012     {
13013         __IOM uint16_t FSUINITR;       /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize                          */
13014 
13015         struct
13016         {
13017             __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY
13018                                         *   bit of FSTATR register is "1". Writing to this bit in FRDY
13019                                         *   = "0" is ignored. Writing to these bits is enabled only
13020                                         *   when this register is accessed in 16-bit size and H'2D
13021                                         *   is written to KEY bits.                                                   */
13022             uint16_t          : 7;
13023             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
13024         } FSUINITR_b;
13025     };
13026     __IM uint16_t RESERVED15;
13027     __IM uint32_t RESERVED16[4];
13028 
13029     union
13030     {
13031         __IM uint16_t FCMDR;           /*!< (@ 0x000000A0) Flash Sequencer Command                                    */
13032 
13033         struct
13034         {
13035             __IM uint16_t PCMDR : 8;   /*!< [7..0] Previous Command Register                                          */
13036             __IM uint16_t CMDR  : 8;   /*!< [15..8] Command Register                                                  */
13037         } FCMDR_b;
13038     };
13039     __IM uint16_t RESERVED17;
13040     __IM uint32_t RESERVED18[7];
13041 
13042     union
13043     {
13044         __IM uint16_t FPESTAT;         /*!< (@ 0x000000C0) Program/Erase Error Status                                 */
13045 
13046         struct
13047         {
13048             __IM uint16_t PEERRST : 8; /*!< [7..0] P/E Error Status                                                   */
13049             uint16_t              : 8;
13050         } FPESTAT_b;
13051     };
13052     __IM uint16_t RESERVED19;
13053     __IM uint32_t RESERVED20[3];
13054 
13055     union
13056     {
13057         __IOM uint8_t FBCCNT;          /*!< (@ 0x000000D0) Blank Check Control                                        */
13058 
13059         struct
13060         {
13061             __IOM uint8_t BCDIR : 1;   /*!< [0..0] Blank Check Direction                                              */
13062             uint8_t             : 7;
13063         } FBCCNT_b;
13064     };
13065     __IM uint8_t  RESERVED21;
13066     __IM uint16_t RESERVED22;
13067 
13068     union
13069     {
13070         __IM uint8_t FBCSTAT;          /*!< (@ 0x000000D4) Blank Check Status                                         */
13071 
13072         struct
13073         {
13074             __IM uint8_t BCST : 1;     /*!< [0..0] Blank Check Status Bit                                             */
13075             uint8_t           : 7;
13076         } FBCSTAT_b;
13077     };
13078     __IM uint8_t  RESERVED23;
13079     __IM uint16_t RESERVED24;
13080 
13081     union
13082     {
13083         __IM uint32_t FPSADDR;         /*!< (@ 0x000000D8) Programmed Area Start Address                              */
13084 
13085         struct
13086         {
13087             __IM uint32_t PSADR : 19;  /*!< [18..0] Programmed Area Start Address NOTE: Indicates address
13088                                         *   of the first programmed data which is found in "Blank Check"
13089                                         *   command execution.                                                        */
13090             uint32_t : 13;
13091         } FPSADDR_b;
13092     };
13093 
13094     union
13095     {
13096         __IM uint32_t FAWMON;          /*!< (@ 0x000000DC) Flash Access Window Monitor                                */
13097 
13098         struct
13099         {
13100             __IM uint32_t FAWS : 11;   /*!< [10..0] Start Sector Address for Access Window NOTE: These bits
13101                                         *   indicate the start sector address for setting the access
13102                                         *   window that is located in the configuration area.                         */
13103             uint32_t           : 4;
13104             __IM uint32_t FSPR : 1;    /*!< [15..15] Protection Flag of programming the Access Window, Boot
13105                                         *   Flag and Temporary Boot Swap Control and "Config Clear"
13106                                         *   command execution                                                         */
13107             __IM uint32_t FAWE : 11;   /*!< [26..16] End Sector Address for Access Window NOTE: These bits
13108                                         *   indicate the end sector address for setting the access
13109                                         *   window that is located in the configuration area.                         */
13110             uint32_t            : 4;
13111             __IM uint32_t BTFLG : 1;   /*!< [31..31] Flag of Start-Up area select for Boot Swap                       */
13112         } FAWMON_b;
13113     };
13114 
13115     union
13116     {
13117         __IOM uint16_t FCPSR;           /*!< (@ 0x000000E0) FCU Process Switch                                         */
13118 
13119         struct
13120         {
13121             __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode                                             */
13122             uint16_t               : 15;
13123         } FCPSR_b;
13124     };
13125     __IM uint16_t RESERVED25;
13126 
13127     union
13128     {
13129         __IOM uint16_t FPCKAR;         /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification    */
13130 
13131         struct
13132         {
13133             __IOM uint16_t PCKA : 8;   /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits
13134                                         *   can be written when FRDY bit in FSTATR register is "1".
13135                                         *   Writing to this bit in FRDY = "0" is ignored. Writing to
13136                                         *   these bits is enabled only when this register is accessed
13137                                         *   in 16-bit size and H'1E is written to KEY bits.                           */
13138             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
13139         } FPCKAR_b;
13140     };
13141     __IM uint16_t RESERVED26;
13142 
13143     union
13144     {
13145         __IOM uint16_t FSUACR;         /*!< (@ 0x000000E8) Flash Start-Up Area Control Register                       */
13146 
13147         struct
13148         {
13149             __IOM uint16_t SAS : 2;    /*!< [1..0] Start Up Area Select These bits can be written when FRDY
13150                                         *   bit in FSTATR register is "1". Writing to this bit in FRDY
13151                                         *   = "0" is ignored. Writing to these bits is enabled only
13152                                         *   when this register is accessed in 16-bit size and H'66
13153                                         *   is written to KEY bits.                                                   */
13154             uint16_t          : 6;
13155             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
13156         } FSUACR_b;
13157     };
13158     __IM uint16_t RESERVED27;
13159 } R_FACI_HP_Type;                      /*!< Size = 236 (0xec)                                                         */
13160 
13161 /* =========================================================================================================================== */
13162 /* ================                                         R_FACI_LP                                         ================ */
13163 /* =========================================================================================================================== */
13164 
13165 /**
13166  * @brief Flash Application Command Interface (R_FACI_LP)
13167  */
13168 
13169 typedef struct                         /*!< (@ 0x407EC000) R_FACI_LP Structure                                        */
13170 {
13171     __IM uint32_t RESERVED[36];
13172     __IOM uint8_t DFLCTL;              /*!< (@ 0x00000090) Flash P/E Mode Control Register                            */
13173     __IM uint8_t  RESERVED1;
13174     __IM uint16_t RESERVED2;
13175     __IM uint32_t RESERVED3[27];
13176 
13177     union
13178     {
13179         __IOM uint8_t FPMCR;           /*!< (@ 0x00000100) Flash P/E Mode Control Register                            */
13180 
13181         struct
13182         {
13183             uint8_t            : 1;
13184             __IOM uint8_t FMS0 : 1;    /*!< [1..1] Flash Operating Mode Select 0FMS2,1,0: 000: Read mode
13185                                         *   011: Discharge mode 1 111: Discharge mode 2 101: Code Flash
13186                                         *   P/E mode 010: Data flash P/E mode Others: Setting prohibited.             */
13187             uint8_t             : 1;
13188             __IOM uint8_t RPDIS : 1;   /*!< [3..3] Code Flash P/E Disable                                             */
13189             __IOM uint8_t FMS1  : 1;   /*!< [4..4] The bit to make data flash a programming modeRefer to
13190                                         *   the description of the FMS0 bit.                                          */
13191             uint8_t            : 1;
13192             __IOM uint8_t VLPE : 1;    /*!< [6..6] Low-Voltage P/E Mode Enable                                        */
13193             __IOM uint8_t FMS2 : 1;    /*!< [7..7] Flash Operating Mode Select 2.Refer to the description
13194                                         *   of the FMS0 bit.                                                          */
13195         } FPMCR_b;
13196     };
13197     __IM uint8_t  RESERVED4;
13198     __IM uint16_t RESERVED5;
13199 
13200     union
13201     {
13202         __IOM uint8_t FASR;            /*!< (@ 0x00000104) Flash Area Select Register                                 */
13203 
13204         struct
13205         {
13206             __IOM uint8_t EXS : 1;     /*!< [0..0] Extra area select                                                  */
13207             uint8_t           : 7;
13208         } FASR_b;
13209     };
13210     __IM uint8_t  RESERVED6;
13211     __IM uint16_t RESERVED7;
13212 
13213     union
13214     {
13215         __IOM uint16_t FSARL;             /*!< (@ 0x00000108) Flash Processing Start Address Register L                  */
13216 
13217         struct
13218         {
13219             __IOM uint16_t FSAR15_0 : 16; /*!< [15..0] Start address                                                     */
13220         } FSARL_b;
13221     };
13222     __IM uint16_t RESERVED8;
13223     __IM uint32_t RESERVED9;
13224 
13225     union
13226     {
13227         __IOM uint16_t FSARH;             /*!< (@ 0x00000110) Flash Processing Start Address Register H                  */
13228 
13229         struct
13230         {
13231             __IOM uint16_t FSAR20_16 : 5; /*!< [4..0] Start address                                                      */
13232             uint16_t                 : 4;
13233             __IOM uint16_t FSAR31_25 : 7; /*!< [15..9] Start address                                                     */
13234         } FSARH_b;
13235     };
13236     __IM uint16_t RESERVED10;
13237 
13238     union
13239     {
13240         __IOM uint8_t FCR;             /*!< (@ 0x00000114) Flash Control Register                                     */
13241 
13242         struct
13243         {
13244             __IOM uint8_t CMD  : 4;    /*!< [3..0] Software Command Setting                                           */
13245             __IOM uint8_t DRC  : 1;    /*!< [4..4] Data Read Completion                                               */
13246             uint8_t            : 1;
13247             __IOM uint8_t STOP : 1;    /*!< [6..6] Forced Processing Stop                                             */
13248             __IOM uint8_t OPST : 1;    /*!< [7..7] Processing Start                                                   */
13249         } FCR_b;
13250     };
13251     __IM uint8_t  RESERVED11;
13252     __IM uint16_t RESERVED12;
13253 
13254     union
13255     {
13256         __IOM uint16_t FEARL;             /*!< (@ 0x00000118) Flash Processing End Address Register L                    */
13257 
13258         struct
13259         {
13260             __IOM uint16_t FEAR15_0 : 16; /*!< [15..0] End address                                                       */
13261         } FEARL_b;
13262     };
13263     __IM uint16_t RESERVED13;
13264     __IM uint32_t RESERVED14;
13265 
13266     union
13267     {
13268         __IOM uint32_t FEARH;             /*!< (@ 0x00000120) Flash Processing End Address Register H                    */
13269 
13270         struct
13271         {
13272             __IOM uint32_t FEAR20_16 : 5; /*!< [4..0] End address                                                        */
13273             uint32_t                 : 4;
13274             __IOM uint32_t FEAR31_25 : 7; /*!< [15..9] End address                                                       */
13275             uint32_t                 : 16;
13276         } FEARH_b;
13277     };
13278 
13279     union
13280     {
13281         __IOM uint32_t FRESETR;        /*!< (@ 0x00000124) Flash Reset Register                                       */
13282 
13283         struct
13284         {
13285             __IOM uint32_t FRESET : 1; /*!< [0..0] Software Reset of the registers                                    */
13286             uint32_t              : 31;
13287         } FRESETR_b;
13288     };
13289 
13290     union
13291     {
13292         __IM uint32_t FSTATR00;         /*!< (@ 0x00000128) Flash Status Register00                                    */
13293 
13294         struct
13295         {
13296             __IM uint32_t ERERR0   : 1; /*!< [0..0] Erase Error Flag0                                                  */
13297             __IM uint32_t PRGERR0  : 1; /*!< [1..1] Program Error Flag0                                                */
13298             __IM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01                                              */
13299             __IM uint32_t BCERR0   : 1; /*!< [3..3] Blank Check Error Flag0                                            */
13300             __IM uint32_t ILGLERR  : 1; /*!< [4..4] Illegal Command Error Flag                                         */
13301             __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag                              */
13302             uint32_t               : 26;
13303         } FSTATR00_b;
13304     };
13305 
13306     union
13307     {
13308         __IM uint32_t FSTATR1;         /*!< (@ 0x0000012C) Flash Status Register1                                     */
13309 
13310         struct
13311         {
13312             uint32_t            : 1;
13313             __IM uint32_t DRRDY : 1;   /*!< [1..1] Data read request                                                  */
13314             uint32_t            : 4;
13315             __IM uint32_t FRDY  : 1;   /*!< [6..6] End status signal of a sequencer                                   */
13316             __IM uint32_t EXRDY : 1;   /*!< [7..7] End status signal of a Extra programming sequencer                 */
13317             uint32_t            : 24;
13318         } FSTATR1_b;
13319     };
13320 
13321     union
13322     {
13323         __IOM uint32_t FWBL0;          /*!< (@ 0x00000130) Flash Write Buffer Register L0                             */
13324 
13325         struct
13326         {
13327             __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command                               */
13328             uint32_t             : 16;
13329         } FWBL0_b;
13330     };
13331     __IM uint32_t RESERVED15;
13332 
13333     union
13334     {
13335         __IOM uint32_t FWBH0;          /*!< (@ 0x00000138) Flash Write Buffer Register H0                             */
13336 
13337         struct
13338         {
13339             __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command                               */
13340             uint32_t             : 16;
13341         } FWBH0_b;
13342     };
13343 
13344     union
13345     {
13346         __IM uint32_t FSTATR01;        /*!< (@ 0x0000013C) Flash Status Register01                                    */
13347 
13348         struct
13349         {
13350             __IM uint32_t ERERR1  : 1; /*!< [0..0] Erase Error Flag1                                                  */
13351             __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag1                                                */
13352             uint32_t              : 1;
13353             __IM uint32_t BCERR1  : 1; /*!< [3..3] Blank Check Error Flag1                                            */
13354             uint32_t              : 28;
13355         } FSTATR01_b;
13356     };
13357 
13358     union
13359     {
13360         __IOM uint32_t FWBL1;               /*!< (@ 0x00000140) Flash Write Buffer Register L1                             */
13361 
13362         struct
13363         {
13364             __IOM uint32_t WDATA47_32 : 16; /*!< [15..0] Program data of the program command                               */
13365             uint32_t                  : 16;
13366         } FWBL1_b;
13367     };
13368 
13369     union
13370     {
13371         __IOM uint32_t FWBH1;               /*!< (@ 0x00000144) Flash Write Buffer Register H1                             */
13372 
13373         struct
13374         {
13375             __IOM uint32_t WDATA63_48 : 16; /*!< [15..0] Program data of the program command                               */
13376             uint32_t                  : 16;
13377         } FWBH1_b;
13378     };
13379 
13380     union
13381     {
13382         __IM uint32_t FRBL1;               /*!< (@ 0x00000148) Flash Read Buffer Register L1                              */
13383 
13384         struct
13385         {
13386             __IM uint32_t RDATA47_32 : 16; /*!< [15..0] Read data of the consecutive read command                         */
13387             uint32_t                 : 16;
13388         } FRBL1_b;
13389     };
13390 
13391     union
13392     {
13393         __IM uint32_t FRBH1;               /*!< (@ 0x0000014C) Flash Read Buffer Register H1                              */
13394 
13395         struct
13396         {
13397             __IM uint32_t RDATA63_48 : 16; /*!< [15..0] Read data of the consecutive read command                         */
13398             uint32_t                 : 16;
13399         } FRBH1_b;
13400     };
13401     __IM uint32_t RESERVED16[12];
13402 
13403     union
13404     {
13405         __OM uint32_t FPR;             /*!< (@ 0x00000180) Protection Unlock Register                                 */
13406 
13407         struct
13408         {
13409             __OM uint32_t FPR : 8;     /*!< [7..0] Protection Unlock Register                                         */
13410             uint32_t          : 24;
13411         } FPR_b;
13412     };
13413 
13414     union
13415     {
13416         __IM uint32_t FPSR;            /*!< (@ 0x00000184) Protection Unlock Status Register                          */
13417 
13418         struct
13419         {
13420             __IM uint32_t PERR : 1;    /*!< [0..0] Protect Error Flag                                                 */
13421             uint32_t           : 31;
13422         } FPSR_b;
13423     };
13424 
13425     union
13426     {
13427         __IM uint32_t FRBL0;           /*!< (@ 0x00000188) Flash Read Buffer Register L0                              */
13428 
13429         struct
13430         {
13431             __IM uint32_t RDATA : 16;  /*!< [15..0] Read data of the consecutive read command                         */
13432             uint32_t            : 16;
13433         } FRBL0_b;
13434     };
13435     __IM uint32_t RESERVED17;
13436 
13437     union
13438     {
13439         __IM uint32_t FRBH0;           /*!< (@ 0x00000190) Flash Read Buffer Register H0                              */
13440 
13441         struct
13442         {
13443             __IM uint32_t RDATA : 16;  /*!< [15..0] Read data of the consecutive read command                         */
13444             uint32_t            : 16;
13445         } FRBH0_b;
13446     };
13447     __IM uint32_t RESERVED18[11];
13448 
13449     union
13450     {
13451         __IM uint32_t FSCMR;           /*!< (@ 0x000001C0) Flash Start-Up Setting Monitor Register                    */
13452 
13453         struct
13454         {
13455             uint32_t            : 8;
13456             __IM uint32_t SASMF : 1;   /*!< [8..8] Start-up Area Setting Monitor Flag                                 */
13457             uint32_t            : 5;
13458             __IM uint32_t FSPR  : 1;   /*!< [14..14] Access Window Protection Flag                                    */
13459             uint32_t            : 17;
13460         } FSCMR_b;
13461     };
13462     __IM uint32_t RESERVED19;
13463 
13464     union
13465     {
13466         __IM uint32_t FAWSMR;          /*!< (@ 0x000001C8) Flash Access Window Start Address Monitor Register         */
13467 
13468         struct
13469         {
13470             __IM uint32_t FAWS : 12;   /*!< [11..0] Flash Access Window Start Address                                 */
13471             uint32_t           : 20;
13472         } FAWSMR_b;
13473     };
13474     __IM uint32_t RESERVED20;
13475 
13476     union
13477     {
13478         __IM uint32_t FAWEMR;          /*!< (@ 0x000001D0) Flash Access Window End Address Monitor Register           */
13479 
13480         struct
13481         {
13482             __IM uint32_t FAWE : 12;   /*!< [11..0] Flash Access Window End Address                                   */
13483             uint32_t           : 20;
13484         } FAWEMR_b;
13485     };
13486     __IM uint32_t RESERVED21;
13487 
13488     union
13489     {
13490         __IOM uint32_t FISR;           /*!< (@ 0x000001D8) Flash Initial Setting Register                             */
13491 
13492         struct
13493         {
13494             __IOM uint32_t PCKA : 6;   /*!< [5..0] Peripheral Clock Notification                                      */
13495             __IOM uint32_t SAS  : 2;   /*!< [7..6] Temporary boot swap mode                                           */
13496             uint32_t            : 24;
13497         } FISR_b;
13498     };
13499 
13500     union
13501     {
13502         __IOM uint32_t FEXCR;          /*!< (@ 0x000001DC) Flash Extra Area Control Register                          */
13503 
13504         struct
13505         {
13506             __IOM uint32_t CMD  : 3;   /*!< [2..0] Processing Start)                                                  */
13507             uint32_t            : 4;
13508             __IOM uint32_t OPST : 1;   /*!< [7..7] Software Command Setting                                           */
13509             uint32_t            : 24;
13510         } FEXCR_b;
13511     };
13512 
13513     union
13514     {
13515         __IM uint32_t FEAML;           /*!< (@ 0x000001E0) Flash Error Address Monitor Register L                     */
13516 
13517         struct
13518         {
13519             __IM uint32_t FEAM : 16;   /*!< [15..0] Flash Error Address Monitor Register                              */
13520             uint32_t           : 16;
13521         } FEAML_b;
13522     };
13523     __IM uint32_t RESERVED22;
13524 
13525     union
13526     {
13527         __IM uint32_t FEAMH;           /*!< (@ 0x000001E8) Flash Error Address Monitor Register H                     */
13528 
13529         struct
13530         {
13531             __IM uint32_t FEAM : 16;   /*!< [15..0] Flash Error Address Monitor Register                              */
13532             uint32_t           : 16;
13533         } FEAMH_b;
13534     };
13535     __IM uint32_t RESERVED23;
13536 
13537     union
13538     {
13539         __IM uint32_t FSTATR2;           /*!< (@ 0x000001F0) Flash Status Register2                                     */
13540 
13541         struct
13542         {
13543             __IM uint32_t  ERERR    : 1; /*!< [0..0] Erase Error Flag                                                   */
13544             __IM uint32_t  PRGERR1  : 1; /*!< [1..1] Program Error Flag                                                 */
13545             __IOM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01                                              */
13546             __IM uint32_t  BCERR    : 1; /*!< [3..3] Blank Check Error Flag                                             */
13547             __IM uint32_t  ILGLERR  : 1; /*!< [4..4] Illegal Command Error Flag                                         */
13548             __IM uint32_t  EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag                              */
13549             uint32_t                : 26;
13550         } FSTATR2_b;
13551     };
13552     __IM uint32_t  RESERVED24[3951];
13553     __IOM uint16_t FENTRYR_MF4;        /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4                      */
13554     __IOM uint16_t FENTRYR;            /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register                              */
13555     __IM uint32_t  RESERVED25[3];
13556     __IOM uint8_t  FLWAITR;            /*!< (@ 0x00003FC0) Flash Wait Cycle Register                                  */
13557     __IM uint8_t   RESERVED26;
13558     __IM uint16_t  RESERVED27;
13559     __IM uint32_t  RESERVED28;
13560     __IOM uint8_t  PFBER;              /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register                            */
13561     __IM uint8_t   RESERVED29;
13562     __IM uint16_t  RESERVED30;
13563 } R_FACI_LP_Type;                      /*!< Size = 16332 (0x3fcc)                                                     */
13564 
13565 /* =========================================================================================================================== */
13566 /* ================                                        R_CTSUTRIM                                         ================ */
13567 /* =========================================================================================================================== */
13568 
13569 /**
13570  * @brief CTSU Trimming Registers (R_CTSUTRIM)
13571  */
13572 
13573 typedef struct                         /*!< (@ 0x407EC000) R_CTSUTRIM Structure                                       */
13574 {
13575     __IM uint32_t RESERVED[233];
13576 
13577     union
13578     {
13579         __IOM uint32_t CTSUTRIMA;         /*!< (@ 0x000003A4) CTSU Trimming Register A                                   */
13580 
13581         struct
13582         {
13583             __IOM uint32_t RTRIM     : 8; /*!< [7..0] CTSU Reference Resistance Adjustment                               */
13584             __IOM uint32_t DACTRIM   : 8; /*!< [15..8] Linearity Adjustment of Offset Current                            */
13585             __IOM uint32_t SUADJD    : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment                                  */
13586             __IOM uint32_t SUADJTRIM : 8; /*!< [31..24] Coefficient of variation for the reference load resistance
13587                                            *   (120k)                                                                    */
13588         } CTSUTRIMA_b;
13589     };
13590 
13591     union
13592     {
13593         __IOM uint32_t CTSUTRIMB;        /*!< (@ 0x000003A8) CTSU Trimming Register B                                   */
13594 
13595         struct
13596         {
13597             __IOM uint32_t TRESULT0 : 8; /*!< [7..0] Coefficient of variation for the reference load resistance
13598                                           *   (7.5k)                                                                    */
13599             __IOM uint32_t TRESULT1 : 8; /*!< [15..8] Coefficient of variation for the reference load resistance
13600                                           *   (15k)                                                                     */
13601             __IOM uint32_t TRESULT2 : 8; /*!< [23..16] Coefficient of variation for the reference load resistance
13602                                           *   (30k)                                                                     */
13603             __IOM uint32_t TRESULT3 : 8; /*!< [31..24] Coefficient of variation for the reference load resistance
13604                                           *   (60k)                                                                     */
13605         } CTSUTRIMB_b;
13606     };
13607 } R_CTSUTRIM_Type;                       /*!< Size = 940 (0x3ac)                                                        */
13608 
13609 /* =========================================================================================================================== */
13610 /* ================                                         R_FCACHE                                          ================ */
13611 /* =========================================================================================================================== */
13612 
13613 /**
13614  * @brief Flash Memory Cache (R_FCACHE)
13615  */
13616 
13617 typedef struct                         /*!< (@ 0x4001C000) R_FCACHE Structure                                         */
13618 {
13619     __IM uint16_t RESERVED[128];
13620 
13621     union
13622     {
13623         __IOM uint16_t FCACHEE;          /*!< (@ 0x00000100) Flash Cache Enable Register                                */
13624 
13625         struct
13626         {
13627             __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable                                                      */
13628             uint16_t                : 15;
13629         } FCACHEE_b;
13630     };
13631     __IM uint16_t RESERVED1;
13632 
13633     union
13634     {
13635         __IOM uint16_t FCACHEIV;         /*!< (@ 0x00000104) Flash Cache Invalidate Register                            */
13636 
13637         struct
13638         {
13639             __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register                                    */
13640             uint16_t                : 15;
13641         } FCACHEIV_b;
13642     };
13643     __IM uint16_t RESERVED2[11];
13644 
13645     union
13646     {
13647         __IOM uint8_t FLWT;            /*!< (@ 0x0000011C) Flash Wait Cycle Register                                  */
13648 
13649         struct
13650         {
13651             __IOM uint8_t FLWT : 3;    /*!< [2..0] Flash Wait Cycle                                                   */
13652             uint8_t            : 5;
13653         } FLWT_b;
13654     };
13655     __IM uint8_t  RESERVED3;
13656     __IM uint16_t RESERVED4[17];
13657 
13658     union
13659     {
13660         __IOM uint16_t FSAR;             /*!< (@ 0x00000140) Flash Security Attribution Register                        */
13661 
13662         struct
13663         {
13664             __IOM uint16_t FLWTSA   : 1; /*!< [0..0] FLWT Security Attribution                                          */
13665             uint16_t                : 7;
13666             __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution                                        */
13667             uint16_t                : 7;
13668         } FSAR_b;
13669     };
13670 } R_FCACHE_Type;                         /*!< Size = 322 (0x142)                                                        */
13671 
13672 /* =========================================================================================================================== */
13673 /* ================                                          R_GLCDC                                          ================ */
13674 /* =========================================================================================================================== */
13675 
13676 /**
13677  * @brief Graphics LCD Controller (R_GLCDC)
13678  */
13679 
13680 typedef struct                         /*!< (@ 0x400E0000) R_GLCDC Structure                                          */
13681 {
13682     union
13683     {
13684         __IOM uint32_t GR1_CLUT0[256]; /*!< (@ 0x00000000) Color Palette 0 Plane for Graphics 1 Plane                 */
13685 
13686         struct
13687         {
13688             __IOM uint32_t B : 8;      /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane              */
13689             __IOM uint32_t G : 8;      /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane             */
13690             __IOM uint32_t R : 8;      /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane            */
13691             __IOM uint32_t A : 8;      /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics
13692                                         *   m Plane                                                                   */
13693         } GR1_CLUT0_b[256];
13694     };
13695 
13696     union
13697     {
13698         __IOM uint32_t GR1_CLUT1[256]; /*!< (@ 0x00000400) Color Palette 1 Plane for Graphics 1 Plane                 */
13699 
13700         struct
13701         {
13702             __IOM uint32_t B : 8;      /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane              */
13703             __IOM uint32_t G : 8;      /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane             */
13704             __IOM uint32_t R : 8;      /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane            */
13705             __IOM uint32_t A : 8;      /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics
13706                                         *   m Plane                                                                   */
13707         } GR1_CLUT1_b[256];
13708     };
13709 
13710     union
13711     {
13712         __IOM uint32_t GR2_CLUT0[256]; /*!< (@ 0x00000800) Color Palette 0 Plane for Graphics 2 Plane                 */
13713 
13714         struct
13715         {
13716             __IOM uint32_t B : 8;      /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane              */
13717             __IOM uint32_t G : 8;      /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane             */
13718             __IOM uint32_t R : 8;      /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane            */
13719             __IOM uint32_t A : 8;      /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics
13720                                         *   m Plane                                                                   */
13721         } GR2_CLUT0_b[256];
13722     };
13723 
13724     union
13725     {
13726         __IOM uint32_t GR2_CLUT1[256]; /*!< (@ 0x00000C00) Color Palette 1 Plane for Graphics 2 Plane                 */
13727 
13728         struct
13729         {
13730             __IOM uint32_t B : 8;      /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane              */
13731             __IOM uint32_t G : 8;      /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane             */
13732             __IOM uint32_t R : 8;      /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane            */
13733             __IOM uint32_t A : 8;      /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics
13734                                         *   m Plane                                                                   */
13735         } GR2_CLUT1_b[256];
13736     };
13737     __IOM R_GLCDC_BG_Type     BG;      /*!< (@ 0x00001000) Background Registers                                       */
13738     __IM uint32_t             RESERVED[57];
13739     __IOM R_GLCDC_GR_Type     GR[2];   /*!< (@ 0x00001100) Layer Registers                                            */
13740     __IOM R_GLCDC_GAM_Type    GAM[3];  /*!< (@ 0x00001300) Gamma Settings                                             */
13741     __IOM R_GLCDC_OUT_Type    OUT;     /*!< (@ 0x000013C0) Output Control Registers                                   */
13742     __IM uint32_t             RESERVED1[6];
13743     __IOM R_GLCDC_TCON_Type   TCON;    /*!< (@ 0x00001400) Timing Control Registers                                   */
13744     __IM uint32_t             RESERVED2[5];
13745     __IOM R_GLCDC_SYSCNT_Type SYSCNT;  /*!< (@ 0x00001440) GLCDC System Control Registers                             */
13746 } R_GLCDC_Type;                        /*!< Size = 5204 (0x1454)                                                      */
13747 
13748 /* =========================================================================================================================== */
13749 /* ================                                          R_GPT0                                           ================ */
13750 /* =========================================================================================================================== */
13751 
13752 /**
13753  * @brief General PWM Timer (R_GPT0)
13754  */
13755 
13756 typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure                                           */
13757 {
13758     union
13759     {
13760         __IOM uint32_t GTWP;           /*!< (@ 0x00000000) General PWM Timer Write-Protection Register                */
13761 
13762         struct
13763         {
13764             __IOM uint32_t WP    : 1;  /*!< [0..0] Register Write Disable                                             */
13765             __IOM uint32_t STRWP : 1;  /*!< [1..1] GTSTR.CSTRT Bit Write Disable                                      */
13766             __IOM uint32_t STPWP : 1;  /*!< [2..2] GTSTP.CSTOP Bit Write Disable                                      */
13767             __IOM uint32_t CLRWP : 1;  /*!< [3..3] GTCLR.CCLR Bit Write Disable                                       */
13768             __IOM uint32_t CMNWP : 1;  /*!< [4..4] Common Register Write Disabled                                     */
13769             uint32_t             : 3;
13770             __OM uint32_t PRKEY  : 8;  /*!< [15..8] GTWP Key Code                                                     */
13771             uint32_t             : 16;
13772         } GTWP_b;
13773     };
13774 
13775     union
13776     {
13777         __IOM uint32_t GTSTR;           /*!< (@ 0x00000004) General PWM Timer Software Start Register                  */
13778 
13779         struct
13780         {
13781             __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
13782                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
13783                                          *   means counter running.                                                    */
13784             __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
13785                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
13786                                          *   means counter running.                                                    */
13787             __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
13788                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
13789                                          *   means counter running.                                                    */
13790             __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
13791                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
13792                                          *   means counter running.                                                    */
13793             __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
13794                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
13795                                          *   means counter running.                                                    */
13796             __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
13797                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
13798                                          *   means counter running.                                                    */
13799             __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
13800                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
13801                                          *   means counter running.                                                    */
13802             __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
13803                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
13804                                          *   means counter running.                                                    */
13805             __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
13806                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
13807                                          *   means counter running.                                                    */
13808             __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
13809                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
13810                                          *   means counter running.                                                    */
13811             __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
13812                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
13813                                          *   means counter running.                                                    */
13814             __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
13815                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
13816                                          *   means counter running.                                                    */
13817             __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
13818                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
13819                                          *   means counter running.                                                    */
13820             __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
13821                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
13822                                          *   means counter running.                                                    */
13823             uint32_t : 18;
13824         } GTSTR_b;
13825     };
13826 
13827     union
13828     {
13829         __IOM uint32_t GTSTP;           /*!< (@ 0x00000008) General PWM Timer Software Stop Register                   */
13830 
13831         struct
13832         {
13833             __IOM uint32_t CSTOP0 : 1;  /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's
13834                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
13835                                          *   1 means counter stop.                                                     */
13836             __IOM uint32_t CSTOP1 : 1;  /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's
13837                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
13838                                          *   1 means counter stop.                                                     */
13839             __IOM uint32_t CSTOP2 : 1;  /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's
13840                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
13841                                          *   1 means counter stop.                                                     */
13842             __IOM uint32_t CSTOP3 : 1;  /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's
13843                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
13844                                          *   1 means counter stop.                                                     */
13845             __IOM uint32_t CSTOP4 : 1;  /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's
13846                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
13847                                          *   1 means counter stop.                                                     */
13848             __IOM uint32_t CSTOP5 : 1;  /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's
13849                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
13850                                          *   1 means counter stop.                                                     */
13851             __IOM uint32_t CSTOP6 : 1;  /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's
13852                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
13853                                          *   1 means counter stop.                                                     */
13854             __IOM uint32_t CSTOP7 : 1;  /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's
13855                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
13856                                          *   1 means counter stop.                                                     */
13857             __IOM uint32_t CSTOP8 : 1;  /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's
13858                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
13859                                          *   1 means counter stop.                                                     */
13860             __IOM uint32_t CSTOP9 : 1;  /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's
13861                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
13862                                          *   1 means counter stop.                                                     */
13863             __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's
13864                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
13865                                          *   1 means counter stop.                                                     */
13866             __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's
13867                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
13868                                          *   1 means counter stop.                                                     */
13869             __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's
13870                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
13871                                          *   1 means counter stop.                                                     */
13872             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
13873                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
13874                                          *   1 means counter stop.                                                     */
13875             uint32_t : 18;
13876         } GTSTP_b;
13877     };
13878 
13879     union
13880     {
13881         __OM uint32_t GTCLR;           /*!< (@ 0x0000000C) General PWM Timer Software Clear Register                  */
13882 
13883         struct
13884         {
13885             __OM uint32_t CCLR0  : 1;  /*!< [0..0] Channel GTCNT Count Clear                                          */
13886             __OM uint32_t CCLR1  : 1;  /*!< [1..1] Channel GTCNT Count Clear                                          */
13887             __OM uint32_t CCLR2  : 1;  /*!< [2..2] Channel GTCNT Count Clear                                          */
13888             __OM uint32_t CCLR3  : 1;  /*!< [3..3] Channel GTCNT Count Clear                                          */
13889             __OM uint32_t CCLR4  : 1;  /*!< [4..4] Channel GTCNT Count Clear                                          */
13890             __OM uint32_t CCLR5  : 1;  /*!< [5..5] Channel GTCNT Count Clear                                          */
13891             __OM uint32_t CCLR6  : 1;  /*!< [6..6] Channel GTCNT Count Clear                                          */
13892             __OM uint32_t CCLR7  : 1;  /*!< [7..7] Channel GTCNT Count Clear                                          */
13893             __OM uint32_t CCLR8  : 1;  /*!< [8..8] Channel GTCNT Count Clear                                          */
13894             __OM uint32_t CCLR9  : 1;  /*!< [9..9] Channel GTCNT Count Clear                                          */
13895             __OM uint32_t CCLR10 : 1;  /*!< [10..10] Channel GTCNT Count Clear                                        */
13896             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
13897             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
13898             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
13899             uint32_t             : 18;
13900         } GTCLR_b;
13901     };
13902 
13903     union
13904     {
13905         __IOM uint32_t GTSSR;            /*!< (@ 0x00000010) General PWM Timer Start Source Select Register             */
13906 
13907         struct
13908         {
13909             __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable                */
13910             __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable               */
13911             __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable                */
13912             __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable               */
13913             __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable                */
13914             __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable               */
13915             __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable                */
13916             __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable               */
13917             __IOM uint32_t SSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
13918                                           *   Counter Start Enable                                                      */
13919             __IOM uint32_t SSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
13920                                           *   Counter Start Enable                                                      */
13921             __IOM uint32_t SSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
13922                                           *   Counter Start Enable                                                      */
13923             __IOM uint32_t SSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
13924                                           *   Counter Start Enable                                                      */
13925             __IOM uint32_t SSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
13926                                           *   Counter Start Enable                                                      */
13927             __IOM uint32_t SSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
13928                                           *   Counter Start Enable                                                      */
13929             __IOM uint32_t SSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
13930                                           *   Counter Start Enable                                                      */
13931             __IOM uint32_t SSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
13932                                           *   Counter Start Enable                                                      */
13933             __IOM uint32_t SSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Start Enable                        */
13934             __IOM uint32_t SSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Start Enable                        */
13935             __IOM uint32_t SSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Start Enable                        */
13936             __IOM uint32_t SSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Start Enable                        */
13937             __IOM uint32_t SSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Start Enable                        */
13938             __IOM uint32_t SSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Start Enable                        */
13939             __IOM uint32_t SSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Start Enable                        */
13940             __IOM uint32_t SSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Start Enable                        */
13941             uint32_t              : 7;
13942             __IOM uint32_t CSTRT  : 1;   /*!< [31..31] Software Source Counter Start Enable                             */
13943         } GTSSR_b;
13944     };
13945 
13946     union
13947     {
13948         __IOM uint32_t GTPSR;            /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register              */
13949 
13950         struct
13951         {
13952             __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable                 */
13953             __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable                */
13954             __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable                 */
13955             __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable                */
13956             __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable                 */
13957             __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable                */
13958             __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable                 */
13959             __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable                */
13960             __IOM uint32_t PSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
13961                                           *   Counter Stop Enable                                                       */
13962             __IOM uint32_t PSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
13963                                           *   Counter Stop Enable                                                       */
13964             __IOM uint32_t PSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
13965                                           *   Counter Stop Enable                                                       */
13966             __IOM uint32_t PSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
13967                                           *   Counter Stop Enable                                                       */
13968             __IOM uint32_t PSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
13969                                           *   Counter Stop Enable                                                       */
13970             __IOM uint32_t PSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
13971                                           *   Counter Stop Enable                                                       */
13972             __IOM uint32_t PSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
13973                                           *   Counter Stop Enable                                                       */
13974             __IOM uint32_t PSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
13975                                           *   Counter Stop Enable                                                       */
13976             __IOM uint32_t PSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable                        */
13977             __IOM uint32_t PSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable                        */
13978             __IOM uint32_t PSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable                        */
13979             __IOM uint32_t PSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable                        */
13980             __IOM uint32_t PSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable                        */
13981             __IOM uint32_t PSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable                        */
13982             __IOM uint32_t PSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable                        */
13983             __IOM uint32_t PSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable                        */
13984             uint32_t              : 7;
13985             __IOM uint32_t CSTOP  : 1;   /*!< [31..31] Software Source Counter Stop Enable                              */
13986         } GTPSR_b;
13987     };
13988 
13989     union
13990     {
13991         __IOM uint32_t GTCSR;            /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register             */
13992 
13993         struct
13994         {
13995             __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable                */
13996             __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable               */
13997             __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable                */
13998             __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable               */
13999             __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable                */
14000             __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable               */
14001             __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable                */
14002             __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable               */
14003             __IOM uint32_t CSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
14004                                           *   Counter Clear Enable                                                      */
14005             __IOM uint32_t CSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
14006                                           *   Counter Clear Enable                                                      */
14007             __IOM uint32_t CSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
14008                                           *   Counter Clear Enable                                                      */
14009             __IOM uint32_t CSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
14010                                           *   Counter Clear Enable                                                      */
14011             __IOM uint32_t CSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
14012                                           *   Counter Clear Enable                                                      */
14013             __IOM uint32_t CSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
14014                                           *   Counter Clear Enable                                                      */
14015             __IOM uint32_t CSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
14016                                           *   Counter Clear Enable                                                      */
14017             __IOM uint32_t CSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
14018                                           *   Counter Clear Enable                                                      */
14019             __IOM uint32_t CSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable                       */
14020             __IOM uint32_t CSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable                       */
14021             __IOM uint32_t CSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable                       */
14022             __IOM uint32_t CSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable                       */
14023             __IOM uint32_t CSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable                       */
14024             __IOM uint32_t CSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable                       */
14025             __IOM uint32_t CSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable                       */
14026             __IOM uint32_t CSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable                       */
14027             __IOM uint32_t CSCMSC : 3;   /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing
14028                                           *   Source Counter Clear Enable.                                              */
14029             __IOM uint32_t CP1CCE : 1;   /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear
14030                                           *   Enable (This bit is only available in GPT324 to GPT329.
14031                                           *   In GPT320 to GPT323, this bit is read as 0. The write value
14032                                           *   should be 0.)                                                             */
14033             uint32_t            : 3;
14034             __IOM uint32_t CCLR : 1;     /*!< [31..31] Software Source Counter Clear Enable                             */
14035         } GTCSR_b;
14036     };
14037 
14038     union
14039     {
14040         __IOM uint32_t GTUPSR;           /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register          */
14041 
14042         struct
14043         {
14044             __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable             */
14045             __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable            */
14046             __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable             */
14047             __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable            */
14048             __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable             */
14049             __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable            */
14050             __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable             */
14051             __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable            */
14052             __IOM uint32_t USCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
14053                                           *   Counter Count Up Enable                                                   */
14054             __IOM uint32_t USCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
14055                                           *   Counter Count Up Enable                                                   */
14056             __IOM uint32_t USCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
14057                                           *   Counter Count Up Enable                                                   */
14058             __IOM uint32_t USCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
14059                                           *   Counter Count Up Enable                                                   */
14060             __IOM uint32_t USCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
14061                                           *   Counter Count Up Enable                                                   */
14062             __IOM uint32_t USCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
14063                                           *   Counter Count Up Enable                                                   */
14064             __IOM uint32_t USCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
14065                                           *   Counter Count Up Enable                                                   */
14066             __IOM uint32_t USCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
14067                                           *   Counter Count Up Enable                                                   */
14068             __IOM uint32_t USELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable                     */
14069             __IOM uint32_t USELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable                     */
14070             __IOM uint32_t USELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable                     */
14071             __IOM uint32_t USELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable                     */
14072             __IOM uint32_t USELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable                     */
14073             __IOM uint32_t USELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable                     */
14074             __IOM uint32_t USELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable                     */
14075             __IOM uint32_t USELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable                     */
14076             __IOM uint32_t USILVL : 4;   /*!< [27..24] External Input Level Source Count-Up Enable                      */
14077             uint32_t              : 4;
14078         } GTUPSR_b;
14079     };
14080 
14081     union
14082     {
14083         __IOM uint32_t GTDNSR;           /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register        */
14084 
14085         struct
14086         {
14087             __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable           */
14088             __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable          */
14089             __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable           */
14090             __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable          */
14091             __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable           */
14092             __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable          */
14093             __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable           */
14094             __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable          */
14095             __IOM uint32_t DSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
14096                                           *   Counter Count Down Enable                                                 */
14097             __IOM uint32_t DSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
14098                                           *   Counter Count Down Enable                                                 */
14099             __IOM uint32_t DSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
14100                                           *   Counter Count Down Enable                                                 */
14101             __IOM uint32_t DSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
14102                                           *   Counter Count Down Enable                                                 */
14103             __IOM uint32_t DSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
14104                                           *   Counter Count Down Enable                                                 */
14105             __IOM uint32_t DSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
14106                                           *   Counter Count Down Enable                                                 */
14107             __IOM uint32_t DSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
14108                                           *   Counter Count Down Enable                                                 */
14109             __IOM uint32_t DSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
14110                                           *   Counter Count Down Enable                                                 */
14111             __IOM uint32_t DSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable                   */
14112             __IOM uint32_t DSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable                   */
14113             __IOM uint32_t DSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable                   */
14114             __IOM uint32_t DSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable                   */
14115             __IOM uint32_t DSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable                   */
14116             __IOM uint32_t DSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable                   */
14117             __IOM uint32_t DSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable                   */
14118             __IOM uint32_t DSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable                   */
14119             __IOM uint32_t DSILVL : 4;   /*!< [27..24] External Input Level Source Count-Down Enable                    */
14120             uint32_t              : 4;
14121         } GTDNSR_b;
14122     };
14123 
14124     union
14125     {
14126         __IOM uint32_t GTICASR;          /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select
14127                                           *                  Register A                                                 */
14128 
14129         struct
14130         {
14131             __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
14132             __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture
14133                                           *   Enable                                                                    */
14134             __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
14135             __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture
14136                                           *   Enable                                                                    */
14137             __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
14138             __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture
14139                                           *   Enable                                                                    */
14140             __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
14141             __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture
14142                                           *   Enable                                                                    */
14143             __IOM uint32_t ASCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
14144                                           *   GTCCRA Input Capture Enable                                               */
14145             __IOM uint32_t ASCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
14146                                           *   GTCCRA Input Capture Enable                                               */
14147             __IOM uint32_t ASCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
14148                                           *   GTCCRA Input Capture Enable                                               */
14149             __IOM uint32_t ASCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
14150                                           *   GTCCRA Input Capture Enable                                               */
14151             __IOM uint32_t ASCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
14152                                           *   GTCCRA Input Capture Enable                                               */
14153             __IOM uint32_t ASCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
14154                                           *   GTCCRA Input Capture Enable                                               */
14155             __IOM uint32_t ASCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
14156                                           *   GTCCRA Input Capture Enable                                               */
14157             __IOM uint32_t ASCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
14158                                           *   GTCCRA Input Capture Enable                                               */
14159             __IOM uint32_t ASELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
14160             __IOM uint32_t ASELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
14161             __IOM uint32_t ASELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
14162             __IOM uint32_t ASELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
14163             __IOM uint32_t ASELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
14164             __IOM uint32_t ASELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
14165             __IOM uint32_t ASELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
14166             __IOM uint32_t ASELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
14167             uint32_t              : 8;
14168         } GTICASR_b;
14169     };
14170 
14171     union
14172     {
14173         __IOM uint32_t GTICBSR;          /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select
14174                                           *                  Register B                                                 */
14175 
14176         struct
14177         {
14178             __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
14179             __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture
14180                                           *   Enable                                                                    */
14181             __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
14182             __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture
14183                                           *   Enable                                                                    */
14184             __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
14185             __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture
14186                                           *   Enable                                                                    */
14187             __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
14188             __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture
14189                                           *   Enable                                                                    */
14190             __IOM uint32_t BSCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
14191                                           *   GTCCRB Input Capture Enable                                               */
14192             __IOM uint32_t BSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
14193                                           *   GTCCRB Input Capture Enable                                               */
14194             __IOM uint32_t BSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
14195                                           *   GTCCRB Input Capture Enable                                               */
14196             __IOM uint32_t BSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
14197                                           *   GTCCRB Input Capture Enable                                               */
14198             __IOM uint32_t BSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
14199                                           *   GTCCRB Input Capture Enable                                               */
14200             __IOM uint32_t BSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
14201                                           *   GTCCRB Input Capture Enable                                               */
14202             __IOM uint32_t BSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
14203                                           *   GTCCRB Input Capture Enable                                               */
14204             __IOM uint32_t BSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
14205                                           *   GTCCRB Input Capture Enable                                               */
14206             __IOM uint32_t BSELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
14207             __IOM uint32_t BSELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
14208             __IOM uint32_t BSELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
14209             __IOM uint32_t BSELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
14210             __IOM uint32_t BSELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
14211             __IOM uint32_t BSELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
14212             __IOM uint32_t BSELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
14213             __IOM uint32_t BSELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
14214             uint32_t              : 8;
14215         } GTICBSR_b;
14216     };
14217 
14218     union
14219     {
14220         __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
14221 
14222         struct
14223         {
14224             __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
14225             uint32_t            : 15;
14226             __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
14227             uint32_t            : 4;
14228             __IOM uint32_t TPCS : 4;   /*!< [26..23] Timer Prescaler Select                                           */
14229             uint32_t            : 5;
14230         } GTCR_b;
14231     };
14232 
14233     union
14234     {
14235         __IOM uint32_t GTUDDTYC;       /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting
14236                                         *                  Register                                                   */
14237 
14238         struct
14239         {
14240             __IOM uint32_t UD     : 1; /*!< [0..0] Count Direction Setting                                            */
14241             __IOM uint32_t UDF    : 1; /*!< [1..1] Forcible Count Direction Setting                                   */
14242             uint32_t              : 14;
14243             __IOM uint32_t OADTY  : 2; /*!< [17..16] GTIOCA Output Duty Setting                                       */
14244             __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting                              */
14245             __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100
14246                                         *   percent Duty Setting                                                      */
14247             uint32_t              : 4;
14248             __IOM uint32_t OBDTY  : 2; /*!< [25..24] GTIOCB Output Duty Setting                                       */
14249             __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting                              */
14250             __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100
14251                                         *   percent Duty Setting                                                      */
14252             uint32_t : 4;
14253         } GTUDDTYC_b;
14254     };
14255 
14256     union
14257     {
14258         __IOM uint32_t GTIOR;          /*!< (@ 0x00000034) General PWM Timer I/O Control Register                     */
14259 
14260         struct
14261         {
14262             __IOM uint32_t GTIOA  : 5; /*!< [4..0] GTIOCA Pin Function Select                                         */
14263             __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous
14264                                         *   Clear Disable.(This bit is only available in GPT324 to
14265                                         *   GPT329. In GPT320 to GPT323, this bit is read as 0. The
14266                                         *   write value should be 0.)                                                 */
14267             __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop                  */
14268             __IOM uint32_t OAHLD  : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count                  */
14269             __IOM uint32_t OAE    : 1; /*!< [8..8] GTIOCA Pin Output Enable                                           */
14270             __IOM uint32_t OADF   : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting                                  */
14271             __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This
14272                                         *   bit is only available in GPT324 to GPT329. In GPT320 to
14273                                         *   GPT323, this bit is read as 0. The write value should be
14274                                         *   0.)                                                                       */
14275             __IOM uint32_t PSYE   : 1; /*!< [12..12] PWM Synchronous output Enable                                    */
14276             __IOM uint32_t NFAEN  : 1; /*!< [13..13] Noise Filter A Enable                                            */
14277             __IOM uint32_t NFCSA  : 2; /*!< [15..14] Noise Filter A Sampling Clock Select                             */
14278             __IOM uint32_t GTIOB  : 5; /*!< [20..16] GTIOCB Pin Function Select                                       */
14279             uint32_t              : 1;
14280             __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop                */
14281             __IOM uint32_t OBHLD  : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count                */
14282             __IOM uint32_t OBE    : 1; /*!< [24..24] GTIOCB Pin Output Enable                                         */
14283             __IOM uint32_t OBDF   : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting                                 */
14284             __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This
14285                                         *   bit is only available in GPT324 to GPT329. In GPT320 to
14286                                         *   GPT323, this bit is read as 0. The write value should be
14287                                         *   0.)                                                                       */
14288             uint32_t             : 1;
14289             __IOM uint32_t NFBEN : 1;  /*!< [29..29] Noise Filter B Enable                                            */
14290             __IOM uint32_t NFCSB : 2;  /*!< [31..30] Noise Filter B Sampling Clock Select                             */
14291         } GTIOR_b;
14292     };
14293 
14294     union
14295     {
14296         __IOM uint32_t GTINTAD;        /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register        */
14297 
14298         struct
14299         {
14300             uint32_t               : 24;
14301             __IOM uint32_t GRP     : 2; /*!< [25..24] Output Disable Source Select                                     */
14302             uint32_t               : 2;
14303             __IOM uint32_t GRPDTE  : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
14304             __IOM uint32_t GRPABH  : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable               */
14305             __IOM uint32_t GRPABL  : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
14306             __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
14307         } GTINTAD_b;
14308     };
14309 
14310     union
14311     {
14312         __IOM uint32_t GTST;            /*!< (@ 0x0000003C) General PWM Timer Status Register                          */
14313 
14314         struct
14315         {
14316             __IOM uint32_t TCFA  : 1;   /*!< [0..0] Input Capture/Compare Match Flag A                                 */
14317             __IOM uint32_t TCFB  : 1;   /*!< [1..1] Input Capture/Compare Match Flag B                                 */
14318             __IOM uint32_t TCFC  : 1;   /*!< [2..2] Input Compare Match Flag C                                         */
14319             __IOM uint32_t TCFD  : 1;   /*!< [3..3] Input Compare Match Flag D                                         */
14320             __IOM uint32_t TCFE  : 1;   /*!< [4..4] Input Compare Match Flag E                                         */
14321             __IOM uint32_t TCFF  : 1;   /*!< [5..5] Input Compare Match Flag F                                         */
14322             __IOM uint32_t TCFPO : 1;   /*!< [6..6] Overflow Flag                                                      */
14323             __IOM uint32_t TCFPU : 1;   /*!< [7..7] Underflow Flag                                                     */
14324             __IM uint32_t  ITCNT : 3;   /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter
14325                                          *   for counting the number of times a timer interrupt has
14326                                          *   been skipped.)                                                            */
14327             uint32_t               : 4;
14328             __IM uint32_t  TUCF    : 1; /*!< [15..15] Count Direction Flag                                             */
14329             __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start
14330                                          *   Request Interrupt Enable                                                  */
14331             __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor
14332                                          *   Start Request Flag                                                        */
14333             __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start
14334                                          *   Request Flag                                                              */
14335             __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor
14336                                          *   Start Request Flag                                                        */
14337             uint32_t             : 4;
14338             __IM uint32_t ODF    : 1;   /*!< [24..24] Output Disable Flag                                              */
14339             uint32_t             : 3;
14340             __IM uint32_t  DTEF  : 1;   /*!< [28..28] Dead Time Error Flag                                             */
14341             __IM uint32_t  OABHF : 1;   /*!< [29..29] Same Time Output Level High Disable Request Enable               */
14342             __IM uint32_t  OABLF : 1;   /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
14343             __IOM uint32_t PCF   : 1;   /*!< [31..31] Period Count Function Finish Flag                                */
14344         } GTST_b;
14345     };
14346 
14347     union
14348     {
14349         __IOM uint32_t GTBER;          /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
14350 
14351         struct
14352         {
14353             __IOM uint32_t BD0    : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
14354             __IOM uint32_t BD1    : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
14355             __IOM uint32_t BD2    : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
14356             __IOM uint32_t BD3    : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
14357             uint32_t              : 12;
14358             __IOM uint32_t CCRA   : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
14359             __IOM uint32_t CCRB   : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
14360             __IOM uint32_t PR     : 2; /*!< [21..20] GTPR Buffer Operation                                            */
14361             __OM uint32_t  CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
14362                                         *   is read as 0.                                                             */
14363             uint32_t             : 1;
14364             __IOM uint32_t ADTTA : 2;  /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
14365                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
14366                                         *   at an underflow (in down-counting) or overflow (in up-counting)
14367                                         *   is performed.                                                             */
14368             __IOM uint32_t ADTDA : 1;  /*!< [26..26] GTADTRA Double Buffer Operation                                  */
14369             uint32_t             : 1;
14370             __IOM uint32_t ADTTB : 2;  /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
14371                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
14372                                         *   at an underflow (in down-counting) or overflow (in up-counting)
14373                                         *   is performed.                                                             */
14374             __IOM uint32_t ADTDB : 1;  /*!< [30..30] GTADTRB Double Buffer Operation                                  */
14375             uint32_t             : 1;
14376         } GTBER_b;
14377     };
14378 
14379     union
14380     {
14381         __IOM uint32_t GTITC;          /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter
14382                                         *                  Start Request Skipping Setting Register                    */
14383 
14384         struct
14385         {
14386             __IOM uint32_t ITLA  : 1;  /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link                  */
14387             __IOM uint32_t ITLB  : 1;  /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link                  */
14388             __IOM uint32_t ITLC  : 1;  /*!< [2..2] GTCCRC Compare Match Interrupt Link                                */
14389             __IOM uint32_t ITLD  : 1;  /*!< [3..3] GTCCRD Compare Match Interrupt Link                                */
14390             __IOM uint32_t ITLE  : 1;  /*!< [4..4] GTCCRE Compare Match Interrupt Link                                */
14391             __IOM uint32_t ITLF  : 1;  /*!< [5..5] GTCCRF Compare Match Interrupt Link                                */
14392             __IOM uint32_t IVTC  : 2;  /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select                 */
14393             __IOM uint32_t IVTT  : 3;  /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select                   */
14394             uint32_t             : 1;
14395             __IOM uint32_t ADTAL : 1;  /*!< [12..12] GTADTRA A/D Converter Start Request Link                         */
14396             uint32_t             : 1;
14397             __IOM uint32_t ADTBL : 1;  /*!< [14..14] GTADTRB A/D Converter Start Request Link                         */
14398             uint32_t             : 17;
14399         } GTITC_b;
14400     };
14401 
14402     union
14403     {
14404         __IOM uint32_t GTCNT;          /*!< (@ 0x00000048) General PWM Timer Counter                                  */
14405 
14406         struct
14407         {
14408             __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter                                                           */
14409         } GTCNT_b;
14410     };
14411 
14412     union
14413     {
14414         __IOM uint32_t GTCCR[6];       /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register                 */
14415 
14416         struct
14417         {
14418             __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A                                        */
14419         } GTCCR_b[6];
14420     };
14421 
14422     union
14423     {
14424         __IOM uint32_t GTPR;           /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register                   */
14425 
14426         struct
14427         {
14428             __IOM uint32_t GTPR : 32;  /*!< [31..0] Cycle Setting Register                                            */
14429         } GTPR_b;
14430     };
14431 
14432     union
14433     {
14434         __IOM uint32_t GTPBR;          /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register            */
14435 
14436         struct
14437         {
14438             __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register                                     */
14439         } GTPBR_b;
14440     };
14441 
14442     union
14443     {
14444         __IOM uint32_t GTPDBR;          /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer
14445                                          *                  Register                                                   */
14446 
14447         struct
14448         {
14449             __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register                              */
14450         } GTPDBR_b;
14451     };
14452 
14453     union
14454     {
14455         __IOM uint32_t GTADTRA;          /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A              */
14456 
14457         struct
14458         {
14459             __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A                     */
14460         } GTADTRA_b;
14461     };
14462 
14463     union
14464     {
14465         __IOM uint32_t GTADTBRA;          /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register
14466                                            *                  A                                                          */
14467 
14468         struct
14469         {
14470             __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A              */
14471         } GTADTBRA_b;
14472     };
14473 
14474     union
14475     {
14476         __IOM uint32_t GTADTDBRA;          /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer
14477                                             *                  Register A                                                 */
14478 
14479         struct
14480         {
14481             __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
14482                                             *   A                                                                         */
14483         } GTADTDBRA_b;
14484     };
14485 
14486     union
14487     {
14488         __IOM uint32_t GTADTRB;          /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B              */
14489 
14490         struct
14491         {
14492             __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B                     */
14493         } GTADTRB_b;
14494     };
14495 
14496     union
14497     {
14498         __IOM uint32_t GTADTBRB;          /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register
14499                                            *                  B                                                          */
14500 
14501         struct
14502         {
14503             __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B              */
14504         } GTADTBRB_b;
14505     };
14506 
14507     union
14508     {
14509         __IOM uint32_t GTADTDBRB;          /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer
14510                                             *                  Register B                                                 */
14511 
14512         struct
14513         {
14514             __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
14515                                             *   B                                                                         */
14516         } GTADTDBRB_b;
14517     };
14518 
14519     union
14520     {
14521         __IOM uint32_t GTDTCR;         /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register               */
14522 
14523         struct
14524         {
14525             __IOM uint32_t TDE   : 1;  /*!< [0..0] Negative-Phase Waveform Setting                                    */
14526             uint32_t             : 3;
14527             __IOM uint32_t TDBUE : 1;  /*!< [4..4] GTDVU Buffer Operation Enable                                      */
14528             __IOM uint32_t TDBDE : 1;  /*!< [5..5] GTDVD Buffer Operation Enable                                      */
14529             uint32_t             : 2;
14530             __IOM uint32_t TDFER : 1;  /*!< [8..8] GTDVD Setting                                                      */
14531             uint32_t             : 23;
14532         } GTDTCR_b;
14533     };
14534 
14535     union
14536     {
14537         __IOM uint32_t GTDVU;          /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U               */
14538 
14539         struct
14540         {
14541             __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U                                        */
14542         } GTDVU_b;
14543     };
14544 
14545     union
14546     {
14547         __IOM uint32_t GTDVD;          /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D               */
14548 
14549         struct
14550         {
14551             __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D                                        */
14552         } GTDVD_b;
14553     };
14554 
14555     union
14556     {
14557         __IOM uint32_t GTDBU;          /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U              */
14558 
14559         struct
14560         {
14561             __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U                                       */
14562         } GTDBU_b;
14563     };
14564 
14565     union
14566     {
14567         __IOM uint32_t GTDBD;          /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D              */
14568 
14569         struct
14570         {
14571             __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D                                       */
14572         } GTDBD_b;
14573     };
14574 
14575     union
14576     {
14577         __IM uint32_t GTSOS;           /*!< (@ 0x0000009C) General PWM Timer Output Protection Function
14578                                         *                  Status Register                                            */
14579 
14580         struct
14581         {
14582             __IM uint32_t SOS : 2;     /*!< [1..0] Output Protection Function Status                                  */
14583             uint32_t          : 30;
14584         } GTSOS_b;
14585     };
14586 
14587     union
14588     {
14589         __IOM uint32_t GTSOTR;         /*!< (@ 0x000000A0) General PWM Timer Output Protection Function
14590                                         *                  Temporary Release Register                                 */
14591 
14592         struct
14593         {
14594             __IOM uint32_t SOTR : 1;   /*!< [0..0] Output Protection Function Temporary Release                       */
14595             uint32_t            : 31;
14596         } GTSOTR_b;
14597     };
14598     __IM uint32_t RESERVED[5];
14599 
14600     union
14601     {
14602         __IOM uint32_t GTICLF;           /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation
14603                                           *                  Function Setting Register                                  */
14604 
14605         struct
14606         {
14607             __IOM uint32_t ICLFA    : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select                   */
14608             uint32_t                : 1;
14609             __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select                                      */
14610             uint32_t                : 6;
14611             __IOM uint32_t ICLFB    : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select                 */
14612             uint32_t                : 1;
14613             __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select                                    */
14614             uint32_t                : 6;
14615         } GTICLF_b;
14616     };
14617 
14618     union
14619     {
14620         __IOM uint32_t GTPC;           /*!< (@ 0x000000BC) General PWM Timer Period Count Register                    */
14621 
14622         struct
14623         {
14624             __IOM uint32_t PCEN : 1;   /*!< [0..0] Period Count Function Enable                                       */
14625             uint32_t            : 7;
14626             __IOM uint32_t ASTP : 1;   /*!< [8..8] Automatic Stop Function Enable                                     */
14627             uint32_t            : 7;
14628             __IOM uint32_t PCNT : 12;  /*!< [27..16] Period Counter                                                   */
14629             uint32_t            : 4;
14630         } GTPC_b;
14631     };
14632     __IM uint32_t RESERVED1[4];
14633 
14634     union
14635     {
14636         __IOM uint32_t GTSECSR;         /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous
14637                                          *                  Control Channel Select Register                            */
14638 
14639         struct
14640         {
14641             __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel
14642                                          *   Select                                                                    */
14643             __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel
14644                                          *   Select                                                                    */
14645             __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel
14646                                          *   Select                                                                    */
14647             __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel
14648                                          *   Select                                                                    */
14649             __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel
14650                                          *   Select                                                                    */
14651             __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel
14652                                          *   Select                                                                    */
14653             __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel
14654                                          *   Select                                                                    */
14655             __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel
14656                                          *   Select                                                                    */
14657             __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel
14658                                          *   Select                                                                    */
14659             __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel
14660                                          *   Select                                                                    */
14661             uint32_t : 22;
14662         } GTSECSR_b;
14663     };
14664 
14665     union
14666     {
14667         __IOM uint32_t GTSECR;         /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous
14668                                         *                  Control Register                                           */
14669 
14670         struct
14671         {
14672             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
14673             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
14674             uint32_t             : 6;
14675             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
14676             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
14677             uint32_t             : 6;
14678             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
14679             uint32_t             : 7;
14680             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
14681             uint32_t             : 7;
14682         } GTSECR_b;
14683     };
14684 } R_GPT0_Type;                         /*!< Size = 216 (0xd8)                                                         */
14685 
14686 /* =========================================================================================================================== */
14687 /* ================                                        R_GPT_GTCLK                                        ================ */
14688 /* =========================================================================================================================== */
14689 
14690 /**
14691  * @brief GTCLK (R_GPT_GTCLK)
14692  */
14693 
14694 typedef struct                         /*!< (@ 0x40169B00) R_GPT_GTCLK Structure                                      */
14695 {
14696     union
14697     {
14698         __IOM uint32_t GTCLKCR;        /*!< (@ 0x00000000) General PWM Timer Clock Control Register                   */
14699 
14700         struct
14701         {
14702             __IOM uint32_t BPEN : 1;   /*!< [0..0] Synchronization Circuit Bypass Enable                              */
14703             uint32_t            : 31;
14704         } GTCLKCR_b;
14705     };
14706 } R_GPT_GTCLK_Type;                    /*!< Size = 4 (0x4)                                                            */
14707 
14708 /* =========================================================================================================================== */
14709 /* ================                                         R_GPT_ODC                                         ================ */
14710 /* =========================================================================================================================== */
14711 
14712 /**
14713  * @brief PWM Delay Generation Circuit (R_GPT_ODC)
14714  */
14715 
14716 typedef struct                         /*!< (@ 0x4007B000) R_GPT_ODC Structure                                        */
14717 {
14718     union
14719     {
14720         __IOM uint16_t GTDLYCR1;       /*!< (@ 0x00000000) PWM Output Delay Control Register1                         */
14721 
14722         struct
14723         {
14724             __IOM uint16_t DLLEN  : 1; /*!< [0..0] DLL Operation Enable                                               */
14725             __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset                                 */
14726             uint16_t              : 6;
14727             __IOM uint16_t FRANGE : 1; /*!< [8..8] GPT core clock Frequency Range                                     */
14728             uint16_t              : 7;
14729         } GTDLYCR1_b;
14730     };
14731 
14732     union
14733     {
14734         __IOM uint16_t GTDLYCR2;         /*!< (@ 0x00000002) PWM Output Delay Control Register2                         */
14735 
14736         struct
14737         {
14738             __IOM uint16_t DLYBS0   : 1; /*!< [0..0] PWM Delay Generation Circuit bypass                                */
14739             __IOM uint16_t DLYBS1   : 1; /*!< [1..1] PWM Delay Generation Circuit bypass                                */
14740             __IOM uint16_t DLYBS2   : 1; /*!< [2..2] PWM Delay Generation Circuit bypass                                */
14741             __IOM uint16_t DLYBS3   : 1; /*!< [3..3] PWM Delay Generation Circuit bypass                                */
14742             uint16_t                : 4;
14743             __IOM uint16_t DLYEN0   : 1; /*!< [8..8] PWM Delay Generation Circuit enable                                */
14744             __IOM uint16_t DLYEN1   : 1; /*!< [9..9] PWM Delay Generation Circuit enable                                */
14745             __IOM uint16_t DLYEN2   : 1; /*!< [10..10] PWM Delay Generation Circuit enable                              */
14746             __IOM uint16_t DLYEN3   : 1; /*!< [11..11] PWM Delay Generation Circuit enable                              */
14747             __IOM uint16_t DLYDENB0 : 1; /*!< [12..12] PWM Delay Generation Circuit Disenable for GTIOCB                */
14748             uint16_t                : 3;
14749         } GTDLYCR2_b;
14750     };
14751     __IM uint16_t               RESERVED[10];
14752     __IOM R_GPT_ODC_GTDLYR_Type GTDLYR[4]; /*!< (@ 0x00000018) PWM DELAY RISING                                           */
14753     __IOM R_GPT_ODC_GTDLYR_Type GTDLYF[4]; /*!< (@ 0x00000028) PWM DELAY FALLING                                          */
14754 } R_GPT_ODC_Type;                          /*!< Size = 56 (0x38)                                                          */
14755 
14756 /* =========================================================================================================================== */
14757 /* ================                                         R_GPT_OPS                                         ================ */
14758 /* =========================================================================================================================== */
14759 
14760 /**
14761  * @brief Output Phase Switching for GPT (R_GPT_OPS)
14762  */
14763 
14764 typedef struct                         /*!< (@ 0x40078FF0) R_GPT_OPS Structure                                        */
14765 {
14766     union
14767     {
14768         __IOM uint32_t OPSCR;          /*!< (@ 0x00000000) Output Phase Switching Control Register                    */
14769 
14770         struct
14771         {
14772             __IOM uint32_t UF : 1;     /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase
14773                                         *   by the software settings.This bit setting is valid when
14774                                         *   the OPSCR.FB bit = 1.                                                     */
14775             __IOM uint32_t VF : 1;     /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase
14776                                         *   by the software settings.This bit setting is valid when
14777                                         *   the OPSCR.FB bit = 1.                                                     */
14778             __IOM uint32_t WF : 1;     /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase
14779                                         *   by the software settings.This bit setting is valid when
14780                                         *   the OPSCR.FB bit = 1.                                                     */
14781             uint32_t        : 1;
14782             __IM uint32_t U : 1;       /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the
14783                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
14784                                         *   e settings (UF/VF/WF)                                                     */
14785             __IM uint32_t V : 1;       /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the
14786                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
14787                                         *   e settings (UF/VF/WF)                                                     */
14788             __IM uint32_t W : 1;       /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the
14789                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
14790                                         *   e settings (UF/VF/WF)                                                     */
14791             uint32_t          : 1;
14792             __IOM uint32_t EN : 1;     /*!< [8..8] Enable-Phase Output Control                                        */
14793             uint32_t          : 7;
14794             __IOM uint32_t FB : 1;     /*!< [16..16] External Feedback Signal EnableThis bit selects the
14795                                         *   input phase from the software settings and external input.                */
14796             __IOM uint32_t P     : 1;  /*!< [17..17] Positive-Phase Output (P) Control                                */
14797             __IOM uint32_t N     : 1;  /*!< [18..18] Negative-Phase Output (N) Control                                */
14798             __IOM uint32_t INV   : 1;  /*!< [19..19] Invert-Phase Output Control                                      */
14799             __IOM uint32_t RV    : 1;  /*!< [20..20] Output phase rotation direction reversal                         */
14800             __IOM uint32_t ALIGN : 1;  /*!< [21..21] Input phase alignment                                            */
14801             uint32_t             : 2;
14802             __IOM uint32_t GRP   : 2;  /*!< [25..24] Output disabled source selection                                 */
14803             __IOM uint32_t GODF  : 1;  /*!< [26..26] Group output disable function                                    */
14804             uint32_t             : 2;
14805             __IOM uint32_t NFEN  : 1;  /*!< [29..29] External Input Noise Filter Enable                               */
14806             __IOM uint32_t NFCS  : 2;  /*!< [31..30] External Input Noise Filter Clock selectionNoise filter
14807                                         *   sampling clock setting of the external input.                             */
14808         } OPSCR_b;
14809     };
14810 } R_GPT_OPS_Type;                      /*!< Size = 4 (0x4)                                                            */
14811 
14812 /* =========================================================================================================================== */
14813 /* ================                                        R_GPT_POEG0                                        ================ */
14814 /* =========================================================================================================================== */
14815 
14816 /**
14817  * @brief Port Output Enable for GPT (R_GPT_POEG0)
14818  */
14819 
14820 typedef struct                         /*!< (@ 0x40042000) R_GPT_POEG0 Structure                                      */
14821 {
14822     union
14823     {
14824         __IOM uint32_t POEGG;          /*!< (@ 0x00000000) POEG Group Setting Register                                */
14825 
14826         struct
14827         {
14828             __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
14829             __IOM uint32_t IOCF  : 1;  /*!< [1..1] Real Time Overcurrent Detection Flag                               */
14830             __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
14831             __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
14832             __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection EnableNote: Can be modified only
14833                                         *   once after a reset.                                                       */
14834             __IOM uint32_t IOCE : 1;   /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified
14835                                         *   only once after a reset.                                                  */
14836             __IOM uint32_t OSTPE : 1;  /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified
14837                                         *   only once after a reset.                                                  */
14838             uint32_t             : 1;
14839             __IOM uint32_t CDRE0 : 1;  /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified
14840                                         *   only once after a reset.                                                  */
14841             __IOM uint32_t CDRE1 : 1;  /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified
14842                                         *   only once after a reset.                                                  */
14843             __IOM uint32_t CDRE2 : 1;  /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified
14844                                         *   only once after a reset.                                                  */
14845             __IOM uint32_t CDRE3 : 1;  /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified
14846                                         *   only once after a reset.                                                  */
14847             __IOM uint32_t CDRE4 : 1;  /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified
14848                                         *   only once after a reset.                                                  */
14849             __IOM uint32_t CDRE5 : 1;  /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified
14850                                         *   only once after a reset.                                                  */
14851             uint32_t            : 2;
14852             __IM uint32_t ST    : 1;   /*!< [16..16] GTETRG Input Status Flag                                         */
14853             uint32_t            : 11;
14854             __IOM uint32_t INV  : 1;   /*!< [28..28] GTETRG Input Reverse                                             */
14855             __IOM uint32_t NFEN : 1;   /*!< [29..29] Noise Filter Enable                                              */
14856             __IOM uint32_t NFCS : 2;   /*!< [31..30] Noise Filter Clock Select                                        */
14857         } POEGG_b;
14858     };
14859 } R_GPT_POEG0_Type;                    /*!< Size = 4 (0x4)                                                            */
14860 
14861 /* =========================================================================================================================== */
14862 /* ================                                           R_ICU                                           ================ */
14863 /* =========================================================================================================================== */
14864 
14865 /**
14866  * @brief Interrupt Controller Unit (R_ICU)
14867  */
14868 
14869 typedef struct                         /*!< (@ 0x40006000) R_ICU Structure                                            */
14870 {
14871     union
14872     {
14873         __IOM uint8_t IRQCR[16];       /*!< (@ 0x00000000) IRQ Control Register [0..15]                               */
14874 
14875         struct
14876         {
14877             __IOM uint8_t IRQMD   : 2; /*!< [1..0] IRQ Detection Sense Select                                         */
14878             uint8_t               : 2;
14879             __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select                           */
14880             uint8_t               : 1;
14881             __IOM uint8_t FLTEN   : 1; /*!< [7..7] IRQ Digital Filter Enable                                          */
14882         } IRQCR_b[16];
14883     };
14884     __IM uint32_t RESERVED[60];
14885 
14886     union
14887     {
14888         __IOM uint8_t NMICR;            /*!< (@ 0x00000100) NMI Pin Interrupt Control Register                         */
14889 
14890         struct
14891         {
14892             __IOM uint8_t NMIMD    : 1; /*!< [0..0] NMI Detection Set                                                  */
14893             uint8_t                : 3;
14894             __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select                           */
14895             uint8_t                : 1;
14896             __IOM uint8_t NFLTEN   : 1; /*!< [7..7] NMI Digital Filter Enable                                          */
14897         } NMICR_b;
14898     };
14899     __IM uint8_t  RESERVED1;
14900     __IM uint16_t RESERVED2;
14901     __IM uint32_t RESERVED3[7];
14902 
14903     union
14904     {
14905         __IOM uint16_t NMIER;           /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register                     */
14906 
14907         struct
14908         {
14909             __IOM uint16_t IWDTEN  : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable                      */
14910             __IOM uint16_t WDTEN   : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable                       */
14911             __IOM uint16_t LVD1EN  : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable                              */
14912             __IOM uint16_t LVD2EN  : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable                              */
14913             __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable                                     */
14914             uint16_t               : 1;
14915             __IOM uint16_t OSTEN   : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable                        */
14916             __IOM uint16_t NMIEN   : 1; /*!< [7..7] NMI Pin Interrupt Enable                                           */
14917             __IOM uint16_t RPEEN   : 1; /*!< [8..8] RAM Parity Error Interrupt Enable                                  */
14918             __IOM uint16_t RECCEN  : 1; /*!< [9..9] RAM ECC Error Interrupt Enable                                     */
14919             __IOM uint16_t BUSSEN  : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable                             */
14920             __IOM uint16_t BUSMEN  : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable                            */
14921             __IOM uint16_t SPEEN   : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable                       */
14922             __IOM uint16_t TZFEN   : 1; /*!< [13..13] TZFEN                                                            */
14923             uint16_t               : 1;
14924             __IOM uint16_t CPEEN   : 1; /*!< [15..15] CPEEN                                                            */
14925         } NMIER_b;
14926     };
14927     __IM uint16_t RESERVED4;
14928     __IM uint32_t RESERVED5[3];
14929 
14930     union
14931     {
14932         __IOM uint16_t NMICLR;          /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register               */
14933 
14934         struct
14935         {
14936             __OM uint16_t IWDTCLR  : 1; /*!< [0..0] IWDT Clear                                                         */
14937             __OM uint16_t WDTCLR   : 1; /*!< [1..1] WDT Clear                                                          */
14938             __OM uint16_t LVD1CLR  : 1; /*!< [2..2] LVD1 Clear                                                         */
14939             __OM uint16_t LVD2CLR  : 1; /*!< [3..3] LVD2 Clear                                                         */
14940             __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear                                                        */
14941             uint16_t               : 1;
14942             __OM uint16_t  OSTCLR  : 1; /*!< [6..6] OST Clear                                                          */
14943             __OM uint16_t  NMICLR  : 1; /*!< [7..7] NMI Clear                                                          */
14944             __OM uint16_t  RPECLR  : 1; /*!< [8..8] SRAM Parity Error Clear                                            */
14945             __OM uint16_t  RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear                                               */
14946             __OM uint16_t  BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear                                            */
14947             __OM uint16_t  BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear                                           */
14948             __OM uint16_t  SPECLR  : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear                        */
14949             __IOM uint16_t TZFCLR  : 1; /*!< [13..13] TZFCLR                                                           */
14950             uint16_t               : 1;
14951             __IOM uint16_t CPECLR  : 1; /*!< [15..15] CPECLR                                                           */
14952         } NMICLR_b;
14953     };
14954     __IM uint16_t RESERVED6;
14955     __IM uint32_t RESERVED7[3];
14956 
14957     union
14958     {
14959         __IM uint16_t NMISR;           /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register                     */
14960 
14961         struct
14962         {
14963             __IM uint16_t IWDTST  : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag                           */
14964             __IM uint16_t WDTST   : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag                            */
14965             __IM uint16_t LVD1ST  : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag                         */
14966             __IM uint16_t LVD2ST  : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag                         */
14967             __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag                                */
14968             uint16_t              : 1;
14969             __IM uint16_t OSTST   : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag                   */
14970             __IM uint16_t NMIST   : 1; /*!< [7..7] NMI Status Flag                                                    */
14971             __IM uint16_t RPEST   : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag                             */
14972             __IM uint16_t RECCST  : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag                                */
14973             __IM uint16_t BUSSST  : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag                        */
14974             __IM uint16_t BUSMST  : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag                       */
14975             __IM uint16_t SPEST   : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag                  */
14976             __IM uint16_t TZFST   : 1; /*!< [13..13] TZFST                                                            */
14977             uint16_t              : 1;
14978             __IM uint16_t CPEST   : 1; /*!< [15..15] CPEST                                                            */
14979         } NMISR_b;
14980     };
14981     __IM uint16_t RESERVED8;
14982     __IM uint32_t RESERVED9[23];
14983 
14984     union
14985     {
14986         __IOM uint32_t WUPEN;                /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register                          */
14987 
14988         struct
14989         {
14990             __IOM uint32_t IRQWUPEN0    : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable                           */
14991             __IOM uint32_t IRQWUPEN1    : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable                           */
14992             __IOM uint32_t IRQWUPEN2    : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable                           */
14993             __IOM uint32_t IRQWUPEN3    : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable                           */
14994             __IOM uint32_t IRQWUPEN4    : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable                           */
14995             __IOM uint32_t IRQWUPEN5    : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable                           */
14996             __IOM uint32_t IRQWUPEN6    : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable                           */
14997             __IOM uint32_t IRQWUPEN7    : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable                           */
14998             __IOM uint32_t IRQWUPEN8    : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable                           */
14999             __IOM uint32_t IRQWUPEN9    : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable                           */
15000             __IOM uint32_t IRQWUPEN10   : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable                         */
15001             __IOM uint32_t IRQWUPEN11   : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable                         */
15002             __IOM uint32_t IRQWUPEN12   : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable                         */
15003             __IOM uint32_t IRQWUPEN13   : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable                         */
15004             __IOM uint32_t IRQWUPEN14   : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable                         */
15005             __IOM uint32_t IRQWUPEN15   : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable                         */
15006             __IOM uint32_t IWDTWUPEN    : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable                        */
15007             __IOM uint32_t KEYWUPEN     : 1; /*!< [17..17] Key interrupt S/W standby returns enable                         */
15008             __IOM uint32_t LVD1WUPEN    : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable                        */
15009             __IOM uint32_t LVD2WUPEN    : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable                        */
15010             __IOM uint32_t VBATTWUPEN   : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable               */
15011             uint32_t                    : 1;
15012             __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit                 */
15013             __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable                     */
15014             __IOM uint32_t RTCALMWUPEN  : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable                   */
15015             __IOM uint32_t RTCPRDWUPEN  : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable                  */
15016             __IOM uint32_t USBHSWUPEN   : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit                   */
15017             __IOM uint32_t USBFSWUPEN   : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable                       */
15018             __IOM uint32_t AGT1UDWUPEN  : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable              */
15019             __IOM uint32_t AGT1CAWUPEN  : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns
15020                                               *   enable                                                                    */
15021             __IOM uint32_t AGT1CBWUPEN : 1;  /*!< [30..30] AGT1 compare match B interrupt S/W standby returns
15022                                               *   enable                                                                    */
15023             __IOM uint32_t IIC0WUPEN : 1;    /*!< [31..31] IIC0 address match interrupt S/W standby returns enable          */
15024         } WUPEN_b;
15025     };
15026 
15027     union
15028     {
15029         __IOM uint32_t WUPEN1;              /*!< (@ 0x000001A4) Wake Up interrupt enable register 1                        */
15030 
15031         struct
15032         {
15033             __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit            */
15034             __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable
15035                                              *   bit                                                                       */
15036             __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable
15037                                              *   bit                                                                       */
15038             uint32_t : 29;
15039         } WUPEN1_b;
15040     };
15041     __IM uint32_t RESERVED10[6];
15042 
15043     union
15044     {
15045         __IOM uint8_t IELEN;            /*!< (@ 0x000001C0) ICU event Enable Register                                  */
15046 
15047         struct
15048         {
15049             __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit
15050                                          *   = 1)                                                                      */
15051             __IOM uint8_t IELEN : 1;    /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when
15052                                          *   LPOPTEN bit = 1)                                                          */
15053             uint8_t : 6;
15054         } IELEN_b;
15055     };
15056     __IM uint8_t  RESERVED11;
15057     __IM uint16_t RESERVED12;
15058     __IM uint32_t RESERVED13[15];
15059 
15060     union
15061     {
15062         __IOM uint16_t SELSR0;         /*!< (@ 0x00000200) Snooze Event Link Setting Register                         */
15063 
15064         struct
15065         {
15066             __IOM uint16_t SELS : 9;   /*!< [8..0] SYS Event Link Select                                              */
15067             uint16_t            : 7;
15068         } SELSR0_b;
15069     };
15070     __IM uint16_t RESERVED14;
15071     __IM uint32_t RESERVED15[31];
15072 
15073     union
15074     {
15075         __IOM uint32_t DELSR[8];       /*!< (@ 0x00000280) DMAC Event Link Setting Register                           */
15076 
15077         struct
15078         {
15079             __IOM uint32_t DELS : 9;   /*!< [8..0] Event selection to DMAC Start request                              */
15080             uint32_t            : 7;
15081             __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
15082                                         *   IR flag is prohibited.                                                    */
15083             uint32_t : 15;
15084         } DELSR_b[8];
15085     };
15086     __IM uint32_t RESERVED16[24];
15087 
15088     union
15089     {
15090         __IOM uint32_t IELSR[96];      /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95]                    */
15091 
15092         struct
15093         {
15094             __IOM uint32_t IELS : 9;   /*!< [8..0] ICU Event selection to NVICSet the number for the event
15095                                         *   signal to be linked .                                                     */
15096             uint32_t            : 7;
15097             __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag                                            */
15098             uint32_t            : 7;
15099             __IOM uint32_t DTCE : 1;   /*!< [24..24] DTC Activation Enable                                            */
15100             uint32_t            : 7;
15101         } IELSR_b[96];
15102     };
15103 } R_ICU_Type;                          /*!< Size = 1152 (0x480)                                                       */
15104 
15105 /* =========================================================================================================================== */
15106 /* ================                                          R_IIC0                                           ================ */
15107 /* =========================================================================================================================== */
15108 
15109 /**
15110  * @brief I2C Bus Interface (R_IIC0)
15111  */
15112 
15113 typedef struct                         /*!< (@ 0x40053000) R_IIC0 Structure                                           */
15114 {
15115     union
15116     {
15117         __IOM uint8_t ICCR1;           /*!< (@ 0x00000000) I2C Bus Control Register 1                                 */
15118 
15119         struct
15120         {
15121             __IM uint8_t  SDAI   : 1;  /*!< [0..0] SDA Line Monitor                                                   */
15122             __IM uint8_t  SCLI   : 1;  /*!< [1..1] SCL Line Monitor                                                   */
15123             __IOM uint8_t SDAO   : 1;  /*!< [2..2] SDA Output Control/Monitor                                         */
15124             __IOM uint8_t SCLO   : 1;  /*!< [3..3] SCL Output Control/Monitor                                         */
15125             __IOM uint8_t SOWP   : 1;  /*!< [4..4] SCLO/SDAO Write Protect                                            */
15126             __IOM uint8_t CLO    : 1;  /*!< [5..5] Extra SCL Clock Cycle Output                                       */
15127             __IOM uint8_t IICRST : 1;  /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset
15128                                         *   is initiated using the IICRST bit for a bus hang-up occurred
15129                                         *   during communication with the master device in slave mode,
15130                                         *   the states may become different between the slave device
15131                                         *   and the master device (due to the difference in the bit
15132                                         *   counter information).                                                     */
15133             __IOM uint8_t ICE : 1;     /*!< [7..7] I2C Bus Interface Enable                                           */
15134         } ICCR1_b;
15135     };
15136 
15137     union
15138     {
15139         __IOM uint8_t ICCR2;           /*!< (@ 0x00000001) I2C Bus Control Register 2                                 */
15140 
15141         struct
15142         {
15143             uint8_t          : 1;
15144             __IOM uint8_t ST : 1;      /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start
15145                                         *   condition issuance request) when the BBSY flag is set to
15146                                         *   0 (bus free state).                                                       */
15147             __IOM uint8_t RS : 1;      /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the
15148                                         *   RS bit to 1 while issuing a stop condition.                               */
15149             __IOM uint8_t SP : 1;      /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP
15150                                         *   bit is not possible while the setting of the BBSY flag
15151                                         *   is 0 (bus free state).Note: Do not set the SP bit to 1
15152                                         *   while a restart condition is being issued.                                */
15153             uint8_t            : 1;
15154             __IOM uint8_t TRS  : 1;    /*!< [5..5] Transmit/Receive Mode                                              */
15155             __IOM uint8_t MST  : 1;    /*!< [6..6] Master/Slave Mode                                                  */
15156             __IM uint8_t  BBSY : 1;    /*!< [7..7] Bus Busy Detection Flag                                            */
15157         } ICCR2_b;
15158     };
15159 
15160     union
15161     {
15162         __IOM uint8_t ICMR1;           /*!< (@ 0x00000002) I2C Bus Mode Register 1                                    */
15163 
15164         struct
15165         {
15166             __IOM uint8_t BC   : 3;    /*!< [2..0] Bit Counter                                                        */
15167             __OM uint8_t  BCWP : 1;    /*!< [3..3] BC Write Protect(This bit is read as 1.)                           */
15168             __IOM uint8_t CKS  : 3;    /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB
15169                                         *   / 2^CKS )                                                                 */
15170             __IOM uint8_t MTWP : 1;    /*!< [7..7] MST/TRS Write Protect                                              */
15171         } ICMR1_b;
15172     };
15173 
15174     union
15175     {
15176         __IOM uint8_t ICMR2;           /*!< (@ 0x00000003) I2C Bus Mode Register 2                                    */
15177 
15178         struct
15179         {
15180             __IOM uint8_t TMOS : 1;    /*!< [0..0] Timeout Detection Time Select                                      */
15181             __IOM uint8_t TMOL : 1;    /*!< [1..1] Timeout L Count Control                                            */
15182             __IOM uint8_t TMOH : 1;    /*!< [2..2] Timeout H Count Control                                            */
15183             uint8_t            : 1;
15184             __IOM uint8_t SDDL : 3;    /*!< [6..4] SDA Output Delay Counter                                           */
15185             __IOM uint8_t DLCS : 1;    /*!< [7..7] SDA Output Delay Clock Source Select                               */
15186         } ICMR2_b;
15187     };
15188 
15189     union
15190     {
15191         __IOM uint8_t ICMR3;           /*!< (@ 0x00000004) I2C Bus Mode Register 3                                    */
15192 
15193         struct
15194         {
15195             __IOM uint8_t NF    : 2;   /*!< [1..0] Noise Filter Stage Selection                                       */
15196             __IM uint8_t  ACKBR : 1;   /*!< [2..2] Receive Acknowledge                                                */
15197             __IOM uint8_t ACKBT : 1;   /*!< [3..3] Transmit Acknowledge                                               */
15198             __IOM uint8_t ACKWP : 1;   /*!< [4..4] ACKBT Write Protect                                                */
15199             __IOM uint8_t RDRFS : 1;   /*!< [5..5] RDRF Flag Set Timing Selection                                     */
15200             __IOM uint8_t WAIT  : 1;   /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read,
15201                                         *   be sure to read the ICDRR beforehand.                                     */
15202             __IOM uint8_t SMBS : 1;    /*!< [7..7] SMBus/I2C Bus Selection                                            */
15203         } ICMR3_b;
15204     };
15205 
15206     union
15207     {
15208         __IOM uint8_t ICFER;           /*!< (@ 0x00000005) I2C Bus Function Enable Register                           */
15209 
15210         struct
15211         {
15212             __IOM uint8_t TMOE  : 1;   /*!< [0..0] Timeout Function Enable                                            */
15213             __IOM uint8_t MALE  : 1;   /*!< [1..1] Master Arbitration-Lost Detection Enable                           */
15214             __IOM uint8_t NALE  : 1;   /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable                */
15215             __IOM uint8_t SALE  : 1;   /*!< [3..3] Slave Arbitration-Lost Detection Enable                            */
15216             __IOM uint8_t NACKE : 1;   /*!< [4..4] NACK Reception Transfer Suspension Enable                          */
15217             __IOM uint8_t NFE   : 1;   /*!< [5..5] Digital Noise Filter Circuit Enable                                */
15218             __IOM uint8_t SCLE  : 1;   /*!< [6..6] SCL Synchronous Circuit Enable                                     */
15219             __IOM uint8_t FMPE  : 1;   /*!< [7..7] Fast-mode Plus Enable                                              */
15220         } ICFER_b;
15221     };
15222 
15223     union
15224     {
15225         __IOM uint8_t ICSER;           /*!< (@ 0x00000006) I2C Bus Status Enable Register                             */
15226 
15227         struct
15228         {
15229             __IOM uint8_t SAR0E : 1;   /*!< [0..0] Slave Address Register 0 Enable                                    */
15230             __IOM uint8_t SAR1E : 1;   /*!< [1..1] Slave Address Register 1 Enable                                    */
15231             __IOM uint8_t SAR2E : 1;   /*!< [2..2] Slave Address Register 2 Enable                                    */
15232             __IOM uint8_t GCAE  : 1;   /*!< [3..3] General Call Address Enable                                        */
15233             uint8_t             : 1;
15234             __IOM uint8_t DIDE  : 1;   /*!< [5..5] Device-ID Address Detection Enable                                 */
15235             uint8_t             : 1;
15236             __IOM uint8_t HOAE  : 1;   /*!< [7..7] Host Address Enable                                                */
15237         } ICSER_b;
15238     };
15239 
15240     union
15241     {
15242         __IOM uint8_t ICIER;           /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register                          */
15243 
15244         struct
15245         {
15246             __IOM uint8_t TMOIE : 1;   /*!< [0..0] Timeout Interrupt Request Enable                                   */
15247             __IOM uint8_t ALIE  : 1;   /*!< [1..1] Arbitration-Lost Interrupt Request Enable                          */
15248             __IOM uint8_t STIE  : 1;   /*!< [2..2] Start Condition Detection Interrupt Request Enable                 */
15249             __IOM uint8_t SPIE  : 1;   /*!< [3..3] Stop Condition Detection Interrupt Request Enable                  */
15250             __IOM uint8_t NAKIE : 1;   /*!< [4..4] NACK Reception Interrupt Request Enable                            */
15251             __IOM uint8_t RIE   : 1;   /*!< [5..5] Receive Data Full Interrupt Request Enable                         */
15252             __IOM uint8_t TEIE  : 1;   /*!< [6..6] Transmit End Interrupt Request Enable                              */
15253             __IOM uint8_t TIE   : 1;   /*!< [7..7] Transmit Data Empty Interrupt Request Enable                       */
15254         } ICIER_b;
15255     };
15256 
15257     union
15258     {
15259         __IOM uint8_t ICSR1;           /*!< (@ 0x00000008) I2C Bus Status Register 1                                  */
15260 
15261         struct
15262         {
15263             __IOM uint8_t AAS0 : 1;    /*!< [0..0] Slave Address 0 Detection Flag                                     */
15264             __IOM uint8_t AAS1 : 1;    /*!< [1..1] Slave Address 1 Detection Flag                                     */
15265             __IOM uint8_t AAS2 : 1;    /*!< [2..2] Slave Address 2 Detection Flag                                     */
15266             __IOM uint8_t GCA  : 1;    /*!< [3..3] General Call Address Detection Flag                                */
15267             uint8_t            : 1;
15268             __IOM uint8_t DID  : 1;    /*!< [5..5] Device-ID Address Detection Flag                                   */
15269             uint8_t            : 1;
15270             __IOM uint8_t HOA  : 1;    /*!< [7..7] Host Address Detection Flag                                        */
15271         } ICSR1_b;
15272     };
15273 
15274     union
15275     {
15276         __IOM uint8_t ICSR2;           /*!< (@ 0x00000009) I2C Bus Status Register 2                                  */
15277 
15278         struct
15279         {
15280             __IOM uint8_t TMOF  : 1;   /*!< [0..0] Timeout Detection Flag                                             */
15281             __IOM uint8_t AL    : 1;   /*!< [1..1] Arbitration-Lost Flag                                              */
15282             __IOM uint8_t START : 1;   /*!< [2..2] Start Condition Detection Flag                                     */
15283             __IOM uint8_t STOP  : 1;   /*!< [3..3] Stop Condition Detection Flag                                      */
15284             __IOM uint8_t NACKF : 1;   /*!< [4..4] NACK Detection Flag                                                */
15285             __IOM uint8_t RDRF  : 1;   /*!< [5..5] Receive Data Full Flag                                             */
15286             __IOM uint8_t TEND  : 1;   /*!< [6..6] Transmit End Flag                                                  */
15287             __IM uint8_t  TDRE  : 1;   /*!< [7..7] Transmit Data Empty Flag                                           */
15288         } ICSR2_b;
15289     };
15290     __IOM R_IIC0_SAR_Type SAR[3];      /*!< (@ 0x0000000A) Slave Address Registers                                    */
15291 
15292     union
15293     {
15294         __IOM uint8_t ICBRL;           /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register                        */
15295 
15296         struct
15297         {
15298             __IOM uint8_t BRL : 5;     /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock)           */
15299             uint8_t           : 3;
15300         } ICBRL_b;
15301     };
15302 
15303     union
15304     {
15305         __IOM uint8_t ICBRH;           /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register                       */
15306 
15307         struct
15308         {
15309             __IOM uint8_t BRH : 5;     /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock)         */
15310             uint8_t           : 3;
15311         } ICBRH_b;
15312     };
15313 
15314     union
15315     {
15316         __IOM uint8_t ICDRT;           /*!< (@ 0x00000012) I2C Bus Transmit Data Register                             */
15317 
15318         struct
15319         {
15320             __IOM uint8_t ICDRT : 8;   /*!< [7..0] 8-bit read-write register that stores transmit data.               */
15321         } ICDRT_b;
15322     };
15323 
15324     union
15325     {
15326         __IM uint8_t ICDRR;            /*!< (@ 0x00000013) I2C Bus Receive Data Register                              */
15327 
15328         struct
15329         {
15330             __IM uint8_t ICDRR : 8;    /*!< [7..0] 8-bit register that stores the received data                       */
15331         } ICDRR_b;
15332     };
15333     __IM uint8_t RESERVED[2];
15334 
15335     union
15336     {
15337         __IOM uint8_t ICWUR;           /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register                              */
15338 
15339         struct
15340         {
15341             __IOM uint8_t WUAFA : 1;   /*!< [0..0] Wakeup Analog Filter Additional Selection                          */
15342             uint8_t             : 3;
15343             __IOM uint8_t WUACK : 1;   /*!< [4..4] ACK bit for Wakeup Mode                                            */
15344             __IOM uint8_t WUF   : 1;   /*!< [5..5] Wakeup Event Occurrence Flag                                       */
15345             __IOM uint8_t WUIE  : 1;   /*!< [6..6] Wakeup Interrupt Request Enable                                    */
15346             __IOM uint8_t WUE   : 1;   /*!< [7..7] Wakeup Function Enable                                             */
15347         } ICWUR_b;
15348     };
15349 
15350     union
15351     {
15352         __IOM uint8_t ICWUR2;          /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2                            */
15353 
15354         struct
15355         {
15356             __IM uint8_t WUSEN  : 1;   /*!< [0..0] Wake-up Function Synchronous Enable                                */
15357             __IM uint8_t WUASYF : 1;   /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag                */
15358             __IM uint8_t WUSYF  : 1;   /*!< [2..2] Wake-up Function Synchronous Operation Status Flag                 */
15359             uint8_t             : 5;
15360         } ICWUR2_b;
15361     };
15362 } R_IIC0_Type;                         /*!< Size = 24 (0x18)                                                          */
15363 
15364 /* =========================================================================================================================== */
15365 /* ================                                          R_IIRFA                                          ================ */
15366 /* =========================================================================================================================== */
15367 
15368 /**
15369  * @brief IIR Filter Accelerator (R_IIRFA)
15370  */
15371 
15372 typedef struct                         /*!< (@ 0x40020000) R_IIRFA Structure                                          */
15373 {
15374     union
15375     {
15376         __IM uint32_t IIRCPRCS;        /*!< (@ 0x00000000) Channel Processing Status Register                         */
15377 
15378         struct
15379         {
15380             __IM uint32_t CPRCS : 16;  /*!< [15..0] Channel processing status bit                                     */
15381             uint32_t            : 16;
15382         } IIRCPRCS_b;
15383     };
15384 
15385     union
15386     {
15387         __IM uint32_t IIRCPRCFF;       /*!< (@ 0x00000004) Channel Processing Completion Flag Register                */
15388 
15389         struct
15390         {
15391             __IM uint32_t CPRCFF : 16; /*!< [15..0] Channel processing completion flag                                */
15392             uint32_t             : 16;
15393         } IIRCPRCFF_b;
15394     };
15395 
15396     union
15397     {
15398         __IM uint32_t IIRORDYF;        /*!< (@ 0x00000008) Output Data Preparation Completion Flag Register           */
15399 
15400         struct
15401         {
15402             __IM uint32_t ORDYF : 16;  /*!< [15..0] Output data preparation completion flag                           */
15403             uint32_t            : 16;
15404         } IIRORDYF_b;
15405     };
15406 
15407     union
15408     {
15409         __IM uint32_t IIRCERRF;        /*!< (@ 0x0000000C) Operation Error Flag Register                              */
15410 
15411         struct
15412         {
15413             __IM uint32_t CERRF : 16;  /*!< [15..0] Operation error flag                                              */
15414             uint32_t            : 16;
15415         } IIRCERRF_b;
15416     };
15417 
15418     union
15419     {
15420         __IOM uint32_t IIROPCNT;       /*!< (@ 0x00000010) Operation Control Register                                 */
15421 
15422         struct
15423         {
15424             __IOM uint32_t RND : 3;    /*!< [2..0] Setting for the rounding mode for addition and multiplication      */
15425             uint32_t           : 29;
15426         } IIROPCNT_b;
15427     };
15428     __IM uint32_t RESERVED[3];
15429 
15430     union
15431     {
15432         __IOM uint32_t IIRECCCNT;        /*!< (@ 0x00000020) ECC Control Register                                       */
15433 
15434         struct
15435         {
15436             __IOM uint32_t ECCMD    : 1; /*!< [0..0] ECC setting bit                                                    */
15437             __IOM uint32_t ECCWBDIS : 1; /*!< [1..1] ECC-corrected data write-back disable bit                          */
15438             uint32_t                : 30;
15439         } IIRECCCNT_b;
15440     };
15441     __IM uint32_t RESERVED1;
15442 
15443     union
15444     {
15445         __IOM uint32_t IIRECCINT;      /*!< (@ 0x00000028) ECC Interrupt Enable Register                              */
15446 
15447         struct
15448         {
15449             __IOM uint32_t ESEIE : 1;  /*!< [0..0] ECC 1-bit error interrupt enable bit                               */
15450             __IOM uint32_t EDEIE : 1;  /*!< [1..1] ECC 2-bit error interrupt enable bit                               */
15451             uint32_t             : 30;
15452         } IIRECCINT_b;
15453     };
15454     __IM uint32_t RESERVED2;
15455 
15456     union
15457     {
15458         __IM uint32_t IIRECCEF;        /*!< (@ 0x00000030) ECC Error Flag Register                                    */
15459 
15460         struct
15461         {
15462             __IM uint32_t ESEF : 1;    /*!< [0..0] ECC 1-bit error flag                                               */
15463             __IM uint32_t EDEF : 1;    /*!< [1..1] ECC 2-bit error flag                                               */
15464             uint32_t           : 30;
15465         } IIRECCEF_b;
15466     };
15467 
15468     union
15469     {
15470         __OM uint32_t IIRECCEFCLR;     /*!< (@ 0x00000034) ECC Error Flag Clear Register                              */
15471 
15472         struct
15473         {
15474             __OM uint32_t ESEFCLR : 1; /*!< [0..0] ECC 1-bit error flag clear bit                                     */
15475             __OM uint32_t EDEFCLR : 1; /*!< [1..1] ECC 2-bit error status flag clear bit                              */
15476             uint32_t              : 30;
15477         } IIRECCEFCLR_b;
15478     };
15479 
15480     union
15481     {
15482         __IM uint32_t IIRESEADR;       /*!< (@ 0x00000038) ECC 1-bit Error Address Register                           */
15483 
15484         struct
15485         {
15486             __IM uint32_t SEADR : 11;  /*!< [10..0] Error address                                                     */
15487             uint32_t            : 21;
15488         } IIRESEADR_b;
15489     };
15490 
15491     union
15492     {
15493         __IM uint32_t IIREDEADR;       /*!< (@ 0x0000003C) ECC 2-bit Error Address Register                           */
15494 
15495         struct
15496         {
15497             __IM uint32_t DEADR : 11;  /*!< [10..0] Error address                                                     */
15498             uint32_t            : 21;
15499         } IIREDEADR_b;
15500     };
15501     __IM uint32_t             RESERVED3[48];
15502     __IOM R_IIRFA_IIRCH_Type  IIRCH[16];  /*!< (@ 0x00000100) Channel Registers                                          */
15503     __IM uint32_t             RESERVED4[128];
15504     __IOM R_IIRFA_IIRSTG_Type IIRSTG[32]; /*!< (@ 0x00000400) Stage Registers                                            */
15505 } R_IIRFA_Type;                           /*!< Size = 2048 (0x800)                                                       */
15506 
15507 /* =========================================================================================================================== */
15508 /* ================                                          R_IRDA                                           ================ */
15509 /* =========================================================================================================================== */
15510 
15511 /**
15512  * @brief IrDA Interface (R_IRDA)
15513  */
15514 
15515 typedef struct                         /*!< (@ 0x40070F00) R_IRDA Structure                                           */
15516 {
15517     union
15518     {
15519         __IOM uint8_t IRCR;            /*!< (@ 0x00000000) IrDA Control Register                                      */
15520 
15521         struct
15522         {
15523             uint8_t               : 2;
15524             __IOM uint8_t IRRXINV : 1; /*!< [2..2] IRRXD Polarity Switching                                           */
15525             __IOM uint8_t IRTXINV : 1; /*!< [3..3] IRTXD Polarity Switching                                           */
15526             uint8_t               : 3;
15527             __IOM uint8_t IRE     : 1; /*!< [7..7] IrDA Enable                                                        */
15528         } IRCR_b;
15529     };
15530 } R_IRDA_Type;                         /*!< Size = 1 (0x1)                                                            */
15531 
15532 /* =========================================================================================================================== */
15533 /* ================                                          R_IWDT                                           ================ */
15534 /* =========================================================================================================================== */
15535 
15536 /**
15537  * @brief Independent Watchdog Timer (R_IWDT)
15538  */
15539 
15540 typedef struct                         /*!< (@ 0x40044400) R_IWDT Structure                                           */
15541 {
15542     union
15543     {
15544         __IOM uint8_t IWDTRR;          /*!< (@ 0x00000000) IWDT Refresh Register                                      */
15545 
15546         struct
15547         {
15548             __IOM uint8_t IWDTRR : 8;  /*!< [7..0] The counter is refreshed by writing 0x00 and then writing
15549                                         *   0xFF to this register.                                                    */
15550         } IWDTRR_b;
15551     };
15552     __IM uint8_t  RESERVED;
15553     __IM uint16_t RESERVED1;
15554 
15555     union
15556     {
15557         __IOM uint16_t IWDTSR;          /*!< (@ 0x00000004) IWDT Status Register                                       */
15558 
15559         struct
15560         {
15561             __IM uint16_t  CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter                         */
15562             __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
15563             __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
15564         } IWDTSR_b;
15565     };
15566 } R_IWDT_Type;                          /*!< Size = 6 (0x6)                                                            */
15567 
15568 /* =========================================================================================================================== */
15569 /* ================                                          R_JPEG                                           ================ */
15570 /* =========================================================================================================================== */
15571 
15572 /**
15573  * @brief JPEG Codec (R_JPEG)
15574  */
15575 
15576 typedef struct                         /*!< (@ 0x400E6000) R_JPEG Structure                                           */
15577 {
15578     union
15579     {
15580         __IOM uint8_t JCMOD;           /*!< (@ 0x00000000) JPEG Code Mode Register                                    */
15581 
15582         struct
15583         {
15584             __IOM uint8_t REDU : 3;    /*!< [2..0] Pixel FormatNOTE: Read-only in Decompression.                      */
15585             __IOM uint8_t DSP  : 1;    /*!< [3..3] Compression/Decompression Set Note: When changing between
15586                                         *   processing for compression and for decompression, be sure
15587                                         *   to reset this module in advance by setting the JCUSRST
15588                                         *   bit in the software reset control register 2 (SWRSTCR2)
15589                                         *   of the power-downmodes.                                                   */
15590             uint8_t : 4;
15591         } JCMOD_b;
15592     };
15593 
15594     union
15595     {
15596         __OM uint8_t JCCMD;            /*!< (@ 0x00000001) JPEG Code Command Register                                 */
15597 
15598         struct
15599         {
15600             __OM uint8_t JSRT : 1;     /*!< [0..0] JPEG Core Process Start CommandTo start JPEG core processing,
15601                                         *   set this bit to 1. Do not write this bit to 1 again while
15602                                         *   this module is in operation.                                              */
15603             __OM uint8_t JRST : 1;     /*!< [1..1] JPEG Core Process Stop Clear CommandTo clear the process-stopped
15604                                         *   state caused by requests to read the image size and pixel
15605                                         *   format (enabled by the INT3 bit in JINTE0), set this bit
15606                                         *   to 1.                                                                     */
15607             __OM uint8_t JEND : 1;     /*!< [2..2] Interrupt Request Clear Command This bit is valid only
15608                                         *   for the interrupt sources corresponding to bits INS6, INS5,
15609                                         *   and INS3 in JINTS0. To clear an interrupt request, set
15610                                         *   this bit to 1                                                             */
15611             uint8_t           : 4;
15612             __OM uint8_t BRST : 1;     /*!< [7..7] Bus Reset. NOTE: When this module is in operation, the
15613                                         *   bus reset command should not be issued.                                   */
15614         } JCCMD_b;
15615     };
15616     __IM uint8_t RESERVED;
15617 
15618     union
15619     {
15620         __IOM uint8_t JCQTN;           /*!< (@ 0x00000003) JPEG Code Quantization Table Number Register               */
15621 
15622         struct
15623         {
15624             __IOM uint8_t QT1 : 2;     /*!< [1..0] Quantization table number for the first color componentNOTE:
15625                                         *   Read-only in Decompression.                                               */
15626             __IOM uint8_t QT2 : 2;     /*!< [3..2] Quantization table number for the second color component
15627                                         *   NOTE: Read-only in Decompression.                                         */
15628             __IOM uint8_t QT3 : 2;     /*!< [5..4] Quantization table number for the third color component
15629                                         *   NOTE: Read-only in Decompression.                                         */
15630             uint8_t : 2;
15631         } JCQTN_b;
15632     };
15633 
15634     union
15635     {
15636         __IOM uint8_t JCHTN;           /*!< (@ 0x00000004) JPEG Code Huffman Table Number Register                    */
15637 
15638         struct
15639         {
15640             __IOM uint8_t HTD1 : 1;    /*!< [0..0] Huffman table number (DC) for the first color component
15641                                         *   NOTE: Read-only in Decompression.                                         */
15642             __IOM uint8_t HTA1 : 1;    /*!< [1..1] Huffman table number (AC) for the first color componentNOTE:
15643                                         *   Read-only in Decompression.                                               */
15644             __IOM uint8_t HTD2 : 1;    /*!< [2..2] Huffman table number (DC) for the second color component
15645                                         *   NOTE: Read-only in Decompression.                                         */
15646             __IOM uint8_t HTA2 : 1;    /*!< [3..3] Huffman table number (AC) for the second color componentNOTE:
15647                                         *   Read-only in Decompression.                                               */
15648             __IOM uint8_t HTD3 : 1;    /*!< [4..4] Huffman table number (DC) for the third color component
15649                                         *   NOTE: Read-only in Decompression.                                         */
15650             __IOM uint8_t HTA3 : 1;    /*!< [5..5] Huffman table number (AC) for the third color componentNOTE:
15651                                         *   Read-only in Decompression.                                               */
15652             uint8_t : 2;
15653         } JCHTN_b;
15654     };
15655 
15656     union
15657     {
15658         __IOM uint8_t JCDRIU;          /*!< (@ 0x00000005) JPEG Code DRI Upper Register                               */
15659 
15660         struct
15661         {
15662             __IOM uint8_t DRIU : 8;    /*!< [7..0] Upper Bytes of MCUs Preceding RST MarkerWhen both upper
15663                                         *   and lower bytes are set to 00h, neither a DRI nor an RST
15664                                         *   marker is placed.NOTE: Read-only in Decompression.                        */
15665         } JCDRIU_b;
15666     };
15667 
15668     union
15669     {
15670         __IOM uint8_t JCDRID;          /*!< (@ 0x00000006) JPEG Code DRI Lower Register                               */
15671 
15672         struct
15673         {
15674             __IOM uint8_t DRID : 8;    /*!< [7..0] Lower Bytes of MCUs Preceding RST MarkerWhen both upper
15675                                         *   and lower bytes are set to 00h, neither a DRI nor an RST
15676                                         *   marker is placed.NOTE: Read-only in Decompression.                        */
15677         } JCDRID_b;
15678     };
15679 
15680     union
15681     {
15682         __IOM uint8_t JCVSZU;          /*!< (@ 0x00000007) JPEG Code Vertical Size Upper Register                     */
15683 
15684         struct
15685         {
15686             __IOM uint8_t VSZU : 8;    /*!< [7..0] Upper Bytes of Vertical Image SizeIn decompression process,
15687                                         *   a downloaded value from the JPEG coded data is set. NOTE:
15688                                         *   Read-only in Decompression.                                               */
15689         } JCVSZU_b;
15690     };
15691 
15692     union
15693     {
15694         __IOM uint8_t JCVSZD;          /*!< (@ 0x00000008) JPEG Code Vertical Size Lower Register                     */
15695 
15696         struct
15697         {
15698             __IOM uint8_t VSZD : 8;    /*!< [7..0] Lower Bytes of Vertical Image SizeIn decompression process,
15699                                         *   a downloaded value from the JPEG coded data is set. NOTE:
15700                                         *   Read-only in Decompression.                                               */
15701         } JCVSZD_b;
15702     };
15703 
15704     union
15705     {
15706         __IOM uint8_t JCHSZU;          /*!< (@ 0x00000009) JPEG Code Horizontal Size Upper Register                   */
15707 
15708         struct
15709         {
15710             __IOM uint8_t HSZU : 8;    /*!< [7..0] Upper Bytes of Horizontal Image SizeIn decompression
15711                                         *   process, a downloaded value from the JPEG coded data is
15712                                         *   set. NOTE: Read-only in Decompression.                                    */
15713         } JCHSZU_b;
15714     };
15715 
15716     union
15717     {
15718         __IOM uint8_t JCHSZD;          /*!< (@ 0x0000000A) JPEG Coded Horizontal Size Lower Register                  */
15719 
15720         struct
15721         {
15722             __IOM uint8_t HSZD : 8;    /*!< [7..0] Lower Bytes of Horizontal Image SizeIn decompression
15723                                         *   process, a downloaded value from the JPEG coded data is
15724                                         *   set. NOTE: Read-only in Decompression.                                    */
15725         } JCHSZD_b;
15726     };
15727 
15728     union
15729     {
15730         __IM uint8_t JCDTCU;           /*!< (@ 0x0000000B) JPEG Code Data Count Upper Register                        */
15731 
15732         struct
15733         {
15734             __IM uint8_t DCU : 8;      /*!< [7..0] Upper bytes of the counted amount of data to be compressed
15735                                         *   The values of this register are reset before compression
15736                                         *   starts.NOTE: Read-only in Decompression.                                  */
15737         } JCDTCU_b;
15738     };
15739 
15740     union
15741     {
15742         __IM uint8_t JCDTCM;           /*!< (@ 0x0000000C) JPEG Code Data Count Middle Register                       */
15743 
15744         struct
15745         {
15746             __IM uint8_t DCM : 8;      /*!< [7..0] Middle bytes of the counted amount of data to be compressedThe
15747                                         *   values of this register are reset before compression starts.
15748                                         *   NOTE: Read-only in Decompression.                                         */
15749         } JCDTCM_b;
15750     };
15751 
15752     union
15753     {
15754         __IM uint8_t JCDTCD;           /*!< (@ 0x0000000D) JPEG Code Data Count Lower Register                        */
15755 
15756         struct
15757         {
15758             __IM uint8_t DCD : 8;      /*!< [7..0] Lower bytes of the counted amount of data to be compressedThe
15759                                         *   values of this register are reset before compression starts.NOTE:
15760                                         *   Read-only in Decompression.                                               */
15761         } JCDTCD_b;
15762     };
15763 
15764     union
15765     {
15766         __IOM uint8_t JINTE0;          /*!< (@ 0x0000000E) JPEG Interrupt Enable Register 0                           */
15767 
15768         struct
15769         {
15770             uint8_t            : 3;
15771             __IOM uint8_t INT3 : 1;    /*!< [3..3] This bit enables an interrupt to be generated when it
15772                                         *   has been determined that the image size and the subsampling
15773                                         *   setting of the compressed data can be read through analyzing
15774                                         *   the data.                                                                 */
15775             uint8_t            : 1;
15776             __IOM uint8_t INT5 : 1;    /*!< [5..5] This bit enables an interrupt to be generated when the
15777                                         *   final number of MCU data in the Huffman-coding segment
15778                                         *   is not correct in decompression. When this bit is not set
15779                                         *   to enable interrupt generation, an error code is not returned.            */
15780             __IOM uint8_t INT6 : 1;    /*!< [6..6] This bit enables an interrupt to be generated when the
15781                                         *   total number of data in the Huffman-coding segment is not
15782                                         *   correct in decompression. When this bit is not set to enable
15783                                         *   interrupt generation, an error code is not returned.                      */
15784             __IOM uint8_t INT7 : 1;    /*!< [7..7] This bit enables an interrupt to be generated when the
15785                                         *   number of data in the restart interval of the Huffman-coding
15786                                         *   segment is not correct in decompression.When this bit is
15787                                         *   not set to enable interrupt generation, an error code is
15788                                         *   not returned.                                                             */
15789         } JINTE0_b;
15790     };
15791 
15792     union
15793     {
15794         __IOM uint8_t JINTS0;          /*!< (@ 0x0000000F) JPEG Interrupt Status Register 0                           */
15795 
15796         struct
15797         {
15798             uint8_t            : 3;
15799             __IOM uint8_t INS3 : 1;    /*!< [3..3] This bit is set to 1 when the image size and pixel format
15800                                         *   can be read. When an interrupt occurs, this module stops
15801                                         *   processing and the state is indicated by the JCRST register.
15802                                         *   To make this module resume processing, set the JPEG core
15803                                         *   process stop clear command bit (JRST) in JCCMD.                           */
15804             uint8_t            : 1;
15805             __IOM uint8_t INS5 : 1;    /*!< [5..5] This bit is set to 1 when a compressed data error occurs.          */
15806             __IOM uint8_t INS6 : 1;    /*!< [6..6] This bit is set to 1 when this module completes compression
15807                                         *   process normally.                                                         */
15808             uint8_t : 1;
15809         } JINTS0_b;
15810     };
15811 
15812     union
15813     {
15814         __IOM uint8_t JCDERR;          /*!< (@ 0x00000010) JPEG Code Decode Error Register                            */
15815 
15816         struct
15817         {
15818             __IOM uint8_t ERR : 4;     /*!< [3..0] Error Code (See tables )Identify the type of the error
15819                                         *   which has occurred in the compressed data analysis for
15820                                         *   decompression.                                                            */
15821             uint8_t : 4;
15822         } JCDERR_b;
15823     };
15824 
15825     union
15826     {
15827         __IM uint8_t JCRST;            /*!< (@ 0x00000011) JPEG Code Reset Register                                   */
15828 
15829         struct
15830         {
15831             __IM uint8_t RST : 1;      /*!< [0..0] Operating State                                                    */
15832             uint8_t          : 7;
15833         } JCRST_b;
15834     };
15835     __IM uint16_t RESERVED1;
15836     __IM uint32_t RESERVED2[11];
15837 
15838     union
15839     {
15840         __IOM uint32_t JIFECNT;          /*!< (@ 0x00000040) JPEG Interface Compression Control Register                */
15841 
15842         struct
15843         {
15844             __IOM uint32_t DINSWAP : 3;  /*!< [2..0] Byte/Halfword Swap                                                 */
15845             uint32_t               : 1;
15846             __IOM uint32_t DINLC   : 1;  /*!< [4..4] Count Mode Setting for Stopping Input Image Data Lines             */
15847             __OM uint32_t  DINRCMD : 1;  /*!< [5..5] Input Image Data Lines Resume Command This bit is valid
15848                                           *   only when the count mode for stopping the input of image
15849                                           *   data lines is on. Setting this bit to 1 resumes reading
15850                                           *   input image data. This bit is always read as 0.                           */
15851             __IOM uint32_t DINRINI : 1;  /*!< [6..6] Address Initialization when Resuming Input of Image Data
15852                                           *   Lines This bit is only valid when the count mode for stopping
15853                                           *   the input of image data lines is on. Set this bit before
15854                                           *   writing 1 to the data-line resume command bit.                            */
15855             uint32_t                : 1;
15856             __IOM uint32_t JOUTSWAP : 3; /*!< [10..8] Byte/Halfword/Word Swap Output coded data in compression
15857                                           *   is swapped.                                                               */
15858             uint32_t : 21;
15859         } JIFECNT_b;
15860     };
15861 
15862     union
15863     {
15864         __IOM uint32_t JIFESA;         /*!< (@ 0x00000044) JPEG Interface Compression Source Address Register         */
15865 
15866         struct
15867         {
15868             __IOM uint32_t ESA : 32;   /*!< [31..0] Input Image Data Source Address (in 8-byte units) The
15869                                         *   lower three bits should be set to 0.                                      */
15870         } JIFESA_b;
15871     };
15872 
15873     union
15874     {
15875         __IOM uint32_t JIFESOFST;      /*!< (@ 0x00000048) JPEG Interface Compression Line Offset Register            */
15876 
15877         struct
15878         {
15879             __IOM uint32_t ESMW : 15;  /*!< [14..0] Input Image Data Lines Offset(in 8-byte units)The lower
15880                                         *   three bits should be set to 0.                                            */
15881             uint32_t : 17;
15882         } JIFESOFST_b;
15883     };
15884 
15885     union
15886     {
15887         __IOM uint32_t JIFEDA;         /*!< (@ 0x0000004C) JPEG Interface Compression Destination Address
15888                                         *                  Register                                                   */
15889 
15890         struct
15891         {
15892             __IOM uint32_t EDA : 32;   /*!< [31..0] Input Image Data Lines Offset (in 8-byte units) The
15893                                         *   lower three bits should be set to 0.                                      */
15894         } JIFEDA_b;
15895     };
15896 
15897     union
15898     {
15899         __IOM uint32_t JIFESLC;        /*!< (@ 0x00000050) JPEG Interface Compression Source Line Count
15900                                         *                  Register                                                   */
15901 
15902         struct
15903         {
15904             __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Data Lines to be Read (in 8-line
15905                                         *   units) The lower three bits should be set to 0.                           */
15906             uint32_t : 16;
15907         } JIFESLC_b;
15908     };
15909     __IM uint32_t RESERVED3;
15910 
15911     union
15912     {
15913         __IOM uint32_t JIFDCNT;          /*!< (@ 0x00000058) JPEG Interface Decompression Control Register              */
15914 
15915         struct
15916         {
15917             __IOM uint32_t DOUTSWAP : 3; /*!< [2..0] Byte/Word Swap Output image data in decompression is
15918                                           *   swapped.                                                                  */
15919             uint32_t                : 1;
15920             __IOM uint32_t DOUTLC   : 1; /*!< [4..4] Count Mode for Stopping Output Image Data Lines                    */
15921             __OM uint32_t  DOUTRCMD : 1; /*!< [5..5] Output Image Data Lines Resume Command This bit is valid
15922                                           *   only when the count mode for stopping the output of image
15923                                           *   data lines is on. Setting this bit to 1 resumes writing
15924                                           *   image data. This bit is always read as 0.                                 */
15925             __IOM uint32_t DOUTRINI : 1; /*!< [6..6] Address Initialization when Resuming Output of Image
15926                                           *   Data Lines This bit is only valid when the count mode for
15927                                           *   stopping the output of image data lines is on. Set this
15928                                           *   bit before writing 1 to the data-line resume command bit.                 */
15929             uint32_t               : 1;
15930             __IOM uint32_t JINSWAP : 3;  /*!< [10..8] Byte/Word/Longword Swap Input coded data in decompression
15931                                           *   is swapped.                                                               */
15932             uint32_t               : 1;
15933             __IOM uint32_t JINC    : 1;  /*!< [12..12] Count Mode Setting for Stopping Input Coded Data                 */
15934             __OM uint32_t  JINRCMD : 1;  /*!< [13..13] Input Coded Data Resume CommandThis bit is valid only
15935                                           *   when the count mode for stopping the input of coded data
15936                                           *   is on. Setting this bit to 1 resumes reading input coded
15937                                           *   data. This bit is always read as 0.                                       */
15938             __IOM uint32_t JINRINI : 1;  /*!< [14..14] Address Initialization when Input Coded Data is Resumed
15939                                           *   This bit is only valid when the count mode for stopping
15940                                           *   the input of coded data is on. Set this bit before writing
15941                                           *   1 to the data resume command bit.                                         */
15942             uint32_t              : 9;
15943             __IOM uint32_t OPF    : 2;   /*!< [25..24] Specifies output image data pixel format.                        */
15944             __IOM uint32_t HINTER : 2;   /*!< [27..26] Horizontal Subsampling Subsamples horizontal output
15945                                           *   image data.                                                               */
15946             __IOM uint32_t VINTER : 2;   /*!< [29..28] Vertical SubsamplingSubsamples vertical output image
15947                                           *   data.                                                                     */
15948             uint32_t : 2;
15949         } JIFDCNT_b;
15950     };
15951 
15952     union
15953     {
15954         __IOM uint32_t JIFDSA;         /*!< (@ 0x0000005C) JPEG Interface Decompression Source Address Register       */
15955 
15956         struct
15957         {
15958             __IOM uint32_t DSA : 32;   /*!< [31..0] Input Coded Data Source AddressInput Coded Data Source
15959                                         *   Address (in 8-byte units) The lower three bits should be
15960                                         *   set to 0.                                                                 */
15961         } JIFDSA_b;
15962     };
15963 
15964     union
15965     {
15966         __IOM uint32_t JIFDDOFST;      /*!< (@ 0x00000060) JPEG Interface Decompression Line Offset Register          */
15967 
15968         struct
15969         {
15970             __IOM uint32_t DDMW : 15;  /*!< [14..0] Output Image Data Lines Offset (in 8-byte units) The
15971                                         *   lower three bits should be set to 0.                                      */
15972             uint32_t : 17;
15973         } JIFDDOFST_b;
15974     };
15975 
15976     union
15977     {
15978         __IOM uint32_t JIFDDA;         /*!< (@ 0x00000064) JPEG Interface Decompression Destination Address
15979                                         *                  Register                                                   */
15980 
15981         struct
15982         {
15983             __IOM uint32_t DDA : 32;   /*!< [31..0] Output Image Data Destination Address (in 8-byte units)
15984                                         *   The lower three bits should be set to 0.                                  */
15985         } JIFDDA_b;
15986     };
15987 
15988     union
15989     {
15990         __IOM uint32_t JIFDSDC;         /*!< (@ 0x00000068) JPEG Interface Decompression Source Data Count
15991                                          *                  Register                                                   */
15992 
15993         struct
15994         {
15995             __IOM uint32_t JDATAS : 16; /*!< [15..0] Amount of Input Coded Data to be Read (in 8-byte units)
15996                                          *   The lower three bits should be set to 0.                                  */
15997             uint32_t : 16;
15998         } JIFDSDC_b;
15999     };
16000 
16001     union
16002     {
16003         __IOM uint32_t JIFDDLC;        /*!< (@ 0x0000006C) JPEG Interface Decompression Destination Line
16004                                         *                  Count Register                                             */
16005 
16006         struct
16007         {
16008             __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Lines to Be ReadThe lower three
16009                                         *   bits should be set to 0. These bits are read as0.Number
16010                                         *   of input image data lines to be read, in 8-line units.                    */
16011             uint32_t : 16;
16012         } JIFDDLC_b;
16013     };
16014 
16015     union
16016     {
16017         __IOM uint32_t JIFDADT;        /*!< (@ 0x00000070) JPEG Interface Decompression alpha Set Register            */
16018 
16019         struct
16020         {
16021             __IOM uint32_t ALPHA : 8;  /*!< [7..0] Setting of the alpha value for output in ARGB8888 format.          */
16022             uint32_t             : 24;
16023         } JIFDADT_b;
16024     };
16025     __IM uint32_t RESERVED4[6];
16026 
16027     union
16028     {
16029         __IOM uint32_t JINTE1;          /*!< (@ 0x0000008C) JPEG Interrupt Enable Register 1                           */
16030 
16031         struct
16032         {
16033             __IOM uint32_t DOUTLEN : 1; /*!< [0..0] Enables or disables a data transfer processing interrupt
16034                                          *   request (JDTI) when the DOUTLF bit in JINTS1 is set to
16035                                          *   1                                                                         */
16036             __IOM uint32_t JINEN : 1;   /*!< [1..1] Enables or disables a data transfer processing interrupt
16037                                          *   request (JDTI) when the JINF bit in JINTS1 is set to 1.                   */
16038             __IOM uint32_t DBTEN : 1;   /*!< [2..2] Enables or disables a data transfer processing interrupt
16039                                          *   request (JDTI) when the DBTF bit in JINTS1 is set to 1.                   */
16040             uint32_t              : 2;
16041             __IOM uint32_t DINLEN : 1;  /*!< [5..5] Enables or disables a data transfer processing interrupt
16042                                          *   request (JDTI) when the DINLF bit in JINTS1 is set to 1.                  */
16043             __IOM uint32_t CBTEN : 1;   /*!< [6..6] Enables or disables a data transfer processing interrupt
16044                                          *   request (JDTI) when the CBTF bit in JINTS1 is set to 1.                   */
16045             uint32_t : 25;
16046         } JINTE1_b;
16047     };
16048 
16049     union
16050     {
16051         __IOM uint32_t JINTS1;         /*!< (@ 0x00000090) JPEG Interrupt Status Register 1                           */
16052 
16053         struct
16054         {
16055             __IOM uint32_t DOUTLF : 1; /*!< [0..0] In decompression, this bit is set to 1 when the number
16056                                         *   of lines of output image data indicated by JIFDDLC have
16057                                         *   been written. This bit is only valid when the DOUTLC bit
16058                                         *   in JIFDCNT is set to 1.                                                   */
16059             __IOM uint32_t JINF : 1;   /*!< [1..1] This bit is set to 1 when the amount of input coded data
16060                                         *   indicated by JIFDSDC is read in decompression. This bit
16061                                         *   is valid only when the JINC bit in JIFDCNT is set to 1.                   */
16062             __IOM uint32_t DBTF : 1;   /*!< [2..2] This bit is set to 1 when the last output image data
16063                                         *   is written in decompression.                                              */
16064             uint32_t             : 2;
16065             __IOM uint32_t DINLF : 1;  /*!< [5..5] This bit is set to 1 when the number of input image data
16066                                         *   lines indicated by JIFESLC is read in compression. This
16067                                         *   bit is valid only when the DINLC bit in JIFECNT is set
16068                                         *   to 1.                                                                     */
16069             __IOM uint32_t CBTF : 1;   /*!< [6..6] This bit is set to 1 when the last output coded data
16070                                         *   is written in compression.                                                */
16071             uint32_t : 25;
16072         } JINTS1_b;
16073     };
16074     __IM uint32_t RESERVED5[27];
16075     __OM uint8_t  JCQTBL0[64];         /*!< (@ 0x00000100) Quantization Table 0                                       */
16076     __OM uint8_t  JCQTBL1[64];         /*!< (@ 0x00000140) Quantization Table 1                                       */
16077     __OM uint8_t  JCQTBL2[64];         /*!< (@ 0x00000180) Quantization Table 2                                       */
16078     __OM uint8_t  JCQTBL3[64];         /*!< (@ 0x000001C0) Quantization Table 3                                       */
16079     __IOM uint8_t JCHTBD0[28];         /*!< (@ 0x00000200) DC Huffman Table 0                                         */
16080     __IM uint32_t RESERVED6;
16081     __IOM uint8_t JCHTBA0[178];        /*!< (@ 0x00000220) AC Huffman Table 0                                         */
16082     __IM uint16_t RESERVED7;
16083     __IM uint32_t RESERVED8[11];
16084     __IOM uint8_t JCHTBD1[28];         /*!< (@ 0x00000300) DC Huffman Table 1                                         */
16085     __IM uint32_t RESERVED9;
16086     __IOM uint8_t JCHTBA1[178];        /*!< (@ 0x00000320) DC Huffman Table 1                                         */
16087     __IM uint16_t RESERVED10;
16088 } R_JPEG_Type;                         /*!< Size = 980 (0x3d4)                                                        */
16089 
16090 /* =========================================================================================================================== */
16091 /* ================                                          R_KINT                                           ================ */
16092 /* =========================================================================================================================== */
16093 
16094 /**
16095  * @brief Key Interrupt Function (R_KINT)
16096  */
16097 
16098 typedef struct                         /*!< (@ 0x40080000) R_KINT Structure                                           */
16099 {
16100     union
16101     {
16102         __IOM uint8_t KRCTL;           /*!< (@ 0x00000000) KEY Return Control Register                                */
16103 
16104         struct
16105         {
16106             __IOM uint8_t KREG : 1;    /*!< [0..0] Detection Edge Selection (KRF0 to KRF7)                            */
16107             uint8_t            : 6;
16108             __IOM uint8_t KRMD : 1;    /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7)                           */
16109         } KRCTL_b;
16110     };
16111     __IM uint8_t RESERVED[3];
16112 
16113     union
16114     {
16115         __IOM uint8_t KRF;             /*!< (@ 0x00000004) KEY Return Flag Register                                   */
16116 
16117         struct
16118         {
16119             __IOM uint8_t KRF0 : 1;    /*!< [0..0] Key interrupt flag 0                                               */
16120             __IOM uint8_t KRF1 : 1;    /*!< [1..1] Key interrupt flag 1                                               */
16121             __IOM uint8_t KRF2 : 1;    /*!< [2..2] Key interrupt flag 2                                               */
16122             __IOM uint8_t KRF3 : 1;    /*!< [3..3] Key interrupt flag 3                                               */
16123             __IOM uint8_t KRF4 : 1;    /*!< [4..4] Key interrupt flag 4                                               */
16124             __IOM uint8_t KRF5 : 1;    /*!< [5..5] Key interrupt flag 5                                               */
16125             __IOM uint8_t KRF6 : 1;    /*!< [6..6] Key interrupt flag 6                                               */
16126             __IOM uint8_t KRF7 : 1;    /*!< [7..7] Key interrupt flag 7                                               */
16127         } KRF_b;
16128     };
16129     __IM uint8_t RESERVED1[3];
16130 
16131     union
16132     {
16133         __IOM uint8_t KRM;             /*!< (@ 0x00000008) KEY Return Mode Register                                   */
16134 
16135         struct
16136         {
16137             __IOM uint8_t KRM0 : 1;    /*!< [0..0] Key interrupt mode control 0                                       */
16138             __IOM uint8_t KRM1 : 1;    /*!< [1..1] Key interrupt mode control 1                                       */
16139             __IOM uint8_t KRM2 : 1;    /*!< [2..2] Key interrupt mode control 2                                       */
16140             __IOM uint8_t KRM3 : 1;    /*!< [3..3] Key interrupt mode control 3                                       */
16141             __IOM uint8_t KRM4 : 1;    /*!< [4..4] Key interrupt mode control 4                                       */
16142             __IOM uint8_t KRM5 : 1;    /*!< [5..5] Key interrupt mode control 5                                       */
16143             __IOM uint8_t KRM6 : 1;    /*!< [6..6] Key interrupt mode control 6                                       */
16144             __IOM uint8_t KRM7 : 1;    /*!< [7..7] Key interrupt mode control 7                                       */
16145         } KRM_b;
16146     };
16147 } R_KINT_Type;                         /*!< Size = 9 (0x9)                                                            */
16148 
16149 /* =========================================================================================================================== */
16150 /* ================                                          R_I3C0                                           ================ */
16151 /* =========================================================================================================================== */
16152 
16153 /**
16154  * @brief I3C Bus Interface (R_I3C0)
16155  */
16156 
16157 typedef struct                         /*!< (@ 0x40083000) R_I3C0 Structure                                           */
16158 {
16159     union
16160     {
16161         __IOM uint32_t PRTS;           /*!< (@ 0x00000000) Protocol Selection Register                                */
16162 
16163         struct
16164         {
16165             __IOM uint32_t PRTMD : 1;  /*!< [0..0] Protocol Mode                                                      */
16166             uint32_t             : 31;
16167         } PRTS_b;
16168     };
16169     __IM uint32_t RESERVED[3];
16170 
16171     union
16172     {
16173         __IOM uint32_t CECTL;          /*!< (@ 0x00000010) Clock Enable Control Resisters                             */
16174 
16175         struct
16176         {
16177             __IOM uint32_t CLKE : 1;   /*!< [0..0] Clock Enable                                                       */
16178             uint32_t            : 31;
16179         } CECTL_b;
16180     };
16181 
16182     union
16183     {
16184         __IOM uint32_t BCTL;             /*!< (@ 0x00000014) Bus Control Register                                       */
16185 
16186         struct
16187         {
16188             __IOM uint32_t INCBA    : 1; /*!< [0..0] Include I3C Broadcast Address                                      */
16189             uint32_t                : 6;
16190             __IOM uint32_t BMDS     : 1; /*!< [7..7] Bus Mode Selection                                                 */
16191             __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control                                       */
16192             uint32_t                : 20;
16193             __IOM uint32_t ABT      : 1; /*!< [29..29] Abort                                                            */
16194             __IOM uint32_t RSM      : 1; /*!< [30..30] Resume                                                           */
16195             __IOM uint32_t BUSE     : 1; /*!< [31..31] Bus Enable                                                       */
16196         } BCTL_b;
16197     };
16198 
16199     union
16200     {
16201         __IOM uint32_t MSDVAD;         /*!< (@ 0x00000018) Master Device Address Register                             */
16202 
16203         struct
16204         {
16205             uint32_t              : 16;
16206             __IOM uint32_t MDYAD  : 7; /*!< [22..16] Master Dynamic Address                                           */
16207             uint32_t              : 8;
16208             __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid                                     */
16209         } MSDVAD_b;
16210     };
16211     __IM uint32_t RESERVED1;
16212 
16213     union
16214     {
16215         __IOM uint32_t RSTCTL;          /*!< (@ 0x00000020) Reset Control Register                                     */
16216 
16217         struct
16218         {
16219             __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset                                                 */
16220             __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset                                       */
16221             __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset                                      */
16222             __IOM uint32_t TDBRST  : 1; /*!< [3..3] Transmit Data Buffer Software Reset                                */
16223             __IOM uint32_t RDBRST  : 1; /*!< [4..4] Receive Data Buffer Software Reset                                 */
16224             __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset                                           */
16225             __IOM uint32_t RSQRST  : 1; /*!< [6..6] Receive Status Queue Software Reset                                */
16226             uint32_t               : 9;
16227             __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset                                          */
16228             uint32_t               : 15;
16229         } RSTCTL_b;
16230     };
16231 
16232     union
16233     {
16234         __IOM uint32_t PRSST;          /*!< (@ 0x00000024) Present State Register                                     */
16235 
16236         struct
16237         {
16238             uint32_t              : 2;
16239             __IOM uint32_t CRMS   : 1; /*!< [2..2] Current Master                                                     */
16240             uint32_t              : 1;
16241             __IM uint32_t TRMD    : 1; /*!< [4..4] Transmit/Receive Mode                                              */
16242             uint32_t              : 2;
16243             __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect                                        */
16244             uint32_t              : 24;
16245         } PRSST_b;
16246     };
16247     __IM uint32_t RESERVED2[2];
16248 
16249     union
16250     {
16251         __IOM uint32_t INST;           /*!< (@ 0x00000030) Internal Status Register                                   */
16252 
16253         struct
16254         {
16255             uint32_t            : 10;
16256             __IOM uint32_t INEF : 1;   /*!< [10..10] Internal Error Flag                                              */
16257             uint32_t            : 21;
16258         } INST_b;
16259     };
16260 
16261     union
16262     {
16263         __IOM uint32_t INSTE;          /*!< (@ 0x00000034) Internal Status Enable Register                            */
16264 
16265         struct
16266         {
16267             uint32_t            : 10;
16268             __IOM uint32_t INEE : 1;   /*!< [10..10] Internal Error Enable                                            */
16269             uint32_t            : 21;
16270         } INSTE_b;
16271     };
16272 
16273     union
16274     {
16275         __IOM uint32_t INIE;           /*!< (@ 0x00000038) Internal Interrupt Enable Register                         */
16276 
16277         struct
16278         {
16279             uint32_t             : 10;
16280             __IOM uint32_t INEIE : 1;  /*!< [10..10] Internal Error Interrupt Enable                                  */
16281             uint32_t             : 21;
16282         } INIE_b;
16283     };
16284 
16285     union
16286     {
16287         __IOM uint32_t INSTFC;         /*!< (@ 0x0000003C) Internal Status Force Register                             */
16288 
16289         struct
16290         {
16291             uint32_t            : 10;
16292             __OM uint32_t INEFC : 1;   /*!< [10..10] Internal Error Force                                             */
16293             uint32_t            : 21;
16294         } INSTFC_b;
16295     };
16296     __IM uint32_t RESERVED3;
16297 
16298     union
16299     {
16300         __IM uint32_t DVCT;            /*!< (@ 0x00000044) Device Characteristic Table Register                       */
16301 
16302         struct
16303         {
16304             uint32_t          : 19;
16305             __IM uint32_t IDX : 5;     /*!< [23..19] DCT Table Index                                                  */
16306             uint32_t          : 8;
16307         } DVCT_b;
16308     };
16309     __IM uint32_t RESERVED4[4];
16310 
16311     union
16312     {
16313         __IOM uint32_t IBINCTL;          /*!< (@ 0x00000058) IBI Notify Control Register                                */
16314 
16315         struct
16316         {
16317             __IOM uint32_t NRHJCTL  : 1; /*!< [0..0] Notify Rejected Hot-Join Control                                   */
16318             __IOM uint32_t NRMRCTL  : 1; /*!< [1..1] Notify Rejected Master Request Control                             */
16319             uint32_t                : 1;
16320             __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control                    */
16321             uint32_t                : 28;
16322         } IBINCTL_b;
16323     };
16324     __IM uint32_t RESERVED5;
16325 
16326     union
16327     {
16328         __IOM uint32_t BFCTL;          /*!< (@ 0x00000060) Bus Function Control Register                              */
16329 
16330         struct
16331         {
16332             __IOM uint32_t MALE   : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable                           */
16333             __IOM uint32_t NALE   : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable                */
16334             __IOM uint32_t SALE   : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable                            */
16335             uint32_t              : 5;
16336             __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable                                     */
16337             uint32_t              : 3;
16338             __IOM uint32_t SMBS   : 1; /*!< [12..12] SMBus/I2C Bus Selection                                          */
16339             uint32_t              : 1;
16340             __IOM uint32_t FMPE   : 1; /*!< [14..14] Fast-mode Plus Enable                                            */
16341             __IOM uint32_t HSME   : 1; /*!< [15..15] High Speed Mode Enable                                           */
16342             uint32_t              : 16;
16343         } BFCTL_b;
16344     };
16345 
16346     union
16347     {
16348         __IOM uint32_t SVCTL;          /*!< (@ 0x00000064) Slave Control Register                                     */
16349 
16350         struct
16351         {
16352             __IOM uint32_t GCAE  : 1;  /*!< [0..0] General Call Address Enable                                        */
16353             uint32_t             : 4;
16354             __IOM uint32_t HSMCE : 1;  /*!< [5..5] Hs-mode Master Code Enable                                         */
16355             __IOM uint32_t DVIDE : 1;  /*!< [6..6] Device-ID Address Enable                                           */
16356             uint32_t             : 8;
16357             __IOM uint32_t HOAE  : 1;  /*!< [15..15] Host Address Enable                                              */
16358             __IOM uint32_t SVAEn : 1;  /*!< [16..16] Slave Address Enable n (n = 0)                                   */
16359             uint32_t             : 15;
16360         } SVCTL_b;
16361     };
16362     __IM uint32_t RESERVED6[2];
16363 
16364     union
16365     {
16366         __IOM uint32_t REFCKCTL;        /*!< (@ 0x00000070) Reference Clock Control Register                           */
16367 
16368         struct
16369         {
16370             __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection                                 */
16371             uint32_t               : 29;
16372         } REFCKCTL_b;
16373     };
16374 
16375     union
16376     {
16377         __IOM uint32_t STDBR;          /*!< (@ 0x00000074) Standard Bit Rate Register                                 */
16378 
16379         struct
16380         {
16381             __IOM uint32_t SBRLO  : 8; /*!< [7..0] Count value of the Low-level period of SCL clock                   */
16382             __IOM uint32_t SBRHO  : 8; /*!< [15..8] Count value of the High-level period of SCL clock                 */
16383             __IOM uint32_t SBRLP  : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull                     */
16384             uint32_t              : 2;
16385             __IOM uint32_t SBRHP  : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull                    */
16386             uint32_t              : 1;
16387             __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain               */
16388         } STDBR_b;
16389     };
16390 
16391     union
16392     {
16393         __IOM uint32_t EXTBR;          /*!< (@ 0x00000078) Extended Bit Rate Register                                 */
16394 
16395         struct
16396         {
16397             __IOM uint32_t EBRLO : 8;  /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain                      */
16398             __IOM uint32_t EBRHO : 8;  /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain                    */
16399             __IOM uint32_t EBRLP : 6;  /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull                     */
16400             uint32_t             : 2;
16401             __IOM uint32_t EBRHP : 6;  /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull                     */
16402             uint32_t             : 2;
16403         } EXTBR_b;
16404     };
16405 
16406     union
16407     {
16408         __IOM uint32_t BFRECDT;        /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register                 */
16409 
16410         struct
16411         {
16412             __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle                                 */
16413             uint32_t              : 23;
16414         } BFRECDT_b;
16415     };
16416 
16417     union
16418     {
16419         __IOM uint32_t BAVLCDT;        /*!< (@ 0x00000080) Bus Available Condition Detection Time Register            */
16420 
16421         struct
16422         {
16423             __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle                            */
16424             uint32_t              : 23;
16425         } BAVLCDT_b;
16426     };
16427 
16428     union
16429     {
16430         __IOM uint32_t BIDLCDT;         /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register                 */
16431 
16432         struct
16433         {
16434             __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle                                */
16435             uint32_t              : 14;
16436         } BIDLCDT_b;
16437     };
16438 
16439     union
16440     {
16441         __IOM uint32_t OUTCTL;         /*!< (@ 0x00000088) Output Control Register                                    */
16442 
16443         struct
16444         {
16445             __IOM uint32_t SDOC   : 1; /*!< [0..0] SDA Output Control                                                 */
16446             __IOM uint32_t SCOC   : 1; /*!< [1..1] SCL Output Control                                                 */
16447             __OM uint32_t  SOCWP  : 1; /*!< [2..2] SCL/SDA Output Control Write Protect                               */
16448             uint32_t              : 1;
16449             __IOM uint32_t EXCYC  : 1; /*!< [4..4] Extra SCL Clock Cycle Output                                       */
16450             uint32_t              : 3;
16451             __IOM uint32_t SDOD   : 3; /*!< [10..8] SDA Output Delay                                                  */
16452             uint32_t              : 4;
16453             __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection                          */
16454             uint32_t              : 16;
16455         } OUTCTL_b;
16456     };
16457 
16458     union
16459     {
16460         __IOM uint32_t INCTL;          /*!< (@ 0x0000008C) Input Control Register                                     */
16461 
16462         struct
16463         {
16464             __IOM uint32_t DNFS : 4;   /*!< [3..0] Digital Noise Filter Stage Selection                               */
16465             __IOM uint32_t DNFE : 1;   /*!< [4..4] Digital Noise Filter Circuit Enable                                */
16466             uint32_t            : 27;
16467         } INCTL_b;
16468     };
16469 
16470     union
16471     {
16472         __IOM uint32_t TMOCTL;         /*!< (@ 0x00000090) Timeout Control Register                                   */
16473 
16474         struct
16475         {
16476             __IOM uint32_t TODTS  : 2; /*!< [1..0] Timeout Detection Time Selection                                   */
16477             uint32_t              : 2;
16478             __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control                                            */
16479             __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control                                            */
16480             __IOM uint32_t TOMDS  : 2; /*!< [7..6] Timeout Operation Mode Selection                                   */
16481             uint32_t              : 24;
16482         } TMOCTL_b;
16483     };
16484     __IM uint32_t RESERVED7;
16485 
16486     union
16487     {
16488         __IOM uint32_t WUCTL;           /*!< (@ 0x00000098) Wake Up Unit Control Register                              */
16489 
16490         struct
16491         {
16492             __IOM uint32_t WUACKS  : 1; /*!< [0..0] Wake-Up Acknowledge Selection                                      */
16493             uint32_t               : 3;
16494             __IOM uint32_t WUANFS  : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection                              */
16495             uint32_t               : 1;
16496             __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable                          */
16497             __IOM uint32_t WUFE    : 1; /*!< [7..7] Wake-Up function Enable.                                           */
16498             uint32_t               : 24;
16499         } WUCTL_b;
16500     };
16501     __IM uint32_t RESERVED8;
16502 
16503     union
16504     {
16505         __IOM uint32_t ACKCTL;         /*!< (@ 0x000000A0) Acknowledge Control Register                               */
16506 
16507         struct
16508         {
16509             __IM uint32_t  ACKR   : 1; /*!< [0..0] Acknowledge Reception                                              */
16510             __IOM uint32_t ACKT   : 1; /*!< [1..1] Acknowledge Transmission                                           */
16511             __OM uint32_t  ACKTWP : 1; /*!< [2..2] ACKT Write Protect                                                 */
16512             uint32_t              : 29;
16513         } ACKCTL_b;
16514     };
16515 
16516     union
16517     {
16518         __IOM uint32_t SCSTRCTL;       /*!< (@ 0x000000A4) SCL Stretch Control Register                               */
16519 
16520         struct
16521         {
16522             __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable                               */
16523             __IOM uint32_t RWE    : 1; /*!< [1..1] Receive Wait Enable                                                */
16524             uint32_t              : 30;
16525         } SCSTRCTL_b;
16526     };
16527     __IM uint32_t RESERVED9[2];
16528 
16529     union
16530     {
16531         __IOM uint32_t SCSTLCTL;        /*!< (@ 0x000000B0) SCL Stalling Control Register                              */
16532 
16533         struct
16534         {
16535             __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle                                                    */
16536             uint32_t              : 12;
16537             __IOM uint32_t AAPE   : 1;  /*!< [28..28] Assigend Address Phase Enable                                    */
16538             __IOM uint32_t TRAPE  : 1;  /*!< [29..29] Transition Phase Enable                                          */
16539             __IOM uint32_t PARPE  : 1;  /*!< [30..30] Parity Phase Enable                                              */
16540             __IOM uint32_t ACKPE  : 1;  /*!< [31..31] ACK phase Enable                                                 */
16541         } SCSTLCTL_b;
16542     };
16543     __IM uint32_t RESERVED10[3];
16544 
16545     union
16546     {
16547         __IOM uint32_t SVTDLG0;        /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0                      */
16548 
16549         struct
16550         {
16551             uint32_t             : 16;
16552             __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length                                       */
16553         } SVTDLG0_b;
16554     };
16555     __IM uint32_t RESERVED11[31];
16556 
16557     union
16558     {
16559         __IOM uint32_t CNDCTL;         /*!< (@ 0x00000140) Condition Control Register                                 */
16560 
16561         struct
16562         {
16563             __IOM uint32_t STCND : 1;  /*!< [0..0] START (S) Condition Issuance                                       */
16564             __IOM uint32_t SRCND : 1;  /*!< [1..1] Repeated START (Sr) Condition Issuance                             */
16565             __IOM uint32_t SPCND : 1;  /*!< [2..2] STOP (P) Condition Issuance                                        */
16566             uint32_t             : 29;
16567         } CNDCTL_b;
16568     };
16569     __IM uint32_t  RESERVED12[3];
16570     __OM uint32_t  NCMDQP;             /*!< (@ 0x00000150) Normal Command Queue Port Register                         */
16571     __IM uint32_t  NRSPQP;             /*!< (@ 0x00000154) Normal Response Queue Port Register                        */
16572     __IOM uint32_t NTDTBP0;            /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0                */
16573     __IM uint32_t  RESERVED13[8];
16574     __IOM uint32_t NIBIQP;             /*!< (@ 0x0000017C) Normal IBI Queue Port Register                             */
16575     __IM uint32_t  NRSQP;              /*!< (@ 0x00000180) Normal Receive Status Queue Port Register                  */
16576     __IM uint32_t  RESERVED14[3];
16577 
16578     union
16579     {
16580         __IOM uint32_t NQTHCTL;         /*!< (@ 0x00000190) Normal Queue Threshold Control Register                    */
16581 
16582         struct
16583         {
16584             __IOM uint32_t CMDQTH  : 8; /*!< [7..0] Normal Command Ready Queue Threshold                               */
16585             __IOM uint32_t RSPQTH  : 8; /*!< [15..8] Normal Response Queue Threshold                                   */
16586             __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size                                     */
16587             __IOM uint32_t IBIQTH  : 8; /*!< [31..24] Normal IBI Queue Threshold                                       */
16588         } NQTHCTL_b;
16589     };
16590 
16591     union
16592     {
16593         __IOM uint32_t NTBTHCTL0;      /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control
16594                                         *                  Register 0                                                 */
16595 
16596         struct
16597         {
16598             __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold                              */
16599             uint32_t              : 5;
16600             __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold                              */
16601             uint32_t              : 5;
16602             __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold                                        */
16603             uint32_t              : 5;
16604             __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold                                        */
16605             uint32_t              : 5;
16606         } NTBTHCTL0_b;
16607     };
16608     __IM uint32_t RESERVED15[10];
16609 
16610     union
16611     {
16612         __IOM uint32_t NRQTHCTL;       /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control
16613                                         *                  Register                                                   */
16614 
16615         struct
16616         {
16617             __IOM uint32_t RSQTH : 8;  /*!< [7..0] Normal Receive Status Queue Threshold                              */
16618             uint32_t             : 24;
16619         } NRQTHCTL_b;
16620     };
16621     __IM uint32_t RESERVED16[3];
16622 
16623     union
16624     {
16625         __IOM uint32_t BST;             /*!< (@ 0x000001D0) Bus Status Register                                        */
16626 
16627         struct
16628         {
16629             __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag                                     */
16630             __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag                                      */
16631             __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag                                    */
16632             uint32_t               : 1;
16633             __IOM uint32_t NACKDF  : 1; /*!< [4..4] NACK Detection Flag                                                */
16634             uint32_t               : 3;
16635             __IOM uint32_t TENDF   : 1; /*!< [8..8] Transmit End Flag                                                  */
16636             uint32_t               : 7;
16637             __IOM uint32_t ALF     : 1; /*!< [16..16] Arbitration Lost Flag                                            */
16638             uint32_t               : 3;
16639             __IOM uint32_t TODF    : 1; /*!< [20..20] Timeout Detection Flag                                           */
16640             uint32_t               : 11;
16641         } BST_b;
16642     };
16643 
16644     union
16645     {
16646         __IOM uint32_t BSTE;            /*!< (@ 0x000001D4) Bus Status Enable Register                                 */
16647 
16648         struct
16649         {
16650             __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable                                   */
16651             __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable                                    */
16652             __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable                                  */
16653             uint32_t               : 1;
16654             __IOM uint32_t NACKDE  : 1; /*!< [4..4] NACK Detection Enable                                              */
16655             uint32_t               : 3;
16656             __IOM uint32_t TENDE   : 1; /*!< [8..8] Transmit End Enable                                                */
16657             uint32_t               : 7;
16658             __IOM uint32_t ALE     : 1; /*!< [16..16] Arbitration Lost Enable                                          */
16659             uint32_t               : 3;
16660             __IOM uint32_t TODE    : 1; /*!< [20..20] Timeout Detection Enable                                         */
16661             uint32_t               : 11;
16662         } BSTE_b;
16663     };
16664 
16665     union
16666     {
16667         __IOM uint32_t BIE;              /*!< (@ 0x000001D8) Bus Interrupt Enable Register                              */
16668 
16669         struct
16670         {
16671             __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable                         */
16672             __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable                          */
16673             __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable                        */
16674             uint32_t                : 1;
16675             __IOM uint32_t NACKDIE  : 1; /*!< [4..4] NACK Detection Interrupt Enable                                    */
16676             uint32_t                : 3;
16677             __IOM uint32_t TENDIE   : 1; /*!< [8..8] Transmit End Interrupt Enable                                      */
16678             uint32_t                : 7;
16679             __IOM uint32_t ALIE     : 1; /*!< [16..16] Arbitration Lost Interrupt Enable                                */
16680             uint32_t                : 3;
16681             __IOM uint32_t TODIE    : 1; /*!< [20..20] Timeout Detection Interrupt Enable                               */
16682             uint32_t                : 11;
16683         } BIE_b;
16684     };
16685 
16686     union
16687     {
16688         __IOM uint32_t BSTFC;           /*!< (@ 0x000001DC) Bus Status Force Register                                  */
16689 
16690         struct
16691         {
16692             __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force                                    */
16693             __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force                                     */
16694             __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force                                   */
16695             uint32_t               : 1;
16696             __OM uint32_t NACKDFC  : 1; /*!< [4..4] NACK Detection Force                                               */
16697             uint32_t               : 3;
16698             __OM uint32_t TENDFC   : 1; /*!< [8..8] Transmit End Force                                                 */
16699             uint32_t               : 7;
16700             __OM uint32_t ALFC     : 1; /*!< [16..16] Arbitration Lost Force                                           */
16701             uint32_t               : 3;
16702             __OM uint32_t TODFC    : 1; /*!< [20..20] Timeout Detection Force                                          */
16703             uint32_t               : 11;
16704         } BSTFC_b;
16705     };
16706 
16707     union
16708     {
16709         __IOM uint32_t NTST;            /*!< (@ 0x000001E0) Normal Transfer Status Register                            */
16710 
16711         struct
16712         {
16713             __IOM uint32_t TDBEF0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0                           */
16714             __IOM uint32_t RDBFF0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0                             */
16715             __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag                                   */
16716             __IOM uint32_t CMDQEF  : 1; /*!< [3..3] Normal Command Queue Empty Flag                                    */
16717             __IOM uint32_t RSPQFF  : 1; /*!< [4..4] Normal Response Queue Full Flag                                    */
16718             __IOM uint32_t TABTF   : 1; /*!< [5..5] Normal Transfer Abort Flag                                         */
16719             uint32_t               : 3;
16720             __IOM uint32_t TEF     : 1; /*!< [9..9] Normal Transfer Error Flag                                         */
16721             uint32_t               : 10;
16722             __IOM uint32_t RSQFF   : 1; /*!< [20..20] Normal Receive Status Queue Full Flag                            */
16723             uint32_t               : 11;
16724         } NTST_b;
16725     };
16726 
16727     union
16728     {
16729         __IOM uint32_t NTSTE;           /*!< (@ 0x000001E4) Normal Transfer Status Enable Register                     */
16730 
16731         struct
16732         {
16733             __IOM uint32_t TDBEE0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0                         */
16734             __IOM uint32_t RDBFE0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0                           */
16735             __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable                                 */
16736             __IOM uint32_t CMDQEE  : 1; /*!< [3..3] Normal Command Queue Empty Enable                                  */
16737             __IOM uint32_t RSPQFE  : 1; /*!< [4..4] Normal Response Queue Full Enable                                  */
16738             __IOM uint32_t TABTE   : 1; /*!< [5..5] Normal Transfer Abort Enable                                       */
16739             uint32_t               : 3;
16740             __IOM uint32_t TEE     : 1; /*!< [9..9] Normal Transfer Error Enable                                       */
16741             uint32_t               : 10;
16742             __IOM uint32_t RSQFE   : 1; /*!< [20..20] Normal Receive Status Queue Full Enable                          */
16743             uint32_t               : 11;
16744         } NTSTE_b;
16745     };
16746 
16747     union
16748     {
16749         __IOM uint32_t NTIE;             /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register                  */
16750 
16751         struct
16752         {
16753             __IOM uint32_t TDBEIE0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0               */
16754             __IOM uint32_t RDBFIE0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0                 */
16755             __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable                       */
16756             __IOM uint32_t CMDQEIE  : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable                        */
16757             __IOM uint32_t RSPQFIE  : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable                        */
16758             __IOM uint32_t TABTIE   : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable                             */
16759             uint32_t                : 3;
16760             __IOM uint32_t TEIE     : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable                             */
16761             uint32_t                : 10;
16762             __IOM uint32_t RSQFIE   : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable                */
16763             uint32_t                : 11;
16764         } NTIE_b;
16765     };
16766 
16767     union
16768     {
16769         __IOM uint32_t NTSTFC;          /*!< (@ 0x000001EC) Normal Transfer Status Force Register                      */
16770 
16771         struct
16772         {
16773             __OM uint32_t TDBEFC0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0                          */
16774             __OM uint32_t RDBFFC0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0                            */
16775             __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force                                  */
16776             __OM uint32_t CMDQEFC  : 1; /*!< [3..3] Normal Command Queue Empty Force                                   */
16777             __OM uint32_t RSPQFFC  : 1; /*!< [4..4] Normal Response Queue Full Force                                   */
16778             __OM uint32_t TABTFC   : 1; /*!< [5..5] Normal Transfer Abort Force                                        */
16779             uint32_t               : 3;
16780             __OM uint32_t TEFC     : 1; /*!< [9..9] Normal Transfer Error Force                                        */
16781             uint32_t               : 10;
16782             __OM uint32_t RSQFFC   : 1; /*!< [20..20] Normal Receive Status Queue Full Force                           */
16783             uint32_t               : 11;
16784         } NTSTFC_b;
16785     };
16786     __IM uint32_t RESERVED17[8];
16787 
16788     union
16789     {
16790         __IM uint32_t BCST;            /*!< (@ 0x00000210) Bus Condition Status Register                              */
16791 
16792         struct
16793         {
16794             __IM uint32_t BFREF : 1;   /*!< [0..0] Bus Free Detection Flag                                            */
16795             __IM uint32_t BAVLF : 1;   /*!< [1..1] Bus Available Detection Flag                                       */
16796             __IM uint32_t BIDLF : 1;   /*!< [2..2] Bus Idle Detection Flag                                            */
16797             uint32_t            : 29;
16798         } BCST_b;
16799     };
16800 
16801     union
16802     {
16803         __IOM uint32_t SVST;           /*!< (@ 0x00000214) Slave Status Register                                      */
16804 
16805         struct
16806         {
16807             __IOM uint32_t GCAF  : 1;  /*!< [0..0] General Call Address Detection Flag                                */
16808             uint32_t             : 4;
16809             __IOM uint32_t HSMCF : 1;  /*!< [5..5] Hs-mode Master Code Detection Flag                                 */
16810             __IOM uint32_t DVIDF : 1;  /*!< [6..6] Device-ID Address Detection Flag                                   */
16811             uint32_t             : 8;
16812             __IOM uint32_t HOAF  : 1;  /*!< [15..15] Host Address Detection Flag                                      */
16813             __IOM uint32_t SVAFn : 1;  /*!< [16..16] Slave Address Detection Flag n (n = 0)                           */
16814             uint32_t             : 15;
16815         } SVST_b;
16816     };
16817 
16818     union
16819     {
16820         __IOM uint32_t WUST;            /*!< (@ 0x00000218) Wake Up Unit Control Register                              */
16821 
16822         struct
16823         {
16824             __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag.               */
16825             uint32_t               : 31;
16826         } WUST_b;
16827     };
16828     __IM uint32_t RESERVED18[2];
16829 
16830     union
16831     {
16832         __IOM uint32_t DATBAS0;         /*!< (@ 0x00000224) Device Address Table Basic Register 0                      */
16833 
16834         struct
16835         {
16836             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
16837             uint32_t               : 5;
16838             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
16839             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
16840             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
16841             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
16842             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
16843             uint32_t               : 5;
16844             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
16845             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
16846         } DATBAS0_b;
16847     };
16848     __IM uint32_t RESERVED19;
16849 
16850     union
16851     {
16852         __IOM uint32_t DATBAS1;         /*!< (@ 0x0000022C) Device Address Table Basic Register 1                      */
16853 
16854         struct
16855         {
16856             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
16857             uint32_t               : 5;
16858             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
16859             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
16860             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
16861             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
16862             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
16863             uint32_t               : 5;
16864             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
16865             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
16866         } DATBAS1_b;
16867     };
16868     __IM uint32_t RESERVED20;
16869 
16870     union
16871     {
16872         __IOM uint32_t DATBAS2;         /*!< (@ 0x00000234) Device Address Table Basic Register 2                      */
16873 
16874         struct
16875         {
16876             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
16877             uint32_t               : 5;
16878             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
16879             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
16880             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
16881             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
16882             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
16883             uint32_t               : 5;
16884             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
16885             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
16886         } DATBAS2_b;
16887     };
16888     __IM uint32_t RESERVED21;
16889 
16890     union
16891     {
16892         __IOM uint32_t DATBAS3;         /*!< (@ 0x0000023C) Device Address Table Basic Register 3                      */
16893 
16894         struct
16895         {
16896             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
16897             uint32_t               : 5;
16898             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
16899             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
16900             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
16901             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
16902             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
16903             uint32_t               : 5;
16904             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
16905             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
16906         } DATBAS3_b;
16907     };
16908     __IM uint32_t RESERVED22[24];
16909 
16910     union
16911     {
16912         __IOM uint32_t EXDATBAS;       /*!< (@ 0x000002A0) Extended Device Address Table Basic Register               */
16913 
16914         struct
16915         {
16916             __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address                                     */
16917             uint32_t              : 9;
16918             __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address                              */
16919             uint32_t              : 5;
16920             __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count                                 */
16921             __IOM uint32_t EDTYP  : 1; /*!< [31..31] Extended Device Type                                             */
16922         } EXDATBAS_b;
16923     };
16924     __IM uint32_t RESERVED23[3];
16925 
16926     union
16927     {
16928         __IOM uint32_t SDATBAS0;         /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0                */
16929 
16930         struct
16931         {
16932             __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
16933             __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
16934             uint32_t               : 1;
16935             __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
16936             uint32_t               : 3;
16937             __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
16938             uint32_t               : 9;
16939         } SDATBAS0_b;
16940     };
16941 
16942     union
16943     {
16944         __IOM uint32_t SDATBAS1;         /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1                */
16945 
16946         struct
16947         {
16948             __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
16949             __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
16950             uint32_t               : 1;
16951             __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
16952             uint32_t               : 3;
16953             __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
16954             uint32_t               : 9;
16955         } SDATBAS1_b;
16956     };
16957 
16958     union
16959     {
16960         __IOM uint32_t SDATBAS2;         /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2                */
16961 
16962         struct
16963         {
16964             __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
16965             __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
16966             uint32_t               : 1;
16967             __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
16968             uint32_t               : 3;
16969             __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
16970             uint32_t               : 9;
16971         } SDATBAS2_b;
16972     };
16973     __IM uint32_t RESERVED24[5];
16974 
16975     union
16976     {
16977         __IOM uint32_t MSDCT0;         /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0              */
16978 
16979         struct
16980         {
16981             uint32_t              : 8;
16982             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
16983             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
16984             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
16985             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
16986             uint32_t              : 2;
16987             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
16988             uint32_t              : 16;
16989         } MSDCT0_b;
16990     };
16991 
16992     union
16993     {
16994         __IOM uint32_t MSDCT1;         /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1              */
16995 
16996         struct
16997         {
16998             uint32_t              : 8;
16999             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
17000             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
17001             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
17002             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
17003             uint32_t              : 2;
17004             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
17005             uint32_t              : 16;
17006         } MSDCT1_b;
17007     };
17008 
17009     union
17010     {
17011         __IOM uint32_t MSDCT2;         /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2              */
17012 
17013         struct
17014         {
17015             uint32_t              : 8;
17016             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
17017             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
17018             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
17019             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
17020             uint32_t              : 2;
17021             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
17022             uint32_t              : 16;
17023         } MSDCT2_b;
17024     };
17025 
17026     union
17027     {
17028         __IOM uint32_t MSDCT3;         /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3              */
17029 
17030         struct
17031         {
17032             uint32_t              : 8;
17033             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
17034             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
17035             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
17036             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
17037             uint32_t              : 2;
17038             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
17039             uint32_t              : 16;
17040         } MSDCT3_b;
17041     };
17042     __IM uint32_t RESERVED25[16];
17043 
17044     union
17045     {
17046         __IOM uint32_t SVDCT;          /*!< (@ 0x00000320) Slave Device Characteristic Table Register                 */
17047 
17048         struct
17049         {
17050             __IOM uint32_t TDCR   : 8; /*!< [7..0] Transfar Device Characteristic Register                            */
17051             __IOM uint32_t TBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
17052             __IOM uint32_t TBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
17053             __IOM uint32_t TBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
17054             __IOM uint32_t TBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
17055             uint32_t              : 2;
17056             __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role                                                      */
17057             uint32_t              : 16;
17058         } SVDCT_b;
17059     };
17060     __IOM uint32_t SDCTPIDL;           /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional
17061                                         *                  ID Low Register                                            */
17062     __IOM uint32_t SDCTPIDH;           /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional
17063                                         *                  ID High Register                                           */
17064     __IM uint32_t RESERVED26;
17065 
17066     union
17067     {
17068         __IM uint32_t SVDVAD0;         /*!< (@ 0x00000330) Slave Device Address Register 0                            */
17069 
17070         struct
17071         {
17072             uint32_t             : 16;
17073             __IM uint32_t SVAD   : 10; /*!< [25..16] Slave Address                                                    */
17074             uint32_t             : 1;
17075             __IM uint32_t SADLG  : 1;  /*!< [27..27] Slave Address Length                                             */
17076             uint32_t             : 2;
17077             __IM uint32_t SSTADV : 1;  /*!< [30..30] Slave Static Address Valid                                       */
17078             __IM uint32_t SDYADV : 1;  /*!< [31..31] Slave Dynamic Address Valid                                      */
17079         } SVDVAD0_b;
17080     };
17081     __IM uint32_t RESERVED27[7];
17082 
17083     union
17084     {
17085         __IOM uint32_t CSECMD;         /*!< (@ 0x00000350) CCC Slave Events Command Register                          */
17086 
17087         struct
17088         {
17089             __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable                                    */
17090             __IOM uint32_t MSRQE  : 1; /*!< [1..1] Mastership Requests Enable                                         */
17091             uint32_t              : 1;
17092             __IOM uint32_t HJEVE  : 1; /*!< [3..3] Hot-Join Event Enable                                              */
17093             uint32_t              : 28;
17094         } CSECMD_b;
17095     };
17096 
17097     union
17098     {
17099         __IOM uint32_t CEACTST;        /*!< (@ 0x00000354) CCC Enter Activity State Register                          */
17100 
17101         struct
17102         {
17103             __IOM uint32_t ACTST : 4;  /*!< [3..0] Activity State                                                     */
17104             uint32_t             : 28;
17105         } CEACTST_b;
17106     };
17107 
17108     union
17109     {
17110         __IOM uint32_t CMWLG;          /*!< (@ 0x00000358) CCC Max Write Length Register                              */
17111 
17112         struct
17113         {
17114             __IOM uint32_t MWLG : 16;  /*!< [15..0] Max Write Length                                                  */
17115             uint32_t            : 16;
17116         } CMWLG_b;
17117     };
17118 
17119     union
17120     {
17121         __IOM uint32_t CMRLG;           /*!< (@ 0x0000035C) CCC Max Read Length Register                               */
17122 
17123         struct
17124         {
17125             __IOM uint32_t MRLG   : 16; /*!< [15..0] Max Read Length                                                   */
17126             __IOM uint32_t IBIPSZ : 8;  /*!< [23..16] IBI Payload Size                                                 */
17127             uint32_t              : 8;
17128         } CMRLG_b;
17129     };
17130 
17131     union
17132     {
17133         __IM uint32_t CETSTMD;         /*!< (@ 0x00000360) CCC Enter Test Mode Register                               */
17134 
17135         struct
17136         {
17137             __IM uint32_t TSTMD : 8;   /*!< [7..0] Test Mode                                                          */
17138             uint32_t            : 24;
17139         } CETSTMD_b;
17140     };
17141 
17142     union
17143     {
17144         __IOM uint32_t CGDVST;         /*!< (@ 0x00000364) CCC Get Device Status Register                             */
17145 
17146         struct
17147         {
17148             __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt                                                  */
17149             uint32_t              : 1;
17150             __IOM uint32_t PRTE   : 1; /*!< [5..5] Protocol Error                                                     */
17151             __IOM uint32_t ACTMD  : 2; /*!< [7..6] Slave Device’s current Activity Mode                             */
17152             __IOM uint32_t VDRSV  : 8; /*!< [15..8] Vendor Reserved                                                   */
17153             uint32_t              : 16;
17154         } CGDVST_b;
17155     };
17156 
17157     union
17158     {
17159         __IOM uint32_t CMDSPW;         /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register                      */
17160 
17161         struct
17162         {
17163             __IOM uint32_t MSWDR : 3;  /*!< [2..0] Maximum Sustained Write Data Rate                                  */
17164             uint32_t             : 29;
17165         } CMDSPW_b;
17166     };
17167 
17168     union
17169     {
17170         __IOM uint32_t CMDSPR;         /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register                       */
17171 
17172         struct
17173         {
17174             __IOM uint32_t MSRDR  : 3; /*!< [2..0] Maximum Sustained Read Data Rate                                   */
17175             __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO)                               */
17176             uint32_t              : 26;
17177         } CMDSPR_b;
17178     };
17179 
17180     union
17181     {
17182         __IOM uint32_t CMDSPT;          /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register                 */
17183 
17184         struct
17185         {
17186             __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time                                      */
17187             uint32_t              : 7;
17188             __IOM uint32_t MRTE   : 1;  /*!< [31..31] Maximum Read Turnaround Time Enable                              */
17189         } CMDSPT_b;
17190     };
17191 
17192     union
17193     {
17194         __IOM uint32_t CETSM;          /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode)
17195                                         *                  Register                                                   */
17196 
17197         struct
17198         {
17199             uint32_t            : 8;
17200             __IOM uint32_t FREQ : 8;   /*!< [15..8] Frequency Byte                                                    */
17201             __IOM uint32_t INAC : 8;   /*!< [23..16] Inaccuracy Byte                                                  */
17202             uint32_t            : 8;
17203         } CETSM_b;
17204     };
17205     __IM uint32_t RESERVED28[2];
17206 
17207     union
17208     {
17209         __IOM uint32_t BITCNT;         /*!< (@ 0x00000380) Bit Count Register                                         */
17210 
17211         struct
17212         {
17213             __IOM uint32_t BCNT  : 5;  /*!< [4..0] Bit Counter                                                        */
17214             uint32_t             : 2;
17215             __OM uint32_t BCNTWP : 1;  /*!< [7..7] BCNT Write Protect                                                 */
17216             uint32_t             : 24;
17217         } BITCNT_b;
17218     };
17219     __IM uint32_t RESERVED29[4];
17220 
17221     union
17222     {
17223         __IM uint32_t NQSTLV;          /*!< (@ 0x00000394) Normal Queue Status Level Register                         */
17224 
17225         struct
17226         {
17227             __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level                                    */
17228             __IM uint32_t RSPQLV  : 8; /*!< [15..8] Normal Response Queue Level                                       */
17229             __IM uint32_t IBIQLV  : 8; /*!< [23..16] Normal IBI Queue Level                                           */
17230             __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count                                          */
17231             uint32_t              : 3;
17232         } NQSTLV_b;
17233     };
17234 
17235     union
17236     {
17237         __IM uint32_t NDBSTLV0;        /*!< (@ 0x00000398) Normal Data Buffer Status Level Register                   */
17238 
17239         struct
17240         {
17241             __IM uint32_t TDBFLV : 8;  /*!< [7..0] Normal Transmit Data Buffer Free Level                             */
17242             __IM uint32_t RDBLV  : 8;  /*!< [15..8] Normal Receive Data Buffer Level                                  */
17243             uint32_t             : 16;
17244         } NDBSTLV0_b;
17245     };
17246     __IM uint32_t RESERVED30[9];
17247 
17248     union
17249     {
17250         __IM uint32_t NRSQSTLV;        /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register          */
17251 
17252         struct
17253         {
17254             __IM uint32_t RSQLV : 8;   /*!< [7..0] Normal Receive Status Queue Level                                  */
17255             uint32_t            : 24;
17256         } NRSQSTLV_b;
17257     };
17258     __IM uint32_t RESERVED31[2];
17259 
17260     union
17261     {
17262         __IM uint32_t PRSTDBG;         /*!< (@ 0x000003CC) Present State Debug Register                               */
17263 
17264         struct
17265         {
17266             __IM uint32_t SCILV : 1;   /*!< [0..0] SCL Line Signal Level                                              */
17267             __IM uint32_t SDILV : 1;   /*!< [1..1] SDA Line Signal Level                                              */
17268             __IM uint32_t SCOLV : 1;   /*!< [2..2] SCL Output Level                                                   */
17269             __IM uint32_t SDOLV : 1;   /*!< [3..3] SDA Output Level                                                   */
17270             uint32_t            : 28;
17271         } PRSTDBG_b;
17272     };
17273 
17274     union
17275     {
17276         __IM uint32_t MSERRCNT;        /*!< (@ 0x000003D0) Master Error Counters Register                             */
17277 
17278         struct
17279         {
17280             __IM uint32_t M2ECNT : 8;  /*!< [7..0] M2 Error Counter                                                   */
17281             uint32_t             : 24;
17282         } MSERRCNT_b;
17283     };
17284 } R_I3C0_Type;                         /*!< Size = 980 (0x3d4)                                                        */
17285 
17286 /* =========================================================================================================================== */
17287 /* ================                                           R_MMF                                           ================ */
17288 /* =========================================================================================================================== */
17289 
17290 /**
17291  * @brief Memory Mirror Function (R_MMF)
17292  */
17293 
17294 typedef struct                         /*!< (@ 0x40001000) R_MMF Structure                                            */
17295 {
17296     union
17297     {
17298         __IOM uint32_t MMSFR;          /*!< (@ 0x00000000) MemMirror Special Function Register                        */
17299 
17300         struct
17301         {
17302             uint32_t                  : 7;
17303             __IOM uint32_t MEMMIRADDR : 16; /*!< [22..7] Specifies the memory mirror address.NOTE: A value cannot
17304                                              *   be set in the low-order 7 bits. These bits are fixed to
17305                                              *   0.                                                                        */
17306             uint32_t          : 1;
17307             __OM uint32_t KEY : 8;          /*!< [31..24] MMSFR Key Code                                                   */
17308         } MMSFR_b;
17309     };
17310 
17311     union
17312     {
17313         __IOM uint32_t MMEN;           /*!< (@ 0x00000004) MemMirror Enable Register                                  */
17314 
17315         struct
17316         {
17317             __IOM uint32_t EN : 1;     /*!< [0..0] Memory Mirror Function Enable                                      */
17318             uint32_t          : 23;
17319             __OM uint32_t KEY : 8;     /*!< [31..24] MMEN Key Code                                                    */
17320         } MMEN_b;
17321     };
17322 } R_MMF_Type;                          /*!< Size = 8 (0x8)                                                            */
17323 
17324 /* =========================================================================================================================== */
17325 /* ================                                        R_MPU_MMPU                                         ================ */
17326 /* =========================================================================================================================== */
17327 
17328 /**
17329  * @brief Bus Master MPU (R_MPU_MMPU)
17330  */
17331 
17332 typedef struct                          /*!< (@ 0x40000000) R_MPU_MMPU Structure                                       */
17333 {
17334     __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers                                   */
17335 } R_MPU_MMPU_Type;                      /*!< Size = 3072 (0xc00)                                                       */
17336 
17337 /* =========================================================================================================================== */
17338 /* ================                                        R_MPU_SMPU                                         ================ */
17339 /* =========================================================================================================================== */
17340 
17341 /**
17342  * @brief Bus Slave MPU (R_MPU_SMPU)
17343  */
17344 
17345 typedef struct                           /*!< (@ 0x40000C00) R_MPU_SMPU Structure                                       */
17346 {
17347     union
17348     {
17349         __IOM uint16_t SMPUCTL;          /*!< (@ 0x00000000) Slave MPU Control Register                                 */
17350 
17351         struct
17352         {
17353             __IOM uint16_t OAD     : 1;  /*!< [0..0] Master Group enable                                                */
17354             __IOM uint16_t PROTECT : 1;  /*!< [1..1] Protection of register                                             */
17355             uint16_t               : 6;
17356             __OM uint16_t KEY      : 8;  /*!< [15..8] Key Code This bit is used to enable or disable rewriting
17357                                           *   of the PROTECT and OAD bit.                                               */
17358         } SMPUCTL_b;
17359     };
17360     __IM uint16_t              RESERVED[7];
17361     __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU                          */
17362 } R_MPU_SMPU_Type;                       /*!< Size = 56 (0x38)                                                          */
17363 
17364 /* =========================================================================================================================== */
17365 /* ================                                        R_MPU_SPMON                                        ================ */
17366 /* =========================================================================================================================== */
17367 
17368 /**
17369  * @brief CPU Stack Pointer Monitor (R_MPU_SPMON)
17370  */
17371 
17372 typedef struct                         /*!< (@ 0x40000D00) R_MPU_SPMON Structure                                      */
17373 {
17374     __IOM R_MPU_SPMON_SP_Type SP[2];   /*!< (@ 0x00000000) Stack Pointer Monitor                                      */
17375 } R_MPU_SPMON_Type;                    /*!< Size = 32 (0x20)                                                          */
17376 
17377 /* =========================================================================================================================== */
17378 /* ================                                          R_MSTP                                           ================ */
17379 /* =========================================================================================================================== */
17380 
17381 /**
17382  * @brief System-Module Stop (R_MSTP)
17383  */
17384 
17385 typedef struct                          /*!< (@ 0x40047000) R_MSTP Structure                                           */
17386 {
17387     union
17388     {
17389         __IOM uint32_t MSTPCRA;         /*!< (@ 0x00000000) Module Stop Control Register A                             */
17390 
17391         struct
17392         {
17393             __IOM uint32_t MSTPA0  : 1; /*!< [0..0] RAM0 Module Stop                                                   */
17394             uint32_t               : 6;
17395             __IOM uint32_t MSTPA7  : 1; /*!< [7..7] Standby RAM Module Stop                                            */
17396             uint32_t               : 14;
17397             __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop              */
17398             uint32_t               : 9;
17399         } MSTPCRA_b;
17400     };
17401 
17402     union
17403     {
17404         __IOM uint32_t MSTPCRB;        /*!< (@ 0x00000004) Module Stop Control Register B                             */
17405 
17406         struct
17407         {
17408             uint32_t               : 1;
17409             __IOM uint32_t MSTPB1  : 1; /*!< [1..1] RCAN1 Module Stop                                                  */
17410             __IOM uint32_t MSTPB2  : 1; /*!< [2..2] RCAN0 Module Stop                                                  */
17411             __IOM uint32_t MSTPB3  : 1; /*!< [3..3] RCEC Module Stop                                                   */
17412             uint32_t               : 1;
17413             __IOM uint32_t MSTPB5  : 1; /*!< [5..5] IrDA Module Stop                                                   */
17414             __IOM uint32_t MSTPB6  : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop                     */
17415             __IOM uint32_t MSTPB7  : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop                                    */
17416             __IOM uint32_t MSTPB8  : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop                                    */
17417             __IOM uint32_t MSTPB9  : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop                                */
17418             uint32_t               : 1;
17419             __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop                */
17420             __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop                */
17421             __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop                                   */
17422             __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop                                   */
17423             __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop                                   */
17424             uint32_t               : 2;
17425             __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop                          */
17426             __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop                        */
17427             uint32_t               : 2;
17428             __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop                     */
17429             __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop                     */
17430             __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop                     */
17431             __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop                     */
17432             __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop                     */
17433             __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop                     */
17434             __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop                     */
17435             __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop                     */
17436             __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop                     */
17437             __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop                     */
17438         } MSTPCRB_b;
17439     };
17440 
17441     union
17442     {
17443         __IOM uint32_t MSTPCRC;         /*!< (@ 0x00000008) Module Stop Control Register C                             */
17444 
17445         struct
17446         {
17447             __IOM uint32_t MSTPC0  : 1; /*!< [0..0] CAC Module Stop                                                    */
17448             __IOM uint32_t MSTPC1  : 1; /*!< [1..1] CRC Calculator Module Stop                                         */
17449             __IOM uint32_t MSTPC2  : 1; /*!< [2..2] Parallel Data Capture Module Stop                                  */
17450             __IOM uint32_t MSTPC3  : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop                          */
17451             __IOM uint32_t MSTPC4  : 1; /*!< [4..4] Segment LCD Controller Module Stop                                 */
17452             __IOM uint32_t MSTPC5  : 1; /*!< [5..5] JPEG codec engine Module Stop                                      */
17453             __IOM uint32_t MSTPC6  : 1; /*!< [6..6] 2DG engine Module Stop                                             */
17454             __IOM uint32_t MSTPC7  : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop                         */
17455             __IOM uint32_t MSTPC8  : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop                         */
17456             __IOM uint32_t MSTPC9  : 1; /*!< [9..9] Sampling Rate Converter Module Stop                                */
17457             uint32_t               : 1;
17458             __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop           */
17459             __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop           */
17460             __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop                               */
17461             __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop                                */
17462             uint32_t               : 5;
17463             __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop                          */
17464             __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop                               */
17465             uint32_t               : 5;
17466             __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop                                                */
17467             __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop                              */
17468             uint32_t               : 2;
17469             __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop                                                  */
17470         } MSTPCRC_b;
17471     };
17472 
17473     union
17474     {
17475         __IOM uint32_t MSTPCRD;         /*!< (@ 0x0000000C) Module Stop Control Register D                             */
17476 
17477         struct
17478         {
17479             __IOM uint32_t MSTPD0 : 1;  /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module
17480                                          *   Stop                                                                      */
17481             __IOM uint32_t MSTPD1 : 1;  /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module
17482                                          *   Stop                                                                      */
17483             __IOM uint32_t MSTPD2 : 1;  /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state
17484                                          *   when the count source is either of PCLKB, PCLKB/2 or PCLKB/8.
17485                                          *   In case the count source is sub-clock or LOCO, this bit
17486                                          *   should be set to 1 except when accessing the registers
17487                                          *   of AGT1.                                                                  */
17488             __IOM uint32_t MSTPD3 : 1;  /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state
17489                                          *   when the count source is either of PCLKB, PCLKB/2 or PCLKB/8.
17490                                          *   In case the count source is sub-clock or LOCO, this bit
17491                                          *   should be set to 1 except when accessing the registers
17492                                          *   of AGT0.                                                                  */
17493             uint32_t               : 1;
17494             __IOM uint32_t MSTPD5  : 1; /*!< [5..5] GPT Lower Module Stop                                              */
17495             __IOM uint32_t MSTPD6  : 1; /*!< [6..6] GPT Higher Module Stop                                             */
17496             uint32_t               : 4;
17497             __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop                         */
17498             __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop                         */
17499             __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop                         */
17500             __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop                                                 */
17501             __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop                               */
17502             __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop                                 */
17503             __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop                      */
17504             uint32_t               : 1;
17505             __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop                                  */
17506             __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop                                 */
17507             uint32_t               : 1;
17508             __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop                                   */
17509             __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop                                              */
17510             __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop                                              */
17511             __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop                                              */
17512             __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop                                              */
17513             __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop                                              */
17514             __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop                                              */
17515             __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop                                        */
17516             uint32_t               : 1;
17517             __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop                                */
17518         } MSTPCRD_b;
17519     };
17520 
17521     union
17522     {
17523         __IOM uint32_t MSTPCRE;        /*!< (@ 0x00000010) Module Stop Control Register E                             */
17524 
17525         struct
17526         {
17527             uint32_t               : 4;
17528             __IOM uint32_t MSTPE4  : 1; /*!< [4..4] KINT Module Stop                                                   */
17529             uint32_t               : 9;
17530             __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module
17531                                          *   Stop                                                                      */
17532             __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module
17533                                          *   Stop                                                                      */
17534             uint32_t               : 6;
17535             __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop                                                 */
17536             __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop                                                 */
17537             __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop                                                 */
17538             __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop                                                 */
17539             __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop                                                 */
17540             __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop                                                 */
17541             __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop                                                 */
17542             __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop                                                 */
17543             __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop                                                 */
17544             __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop                                                 */
17545         } MSTPCRE_b;
17546     };
17547 } R_MSTP_Type;                          /*!< Size = 20 (0x14)                                                          */
17548 
17549 /* =========================================================================================================================== */
17550 /* ================                                          R_OPAMP                                          ================ */
17551 /* =========================================================================================================================== */
17552 
17553 /**
17554  * @brief Operational Amplifier (R_OPAMP)
17555  */
17556 
17557 typedef struct                         /*!< (@ 0x40086000) R_OPAMP Structure                                          */
17558 {
17559     __IM uint8_t RESERVED[8];
17560 
17561     union
17562     {
17563         __IOM uint8_t AMPMC;           /*!< (@ 0x00000008) Operational amplifier mode control register                */
17564 
17565         struct
17566         {
17567             __IOM uint8_t AMPPC0 : 1;  /*!< [0..0] Operational amplifier precharge control status                     */
17568             __IOM uint8_t AMPPC1 : 1;  /*!< [1..1] Operational amplifier precharge control status                     */
17569             __IOM uint8_t AMPPC2 : 1;  /*!< [2..2] Operational amplifier precharge control status                     */
17570             uint8_t              : 4;
17571             __IOM uint8_t AMPSP  : 1;  /*!< [7..7] Operation mode selection                                           */
17572         } AMPMC_b;
17573     };
17574 
17575     union
17576     {
17577         __IOM uint8_t AMPTRM;          /*!< (@ 0x00000009) Operational amplifier trigger mode control register        */
17578 
17579         struct
17580         {
17581             __IOM uint8_t AMPTRM0 : 2; /*!< [1..0] Operational amplifier function activation/stop trigger
17582                                         *   control                                                                   */
17583             __IOM uint8_t AMPTRM1 : 2; /*!< [3..2] Operational amplifier function activation/stop trigger
17584                                         *   control                                                                   */
17585             __IOM uint8_t AMPTRM2 : 2; /*!< [5..4] Operational amplifier function activation/stop trigger
17586                                         *   control                                                                   */
17587             __IOM uint8_t AMPTRM3 : 2; /*!< [7..6] Operational amplifier function activation/stop trigger
17588                                         *   control                                                                   */
17589         } AMPTRM_b;
17590     };
17591 
17592     union
17593     {
17594         __IOM uint8_t AMPTRS;          /*!< (@ 0x0000000A) Operational Amplifier Activation Trigger Select
17595                                         *                  Register                                                   */
17596 
17597         struct
17598         {
17599             __IOM uint8_t AMPTRS : 2;  /*!< [1..0] ELC trigger selection Do not change the value of the
17600                                         *   AMPTRS register after setting the AMPTRM register.                        */
17601             uint8_t : 6;
17602         } AMPTRS_b;
17603     };
17604 
17605     union
17606     {
17607         __IOM uint8_t AMPC;            /*!< (@ 0x0000000B) Operational amplifier control register                     */
17608 
17609         struct
17610         {
17611             __IOM uint8_t AMPE0 : 1;   /*!< [0..0] Operation control of operational amplifier                         */
17612             __IOM uint8_t AMPE1 : 1;   /*!< [1..1] Operation control of operational amplifier                         */
17613             __IOM uint8_t AMPE2 : 1;   /*!< [2..2] Operation control of operational amplifier                         */
17614             __IOM uint8_t AMPE3 : 1;   /*!< [3..3] Operation control of operational amplifier                         */
17615             uint8_t             : 3;
17616             __IOM uint8_t IREFE : 1;   /*!< [7..7] Operation control of operational amplifier reference
17617                                         *   current circuit                                                           */
17618         } AMPC_b;
17619     };
17620 
17621     union
17622     {
17623         __IM uint8_t AMPMON;           /*!< (@ 0x0000000C) Operational amplifier monitor register                     */
17624 
17625         struct
17626         {
17627             __IM uint8_t AMPMON0 : 1;  /*!< [0..0] Operational amplifier status                                       */
17628             __IM uint8_t AMPMON1 : 1;  /*!< [1..1] Operational amplifier status                                       */
17629             __IM uint8_t AMPMON2 : 1;  /*!< [2..2] Operational amplifier status                                       */
17630             __IM uint8_t AMPMON3 : 1;  /*!< [3..3] Operational amplifier status                                       */
17631             uint8_t              : 4;
17632         } AMPMON_b;
17633     };
17634     __IM uint8_t           RESERVED1;
17635     __IOM R_OPAMP_AMP_Type AMP[4];     /*!< (@ 0x0000000E) Input and Output Selectors for Operational Amplifier
17636                                         *                  [0..3]                                                     */
17637 
17638     union
17639     {
17640         __IOM uint8_t AMPCPC;          /*!< (@ 0x0000001A) Operational amplifier switch charge pump control
17641                                         *                  register                                                   */
17642 
17643         struct
17644         {
17645             __IOM uint8_t PUMP0EN : 1; /*!< [0..0] charge pump for AMP0 enable/disable                                */
17646             __IOM uint8_t PUMP1EN : 1; /*!< [1..1] charge pump for AMP1 enable/disable                                */
17647             __IOM uint8_t PUMP2EN : 1; /*!< [2..2] charge pump for AMP2 enable/disable                                */
17648             uint8_t               : 5;
17649         } AMPCPC_b;
17650     };
17651     __IM uint8_t RESERVED2[4];
17652 
17653     union
17654     {
17655         __IOM uint8_t AMPUOTE;         /*!< (@ 0x0000001F) Operational Amplifier User Offset Trimming Enable
17656                                         *                  Register                                                   */
17657 
17658         struct
17659         {
17660             __IOM uint8_t AMP0TE : 1;  /*!< [0..0] AMP0OT write enable                                                */
17661             __IOM uint8_t AMP1TE : 1;  /*!< [1..1] AMP1OT write enable                                                */
17662             __IOM uint8_t AMP2TE : 1;  /*!< [2..2] AMP2OT write enable                                                */
17663             uint8_t              : 5;
17664         } AMPUOTE_b;
17665     };
17666     __IOM R_OPAMP_AMPOT_Type AMPOT[3]; /*!< (@ 0x00000020) Operational Amplifier n Offset Trimming Registers          */
17667 } R_OPAMP_Type;                        /*!< Size = 38 (0x26)                                                          */
17668 
17669 /* =========================================================================================================================== */
17670 /* ================                                           R_PDC                                           ================ */
17671 /* =========================================================================================================================== */
17672 
17673 /**
17674  * @brief Parallel Data Capture Unit (R_PDC)
17675  */
17676 
17677 typedef struct                         /*!< (@ 0x40094000) R_PDC Structure                                            */
17678 {
17679     union
17680     {
17681         __IOM uint32_t PCCR0;          /*!< (@ 0x00000000) PDC Control Register 0                                     */
17682 
17683         struct
17684         {
17685             __IOM uint32_t PCKE   : 1; /*!< [0..0] Channel 0 GTCNT Count Clear                                        */
17686             __IOM uint32_t VPS    : 1; /*!< [1..1] VSYNC Signal Polarity Select                                       */
17687             __IOM uint32_t HPS    : 1; /*!< [2..2] HSYNC Signal Polarity Select                                       */
17688             __OM uint32_t  PRST   : 1; /*!< [3..3] PDC Reset                                                          */
17689             __IOM uint32_t DFIE   : 1; /*!< [4..4] Receive Data Ready Interrupt Enable                                */
17690             __IOM uint32_t FEIE   : 1; /*!< [5..5] Frame End Interrupt Enable                                         */
17691             __IOM uint32_t OVIE   : 1; /*!< [6..6] Overrun Interrupt Enable                                           */
17692             __IOM uint32_t UDRIE  : 1; /*!< [7..7] Underrun Interrupt Enable                                          */
17693             __IOM uint32_t VERIE  : 1; /*!< [8..8] Vertical Line Number Setting Error Interrupt Enable                */
17694             __IOM uint32_t HERIE  : 1; /*!< [9..9] Horizontal Byte Number Setting Error Interrupt Enable              */
17695             __IOM uint32_t PCKOE  : 1; /*!< [10..10] PCKO Output Enable                                               */
17696             __IOM uint32_t PCKDIV : 3; /*!< [13..11] PCKO Frequency Division Ratio Select                             */
17697             __IOM uint32_t EDS    : 1; /*!< [14..14] Endian Select                                                    */
17698             uint32_t              : 17;
17699         } PCCR0_b;
17700     };
17701 
17702     union
17703     {
17704         __IOM uint32_t PCCR1;          /*!< (@ 0x00000004) PDC Control Register 1                                     */
17705 
17706         struct
17707         {
17708             __IOM uint32_t PCE : 1;    /*!< [0..0] PDC Operation Enable                                               */
17709             uint32_t           : 31;
17710         } PCCR1_b;
17711     };
17712 
17713     union
17714     {
17715         __IOM uint32_t PCSR;           /*!< (@ 0x00000008) PDC Status Register                                        */
17716 
17717         struct
17718         {
17719             __IM uint32_t  FBSY  : 1;  /*!< [0..0] Frame Busy Flag                                                    */
17720             __IM uint32_t  FEMPF : 1;  /*!< [1..1] FIFO Empty Flag                                                    */
17721             __IOM uint32_t FEF   : 1;  /*!< [2..2] Frame End Flag                                                     */
17722             __IOM uint32_t OVRF  : 1;  /*!< [3..3] Overrun Flag                                                       */
17723             __IOM uint32_t UDRF  : 1;  /*!< [4..4] Underrun Flag                                                      */
17724             __IOM uint32_t VERF  : 1;  /*!< [5..5] Vertical Line Number Setting Error Flag                            */
17725             __IOM uint32_t HERF  : 1;  /*!< [6..6] Horizontal Byte Number Setting Error Flag                          */
17726             uint32_t             : 25;
17727         } PCSR_b;
17728     };
17729 
17730     union
17731     {
17732         __IM uint32_t PCMONR;          /*!< (@ 0x0000000C) PDC Pin Monitor Register                                   */
17733 
17734         struct
17735         {
17736             __IM uint32_t VSYNC : 1;   /*!< [0..0] VSYNC Signal Status Flag                                           */
17737             __IM uint32_t HSYNC : 1;   /*!< [1..1] HSYNC Signal Status Flag                                           */
17738             uint32_t            : 30;
17739         } PCMONR_b;
17740     };
17741 
17742     union
17743     {
17744         __IM uint32_t PCDR;            /*!< (@ 0x00000010) PDC Receive Data Register                                  */
17745 
17746         struct
17747         {
17748             __IM uint32_t PCDR : 32;   /*!< [31..0] The PDC includes a 32-bit-wide, 22-stage FIFO for the
17749                                         *   storage of captured data. The PCDR register is a 4-byte
17750                                         *   space to which the FIFO is mapped, and four bytes of data
17751                                         *   are read from the PCDR register at a time.                                */
17752         } PCDR_b;
17753     };
17754 
17755     union
17756     {
17757         __IOM uint32_t VCR;            /*!< (@ 0x00000014) Vertical Capture Register                                  */
17758 
17759         struct
17760         {
17761             __IOM uint32_t VST : 12;   /*!< [11..0] Vertical Capture Start Line PositionNumber of the line
17762                                         *   where capture is to start.                                                */
17763             uint32_t           : 4;
17764             __IOM uint32_t VSZ : 12;   /*!< [27..16] Vertical Capture Size Number of lines to be captured.            */
17765             uint32_t           : 4;
17766         } VCR_b;
17767     };
17768 
17769     union
17770     {
17771         __IOM uint32_t HCR;            /*!< (@ 0x00000018) Horizontal Capture Register                                */
17772 
17773         struct
17774         {
17775             __IOM uint32_t HST : 12;   /*!< [11..0] Horizontal Capture Start Byte Position Horizontal position
17776                                         *   in bytes where capture is to start.                                       */
17777             uint32_t           : 4;
17778             __IOM uint32_t HSZ : 12;   /*!< [27..16] Horizontal Capture Size Number of bytes to capture
17779                                         *   horizontally.                                                             */
17780             uint32_t : 4;
17781         } HCR_b;
17782     };
17783 } R_PDC_Type;                          /*!< Size = 28 (0x1c)                                                          */
17784 
17785 /* =========================================================================================================================== */
17786 /* ================                                          R_PORT0                                          ================ */
17787 /* =========================================================================================================================== */
17788 
17789 /**
17790  * @brief I/O Ports (R_PORT0)
17791  */
17792 
17793  #ifndef BSP_OVERRIDE_REG_R_PORT0_TYPE
17794 
17795 typedef struct                         /*!< (@ 0x40040000) R_PORT0 Structure                                          */
17796 {
17797     union
17798     {
17799         union
17800         {
17801             __IOM uint32_t PCNTR1;        /*!< (@ 0x00000000) Port Control Register 1                                    */
17802 
17803             struct
17804             {
17805                 __IOM uint32_t PDR  : 16; /*!< [15..0] Pmn Direction                                                     */
17806                 __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data                                                  */
17807             } PCNTR1_b;
17808         };
17809 
17810         struct
17811         {
17812             union
17813             {
17814                 __IOM uint16_t PODR;           /*!< (@ 0x00000000) Output data register                                       */
17815 
17816                 struct
17817                 {
17818                     __IOM uint16_t PODR0  : 1; /*!< [0..0] Pmn Output Data                                                    */
17819                     __IOM uint16_t PODR1  : 1; /*!< [1..1] Pmn Output Data                                                    */
17820                     __IOM uint16_t PODR2  : 1; /*!< [2..2] Pmn Output Data                                                    */
17821                     __IOM uint16_t PODR3  : 1; /*!< [3..3] Pmn Output Data                                                    */
17822                     __IOM uint16_t PODR4  : 1; /*!< [4..4] Pmn Output Data                                                    */
17823                     __IOM uint16_t PODR5  : 1; /*!< [5..5] Pmn Output Data                                                    */
17824                     __IOM uint16_t PODR6  : 1; /*!< [6..6] Pmn Output Data                                                    */
17825                     __IOM uint16_t PODR7  : 1; /*!< [7..7] Pmn Output Data                                                    */
17826                     __IOM uint16_t PODR8  : 1; /*!< [8..8] Pmn Output Data                                                    */
17827                     __IOM uint16_t PODR9  : 1; /*!< [9..9] Pmn Output Data                                                    */
17828                     __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data                                                  */
17829                     __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data                                                  */
17830                     __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data                                                  */
17831                     __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data                                                  */
17832                     __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data                                                  */
17833                     __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data                                                  */
17834                 } PODR_b;
17835             };
17836 
17837             union
17838             {
17839                 __IOM uint16_t PDR;           /*!< (@ 0x00000002) Data direction register                                    */
17840 
17841                 struct
17842                 {
17843                     __IOM uint16_t PDR0  : 1; /*!< [0..0] Pmn Direction                                                      */
17844                     __IOM uint16_t PDR1  : 1; /*!< [1..1] Pmn Direction                                                      */
17845                     __IOM uint16_t PDR2  : 1; /*!< [2..2] Pmn Direction                                                      */
17846                     __IOM uint16_t PDR3  : 1; /*!< [3..3] Pmn Direction                                                      */
17847                     __IOM uint16_t PDR4  : 1; /*!< [4..4] Pmn Direction                                                      */
17848                     __IOM uint16_t PDR5  : 1; /*!< [5..5] Pmn Direction                                                      */
17849                     __IOM uint16_t PDR6  : 1; /*!< [6..6] Pmn Direction                                                      */
17850                     __IOM uint16_t PDR7  : 1; /*!< [7..7] Pmn Direction                                                      */
17851                     __IOM uint16_t PDR8  : 1; /*!< [8..8] Pmn Direction                                                      */
17852                     __IOM uint16_t PDR9  : 1; /*!< [9..9] Pmn Direction                                                      */
17853                     __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction                                                    */
17854                     __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction                                                    */
17855                     __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction                                                    */
17856                     __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction                                                    */
17857                     __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction                                                    */
17858                     __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction                                                    */
17859                 } PDR_b;
17860             };
17861         };
17862     };
17863 
17864     union
17865     {
17866         union
17867         {
17868             __IM uint32_t PCNTR2;        /*!< (@ 0x00000004) Port Control Register 2                                    */
17869 
17870             struct
17871             {
17872                 __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data                                                    */
17873                 __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data                                             */
17874             } PCNTR2_b;
17875         };
17876 
17877         struct
17878         {
17879             union
17880             {
17881                 __IM uint16_t EIDR;           /*!< (@ 0x00000004) Event input data register                                  */
17882 
17883                 struct
17884                 {
17885                     __IM uint16_t EIDR0  : 1; /*!< [0..0] Pmn Event Input Data                                               */
17886                     __IM uint16_t EIDR1  : 1; /*!< [1..1] Pmn Event Input Data                                               */
17887                     __IM uint16_t EIDR2  : 1; /*!< [2..2] Pmn Event Input Data                                               */
17888                     __IM uint16_t EIDR3  : 1; /*!< [3..3] Pmn Event Input Data                                               */
17889                     __IM uint16_t EIDR4  : 1; /*!< [4..4] Pmn Event Input Data                                               */
17890                     __IM uint16_t EIDR5  : 1; /*!< [5..5] Pmn Event Input Data                                               */
17891                     __IM uint16_t EIDR6  : 1; /*!< [6..6] Pmn Event Input Data                                               */
17892                     __IM uint16_t EIDR7  : 1; /*!< [7..7] Pmn Event Input Data                                               */
17893                     __IM uint16_t EIDR8  : 1; /*!< [8..8] Pmn Event Input Data                                               */
17894                     __IM uint16_t EIDR9  : 1; /*!< [9..9] Pmn Event Input Data                                               */
17895                     __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data                                             */
17896                     __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data                                             */
17897                     __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data                                             */
17898                     __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data                                             */
17899                     __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data                                             */
17900                     __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data                                             */
17901                 } EIDR_b;
17902             };
17903 
17904             union
17905             {
17906                 __IM uint16_t PIDR;           /*!< (@ 0x00000006) Input data register                                        */
17907 
17908                 struct
17909                 {
17910                     __IM uint16_t PIDR0  : 1; /*!< [0..0] Pmn Input Data                                                     */
17911                     __IM uint16_t PIDR1  : 1; /*!< [1..1] Pmn Input Data                                                     */
17912                     __IM uint16_t PIDR2  : 1; /*!< [2..2] Pmn Input Data                                                     */
17913                     __IM uint16_t PIDR3  : 1; /*!< [3..3] Pmn Input Data                                                     */
17914                     __IM uint16_t PIDR4  : 1; /*!< [4..4] Pmn Input Data                                                     */
17915                     __IM uint16_t PIDR5  : 1; /*!< [5..5] Pmn Input Data                                                     */
17916                     __IM uint16_t PIDR6  : 1; /*!< [6..6] Pmn Input Data                                                     */
17917                     __IM uint16_t PIDR7  : 1; /*!< [7..7] Pmn Input Data                                                     */
17918                     __IM uint16_t PIDR8  : 1; /*!< [8..8] Pmn Input Data                                                     */
17919                     __IM uint16_t PIDR9  : 1; /*!< [9..9] Pmn Input Data                                                     */
17920                     __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data                                                   */
17921                     __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data                                                   */
17922                     __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data                                                   */
17923                     __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data                                                   */
17924                     __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data                                                   */
17925                     __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data                                                   */
17926                 } PIDR_b;
17927             };
17928         };
17929     };
17930 
17931     union
17932     {
17933         union
17934         {
17935             __OM uint32_t PCNTR3;        /*!< (@ 0x00000008) Port Control Register 3                                    */
17936 
17937             struct
17938             {
17939                 __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set                                                    */
17940                 __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset                                                 */
17941             } PCNTR3_b;
17942         };
17943 
17944         struct
17945         {
17946             union
17947             {
17948                 __OM uint16_t PORR;           /*!< (@ 0x00000008) Output set register                                        */
17949 
17950                 struct
17951                 {
17952                     __OM uint16_t PORR0  : 1; /*!< [0..0] Pmn Output Reset                                                   */
17953                     __OM uint16_t PORR1  : 1; /*!< [1..1] Pmn Output Reset                                                   */
17954                     __OM uint16_t PORR2  : 1; /*!< [2..2] Pmn Output Reset                                                   */
17955                     __OM uint16_t PORR3  : 1; /*!< [3..3] Pmn Output Reset                                                   */
17956                     __OM uint16_t PORR4  : 1; /*!< [4..4] Pmn Output Reset                                                   */
17957                     __OM uint16_t PORR5  : 1; /*!< [5..5] Pmn Output Reset                                                   */
17958                     __OM uint16_t PORR6  : 1; /*!< [6..6] Pmn Output Reset                                                   */
17959                     __OM uint16_t PORR7  : 1; /*!< [7..7] Pmn Output Reset                                                   */
17960                     __OM uint16_t PORR8  : 1; /*!< [8..8] Pmn Output Reset                                                   */
17961                     __OM uint16_t PORR9  : 1; /*!< [9..9] Pmn Output Reset                                                   */
17962                     __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset                                                 */
17963                     __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset                                                 */
17964                     __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset                                                 */
17965                     __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset                                                 */
17966                     __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset                                                 */
17967                     __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset                                                 */
17968                 } PORR_b;
17969             };
17970 
17971             union
17972             {
17973                 __OM uint16_t POSR;           /*!< (@ 0x0000000A) Output reset register                                      */
17974 
17975                 struct
17976                 {
17977                     __OM uint16_t POSR0  : 1; /*!< [0..0] Pmn Output Set                                                     */
17978                     __OM uint16_t POSR1  : 1; /*!< [1..1] Pmn Output Set                                                     */
17979                     __OM uint16_t POSR2  : 1; /*!< [2..2] Pmn Output Set                                                     */
17980                     __OM uint16_t POSR3  : 1; /*!< [3..3] Pmn Output Set                                                     */
17981                     __OM uint16_t POSR4  : 1; /*!< [4..4] Pmn Output Set                                                     */
17982                     __OM uint16_t POSR5  : 1; /*!< [5..5] Pmn Output Set                                                     */
17983                     __OM uint16_t POSR6  : 1; /*!< [6..6] Pmn Output Set                                                     */
17984                     __OM uint16_t POSR7  : 1; /*!< [7..7] Pmn Output Set                                                     */
17985                     __OM uint16_t POSR8  : 1; /*!< [8..8] Pmn Output Set                                                     */
17986                     __OM uint16_t POSR9  : 1; /*!< [9..9] Pmn Output Set                                                     */
17987                     __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set                                                   */
17988                     __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set                                                   */
17989                     __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set                                                   */
17990                     __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set                                                   */
17991                     __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set                                                   */
17992                     __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set                                                   */
17993                 } POSR_b;
17994             };
17995         };
17996     };
17997 
17998     union
17999     {
18000         union
18001         {
18002             __IOM uint32_t PCNTR4;        /*!< (@ 0x0000000C) Port Control Register 4                                    */
18003 
18004             struct
18005             {
18006                 __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set                                              */
18007                 __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset                                           */
18008             } PCNTR4_b;
18009         };
18010 
18011         struct
18012         {
18013             union
18014             {
18015                 __IOM uint16_t EORR;           /*!< (@ 0x0000000C) Event output set register                                  */
18016 
18017                 struct
18018                 {
18019                     __IOM uint16_t EORR0  : 1; /*!< [0..0] Pmn Event Output Reset                                             */
18020                     __IOM uint16_t EORR1  : 1; /*!< [1..1] Pmn Event Output Reset                                             */
18021                     __IOM uint16_t EORR2  : 1; /*!< [2..2] Pmn Event Output Reset                                             */
18022                     __IOM uint16_t EORR3  : 1; /*!< [3..3] Pmn Event Output Reset                                             */
18023                     __IOM uint16_t EORR4  : 1; /*!< [4..4] Pmn Event Output Reset                                             */
18024                     __IOM uint16_t EORR5  : 1; /*!< [5..5] Pmn Event Output Reset                                             */
18025                     __IOM uint16_t EORR6  : 1; /*!< [6..6] Pmn Event Output Reset                                             */
18026                     __IOM uint16_t EORR7  : 1; /*!< [7..7] Pmn Event Output Reset                                             */
18027                     __IOM uint16_t EORR8  : 1; /*!< [8..8] Pmn Event Output Reset                                             */
18028                     __IOM uint16_t EORR9  : 1; /*!< [9..9] Pmn Event Output Reset                                             */
18029                     __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset                                           */
18030                     __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset                                           */
18031                     __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset                                           */
18032                     __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset                                           */
18033                     __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset                                           */
18034                     __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset                                           */
18035                 } EORR_b;
18036             };
18037 
18038             union
18039             {
18040                 __IOM uint16_t EOSR;           /*!< (@ 0x0000000E) Event output reset register                                */
18041 
18042                 struct
18043                 {
18044                     __IOM uint16_t EOSR0  : 1; /*!< [0..0] Pmn Event Output Set                                               */
18045                     __IOM uint16_t EOSR1  : 1; /*!< [1..1] Pmn Event Output Set                                               */
18046                     __IOM uint16_t EOSR2  : 1; /*!< [2..2] Pmn Event Output Set                                               */
18047                     __IOM uint16_t EOSR3  : 1; /*!< [3..3] Pmn Event Output Set                                               */
18048                     __IOM uint16_t EOSR4  : 1; /*!< [4..4] Pmn Event Output Set                                               */
18049                     __IOM uint16_t EOSR5  : 1; /*!< [5..5] Pmn Event Output Set                                               */
18050                     __IOM uint16_t EOSR6  : 1; /*!< [6..6] Pmn Event Output Set                                               */
18051                     __IOM uint16_t EOSR7  : 1; /*!< [7..7] Pmn Event Output Set                                               */
18052                     __IOM uint16_t EOSR8  : 1; /*!< [8..8] Pmn Event Output Set                                               */
18053                     __IOM uint16_t EOSR9  : 1; /*!< [9..9] Pmn Event Output Set                                               */
18054                     __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set                                             */
18055                     __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set                                             */
18056                     __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set                                             */
18057                     __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set                                             */
18058                     __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set                                             */
18059                     __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set                                             */
18060                 } EOSR_b;
18061             };
18062         };
18063     };
18064 } R_PORT0_Type;                        /*!< Size = 16 (0x10)                                                          */
18065 
18066  #endif
18067 
18068 /* =========================================================================================================================== */
18069 /* ================                                           R_PFS                                           ================ */
18070 /* =========================================================================================================================== */
18071 
18072 /**
18073  * @brief I/O Ports-PFS (R_PFS)
18074  */
18075 
18076 typedef struct                         /*!< (@ 0x40040800) R_PFS Structure                                            */
18077 {
18078     __IOM R_PFS_PORT_Type PORT[15];    /*!< (@ 0x00000000) Port [0..14]                                               */
18079 } R_PFS_Type;                          /*!< Size = 960 (0x3c0)                                                        */
18080 
18081 /* =========================================================================================================================== */
18082 /* ================                                          R_PMISC                                          ================ */
18083 /* =========================================================================================================================== */
18084 
18085 /**
18086  * @brief I/O Ports-MISC (R_PMISC)
18087  */
18088 
18089  #ifndef BSP_OVERRIDE_REG_R_PMISC_TYPE
18090 
18091 typedef struct                         /*!< (@ 0x40040D00) R_PMISC Structure                                          */
18092 {
18093     union
18094     {
18095         __IOM uint8_t PFENET;          /*!< (@ 0x00000000) Ethernet Control Register                                  */
18096 
18097         struct
18098         {
18099             uint8_t                : 4;
18100             __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0                                          */
18101             __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1                                          */
18102             uint8_t                : 2;
18103         } PFENET_b;
18104     };
18105     __IM uint8_t RESERVED[2];
18106 
18107     union
18108     {
18109         __IOM uint8_t PWPR;            /*!< (@ 0x00000003) Write-Protect Register                                     */
18110 
18111         struct
18112         {
18113             uint8_t             : 6;
18114             __IOM uint8_t PFSWE : 1;   /*!< [6..6] PmnPFS Register Write                                              */
18115             __IOM uint8_t B0WI  : 1;   /*!< [7..7] PFSWE Bit Write Disable                                            */
18116         } PWPR_b;
18117     };
18118     __IM uint8_t RESERVED1;
18119 
18120     union
18121     {
18122         __IOM uint8_t PWPRS;           /*!< (@ 0x00000005) Write-Protect Register for Secure                          */
18123 
18124         struct
18125         {
18126             uint8_t             : 6;
18127             __IOM uint8_t PFSWE : 1;    /*!< [6..6] PmnPFS Register Write                                              */
18128             __IOM uint8_t B0WI  : 1;    /*!< [7..7] PFSWE Bit Write Disable                                            */
18129         } PWPRS_b;
18130     };
18131     __IM uint16_t            RESERVED2[5];
18132     __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register                         */
18133 } R_PMISC_Type;                         /*!< Size = 40 (0x28)                                                          */
18134 
18135  #endif
18136 
18137 /* =========================================================================================================================== */
18138 /* ================                                          R_QSPI                                           ================ */
18139 /* =========================================================================================================================== */
18140 
18141 /**
18142  * @brief Quad Serial Peripheral Interface (R_QSPI)
18143  */
18144 
18145 typedef struct                         /*!< (@ 0x64000000) R_QSPI Structure                                           */
18146 {
18147     union
18148     {
18149         __IOM uint32_t SFMSMD;         /*!< (@ 0x00000000) Transfer Mode Control Register                             */
18150 
18151         struct
18152         {
18153             __IOM uint32_t SFMRM  : 3; /*!< [2..0] Serial interface read mode selection                               */
18154             uint32_t              : 1;
18155             __IOM uint32_t SFMSE  : 2; /*!< [5..4] Selection of the prefetch function                                 */
18156             __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function                                 */
18157             __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations
18158                                         *   other than on byte boundaries                                             */
18159             __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by
18160                                         *   input to CFGMD3.                                                          */
18161             __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for
18162                                         *   the serial interface                                                      */
18163             __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission                     */
18164             __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission                    */
18165             uint32_t              : 3;
18166             __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection.                                 */
18167             uint32_t              : 16;
18168         } SFMSMD_b;
18169     };
18170 
18171     union
18172     {
18173         __IOM uint32_t SFMSSC;         /*!< (@ 0x00000004) Chip Selection Control Register                            */
18174 
18175         struct
18176         {
18177             __IOM uint32_t SFMSW  : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal         */
18178             __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection                               */
18179             __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection                                */
18180             uint32_t              : 26;
18181         } SFMSSC_b;
18182     };
18183 
18184     union
18185     {
18186         __IOM uint32_t SFMSKC;         /*!< (@ 0x00000008) Clock Control Register                                     */
18187 
18188         struct
18189         {
18190             __IOM uint32_t SFMDV : 5;  /*!< [4..0] Serial interface reference cycle selection (* Pay attention
18191                                         *   to the irregularity.)NOTE: When PCLKA multiplied by an
18192                                         *   odd number is selected, the high-level width of the SCK
18193                                         *   signal is longer than the low-level width by 1 x PCLKA
18194                                         *   before duty ratio correction.                                             */
18195             __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the
18196                                         *   SCK signal                                                                */
18197             uint32_t : 26;
18198         } SFMSKC_b;
18199     };
18200 
18201     union
18202     {
18203         __IM uint32_t SFMSST;          /*!< (@ 0x0000000C) Status Register                                            */
18204 
18205         struct
18206         {
18207             __IM uint32_t PFCNT : 5;   /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010
18208                                         *   (No combination other than the above is available.)                       */
18209             uint32_t            : 1;
18210             __IM uint32_t PFFUL : 1;   /*!< [6..6] Prefetch buffer state                                              */
18211             __IM uint32_t PFOFF : 1;   /*!< [7..7] Prefetch function operation state                                  */
18212             uint32_t            : 24;
18213         } SFMSST_b;
18214     };
18215 
18216     union
18217     {
18218         __IOM uint32_t SFMCOM;         /*!< (@ 0x00000010) Communication Port Register                                */
18219 
18220         struct
18221         {
18222             __IOM uint32_t SFMD : 8;   /*!< [7..0] Port for direct communication with the SPI bus.Input/output
18223                                         *   to and from this port is converted to a SPIbus cycle. This
18224                                         *   port is accessible in the direct communication mode (DCOM=1)
18225                                         *   only.Access to this port is ignored in the ROM access mode.               */
18226             uint32_t : 24;
18227         } SFMCOM_b;
18228     };
18229 
18230     union
18231     {
18232         __IOM uint32_t SFMCMD;         /*!< (@ 0x00000014) Communication Mode Control Register                        */
18233 
18234         struct
18235         {
18236             __IOM uint32_t DCOM : 1;   /*!< [0..0] Selection of a mode of communication with the SPI bus              */
18237             uint32_t            : 31;
18238         } SFMCMD_b;
18239     };
18240 
18241     union
18242     {
18243         __IOM uint32_t SFMCST;         /*!< (@ 0x00000018) Communication Status Register                              */
18244 
18245         struct
18246         {
18247             __IM uint32_t COMBSY : 1;  /*!< [0..0] SPI bus cycle completion state in direct communication             */
18248             uint32_t             : 6;
18249             __IM uint32_t EROMR  : 1;  /*!< [7..7] Status of ROM access detection in the direct communication
18250                                         *   modeNOTE: Writing of 0 only is possible. Writing of 1 is
18251                                         *   ignored.                                                                  */
18252             uint32_t : 24;
18253         } SFMCST_b;
18254     };
18255     __IM uint32_t RESERVED;
18256 
18257     union
18258     {
18259         __IOM uint32_t SFMSIC;         /*!< (@ 0x00000020) Instruction Code Register                                  */
18260 
18261         struct
18262         {
18263             __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute                          */
18264             uint32_t              : 24;
18265         } SFMSIC_b;
18266     };
18267 
18268     union
18269     {
18270         __IOM uint32_t SFMSAC;         /*!< (@ 0x00000024) Address Mode Control Register                              */
18271 
18272         struct
18273         {
18274             __IOM uint32_t SFMAS  : 2; /*!< [1..0] Selection the number of address bits of the serial interface       */
18275             uint32_t              : 2;
18276             __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial
18277                                         *   Interface address width is selected 4 bytes.                              */
18278             uint32_t : 27;
18279         } SFMSAC_b;
18280     };
18281 
18282     union
18283     {
18284         __IOM uint32_t SFMSDC;         /*!< (@ 0x00000028) Dummy Cycle Control Register                               */
18285 
18286         struct
18287         {
18288             __IOM uint32_t SFMDN : 4;  /*!< [3..0] Selection of the number of dummy cycles of Fast Read
18289                                         *   instructions                                                              */
18290             uint32_t              : 2;
18291             __IM uint32_t  SFMXST : 1; /*!< [6..6] XIP mode status                                                    */
18292             __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission                                                */
18293             __IOM uint32_t SFMXD  : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode)                      */
18294             uint32_t              : 16;
18295         } SFMSDC_b;
18296     };
18297     __IM uint32_t RESERVED1;
18298 
18299     union
18300     {
18301         __IOM uint32_t SFMSPC;         /*!< (@ 0x00000030) SPI Protocol Control Register                              */
18302 
18303         struct
18304         {
18305             __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol
18306                                         *   is required to be set by software separately.                             */
18307             uint32_t              : 2;
18308             __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch,
18309                                         *   when Dual SPI protocol or Quad SPI protocol is selected.                  */
18310             uint32_t : 27;
18311         } SFMSPC_b;
18312     };
18313 
18314     union
18315     {
18316         __IOM uint32_t SFMPMD;         /*!< (@ 0x00000034) Port Control Register                                      */
18317 
18318         struct
18319         {
18320             uint32_t              : 2;
18321             __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin                                            */
18322             uint32_t              : 29;
18323         } SFMPMD_b;
18324     };
18325     __IM uint32_t RESERVED2[499];
18326 
18327     union
18328     {
18329         __IOM uint32_t SFMCNT1;        /*!< (@ 0x00000804) External QSPI Address Register 1                           */
18330 
18331         struct
18332         {
18333             uint32_t                : 26;
18334             __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000
18335                                           *   to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order
18336                                           *   6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited.                   */
18337         } SFMCNT1_b;
18338     };
18339 } R_QSPI_Type;                           /*!< Size = 2056 (0x808)                                                       */
18340 
18341 /* =========================================================================================================================== */
18342 /* ================                                           R_RTC                                           ================ */
18343 /* =========================================================================================================================== */
18344 
18345 /**
18346  * @brief Realtime Clock (R_RTC)
18347  */
18348 
18349 typedef struct                         /*!< (@ 0x40044000) R_RTC Structure                                            */
18350 {
18351     union
18352     {
18353         __IM uint8_t R64CNT;           /*!< (@ 0x00000000) 64-Hz Counter                                              */
18354 
18355         struct
18356         {
18357             __IM uint8_t F64HZ : 1;    /*!< [0..0] 64Hz                                                               */
18358             __IM uint8_t F32HZ : 1;    /*!< [1..1] 32Hz                                                               */
18359             __IM uint8_t F16HZ : 1;    /*!< [2..2] 16Hz                                                               */
18360             __IM uint8_t F8HZ  : 1;    /*!< [3..3] 8Hz                                                                */
18361             __IM uint8_t F4HZ  : 1;    /*!< [4..4] 4Hz                                                                */
18362             __IM uint8_t F2HZ  : 1;    /*!< [5..5] 2Hz                                                                */
18363             __IM uint8_t F1HZ  : 1;    /*!< [6..6] 1Hz                                                                */
18364             uint8_t            : 1;
18365         } R64CNT_b;
18366     };
18367     __IM uint8_t RESERVED;
18368 
18369     union
18370     {
18371         union
18372         {
18373             __IOM uint8_t RSECCNT;       /*!< (@ 0x00000002) Second Counter                                             */
18374 
18375             struct
18376             {
18377                 __IOM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When
18378                                           *   a carry is generated, 1 is added to the tens place.                       */
18379                 __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting.         */
18380                 uint8_t             : 1;
18381             } RSECCNT_b;
18382         };
18383 
18384         union
18385         {
18386             __IOM uint8_t BCNT0;         /*!< (@ 0x00000002) Binary Counter 0                                           */
18387 
18388             struct
18389             {
18390                 __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary
18391                                           *   counter b7 to b0.                                                         */
18392             } BCNT0_b;
18393         };
18394     };
18395     __IM uint8_t RESERVED1;
18396 
18397     union
18398     {
18399         union
18400         {
18401             __IOM uint8_t RMINCNT;       /*!< (@ 0x00000004) Minute Counter                                             */
18402 
18403             struct
18404             {
18405                 __IOM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When
18406                                           *   a carry is generated, 1 is added to the tens place.                       */
18407                 __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting.         */
18408                 uint8_t             : 1;
18409             } RMINCNT_b;
18410         };
18411 
18412         union
18413         {
18414             __IOM uint8_t BCNT1;         /*!< (@ 0x00000004) Binary Counter 1                                           */
18415 
18416             struct
18417             {
18418                 __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary
18419                                           *   counter b15 to b8.                                                        */
18420             } BCNT1_b;
18421         };
18422     };
18423     __IM uint8_t RESERVED2;
18424 
18425     union
18426     {
18427         union
18428         {
18429             __IOM uint8_t RHRCNT;       /*!< (@ 0x00000006) Hour Counter                                               */
18430 
18431             struct
18432             {
18433                 __IOM uint8_t HR1 : 4;  /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a
18434                                          *   carry is generated, 1 is added to the tens place.                         */
18435                 __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from
18436                                          *   the ones place.                                                           */
18437                 __IOM uint8_t PM : 1;   /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
18438                 uint8_t          : 1;
18439             } RHRCNT_b;
18440         };
18441 
18442         union
18443         {
18444             __IOM uint8_t BCNT2;         /*!< (@ 0x00000006) Binary Counter 2                                           */
18445 
18446             struct
18447             {
18448                 __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary
18449                                           *   counter b23 to b16.                                                       */
18450             } BCNT2_b;
18451         };
18452     };
18453     __IM uint8_t RESERVED3;
18454 
18455     union
18456     {
18457         union
18458         {
18459             __IOM uint8_t RWKCNT;       /*!< (@ 0x00000008) Day-of-Week Counter                                        */
18460 
18461             struct
18462             {
18463                 __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
18464                 uint8_t            : 5;
18465             } RWKCNT_b;
18466         };
18467 
18468         union
18469         {
18470             __IOM uint8_t BCNT3;         /*!< (@ 0x00000008) Binary Counter 3                                           */
18471 
18472             struct
18473             {
18474                 __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary
18475                                           *   counter b31 to b24.                                                       */
18476             } BCNT3_b;
18477         };
18478     };
18479     __IM uint8_t RESERVED4;
18480 
18481     union
18482     {
18483         __IOM uint8_t RDAYCNT;         /*!< (@ 0x0000000A) Day Counter                                                */
18484 
18485         struct
18486         {
18487             __IOM uint8_t DATE1 : 4;   /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry
18488                                         *   is generated, 1 is added to the tens place.                               */
18489             __IOM uint8_t DATE10 : 2;  /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the
18490                                         *   ones place.                                                               */
18491             uint8_t : 2;
18492         } RDAYCNT_b;
18493     };
18494     __IM uint8_t RESERVED5;
18495 
18496     union
18497     {
18498         __IOM uint8_t RMONCNT;         /*!< (@ 0x0000000C) Month Counter                                              */
18499 
18500         struct
18501         {
18502             __IOM uint8_t MON1 : 4;    /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When
18503                                         *   a carry is generated, 1 is added to the tens place.                       */
18504             __IOM uint8_t MON10 : 1;   /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from
18505                                         *   the ones place.                                                           */
18506             uint8_t : 3;
18507         } RMONCNT_b;
18508     };
18509     __IM uint8_t RESERVED6;
18510 
18511     union
18512     {
18513         __IOM uint16_t RYRCNT;         /*!< (@ 0x0000000E) Year Counter                                               */
18514 
18515         struct
18516         {
18517             __IOM uint16_t YR1 : 4;    /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a
18518                                         *   carry is generated, 1 is added to the tens place.                         */
18519             __IOM uint16_t YR10 : 4;   /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from
18520                                         *   ones place. When a carry is generated in the tens place,
18521                                         *   1 is added to the hundreds place.                                         */
18522             uint16_t : 8;
18523         } RYRCNT_b;
18524     };
18525 
18526     union
18527     {
18528         union
18529         {
18530             __IOM uint8_t RSECAR;        /*!< (@ 0x00000010) Second Alarm Register                                      */
18531 
18532             struct
18533             {
18534                 __OM uint8_t  SEC1  : 4; /*!< [3..0] 1-Second Value for the ones place of seconds                       */
18535                 __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds                     */
18536                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
18537             } RSECAR_b;
18538         };
18539 
18540         union
18541         {
18542             __IOM uint8_t BCNT0AR;         /*!< (@ 0x00000010) Binary Counter 0 Alarm Register                            */
18543 
18544             struct
18545             {
18546                 __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register
18547                                             *   corresponding to 32-bit binary counter b7 to b0.                          */
18548             } BCNT0AR_b;
18549         };
18550     };
18551     __IM uint8_t RESERVED7;
18552 
18553     union
18554     {
18555         union
18556         {
18557             __IOM uint8_t RMINAR;        /*!< (@ 0x00000012) Minute Alarm Register                                      */
18558 
18559             struct
18560             {
18561                 __IOM uint8_t MIN1  : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes                 */
18562                 __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes                */
18563                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
18564             } RMINAR_b;
18565         };
18566 
18567         union
18568         {
18569             __IOM uint8_t BCNT1AR;         /*!< (@ 0x00000012) Binary Counter 1 Alarm Register                            */
18570 
18571             struct
18572             {
18573                 __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register
18574                                             *   corresponding to 32-bit binary counter b15 to b8.                         */
18575             } BCNT1AR_b;
18576         };
18577     };
18578     __IM uint8_t RESERVED8;
18579 
18580     union
18581     {
18582         union
18583         {
18584             __IOM uint8_t RHRAR;        /*!< (@ 0x00000014) Hour Alarm Register                                        */
18585 
18586             struct
18587             {
18588                 __IOM uint8_t HR1  : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours                     */
18589                 __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours                    */
18590                 __IOM uint8_t PM   : 1; /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
18591                 __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
18592             } RHRAR_b;
18593         };
18594 
18595         union
18596         {
18597             __IOM uint8_t BCNT2AR;         /*!< (@ 0x00000014) Binary Counter 2 Alarm Register                            */
18598 
18599             struct
18600             {
18601                 __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary
18602                                             *   counter b23 to b16.                                                       */
18603             } BCNT2AR_b;
18604         };
18605     };
18606     __IM uint8_t RESERVED9;
18607 
18608     union
18609     {
18610         union
18611         {
18612             __IOM uint8_t RWKAR;        /*!< (@ 0x00000016) Day-of-Week Alarm Register                                 */
18613 
18614             struct
18615             {
18616                 __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
18617                 uint8_t            : 4;
18618                 __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
18619             } RWKAR_b;
18620         };
18621 
18622         union
18623         {
18624             __IOM uint8_t BCNT3AR;         /*!< (@ 0x00000016) Binary Counter 3 Alarm Register                            */
18625 
18626             struct
18627             {
18628                 __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary
18629                                             *   counter b31 to b24.                                                       */
18630             } BCNT3AR_b;
18631         };
18632     };
18633     __IM uint8_t RESERVED10;
18634 
18635     union
18636     {
18637         union
18638         {
18639             __IOM uint8_t RDAYAR;         /*!< (@ 0x00000018) Date Alarm Register                                        */
18640 
18641             struct
18642             {
18643                 __IOM uint8_t DATE1  : 4; /*!< [3..0] 1 Day Value for the ones place of days                             */
18644                 __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days                           */
18645                 uint8_t              : 1;
18646                 __IOM uint8_t ENB    : 1; /*!< [7..7] Compare enable                                                     */
18647             } RDAYAR_b;
18648         };
18649 
18650         union
18651         {
18652             __IOM uint8_t BCNT0AER;    /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register                     */
18653 
18654             struct
18655             {
18656                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register
18657                                         *   for setting the alarm enable corresponding to 32-bit binary
18658                                         *   counter b7 to b0.                                                         */
18659             } BCNT0AER_b;
18660         };
18661     };
18662     __IM uint8_t RESERVED11;
18663 
18664     union
18665     {
18666         union
18667         {
18668             __IOM uint8_t RMONAR;        /*!< (@ 0x0000001A) Month Alarm Register                                       */
18669 
18670             struct
18671             {
18672                 __IOM uint8_t MON1  : 4; /*!< [3..0] 1 Month Value for the ones place of months                         */
18673                 __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months                       */
18674                 uint8_t             : 2;
18675                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
18676             } RMONAR_b;
18677         };
18678 
18679         union
18680         {
18681             __IOM uint8_t BCNT1AER;    /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register                     */
18682 
18683             struct
18684             {
18685                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register
18686                                         *   for setting the alarm enable corresponding to 32-bit binary
18687                                         *   counter b15 to b8.                                                        */
18688             } BCNT1AER_b;
18689         };
18690     };
18691     __IM uint8_t RESERVED12;
18692 
18693     union
18694     {
18695         union
18696         {
18697             __IOM uint16_t RYRAR;        /*!< (@ 0x0000001C) Year Alarm Register                                        */
18698 
18699             struct
18700             {
18701                 __IOM uint16_t YR1  : 4; /*!< [3..0] 1 Year Value for the ones place of years                           */
18702                 __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years                         */
18703                 uint16_t            : 8;
18704             } RYRAR_b;
18705         };
18706 
18707         union
18708         {
18709             __IOM uint16_t BCNT2AER;    /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register                     */
18710 
18711             struct
18712             {
18713                 __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register
18714                                          *   for setting the alarm enable corresponding to 32-bit binary
18715                                          *   counter b23 to b16.                                                       */
18716                 uint16_t : 8;
18717             } BCNT2AER_b;
18718         };
18719     };
18720 
18721     union
18722     {
18723         union
18724         {
18725             __IOM uint8_t RYRAREN;     /*!< (@ 0x0000001E) Year Alarm Enable Register                                 */
18726 
18727             struct
18728             {
18729                 uint8_t           : 7;
18730                 __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable                                                     */
18731             } RYRAREN_b;
18732         };
18733 
18734         union
18735         {
18736             __IOM uint8_t BCNT3AER;    /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register                     */
18737 
18738             struct
18739             {
18740                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register
18741                                         *   for setting the alarm enable corresponding to 32-bit binary
18742                                         *   counter b31 to b24.                                                       */
18743             } BCNT3AER_b;
18744         };
18745     };
18746     __IM uint8_t  RESERVED13;
18747     __IM uint16_t RESERVED14;
18748 
18749     union
18750     {
18751         __IOM uint8_t RCR1;            /*!< (@ 0x00000022) RTC Control Register 1                                     */
18752 
18753         struct
18754         {
18755             __IOM uint8_t AIE   : 1;   /*!< [0..0] Alarm Interrupt Enable                                             */
18756             __IOM uint8_t CIE   : 1;   /*!< [1..1] Carry Interrupt Enable                                             */
18757             __IOM uint8_t PIE   : 1;   /*!< [2..2] Periodic Interrupt Enable                                          */
18758             __IOM uint8_t RTCOS : 1;   /*!< [3..3] RTCOUT Output Select                                               */
18759             __IOM uint8_t PES   : 4;   /*!< [7..4] Periodic Interrupt Select                                          */
18760         } RCR1_b;
18761     };
18762     __IM uint8_t RESERVED15;
18763 
18764     union
18765     {
18766         __IOM uint8_t RCR2;            /*!< (@ 0x00000024) RTC Control Register 2                                     */
18767 
18768         struct
18769         {
18770             __IOM uint8_t START : 1;   /*!< [0..0] Start                                                              */
18771             __IOM uint8_t RESET : 1;   /*!< [1..1] RTC Software Reset                                                 */
18772             __IOM uint8_t ADJ30 : 1;   /*!< [2..2] 30-Second Adjustment                                               */
18773             __IOM uint8_t RTCOE : 1;   /*!< [3..3] RTCOUT Output Enable                                               */
18774             __IOM uint8_t AADJE : 1;   /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected,
18775                                         *   the setting of this bit is disabled.)                                     */
18776             __IOM uint8_t AADJP : 1;   /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock
18777                                         *   is selected, the setting of this bit is disabled.)                        */
18778             __IOM uint8_t HR24  : 1;   /*!< [6..6] Hours Mode                                                         */
18779             __IOM uint8_t CNTMD : 1;   /*!< [7..7] Count Mode Select                                                  */
18780         } RCR2_b;
18781     };
18782     __IM uint8_t  RESERVED16;
18783     __IM uint16_t RESERVED17;
18784 
18785     union
18786     {
18787         __IOM uint8_t RCR4;            /*!< (@ 0x00000028) RTC Control Register 4                                     */
18788 
18789         struct
18790         {
18791             __IOM uint8_t RCKSEL : 1;  /*!< [0..0] Count Source Select                                                */
18792             uint8_t              : 6;
18793             __IOM uint8_t ROPSEL : 1;  /*!< [7..7] RTC Operation Mode Select                                          */
18794         } RCR4_b;
18795     };
18796     __IM uint8_t RESERVED18;
18797 
18798     union
18799     {
18800         __IOM uint16_t RFRH;           /*!< (@ 0x0000002A) Frequency Register H                                       */
18801 
18802         struct
18803         {
18804             __IOM uint16_t RFC16 : 1;  /*!< [0..0] Frequency Comparison Value (b16) To generate the operating
18805                                         *   clock from the LOCOclock, this bit sets the comparison
18806                                         *   value of the 128-Hz clock cycle.                                          */
18807             uint16_t : 15;
18808         } RFRH_b;
18809     };
18810 
18811     union
18812     {
18813         __IOM uint16_t RFRL;           /*!< (@ 0x0000002C) Frequency Register L                                       */
18814 
18815         struct
18816         {
18817             __IOM uint16_t RFC : 16;   /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating
18818                                         *   clock from the main clock, this bit sets the comparison
18819                                         *   value of the 128-Hz clock cycle.                                          */
18820         } RFRL_b;
18821     };
18822 
18823     union
18824     {
18825         __IOM uint8_t RADJ;            /*!< (@ 0x0000002E) Time Error Adjustment Register                             */
18826 
18827         struct
18828         {
18829             __IOM uint8_t ADJ : 6;     /*!< [5..0] Adjustment Value These bits specify the adjustment value
18830                                         *   from the prescaler.                                                       */
18831             __IOM uint8_t PMADJ : 2;   /*!< [7..6] Plus-Minus                                                         */
18832         } RADJ_b;
18833     };
18834     __IM uint8_t           RESERVED19;
18835     __IM uint16_t          RESERVED20[8];
18836     __IOM R_RTC_RTCCR_Type RTCCR[3];   /*!< (@ 0x00000040) Time Capture Control Register                              */
18837     __IM uint16_t          RESERVED21[5];
18838     __IOM R_RTC_CP_Type    CP[3];      /*!< (@ 0x00000050) Capture registers                                          */
18839 } R_RTC_Type;                          /*!< Size = 128 (0x80)                                                         */
18840 
18841 /* =========================================================================================================================== */
18842 /* ================                                          R_SCI0                                           ================ */
18843 /* =========================================================================================================================== */
18844 
18845 /**
18846  * @brief Serial Communications Interface (R_SCI0)
18847  */
18848 
18849 typedef struct                         /*!< (@ 0x40070000) R_SCI0 Structure                                           */
18850 {
18851     union
18852     {
18853         union
18854         {
18855             __IOM uint8_t SMR;          /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0)                       */
18856 
18857             struct
18858             {
18859                 __IOM uint8_t CKS  : 2; /*!< [1..0] Clock Select                                                       */
18860                 __IOM uint8_t MP   : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode)              */
18861                 __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode)                   */
18862                 __IOM uint8_t PM   : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
18863                 __IOM uint8_t PE   : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
18864                 __IOM uint8_t CHR  : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode)                  */
18865                 __IOM uint8_t CM   : 1; /*!< [7..7] Communication Mode                                                 */
18866             } SMR_b;
18867         };
18868 
18869         union
18870         {
18871             __IOM uint8_t SMR_SMCI;    /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1)                       */
18872 
18873             struct
18874             {
18875                 __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select                                                       */
18876                 __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode)                  */
18877                 __IOM uint8_t PM  : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
18878                 __IOM uint8_t PE  : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
18879                 __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode                                                */
18880                 __IOM uint8_t GM  : 1; /*!< [7..7] GSM Mode                                                           */
18881             } SMR_SMCI_b;
18882         };
18883     };
18884 
18885     union
18886     {
18887         __IOM uint8_t BRR;             /*!< (@ 0x00000001) Bit Rate Register                                          */
18888 
18889         struct
18890         {
18891             __IOM uint8_t BRR : 8;     /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate.                */
18892         } BRR_b;
18893     };
18894 
18895     union
18896     {
18897         union
18898         {
18899             __IOM uint8_t SCR;          /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0)                    */
18900 
18901             struct
18902             {
18903                 __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
18904                 __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
18905                 __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous
18906                                          *   mode when SMR.MP = 1)                                                     */
18907                 __IOM uint8_t RE  : 1;  /*!< [4..4] Receive Enable                                                     */
18908                 __IOM uint8_t TE  : 1;  /*!< [5..5] Transmit Enable                                                    */
18909                 __IOM uint8_t RIE : 1;  /*!< [6..6] Receive Interrupt Enable                                           */
18910                 __IOM uint8_t TIE : 1;  /*!< [7..7] Transmit Interrupt Enable                                          */
18911             } SCR_b;
18912         };
18913 
18914         union
18915         {
18916             __IOM uint8_t SCR_SMCI;     /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1)                     */
18917 
18918             struct
18919             {
18920                 __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
18921                 __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
18922                 __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable                                   */
18923                 __IOM uint8_t RE   : 1; /*!< [4..4] Receive Enable                                                     */
18924                 __IOM uint8_t TE   : 1; /*!< [5..5] Transmit Enable                                                    */
18925                 __IOM uint8_t RIE  : 1; /*!< [6..6] Receive Interrupt Enable                                           */
18926                 __IOM uint8_t TIE  : 1; /*!< [7..7] Transmit Interrupt Enable                                          */
18927             } SCR_SMCI_b;
18928         };
18929     };
18930 
18931     union
18932     {
18933         __IOM uint8_t TDR;             /*!< (@ 0x00000003) Transmit Data Register                                     */
18934 
18935         struct
18936         {
18937             __IOM uint8_t TDR : 8;     /*!< [7..0] TDR is an 8-bit register that stores transmit data.                */
18938         } TDR_b;
18939     };
18940 
18941     union
18942     {
18943         union
18944         {
18945             __IOM uint8_t SSR;          /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)         */
18946 
18947             struct
18948             {
18949                 __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer                                       */
18950                 __IM uint8_t  MPB  : 1; /*!< [1..1] Multi-Processor                                                    */
18951                 __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
18952                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
18953                 __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
18954                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
18955                 __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
18956                 __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
18957             } SSR_b;
18958         };
18959 
18960         union
18961         {
18962             __IOM uint8_t SSR_FIFO;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1)         */
18963 
18964             struct
18965             {
18966                 __IOM uint8_t DR : 1;   /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including
18967                                          *   multi-processor) and FIFO selected)                                       */
18968                 uint8_t            : 1;
18969                 __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
18970                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
18971                 __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
18972                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
18973                 __IOM uint8_t RDF  : 1; /*!< [6..6] Receive FIFO data full flag                                        */
18974                 __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag                                      */
18975             } SSR_FIFO_b;
18976         };
18977 
18978         union
18979         {
18980             __IOM uint8_t SSR_SMCI;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1)                      */
18981 
18982             struct
18983             {
18984                 __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart
18985                                          *   card interface mode.                                                      */
18986                 __IM uint8_t MPB : 1;   /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface
18987                                          *   mode.                                                                     */
18988                 __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
18989                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
18990                 __IOM uint8_t ERS  : 1; /*!< [4..4] Error Signal Status Flag                                           */
18991                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
18992                 __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
18993                 __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
18994             } SSR_SMCI_b;
18995         };
18996     };
18997 
18998     union
18999     {
19000         __IM uint8_t RDR;              /*!< (@ 0x00000005) Receive Data Register                                      */
19001 
19002         struct
19003         {
19004             __IM uint8_t RDR : 8;      /*!< [7..0] RDR is an 8-bit register that stores receive data.                 */
19005         } RDR_b;
19006     };
19007 
19008     union
19009     {
19010         __IOM uint8_t SCMR;            /*!< (@ 0x00000006) Smart Card Mode Register                                   */
19011 
19012         struct
19013         {
19014             __IOM uint8_t SMIF : 1;    /*!< [0..0] Smart Card Interface Mode Select                                   */
19015             uint8_t            : 1;
19016             __IOM uint8_t SINV : 1;    /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if
19017                                         *   operation is to be in simple I2C mode.                                    */
19018             __IOM uint8_t SDIR : 1;    /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The
19019                                         *   setting is invalid and a fixed data length of 8 bits is
19020                                         *   used in modes other than asynchronous mode.Set this bit
19021                                         *   to 1 if operation is to be in simple I2C mode.                            */
19022             __IOM uint8_t CHR1 : 1;    /*!< [4..4] Character Length 1(Only valid in asynchronous mode)                */
19023             uint8_t            : 2;
19024             __IOM uint8_t BCP2 : 1;    /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles
19025                                         *   in combination with the SMR.BCP[1:0] bits                                 */
19026         } SCMR_b;
19027     };
19028 
19029     union
19030     {
19031         __IOM uint8_t SEMR;            /*!< (@ 0x00000007) Serial Extended Mode Register                              */
19032 
19033         struct
19034         {
19035             __IOM uint8_t ACS0 : 1;    /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in
19036                                         *   asynchronous mode).                                                       */
19037             __IOM uint8_t PADIS : 1;   /*!< [1..1] Preamble function Disable (Valid only in asynchronous
19038                                         *   mode).                                                                    */
19039             __IOM uint8_t BRME  : 1;   /*!< [2..2] Bit Rate Modulation Enable                                         */
19040             __IOM uint8_t ABCSE : 1;   /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid
19041                                         *   only in asynchronous mode and SCR.CKE[1]=0)                               */
19042             __IOM uint8_t ABCS : 1;    /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous
19043                                         *   mode)                                                                     */
19044             __IOM uint8_t NFEN : 1;    /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should
19045                                         *   be 0 without simple I2C mode and asynchronous mode.)In
19046                                         *   asynchronous mode, for RXDn input only. In simple I2C mode,
19047                                         *   for RXDn/TxDn input.                                                      */
19048             __IOM uint8_t BGDM : 1;    /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid
19049                                         *   the CKE[1] bit in SCR is 0 in asynchronous mode).                         */
19050             __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only
19051                                         *   in asynchronous mode)                                                     */
19052         } SEMR_b;
19053     };
19054 
19055     union
19056     {
19057         __IOM uint8_t SNFR;            /*!< (@ 0x00000008) Noise Filter Setting Register                              */
19058 
19059         struct
19060         {
19061             __IOM uint8_t NFCS : 3;    /*!< [2..0] Noise Filter Clock Select                                          */
19062             uint8_t            : 5;
19063         } SNFR_b;
19064     };
19065 
19066     union
19067     {
19068         __IOM uint8_t SIMR1;           /*!< (@ 0x00000009) I2C Mode Register 1                                        */
19069 
19070         struct
19071         {
19072             __IOM uint8_t IICM  : 1;   /*!< [0..0] Simple I2C Mode Select                                             */
19073             uint8_t             : 2;
19074             __IOM uint8_t IICDL : 5;   /*!< [7..3] SDA Delay Output SelectCycles below are of the clock
19075                                         *   signal from the on-chip baud rate generator.                              */
19076         } SIMR1_b;
19077     };
19078 
19079     union
19080     {
19081         __IOM uint8_t SIMR2;           /*!< (@ 0x0000000A) I2C Mode Register 2                                        */
19082 
19083         struct
19084         {
19085             __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select                                          */
19086             __IOM uint8_t IICCSC  : 1; /*!< [1..1] Clock Synchronization                                              */
19087             uint8_t               : 3;
19088             __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data                                              */
19089             uint8_t               : 2;
19090         } SIMR2_b;
19091     };
19092 
19093     union
19094     {
19095         __IOM uint8_t SIMR3;              /*!< (@ 0x0000000B) I2C Mode Register 3                                        */
19096 
19097         struct
19098         {
19099             __IOM uint8_t IICSTAREQ  : 1; /*!< [0..0] Start Condition Generation                                         */
19100             __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation                                       */
19101             __IOM uint8_t IICSTPREQ  : 1; /*!< [2..2] Stop Condition Generation                                          */
19102             __IOM uint8_t IICSTIF    : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
19103                                            *   Flag(When 0 is written to IICSTIF, it is cleared to 0.)                   */
19104             __IOM uint8_t IICSDAS : 2;    /*!< [5..4] SDA Output Select                                                  */
19105             __IOM uint8_t IICSCLS : 2;    /*!< [7..6] SCL Output Select                                                  */
19106         } SIMR3_b;
19107     };
19108 
19109     union
19110     {
19111         __IM uint8_t SISR;             /*!< (@ 0x0000000C) I2C Status Register                                        */
19112 
19113         struct
19114         {
19115             __IM uint8_t IICACKR : 1;  /*!< [0..0] ACK Reception Data Flag                                            */
19116             uint8_t              : 7;
19117         } SISR_b;
19118     };
19119 
19120     union
19121     {
19122         __IOM uint8_t SPMR;            /*!< (@ 0x0000000D) SPI Mode Register                                          */
19123 
19124         struct
19125         {
19126             __IOM uint8_t SSE    : 1;  /*!< [0..0] SSn Pin Function Enable                                            */
19127             __IOM uint8_t CTSE   : 1;  /*!< [1..1] CTS Enable                                                         */
19128             __IOM uint8_t MSS    : 1;  /*!< [2..2] Master Slave Select                                                */
19129             __IOM uint8_t CSTPEN : 1;  /*!< [3..3] CTS external pin Enable                                            */
19130             __IOM uint8_t MFF    : 1;  /*!< [4..4] Mode Fault Flag                                                    */
19131             uint8_t              : 1;
19132             __IOM uint8_t CKPOL  : 1;  /*!< [6..6] Clock Polarity Select                                              */
19133             __IOM uint8_t CKPH   : 1;  /*!< [7..7] Clock Phase Select                                                 */
19134         } SPMR_b;
19135     };
19136 
19137     union
19138     {
19139         union
19140         {
19141             __IOM uint16_t TDRHL;         /*!< (@ 0x0000000E) Transmit 9-bit Data Register                               */
19142 
19143             struct
19144             {
19145                 __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data.             */
19146             } TDRHL_b;
19147         };
19148 
19149         union
19150         {
19151             __OM uint16_t FTDRHL;       /*!< (@ 0x0000000E) Transmit FIFO Data Register HL                             */
19152 
19153             struct
19154             {
19155                 __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including
19156                                          *   multi-processor) or clock synchronous mode, and FIFO selected)            */
19157                 __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous
19158                                          *   mode and SMR.MP=1 and FIFO selected)                                      */
19159                 uint16_t : 6;
19160             } FTDRHL_b;
19161         };
19162 
19163         struct
19164         {
19165             union
19166             {
19167                 __OM uint8_t FTDRH;         /*!< (@ 0x0000000E) Transmit FIFO Data Register H                              */
19168 
19169                 struct
19170                 {
19171                     __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous
19172                                              *   mode(including multi-processor) or clock synchronous mode,
19173                                              *   and FIFO selected)                                                        */
19174                     __OM uint8_t MPBT : 1;  /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous
19175                                              *   mode and SMR.MP=1 and FIFO selected)                                      */
19176                     uint8_t : 6;
19177                 } FTDRH_b;
19178             };
19179 
19180             union
19181             {
19182                 __OM uint8_t FTDRL;         /*!< (@ 0x0000000F) Transmit FIFO Data Register L                              */
19183 
19184                 struct
19185                 {
19186                     __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous
19187                                              *   mode(including multi-processor) or clock synchronous mode,
19188                                              *   and FIFO selected)                                                        */
19189                 } FTDRL_b;
19190             };
19191         };
19192     };
19193 
19194     union
19195     {
19196         union
19197         {
19198             __IM uint16_t RDRHL;          /*!< (@ 0x00000010) Receive 9-bit Data Register                                */
19199 
19200             struct
19201             {
19202                 __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data.             */
19203             } RDRHL_b;
19204         };
19205 
19206         union
19207         {
19208             __IM uint16_t FRDRHL;       /*!< (@ 0x00000010) Receive FIFO Data Register HL                              */
19209 
19210             struct
19211             {
19212                 __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including
19213                                          *   multi-processor) or clock synchronous mode, and FIFO selected)            */
19214                 __IM uint16_t MPB : 1;  /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode
19215                                          *   with SMR.MP=1 and FIFO selected) It can read multi-processor
19216                                          *   bit corresponded to serial receive data(RDATA[8:0])                       */
19217                 __IM uint16_t DR   : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR)                    */
19218                 __IM uint16_t PER  : 1; /*!< [11..11] Parity error flag                                                */
19219                 __IM uint16_t FER  : 1; /*!< [12..12] Framing error flag                                               */
19220                 __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER)                       */
19221                 __IM uint16_t RDF  : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF)               */
19222                 uint16_t           : 1;
19223             } FRDRHL_b;
19224         };
19225 
19226         struct
19227         {
19228             union
19229             {
19230                 __IM uint8_t FRDRH;         /*!< (@ 0x00000010) Receive FIFO Data Register H                               */
19231 
19232                 struct
19233                 {
19234                     __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including
19235                                              *   multi-processor) or clock synchronous mode, and FIFO selected)            */
19236                     __IM uint8_t MPB : 1;   /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode
19237                                              *   with SMR.MP=1 and FIFO selected) It can read multi-processor
19238                                              *   bit corresponded to serial receive data(RDATA[8:0])                       */
19239                     __IM uint8_t DR   : 1;  /*!< [2..2] Receive data ready flag(It is same as SSR.DR)                      */
19240                     __IM uint8_t PER  : 1;  /*!< [3..3] Parity error flag                                                  */
19241                     __IM uint8_t FER  : 1;  /*!< [4..4] Framing error flag                                                 */
19242                     __IM uint8_t ORER : 1;  /*!< [5..5] Overrun error flag(It is same as SSR.ORER)                         */
19243                     __IM uint8_t RDF  : 1;  /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF)                 */
19244                     uint8_t           : 1;
19245                 } FRDRH_b;
19246             };
19247 
19248             union
19249             {
19250                 __IM uint8_t FRDRL;         /*!< (@ 0x00000011) Receive FIFO Data Register L                               */
19251 
19252                 struct
19253                 {
19254                     __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including
19255                                              *   multi-processor) or clock synchronous mode, and FIFO selected)NOTE:
19256                                              *   When reading both of FRDRH register and FRDRL register,
19257                                              *   please read by an order of the FRDRH register and the FRDRL
19258                                              *   register.                                                                 */
19259                 } FRDRL_b;
19260             };
19261         };
19262     };
19263 
19264     union
19265     {
19266         __IOM uint8_t MDDR;            /*!< (@ 0x00000012) Modulation Duty Register                                   */
19267 
19268         struct
19269         {
19270             __IOM uint8_t MDDR : 8;    /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register.           */
19271         } MDDR_b;
19272     };
19273 
19274     union
19275     {
19276         __IOM uint8_t DCCR;            /*!< (@ 0x00000013) Data Compare Match Control Register                        */
19277 
19278         struct
19279         {
19280             __IOM uint8_t DCMF  : 1;   /*!< [0..0] Data Compare Match Flag                                            */
19281             uint8_t             : 2;
19282             __IOM uint8_t DPER  : 1;   /*!< [3..3] Data Compare Match Parity Error Flag                               */
19283             __IOM uint8_t DFER  : 1;   /*!< [4..4] Data Compare Match Framing Error Flag                              */
19284             uint8_t             : 1;
19285             __IOM uint8_t IDSEL : 1;   /*!< [6..6] ID frame select(Valid only in asynchronous mode(including
19286                                         *   multi-processor)                                                          */
19287             __IOM uint8_t DCME : 1;    /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous
19288                                         *   mode(including multi-processor)                                           */
19289         } DCCR_b;
19290     };
19291 
19292     union
19293     {
19294         __IOM uint16_t FCR;            /*!< (@ 0x00000014) FIFO Control Register                                      */
19295 
19296         struct
19297         {
19298             __IOM uint16_t FM : 1;     /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including
19299                                         *   multi-processor) or clock synchronous mode)                               */
19300             __IOM uint16_t RFRST : 1;  /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1)           */
19301             __IOM uint16_t TFRST : 1;  /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1)          */
19302             __IOM uint16_t DRES  : 1;  /*!< [3..3] Receive data ready error select bit(When detecting a
19303                                         *   reception data ready, the interrupt request is selected.)                 */
19304             __IOM uint16_t TTRG : 4;   /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous
19305                                         *   mode(including multi-processor) or clock synchronous mode)                */
19306             __IOM uint16_t RTRG : 4;   /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous
19307                                         *   mode(including multi-processor) or clock synchronous mode)                */
19308             __IOM uint16_t RSTRG : 4;  /*!< [15..12] RTS Output Active Trigger Number Select(Valid only
19309                                         *   in asynchronous mode(including multi-processor) or clock
19310                                         *   synchronous mode)                                                         */
19311         } FCR_b;
19312     };
19313 
19314     union
19315     {
19316         __IM uint16_t FDR;             /*!< (@ 0x00000016) FIFO Data Count Register                                   */
19317 
19318         struct
19319         {
19320             __IM uint16_t R : 5;       /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive
19321                                         *   data stored in FRDRH and FRDRL(Valid only in asynchronous
19322                                         *   mode(including multi-processor) or clock synchronous mode,
19323                                         *   while FCR.FM=1)                                                           */
19324             uint16_t        : 3;
19325             __IM uint16_t T : 5;       /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit
19326                                         *   data stored in FTDRH and FTDRL(Valid only in asynchronous
19327                                         *   mode(including multi-processor) or clock synchronous mode,
19328                                         *   while FCR.FM=1)                                                           */
19329             uint16_t : 3;
19330         } FDR_b;
19331     };
19332 
19333     union
19334     {
19335         __IM uint16_t LSR;             /*!< (@ 0x00000018) Line Status Register                                       */
19336 
19337         struct
19338         {
19339             __IM uint16_t ORER : 1;    /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including
19340                                         *   multi-processor) or clock synchronous mode, and FIFO selected)            */
19341             uint16_t           : 1;
19342             __IM uint16_t FNUM : 5;    /*!< [6..2] Framing Error CountIndicates the quantity of data with
19343                                         *   a framing error among the receive data stored in the receive
19344                                         *   FIFO data register (FRDRH and FRDRL).                                     */
19345             uint16_t           : 1;
19346             __IM uint16_t PNUM : 5;    /*!< [12..8] Parity Error CountIndicates the quantity of data with
19347                                         *   a parity error among the receive data stored in the receive
19348                                         *   FIFO data register (FRDRH and FRDRL).                                     */
19349             uint16_t : 3;
19350         } LSR_b;
19351     };
19352 
19353     union
19354     {
19355         __IOM uint16_t CDR;            /*!< (@ 0x0000001A) Compare Match Data Register                                */
19356 
19357         struct
19358         {
19359             __IOM uint16_t CMPD : 9;   /*!< [8..0] Compare Match DataCompare data pattern for address match
19360                                         *   wake-up function                                                          */
19361             uint16_t : 7;
19362         } CDR_b;
19363     };
19364 
19365     union
19366     {
19367         __IOM uint8_t SPTR;            /*!< (@ 0x0000001C) Serial Port Register                                       */
19368 
19369         struct
19370         {
19371             __IM uint8_t RXDMON : 1;   /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal
19372                                         *   is shown.)                                                                */
19373             __IOM uint8_t SPB2DT : 1;  /*!< [1..1] Serial port break data select bit(The output level of
19374                                         *   TxD terminal is selected when SCR.TE = 0.)                                */
19375             __IOM uint8_t SPB2IO : 1;  /*!< [2..2] Serial port break I/O bit(It's selected whether the value
19376                                         *   of SPB2DT is output to TxD terminal.)                                     */
19377             uint8_t            : 1;
19378             __IOM uint8_t RINV : 1;    /*!< [4..4] RXD invert bit                                                     */
19379             __IOM uint8_t TINV : 1;    /*!< [5..5] TXD invert bit                                                     */
19380             __IOM uint8_t ASEN : 1;    /*!< [6..6] Adjust receive sampling timing enable                              */
19381             __IOM uint8_t ATEN : 1;    /*!< [7..7] Adjust transmit timing enable                                      */
19382         } SPTR_b;
19383     };
19384 
19385     union
19386     {
19387         __IOM uint8_t ACTR;            /*!< (@ 0x0000001D) Adjustment Communication Timing Register                   */
19388 
19389         struct
19390         {
19391             __IOM uint8_t AST : 3;     /*!< [2..0] Adjustment value for receive Sampling Timing                       */
19392             __IOM uint8_t AJD : 1;     /*!< [3..3] Adjustment Direction for receive sampling timing                   */
19393             __IOM uint8_t ATT : 3;     /*!< [6..4] Adjustment value for Transmit timing                               */
19394             __IOM uint8_t AET : 1;     /*!< [7..7] Adjustment edge for transmit timing                                */
19395         } ACTR_b;
19396     };
19397     __IM uint16_t RESERVED;
19398 
19399     union
19400     {
19401         __IOM uint8_t ESMER;           /*!< (@ 0x00000020) Extended Serial Module Enable Register                     */
19402 
19403         struct
19404         {
19405             __IOM uint8_t ESME : 1;    /*!< [0..0] Extended Serial Mode Enable                                        */
19406             uint8_t            : 7;
19407         } ESMER_b;
19408     };
19409 
19410     union
19411     {
19412         __IOM uint8_t CR0;             /*!< (@ 0x00000021) Control Register 0                                         */
19413 
19414         struct
19415         {
19416             uint8_t             : 1;
19417             __IM uint8_t  SFSF  : 1;   /*!< [1..1] Start Frame Status Flag                                            */
19418             __IM uint8_t  RXDSF : 1;   /*!< [2..2] RXDXn Input Status Flag                                            */
19419             __IOM uint8_t BRME  : 1;   /*!< [3..3] Bit Rate Measurement Enable                                        */
19420             uint8_t             : 4;
19421         } CR0_b;
19422     };
19423 
19424     union
19425     {
19426         __IOM uint8_t CR1;             /*!< (@ 0x00000022) Control Register 1                                         */
19427 
19428         struct
19429         {
19430             __IOM uint8_t BFE   : 1;   /*!< [0..0] Break Field Enable                                                 */
19431             __IOM uint8_t CF0RE : 1;   /*!< [1..1] Control Field 0 Reception Enable                                   */
19432             __IOM uint8_t CF1DS : 2;   /*!< [3..2] Control Field 1 Data Register Select                               */
19433             __IOM uint8_t PIBE  : 1;   /*!< [4..4] Priority Interrupt Bit Enable                                      */
19434             __IOM uint8_t PIBS  : 3;   /*!< [7..5] Priority Interrupt Bit Select                                      */
19435         } CR1_b;
19436     };
19437 
19438     union
19439     {
19440         __IOM uint8_t CR2;             /*!< (@ 0x00000023) Control Register 2                                         */
19441 
19442         struct
19443         {
19444             __IOM uint8_t DFCS : 3;    /*!< [2..0] RXDXn Signal Digital Filter Clock Select                           */
19445             uint8_t            : 1;
19446             __IOM uint8_t BCCS : 2;    /*!< [5..4] Bus Collision Detection Clock Select                               */
19447             __IOM uint8_t RTS  : 2;    /*!< [7..6] RXDXn Reception Sampling Timing Select                             */
19448         } CR2_b;
19449     };
19450 
19451     union
19452     {
19453         __IOM uint8_t CR3;             /*!< (@ 0x00000024) Control Register 3                                         */
19454 
19455         struct
19456         {
19457             __IOM uint8_t SDST : 1;    /*!< [0..0] Start Frame Detection Start                                        */
19458             uint8_t            : 7;
19459         } CR3_b;
19460     };
19461 
19462     union
19463     {
19464         __IOM uint8_t PCR;             /*!< (@ 0x00000025) Port Control Register                                      */
19465 
19466         struct
19467         {
19468             __IOM uint8_t TXDXPS : 1;  /*!< [0..0] TXDXn Signal Polarity Select                                       */
19469             __IOM uint8_t RXDXPS : 1;  /*!< [1..1] RXDXn Signal Polarity Select                                       */
19470             uint8_t              : 2;
19471             __IOM uint8_t SHARPS : 1;  /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select                                */
19472             uint8_t              : 3;
19473         } PCR_b;
19474     };
19475 
19476     union
19477     {
19478         __IOM uint8_t ICR;             /*!< (@ 0x00000026) Interrupt Control Register                                 */
19479 
19480         struct
19481         {
19482             __IOM uint8_t BFDIE  : 1;  /*!< [0..0] Break Field Low Width Detected Interrupt Enable                    */
19483             __IOM uint8_t CF0MIE : 1;  /*!< [1..1] Control Field 0 Match Detected Interrupt Enable                    */
19484             __IOM uint8_t CF1MIE : 1;  /*!< [2..2] Control Field 1 Match Detected Interrupt Enable                    */
19485             __IOM uint8_t PIBDIE : 1;  /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable                   */
19486             __IOM uint8_t BCDIE  : 1;  /*!< [4..4] Bus Collision Detected Interrupt Enable                            */
19487             __IOM uint8_t AEDIE  : 1;  /*!< [5..5] Valid Edge Detected Interrupt Enable                               */
19488             uint8_t              : 2;
19489         } ICR_b;
19490     };
19491 
19492     union
19493     {
19494         __IM uint8_t STR;              /*!< (@ 0x00000027) Status Register                                            */
19495 
19496         struct
19497         {
19498             __IM uint8_t BFDF  : 1;    /*!< [0..0] Break Field Low Width Detection Flag                               */
19499             __IM uint8_t CF0MF : 1;    /*!< [1..1] Control Field 0 Match Flag                                         */
19500             __IM uint8_t CF1MF : 1;    /*!< [2..2] Control Field 1 Match Flag                                         */
19501             __IM uint8_t PIBDF : 1;    /*!< [3..3] Priority Interrupt Bit Detection Flag                              */
19502             __IM uint8_t BCDF  : 1;    /*!< [4..4] Bus Collision Detected Flag                                        */
19503             __IM uint8_t AEDF  : 1;    /*!< [5..5] Valid Edge Detection Flag                                          */
19504             uint8_t            : 2;
19505         } STR_b;
19506     };
19507 
19508     union
19509     {
19510         __IOM uint8_t STCR;            /*!< (@ 0x00000028) Status Clear Register                                      */
19511 
19512         struct
19513         {
19514             __IOM uint8_t BFDCL  : 1;  /*!< [0..0] BFDF Clear                                                         */
19515             __IOM uint8_t CF0MCL : 1;  /*!< [1..1] CF0MF Clear                                                        */
19516             __IOM uint8_t CF1MCL : 1;  /*!< [2..2] CF1MF Clear                                                        */
19517             __IOM uint8_t PIBDCL : 1;  /*!< [3..3] PIBDF Clear                                                        */
19518             __IOM uint8_t BCDCL  : 1;  /*!< [4..4] BCDF Clear                                                         */
19519             __IOM uint8_t AEDCL  : 1;  /*!< [5..5] AEDF Clear                                                         */
19520             uint8_t              : 2;
19521         } STCR_b;
19522     };
19523     __IOM uint8_t CF0DR;               /*!< (@ 0x00000029) Control Field 0 Data Register                              */
19524 
19525     union
19526     {
19527         __IOM uint8_t CF0CR;           /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register                    */
19528 
19529         struct
19530         {
19531             __IOM uint8_t CF0CE0 : 1;  /*!< [0..0] Control Field 0 Bit 0 Compare Enable                               */
19532             __IOM uint8_t CF0CE1 : 1;  /*!< [1..1] Control Field 1 Bit 0 Compare Enable                               */
19533             __IOM uint8_t CF0CE2 : 1;  /*!< [2..2] Control Field 2 Bit 0 Compare Enable                               */
19534             __IOM uint8_t CF0CE3 : 1;  /*!< [3..3] Control Field 3 Bit 0 Compare Enable                               */
19535             __IOM uint8_t CF0CE4 : 1;  /*!< [4..4] Control Field 4 Bit 0 Compare Enable                               */
19536             __IOM uint8_t CF0CE5 : 1;  /*!< [5..5] Control Field 5 Bit 0 Compare Enable                               */
19537             __IOM uint8_t CF0CE6 : 1;  /*!< [6..6] Control Field 6 Bit 0 Compare Enable                               */
19538             __IOM uint8_t CF0CE7 : 1;  /*!< [7..7] Control Field 7 Bit 0 Compare Enable                               */
19539         } CF0CR_b;
19540     };
19541     __IOM uint8_t CF0RR;               /*!< (@ 0x0000002B) Control Field 0 Receive Data Register                      */
19542     __IOM uint8_t PCF1DR;              /*!< (@ 0x0000002C) Primary Control Field 1 Data Register                      */
19543     __IOM uint8_t SCF1DR;              /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register                    */
19544 
19545     union
19546     {
19547         __IOM uint8_t CF1CR;           /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register                    */
19548 
19549         struct
19550         {
19551             __IOM uint8_t CF1CE0 : 1;  /*!< [0..0] Control Field 1 Bit 0 Compare Enable                               */
19552             __IOM uint8_t CF1CE1 : 1;  /*!< [1..1] Control Field 1 Bit 1 Compare Enable                               */
19553             __IOM uint8_t CF1CE2 : 1;  /*!< [2..2] Control Field 1 Bit 2 Compare Enable                               */
19554             __IOM uint8_t CF1CE3 : 1;  /*!< [3..3] Control Field 1 Bit 3 Compare Enable                               */
19555             __IOM uint8_t CF1CE4 : 1;  /*!< [4..4] Control Field 1 Bit 4 Compare Enable                               */
19556             __IOM uint8_t CF1CE5 : 1;  /*!< [5..5] Control Field 1 Bit 5 Compare Enable                               */
19557             __IOM uint8_t CF1CE6 : 1;  /*!< [6..6] Control Field 1 Bit 6 Compare Enable                               */
19558             __IOM uint8_t CF1CE7 : 1;  /*!< [7..7] Control Field 1 Bit 7 Compare Enable                               */
19559         } CF1CR_b;
19560     };
19561     __IOM uint8_t CF1RR;               /*!< (@ 0x0000002F) Control Field 1 Receive Data Register                      */
19562 
19563     union
19564     {
19565         __IOM uint8_t TCR;             /*!< (@ 0x00000030) Timer Control Register                                     */
19566 
19567         struct
19568         {
19569             __IOM uint8_t TCST : 1;    /*!< [0..0] Timer Count Start                                                  */
19570             uint8_t            : 7;
19571         } TCR_b;
19572     };
19573 
19574     union
19575     {
19576         __IOM uint8_t TMR;             /*!< (@ 0x00000031) Timer Mode Register                                        */
19577 
19578         struct
19579         {
19580             __IOM uint8_t TOMS : 2;    /*!< [1..0] Timer Operating Mode Select                                        */
19581             uint8_t            : 1;
19582             __IOM uint8_t TWRC : 1;    /*!< [3..3] Counter Write Control                                              */
19583             __IOM uint8_t TCSS : 3;    /*!< [6..4] Timer Count Clock Source Select                                    */
19584             uint8_t            : 1;
19585         } TMR_b;
19586     };
19587     __IOM uint8_t TPRE;                /*!< (@ 0x00000032) Timer Prescaler Register                                   */
19588     __IOM uint8_t TCNT;                /*!< (@ 0x00000033) Timer Count Register                                       */
19589 } R_SCI0_Type;                         /*!< Size = 52 (0x34)                                                          */
19590 
19591 /* =========================================================================================================================== */
19592 /* ================                                         R_SDADC0                                          ================ */
19593 /* =========================================================================================================================== */
19594 
19595 /**
19596  * @brief R_SDADC0 (R_SDADC0)
19597  */
19598 
19599 typedef struct                          /*!< (@ 0x4009C000) R_SDADC0 Structure                                         */
19600 {
19601     union
19602     {
19603         __IOM uint16_t STC1;            /*!< (@ 0x00000000) Startup Control Register 1                                 */
19604 
19605         struct
19606         {
19607             __IOM uint16_t CLKDIV  : 4; /*!< [3..0] SDADC24 Reference Clock Division                                   */
19608             uint16_t               : 3;
19609             __IOM uint16_t SDADLPM : 1; /*!< [7..7] A/D conversion operation model select                              */
19610             __IOM uint16_t VSBIAS  : 4; /*!< [11..8] Reference voltage select                                          */
19611             uint16_t               : 3;
19612             __IOM uint16_t VREFSEL : 1; /*!< [15..15] VREF mode select                                                 */
19613         } STC1_b;
19614     };
19615     __IM uint16_t RESERVED;
19616 
19617     union
19618     {
19619         __IOM uint8_t STC2;            /*!< (@ 0x00000004) Startup Control Register 2                                 */
19620 
19621         struct
19622         {
19623             __IOM uint8_t BGRPON  : 1; /*!< [0..0] BGR part power control                                             */
19624             __IOM uint8_t ADCPON  : 1; /*!< [1..1] ADREG forced power-down                                            */
19625             __IOM uint8_t ADFPWDS : 1; /*!< [2..2] ADC reference supply part                                          */
19626             uint8_t               : 5;
19627         } STC2_b;
19628     };
19629     __IM uint8_t  RESERVED1;
19630     __IM uint16_t RESERVED2;
19631 
19632     union
19633     {
19634         __IOM uint32_t PGAC[5];        /*!< (@ 0x00000008) Input Multiplexer [0..4] Setting Register                  */
19635 
19636         struct
19637         {
19638             __IOM uint32_t PGAGC : 5;  /*!< [4..0] Gain selection of a programmable gain instrumentation
19639                                         *   amplifier ( Gset1, Gset2, Gtotal )                                        */
19640             __IOM uint32_t PGAOSR : 3; /*!< [7..5] Oversampling ratio select                                          */
19641             __IOM uint32_t PGAOFS : 5; /*!< [12..8] Offset voltage select                                             */
19642             uint32_t              : 1;
19643             __IOM uint32_t PGAPOL : 1; /*!< [14..14] Polarity select                                                  */
19644             __IOM uint32_t PGASEL : 1; /*!< [15..15] Analog Channel Input Mode Select                                 */
19645             __IOM uint32_t PGACTM : 5; /*!< [20..16] Coefficient (m) selection of the A/D conversion count
19646                                         *   (N) in AUTOSCAN                                                           */
19647             __IOM uint32_t PGACTN : 3; /*!< [23..21] Coefficient (n) selection of the A/D conversion count
19648                                         *   (N) in AUTOSCAN                                                           */
19649             __IOM uint32_t PGAAVN : 2; /*!< [25..24] Selection of the number of data to be averaged                   */
19650             __IOM uint32_t PGAAVE : 2; /*!< [27..26] Selection of averaging processing                                */
19651             __IOM uint32_t PGAREV : 1; /*!< [28..28] Single-End Input A/D Converted Data Inversion Select             */
19652             uint32_t              : 1;
19653             __IOM uint32_t PGACVE : 1; /*!< [30..30] Calibration enable                                               */
19654             __IOM uint32_t PGAASN : 1; /*!< [31..31] Selection of the mode for specifying the number of
19655                                         *   A/D conversions in ADSCAN                                                 */
19656         } PGAC_b[5];
19657     };
19658 
19659     union
19660     {
19661         __IOM uint32_t ADC1;            /*!< (@ 0x0000001C) Sigma-Delta A/D Converter Control Register 1               */
19662 
19663         struct
19664         {
19665             __IOM uint32_t SDADSCM : 1; /*!< [0..0] Selection of autoscan mode                                         */
19666             uint32_t               : 3;
19667             __IOM uint32_t SDADTMD : 1; /*!< [4..4] Selection of A/D conversion trigger signal                         */
19668             uint32_t               : 3;
19669             __IOM uint32_t SDADBMP : 5; /*!< [12..8] A/D conversion control of the signal from input multiplexer       */
19670             uint32_t               : 3;
19671             __IOM uint32_t PGADISA : 1; /*!< [16..16] Control of disconnection detection                               */
19672             __IOM uint32_t PGADISC : 1; /*!< [17..17] Disconnection Detection Assist Setting                           */
19673             uint32_t               : 2;
19674             __IOM uint32_t PGASLFT : 1; /*!< [20..20] PGA offset self-diagnosis enable                                 */
19675             uint32_t               : 11;
19676         } ADC1_b;
19677     };
19678 
19679     union
19680     {
19681         __IOM uint8_t ADC2;            /*!< (@ 0x00000020) Sigma-Delta A/D Converter Control Register 2               */
19682 
19683         struct
19684         {
19685             __IOM uint8_t SDADST : 1;  /*!< [0..0] Control of A/D conversion                                          */
19686             uint8_t              : 7;
19687         } ADC2_b;
19688     };
19689     __IM uint8_t  RESERVED3;
19690     __IM uint16_t RESERVED4;
19691 
19692     union
19693     {
19694         __IOM uint32_t ADCR;            /*!< (@ 0x00000024) Sigma-delta A/D Converter Conversion Result Register       */
19695 
19696         struct
19697         {
19698             __IM uint32_t SDADCRD : 24; /*!< [23..0] The 24-bit A/D conversion result                                  */
19699             __IM uint32_t SDADCRS : 1;  /*!< [24..24] Status of an A/D conversion result                               */
19700             __IM uint32_t SDADCRC : 3;  /*!< [27..25] Channel number for an A/D conversion result                      */
19701             uint32_t              : 4;
19702         } ADCR_b;
19703     };
19704 
19705     union
19706     {
19707         __IM uint32_t ADAR;             /*!< (@ 0x00000028) Sigma-delta A/D Converter Average Value Register           */
19708 
19709         struct
19710         {
19711             __IM uint32_t SDADMVD : 24; /*!< [23..0] The 24-bit A/D average value                                      */
19712             __IM uint32_t SDADMVS : 1;  /*!< [24..24] Status of an A/D conversion result                               */
19713             __IM uint32_t SDADMVC : 3;  /*!< [27..25] Channel number for an A/D conversion result                      */
19714             uint32_t              : 4;
19715         } ADAR_b;
19716     };
19717     __IM uint32_t RESERVED5;
19718 
19719     union
19720     {
19721         __IOM uint8_t CLBC;            /*!< (@ 0x00000030) Calibration Control Register                               */
19722 
19723         struct
19724         {
19725             __IOM uint8_t CLBMD : 2;   /*!< [1..0] These bits are read as 0. The write value should be 0.             */
19726             uint8_t             : 6;
19727         } CLBC_b;
19728     };
19729     __IM uint8_t  RESERVED6;
19730     __IM uint16_t RESERVED7;
19731 
19732     union
19733     {
19734         __IOM uint8_t CLBSTR;          /*!< (@ 0x00000034) Calibration Start Control Register                         */
19735 
19736         struct
19737         {
19738             __IOM uint8_t CLBST : 1;   /*!< [0..0] Calibration start control                                          */
19739             uint8_t             : 7;
19740         } CLBSTR_b;
19741     };
19742     __IM uint8_t  RESERVED8;
19743     __IM uint16_t RESERVED9;
19744     __IM uint32_t RESERVED10;
19745 
19746     union
19747     {
19748         __IM uint8_t CLBSSR;           /*!< (@ 0x0000003C) Calibration Status Register                                */
19749 
19750         struct
19751         {
19752             __IM uint8_t CLBSS : 1;    /*!< [0..0] Calibration status                                                 */
19753             uint8_t            : 7;
19754         } CLBSSR_b;
19755     };
19756     __IM uint8_t  RESERVED11;
19757     __IM uint16_t RESERVED12;
19758 } R_SDADC0_Type;                       /*!< Size = 64 (0x40)                                                          */
19759 
19760 /* =========================================================================================================================== */
19761 /* ================                                          R_SDHI0                                          ================ */
19762 /* =========================================================================================================================== */
19763 
19764 /**
19765  * @brief SD/MMC Host Interface (R_SDHI0)
19766  */
19767 
19768 typedef struct                          /*!< (@ 0x40062000) R_SDHI0 Structure                                          */
19769 {
19770     union
19771     {
19772         __IOM uint32_t SD_CMD;          /*!< (@ 0x00000000) Command Type Register                                      */
19773 
19774         struct
19775         {
19776             __IOM uint32_t CMDIDX : 6;  /*!< [5..0] Command IndexThese bits specify Command Format[45:40]
19777                                          *   (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18:
19778                                          *   SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101              */
19779             __IOM uint32_t ACMD  : 2;   /*!< [7..6] Command Type Select                                                */
19780             __IOM uint32_t RSPTP : 3;   /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used
19781                                          *   in normal mode, see section 1.4.10, Example of SD_CMD Register
19782                                          *   Setting to select mode/response type.                                     */
19783             __IOM uint32_t CMDTP : 1;   /*!< [11..11] Data Mode (Command Type)                                         */
19784             __IOM uint32_t CMDRW : 1;   /*!< [12..12] Write/Read Mode (enabled when the command with data
19785                                          *   is handled)                                                               */
19786             __IOM uint32_t TRSTP : 1;   /*!< [13..13] Single/Multiple Block Transfer (enabled when the command
19787                                          *   with data is handled)                                                     */
19788             __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block
19789                                          *   transfer)                                                                 */
19790             uint32_t : 16;
19791         } SD_CMD_b;
19792     };
19793     __IM uint32_t RESERVED;
19794 
19795     union
19796     {
19797         __IOM uint32_t SD_ARG;          /*!< (@ 0x00000008) SD Command Argument Register                               */
19798 
19799         struct
19800         {
19801             __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument)              */
19802         } SD_ARG_b;
19803     };
19804 
19805     union
19806     {
19807         __IOM uint32_t SD_ARG1;          /*!< (@ 0x0000000C) SD Command Argument Register 1                             */
19808 
19809         struct
19810         {
19811             __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument)           */
19812             uint32_t               : 16;
19813         } SD_ARG1_b;
19814     };
19815 
19816     union
19817     {
19818         __IOM uint32_t SD_STOP;        /*!< (@ 0x00000010) Data Stop Register                                         */
19819 
19820         struct
19821         {
19822             __IOM uint32_t STP : 1;    /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer,
19823                                         *   CMD12 is issued to halt the transfer through the SD host
19824                                         *   interface.However, if a command sequence is halted because
19825                                         *   of a communications error or timeout, CMD12 is not issued.
19826                                         *   Although continued buffer access is possible even after
19827                                         *   STP has been set to 1, the buffer access error bit (ERR5
19828                                         *   or ERR4) in SD_INFO2 will be set accordingly.- When STP
19829                                         *   has been set to 1 during transfer for single block write,
19830                                         *   the access end flag is set when SD_BUF becomes emp                        */
19831             uint32_t           : 7;
19832             __IOM uint32_t SEC : 1;    /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When
19833                                         *   SD_CMD is set as follows to start the command sequence
19834                                         *   while SEC is set to 1, CMD12 is automatically issued to
19835                                         *   stop multi-block transfer with the number of blocks which
19836                                         *   is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8]
19837                                         *   = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is
19838                                         *   automatically issued, multiple block transfer)When the
19839                                         *   command sequence is halted because of a communications
19840                                         *   error or timeout, CMD12 is not automatically i                            */
19841             uint32_t : 23;
19842         } SD_STOP_b;
19843     };
19844 
19845     union
19846     {
19847         __IOM uint32_t SD_SECCNT;          /*!< (@ 0x00000014) Block Count Register                                       */
19848 
19849         struct
19850         {
19851             __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value
19852                                             *   of this bit when the CBSY bit in SD_INFO2 is set to 1.                    */
19853         } SD_SECCNT_b;
19854     };
19855 
19856     union
19857     {
19858         __IM uint32_t SD_RSP10;          /*!< (@ 0x00000018) SD Card Response Register 10                               */
19859 
19860         struct
19861         {
19862             __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC                           */
19863         } SD_RSP10_b;
19864     };
19865 
19866     union
19867     {
19868         __IM uint32_t SD_RSP1;          /*!< (@ 0x0000001C) SD Card Response Register 1                                */
19869 
19870         struct
19871         {
19872             __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC                           */
19873             uint32_t              : 16;
19874         } SD_RSP1_b;
19875     };
19876 
19877     union
19878     {
19879         __IM uint32_t SD_RSP32;          /*!< (@ 0x00000020) SD Card Response Register 32                               */
19880 
19881         struct
19882         {
19883             __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC                           */
19884         } SD_RSP32_b;
19885     };
19886 
19887     union
19888     {
19889         __IM uint32_t SD_RSP3;          /*!< (@ 0x00000024) SD Card Response Register 3                                */
19890 
19891         struct
19892         {
19893             __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC                           */
19894             uint32_t              : 16;
19895         } SD_RSP3_b;
19896     };
19897 
19898     union
19899     {
19900         __IM uint32_t SD_RSP54;          /*!< (@ 0x00000028) SD Card Response Register 54                               */
19901 
19902         struct
19903         {
19904             __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC                           */
19905         } SD_RSP54_b;
19906     };
19907 
19908     union
19909     {
19910         __IM uint32_t SD_RSP5;          /*!< (@ 0x0000002C) SD Card Response Register 5                                */
19911 
19912         struct
19913         {
19914             __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC                           */
19915             uint32_t              : 16;
19916         } SD_RSP5_b;
19917     };
19918 
19919     union
19920     {
19921         __IM uint32_t SD_RSP76;          /*!< (@ 0x00000030) SD Card Response Register 76                               */
19922 
19923         struct
19924         {
19925             __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC                           */
19926             uint32_t               : 8;
19927         } SD_RSP76_b;
19928     };
19929 
19930     union
19931     {
19932         __IM uint32_t SD_RSP7;         /*!< (@ 0x00000034) SD Card Response Register 7                                */
19933 
19934         struct
19935         {
19936             __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC                            */
19937             uint32_t              : 24;
19938         } SD_RSP7_b;
19939     };
19940 
19941     union
19942     {
19943         __IOM uint32_t SD_INFO1;        /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1                          */
19944 
19945         struct
19946         {
19947             __IOM uint32_t RSPEND  : 1; /*!< [0..0] Response End Detection                                             */
19948             uint32_t               : 1;
19949             __IOM uint32_t ACEND   : 1; /*!< [2..2] Access End                                                         */
19950             __IOM uint32_t SDCDRM  : 1; /*!< [3..3] SDnCD Card Removal                                                 */
19951             __IOM uint32_t SDCDIN  : 1; /*!< [4..4] SDnCD Card Insertion                                               */
19952             __IM uint32_t  SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state                                          */
19953             uint32_t               : 1;
19954             __IM uint32_t  SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state                                          */
19955             __IOM uint32_t SDD3RM  : 1; /*!< [8..8] SDnDAT3 Card Removal                                               */
19956             __IOM uint32_t SDD3IN  : 1; /*!< [9..9] SDnDAT3 Card Insertion                                             */
19957             __IM uint32_t  SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State                                      */
19958             uint32_t               : 21;
19959         } SD_INFO1_b;
19960     };
19961 
19962     union
19963     {
19964         __IOM uint32_t SD_INFO2;             /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2                          */
19965 
19966         struct
19967         {
19968             __IOM uint32_t CMDE    : 1;      /*!< [0..0] Command Error                                                      */
19969             __IOM uint32_t CRCE    : 1;      /*!< [1..1] CRC Error                                                          */
19970             __IOM uint32_t ENDE    : 1;      /*!< [2..2] END Error                                                          */
19971             __IOM uint32_t DTO     : 1;      /*!< [3..3] Data Timeout                                                       */
19972             __IOM uint32_t ILW     : 1;      /*!< [4..4] SD_BUF Illegal Write Access                                        */
19973             __IOM uint32_t ILR     : 1;      /*!< [5..5] SD_BUF Illegal Read Access                                         */
19974             __IOM uint32_t RSPTO   : 1;      /*!< [6..6] Response Timeout                                                   */
19975             __IM uint32_t  SDD0MON : 1;      /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified
19976                                               *   by SD_PORTSEL.                                                            */
19977             __IOM uint32_t BRE          : 1; /*!< [8..8] SD_BUF Read Enable                                                 */
19978             __IOM uint32_t BWE          : 1; /*!< [9..9] SD_BUF Write Enable                                                */
19979             uint32_t                    : 3;
19980             __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD,
19981                                               *   the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN
19982                                               *   bit is set to 0. The SCLKDIVEN bit is set to 1 after 8
19983                                               *   cycles of SDCLK have elapsed after setting of the CBSY
19984                                               *   bit to 0 due to completion of the command sequence.                       */
19985             __IM uint32_t  CBSY : 1;         /*!< [14..14] Command Type Register Busy                                       */
19986             __IOM uint32_t ILA  : 1;         /*!< [15..15] Illegal Access Error                                             */
19987             uint32_t            : 16;
19988         } SD_INFO2_b;
19989     };
19990 
19991     union
19992     {
19993         __IOM uint32_t SD_INFO1_MASK;   /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register                           */
19994 
19995         struct
19996         {
19997             __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask                                */
19998             uint32_t               : 1;
19999             __IOM uint32_t ACENDM  : 1; /*!< [2..2] Access End Interrupt Request Mask                                  */
20000             __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask                          */
20001             __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask                        */
20002             uint32_t               : 3;
20003             __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask                        */
20004             __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask                      */
20005             uint32_t               : 22;
20006         } SD_INFO1_MASK_b;
20007     };
20008 
20009     union
20010     {
20011         __IOM uint32_t SD_INFO2_MASK;  /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register                           */
20012 
20013         struct
20014         {
20015             __IOM uint32_t CMDEM  : 1; /*!< [0..0] Command Error Interrupt Request Mask                               */
20016             __IOM uint32_t CRCEM  : 1; /*!< [1..1] CRC Error Interrupt Request Mask                                   */
20017             __IOM uint32_t ENDEM  : 1; /*!< [2..2] End Bit Error Interrupt Request Mask                               */
20018             __IOM uint32_t DTOM   : 1; /*!< [3..3] Data Timeout Interrupt Request Mask                                */
20019             __IOM uint32_t ILWM   : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask               */
20020             __IOM uint32_t ILRM   : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask                */
20021             __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask                            */
20022             uint32_t              : 1;
20023             __IOM uint32_t BREM   : 1; /*!< [8..8] BRE Interrupt Request Mask                                         */
20024             __IOM uint32_t BWEM   : 1; /*!< [9..9] BWE Interrupt Request Mask                                         */
20025             uint32_t              : 5;
20026             __IOM uint32_t ILAM   : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask                      */
20027             uint32_t              : 16;
20028         } SD_INFO2_MASK_b;
20029     };
20030 
20031     union
20032     {
20033         __IOM uint32_t SD_CLK_CTRL;       /*!< (@ 0x00000048) SD Clock Control Register                                  */
20034 
20035         struct
20036         {
20037             __IOM uint32_t CLKSEL    : 8; /*!< [7..0] SDHI Clock Frequency Select                                        */
20038             __IOM uint32_t CLKEN     : 1; /*!< [8..8] SD/MMC Clock Output Control Enable                                 */
20039             __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable                       */
20040             uint32_t                 : 22;
20041         } SD_CLK_CTRL_b;
20042     };
20043 
20044     union
20045     {
20046         __IOM uint32_t SD_SIZE;        /*!< (@ 0x0000004C) Transfer Data Length Register                              */
20047 
20048         struct
20049         {
20050             __IOM uint32_t LEN : 10;   /*!< [9..0] Transfer Data SizeThese bits specify a size between 1
20051                                         *   and 512 bytes for the transfer of single blocks.In cases
20052                                         *   of multiple block transfer with automatic issuing of CMD12
20053                                         *   (CMD18 and CMD25), the only specifiable transfer data size
20054                                         *   is 512 bytes. Furthermore, in cases of multiple block transfer
20055                                         *   without automatic issuing of CMD12, as well as 512 bytes,
20056                                         *   32, 64, 128, and 256 bytes are specifiable. However, in
20057                                         *   the reading of 32, 64, 128, and 256 bytes for the transfer
20058                                         *   of multiple blocks, this is restricted to mult                            */
20059             uint32_t : 22;
20060         } SD_SIZE_b;
20061     };
20062 
20063     union
20064     {
20065         __IOM uint32_t SD_OPTION;        /*!< (@ 0x00000050) SD Card Access Control Option Register                     */
20066 
20067         struct
20068         {
20069             __IOM uint32_t CTOP     : 4; /*!< [3..0] Card Detect Time Counter                                           */
20070             __IOM uint32_t TOP      : 4; /*!< [7..4] Timeout Counter                                                    */
20071             __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating
20072                                           *   timeout, software reset should be executed to terminate
20073                                           *   command sequence.                                                         */
20074             uint32_t              : 4;
20075             __IOM uint32_t WIDTH8 : 1;   /*!< [13..13] Bus Widthsee b15, WIDTH bit                                      */
20076             uint32_t              : 1;
20077             __IOM uint32_t WIDTH  : 1;   /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset
20078                                           *   and when the SOFT_RST.SDRST flag is 0.                                    */
20079             uint32_t : 16;
20080         } SD_OPTION_b;
20081     };
20082     __IM uint32_t RESERVED1;
20083 
20084     union
20085     {
20086         __IM uint32_t SD_ERR_STS1;      /*!< (@ 0x00000058) SD Error Status Register 1                                 */
20087 
20088         struct
20089         {
20090             __IM uint32_t CMDE0 : 1;    /*!< [0..0] Command Error 0NOTE: other than a response to a command
20091                                          *   issued within a command sequence                                          */
20092             __IM uint32_t CMDE1 : 1;    /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by
20093                                          *   setting a command index in SD_CMD, this is Indicated in
20094                                          *   CMDE0.                                                                    */
20095             __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to
20096                                          *   a command issued within a command sequence                                */
20097             __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is
20098                                          *   issued by setting a command index in SD_CMD, this is indicated
20099                                          *   in RSPLENE0.                                                              */
20100             __IM uint32_t RDLENE   : 1; /*!< [4..4] Read Data Length Error                                             */
20101             __IM uint32_t CRCLENE  : 1; /*!< [5..5] CRC Status Token Length Error                                      */
20102             uint32_t               : 2;
20103             __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a
20104                                          *   command issued within a command sequence                                  */
20105             __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued
20106                                          *   by setting a command index in SD_CMD, this is indicated
20107                                          *   in RSPCRCE0.                                                              */
20108             __IM uint32_t RDCRCE : 1;   /*!< [10..10] Read Data CRC Error                                              */
20109             __IM uint32_t CRCTKE : 1;   /*!< [11..11] CRC Status Token Error                                           */
20110             __IM uint32_t CRCTK  : 3;   /*!< [14..12] CRC Status TokenStore the CRC status token value (normal
20111                                          *   value is 010b)                                                            */
20112             uint32_t : 17;
20113         } SD_ERR_STS1_b;
20114     };
20115 
20116     union
20117     {
20118         __IM uint32_t SD_ERR_STS2;      /*!< (@ 0x0000005C) SD Error Status Register 2                                 */
20119 
20120         struct
20121         {
20122             __IM uint32_t RSPTO0   : 1; /*!< [0..0] Response Timeout 0                                                 */
20123             __IM uint32_t RSPTO1   : 1; /*!< [1..1] Response Timeout 1                                                 */
20124             __IM uint32_t BSYTO0   : 1; /*!< [2..2] Busy Timeout 0                                                     */
20125             __IM uint32_t BSYTO1   : 1; /*!< [3..3] Busy Timeout 1                                                     */
20126             __IM uint32_t RDTO     : 1; /*!< [4..4] Read Data Timeout                                                  */
20127             __IM uint32_t CRCTO    : 1; /*!< [5..5] CRC Status Token Timeout                                           */
20128             __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout                                      */
20129             uint32_t               : 25;
20130         } SD_ERR_STS2_b;
20131     };
20132 
20133     union
20134     {
20135         __IOM uint32_t SD_BUF0;         /*!< (@ 0x00000060) SD Buffer Register                                         */
20136 
20137         struct
20138         {
20139             __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write
20140                                          *   data is written to this register. When reading from the
20141                                          *   SD card, the read data is read from this register. This
20142                                          *   register is internally connected to two 512-byte buffers.If
20143                                          *   both buffers are not empty when executing multiple block
20144                                          *   read, SD/MMC clock is stopped to suspend receiving data.
20145                                          *   When one of buffers is empty, SD/MMC clock is supplied
20146                                          *   to resume receiving data.                                                 */
20147         } SD_BUF0_b;
20148     };
20149     __IM uint32_t RESERVED2;
20150 
20151     union
20152     {
20153         __IOM uint32_t SDIO_MODE;      /*!< (@ 0x00000068) SDIO Mode Control Register                                 */
20154 
20155         struct
20156         {
20157             __IOM uint32_t INTEN  : 1; /*!< [0..0] SDIO Mode                                                          */
20158             uint32_t              : 1;
20159             __IOM uint32_t RWREQ  : 1; /*!< [2..2] Read Wait Request                                                  */
20160             uint32_t              : 5;
20161             __IOM uint32_t IOABT  : 1; /*!< [8..8] SDIO AbortNOTE: See manual                                         */
20162             __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual                                    */
20163             uint32_t              : 22;
20164         } SDIO_MODE_b;
20165     };
20166 
20167     union
20168     {
20169         __IOM uint32_t SDIO_INFO1;      /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1                             */
20170 
20171         struct
20172         {
20173             __IOM uint32_t IOIRQ   : 1; /*!< [0..0] SDIO Interrupt Status                                              */
20174             uint32_t               : 13;
20175             __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual                              */
20176             __IOM uint32_t EXWT    : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual                                 */
20177             uint32_t               : 16;
20178         } SDIO_INFO1_b;
20179     };
20180 
20181     union
20182     {
20183         __IOM uint32_t SDIO_INFO1_MASK;  /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register                         */
20184 
20185         struct
20186         {
20187             __IOM uint32_t IOIRQM   : 1; /*!< [0..0] IOIRQ Interrupt Mask Control                                       */
20188             uint32_t                : 13;
20189             __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control                           */
20190             __IOM uint32_t EXWTM    : 1; /*!< [15..15] EXWT Interrupt Request Mask Control                              */
20191             uint32_t                : 16;
20192         } SDIO_INFO1_MASK_b;
20193     };
20194     __IM uint32_t RESERVED3[79];
20195 
20196     union
20197     {
20198         __IOM uint32_t SD_DMAEN;       /*!< (@ 0x000001B0) DMA Mode Enable Register                                   */
20199 
20200         struct
20201         {
20202             uint32_t             : 1;
20203             __IOM uint32_t DMAEN : 1;  /*!< [1..1] SD_BUF Read/Write DMA Transfer                                     */
20204             uint32_t             : 30;
20205         } SD_DMAEN_b;
20206     };
20207     __IM uint32_t RESERVED4[3];
20208 
20209     union
20210     {
20211         __IOM uint32_t SOFT_RST;       /*!< (@ 0x000001C0) Software Reset Register                                    */
20212 
20213         struct
20214         {
20215             __IOM uint32_t SDRST : 1;  /*!< [0..0] Software Reset of SD I/F Unit                                      */
20216             uint32_t             : 31;
20217         } SOFT_RST_b;
20218     };
20219     __IM uint32_t RESERVED5[2];
20220 
20221     union
20222     {
20223         __IOM uint32_t SDIF_MODE;      /*!< (@ 0x000001CC) SD Interface Mode Setting Register                         */
20224 
20225         struct
20226         {
20227             uint32_t               : 8;
20228             __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands)                             */
20229             uint32_t               : 23;
20230         } SDIF_MODE_b;
20231     };
20232     __IM uint32_t RESERVED6[4];
20233 
20234     union
20235     {
20236         __IOM uint32_t EXT_SWAP;       /*!< (@ 0x000001E0) Swap Control Register                                      */
20237 
20238         struct
20239         {
20240             uint32_t             : 6;
20241             __IOM uint32_t BWSWP : 1;  /*!< [6..6] SD_BUF0 Swap Write                                                 */
20242             __IOM uint32_t BRSWP : 1;  /*!< [7..7] SD_BUF0 Swap Read                                                  */
20243             uint32_t             : 24;
20244         } EXT_SWAP_b;
20245     };
20246 } R_SDHI0_Type;                        /*!< Size = 484 (0x1e4)                                                        */
20247 
20248 /* =========================================================================================================================== */
20249 /* ================                                          R_SLCDC                                          ================ */
20250 /* =========================================================================================================================== */
20251 
20252 /**
20253  * @brief Segment LCD Controller/Driver (R_SLCDC)
20254  */
20255 
20256 typedef struct                         /*!< (@ 0x40082000) R_SLCDC Structure                                          */
20257 {
20258     union
20259     {
20260         __IOM uint8_t LCDM0;           /*!< (@ 0x00000000) LCD Mode Register 0                                        */
20261 
20262         struct
20263         {
20264             __IOM uint8_t LBAS  : 2;   /*!< [1..0] LCD Display Bias Method Select                                     */
20265             __IOM uint8_t LDTY  : 3;   /*!< [4..2] Time Slice of LCD Display Select                                   */
20266             __IOM uint8_t LWAVE : 1;   /*!< [5..5] LCD display waveform selection                                     */
20267             __IOM uint8_t MDSET : 2;   /*!< [7..6] LCD drive voltage generator selection                              */
20268         } LCDM0_b;
20269     };
20270 
20271     union
20272     {
20273         __IOM uint8_t LCDM1;           /*!< (@ 0x00000001) LCD Mode Register 1                                        */
20274 
20275         struct
20276         {
20277             __IOM uint8_t LCDVLM : 1;  /*!< [0..0] Voltage Boosting Pin Initial Value Switching Control               */
20278             uint8_t              : 2;
20279             __IOM uint8_t LCDSEL : 1;  /*!< [3..3] Display data area control                                          */
20280             __IOM uint8_t BLON   : 1;  /*!< [4..4] Display data area control                                          */
20281             __IOM uint8_t VLCON  : 1;  /*!< [5..5] Voltage boost circuit or capacitor split circuit operation
20282                                         *   enable/disable                                                            */
20283             __IOM uint8_t SCOC  : 1;   /*!< [6..6] LCD Display Enable/Disable                                         */
20284             __IOM uint8_t LCDON : 1;   /*!< [7..7] LCD Display Enable/Disable                                         */
20285         } LCDM1_b;
20286     };
20287 
20288     union
20289     {
20290         __IOM uint8_t LCDC0;           /*!< (@ 0x00000002) LCD Clock Control Register 0                               */
20291 
20292         struct
20293         {
20294             __IOM uint8_t LCDC : 6;    /*!< [5..0] LCD clock (LCDCL)                                                  */
20295             uint8_t            : 2;
20296         } LCDC0_b;
20297     };
20298 
20299     union
20300     {
20301         __IOM uint8_t VLCD;            /*!< (@ 0x00000003) LCD Boost Level Control Register                           */
20302 
20303         struct
20304         {
20305             __IOM uint8_t VLCD : 5;    /*!< [4..0] Reference Voltage(Contrast Adjustment) Select                      */
20306             uint8_t            : 3;
20307         } VLCD_b;
20308     };
20309     __IM uint8_t RESERVED[252];
20310 
20311     union
20312     {
20313         __IOM uint8_t SEG[64];         /*!< (@ 0x00000100) LCD Display Data Array                                     */
20314 
20315         struct
20316         {
20317             __IOM uint8_t A : 4;       /*!< [3..0] A-Pattern Area                                                     */
20318             __IOM uint8_t B : 4;       /*!< [7..4] B-Pattern Area                                                     */
20319         } SEG_b[64];
20320     };
20321 } R_SLCDC_Type;                        /*!< Size = 320 (0x140)                                                        */
20322 
20323 /* =========================================================================================================================== */
20324 /* ================                                          R_SPI0                                           ================ */
20325 /* =========================================================================================================================== */
20326 
20327 /**
20328  * @brief Serial Peripheral Interface (R_SPI0)
20329  */
20330 
20331 typedef struct                         /*!< (@ 0x40072000) R_SPI0 Structure                                           */
20332 {
20333     union
20334     {
20335         __IOM uint8_t SPCR;            /*!< (@ 0x00000000) SPI Control Register                                       */
20336 
20337         struct
20338         {
20339             __IOM uint8_t SPMS   : 1;  /*!< [0..0] SPI Mode Select                                                    */
20340             __IOM uint8_t TXMD   : 1;  /*!< [1..1] Communications Operating Mode Select                               */
20341             __IOM uint8_t MODFEN : 1;  /*!< [2..2] Mode Fault Error Detection Enable                                  */
20342             __IOM uint8_t MSTR   : 1;  /*!< [3..3] SPI Master/Slave Mode Select                                       */
20343             __IOM uint8_t SPEIE  : 1;  /*!< [4..4] SPI Error Interrupt Enable                                         */
20344             __IOM uint8_t SPTIE  : 1;  /*!< [5..5] Transmit Buffer Empty Interrupt Enable                             */
20345             __IOM uint8_t SPE    : 1;  /*!< [6..6] SPI Function Enable                                                */
20346             __IOM uint8_t SPRIE  : 1;  /*!< [7..7] SPI Receive Buffer Full Interrupt Enable                           */
20347         } SPCR_b;
20348     };
20349 
20350     union
20351     {
20352         __IOM uint8_t SSLP;            /*!< (@ 0x00000001) SPI Slave Select Polarity Register                         */
20353 
20354         struct
20355         {
20356             __IOM uint8_t SSL0P : 1;   /*!< [0..0] SSL0 Signal Polarity Setting                                       */
20357             __IOM uint8_t SSL1P : 1;   /*!< [1..1] SSL1 Signal Polarity Setting                                       */
20358             __IOM uint8_t SSL2P : 1;   /*!< [2..2] SSL2 Signal Polarity Setting                                       */
20359             __IOM uint8_t SSL3P : 1;   /*!< [3..3] SSL3 Signal Polarity Setting                                       */
20360             __IOM uint8_t SSL4P : 1;   /*!< [4..4] SSL4 Signal Polarity Setting                                       */
20361             __IOM uint8_t SSL5P : 1;   /*!< [5..5] SSL5 Signal Polarity Setting                                       */
20362             __IOM uint8_t SSL6P : 1;   /*!< [6..6] SSL6 Signal Polarity Setting                                       */
20363             __IOM uint8_t SSL7P : 1;   /*!< [7..7] SSL7 Signal Polarity Setting                                       */
20364         } SSLP_b;
20365     };
20366 
20367     union
20368     {
20369         __IOM uint8_t SPPCR;           /*!< (@ 0x00000002) SPI Pin Control Register                                   */
20370 
20371         struct
20372         {
20373             __IOM uint8_t SPLP  : 1;   /*!< [0..0] SPI Loopback                                                       */
20374             __IOM uint8_t SPLP2 : 1;   /*!< [1..1] SPI Loopback 2                                                     */
20375             uint8_t             : 2;
20376             __IOM uint8_t MOIFV : 1;   /*!< [4..4] MOSI Idle Fixed Value                                              */
20377             __IOM uint8_t MOIFE : 1;   /*!< [5..5] MOSI Idle Value Fixing Enable                                      */
20378             uint8_t             : 2;
20379         } SPPCR_b;
20380     };
20381 
20382     union
20383     {
20384         __IOM uint8_t SPSR;            /*!< (@ 0x00000003) SPI Status Register                                        */
20385 
20386         struct
20387         {
20388             __IOM uint8_t OVRF  : 1;   /*!< [0..0] Overrun Error Flag                                                 */
20389             __IM uint8_t  IDLNF : 1;   /*!< [1..1] SPI Idle Flag                                                      */
20390             __IOM uint8_t MODF  : 1;   /*!< [2..2] Mode Fault Error Flag                                              */
20391             __IOM uint8_t PERF  : 1;   /*!< [3..3] Parity Error Flag                                                  */
20392             __IOM uint8_t UDRF  : 1;   /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.)          */
20393             __IOM uint8_t SPTEF : 1;   /*!< [5..5] SPI Transmit Buffer Empty Flag                                     */
20394             __IOM uint8_t CENDF : 1;   /*!< [6..6] Communication End Flag                                             */
20395             __IOM uint8_t SPRF  : 1;   /*!< [7..7] SPI Receive Buffer Full Flag                                       */
20396         } SPSR_b;
20397     };
20398 
20399     union
20400     {
20401         __IOM uint32_t SPDR;           /*!< (@ 0x00000004) SPI Data Register                                          */
20402         __IOM uint16_t SPDR_HA;        /*!< (@ 0x00000004) SPI Data Register ( halfword access )                      */
20403         __IOM uint8_t  SPDR_BY;        /*!< (@ 0x00000004) SPI Data Register ( byte access )                          */
20404     };
20405 
20406     union
20407     {
20408         __IOM uint8_t SPSCR;           /*!< (@ 0x00000008) SPI Sequence Control Register                              */
20409 
20410         struct
20411         {
20412             __IOM uint8_t SPSLN : 3;   /*!< [2..0] RSPI Sequence Length SpecificationThe order in which
20413                                         *   the SPCMD0 to SPCMD07 registers are to be referenced is
20414                                         *   changed in accordance with the sequence length that is
20415                                         *   set in these bits. The relationship among the setting of
20416                                         *   these bits, sequence length, and SPCMD0 to SPCMD7 registers
20417                                         *   referenced by the RSPI is shown above. However, the RSPI
20418                                         *   in slave mode always references SPCMD0.                                   */
20419             uint8_t : 5;
20420         } SPSCR_b;
20421     };
20422 
20423     union
20424     {
20425         __IM uint8_t SPSSR;            /*!< (@ 0x00000009) SPI Sequence Status Register                               */
20426 
20427         struct
20428         {
20429             __IM uint8_t SPCP  : 3;    /*!< [2..0] RSPI Command Pointer                                               */
20430             uint8_t            : 1;
20431             __IM uint8_t SPECM : 3;    /*!< [6..4] RSPI Error Command                                                 */
20432             uint8_t            : 1;
20433         } SPSSR_b;
20434     };
20435 
20436     union
20437     {
20438         __IOM uint8_t SPBR;            /*!< (@ 0x0000000A) SPI Bit Rate Register                                      */
20439 
20440         struct
20441         {
20442             __IOM uint8_t SPR : 8;     /*!< [7..0] SPBR sets the bit rate in master mode.                             */
20443         } SPBR_b;
20444     };
20445 
20446     union
20447     {
20448         __IOM uint8_t SPDCR;           /*!< (@ 0x0000000B) SPI Data Control Register                                  */
20449 
20450         struct
20451         {
20452             __IOM uint8_t SPFC   : 2;  /*!< [1..0] Number of Frames Specification                                     */
20453             __IOM uint8_t SLSEL  : 2;  /*!< [3..2] SSL Pin Output Select                                              */
20454             __IOM uint8_t SPRDTD : 1;  /*!< [4..4] SPI Receive/Transmit Data Selection                                */
20455             __IOM uint8_t SPLW   : 1;  /*!< [5..5] SPI Word Access/Halfword Access Specification                      */
20456             __IOM uint8_t SPBYT  : 1;  /*!< [6..6] SPI Byte Access Specification                                      */
20457             uint8_t              : 1;
20458         } SPDCR_b;
20459     };
20460 
20461     union
20462     {
20463         __IOM uint8_t SPCKD;           /*!< (@ 0x0000000C) SPI Clock Delay Register                                   */
20464 
20465         struct
20466         {
20467             __IOM uint8_t SCKDL : 3;   /*!< [2..0] RSPCK Delay Setting                                                */
20468             uint8_t             : 5;
20469         } SPCKD_b;
20470     };
20471 
20472     union
20473     {
20474         __IOM uint8_t SSLND;           /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register                   */
20475 
20476         struct
20477         {
20478             __IOM uint8_t SLNDL : 3;   /*!< [2..0] SSL Negation Delay Setting                                         */
20479             uint8_t             : 5;
20480         } SSLND_b;
20481     };
20482 
20483     union
20484     {
20485         __IOM uint8_t SPND;            /*!< (@ 0x0000000E) SPI Next-Access Delay Register                             */
20486 
20487         struct
20488         {
20489             __IOM uint8_t SPNDL : 3;   /*!< [2..0] SPI Next-Access Delay Setting                                      */
20490             uint8_t             : 5;
20491         } SPND_b;
20492     };
20493 
20494     union
20495     {
20496         __IOM uint8_t SPCR2;           /*!< (@ 0x0000000F) SPI Control Register 2                                     */
20497 
20498         struct
20499         {
20500             __IOM uint8_t SPPE   : 1;  /*!< [0..0] Parity Enable                                                      */
20501             __IOM uint8_t SPOE   : 1;  /*!< [1..1] Parity Mode                                                        */
20502             __IOM uint8_t SPIIE  : 1;  /*!< [2..2] SPI Idle Interrupt Enable                                          */
20503             __IOM uint8_t PTE    : 1;  /*!< [3..3] Parity Self-Testing                                                */
20504             __IOM uint8_t SCKASE : 1;  /*!< [4..4] RSPCK Auto-Stop Function Enable                                    */
20505             __IOM uint8_t SPTDDL : 3;  /*!< [7..5] RSPI Transmit Data Delay                                           */
20506         } SPCR2_b;
20507     };
20508 
20509     union
20510     {
20511         __IOM uint16_t SPCMD[8];       /*!< (@ 0x00000010) SPI Command Register [0..7]                                */
20512 
20513         struct
20514         {
20515             __IOM uint16_t CPHA   : 1; /*!< [0..0] RSPCK Phase Setting                                                */
20516             __IOM uint16_t CPOL   : 1; /*!< [1..1] RSPCK Polarity Setting                                             */
20517             __IOM uint16_t BRDV   : 2; /*!< [3..2] Bit Rate Division Setting                                          */
20518             __IOM uint16_t SSLA   : 3; /*!< [6..4] SSL Signal Assertion Setting                                       */
20519             __IOM uint16_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Keeping                                           */
20520             __IOM uint16_t SPB    : 4; /*!< [11..8] SPI Data Length Setting                                           */
20521             __IOM uint16_t LSBF   : 1; /*!< [12..12] SPI LSB First                                                    */
20522             __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable                                     */
20523             __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
20524             __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
20525         } SPCMD_b[8];
20526     };
20527 
20528     union
20529     {
20530         __IOM uint8_t SPDCR2;          /*!< (@ 0x00000020) SPI Data Control Register 2                                */
20531 
20532         struct
20533         {
20534             __IOM uint8_t BYSW : 1;    /*!< [0..0] Byte Swap Operating Mode Select                                    */
20535             __IOM uint8_t SINV : 1;    /*!< [1..1] Serial data invert bit                                             */
20536             uint8_t            : 6;
20537         } SPDCR2_b;
20538     };
20539 
20540     union
20541     {
20542         __IOM uint8_t SPCR3;           /*!< (@ 0x00000021) RSPI Control Register 3                                    */
20543 
20544         struct
20545         {
20546             __IOM uint8_t ETXMD  : 1;  /*!< [0..0] Extended Communication Mode Select                                 */
20547             __IOM uint8_t BFDS   : 1;  /*!< [1..1] Between Burst Transfer Frames Delay Select                         */
20548             uint8_t              : 2;
20549             __IOM uint8_t CENDIE : 1;  /*!< [4..4] RSPI Communication End Interrupt Enable                            */
20550             uint8_t              : 3;
20551         } SPCR3_b;
20552     };
20553     __IM uint16_t RESERVED;
20554     __IM uint32_t RESERVED1[6];
20555     __IM uint16_t RESERVED2;
20556 
20557     union
20558     {
20559         __IOM uint16_t SPPR;           /*!< (@ 0x0000003E) RSPI Parameter Read Register                               */
20560 
20561         struct
20562         {
20563             uint16_t              : 4;
20564             __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check                                                 */
20565             uint16_t              : 3;
20566             __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check                                               */
20567             uint16_t              : 1;
20568             __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check                                             */
20569         } SPPR_b;
20570     };
20571 } R_SPI0_Type;                         /*!< Size = 64 (0x40)                                                          */
20572 
20573 /* =========================================================================================================================== */
20574 /* ================                                          R_SRAM                                           ================ */
20575 /* =========================================================================================================================== */
20576 
20577 /**
20578  * @brief SRAM (R_SRAM)
20579  */
20580 
20581 typedef struct                         /*!< (@ 0x40002000) R_SRAM Structure                                           */
20582 {
20583     union
20584     {
20585         __IOM uint8_t PARIOAD;         /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register       */
20586 
20587         struct
20588         {
20589             __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after Detection                                          */
20590             uint8_t           : 7;
20591         } PARIOAD_b;
20592     };
20593     __IM uint8_t RESERVED[3];
20594 
20595     union
20596     {
20597         __IOM uint8_t SRAMPRCR;         /*!< (@ 0x00000004) SRAM Protection Register                                   */
20598 
20599         struct
20600         {
20601             __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control                                             */
20602             __OM uint8_t  KW       : 7; /*!< [7..1] Write Key Code                                                     */
20603         } SRAMPRCR_b;
20604     };
20605     __IM uint8_t  RESERVED1[3];
20606     __IOM uint8_t SRAMWTSC;             /*!< (@ 0x00000008) RAM Wait State Control Register                            */
20607     __IM uint8_t  RESERVED2[3];
20608 
20609     union
20610     {
20611         __IOM uint8_t SRAMPRCR2;         /*!< (@ 0x0000000C) SRAM Protection Register 2                                 */
20612 
20613         struct
20614         {
20615             __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control                                             */
20616             __OM uint8_t  KW        : 7; /*!< [7..1] Write Key Code                                                     */
20617         } SRAMPRCR2_b;
20618     };
20619     __IM uint8_t RESERVED3[179];
20620 
20621     union
20622     {
20623         __IOM uint8_t ECCMODE;         /*!< (@ 0x000000C0) ECC Operating Mode Control Register                        */
20624 
20625         struct
20626         {
20627             __IOM uint8_t ECCMOD : 2;  /*!< [1..0] ECC Operating Mode Select                                          */
20628             uint8_t              : 6;
20629         } ECCMODE_b;
20630     };
20631 
20632     union
20633     {
20634         __IOM uint8_t ECC2STS;         /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register                            */
20635 
20636         struct
20637         {
20638             __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status                                             */
20639             uint8_t               : 7;
20640         } ECC2STS_b;
20641     };
20642 
20643     union
20644     {
20645         __IOM uint8_t ECC1STSEN;       /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register         */
20646 
20647         struct
20648         {
20649             __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable                          */
20650             uint8_t               : 7;
20651         } ECC1STSEN_b;
20652     };
20653 
20654     union
20655     {
20656         __IOM uint8_t ECC1STS;         /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register                            */
20657 
20658         struct
20659         {
20660             __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status                                             */
20661             uint8_t               : 7;
20662         } ECC1STS_b;
20663     };
20664 
20665     union
20666     {
20667         __IOM uint8_t ECCPRCR;         /*!< (@ 0x000000C4) ECC Protection Register                                    */
20668 
20669         struct
20670         {
20671             __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control                                             */
20672             __OM uint8_t  KW      : 7; /*!< [7..1] Write Key Code                                                     */
20673         } ECCPRCR_b;
20674     };
20675     __IM uint8_t RESERVED4[11];
20676 
20677     union
20678     {
20679         __IOM uint8_t ECCPRCR2;         /*!< (@ 0x000000D0) ECC Protection Register 2                                  */
20680 
20681         struct
20682         {
20683             __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control                                             */
20684             __OM uint8_t  KW2      : 7; /*!< [7..1] Write Key Code                                                     */
20685         } ECCPRCR2_b;
20686     };
20687     __IM uint8_t RESERVED5[3];
20688 
20689     union
20690     {
20691         __IOM uint8_t ECCETST;         /*!< (@ 0x000000D4) ECC Test Control Register                                  */
20692 
20693         struct
20694         {
20695             __IOM uint8_t TSTBYP : 1;  /*!< [0..0] ECC Bypass Select                                                  */
20696             uint8_t              : 7;
20697         } ECCETST_b;
20698     };
20699     __IM uint8_t RESERVED6[3];
20700 
20701     union
20702     {
20703         __IOM uint8_t ECCOAD;          /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register          */
20704 
20705         struct
20706         {
20707             __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after Detection                                          */
20708             uint8_t           : 7;
20709         } ECCOAD_b;
20710     };
20711 } R_SRAM_Type;                         /*!< Size = 217 (0xd9)                                                         */
20712 
20713 /* =========================================================================================================================== */
20714 /* ================                                          R_BUS_B                                          ================ */
20715 /* =========================================================================================================================== */
20716 
20717 /**
20718  * @brief Bus Interface (R_BUS_B)
20719  */
20720 
20721 typedef struct                          /*!< (@ 0x40003000) R_BUS_B Structure                                          */
20722 {
20723     __IOM R_BUS_B_CSa_Type CSa[8];      /*!< (@ 0x00000000) CS Registers                                               */
20724     __IM uint32_t          RESERVED[480];
20725     __IOM R_BUS_B_CSb_Type CSb[8];      /*!< (@ 0x00000800) CS Registers                                               */
20726 
20727     union
20728     {
20729         __IOM uint16_t CSRECEN;         /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register                */
20730 
20731         struct
20732         {
20733             __IOM uint16_t RCVEN0  : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable                       */
20734             __IOM uint16_t RCVEN1  : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable                       */
20735             __IOM uint16_t RCVEN2  : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable                       */
20736             __IOM uint16_t RCVEN3  : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable                       */
20737             __IOM uint16_t RCVEN4  : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable                       */
20738             __IOM uint16_t RCVEN5  : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable                       */
20739             __IOM uint16_t RCVEN6  : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable                       */
20740             __IOM uint16_t RCVEN7  : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable                       */
20741             __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable                    */
20742             __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable                    */
20743             __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable                  */
20744             __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable                  */
20745             __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable                  */
20746             __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable                  */
20747             __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable                  */
20748             __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable                  */
20749         } CSRECEN_b;
20750     };
20751     __IM uint16_t RESERVED1;
20752     __IM uint32_t RESERVED2[543];
20753 
20754     union
20755     {
20756         __IOM uint16_t BUSSCNTFHBIU;   /*!< (@ 0x00001100) Slave Bus Control Register                                 */
20757 
20758         struct
20759         {
20760             __IOM uint16_t ARBS : 2;   /*!< [1..0] Arbitration Select for three masters                               */
20761             uint16_t            : 14;
20762         } BUSSCNTFHBIU_b;
20763     };
20764     __IM uint16_t RESERVED3;
20765 
20766     union
20767     {
20768         __IOM uint16_t BUSSCNTFLBIU;   /*!< (@ 0x00001104) Slave Bus Control Register                                 */
20769 
20770         struct
20771         {
20772             __IOM uint16_t ARBS : 2;   /*!< [1..0] Arbitration Select for three masters                               */
20773             uint16_t            : 14;
20774         } BUSSCNTFLBIU_b;
20775     };
20776     __IM uint16_t RESERVED4;
20777     __IM uint32_t RESERVED5[2];
20778 
20779     union
20780     {
20781         __IOM uint16_t BUSSCNTS0BIU;   /*!< (@ 0x00001110) Slave Bus Control Register                                 */
20782 
20783         struct
20784         {
20785             __IOM uint16_t ARBS : 2;   /*!< [1..0] Arbitration Select for three masters                               */
20786             uint16_t            : 14;
20787         } BUSSCNTS0BIU_b;
20788     };
20789     __IM uint16_t RESERVED6;
20790     __IM uint32_t RESERVED7[3];
20791 
20792     union
20793     {
20794         __IOM uint16_t BUSSCNTPSBIU;   /*!< (@ 0x00001120) Slave Bus Control Register                                 */
20795 
20796         struct
20797         {
20798             __IOM uint16_t ARBS : 1;   /*!< [0..0] Arbitration Select for two masters                                 */
20799             uint16_t            : 15;
20800         } BUSSCNTPSBIU_b;
20801     };
20802     __IM uint16_t RESERVED8;
20803     __IM uint32_t RESERVED9[3];
20804 
20805     union
20806     {
20807         __IOM uint16_t BUSSCNTPLBIU;   /*!< (@ 0x00001130) Slave Bus Control Register                                 */
20808 
20809         struct
20810         {
20811             __IOM uint16_t ARBS : 1;   /*!< [0..0] Arbitration Select for two masters                                 */
20812             uint16_t            : 15;
20813         } BUSSCNTPLBIU_b;
20814     };
20815     __IM uint16_t RESERVED10;
20816 
20817     union
20818     {
20819         __IOM uint16_t BUSSCNTPHBIU;   /*!< (@ 0x00001134) Slave Bus Control Register                                 */
20820 
20821         struct
20822         {
20823             __IOM uint16_t ARBS : 1;   /*!< [0..0] Arbitration Select for two masters                                 */
20824             uint16_t            : 15;
20825         } BUSSCNTPHBIU_b;
20826     };
20827     __IM uint16_t RESERVED11;
20828     __IM uint32_t RESERVED12[2];
20829 
20830     union
20831     {
20832         __IOM uint16_t BUSSCNTEQBIU;   /*!< (@ 0x00001140) Slave Bus Control Register                                 */
20833 
20834         struct
20835         {
20836             __IOM uint16_t ARBS : 2;   /*!< [1..0] Arbitration Select for three masters                               */
20837             uint16_t            : 14;
20838         } BUSSCNTEQBIU_b;
20839     };
20840     __IM uint16_t RESERVED13;
20841 
20842     union
20843     {
20844         __IOM uint16_t BUSSCNTEOBIU;   /*!< (@ 0x00001144) Slave Bus Control Register                                 */
20845 
20846         struct
20847         {
20848             __IOM uint16_t ARBS : 2;   /*!< [1..0] Arbitration Select for three masters                               */
20849             uint16_t            : 14;
20850         } BUSSCNTEOBIU_b;
20851     };
20852     __IM uint16_t RESERVED14;
20853 
20854     union
20855     {
20856         __IOM uint16_t BUSSCNTECBIU;   /*!< (@ 0x00001148) Slave Bus Control Register                                 */
20857 
20858         struct
20859         {
20860             __IOM uint16_t ARBS : 2;   /*!< [1..0] Arbitration Select for three masters                               */
20861             uint16_t            : 14;
20862         } BUSSCNTECBIU_b;
20863     };
20864     __IM uint16_t                RESERVED15;
20865     __IM uint32_t                RESERVED16[429];
20866     __IOM R_BUS_B_BUSERR_Type    BUSERR[4];    /*!< (@ 0x00001800) Bus Error Registers                                        */
20867     __IM uint32_t                RESERVED17[48];
20868     __IOM R_BUS_B_BUSTZFERR_Type BUSTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers                                    */
20869     __IM uint32_t                RESERVED18[48];
20870 
20871     union
20872     {
20873         __IM uint8_t BUS1ERRSTAT;       /*!< (@ 0x00001A00) BUS Error Status Register 1                                */
20874 
20875         struct
20876         {
20877             __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status                                             */
20878             __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status                                */
20879             uint8_t                : 1;
20880             __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status                                            */
20881             __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status                                */
20882             uint8_t                : 3;
20883         } BUS1ERRSTAT_b;
20884     };
20885     __IM uint8_t  RESERVED19;
20886     __IM uint16_t RESERVED20;
20887     __IM uint32_t RESERVED21;
20888 
20889     union
20890     {
20891         __IOM uint8_t BUS1ERRCLR;       /*!< (@ 0x00001A08) BUS Error Clear Register 1                                 */
20892 
20893         struct
20894         {
20895             __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear                                              */
20896             __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear                                 */
20897             uint8_t                : 1;
20898             __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear                                             */
20899             __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear                                 */
20900             uint8_t                : 3;
20901         } BUS1ERRCLR_b;
20902     };
20903     __IM uint8_t  RESERVED22;
20904     __IM uint16_t RESERVED23;
20905     __IM uint32_t RESERVED24;
20906 
20907     union
20908     {
20909         __IM uint8_t BUS2ERRSTAT;       /*!< (@ 0x00001A10) BUS Error Status Register 2                                */
20910 
20911         struct
20912         {
20913             __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status                                             */
20914             __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status                                */
20915             uint8_t                : 1;
20916             __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status                                            */
20917             __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status                                */
20918             uint8_t                : 3;
20919         } BUS2ERRSTAT_b;
20920     };
20921     __IM uint8_t  RESERVED25;
20922     __IM uint16_t RESERVED26;
20923     __IM uint32_t RESERVED27;
20924 
20925     union
20926     {
20927         __IOM uint8_t BUS2ERRCLR;       /*!< (@ 0x00001A18) BUS Error Clear Register 2                                 */
20928 
20929         struct
20930         {
20931             __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear                                              */
20932             __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear                                 */
20933             uint8_t                : 1;
20934             __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear                                             */
20935             __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear                                 */
20936             uint8_t                : 3;
20937         } BUS2ERRCLR_b;
20938     };
20939     __IM uint8_t  RESERVED28;
20940     __IM uint16_t RESERVED29;
20941     __IM uint32_t RESERVED30;
20942 
20943     union
20944     {
20945         __IM uint8_t BUS3ERRSTAT;       /*!< (@ 0x00001A20) BUS Error Status Register 3                                */
20946 
20947         struct
20948         {
20949             __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status                                             */
20950             __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status                                */
20951             uint8_t                : 1;
20952             __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status                                            */
20953             __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status                                */
20954             uint8_t                : 3;
20955         } BUS3ERRSTAT_b;
20956     };
20957     __IM uint8_t  RESERVED31;
20958     __IM uint16_t RESERVED32;
20959 
20960     union
20961     {
20962         __IM uint8_t DMACDTCERRSTAT;    /*!< (@ 0x00001A24) DMAC/DTC Error Status Register                             */
20963 
20964         struct
20965         {
20966             __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status                               */
20967             uint8_t                : 7;
20968         } DMACDTCERRSTAT_b;
20969     };
20970     __IM uint8_t  RESERVED33;
20971     __IM uint16_t RESERVED34;
20972 
20973     union
20974     {
20975         __IOM uint8_t BUS3ERRCLR;       /*!< (@ 0x00001A28) BUS Error Clear Register 3                                 */
20976 
20977         struct
20978         {
20979             __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear                                              */
20980             __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear                                 */
20981             uint8_t                : 1;
20982             __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear                                             */
20983             __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear                                 */
20984             uint8_t                : 3;
20985         } BUS3ERRCLR_b;
20986     };
20987     __IM uint8_t  RESERVED35;
20988     __IM uint16_t RESERVED36;
20989 
20990     union
20991     {
20992         __IOM uint8_t DMACDTCERRCLR;    /*!< (@ 0x00001A2C) DMAC/DTC Error Clear Register                              */
20993 
20994         struct
20995         {
20996             __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear                                */
20997             uint8_t                : 7;
20998         } DMACDTCERRCLR_b;
20999     };
21000     __IM uint8_t  RESERVED37;
21001     __IM uint16_t RESERVED38;
21002 
21003     union
21004     {
21005         __IM uint8_t BUS4ERRSTAT;       /*!< (@ 0x00001A30) BUS Error Status Register 4                                */
21006 
21007         struct
21008         {
21009             __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status                                             */
21010             __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status                                */
21011             uint8_t                : 1;
21012             __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status                                            */
21013             __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status                                */
21014             uint8_t                : 3;
21015         } BUS4ERRSTAT_b;
21016     };
21017     __IM uint8_t  RESERVED39;
21018     __IM uint16_t RESERVED40;
21019     __IM uint32_t RESERVED41;
21020 
21021     union
21022     {
21023         __IOM uint8_t BUS4ERRCLR;       /*!< (@ 0x00001A38) BUS Error Clear Register 4                                 */
21024 
21025         struct
21026         {
21027             __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear                                              */
21028             __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear                                 */
21029             uint8_t                : 1;
21030             __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear                                             */
21031             __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear                                 */
21032             uint8_t                : 3;
21033         } BUS4ERRCLR_b;
21034     };
21035     __IM uint8_t  RESERVED42;
21036     __IM uint16_t RESERVED43;
21037 } R_BUS_B_Type;                        /*!< Size = 6716 (0x1a3c)                                                      */
21038 
21039 /* =========================================================================================================================== */
21040 /* ================                                           R_SRC                                           ================ */
21041 /* =========================================================================================================================== */
21042 
21043 /**
21044  * @brief Sampling Rate Converter (R_SRC)
21045  */
21046 
21047 typedef struct                           /*!< (@ 0x40048000) R_SRC Structure                                            */
21048 {
21049     union
21050     {
21051         __IOM uint32_t SRCFCTR[5552];    /*!< (@ 0x00000000) Filter Coefficient Table [0..5551]                         */
21052 
21053         struct
21054         {
21055             __IOM uint32_t SRCFCOE : 22; /*!< [21..0] Stores a filter coefficient value.                                */
21056             uint32_t               : 10;
21057         } SRCFCTR_b[5552];
21058     };
21059     __IM uint32_t RESERVED[588];
21060 
21061     union
21062     {
21063         __OM uint32_t SRCID;           /*!< (@ 0x00005FF0) Input Data Register                                        */
21064 
21065         struct
21066         {
21067             __OM uint32_t SRCID : 32;  /*!< [31..0] SRCID is a 32-bit writ-only register that is used to
21068                                         *   input the data before sampling rate conversion. All the
21069                                         *   bits are read as 0.                                                       */
21070         } SRCID_b;
21071     };
21072 
21073     union
21074     {
21075         __IM uint32_t SRCOD;           /*!< (@ 0x00005FF4) Output Data Register                                       */
21076 
21077         struct
21078         {
21079             __IM uint32_t SRCOD : 32;  /*!< [31..0] SRCOD is a 32-bit read-only register used to output
21080                                         *   the data after sampling rate conversion. The data in the
21081                                         *   16-stage output data FIFO is read through SRCOD. When the
21082                                         *   number of data in the output data FIFO is zero after the
21083                                         *   start of conversion, the value previously read is read
21084                                         *   again.                                                                    */
21085         } SRCOD_b;
21086     };
21087 
21088     union
21089     {
21090         __IOM uint16_t SRCIDCTRL;      /*!< (@ 0x00005FF8) Input Data Control Register                                */
21091 
21092         struct
21093         {
21094             __IOM uint16_t IFTRG : 2;  /*!< [1..0] Input FIFO Data Triggering Number                                  */
21095             uint16_t             : 6;
21096             __IOM uint16_t IEN   : 1;  /*!< [8..8] Input FIFO Empty Interrupt Enable                                  */
21097             __IOM uint16_t IED   : 1;  /*!< [9..9] Input Data Endian                                                  */
21098             uint16_t             : 6;
21099         } SRCIDCTRL_b;
21100     };
21101 
21102     union
21103     {
21104         __IOM uint16_t SRCODCTRL;      /*!< (@ 0x00005FFA) Output Data Control Register                               */
21105 
21106         struct
21107         {
21108             __IOM uint16_t OFTRG : 2;  /*!< [1..0] Output FIFO Data Trigger Number                                    */
21109             uint16_t             : 6;
21110             __IOM uint16_t OEN   : 1;  /*!< [8..8] Output Data FIFO Full Interrupt Enable                             */
21111             __IOM uint16_t OED   : 1;  /*!< [9..9] Output Data Endian                                                 */
21112             __IOM uint16_t OCH   : 1;  /*!< [10..10] Output Data Channel Exchange                                     */
21113             uint16_t             : 5;
21114         } SRCODCTRL_b;
21115     };
21116 
21117     union
21118     {
21119         __IOM uint16_t SRCCTRL;        /*!< (@ 0x00005FFC) Control Register                                           */
21120 
21121         struct
21122         {
21123             __IOM uint16_t OFS    : 3; /*!< [2..0] Output Sampling Rate                                               */
21124             uint16_t              : 1;
21125             __IOM uint16_t IFS    : 4; /*!< [7..4] Input Sampling Rate                                                */
21126             __IOM uint16_t CL     : 1; /*!< [8..8] Internal Work Memory Clear                                         */
21127             __IOM uint16_t FL     : 1; /*!< [9..9] Internal Work Memory Flush                                         */
21128             __IOM uint16_t OVEN   : 1; /*!< [10..10] Output Data FIFO Overwrite Interrupt Enable                      */
21129             __IOM uint16_t UDEN   : 1; /*!< [11..11] Output Data FIFO Underflow Interrupt Enable                      */
21130             __IOM uint16_t SRCEN  : 1; /*!< [12..12] Module Enable                                                    */
21131             __IOM uint16_t CEEN   : 1; /*!< [13..13] Conversion End Interrupt Enable                                  */
21132             uint16_t              : 1;
21133             __IOM uint16_t FICRAE : 1; /*!< [15..15] Filter Coefficient Table Access Enable                           */
21134         } SRCCTRL_b;
21135     };
21136 
21137     union
21138     {
21139         __IOM uint16_t SRCSTAT;        /*!< (@ 0x00005FFE) Status Register                                            */
21140 
21141         struct
21142         {
21143             __IOM uint16_t OINT : 1;   /*!< [0..0] Output Data FIFO Full Interrupt Request Flag                       */
21144             __IOM uint16_t IINT : 1;   /*!< [1..1] Input Data FIFO Empty Interrupt Request Flag                       */
21145             __IOM uint16_t OVF  : 1;   /*!< [2..2] Output Data FIFO Overwrite Interrupt Request Flag                  */
21146             __IOM uint16_t UDF  : 1;   /*!< [3..3] Output FIFO Underflow Interrupt Request Flag                       */
21147             __IM uint16_t  FLF  : 1;   /*!< [4..4] Flush Processing Status Flag                                       */
21148             __IOM uint16_t CEF  : 1;   /*!< [5..5] Conversion End Flag                                                */
21149             uint16_t            : 1;
21150             __IOM uint16_t IFDN : 4;   /*!< [10..7] Input FIFO Data CountIndicates the number of data units
21151                                         *   in the input FIFO.                                                        */
21152             __IOM uint16_t OFDN : 5;   /*!< [15..11] Output FIFO Data CountIndicates the number of data
21153                                         *   units in the output FIFO.                                                 */
21154         } SRCSTAT_b;
21155     };
21156 } R_SRC_Type;                          /*!< Size = 24576 (0x6000)                                                     */
21157 
21158 /* =========================================================================================================================== */
21159 /* ================                                          R_SSI0                                           ================ */
21160 /* =========================================================================================================================== */
21161 
21162 /**
21163  * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0)
21164  */
21165 
21166 typedef struct                         /*!< (@ 0x4004E000) R_SSI0 Structure                                           */
21167 {
21168     union
21169     {
21170         __IOM uint32_t SSICR;          /*!< (@ 0x00000000) Control Register                                           */
21171 
21172         struct
21173         {
21174             __IOM uint32_t REN  : 1;   /*!< [0..0] Receive Enable                                                     */
21175             __IOM uint32_t TEN  : 1;   /*!< [1..1] Transmit Enable                                                    */
21176             uint32_t            : 1;
21177             __IOM uint32_t MUEN : 1;   /*!< [3..3] Mute EnableNOTE: When this module is muted, the value
21178                                         *   of outputting serial data is rewritten to 0 but data transmission
21179                                         *   is not stopped. Write dummy data to the SSIFTDR not to
21180                                         *   generate a transmit underflow because the number of data
21181                                         *   in the transmit FIFO is decreasing.                                       */
21182             __IOM uint32_t CKDV  : 4;  /*!< [7..4] Serial Oversampling Clock Division Ratio                           */
21183             __IOM uint32_t DEL   : 1;  /*!< [8..8] Serial Data Delay                                                  */
21184             __IOM uint32_t PDTA  : 1;  /*!< [9..9] Parallel Data Alignment                                            */
21185             __IOM uint32_t SDTA  : 1;  /*!< [10..10] Serial Data Alignment                                            */
21186             __IOM uint32_t SPDP  : 1;  /*!< [11..11] Serial Padding Polarity                                          */
21187             __IOM uint32_t LRCKP : 1;  /*!< [12..12] Serial WS Polarity                                               */
21188             __IOM uint32_t BCKP  : 1;  /*!< [13..13] Serial Bit Clock Polarity                                        */
21189             __IOM uint32_t MST   : 1;  /*!< [14..14] Serial WS Direction NOTE: Only the following settings
21190                                         *   are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings
21191                                         *   are prohibited.                                                           */
21192             uint32_t           : 1;
21193             __IOM uint32_t SWL : 3;    /*!< [18..16] System Word LengthSet the system word length to the
21194                                         *   bit clock frequency/2 fs.                                                 */
21195             __IOM uint32_t DWL   : 3;  /*!< [21..19] Data Word Length                                                 */
21196             __IOM uint32_t FRM   : 2;  /*!< [23..22] Channels                                                         */
21197             uint32_t             : 1;
21198             __IOM uint32_t IIEN  : 1;  /*!< [25..25] Idle Mode Interrupt Enable                                       */
21199             __IOM uint32_t ROIEN : 1;  /*!< [26..26] Receive Overflow Interrupt Enable                                */
21200             __IOM uint32_t RUIEN : 1;  /*!< [27..27] Receive Underflow Interrupt Enable                               */
21201             __IOM uint32_t TOIEN : 1;  /*!< [28..28] Transmit Overflow Interrupt Enable                               */
21202             __IOM uint32_t TUIEN : 1;  /*!< [29..29] Transmit Underflow Interrupt Enable                              */
21203             __IOM uint32_t CKS   : 1;  /*!< [30..30] Oversampling Clock Select                                        */
21204             uint32_t             : 1;
21205         } SSICR_b;
21206     };
21207 
21208     union
21209     {
21210         __IOM uint32_t SSISR;          /*!< (@ 0x00000004) Status Register                                            */
21211 
21212         struct
21213         {
21214             __IM uint32_t IDST   : 1;  /*!< [0..0] Idle Mode Status Flag                                              */
21215             __IM uint32_t RSWNO  : 1;  /*!< [1..1] Receive Serial Word Number                                         */
21216             __IM uint32_t RCHNO  : 2;  /*!< [3..2] Receive Channel Number.These bits are read as 00b.                 */
21217             __IM uint32_t TSWNO  : 1;  /*!< [4..4] Transmit Serial Word Number                                        */
21218             __IM uint32_t TCHNO  : 2;  /*!< [6..5] Transmit Channel Number                                            */
21219             uint32_t             : 18;
21220             __IM uint32_t  IIRQ  : 1;  /*!< [25..25] Idle Mode Interrupt Status Flag                                  */
21221             __IOM uint32_t ROIRQ : 1;  /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE:
21222                                         *   Writable only to clear the flag. Confirm the value is 1
21223                                         *   and then write 0.                                                         */
21224             __IOM uint32_t RUIRQ : 1;  /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE:
21225                                         *   Writable only to clear the flag. Confirm the value is 1
21226                                         *   and then write 0.                                                         */
21227             __IOM uint32_t TOIRQ : 1;  /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE:
21228                                         *   Writable only to clear the flag. Confirm the value is 1
21229                                         *   and then write 0.                                                         */
21230             __IOM uint32_t TUIRQ : 1;  /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE:
21231                                         *   Writable only to clear the flag. Confirm the value is 1
21232                                         *   and then write 0.                                                         */
21233             uint32_t : 2;
21234         } SSISR_b;
21235     };
21236     __IM uint32_t RESERVED[2];
21237 
21238     union
21239     {
21240         __IOM uint32_t SSIFCR;         /*!< (@ 0x00000010) FIFO Control Register                                      */
21241 
21242         struct
21243         {
21244             __IOM uint32_t RFRST : 1;  /*!< [0..0] Receive FIFO Data Register Reset                                   */
21245             __IOM uint32_t TFRST : 1;  /*!< [1..1] Transmit FIFO Data Register Reset                                  */
21246             __IOM uint32_t RIE   : 1;  /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by
21247                                         *   clearing either the RDF flag (see the description of the
21248                                         *   RDF bit for details) or RIE bit.                                          */
21249             __IOM uint32_t TIE : 1;    /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by
21250                                         *   clearing either the TDE flag (see the description of the
21251                                         *   TDE bit for details) or TIE bit.                                          */
21252             __IOM uint32_t RTRG : 2;   /*!< [5..4] Receive Data Trigger Number                                        */
21253             __IOM uint32_t TTRG : 2;   /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis
21254                                         *   are the number of empty stages in SSIFTDR at which the
21255                                         *   TDE flag is set.                                                          */
21256             uint32_t              : 3;
21257             __IOM uint32_t BSW    : 1; /*!< [11..11] Byte Swap Enable                                                 */
21258             uint32_t              : 4;
21259             __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset                                              */
21260             uint32_t              : 14;
21261             __IOM uint32_t AUCKE  : 1; /*!< [31..31] Oversampling Clock Enable                                        */
21262         } SSIFCR_b;
21263     };
21264 
21265     union
21266     {
21267         __IOM uint32_t SSIFSR;         /*!< (@ 0x00000014) FIFO Status Register                                       */
21268 
21269         struct
21270         {
21271             __IOM uint32_t RDF : 1;    /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register
21272                                         *   is a 32-byte FIFO register, the maximum number of data
21273                                         *   bytes that can be read from it while the RDF flag is 1
21274                                         *   is indicated in the RDC[3:0] flags. If reading data from
21275                                         *   the SSIFRDR register is continued after all the data is
21276                                         *   read, undefined values will be read.                                      */
21277             uint32_t          : 7;
21278             __IM uint32_t RDC : 6;     /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data
21279                                         *   units stored in SSIFRDR)                                                  */
21280             uint32_t           : 2;
21281             __IOM uint32_t TDE : 1;    /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register
21282                                         *   is a 32-byte FIFO register, the maximum number of bytes
21283                                         *   that can be written to it while the TDE flag is 1 is 8
21284                                         *   - TDC[3:0]. If writing data to the SSIFTDR register is
21285                                         *   continued after all the data is written, writing will be
21286                                         *   invalid and an overflow occurs.                                           */
21287             uint32_t          : 7;
21288             __IM uint32_t TDC : 6;     /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of
21289                                         *   data units stored in SSIFTDR)                                             */
21290             uint32_t : 2;
21291         } SSIFSR_b;
21292     };
21293 
21294     union
21295     {
21296         union
21297         {
21298             __OM uint32_t SSIFTDR;          /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
21299 
21300             struct
21301             {
21302                 __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of
21303                                              *   eight stages of 32-bit registers for storing data to be
21304                                              *   serially transmitted. NOTE: that when the SSIFTDR register
21305                                              *   is full of data (32 bytes), the next data cannot be written
21306                                              *   to it. If writing is attempted, it will be ignored and
21307                                              *   an overflow occurs.                                                       */
21308             } SSIFTDR_b;
21309         };
21310         __OM uint16_t SSIFTDR16;            /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
21311         __OM uint8_t  SSIFTDR8;             /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
21312     };
21313 
21314     union
21315     {
21316         union
21317         {
21318             __IM uint32_t SSIFRDR;          /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
21319 
21320             struct
21321             {
21322                 __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight
21323                                              *   stages of 32-bit registers for storing serially received
21324                                              *   data.                                                                     */
21325             } SSIFRDR_b;
21326         };
21327         __IM uint16_t SSIFRDR16;            /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
21328         __IM uint8_t  SSIFRDR8;             /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
21329     };
21330 
21331     union
21332     {
21333         __IOM uint32_t SSIOFR;          /*!< (@ 0x00000020) Audio Format Register                                      */
21334 
21335         struct
21336         {
21337             __IOM uint32_t OMOD    : 2; /*!< [1..0] Audio Format Select                                                */
21338             uint32_t               : 6;
21339             __IOM uint32_t LRCONT  : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation                             */
21340             __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in
21341                                          *   Idle Status                                                               */
21342             uint32_t : 22;
21343         } SSIOFR_b;
21344     };
21345 
21346     union
21347     {
21348         __IOM uint32_t SSISCR;         /*!< (@ 0x00000024) Status Control Register                                    */
21349 
21350         struct
21351         {
21352             __IOM uint32_t RDFS : 5;   /*!< [4..0] RDF Setting Condition Select                                       */
21353             uint32_t            : 3;
21354             __IOM uint32_t TDES : 5;   /*!< [12..8] TDE Setting Condition Select                                      */
21355             uint32_t            : 19;
21356         } SSISCR_b;
21357     };
21358 } R_SSI0_Type;                         /*!< Size = 40 (0x28)                                                          */
21359 
21360 /* =========================================================================================================================== */
21361 /* ================                                         R_SYSTEM                                          ================ */
21362 /* =========================================================================================================================== */
21363 
21364 /**
21365  * @brief System Pins (R_SYSTEM)
21366  */
21367 
21368 typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure                                         */
21369 {
21370     __IM uint32_t RESERVED[3];
21371 
21372     union
21373     {
21374         __IOM uint16_t SBYCR;          /*!< (@ 0x0000000C) Standby Control Register                                   */
21375 
21376         struct
21377         {
21378             uint16_t            : 14;
21379             __IOM uint16_t OPE  : 1;   /*!< [14..14] Output Port Enable                                               */
21380             __IOM uint16_t SSBY : 1;   /*!< [15..15] Software Standby                                                 */
21381         } SBYCR_b;
21382     };
21383     __IM uint16_t RESERVED1;
21384     __IM uint32_t RESERVED2[3];
21385 
21386     union
21387     {
21388         __IOM uint32_t MSTPCRA;         /*!< (@ 0x0000001C) Module Stop Control Register A                             */
21389 
21390         struct
21391         {
21392             __IOM uint32_t MSTPA0  : 1; /*!< [0..0] RAM0 Module Stop                                                   */
21393             __IOM uint32_t MSTPA1  : 1; /*!< [1..1] RAM1 Module Stop                                                   */
21394             uint32_t               : 3;
21395             __IOM uint32_t MSTPA5  : 1; /*!< [5..5] High-Speed RAM Module Stop                                         */
21396             __IOM uint32_t MSTPA6  : 1; /*!< [6..6] ECCRAM Module Stop                                                 */
21397             __IOM uint32_t MSTPA7  : 1; /*!< [7..7] Standby RAM Module Stop                                            */
21398             uint32_t               : 14;
21399             __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop              */
21400             uint32_t               : 9;
21401         } MSTPCRA_b;
21402     };
21403 
21404     union
21405     {
21406         __IOM uint32_t SCKDIVCR;       /*!< (@ 0x00000020) System Clock Division Control Register                     */
21407 
21408         struct
21409         {
21410             __IOM uint32_t PCKD : 3;   /*!< [2..0] Peripheral Module Clock D (PCLKD) Select                           */
21411             uint32_t            : 1;
21412             __IOM uint32_t PCKC : 3;   /*!< [6..4] Peripheral Module Clock C (PCLKC) Select                           */
21413             uint32_t            : 1;
21414             __IOM uint32_t PCKB : 3;   /*!< [10..8] Peripheral Module Clock B (PCLKB) Select                          */
21415             uint32_t            : 1;
21416             __IOM uint32_t PCKA : 3;   /*!< [14..12] Peripheral Module Clock A (PCLKA) Select                         */
21417             uint32_t            : 1;
21418             __IOM uint32_t BCK  : 3;   /*!< [18..16] External Bus Clock (BCLK) Select                                 */
21419             uint32_t            : 5;
21420             __IOM uint32_t ICK  : 3;   /*!< [26..24] System Clock (ICLK) Select                                       */
21421             uint32_t            : 1;
21422             __IOM uint32_t FCK  : 3;   /*!< [30..28] Flash IF Clock (FCLK) Select                                     */
21423             uint32_t            : 1;
21424         } SCKDIVCR_b;
21425     };
21426 
21427     union
21428     {
21429         __IOM uint8_t SCKDIVCR2;       /*!< (@ 0x00000024) System Clock Division Control Register 2                   */
21430 
21431         struct
21432         {
21433             uint8_t           : 4;
21434             __IOM uint8_t UCK : 3;     /*!< [6..4] USB Clock (UCLK) Select                                            */
21435             uint8_t           : 1;
21436         } SCKDIVCR2_b;
21437     };
21438     __IM uint8_t RESERVED3;
21439 
21440     union
21441     {
21442         __IOM uint8_t SCKSCR;          /*!< (@ 0x00000026) System Clock Source Control Register                       */
21443 
21444         struct
21445         {
21446             __IOM uint8_t CKSEL : 3;   /*!< [2..0] Clock Source Select                                                */
21447             uint8_t             : 5;
21448         } SCKSCR_b;
21449     };
21450     __IM uint8_t RESERVED4;
21451 
21452     union
21453     {
21454         __IOM uint16_t PLLCCR;           /*!< (@ 0x00000028) PLL Clock Control Register                                 */
21455 
21456         struct
21457         {
21458             __IOM uint16_t PLIDIV   : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select                          */
21459             uint16_t                : 2;
21460             __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select                                            */
21461             uint16_t                : 3;
21462             __IOM uint16_t PLLMUL   : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency
21463                                           *   Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 -
21464                                           *   0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0
21465                                           *   : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5
21466                                           *   111011: x30.0                                                             */
21467             uint16_t : 2;
21468         } PLLCCR_b;
21469     };
21470 
21471     union
21472     {
21473         __IOM uint8_t PLLCR;           /*!< (@ 0x0000002A) PLL Control Register                                       */
21474 
21475         struct
21476         {
21477             __IOM uint8_t PLLSTP : 1;  /*!< [0..0] PLL Stop Control                                                   */
21478             uint8_t              : 7;
21479         } PLLCR_b;
21480     };
21481 
21482     union
21483     {
21484         __IOM uint8_t PLLCCR2;         /*!< (@ 0x0000002B) PLL Clock Control Register2                                */
21485 
21486         struct
21487         {
21488             __IOM uint8_t PLLMUL : 5;  /*!< [4..0] PLL Frequency Multiplication Factor Select                         */
21489             uint8_t              : 1;
21490             __IOM uint8_t PLODIV : 2;  /*!< [7..6] PLL Output Frequency Division Ratio Select                         */
21491         } PLLCCR2_b;
21492     };
21493     __IM uint32_t RESERVED5;
21494 
21495     union
21496     {
21497         __IOM uint8_t BCKCR;           /*!< (@ 0x00000030) External Bus Clock Control Register                        */
21498 
21499         struct
21500         {
21501             __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select                                             */
21502             uint8_t               : 7;
21503         } BCKCR_b;
21504     };
21505 
21506     union
21507     {
21508         __IOM uint8_t MEMWAIT;         /*!< (@ 0x00000031) Memory Wait Cycle Control Register                         */
21509 
21510         struct
21511         {
21512             __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT
21513                                         *   is prohibited when SCKDIVCR.ICK selects division by 1 and
21514                                         *   SCKSCR.CKSEL[2:0] bits select thesystem clock source that
21515                                         *   is faster than 32 MHz (ICLK > 32 MHz).                                    */
21516             uint8_t : 7;
21517         } MEMWAIT_b;
21518     };
21519 
21520     union
21521     {
21522         __IOM uint8_t MOSCCR;          /*!< (@ 0x00000032) Main Clock Oscillator Control Register                     */
21523 
21524         struct
21525         {
21526             __IOM uint8_t MOSTP : 1;   /*!< [0..0] Main Clock Oscillator Stop                                         */
21527             uint8_t             : 7;
21528         } MOSCCR_b;
21529     };
21530     __IM uint8_t  RESERVED6;
21531     __IM uint16_t RESERVED7;
21532 
21533     union
21534     {
21535         __IOM uint8_t HOCOCR;          /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register             */
21536 
21537         struct
21538         {
21539             __IOM uint8_t HCSTP : 1;   /*!< [0..0] HOCO Stop                                                          */
21540             uint8_t             : 7;
21541         } HOCOCR_b;
21542     };
21543     __IM uint8_t RESERVED8;
21544 
21545     union
21546     {
21547         __IOM uint8_t MOCOCR;          /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register           */
21548 
21549         struct
21550         {
21551             __IOM uint8_t MCSTP : 1;   /*!< [0..0] MOCO Stop                                                          */
21552             uint8_t             : 7;
21553         } MOCOCR_b;
21554     };
21555 
21556     union
21557     {
21558         __IOM uint8_t FLLCR1;          /*!< (@ 0x00000039) FLL Control Register 1                                     */
21559 
21560         struct
21561         {
21562             __IOM uint8_t FLLEN : 1;   /*!< [0..0] FLL Enable                                                         */
21563             uint8_t             : 7;
21564         } FLLCR1_b;
21565     };
21566 
21567     union
21568     {
21569         __IOM uint16_t FLLCR2;           /*!< (@ 0x0000003A) FLL Control Register 2                                     */
21570 
21571         struct
21572         {
21573             __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the
21574                                           *   FLL reference clock select                                                */
21575             uint16_t : 5;
21576         } FLLCR2_b;
21577     };
21578 
21579     union
21580     {
21581         __IM uint8_t OSCSF;            /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register                    */
21582 
21583         struct
21584         {
21585             __IM uint8_t HOCOSF : 1;   /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF
21586                                         *   bit value after a reset is 1 when the OFS1.HOCOEN bit is
21587                                         *   0. It is 0 when the OFS1.HOCOEN bit is 1.                                 */
21588             uint8_t             : 2;
21589             __IM uint8_t MOSCSF : 1;   /*!< [3..3] Main Clock Oscillation Stabilization Flag                          */
21590             uint8_t             : 1;
21591             __IM uint8_t PLLSF  : 1;   /*!< [5..5] PLL Clock Oscillation Stabilization Flag                           */
21592             __IM uint8_t PLL2SF : 1;   /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag                          */
21593             uint8_t             : 1;
21594         } OSCSF_b;
21595     };
21596     __IM uint8_t RESERVED9;
21597 
21598     union
21599     {
21600         __IOM uint8_t CKOCR;           /*!< (@ 0x0000003E) Clock Out Control Register                                 */
21601 
21602         struct
21603         {
21604             __IOM uint8_t CKOSEL : 3;  /*!< [2..0] Clock out source select                                            */
21605             uint8_t              : 1;
21606             __IOM uint8_t CKODIV : 3;  /*!< [6..4] Clock out input frequency Division Select                          */
21607             __IOM uint8_t CKOEN  : 1;  /*!< [7..7] Clock out enable                                                   */
21608         } CKOCR_b;
21609     };
21610 
21611     union
21612     {
21613         __IOM uint8_t TRCKCR;          /*!< (@ 0x0000003F) Trace Clock Control Register                               */
21614 
21615         struct
21616         {
21617             __IOM uint8_t TRCK   : 4;  /*!< [3..0] Trace Clock operating frequency select                             */
21618             uint8_t              : 3;
21619             __IOM uint8_t TRCKEN : 1;  /*!< [7..7] Trace Clock operating Enable                                       */
21620         } TRCKCR_b;
21621     };
21622 
21623     union
21624     {
21625         __IOM uint8_t OSTDCR;          /*!< (@ 0x00000040) Oscillation Stop Detection Control Register                */
21626 
21627         struct
21628         {
21629             __IOM uint8_t OSTDIE : 1;  /*!< [0..0] Oscillation Stop Detection Interrupt Enable                        */
21630             uint8_t              : 6;
21631             __IOM uint8_t OSTDE  : 1;  /*!< [7..7] Oscillation Stop Detection Function Enable                         */
21632         } OSTDCR_b;
21633     };
21634 
21635     union
21636     {
21637         __IOM uint8_t OSTDSR;          /*!< (@ 0x00000041) Oscillation Stop Detection Status Register                 */
21638 
21639         struct
21640         {
21641             __IOM uint8_t OSTDF : 1;   /*!< [0..0] Oscillation Stop Detection Flag                                    */
21642             uint8_t             : 7;
21643         } OSTDSR_b;
21644     };
21645     __IM uint16_t RESERVED10;
21646     __IM uint32_t RESERVED11;
21647 
21648     union
21649     {
21650         __IOM uint16_t PLL2CCR;           /*!< (@ 0x00000048) PLL2 Clock Control Register                                */
21651 
21652         struct
21653         {
21654             __IOM uint16_t PL2IDIV   : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select                         */
21655             uint16_t                 : 2;
21656             __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select                                           */
21657             uint16_t                 : 3;
21658             __IOM uint16_t PLL2MUL   : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select                       */
21659             uint16_t                 : 2;
21660         } PLL2CCR_b;
21661     };
21662 
21663     union
21664     {
21665         __IOM uint8_t PLL2CR;          /*!< (@ 0x0000004A) PLL2 Control Register                                      */
21666 
21667         struct
21668         {
21669             __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control                                                  */
21670             uint8_t               : 7;
21671         } PLL2CR_b;
21672     };
21673     __IM uint8_t RESERVED12;
21674 
21675     union
21676     {
21677         __IOM uint8_t LPOPT;             /*!< (@ 0x0000004C) Lower Power Operation Control Register                     */
21678 
21679         struct
21680         {
21681             __IOM uint8_t MPUDIS : 1;    /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock
21682                                           *   (valid only when LPOPTEN = 1)                                             */
21683             __IOM uint8_t DCLKDIS   : 2; /*!< [2..1] Debug Clock Disable Control                                        */
21684             __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W
21685                                           *   clock (valid only when LPOPT.LPOPTEN = 1)                                 */
21686             uint8_t               : 3;
21687             __IOM uint8_t LPOPTEN : 1;   /*!< [7..7] Lower Power Operation Enable                                       */
21688         } LPOPT_b;
21689     };
21690     __IM uint8_t  RESERVED13;
21691     __IM uint16_t RESERVED14;
21692 
21693     union
21694     {
21695         __IOM uint8_t SLCDSCKCR;         /*!< (@ 0x00000050) Segment LCD Source Clock Control Register                  */
21696 
21697         struct
21698         {
21699             __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select                                */
21700             uint8_t                 : 4;
21701             __IOM uint8_t LCDSCKEN  : 1; /*!< [7..7] LCD Source Clock Out Enable                                        */
21702         } SLCDSCKCR_b;
21703     };
21704     __IM uint8_t RESERVED15;
21705 
21706     union
21707     {
21708         __IOM uint8_t EBCKOCR;         /*!< (@ 0x00000052) External Bus Clock Output Control Register                 */
21709 
21710         struct
21711         {
21712             __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control                                            */
21713             uint8_t               : 7;
21714         } EBCKOCR_b;
21715     };
21716 
21717     union
21718     {
21719         __IOM uint8_t SDCKOCR;         /*!< (@ 0x00000053) SDRAM Clock Output Control Register                        */
21720 
21721         struct
21722         {
21723             __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control                                           */
21724             uint8_t               : 7;
21725         } SDCKOCR_b;
21726     };
21727     __IM uint32_t RESERVED16[3];
21728     __IM uint8_t  RESERVED17;
21729 
21730     union
21731     {
21732         __IOM uint8_t MOCOUTCR;         /*!< (@ 0x00000061) MOCO User Trimming Control Register                        */
21733 
21734         struct
21735         {
21736             __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127
21737                                          *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
21738                                          *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
21739                                          +126 0111_1111 : +127These bits are added to original MOCO
21740                                          *   trimming bits                                                             */
21741         } MOCOUTCR_b;
21742     };
21743 
21744     union
21745     {
21746         __IOM uint8_t HOCOUTCR;         /*!< (@ 0x00000062) HOCO User Trimming Control Register                        */
21747 
21748         struct
21749         {
21750             __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127
21751                                          *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
21752                                          *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
21753                                          +126 0111_1111 : +127These bits are added to original HOCO
21754                                          *   trimming bits                                                             */
21755         } HOCOUTCR_b;
21756     };
21757     __IM uint8_t  RESERVED18;
21758     __IM uint32_t RESERVED19[2];
21759 
21760     union
21761     {
21762         __IOM uint8_t USBCKDIVCR;       /*!< (@ 0x0000006C) USB Clock Division Control Register                        */
21763 
21764         struct
21765         {
21766             __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select                                 */
21767             uint8_t                : 5;
21768         } USBCKDIVCR_b;
21769     };
21770 
21771     union
21772     {
21773         union
21774         {
21775             __IOM uint8_t OCTACKDIVCR;       /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register                  */
21776 
21777             struct
21778             {
21779                 __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select                          */
21780                 uint8_t                 : 5;
21781             } OCTACKDIVCR_b;
21782         };
21783 
21784         union
21785         {
21786             __IOM uint8_t SCISPICKDIVCR;       /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register                    */
21787 
21788             struct
21789             {
21790                 __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select                          */
21791                 uint8_t                   : 5;
21792             } SCISPICKDIVCR_b;
21793         };
21794     };
21795 
21796     union
21797     {
21798         __IOM uint8_t CANFDCKDIVCR;       /*!< (@ 0x0000006E) CANFD Clock Division Control Register                      */
21799 
21800         struct
21801         {
21802             __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select                             */
21803             uint8_t                  : 5;
21804         } CANFDCKDIVCR_b;
21805     };
21806 
21807     union
21808     {
21809         __IOM uint8_t GPTCKDIVCR;       /*!< (@ 0x0000006F) GPT Clock Division Control Register                        */
21810 
21811         struct
21812         {
21813             __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select                                 */
21814             uint8_t                : 5;
21815         } GPTCKDIVCR_b;
21816     };
21817 
21818     union
21819     {
21820         __IOM uint8_t IICCKDIVCR;       /*!< (@ 0x00000070) IIC Clock Division Control Register                        */
21821 
21822         struct
21823         {
21824             __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select                                 */
21825             uint8_t                : 5;
21826         } IICCKDIVCR_b;
21827     };
21828     __IM uint8_t  RESERVED20;
21829     __IM uint16_t RESERVED21;
21830 
21831     union
21832     {
21833         __IOM uint8_t USBCKCR;           /*!< (@ 0x00000074) USB Clock Control Register                                 */
21834 
21835         struct
21836         {
21837             __IOM uint8_t USBCKSEL  : 3; /*!< [2..0] USB Clock (USBCLK) Source Select                                   */
21838             uint8_t                 : 3;
21839             __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request                               */
21840             __IM uint8_t  USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag                      */
21841         } USBCKCR_b;
21842     };
21843 
21844     union
21845     {
21846         union
21847         {
21848             __IOM uint8_t OCTACKCR;           /*!< (@ 0x00000075) Octal-SPI Clock Control Register                           */
21849 
21850             struct
21851             {
21852                 __IOM uint8_t OCTACKSEL  : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select                            */
21853                 uint8_t                  : 3;
21854                 __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request                        */
21855                 __IM uint8_t  OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag               */
21856             } OCTACKCR_b;
21857         };
21858 
21859         union
21860         {
21861             __IOM uint8_t SCISPICKCR;           /*!< (@ 0x00000075) SCI SPI Clock Control Register                             */
21862 
21863             struct
21864             {
21865                 __IOM uint8_t SCISPICKSEL  : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select                            */
21866                 uint8_t                    : 3;
21867                 __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request                        */
21868                 __IM uint8_t  SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag               */
21869             } SCISPICKCR_b;
21870         };
21871     };
21872 
21873     union
21874     {
21875         __IOM uint8_t CANFDCKCR;           /*!< (@ 0x00000076) CANFD Clock Control Register                               */
21876 
21877         struct
21878         {
21879             __IOM uint8_t CANFDCKSEL  : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select                               */
21880             uint8_t                   : 3;
21881             __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request                           */
21882             __IM uint8_t  CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag                  */
21883         } CANFDCKCR_b;
21884     };
21885 
21886     union
21887     {
21888         __IOM uint8_t GPTCKCR;           /*!< (@ 0x00000077) GPT Clock Control Register                                 */
21889 
21890         struct
21891         {
21892             __IOM uint8_t GPTCKSEL  : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select                                   */
21893             uint8_t                 : 3;
21894             __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request                               */
21895             __IM uint8_t  GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag                      */
21896         } GPTCKCR_b;
21897     };
21898 
21899     union
21900     {
21901         __IOM uint8_t IICCKCR;           /*!< (@ 0x00000078) IIC Clock Control Register                                 */
21902 
21903         struct
21904         {
21905             __IOM uint8_t IICCKSEL  : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select                                   */
21906             uint8_t                 : 3;
21907             __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request                               */
21908             __IM uint8_t  IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag                      */
21909         } IICCKCR_b;
21910     };
21911     __IM uint8_t  RESERVED22;
21912     __IM uint16_t RESERVED23;
21913     __IM uint32_t RESERVED24[3];
21914 
21915     union
21916     {
21917         __IOM uint32_t SNZREQCR1;         /*!< (@ 0x00000088) Snooze Request Control Register 1                          */
21918 
21919         struct
21920         {
21921             __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request                               */
21922             __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request                               */
21923             __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request                               */
21924             uint32_t                 : 29;
21925         } SNZREQCR1_b;
21926     };
21927     __IM uint32_t RESERVED25;
21928     __IM uint16_t RESERVED26;
21929 
21930     union
21931     {
21932         __IOM uint8_t SNZCR;            /*!< (@ 0x00000092) Snooze Control Register                                    */
21933 
21934         struct
21935         {
21936             __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other
21937                                          *   than in asynchronous mode.                                                */
21938             __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode                                          */
21939             uint8_t                : 5;
21940             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
21941         } SNZCR_b;
21942     };
21943     __IM uint8_t RESERVED27;
21944 
21945     union
21946     {
21947         __IOM uint8_t SNZEDCR;           /*!< (@ 0x00000094) Snooze End Control Register                                */
21948 
21949         struct
21950         {
21951             __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable                                   */
21952             __IOM uint8_t DTCZRED   : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable                 */
21953             __IOM uint8_t DTCNZRED  : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable             */
21954             __IOM uint8_t AD0MATED  : 1; /*!< [3..3] AD compare match 0 Snooze End Enable                               */
21955             __IOM uint8_t AD0UMTED  : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable                            */
21956             __IOM uint8_t AD1MATED  : 1; /*!< [5..5] AD compare match 1 Snooze End Enable                               */
21957             __IOM uint8_t AD1UMTED  : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable                            */
21958             __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set
21959                                           *   to 1 other than in asynchronous mode.                                     */
21960         } SNZEDCR_b;
21961     };
21962 
21963     union
21964     {
21965         __IOM uint8_t SNZEDCR1;          /*!< (@ 0x00000095) Snooze End Control Register 1                              */
21966 
21967         struct
21968         {
21969             __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable                                   */
21970             uint8_t                 : 7;
21971         } SNZEDCR1_b;
21972     };
21973     __IM uint16_t RESERVED28;
21974 
21975     union
21976     {
21977         __IOM uint32_t SNZREQCR;           /*!< (@ 0x00000098) Snooze Request Control Register                            */
21978 
21979         struct
21980         {
21981             __IOM uint32_t SNZREQEN0  : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request             */
21982             __IOM uint32_t SNZREQEN1  : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request             */
21983             __IOM uint32_t SNZREQEN2  : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request             */
21984             __IOM uint32_t SNZREQEN3  : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request             */
21985             __IOM uint32_t SNZREQEN4  : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request             */
21986             __IOM uint32_t SNZREQEN5  : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request             */
21987             __IOM uint32_t SNZREQEN6  : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request             */
21988             __IOM uint32_t SNZREQEN7  : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request             */
21989             __IOM uint32_t SNZREQEN8  : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request             */
21990             __IOM uint32_t SNZREQEN9  : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request             */
21991             __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request          */
21992             __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request          */
21993             __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request          */
21994             __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request          */
21995             __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request          */
21996             __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request          */
21997             uint32_t                  : 1;
21998             __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request                 */
21999             uint32_t                  : 4;
22000             __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze
22001                                             *   request                                                                   */
22002             __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze
22003                                             *   request                                                                   */
22004             __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request          */
22005             __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request         */
22006             uint32_t                  : 2;
22007             __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze
22008                                             *   request                                                                   */
22009             __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A
22010                                             *   snooze request                                                            */
22011             __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B
22012                                             *   snooze request                                                            */
22013             uint32_t : 1;
22014         } SNZREQCR_b;
22015     };
22016     __IM uint16_t RESERVED29;
22017 
22018     union
22019     {
22020         __IOM uint8_t FLSTOP;          /*!< (@ 0x0000009E) Flash Operation Control Register                           */
22021 
22022         struct
22023         {
22024             __IOM uint8_t FLSTOP : 1;  /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation                     */
22025             uint8_t              : 3;
22026             __IOM uint8_t FLSTPF : 1;  /*!< [4..4] Flash Memory Operation Status Flag                                 */
22027             uint8_t              : 3;
22028         } FLSTOP_b;
22029     };
22030 
22031     union
22032     {
22033         __IOM uint8_t PSMCR;           /*!< (@ 0x0000009F) Power Save Memory Control Register                         */
22034 
22035         struct
22036         {
22037             __IOM uint8_t PSMC : 2;    /*!< [1..0] Power save memory control.                                         */
22038             uint8_t            : 6;
22039         } PSMCR_b;
22040     };
22041 
22042     union
22043     {
22044         __IOM uint8_t OPCCR;           /*!< (@ 0x000000A0) Operating Power Control Register                           */
22045 
22046         struct
22047         {
22048             __IOM uint8_t OPCM   : 2;  /*!< [1..0] Operating Power Control Mode Select                                */
22049             uint8_t              : 2;
22050             __IM uint8_t OPCMTSF : 1;  /*!< [4..4] Operating Power Control Mode Transition Status Flag                */
22051             uint8_t              : 3;
22052         } OPCCR_b;
22053     };
22054     __IM uint8_t RESERVED30;
22055 
22056     union
22057     {
22058         __IOM uint8_t MOSCWTCR;        /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register                */
22059 
22060         struct
22061         {
22062             __IOM uint8_t MSTS : 4;    /*!< [3..0] Main clock oscillator wait time setting                            */
22063             uint8_t            : 4;
22064         } MOSCWTCR_b;
22065     };
22066     __IM uint8_t RESERVED31[2];
22067 
22068     union
22069     {
22070         __IOM uint8_t HOCOWTCR;        /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register        */
22071 
22072         struct
22073         {
22074             __IOM uint8_t HSTS : 3;    /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of
22075                                         *   the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed)                     */
22076             uint8_t : 5;
22077         } HOCOWTCR_b;
22078     };
22079     __IM uint16_t RESERVED32[2];
22080 
22081     union
22082     {
22083         __IOM uint8_t SOPCCR;          /*!< (@ 0x000000AA) Sub Operating Power Control Register                       */
22084 
22085         struct
22086         {
22087             __IOM uint8_t SOPCM   : 1; /*!< [0..0] Sub Operating Power Control Mode Select                            */
22088             uint8_t               : 3;
22089             __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag            */
22090             uint8_t               : 3;
22091         } SOPCCR_b;
22092     };
22093     __IM uint8_t  RESERVED33;
22094     __IM uint32_t RESERVED34[5];
22095 
22096     union
22097     {
22098         __IOM uint16_t RSTSR1;         /*!< (@ 0x000000C0) Reset Status Register 1                                    */
22099 
22100         struct
22101         {
22102             __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable
22103                                         *   only to clear the flag. Confirm the value is 1 and then
22104                                         *   write 0.                                                                  */
22105             __IOM uint16_t WDTRF : 1;  /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to
22106                                         *   clear the flag. Confirm the value is 1 and then write 0.                  */
22107             __IOM uint16_t SWRF : 1;   /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear
22108                                         *   the flag. Confirm the value is 1 and then write 0.                        */
22109             uint16_t             : 5;
22110             __IOM uint16_t RPERF : 1;  /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only
22111                                         *   to clear the flag. Confirm the value is 1 and then write
22112                                         *   0.                                                                        */
22113             __IOM uint16_t REERF : 1;  /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to
22114                                         *   clear the flag. Confirm the value is 1 and then write 0.                  */
22115             __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only
22116                                         *   to clear the flag. Confirm the value is 1 and then write
22117                                         *   0.                                                                        */
22118             __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only
22119                                         *   to clear the flag. Confirm the value is 1 and then write
22120                                         *   0.                                                                        */
22121             __IOM uint16_t SPERF : 1;  /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear
22122                                         *   the flag. Confirm the value is 1 and then write 0.                        */
22123             __IOM uint16_t TZERF : 1;  /*!< [13..13] Trust Zone Error Reset Detect Flag                               */
22124             uint16_t             : 1;
22125             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
22126         } RSTSR1_b;
22127     };
22128     __IM uint16_t RESERVED35;
22129     __IM uint32_t RESERVED36[3];
22130 
22131     union
22132     {
22133         __IOM uint8_t USBCKCR_ALT;       /*!< (@ 0x000000D0) USB Clock Control Register                                 */
22134 
22135         struct
22136         {
22137             __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock
22138                                           *   (UCLK).                                                                   */
22139             uint8_t : 7;
22140         } USBCKCR_ALT_b;
22141     };
22142 
22143     union
22144     {
22145         __IOM uint8_t SDADCCKCR;          /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control
22146                                            *                  Register                                                   */
22147 
22148         struct
22149         {
22150             __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select                      */
22151             uint8_t                  : 6;
22152             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
22153         } SDADCCKCR_b;
22154     };
22155     __IM uint16_t RESERVED37;
22156     __IM uint32_t RESERVED38[3];
22157 
22158     union
22159     {
22160         __IOM uint8_t LVD1CR1;         /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1               */
22161 
22162         struct
22163         {
22164             __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
22165             __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
22166             uint8_t              : 5;
22167         } LVD1CR1_b;
22168     };
22169 
22170     union
22171     {
22172         __IOM uint8_t LVD1SR;          /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register                  */
22173 
22174         struct
22175         {
22176             __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
22177                                         *   0 can be written to this bit. After writing 0 to this bit,
22178                                         *   it takes 2 system clock cycles for the bit to be read as
22179                                         *   0.                                                                        */
22180             __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag                              */
22181             uint8_t          : 6;
22182         } LVD1SR_b;
22183     };
22184 
22185     union
22186     {
22187         __IOM uint8_t LVD2CR1;         /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1               */
22188 
22189         struct
22190         {
22191             __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
22192             __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
22193             uint8_t              : 5;
22194         } LVD2CR1_b;
22195     };
22196 
22197     union
22198     {
22199         __IOM uint8_t LVD2SR;          /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register                  */
22200 
22201         struct
22202         {
22203             __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
22204                                         *   0 can be written to this bit. After writing 0 to this bit,
22205                                         *   it takes 2 system clock cycles for the bit to be read as
22206                                         *   0.                                                                        */
22207             __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag                              */
22208             uint8_t          : 6;
22209         } LVD2SR_b;
22210     };
22211     __IM uint32_t RESERVED39[183];
22212 
22213     union
22214     {
22215         __IOM uint32_t CGFSAR;           /*!< (@ 0x000003C0) Clock Generation Function Security Attribute
22216                                           *                  Register                                                   */
22217 
22218         struct
22219         {
22220             __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00                                        */
22221             uint32_t                : 1;
22222             __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02                                        */
22223             __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03                                        */
22224             __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04                                        */
22225             __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05                                        */
22226             __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06                                        */
22227             __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07                                        */
22228             __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08                                        */
22229             __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09                                        */
22230             uint32_t                : 1;
22231             __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11                                      */
22232             __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12                                      */
22233             uint32_t                : 3;
22234             __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16                                      */
22235             __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17                                      */
22236             uint32_t                : 14;
22237         } CGFSAR_b;
22238     };
22239     __IM uint32_t RESERVED40;
22240 
22241     union
22242     {
22243         __IOM uint32_t LPMSAR;          /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register               */
22244 
22245         struct
22246         {
22247             __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
22248             uint32_t               : 1;
22249             __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
22250             uint32_t               : 1;
22251             __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4                                         */
22252             uint32_t               : 3;
22253             __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8                                         */
22254             __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9                                         */
22255             uint32_t               : 22;
22256         } LPMSAR_b;
22257     };
22258 
22259     union
22260     {
22261         union
22262         {
22263             __IOM uint32_t LVDSAR;          /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register        */
22264 
22265             struct
22266             {
22267                 __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
22268                 __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
22269                 uint32_t               : 30;
22270             } LVDSAR_b;
22271         };
22272 
22273         union
22274         {
22275             __IOM uint32_t RSTSAR;          /*!< (@ 0x000003CC) Reset Security Attribution Register                        */
22276 
22277             struct
22278             {
22279                 __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
22280                 __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
22281                 __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
22282                 uint32_t               : 29;
22283             } RSTSAR_b;
22284         };
22285     };
22286 
22287     union
22288     {
22289         __IOM uint32_t BBFSAR;           /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register        */
22290 
22291         struct
22292         {
22293             __IOM uint32_t NONSEC0  : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
22294             __IOM uint32_t NONSEC1  : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
22295             __IOM uint32_t NONSEC2  : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
22296             uint32_t                : 13;
22297             __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16                                      */
22298             __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17                                      */
22299             __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18                                      */
22300             __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19                                      */
22301             __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20                                      */
22302             __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21                                      */
22303             __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22                                      */
22304             __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23                                      */
22305             uint32_t                : 8;
22306         } BBFSAR_b;
22307     };
22308     __IM uint32_t RESERVED41[3];
22309 
22310     union
22311     {
22312         __IOM uint32_t DPFSAR;          /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution
22313                                          *                  Register                                                   */
22314 
22315         struct
22316         {
22317             __IOM uint32_t DPFSA0 : 1;  /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit
22318                                          *   0                                                                         */
22319             __IOM uint32_t DPFSA1 : 1;  /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit
22320                                          *   1                                                                         */
22321             __IOM uint32_t DPFSA2 : 1;  /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit
22322                                          *   2                                                                         */
22323             __IOM uint32_t DPFSA3 : 1;  /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit
22324                                          *   3                                                                         */
22325             __IOM uint32_t DPFSA4 : 1;  /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit
22326                                          *   4                                                                         */
22327             __IOM uint32_t DPFSA5 : 1;  /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit
22328                                          *   5                                                                         */
22329             __IOM uint32_t DPFSA6 : 1;  /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit
22330                                          *   6                                                                         */
22331             __IOM uint32_t DPFSA7 : 1;  /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit
22332                                          *   7                                                                         */
22333             __IOM uint32_t DPFSA8 : 1;  /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit
22334                                          *   8                                                                         */
22335             __IOM uint32_t DPFSA9 : 1;  /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit
22336                                          *   9                                                                         */
22337             __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit
22338                                          *   10                                                                        */
22339             __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit
22340                                          *   11                                                                        */
22341             __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit
22342                                          *   12                                                                        */
22343             __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit
22344                                          *   13                                                                        */
22345             __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit
22346                                          *   14                                                                        */
22347             __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit
22348                                          *   15                                                                        */
22349             __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit
22350                                          *   16                                                                        */
22351             __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit
22352                                          *   17                                                                        */
22353             __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit
22354                                          *   18                                                                        */
22355             __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit
22356                                          *   19                                                                        */
22357             __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit
22358                                          *   20                                                                        */
22359             uint32_t               : 3;
22360             __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit
22361                                          *   24                                                                        */
22362             uint32_t               : 1;
22363             __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit
22364                                          *   26                                                                        */
22365             __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit
22366                                          *   27                                                                        */
22367             uint32_t : 4;
22368         } DPFSAR_b;
22369     };
22370     __IM uint32_t RESERVED42[6];
22371     __IM uint16_t RESERVED43;
22372 
22373     union
22374     {
22375         __IOM uint16_t PRCR;           /*!< (@ 0x000003FE) Protect Register                                           */
22376 
22377         struct
22378         {
22379             __IOM uint16_t PRC0 : 1;   /*!< [0..0] Enables writing to the registers related to the clock
22380                                         *   generation circuit.                                                       */
22381             __IOM uint16_t PRC1 : 1;   /*!< [1..1] Enables writing to the registers related to the operating
22382                                         *   modes, the low power consumption modes and the battery
22383                                         *   backup function.                                                          */
22384             uint16_t            : 1;
22385             __IOM uint16_t PRC3 : 1;   /*!< [3..3] Enables writing to the registers related to the LVD.               */
22386             __IOM uint16_t PRC4 : 1;   /*!< [4..4] PRC4                                                               */
22387             uint16_t            : 3;
22388             __OM uint16_t PRKEY : 8;   /*!< [15..8] PRKEY Key Code                                                    */
22389         } PRCR_b;
22390     };
22391 
22392     union
22393     {
22394         __IOM uint8_t DPSBYCR;         /*!< (@ 0x00000400) Deep Standby Control Register                              */
22395 
22396         struct
22397         {
22398             __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control                                               */
22399             uint8_t               : 4;
22400             __IOM uint8_t IOKEEP  : 1; /*!< [6..6] I/O Port Retention                                                 */
22401             __IOM uint8_t DPSBY   : 1; /*!< [7..7] Deep Software Standby                                              */
22402         } DPSBYCR_b;
22403     };
22404 
22405     union
22406     {
22407         __IOM uint8_t DPSWCR;          /*!< (@ 0x00000401) Deep Standby Wait Control Register                         */
22408 
22409         struct
22410         {
22411             __IOM uint8_t WTSTS : 6;   /*!< [5..0] Deep Software Wait Standby Time Setting Bit                        */
22412             uint8_t             : 2;
22413         } DPSWCR_b;
22414     };
22415 
22416     union
22417     {
22418         __IOM uint8_t DPSIER0;         /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0                   */
22419 
22420         struct
22421         {
22422             __IOM uint8_t DIRQ0E : 1;  /*!< [0..0] IRQ-DS Pin Enable                                                  */
22423             __IOM uint8_t DIRQ1E : 1;  /*!< [1..1] IRQ-DS Pin Enable                                                  */
22424             __IOM uint8_t DIRQ2E : 1;  /*!< [2..2] IRQ-DS Pin Enable                                                  */
22425             __IOM uint8_t DIRQ3E : 1;  /*!< [3..3] IRQ-DS Pin Enable                                                  */
22426             __IOM uint8_t DIRQ4E : 1;  /*!< [4..4] IRQ-DS Pin Enable                                                  */
22427             __IOM uint8_t DIRQ5E : 1;  /*!< [5..5] IRQ-DS Pin Enable                                                  */
22428             __IOM uint8_t DIRQ6E : 1;  /*!< [6..6] IRQ-DS Pin Enable                                                  */
22429             __IOM uint8_t DIRQ7E : 1;  /*!< [7..7] IRQ-DS Pin Enable                                                  */
22430         } DPSIER0_b;
22431     };
22432 
22433     union
22434     {
22435         __IOM uint8_t DPSIER1;         /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1                   */
22436 
22437         struct
22438         {
22439             __IOM uint8_t DIRQ8E  : 1; /*!< [0..0] IRQ-DS Pin Enable                                                  */
22440             __IOM uint8_t DIRQ9E  : 1; /*!< [1..1] IRQ-DS Pin Enable                                                  */
22441             __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable                                                  */
22442             __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable                                                  */
22443             __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable                                                  */
22444             __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable                                                  */
22445             __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable                                                  */
22446             __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable                                                  */
22447         } DPSIER1_b;
22448     };
22449 
22450     union
22451     {
22452         __IOM uint8_t DPSIER2;          /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2                   */
22453 
22454         struct
22455         {
22456             __IOM uint8_t DLVD1IE  : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable                             */
22457             __IOM uint8_t DLVD2IE  : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable                             */
22458             __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable           */
22459             __IOM uint8_t DRTCAIE  : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable              */
22460             __IOM uint8_t DNMIE    : 1; /*!< [4..4] NMI Pin Enable                                                     */
22461             uint8_t                : 3;
22462         } DPSIER2_b;
22463     };
22464 
22465     union
22466     {
22467         __IOM uint8_t DPSIER3;          /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3                   */
22468 
22469         struct
22470         {
22471             __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable             */
22472             __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable             */
22473             __IOM uint8_t DAGT1IE  : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable                   */
22474             __IOM uint8_t DAGT3IE  : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable                   */
22475             uint8_t                : 4;
22476         } DPSIER3_b;
22477     };
22478 
22479     union
22480     {
22481         __IOM uint8_t DPSIFR0;         /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0                     */
22482 
22483         struct
22484         {
22485             __IOM uint8_t DIRQ0F : 1;  /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag                                */
22486             __IOM uint8_t DIRQ1F : 1;  /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag                                */
22487             __IOM uint8_t DIRQ2F : 1;  /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag                                */
22488             __IOM uint8_t DIRQ3F : 1;  /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag                                */
22489             __IOM uint8_t DIRQ4F : 1;  /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag                                */
22490             __IOM uint8_t DIRQ5F : 1;  /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag                                */
22491             __IOM uint8_t DIRQ6F : 1;  /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag                                */
22492             __IOM uint8_t DIRQ7F : 1;  /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag                                */
22493         } DPSIFR0_b;
22494     };
22495 
22496     union
22497     {
22498         __IOM uint8_t DPSIFR1;         /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1                     */
22499 
22500         struct
22501         {
22502             __IOM uint8_t DIRQ8F  : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag                                */
22503             __IOM uint8_t DIRQ9F  : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag                                */
22504             __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag                                */
22505             __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag                                */
22506             __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag                                */
22507             __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag                                */
22508             __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag                                */
22509             __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag                                */
22510         } DPSIFR1_b;
22511     };
22512 
22513     union
22514     {
22515         __IOM uint8_t DPSIFR2;          /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2                     */
22516 
22517         struct
22518         {
22519             __IOM uint8_t DLVD1IF  : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag                                      */
22520             __IOM uint8_t DLVD2IF  : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag                                      */
22521             __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag                    */
22522             __IOM uint8_t DRTCAIF  : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag                       */
22523             __IOM uint8_t DNMIF    : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag                                   */
22524             uint8_t                : 3;
22525         } DPSIFR2_b;
22526     };
22527 
22528     union
22529     {
22530         __IOM uint8_t DPSIFR3;          /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3                     */
22531 
22532         struct
22533         {
22534             __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag                      */
22535             __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag                      */
22536             __IOM uint8_t DAGT1IF  : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag                            */
22537             __IOM uint8_t DAGT3IF  : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag                            */
22538             uint8_t                : 4;
22539         } DPSIFR3_b;
22540     };
22541 
22542     union
22543     {
22544         __IOM uint8_t DPSIEGR0;        /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0                     */
22545 
22546         struct
22547         {
22548             __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select                                             */
22549             __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select                                             */
22550             __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select                                             */
22551             __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select                                             */
22552             __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select                                             */
22553             __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select                                             */
22554             __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select                                             */
22555             __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select                                             */
22556         } DPSIEGR0_b;
22557     };
22558 
22559     union
22560     {
22561         __IOM uint8_t DPSIEGR1;        /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1                     */
22562 
22563         struct
22564         {
22565             __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select                                             */
22566             __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select                                             */
22567             __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select                                             */
22568             __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select                                             */
22569             __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select                                             */
22570             __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select                                             */
22571             __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select                                             */
22572             __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select                                             */
22573         } DPSIEGR1_b;
22574     };
22575 
22576     union
22577     {
22578         __IOM uint8_t DPSIEGR2;         /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2                     */
22579 
22580         struct
22581         {
22582             __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select                                                   */
22583             __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select                                                   */
22584             uint8_t                : 2;
22585             __IOM uint8_t DNMIEG   : 1; /*!< [4..4] NMI Pin Edge Select                                                */
22586             uint8_t                : 3;
22587         } DPSIEGR2_b;
22588     };
22589     __IM uint8_t RESERVED44;
22590 
22591     union
22592     {
22593         __IOM uint8_t SYOCDCR;         /*!< (@ 0x0000040E) System Control OCD Control Register                        */
22594 
22595         struct
22596         {
22597             __IOM uint8_t DOCDF : 1;   /*!< [0..0] Deep Standby OCD flag                                              */
22598             uint8_t             : 6;
22599             __IOM uint8_t DBGEN : 1;   /*!< [7..7] Debugger Enable bit                                                */
22600         } SYOCDCR_b;
22601     };
22602 
22603     union
22604     {
22605         __IOM uint8_t STCONR;          /*!< (@ 0x0000040F) Standby Condition Register                                 */
22606 
22607         struct
22608         {
22609             __IOM uint8_t STCON : 2;   /*!< [1..0] SSTBY condition bit                                                */
22610             uint8_t             : 6;
22611         } STCONR_b;
22612     };
22613 
22614     union
22615     {
22616         __IOM uint8_t RSTSR0;          /*!< (@ 0x00000410) Reset Status Register 0                                    */
22617 
22618         struct
22619         {
22620             __IOM uint8_t PORF : 1;    /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear
22621                                         *   the flag. Confirm the value is 1 and then write 0.                        */
22622             __IOM uint8_t LVD0RF : 1;  /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only
22623                                         *   to clear the flag. Confirm the value is 1 and then write
22624                                         *   0.                                                                        */
22625             __IOM uint8_t LVD1RF : 1;  /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only
22626                                         *   to clear the flag. Confirm the value is 1 and then write
22627                                         *   0.                                                                        */
22628             __IOM uint8_t LVD2RF : 1;  /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only
22629                                         *   to clear the flag. Confirm the value is 1 and then write
22630                                         *   0.                                                                        */
22631             uint8_t               : 3;
22632             __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to
22633                                         *   clear the flag. Confirm the value is 1 and then write 0.                  */
22634         } RSTSR0_b;
22635     };
22636 
22637     union
22638     {
22639         __IOM uint8_t RSTSR2;          /*!< (@ 0x00000411) Reset Status Register 2                                    */
22640 
22641         struct
22642         {
22643             __IOM uint8_t CWSF : 1;    /*!< [0..0] Cold/Warm Start Determination Flag                                 */
22644             uint8_t            : 7;
22645         } RSTSR2_b;
22646     };
22647     __IM uint8_t RESERVED45;
22648 
22649     union
22650     {
22651         __IOM uint8_t MOMCR;           /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control
22652                                         *                  Register                                                   */
22653 
22654         struct
22655         {
22656             uint8_t                 : 3;
22657             __IOM uint8_t MODRV1    : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching                 */
22658             __IOM uint8_t MODRV0    : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching                 */
22659             __IOM uint8_t MOSEL     : 1; /*!< [6..6] Main Clock Oscillator Switching                                    */
22660             __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching
22661                                           *   Enable                                                                    */
22662         } MOMCR_b;
22663     };
22664     __IM uint16_t RESERVED46;
22665 
22666     union
22667     {
22668         __IOM uint8_t FWEPROR;         /*!< (@ 0x00000416) Flash P/E Protect Register                                 */
22669 
22670         struct
22671         {
22672             __IOM uint8_t FLWE : 2;    /*!< [1..0] Flash Programming and Erasure                                      */
22673             uint8_t            : 6;
22674         } FWEPROR_b;
22675     };
22676 
22677     union
22678     {
22679         union
22680         {
22681             __IOM uint8_t LVCMPCR;     /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register                   */
22682 
22683             struct
22684             {
22685                 uint8_t             : 5;
22686                 __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable                                         */
22687                 __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable                                         */
22688                 uint8_t             : 1;
22689             } LVCMPCR_b;
22690         };
22691 
22692         union
22693         {
22694             __IOM uint8_t LVD1CMPCR;       /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register           */
22695 
22696             struct
22697             {
22698                 __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during
22699                                             *   drop in voltage)                                                          */
22700                 uint8_t             : 2;
22701                 __IOM uint8_t LVD1E : 1;   /*!< [7..7] Voltage Detection 1 Enable                                         */
22702             } LVD1CMPCR_b;
22703         };
22704     };
22705 
22706     union
22707     {
22708         union
22709         {
22710             __IOM uint8_t LVDLVLR;         /*!< (@ 0x00000418) Voltage Detection Level Select Register                    */
22711 
22712             struct
22713             {
22714                 __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during
22715                                             *   fall in voltage)                                                          */
22716                 __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during
22717                                             *   fall in voltage)                                                          */
22718             } LVDLVLR_b;
22719         };
22720 
22721         union
22722         {
22723             __IOM uint8_t LVD2CMPCR;       /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register           */
22724 
22725             struct
22726             {
22727                 __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during
22728                                             *   drop in voltage)                                                          */
22729                 uint8_t             : 4;
22730                 __IOM uint8_t LVD2E : 1;   /*!< [7..7] Voltage Detection 2 Enable                                         */
22731             } LVD2CMPCR_b;
22732         };
22733     };
22734     __IM uint8_t RESERVED47;
22735 
22736     union
22737     {
22738         __IOM uint8_t LVD1CR0;         /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0               */
22739 
22740         struct
22741         {
22742             __IOM uint8_t RIE   : 1;   /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
22743             __IOM uint8_t DFDIS : 1;   /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select                 */
22744             __IOM uint8_t CMPE  : 1;   /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
22745             uint8_t             : 1;
22746             __IOM uint8_t FSAMP : 2;   /*!< [5..4] Sampling Clock Select                                              */
22747             __IOM uint8_t RI    : 1;   /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
22748             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
22749         } LVD1CR0_b;
22750     };
22751 
22752     union
22753     {
22754         __IOM uint8_t LVD2CR0;         /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0               */
22755 
22756         struct
22757         {
22758             __IOM uint8_t RIE   : 1;   /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
22759             __IOM uint8_t DFDIS : 1;   /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select                 */
22760             __IOM uint8_t CMPE  : 1;   /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
22761             uint8_t             : 1;
22762             __IOM uint8_t FSAMP : 2;   /*!< [5..4] Sampling Clock Select                                              */
22763             __IOM uint8_t RI    : 1;   /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
22764             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
22765         } LVD2CR0_b;
22766     };
22767     __IM uint8_t RESERVED48;
22768 
22769     union
22770     {
22771         __IOM uint8_t VBATTMNSELR;        /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select
22772                                            *                  Register                                                   */
22773 
22774         struct
22775         {
22776             __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit                       */
22777             uint8_t                  : 7;
22778         } VBATTMNSELR_b;
22779     };
22780 
22781     union
22782     {
22783         __IM uint8_t VBATTMONR;        /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register                    */
22784 
22785         struct
22786         {
22787             __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit                                          */
22788             uint8_t               : 7;
22789         } VBATTMONR_b;
22790     };
22791 
22792     union
22793     {
22794         __IOM uint8_t VBTCR1;           /*!< (@ 0x0000041F) VBATT Control Register1                                    */
22795 
22796         struct
22797         {
22798             __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop                                   */
22799             uint8_t                : 7;
22800         } VBTCR1_b;
22801     };
22802     __IM uint32_t RESERVED49[8];
22803 
22804     union
22805     {
22806         __IOM uint8_t DCDCCTL;         /*!< (@ 0x00000440) DCDC/LDO Control Register                                  */
22807 
22808         struct
22809         {
22810             __IOM uint8_t DCDCON  : 1; /*!< [0..0] LDO/DCDC on/off Control bit                                        */
22811             __IOM uint8_t OCPEN   : 1; /*!< [1..1] DCDC OCP Function Enable bit                                       */
22812             uint8_t               : 2;
22813             __IOM uint8_t STOPZA  : 1; /*!< [4..4] DCDC IO Buffer Power Control bit                                   */
22814             __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit                                       */
22815             __IOM uint8_t FST     : 1; /*!< [6..6] DCDC Fast Startup                                                  */
22816             __IOM uint8_t PD      : 1; /*!< [7..7] DCDC VREF Generate Disable bit                                     */
22817         } DCDCCTL_b;
22818     };
22819 
22820     union
22821     {
22822         __IOM uint8_t VCCSEL;          /*!< (@ 0x00000441) Voltage Level Selection Control Register                   */
22823 
22824         struct
22825         {
22826             __IOM uint8_t VCCSEL : 2;  /*!< [1..0] DCDC Working Voltage Level Selection                               */
22827             uint8_t              : 6;
22828         } VCCSEL_b;
22829     };
22830     __IM uint16_t RESERVED50;
22831     __IM uint32_t RESERVED51[15];
22832 
22833     union
22834     {
22835         __IOM uint8_t SOSCCR;          /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register                      */
22836 
22837         struct
22838         {
22839             __IOM uint8_t SOSTP : 1;   /*!< [0..0] Sub-Clock Oscillator Stop                                          */
22840             uint8_t             : 7;
22841         } SOSCCR_b;
22842     };
22843 
22844     union
22845     {
22846         __IOM uint8_t SOMCR;           /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register                 */
22847 
22848         struct
22849         {
22850             __IOM uint8_t SODRV : 2;   /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching                    */
22851             uint8_t             : 6;
22852         } SOMCR_b;
22853     };
22854     __IM uint16_t RESERVED52;
22855     __IM uint32_t RESERVED53[3];
22856 
22857     union
22858     {
22859         __IOM uint8_t LOCOCR;          /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register              */
22860 
22861         struct
22862         {
22863             __IOM uint8_t LCSTP : 1;   /*!< [0..0] LOCO Stop                                                          */
22864             uint8_t             : 7;
22865         } LOCOCR_b;
22866     };
22867     __IM uint8_t RESERVED54;
22868 
22869     union
22870     {
22871         __IOM uint8_t LOCOUTCR;         /*!< (@ 0x00000492) LOCO User Trimming Control Register                        */
22872 
22873         struct
22874         {
22875             __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127
22876                                          *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
22877                                          *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
22878                                          +126 0111_1111 : +127These bits are added to original LOCO
22879                                          *   trimming bits                                                             */
22880         } LOCOUTCR_b;
22881     };
22882     __IM uint8_t  RESERVED55;
22883     __IM uint32_t RESERVED56[7];
22884 
22885     union
22886     {
22887         __IOM uint8_t VBTCR2;          /*!< (@ 0x000004B0) VBATT Control Register2                                    */
22888 
22889         struct
22890         {
22891             uint8_t                 : 4;
22892             __IOM uint8_t VBTLVDEN  : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit                            */
22893             uint8_t                 : 1;
22894             __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit              */
22895         } VBTCR2_b;
22896     };
22897 
22898     union
22899     {
22900         __IOM uint8_t VBTSR;           /*!< (@ 0x000004B1) VBATT Status Register                                      */
22901 
22902         struct
22903         {
22904             __IOM uint8_t VBTRDF  : 1; /*!< [0..0] VBAT_R Reset Detect Flag                                           */
22905             __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag                              */
22906             uint8_t               : 2;
22907             __IM uint8_t VBTRVLD  : 1; /*!< [4..4] VBATT_R Valid                                                      */
22908             uint8_t               : 3;
22909         } VBTSR_b;
22910     };
22911 
22912     union
22913     {
22914         __IOM uint8_t VBTCMPCR;        /*!< (@ 0x000004B2) VBATT Comparator Control Register                          */
22915 
22916         struct
22917         {
22918             __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable                 */
22919             uint8_t               : 7;
22920         } VBTCMPCR_b;
22921     };
22922     __IM uint8_t RESERVED57;
22923 
22924     union
22925     {
22926         __IOM uint8_t VBTLVDICR;          /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control
22927                                            *                  Register                                                   */
22928 
22929         struct
22930         {
22931             __IOM uint8_t VBTLVDIE   : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit                  */
22932             __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit                        */
22933             uint8_t                  : 6;
22934         } VBTLVDICR_b;
22935     };
22936     __IM uint8_t RESERVED58;
22937 
22938     union
22939     {
22940         __IOM uint8_t VBTWCTLR;        /*!< (@ 0x000004B6) VBATT Wakeup function Control Register                     */
22941 
22942         struct
22943         {
22944             __IOM uint8_t VWEN : 1;    /*!< [0..0] VBATT wakeup enable                                                */
22945             uint8_t            : 7;
22946         } VBTWCTLR_b;
22947     };
22948     __IM uint8_t RESERVED59;
22949 
22950     union
22951     {
22952         __IOM uint8_t VBTWCH0OTSR;     /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register          */
22953 
22954         struct
22955         {
22956             uint8_t                  : 1;
22957             __IOM uint8_t CH0VCH1TE  : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable                            */
22958             __IOM uint8_t CH0VCH2TE  : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable                            */
22959             __IOM uint8_t CH0VRTCTE  : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable                         */
22960             __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable                            */
22961             __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable                        */
22962             uint8_t                  : 2;
22963         } VBTWCH0OTSR_b;
22964     };
22965 
22966     union
22967     {
22968         __IOM uint8_t VBTWCH1OTSR;        /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register          */
22969 
22970         struct
22971         {
22972             __IOM uint8_t CH1VCH0TE  : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable                            */
22973             uint8_t                  : 1;
22974             __IOM uint8_t CH1VCH2TE  : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable                            */
22975             __IOM uint8_t CH1VRTCTE  : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable                         */
22976             __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable                            */
22977             __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable                        */
22978             uint8_t                  : 2;
22979         } VBTWCH1OTSR_b;
22980     };
22981 
22982     union
22983     {
22984         __IOM uint8_t VBTWCH2OTSR;        /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register          */
22985 
22986         struct
22987         {
22988             __IOM uint8_t CH2VCH0TE  : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable                            */
22989             __IOM uint8_t CH2VCH1TE  : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable                            */
22990             uint8_t                  : 1;
22991             __IOM uint8_t CH2VRTCTE  : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable                         */
22992             __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable                            */
22993             __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable                        */
22994             uint8_t                  : 2;
22995         } VBTWCH2OTSR_b;
22996     };
22997 
22998     union
22999     {
23000         __IOM uint8_t VBTICTLR;         /*!< (@ 0x000004BB) VBATT Input Control Register                               */
23001 
23002         struct
23003         {
23004             __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable                                                */
23005             __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable                                                */
23006             __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable                                                */
23007             uint8_t                : 5;
23008         } VBTICTLR_b;
23009     };
23010 
23011     union
23012     {
23013         __IOM uint8_t VBTOCTLR;          /*!< (@ 0x000004BC) VBATT Output Control Register                              */
23014 
23015         struct
23016         {
23017             __IOM uint8_t VCH0OEN   : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable                                   */
23018             __IOM uint8_t VCH1OEN   : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable                                   */
23019             __IOM uint8_t VCH2OEN   : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable                                   */
23020             __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection                          */
23021             __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection                          */
23022             __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection                          */
23023             uint8_t                 : 2;
23024         } VBTOCTLR_b;
23025     };
23026 
23027     union
23028     {
23029         __IOM uint8_t VBTWTER;         /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register                */
23030 
23031         struct
23032         {
23033             __IOM uint8_t VCH0E  : 1;  /*!< [0..0] VBATWIO0 Pin Enable                                                */
23034             __IOM uint8_t VCH1E  : 1;  /*!< [1..1] VBATWIO1 Pin Enable                                                */
23035             __IOM uint8_t VCH2E  : 1;  /*!< [2..2] VBATWIO2 Pin Enable                                                */
23036             __IOM uint8_t VRTCIE : 1;  /*!< [3..3] RTC Periodic Signal Enable                                         */
23037             __IOM uint8_t VRTCAE : 1;  /*!< [4..4] RTC Alarm Signal Enable                                            */
23038             __IOM uint8_t VAGTUE : 1;  /*!< [5..5] AGT(ch1) underflow Signal Enable                                   */
23039             uint8_t              : 2;
23040         } VBTWTER_b;
23041     };
23042 
23043     union
23044     {
23045         __IOM uint8_t VBTWEGR;         /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register                  */
23046 
23047         struct
23048         {
23049             __IOM uint8_t VCH0EG : 1;  /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select                         */
23050             __IOM uint8_t VCH1EG : 1;  /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select                         */
23051             __IOM uint8_t VCH2EG : 1;  /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select                         */
23052             uint8_t              : 5;
23053         } VBTWEGR_b;
23054     };
23055 
23056     union
23057     {
23058         __IOM uint8_t VBTWFR;          /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register                  */
23059 
23060         struct
23061         {
23062             __IOM uint8_t VCH0F  : 1;  /*!< [0..0] VBATWIO0 Wakeup Trigger Flag                                       */
23063             __IOM uint8_t VCH1F  : 1;  /*!< [1..1] VBATWIO1 Wakeup Trigger Flag                                       */
23064             __IOM uint8_t VCH2F  : 1;  /*!< [2..2] VBATWIO2 Wakeup Trigger Flag                                       */
23065             __IOM uint8_t VRTCIF : 1;  /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag                             */
23066             __IOM uint8_t VRTCAF : 1;  /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag                                */
23067             __IOM uint8_t VAGTUF : 1;  /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag                       */
23068             uint8_t              : 2;
23069         } VBTWFR_b;
23070     };
23071 
23072     union
23073     {
23074         __IOM uint8_t VBTBER;          /*!< (@ 0x000004C0) VBATT Backup Enable Register                               */
23075 
23076         struct
23077         {
23078             uint8_t            : 3;
23079             __IOM uint8_t VBAE : 1;    /*!< [3..3] VBATT backup register access enable bit                            */
23080             uint8_t            : 4;
23081         } VBTBER_b;
23082     };
23083     __IM uint8_t  RESERVED60;
23084     __IM uint16_t RESERVED61;
23085     __IM uint32_t RESERVED62[15];
23086 
23087     union
23088     {
23089         __IOM uint8_t VBTBKR[512];     /*!< (@ 0x00000500) VBATT Backup Register [0..511]                             */
23090 
23091         struct
23092         {
23093             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store
23094                                         *   data powered by VBATT.The value of this register is retained
23095                                         *   even when VCC is not powered but VBATT is powered.VBTBKR
23096                                         *   is initialized by VBATT selected voltage power-on-reset.                  */
23097         } VBTBKR_b[512];
23098     };
23099 } R_SYSTEM_Type;                       /*!< Size = 1792 (0x700)                                                       */
23100 
23101 /* =========================================================================================================================== */
23102 /* ================                                           R_TSN                                           ================ */
23103 /* =========================================================================================================================== */
23104 
23105 /**
23106  * @brief Temperature Sensor (R_TSN)
23107  */
23108 
23109 typedef struct                         /*!< (@ 0x407EC000) R_TSN Structure                                            */
23110 {
23111     __IM uint8_t RESERVED[552];
23112 
23113     union
23114     {
23115         __IM uint8_t TSCDRL;           /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register
23116                                         *                  L                                                          */
23117 
23118         struct
23119         {
23120             __IM uint8_t TSCDRL : 8;   /*!< [7..0] The calibration data stores the lower 8 bits of the convertedvalue. */
23121         } TSCDRL_b;
23122     };
23123 
23124     union
23125     {
23126         __IM uint8_t TSCDRH;           /*!< (@ 0x00000229) Temperature Sensor Calibration Data Register
23127                                         *                  H                                                          */
23128 
23129         struct
23130         {
23131             __IM uint8_t TSCDRH : 8;   /*!< [7..0] The calibration data stores the higher 8 bits of the
23132                                         *   convertedvalue.                                                           */
23133         } TSCDRH_b;
23134     };
23135 } R_TSN_Type;                          /*!< Size = 554 (0x22a)                                                        */
23136 
23137 /* =========================================================================================================================== */
23138 /* ================                                         R_TSN_CAL                                         ================ */
23139 /* =========================================================================================================================== */
23140 
23141 /**
23142  * @brief Temperature Sensor (R_TSN_CAL)
23143  */
23144 
23145 typedef struct                         /*!< (@ 0x407FB17C) R_TSN_CAL Structure                                        */
23146 {
23147     union
23148     {
23149         __IM uint32_t TSCDR;           /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register        */
23150 
23151         struct
23152         {
23153             __IM uint32_t TSCDR : 32;  /*!< [31..0] The 32 bit TSCDR register stores temperature sensor
23154                                         *   calibration converted value.                                              */
23155         } TSCDR_b;
23156     };
23157 } R_TSN_CAL_Type;                      /*!< Size = 4 (0x4)                                                            */
23158 
23159 /* =========================================================================================================================== */
23160 /* ================                                        R_TSN_CTRL                                         ================ */
23161 /* =========================================================================================================================== */
23162 
23163 /**
23164  * @brief Temperature Sensor (R_TSN_CTRL)
23165  */
23166 
23167 typedef struct                         /*!< (@ 0x4005D000) R_TSN_CTRL Structure                                       */
23168 {
23169     union
23170     {
23171         __IOM uint8_t TSCR;            /*!< (@ 0x00000000) Temperature Sensor Control Register                        */
23172 
23173         struct
23174         {
23175             uint8_t            : 4;
23176             __IOM uint8_t TSOE : 1;    /*!< [4..4] Temperature Sensor Enable                                          */
23177             uint8_t            : 2;
23178             __IOM uint8_t TSEN : 1;    /*!< [7..7] Temperature Sensor Output Enable                                   */
23179         } TSCR_b;
23180     };
23181 } R_TSN_CTRL_Type;                     /*!< Size = 1 (0x1)                                                            */
23182 
23183 /* =========================================================================================================================== */
23184 /* ================                                         R_USB_FS0                                         ================ */
23185 /* =========================================================================================================================== */
23186 
23187 /**
23188  * @brief USB 2.0 Module (R_USB_FS0)
23189  */
23190 
23191 typedef struct                         /*!< (@ 0x40090000) R_USB_FS0 Structure                                        */
23192 {
23193     union
23194     {
23195         __IOM uint16_t SYSCFG;         /*!< (@ 0x00000000) System Configuration Control Register                      */
23196 
23197         struct
23198         {
23199             __IOM uint16_t USBE  : 1;  /*!< [0..0] USB Operation Enable                                               */
23200             uint16_t             : 2;
23201             __IOM uint16_t DMRPU : 1;  /*!< [3..3] D- Line Resistor Control                                           */
23202             __IOM uint16_t DPRPU : 1;  /*!< [4..4] D+ Line Resistor Control                                           */
23203             __IOM uint16_t DRPD  : 1;  /*!< [5..5] D+/D- Line Resistor Control                                        */
23204             __IOM uint16_t DCFM  : 1;  /*!< [6..6] Controller Function Select                                         */
23205             uint16_t             : 1;
23206             __IOM uint16_t CNEN  : 1;  /*!< [8..8] CNEN Single End Receiver Enable                                    */
23207             uint16_t             : 1;
23208             __IOM uint16_t SCKE  : 1;  /*!< [10..10] USB Clock Enable                                                 */
23209             uint16_t             : 5;
23210         } SYSCFG_b;
23211     };
23212 
23213     union
23214     {
23215         __IOM uint16_t BUSWAIT;        /*!< (@ 0x00000002) CPU Bus Wait Register                                      */
23216 
23217         struct
23218         {
23219             __IOM uint16_t BWAIT : 4;  /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
23220                                         *   access cycles)                                                            */
23221             uint16_t : 12;
23222         } BUSWAIT_b;
23223     };
23224 
23225     union
23226     {
23227         __IM uint16_t SYSSTS0;         /*!< (@ 0x00000004) System Configuration Status Register 0                     */
23228 
23229         struct
23230         {
23231             __IM uint16_t LNST  : 2;   /*!< [1..0] USB Data Line Status Monitor                                       */
23232             __IM uint16_t IDMON : 1;   /*!< [2..2] External ID0 Input Pin Monitor                                     */
23233             uint16_t            : 2;
23234             __IM uint16_t SOFEA : 1;   /*!< [5..5] SOF Active Monitor While Host Controller Function is
23235                                         *   Selected.                                                                 */
23236             __IM uint16_t HTACT  : 1;  /*!< [6..6] USB Host Sequencer Status Monitor                                  */
23237             uint16_t             : 7;
23238             __IM uint16_t OVCMON : 2;  /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe
23239                                         *   OCVMON[1] bit indicates the status of the USBHS_OVRCURA
23240                                         *   pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
23241                                         *   pin.                                                                      */
23242         } SYSSTS0_b;
23243     };
23244 
23245     union
23246     {
23247         __IM uint16_t PLLSTA;          /*!< (@ 0x00000006) PLL Status Register                                        */
23248 
23249         struct
23250         {
23251             __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag                                                      */
23252             uint16_t              : 15;
23253         } PLLSTA_b;
23254     };
23255 
23256     union
23257     {
23258         __IOM uint16_t DVSTCTR0;        /*!< (@ 0x00000008) Device State Control Register 0                            */
23259 
23260         struct
23261         {
23262             __IM uint16_t RHST     : 3; /*!< [2..0] USB Bus Reset Status                                               */
23263             uint16_t               : 1;
23264             __IOM uint16_t UACT    : 1; /*!< [4..4] USB Bus Enable                                                     */
23265             __IOM uint16_t RESUME  : 1; /*!< [5..5] Resume Output                                                      */
23266             __IOM uint16_t USBRST  : 1; /*!< [6..6] USB Bus Reset Output                                               */
23267             __IOM uint16_t RWUPE   : 1; /*!< [7..7] Wakeup Detection Enable                                            */
23268             __IOM uint16_t WKUP    : 1; /*!< [8..8] Wakeup Output                                                      */
23269             __IOM uint16_t VBUSEN  : 1; /*!< [9..9] USB_VBUSEN Output Pin Control                                      */
23270             __IOM uint16_t EXICEN  : 1; /*!< [10..10] USB_EXICEN Output Pin Control                                    */
23271             __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is
23272                                          *   used when switching from device B to device A while in
23273                                          *   OTG mode. If the HNPBTOA bit is 1, the internal function
23274                                          *   control keeps the suspended state until the HNP processing
23275                                          *   ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is
23276                                          *   set.                                                                      */
23277             uint16_t : 4;
23278         } DVSTCTR0_b;
23279     };
23280     __IM uint16_t RESERVED;
23281 
23282     union
23283     {
23284         __IOM uint16_t TESTMODE;       /*!< (@ 0x0000000C) USB Test Mode Register                                     */
23285 
23286         struct
23287         {
23288             __IOM uint16_t UTST : 4;   /*!< [3..0] Test Mode                                                          */
23289             uint16_t            : 12;
23290         } TESTMODE_b;
23291     };
23292     __IM uint16_t RESERVED1;
23293     __IM uint32_t RESERVED2;
23294 
23295     union
23296     {
23297         __IOM uint32_t CFIFO;          /*!< (@ 0x00000014) CFIFO Port Register                                        */
23298 
23299         struct
23300         {
23301             union
23302             {
23303                 __IOM uint16_t CFIFOL;  /*!< (@ 0x00000014) CFIFO Port Register L                                      */
23304                 __IOM uint8_t  CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL                                     */
23305             };
23306 
23307             union
23308             {
23309                 __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H                                      */
23310 
23311                 struct
23312                 {
23313                     __IM uint8_t  RESERVED3;
23314                     __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH                                     */
23315                 };
23316             };
23317         };
23318     };
23319 
23320     union
23321     {
23322         __IOM uint32_t D0FIFO;         /*!< (@ 0x00000018) D0FIFO Port Register                                       */
23323 
23324         struct
23325         {
23326             union
23327             {
23328                 __IOM uint16_t D0FIFOL;  /*!< (@ 0x00000018) D0FIFO Port Register L                                     */
23329                 __IOM uint8_t  D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL                                    */
23330             };
23331 
23332             union
23333             {
23334                 __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H                                     */
23335 
23336                 struct
23337                 {
23338                     __IM uint8_t  RESERVED4;
23339                     __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH                                    */
23340                 };
23341             };
23342         };
23343     };
23344 
23345     union
23346     {
23347         __IOM uint32_t D1FIFO;         /*!< (@ 0x0000001C) D1FIFO Port Register                                       */
23348 
23349         struct
23350         {
23351             union
23352             {
23353                 __IOM uint16_t D1FIFOL;  /*!< (@ 0x0000001C) D1FIFO Port Register L                                     */
23354                 __IOM uint8_t  D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL                                    */
23355             };
23356 
23357             union
23358             {
23359                 __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H                                     */
23360 
23361                 struct
23362                 {
23363                     __IM uint8_t  RESERVED5;
23364                     __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH                                    */
23365                 };
23366             };
23367         };
23368     };
23369 
23370     union
23371     {
23372         __IOM uint16_t CFIFOSEL;        /*!< (@ 0x00000020) CFIFO Port Select Register                                 */
23373 
23374         struct
23375         {
23376             __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification                               */
23377             uint16_t               : 1;
23378             __IOM uint16_t ISEL    : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected                   */
23379             uint16_t               : 2;
23380             __IOM uint16_t BIGEND  : 1; /*!< [8..8] CFIFO Port Endian Control                                          */
23381             uint16_t               : 1;
23382             __IOM uint16_t MBW     : 2; /*!< [11..10] CFIFO Port Access Bit Width                                      */
23383             uint16_t               : 2;
23384             __IOM uint16_t REW     : 1; /*!< [14..14] Buffer Pointer Rewind                                            */
23385             __IOM uint16_t RCNT    : 1; /*!< [15..15] Read Count Mode                                                  */
23386         } CFIFOSEL_b;
23387     };
23388 
23389     union
23390     {
23391         __IOM uint16_t CFIFOCTR;       /*!< (@ 0x00000022) CFIFO Port Control Register                                */
23392 
23393         struct
23394         {
23395             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
23396                                         *   data.                                                                     */
23397             uint16_t            : 1;
23398             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
23399             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
23400             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
23401         } CFIFOCTR_b;
23402     };
23403     __IM uint32_t RESERVED6;
23404 
23405     union
23406     {
23407         __IOM uint16_t D0FIFOSEL;       /*!< (@ 0x00000028) D0FIFO Port Select Register                                */
23408 
23409         struct
23410         {
23411             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
23412             uint16_t               : 4;
23413             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
23414             uint16_t               : 1;
23415             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
23416             __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
23417             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
23418                                          *   Pipe Data is Read                                                         */
23419             __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read.                   */
23420             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
23421         } D0FIFOSEL_b;
23422     };
23423 
23424     union
23425     {
23426         __IOM uint16_t D0FIFOCTR;      /*!< (@ 0x0000002A) D0FIFO Port Control Register                               */
23427 
23428         struct
23429         {
23430             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
23431                                         *   data.                                                                     */
23432             uint16_t            : 1;
23433             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
23434             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
23435             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
23436         } D0FIFOCTR_b;
23437     };
23438 
23439     union
23440     {
23441         __IOM uint16_t D1FIFOSEL;       /*!< (@ 0x0000002C) D1FIFO Port Select Register                                */
23442 
23443         struct
23444         {
23445             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
23446             uint16_t               : 4;
23447             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
23448             uint16_t               : 1;
23449             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
23450             __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
23451             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
23452                                          *   Pipe Data is Read                                                         */
23453             __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
23454             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
23455         } D1FIFOSEL_b;
23456     };
23457 
23458     union
23459     {
23460         __IOM uint16_t D1FIFOCTR;      /*!< (@ 0x0000002E) D1FIFO Port Control Register                               */
23461 
23462         struct
23463         {
23464             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
23465                                         *   data.                                                                     */
23466             uint16_t            : 1;
23467             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
23468             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
23469             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
23470         } D1FIFOCTR_b;
23471     };
23472 
23473     union
23474     {
23475         __IOM uint16_t INTENB0;        /*!< (@ 0x00000030) Interrupt Enable Register 0                                */
23476 
23477         struct
23478         {
23479             uint16_t             : 8;
23480             __IOM uint16_t BRDYE : 1;  /*!< [8..8] Buffer Ready Interrupt Enable                                      */
23481             __IOM uint16_t NRDYE : 1;  /*!< [9..9] Buffer Not Ready Response Interrupt Enable                         */
23482             __IOM uint16_t BEMPE : 1;  /*!< [10..10] Buffer Empty Interrupt Enable                                    */
23483             __IOM uint16_t CTRE  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Enable               */
23484             __IOM uint16_t DVSE  : 1;  /*!< [12..12] Device State Transition Interrupt Enable                         */
23485             __IOM uint16_t SOFE  : 1;  /*!< [13..13] Frame Number Update Interrupt Enable                             */
23486             __IOM uint16_t RSME  : 1;  /*!< [14..14] Resume Interrupt Enable                                          */
23487             __IOM uint16_t VBSE  : 1;  /*!< [15..15] VBUS Interrupt Enable                                            */
23488         } INTENB0_b;
23489     };
23490 
23491     union
23492     {
23493         __IOM uint16_t INTENB1;            /*!< (@ 0x00000032) Interrupt Enable Register 1                                */
23494 
23495         struct
23496         {
23497             __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable                               */
23498             uint16_t                  : 3;
23499             __IOM uint16_t SACKE      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable                 */
23500             __IOM uint16_t SIGNE      : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable                           */
23501             __IOM uint16_t EOFERRE    : 1; /*!< [6..6] EOF Error Detection Interrupt Enable                               */
23502             uint16_t                  : 4;
23503             __IOM uint16_t ATTCHE     : 1; /*!< [11..11] Connection Detection Interrupt Enable                            */
23504             __IOM uint16_t DTCHE      : 1; /*!< [12..12] Disconnection Detection Interrupt Enable                         */
23505             uint16_t                  : 1;
23506             __IOM uint16_t BCHGE      : 1; /*!< [14..14] USB Bus Change Interrupt Enable                                  */
23507             __IOM uint16_t OVRCRE     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable                        */
23508         } INTENB1_b;
23509     };
23510     __IM uint16_t RESERVED7;
23511 
23512     union
23513     {
23514         __IOM uint16_t BRDYENB;            /*!< (@ 0x00000036) BRDY Interrupt Enable Register                             */
23515 
23516         struct
23517         {
23518             __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE                                     */
23519             __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE                                     */
23520             __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE                                     */
23521             __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE                                     */
23522             __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE                                     */
23523             __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE                                     */
23524             __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE                                     */
23525             __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE                                     */
23526             __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE                                     */
23527             __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE                                     */
23528             uint16_t                  : 6;
23529         } BRDYENB_b;
23530     };
23531 
23532     union
23533     {
23534         __IOM uint16_t NRDYENB;            /*!< (@ 0x00000038) NRDY Interrupt Enable Register                             */
23535 
23536         struct
23537         {
23538             __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE                                     */
23539             __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE                                     */
23540             __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE                                     */
23541             __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE                                     */
23542             __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE                                     */
23543             __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE                                     */
23544             __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE                                     */
23545             __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE                                     */
23546             __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE                                     */
23547             __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE                                     */
23548             uint16_t                  : 6;
23549         } NRDYENB_b;
23550     };
23551 
23552     union
23553     {
23554         __IOM uint16_t BEMPENB;            /*!< (@ 0x0000003A) BEMP Interrupt Enable Register                             */
23555 
23556         struct
23557         {
23558             __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE                                     */
23559             __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE                                     */
23560             __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE                                     */
23561             __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE                                     */
23562             __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE                                     */
23563             __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE                                     */
23564             __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE                                     */
23565             __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE                                     */
23566             __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE                                     */
23567             __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE                                     */
23568             uint16_t                  : 6;
23569         } BEMPENB_b;
23570     };
23571 
23572     union
23573     {
23574         __IOM uint16_t SOFCFG;         /*!< (@ 0x0000003C) SOF Output Configuration Register                          */
23575 
23576         struct
23577         {
23578             uint16_t                : 4;
23579             __IM uint16_t  EDGESTS  : 1; /*!< [4..4] Edge Interrupt Output Status Monitor                               */
23580             __IOM uint16_t INTL     : 1; /*!< [5..5] Interrupt Output Sense Select                                      */
23581             __IOM uint16_t BRDYM    : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing                                 */
23582             uint16_t                : 1;
23583             __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select                                    */
23584             uint16_t                : 7;
23585         } SOFCFG_b;
23586     };
23587 
23588     union
23589     {
23590         __IOM uint16_t PHYSET;           /*!< (@ 0x0000003E) PHY Setting Register                                       */
23591 
23592         struct
23593         {
23594             __IOM uint16_t DIRPD    : 1; /*!< [0..0] Power-Down Control                                                 */
23595             __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control                                                  */
23596             uint16_t                : 1;
23597             __IOM uint16_t CDPEN    : 1; /*!< [3..3] Charging Downstream Port Enable                                    */
23598             __IOM uint16_t CLKSEL   : 2; /*!< [5..4] Input System Clock Frequency                                       */
23599             uint16_t                : 2;
23600             __IOM uint16_t REPSEL   : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle                            */
23601             uint16_t                : 1;
23602             __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment                 */
23603             uint16_t                : 3;
23604             __IOM uint16_t HSEB     : 1; /*!< [15..15] CL-Only Mode                                                     */
23605         } PHYSET_b;
23606     };
23607 
23608     union
23609     {
23610         __IOM uint16_t INTSTS0;        /*!< (@ 0x00000040) Interrupt Status Register 0                                */
23611 
23612         struct
23613         {
23614             __IM uint16_t  CTSQ  : 3;  /*!< [2..0] Control Transfer Stage                                             */
23615             __IOM uint16_t VALID : 1;  /*!< [3..3] USB Request Reception                                              */
23616             __IM uint16_t  DVSQ  : 3;  /*!< [6..4] Device State                                                       */
23617             __IM uint16_t  VBSTS : 1;  /*!< [7..7] VBUS Input Status                                                  */
23618             __IM uint16_t  BRDY  : 1;  /*!< [8..8] Buffer Ready Interrupt Status                                      */
23619             __IM uint16_t  NRDY  : 1;  /*!< [9..9] Buffer Not Ready Interrupt Status                                  */
23620             __IM uint16_t  BEMP  : 1;  /*!< [10..10] Buffer Empty Interrupt Status                                    */
23621             __IOM uint16_t CTRT  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Status               */
23622             __IOM uint16_t DVST  : 1;  /*!< [12..12] Device State Transition Interrupt Status                         */
23623             __IOM uint16_t SOFR  : 1;  /*!< [13..13] Frame Number Refresh Interrupt Status                            */
23624             __IOM uint16_t RESM  : 1;  /*!< [14..14] Resume Interrupt Status                                          */
23625             __IOM uint16_t VBINT : 1;  /*!< [15..15] VBUS Interrupt Status                                            */
23626         } INTSTS0_b;
23627     };
23628 
23629     union
23630     {
23631         __IOM uint16_t INTSTS1;           /*!< (@ 0x00000042) Interrupt Status Register 1                                */
23632 
23633         struct
23634         {
23635             __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status                                  */
23636             uint16_t                 : 3;
23637             __IOM uint16_t SACK      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status                 */
23638             __IOM uint16_t SIGN      : 1; /*!< [5..5] Setup Transaction Error Interrupt Status                           */
23639             __IOM uint16_t EOFERR    : 1; /*!< [6..6] EOF Error Detection Interrupt Status                               */
23640             uint16_t                 : 1;
23641             __IOM uint16_t LPMEND    : 1; /*!< [8..8] LPM Transaction End Interrupt Status                               */
23642             __IOM uint16_t L1RSMEND  : 1; /*!< [9..9] L1 Resume End Interrupt Status                                     */
23643             uint16_t                 : 1;
23644             __IOM uint16_t ATTCH     : 1; /*!< [11..11] ATTCH Interrupt Status                                           */
23645             __IOM uint16_t DTCH      : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status                     */
23646             uint16_t                 : 1;
23647             __IOM uint16_t BCHG      : 1; /*!< [14..14] USB Bus Change Interrupt Status                                  */
23648             __IOM uint16_t OVRCR     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status                        */
23649         } INTSTS1_b;
23650     };
23651     __IM uint16_t RESERVED8;
23652 
23653     union
23654     {
23655         __IOM uint16_t BRDYSTS;           /*!< (@ 0x00000046) BRDY Interrupt Status Register                             */
23656 
23657         struct
23658         {
23659             __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE                                     */
23660             __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE                                     */
23661             __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE                                     */
23662             __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE                                     */
23663             __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE                                     */
23664             __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE                                     */
23665             __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE                                     */
23666             __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE                                     */
23667             __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE                                     */
23668             __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE                                     */
23669             uint16_t                 : 6;
23670         } BRDYSTS_b;
23671     };
23672 
23673     union
23674     {
23675         __IOM uint16_t NRDYSTS;           /*!< (@ 0x00000048) NRDY Interrupt Status Register                             */
23676 
23677         struct
23678         {
23679             __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE                                     */
23680             __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE                                     */
23681             __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE                                     */
23682             __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE                                     */
23683             __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE                                     */
23684             __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE                                     */
23685             __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE                                     */
23686             __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE                                     */
23687             __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE                                     */
23688             __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE                                     */
23689             uint16_t                 : 6;
23690         } NRDYSTS_b;
23691     };
23692 
23693     union
23694     {
23695         __IOM uint16_t BEMPSTS;           /*!< (@ 0x0000004A) BEMP Interrupt Status Register                             */
23696 
23697         struct
23698         {
23699             __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE                                     */
23700             __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE                                     */
23701             __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE                                     */
23702             __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE                                     */
23703             __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE                                     */
23704             __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE                                     */
23705             __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE                                     */
23706             __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE                                     */
23707             __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE                                     */
23708             __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE                                     */
23709             uint16_t                 : 6;
23710         } BEMPSTS_b;
23711     };
23712 
23713     union
23714     {
23715         __IOM uint16_t FRMNUM;         /*!< (@ 0x0000004C) Frame Number Register                                      */
23716 
23717         struct
23718         {
23719             __IM uint16_t FRNM  : 11;  /*!< [10..0] Frame NumberLatest frame number                                   */
23720             uint16_t            : 3;
23721             __IOM uint16_t CRCE : 1;   /*!< [14..14] Receive Data Error                                               */
23722             __IOM uint16_t OVRN : 1;   /*!< [15..15] Overrun/Underrun Detection Status                                */
23723         } FRMNUM_b;
23724     };
23725 
23726     union
23727     {
23728         __IOM uint16_t UFRMNUM;        /*!< (@ 0x0000004E) uFrame Number Register                                     */
23729 
23730         struct
23731         {
23732             __IM uint16_t UFRNM  : 3;  /*!< [2..0] MicroframeIndicate the microframe number.                          */
23733             uint16_t             : 12;
23734             __IOM uint16_t DVCHG : 1;  /*!< [15..15] Device State Change                                              */
23735         } UFRMNUM_b;
23736     };
23737 
23738     union
23739     {
23740         __IOM uint16_t USBADDR;           /*!< (@ 0x00000050) USB Address Register                                       */
23741 
23742         struct
23743         {
23744             __IM uint16_t USBADDR : 7;    /*!< [6..0] USB Address In device controller mode, these flags indicate
23745                                            *   the USB address assigned by the host when the USBHS processed
23746                                            *   the SET_ADDRESS request successfully.                                     */
23747             uint16_t                 : 1;
23748             __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery                                                   */
23749             uint16_t                 : 5;
23750         } USBADDR_b;
23751     };
23752     __IM uint16_t RESERVED9;
23753 
23754     union
23755     {
23756         __IOM uint16_t USBREQ;                /*!< (@ 0x00000054) USB Request Type Register                                  */
23757 
23758         struct
23759         {
23760             __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType
23761                                                *   value.                                                                    */
23762             __IOM uint16_t BREQUEST : 8;      /*!< [15..8] RequestThese bits store the USB request bRequest value.           */
23763         } USBREQ_b;
23764     };
23765 
23766     union
23767     {
23768         __IOM uint16_t USBVAL;          /*!< (@ 0x00000056) USB Request Value Register                                 */
23769 
23770         struct
23771         {
23772             __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value.                */
23773         } USBVAL_b;
23774     };
23775 
23776     union
23777     {
23778         __IOM uint16_t USBINDX;         /*!< (@ 0x00000058) USB Request Index Register                                 */
23779 
23780         struct
23781         {
23782             __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value.               */
23783         } USBINDX_b;
23784     };
23785 
23786     union
23787     {
23788         __IOM uint16_t USBLENG;          /*!< (@ 0x0000005A) USB Request Length Register                                */
23789 
23790         struct
23791         {
23792             __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value.             */
23793         } USBLENG_b;
23794     };
23795 
23796     union
23797     {
23798         __IOM uint16_t DCPCFG;         /*!< (@ 0x0000005C) DCP Configuration Register                                 */
23799 
23800         struct
23801         {
23802             uint16_t              : 4;
23803             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
23804             uint16_t              : 2;
23805             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
23806             __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
23807             uint16_t              : 7;
23808         } DCPCFG_b;
23809     };
23810 
23811     union
23812     {
23813         __IOM uint16_t DCPMAXP;        /*!< (@ 0x0000005E) DCP Maximum Packet Size Register                           */
23814 
23815         struct
23816         {
23817             __IOM uint16_t MXPS : 7;   /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount
23818                                         *   of data (maximum packet size) in payloads for the DCP.                    */
23819             uint16_t              : 5;
23820             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
23821         } DCPMAXP_b;
23822     };
23823 
23824     union
23825     {
23826         __IOM uint16_t DCPCTR;           /*!< (@ 0x00000060) DCP Control Register                                       */
23827 
23828         struct
23829         {
23830             __IOM uint16_t PID      : 2; /*!< [1..0] Response PID                                                       */
23831             __IOM uint16_t CCPL     : 1; /*!< [2..2] Control Transfer End Enable                                        */
23832             uint16_t                : 2;
23833             __IM uint16_t  PBUSY    : 1; /*!< [5..5] Pipe Busy                                                          */
23834             __IM uint16_t  SQMON    : 1; /*!< [6..6] Sequence Toggle Bit Monitor                                        */
23835             __IOM uint16_t SQSET    : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
23836             __IOM uint16_t SQCLR    : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
23837             uint16_t                : 2;
23838             __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear                                                  */
23839             uint16_t                : 2;
23840             __IOM uint16_t SUREQ    : 1; /*!< [14..14] Setup Token Transmission                                         */
23841             __IM uint16_t  BSTS     : 1; /*!< [15..15] Buffer Status                                                    */
23842         } DCPCTR_b;
23843     };
23844     __IM uint16_t RESERVED10;
23845 
23846     union
23847     {
23848         __IOM uint16_t PIPESEL;         /*!< (@ 0x00000064) Pipe Window Select Register                                */
23849 
23850         struct
23851         {
23852             __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select                                                 */
23853             uint16_t               : 12;
23854         } PIPESEL_b;
23855     };
23856     __IM uint16_t RESERVED11;
23857 
23858     union
23859     {
23860         __IOM uint16_t PIPECFG;        /*!< (@ 0x00000068) Pipe Configuration Register                                */
23861 
23862         struct
23863         {
23864             __IOM uint16_t EPNUM : 4;  /*!< [3..0] Endpoint NumberThese bits specify the endpoint number
23865                                         *   for the selected pipe.Setting 0000b means unused pipe.                    */
23866             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
23867             uint16_t              : 2;
23868             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
23869             uint16_t              : 1;
23870             __IOM uint16_t DBLB   : 1; /*!< [9..9] Double Buffer Mode                                                 */
23871             __IOM uint16_t BFRE   : 1; /*!< [10..10] BRDY Interrupt Operation Specification                           */
23872             uint16_t              : 3;
23873             __IOM uint16_t TYPE   : 2; /*!< [15..14] Transfer Type                                                    */
23874         } PIPECFG_b;
23875     };
23876     __IM uint16_t RESERVED12;
23877 
23878     union
23879     {
23880         __IOM uint16_t PIPEMAXP;       /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register                          */
23881 
23882         struct
23883         {
23884             __IOM uint16_t MXPS : 9;   /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to
23885                                         *   256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes
23886                                         *   (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and
23887                                         *   [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to
23888                                         *   64 bytes (040h) (Bits [8:7] are not provided.)                            */
23889             uint16_t              : 3;
23890             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
23891         } PIPEMAXP_b;
23892     };
23893 
23894     union
23895     {
23896         __IOM uint16_t PIPEPERI;       /*!< (@ 0x0000006E) Pipe Cycle Control Register                                */
23897 
23898         struct
23899         {
23900             __IOM uint16_t IITV : 3;   /*!< [2..0] Interval Error Detection IntervalSpecifies the interval
23901                                         *   error detection timing for the selected pipe in terms of
23902                                         *   frames, which is expressed as nth power of 2.                             */
23903             uint16_t            : 9;
23904             __IOM uint16_t IFIS : 1;   /*!< [12..12] Isochronous IN Buffer Flush                                      */
23905             uint16_t            : 3;
23906         } PIPEPERI_b;
23907     };
23908 
23909     union
23910     {
23911         __IOM uint16_t PIPE_CTR[9];    /*!< (@ 0x00000070) Pipe [0..8] Control Register                               */
23912 
23913         struct
23914         {
23915             __IOM uint16_t PID    : 2; /*!< [1..0] Response PID                                                       */
23916             uint16_t              : 3;
23917             __IM uint16_t  PBUSY  : 1; /*!< [5..5] Pipe Busy                                                          */
23918             __IM uint16_t  SQMON  : 1; /*!< [6..6] Sequence Toggle Bit Confirmation                                   */
23919             __IOM uint16_t SQSET  : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
23920             __IOM uint16_t SQCLR  : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
23921             __IOM uint16_t ACLRM  : 1; /*!< [9..9] Auto Buffer Clear Mode                                             */
23922             __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode                                               */
23923             uint16_t              : 1;
23924             __IM uint16_t CSSTS   : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
23925                                         *   Split Transaction of the relevant pipe                                    */
23926             __IOM uint16_t CSCLR : 1;  /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
23927                                         *   the CSSTS bit of the relevant pipe                                        */
23928             __IM uint16_t INBUFM : 1;  /*!< [14..14] Transmit Buffer Monitor                                          */
23929             __IM uint16_t BSTS   : 1;  /*!< [15..15] Buffer Status                                                    */
23930         } PIPE_CTR_b[9];
23931     };
23932     __IM uint16_t                RESERVED13;
23933     __IM uint32_t                RESERVED14[3];
23934     __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers                         */
23935     __IM uint32_t                RESERVED15[3];
23936 
23937     union
23938     {
23939         __IOM uint16_t USBBCCTRL0;         /*!< (@ 0x000000B0) BC Control Register 0                                      */
23940 
23941         struct
23942         {
23943             __IOM uint16_t RPDME0     : 1; /*!< [0..0] D- Pin Pull-Down Control                                           */
23944             __IOM uint16_t IDPSRCE0   : 1; /*!< [1..1] D+ Pin IDPSRC Output Control                                       */
23945             __IOM uint16_t IDMSINKE0  : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control         */
23946             __IOM uint16_t VDPSRCE0   : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control                               */
23947             __IOM uint16_t IDPSINKE0  : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control         */
23948             __IOM uint16_t VDMSRCE0   : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control                               */
23949             uint16_t                  : 1;
23950             __IOM uint16_t BATCHGE0   : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control           */
23951             __IM uint16_t  CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status                                */
23952             __IM uint16_t  PDDETSTS0  : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status                                */
23953             uint16_t                  : 6;
23954         } USBBCCTRL0_b;
23955     };
23956     __IM uint16_t RESERVED16;
23957     __IM uint32_t RESERVED17[4];
23958 
23959     union
23960     {
23961         __IOM uint16_t UCKSEL;          /*!< (@ 0x000000C4) USB Clock Selection Register                               */
23962 
23963         struct
23964         {
23965             __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection                                                */
23966             uint16_t               : 15;
23967         } UCKSEL_b;
23968     };
23969     __IM uint16_t RESERVED18;
23970     __IM uint32_t RESERVED19;
23971 
23972     union
23973     {
23974         __IOM uint16_t USBMC;           /*!< (@ 0x000000CC) USB Module Control Register                                */
23975 
23976         struct
23977         {
23978             __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control                  */
23979             uint16_t               : 6;
23980             __IOM uint16_t VDCEN   : 1; /*!< [7..7] USB Regulator On/Off Control                                       */
23981             uint16_t               : 8;
23982         } USBMC_b;
23983     };
23984     __IM uint16_t RESERVED20;
23985 
23986     union
23987     {
23988         __IOM uint16_t DEVADD[10];     /*!< (@ 0x000000D0) Device Address Configuration Register                      */
23989 
23990         struct
23991         {
23992             uint16_t               : 6;
23993             __IOM uint16_t USBSPD  : 2; /*!< [7..6] Transfer Speed of Communication Target Device                      */
23994             __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port                          */
23995             __IOM uint16_t UPPHUB  : 4; /*!< [14..11] Communication Target Connecting Hub Register                     */
23996             uint16_t               : 1;
23997         } DEVADD_b[10];
23998     };
23999     __IM uint32_t RESERVED21[3];
24000 
24001     union
24002     {
24003         __IOM uint32_t PHYSLEW;         /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register                        */
24004 
24005         struct
24006         {
24007             __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00                                 */
24008             __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01                                 */
24009             __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00                                 */
24010             __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01                                 */
24011             uint32_t               : 28;
24012         } PHYSLEW_b;
24013     };
24014     __IM uint32_t RESERVED22[3];
24015 
24016     union
24017     {
24018         __IOM uint16_t LPCTRL;         /*!< (@ 0x00000100) Low Power Control Register                                 */
24019 
24020         struct
24021         {
24022             uint16_t             : 7;
24023             __IOM uint16_t HWUPM : 1;  /*!< [7..7] Resume Return Mode Setting                                         */
24024             uint16_t             : 8;
24025         } LPCTRL_b;
24026     };
24027 
24028     union
24029     {
24030         __IOM uint16_t LPSTS;          /*!< (@ 0x00000102) Low Power Status Register                                  */
24031 
24032         struct
24033         {
24034             uint16_t                : 14;
24035             __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control                                            */
24036             uint16_t                : 1;
24037         } LPSTS_b;
24038     };
24039     __IM uint32_t RESERVED23[15];
24040 
24041     union
24042     {
24043         __IOM uint16_t BCCTRL;           /*!< (@ 0x00000140) Battery Charging Control Register                          */
24044 
24045         struct
24046         {
24047             __IOM uint16_t IDPSRCE  : 1; /*!< [0..0] IDPSRC Control                                                     */
24048             __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control                                                    */
24049             __IOM uint16_t VDPSRCE  : 1; /*!< [2..2] VDPSRC Control                                                     */
24050             __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control                                                    */
24051             __IOM uint16_t VDMSRCE  : 1; /*!< [4..4] VDMSRC Control                                                     */
24052             __IOM uint16_t DCPMODE  : 1; /*!< [5..5] DCP Mode Control                                                   */
24053             uint16_t                : 2;
24054             __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status                                                      */
24055             __IM uint16_t PDDETSTS  : 1; /*!< [9..9] PDDET Status                                                       */
24056             uint16_t                : 6;
24057         } BCCTRL_b;
24058     };
24059     __IM uint16_t RESERVED24;
24060 
24061     union
24062     {
24063         __IOM uint16_t PL1CTRL1;         /*!< (@ 0x00000144) Function L1 Control Register 1                             */
24064 
24065         struct
24066         {
24067             __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable                                                 */
24068             __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode                                                   */
24069             __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
24070                                           *   only when the L1RESPMD[1:0] value is 2'b11.                               */
24071             __IM uint16_t DVSQ : 4;      /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
24072                                           *   the L1 state together with the device state bits DVSQ[2:0].               */
24073             __IOM uint16_t HIRDTHR : 4;  /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
24074                                           *   value used for L1NEGOMD.The format is the same as the HIRD
24075                                           *   field in HL1CTRL.                                                         */
24076             uint16_t               : 2;
24077             __IOM uint16_t L1EXTMD : 1;  /*!< [14..14] PHY Control Mode at L1 Return                                    */
24078             uint16_t               : 1;
24079         } PL1CTRL1_b;
24080     };
24081 
24082     union
24083     {
24084         __IOM uint16_t PL1CTRL2;       /*!< (@ 0x00000146) Function L1 Control Register 2                             */
24085 
24086         struct
24087         {
24088             uint16_t               : 8;
24089             __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor                                                */
24090             __IOM uint16_t RWEMON  : 1; /*!< [12..12] RWE Value Monitor                                                */
24091             uint16_t               : 3;
24092         } PL1CTRL2_b;
24093     };
24094 
24095     union
24096     {
24097         __IOM uint16_t HL1CTRL1;         /*!< (@ 0x00000148) Host L1 Control Register 1                                 */
24098 
24099         struct
24100         {
24101             __IOM uint16_t L1REQ    : 1; /*!< [0..0] L1 Transition Request                                              */
24102             __IM uint16_t  L1STATUS : 2; /*!< [2..1] L1 Request Completion Status                                       */
24103             uint16_t                : 13;
24104         } HL1CTRL1_b;
24105     };
24106 
24107     union
24108     {
24109         __IOM uint16_t HL1CTRL2;       /*!< (@ 0x0000014A) Host L1 Control Register 2                                 */
24110 
24111         struct
24112         {
24113             __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
24114                                         *   be set in the ADDR field of LPM token.                                    */
24115             uint16_t             : 4;
24116             __IOM uint16_t HIRD  : 4;  /*!< [11..8] LPM Token HIRD                                                    */
24117             __IOM uint16_t L1RWE : 1;  /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
24118                                         *   value to be set in the RWE field of LPM token.                            */
24119             uint16_t            : 2;
24120             __IOM uint16_t BESL : 1;   /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
24121                                         *   period at the time of L1 Resume.                                          */
24122         } HL1CTRL2_b;
24123     };
24124     __IM uint32_t RESERVED25[5];
24125 
24126     union
24127     {
24128         __IM uint32_t DPUSR0R;         /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
24129                                         *                  Register                                                   */
24130 
24131         struct
24132         {
24133             uint32_t              : 20;
24134             __IM uint32_t DOVCAHM : 1;  /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
24135                                          *   HS side of USB port.                                                      */
24136             __IM uint32_t DOVCBHM : 1;  /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
24137                                          *   HS side of USB port.                                                      */
24138             uint32_t               : 1;
24139             __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
24140                                          *   of USB port.                                                              */
24141             uint32_t : 8;
24142         } DPUSR0R_b;
24143     };
24144 
24145     union
24146     {
24147         __IOM uint32_t DPUSR1R;        /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register         */
24148 
24149         struct
24150         {
24151             uint32_t                : 4;
24152             __IOM uint32_t DOVCAHE  : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear                                     */
24153             __IOM uint32_t DOVCBHE  : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear                                     */
24154             uint32_t                : 1;
24155             __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear                                        */
24156             uint32_t                : 12;
24157             __IM uint32_t DOVCAH    : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source               */
24158             __IM uint32_t DOVCBH    : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source               */
24159             uint32_t                : 1;
24160             __IM uint32_t DVBSTSH   : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source                  */
24161             uint32_t                : 8;
24162         } DPUSR1R_b;
24163     };
24164 
24165     union
24166     {
24167         __IOM uint16_t DPUSR2R;        /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register         */
24168 
24169         struct
24170         {
24171             __IM uint16_t DPINT : 1;   /*!< [0..0] Indication of Return from DP Interrupt Source                      */
24172             __IM uint16_t DMINT : 1;   /*!< [1..1] Indication of Return from DM Interrupt Source                      */
24173             uint16_t            : 2;
24174             __IM uint16_t DPVAL : 1;   /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
24175                                         *   port.                                                                     */
24176             __IM uint16_t DMVAL : 1;   /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
24177                                         *   port.                                                                     */
24178             uint16_t              : 2;
24179             __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear                                          */
24180             __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear                                          */
24181             uint16_t              : 6;
24182         } DPUSR2R_b;
24183     };
24184 
24185     union
24186     {
24187         __IOM uint16_t DPUSRCR;          /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register           */
24188 
24189         struct
24190         {
24191             __IOM uint16_t FIXPHY   : 1; /*!< [0..0] USB Transceiver Control Fix                                        */
24192             __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL                                */
24193             uint16_t                : 14;
24194         } DPUSRCR_b;
24195     };
24196     __IM uint32_t RESERVED26[165];
24197 
24198     union
24199     {
24200         __IOM uint32_t DPUSR0R_FS;      /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin
24201                                          *                  Monitor Register                                           */
24202 
24203         struct
24204         {
24205             __IOM uint32_t SRPC0   : 1; /*!< [0..0] USB Single End Receiver Control                                    */
24206             __IOM uint32_t RPUE0   : 1; /*!< [1..1] DP Pull-Up Resistor Control                                        */
24207             uint32_t               : 1;
24208             __IOM uint32_t DRPD0   : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control                                   */
24209             __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix                                         */
24210             uint32_t               : 11;
24211             __IM uint32_t DP0      : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB.           */
24212             __IM uint32_t DM0      : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB.             */
24213             uint32_t               : 2;
24214             __IM uint32_t DOVCA0   : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal
24215                                          *   of the USB.                                                               */
24216             __IM uint32_t DOVCB0 : 1;   /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal
24217                                          *   of the USB.                                                               */
24218             uint32_t              : 1;
24219             __IM uint32_t DVBSTS0 : 1;  /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the
24220                                          *   USB.                                                                      */
24221             uint32_t : 8;
24222         } DPUSR0R_FS_b;
24223     };
24224 
24225     union
24226     {
24227         __IOM uint32_t DPUSR1R_FS;        /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt
24228                                            *                  Register                                                   */
24229 
24230         struct
24231         {
24232             __IOM uint32_t DPINTE0   : 1; /*!< [0..0] USB DP Interrupt Enable/Clear                                      */
24233             __IOM uint32_t DMINTE0   : 1; /*!< [1..1] USB DM Interrupt Enable/Clear                                      */
24234             uint32_t                 : 2;
24235             __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear                                 */
24236             __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear                                 */
24237             uint32_t                 : 1;
24238             __IOM uint32_t DVBSE0    : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear                                    */
24239             uint32_t                 : 8;
24240             __IM uint32_t DPINT0     : 1; /*!< [16..16] USB DP Interrupt Source Recovery                                 */
24241             __IM uint32_t DMINT0     : 1; /*!< [17..17] USB DM Interrupt Source Recovery                                 */
24242             uint32_t                 : 2;
24243             __IM uint32_t DOVRCRA0   : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery                            */
24244             __IM uint32_t DOVRCRB0   : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery                            */
24245             uint32_t                 : 1;
24246             __IM uint32_t DVBINT0    : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery                               */
24247             uint32_t                 : 8;
24248         } DPUSR1R_FS_b;
24249     };
24250 } R_USB_FS0_Type;                         /*!< Size = 1032 (0x408)                                                       */
24251 
24252 /* =========================================================================================================================== */
24253 /* ================                                          R_USB_HS0                                          ================ */
24254 /* =========================================================================================================================== */
24255 
24256 /**
24257  * @brief USB 2.0 Module (R_USB_HS0)
24258  */
24259 
24260 typedef struct                         /*!< (@ 0x40090000) R_USB_HS0 Structure                                          */
24261 {
24262     union
24263     {
24264         __IOM uint16_t SYSCFG;         /*!< (@ 0x00000000) System Configuration Control Register                      */
24265 
24266         struct
24267         {
24268             __IOM uint16_t USBE  : 1;  /*!< [0..0] USB Operation Enable                                               */
24269             uint16_t             : 3;
24270             __IOM uint16_t DPRPU : 1;  /*!< [4..4] D+ Line Resistor Control                                           */
24271             __IOM uint16_t DRPD  : 1;  /*!< [5..5] D+/D- Line Resistor Control                                        */
24272             __IOM uint16_t DCFM  : 1;  /*!< [6..6] Controller Function Select                                         */
24273             __IOM uint16_t HSE   : 1;  /*!< [7..7] High-Speed Operation Enable                                          */
24274             __IOM uint16_t CNEN  : 1;  /*!< [8..8] CNEN Single End Receiver Enable                                    */
24275             uint16_t             : 1;
24276             __IOM uint16_t SCKE  : 1;  /*!< [10..10] USB Clock Enable                                                 */
24277         } SYSCFG_b;
24278     };
24279 
24280     union
24281     {
24282         __IOM uint16_t BUSWAIT;        /*!< (@ 0x00000002) CPU Bus Wait Register                                      */
24283 
24284         struct
24285         {
24286             __IOM uint16_t BWAIT : 4;  /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
24287                                         *   access cycles)                                                            */
24288         } BUSWAIT_b;
24289     };
24290 
24291     union
24292     {
24293         __IM uint16_t SYSSTS0;         /*!< (@ 0x00000004) System Configuration Status Register 0                     */
24294 
24295         struct
24296         {
24297             __IM uint16_t LNST  : 2;   /*!< [1..0] USB Data Line Status Monitor                                       */
24298             __IM uint16_t IDMON : 1;   /*!< [2..2] External ID0 Input Pin Monitor                                     */
24299             uint16_t            : 2;
24300             __IM uint16_t SOFEA : 1;   /*!< [5..5] SOF Active Monitor While Host Controller Function is
24301                                         *   Selected.                                                                 */
24302             __IM uint16_t HTACT  : 1;  /*!< [6..6] USB Host Sequencer Status Monitor                                  */
24303             uint16_t             : 7;
24304             __IM uint16_t OVCMON : 2;  /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe
24305                                         *   OCVMON[1] bit indicates the status of the USBHS_OVRCURA
24306                                         *   pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
24307                                         *   pin.                                                                      */
24308         } SYSSTS0_b;
24309     };
24310 
24311     union
24312     {
24313         __IM uint16_t PLLSTA;          /*!< (@ 0x00000006) PLL Status Register                                        */
24314 
24315         struct
24316         {
24317             __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag                                                      */
24318         } PLLSTA_b;
24319     };
24320 
24321     union
24322     {
24323         __IOM uint16_t DVSTCTR0;        /*!< (@ 0x00000008) Device State Control Register 0                            */
24324 
24325         struct
24326         {
24327             __IM uint16_t RHST     : 3; /*!< [2..0] USB Bus Reset Status                                               */
24328             uint16_t               : 1;
24329             __IOM uint16_t UACT    : 1; /*!< [4..4] USB Bus Enable                                                     */
24330             __IOM uint16_t RESUME  : 1; /*!< [5..5] Resume Output                                                      */
24331             __IOM uint16_t USBRST  : 1; /*!< [6..6] USB Bus Reset Output                                               */
24332             __IOM uint16_t RWUPE   : 1; /*!< [7..7] Wakeup Detection Enable                                            */
24333             __IOM uint16_t WKUP    : 1; /*!< [8..8] Wakeup Output                                                      */
24334             __IOM uint16_t VBUSEN  : 1; /*!< [9..9] USB_VBUSEN Output Pin Control                                      */
24335             __IOM uint16_t EXICEN  : 1; /*!< [10..10] USB_EXICEN Output Pin Control                                    */
24336             __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is
24337                                          *   used when switching from device B to device A while in
24338                                          *   OTG mode. If the HNPBTOA bit is 1, the internal function
24339                                          *   control keeps the suspended state until the HNP processing
24340                                          *   ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is
24341                                          *   set.                                                                      */
24342         } DVSTCTR0_b;
24343     };
24344     __IM uint16_t RESERVED;
24345 
24346     union
24347     {
24348         __IOM uint16_t TESTMODE;       /*!< (@ 0x0000000C) USB Test Mode Register                                     */
24349 
24350         struct
24351         {
24352             __IOM uint16_t UTST : 4;   /*!< [3..0] Test Mode                                                          */
24353         } TESTMODE_b;
24354     };
24355     __IM uint16_t RESERVED1;
24356     __IM uint32_t RESERVED2;
24357 
24358     union
24359     {
24360         __IOM uint32_t CFIFO;          /*!< (@ 0x00000014) CFIFO Port Register                                        */
24361 
24362         struct
24363         {
24364             union
24365             {
24366                 __IOM uint16_t CFIFOL;  /*!< (@ 0x00000014) CFIFO Port Register L                                      */
24367                 __IOM uint8_t  CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL                                     */
24368             };
24369 
24370             union
24371             {
24372                 __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H                                      */
24373 
24374                 struct
24375                 {
24376                     __IM uint8_t  RESERVED3;
24377                     __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH                                     */
24378                 };
24379             };
24380         };
24381     };
24382 
24383     union
24384     {
24385         __IOM uint32_t D0FIFO;         /*!< (@ 0x00000018) D0FIFO Port Register                                       */
24386 
24387         struct
24388         {
24389             union
24390             {
24391                 __IOM uint16_t D0FIFOL;  /*!< (@ 0x00000018) D0FIFO Port Register L                                     */
24392                 __IOM uint8_t  D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL                                    */
24393             };
24394 
24395             union
24396             {
24397                 __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H                                     */
24398 
24399                 struct
24400                 {
24401                     __IM uint8_t  RESERVED4;
24402                     __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH                                    */
24403                 };
24404             };
24405         };
24406     };
24407 
24408     union
24409     {
24410         __IOM uint32_t D1FIFO;         /*!< (@ 0x0000001C) D1FIFO Port Register                                       */
24411 
24412         struct
24413         {
24414             union
24415             {
24416                 __IOM uint16_t D1FIFOL;  /*!< (@ 0x0000001C) D1FIFO Port Register L                                     */
24417                 __IOM uint8_t  D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL                                    */
24418             };
24419 
24420             union
24421             {
24422                 __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H                                     */
24423 
24424                 struct
24425                 {
24426                     __IM uint8_t  RESERVED5;
24427                     __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH                                    */
24428                 };
24429             };
24430         };
24431     };
24432 
24433     union
24434     {
24435         __IOM uint16_t CFIFOSEL;        /*!< (@ 0x00000020) CFIFO Port Select Register                                 */
24436 
24437         struct
24438         {
24439             __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification                               */
24440             uint16_t               : 1;
24441             __IOM uint16_t ISEL    : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected                   */
24442             uint16_t               : 2;
24443             __IOM uint16_t BIGEND  : 1; /*!< [8..8] CFIFO Port Endian Control                                          */
24444             uint16_t               : 1;
24445             __IOM uint16_t MBW     : 2; /*!< [11..10] CFIFO Port Access Bit Width                                      */
24446             uint16_t               : 2;
24447             __IOM uint16_t REW     : 1; /*!< [14..14] Buffer Pointer Rewind                                            */
24448             __IOM uint16_t RCNT    : 1; /*!< [15..15] Read Count Mode                                                  */
24449         } CFIFOSEL_b;
24450     };
24451 
24452     union
24453     {
24454         __IOM uint16_t CFIFOCTR;       /*!< (@ 0x00000022) CFIFO Port Control Register                                */
24455 
24456         struct
24457         {
24458             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
24459                                         *   data.                                                                     */
24460             uint16_t            : 1;
24461             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
24462             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
24463             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
24464         } CFIFOCTR_b;
24465     };
24466     __IM uint32_t RESERVED6;
24467 
24468     union
24469     {
24470         __IOM uint16_t D0FIFOSEL;       /*!< (@ 0x00000028) D0FIFO Port Select Register                                */
24471 
24472         struct
24473         {
24474             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
24475             uint16_t               : 4;
24476             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
24477             uint16_t               : 1;
24478             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
24479             __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
24480             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
24481                                          *   Pipe Data is Read                                                         */
24482             __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read.                   */
24483             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
24484         } D0FIFOSEL_b;
24485     };
24486 
24487     union
24488     {
24489         __IOM uint16_t D0FIFOCTR;      /*!< (@ 0x0000002A) D0FIFO Port Control Register                               */
24490 
24491         struct
24492         {
24493             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
24494                                         *   data.                                                                     */
24495             uint16_t            : 1;
24496             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
24497             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
24498             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
24499         } D0FIFOCTR_b;
24500     };
24501 
24502     union
24503     {
24504         __IOM uint16_t D1FIFOSEL;       /*!< (@ 0x0000002C) D1FIFO Port Select Register                                */
24505 
24506         struct
24507         {
24508             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
24509             uint16_t               : 4;
24510             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
24511             uint16_t               : 1;
24512             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
24513             __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
24514             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
24515                                          *   Pipe Data is Read                                                         */
24516             __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
24517             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
24518         } D1FIFOSEL_b;
24519     };
24520 
24521     union
24522     {
24523         __IOM uint16_t D1FIFOCTR;      /*!< (@ 0x0000002E) D1FIFO Port Control Register                               */
24524 
24525         struct
24526         {
24527             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
24528                                         *   data.                                                                     */
24529             uint16_t            : 1;
24530             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
24531             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
24532             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
24533         } D1FIFOCTR_b;
24534     };
24535 
24536     union
24537     {
24538         __IOM uint16_t INTENB0;        /*!< (@ 0x00000030) Interrupt Enable Register 0                                  */
24539 
24540         struct
24541         {
24542             uint16_t             : 8;
24543             __IOM uint16_t BRDYE : 1;  /*!< [8..8] Buffer Ready Interrupt Enable                                      */
24544             __IOM uint16_t NRDYE : 1;  /*!< [9..9] Buffer Not Ready Response Interrupt Enable                         */
24545             __IOM uint16_t BEMPE : 1;  /*!< [10..10] Buffer Empty Interrupt Enable                                    */
24546             __IOM uint16_t CTRE  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Enable               */
24547             __IOM uint16_t DVSE  : 1;  /*!< [12..12] Device State Transition Interrupt Enable                         */
24548             __IOM uint16_t SOFE  : 1;  /*!< [13..13] Frame Number Update Interrupt Enable                             */
24549             __IOM uint16_t RSME  : 1;  /*!< [14..14] Resume Interrupt Enable                                          */
24550             __IOM uint16_t VBSE  : 1;  /*!< [15..15] VBUS Interrupt Enable                                            */
24551         } INTENB0_b;
24552     };
24553 
24554     union
24555     {
24556         __IOM uint16_t INTENB1;            /*!< (@ 0x00000032) Interrupt Enable Register 1                                */
24557 
24558         struct
24559         {
24560             __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable                               */
24561             uint16_t                  : 3;
24562             __IOM uint16_t SACKE      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable                 */
24563             __IOM uint16_t SIGNE      : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable                           */
24564             __IOM uint16_t EOFERRE    : 1; /*!< [6..6] EOF Error Detection Interrupt Enable                               */
24565             uint16_t                  : 1;
24566             __IOM uint16_t LPMENDE    : 1; /*!< [8..8] LPM Transaction End Interrupt Enable                               */
24567             __IOM uint16_t L1RSMENDE  : 1; /*!< [9..9] L1 Resume End Interrupt Enable                                     */
24568             uint16_t                  : 1;
24569             __IOM uint16_t ATTCHE     : 1; /*!< [11..11] Connection Detection Interrupt Enable                            */
24570             __IOM uint16_t DTCHE      : 1; /*!< [12..12] Disconnection Detection Interrupt Enable                         */
24571             uint16_t                  : 1;
24572             __IOM uint16_t BCHGE      : 1; /*!< [14..14] USB Bus Change Interrupt Enable                                  */
24573             __IOM uint16_t OVRCRE     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable                        */
24574         } INTENB1_b;
24575     };
24576     __IM uint16_t RESERVED7;
24577 
24578     union
24579     {
24580         __IOM uint16_t BRDYENB;            /*!< (@ 0x00000036) BRDY Interrupt Enable Register                             */
24581 
24582         struct
24583         {
24584             __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE                                     */
24585             __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE                                     */
24586             __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE                                     */
24587             __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE                                     */
24588             __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE                                     */
24589             __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE                                     */
24590             __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE                                     */
24591             __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE                                     */
24592             __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE                                     */
24593             __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE                                     */
24594         } BRDYENB_b;
24595     };
24596 
24597     union
24598     {
24599         __IOM uint16_t NRDYENB;            /*!< (@ 0x00000038) NRDY Interrupt Enable Register                             */
24600 
24601         struct
24602         {
24603             __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE                                     */
24604             __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE                                     */
24605             __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE                                     */
24606             __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE                                     */
24607             __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE                                     */
24608             __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE                                     */
24609             __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE                                     */
24610             __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE                                     */
24611             __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE                                     */
24612             __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE                                     */
24613         } NRDYENB_b;
24614     };
24615 
24616     union
24617     {
24618         __IOM uint16_t BEMPENB;            /*!< (@ 0x0000003A) BEMP Interrupt Enable Register                             */
24619 
24620         struct
24621         {
24622             __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE                                     */
24623             __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE                                     */
24624             __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE                                     */
24625             __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE                                     */
24626             __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE                                     */
24627             __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE                                     */
24628             __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE                                     */
24629             __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE                                     */
24630             __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE                                     */
24631             __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE                                     */
24632         } BEMPENB_b;
24633     };
24634 
24635     union
24636     {
24637         __IOM uint16_t SOFCFG;         /*!< (@ 0x0000003C) SOF Output Configuration Register                          */
24638 
24639         struct
24640         {
24641             uint16_t                : 4;
24642             __IM uint16_t  EDGESTS  : 1; /*!< [4..4] Edge Interrupt Output Status Monitor                               */
24643             __IOM uint16_t INTL     : 1; /*!< [5..5] Interrupt Output Sense Select                                      */
24644             __IOM uint16_t BRDYM    : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing                                 */
24645             uint16_t                : 1;
24646             __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select                                    */
24647         } SOFCFG_b;
24648     };
24649 
24650     union
24651     {
24652         __IOM uint16_t PHYSET;           /*!< (@ 0x0000003E) PHY Setting Register                                       */
24653 
24654         struct
24655         {
24656             __IOM uint16_t DIRPD    : 1; /*!< [0..0] Power-Down Control                                                 */
24657             __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control                                                  */
24658             uint16_t                : 1;
24659             __IOM uint16_t CDPEN    : 1; /*!< [3..3] Charging Downstream Port Enable                                    */
24660             __IOM uint16_t CLKSEL   : 2; /*!< [5..4] Input System Clock Frequency                                       */
24661             uint16_t                : 2;
24662             __IOM uint16_t REPSEL   : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle                            */
24663             uint16_t                : 1;
24664             __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment                 */
24665             uint16_t                : 3;
24666             __IOM uint16_t HSEB     : 1; /*!< [15..15] CL-Only Mode                                                     */
24667         } PHYSET_b;
24668     };
24669 
24670     union
24671     {
24672         __IOM uint16_t INTSTS0;        /*!< (@ 0x00000040) Interrupt Status Register 0                                */
24673 
24674         struct
24675         {
24676             __IM uint16_t  CTSQ  : 3;  /*!< [2..0] Control Transfer Stage                                             */
24677             __IOM uint16_t VALID : 1;  /*!< [3..3] USB Request Reception                                              */
24678             __IM uint16_t  DVSQ  : 3;  /*!< [6..4] Device State                                                       */
24679             __IM uint16_t  VBSTS : 1;  /*!< [7..7] VBUS Input Status                                                  */
24680             __IM uint16_t  BRDY  : 1;  /*!< [8..8] Buffer Ready Interrupt Status                                      */
24681             __IM uint16_t  NRDY  : 1;  /*!< [9..9] Buffer Not Ready Interrupt Status                                  */
24682             __IM uint16_t  BEMP  : 1;  /*!< [10..10] Buffer Empty Interrupt Status                                    */
24683             __IOM uint16_t CTRT  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Status               */
24684             __IOM uint16_t DVST  : 1;  /*!< [12..12] Device State Transition Interrupt Status                         */
24685             __IOM uint16_t SOFR  : 1;  /*!< [13..13] Frame Number Refresh Interrupt Status                            */
24686             __IOM uint16_t RESM  : 1;  /*!< [14..14] Resume Interrupt Status                                          */
24687             __IOM uint16_t VBINT : 1;  /*!< [15..15] VBUS Interrupt Status                                            */
24688         } INTSTS0_b;
24689     };
24690 
24691     union
24692     {
24693         __IOM uint16_t INTSTS1;           /*!< (@ 0x00000042) Interrupt Status Register 1                                */
24694 
24695         struct
24696         {
24697             __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status                                  */
24698             uint16_t                 : 3;
24699             __IOM uint16_t SACK      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status                 */
24700             __IOM uint16_t SIGN      : 1; /*!< [5..5] Setup Transaction Error Interrupt Status                           */
24701             __IOM uint16_t EOFERR    : 1; /*!< [6..6] EOF Error Detection Interrupt Status                               */
24702             uint16_t                 : 1;
24703             __IOM uint16_t LPMEND    : 1; /*!< [8..8] LPM Transaction End Interrupt Status                               */
24704             __IOM uint16_t L1RSMEND  : 1; /*!< [9..9] L1 Resume End Interrupt Status                                     */
24705             uint16_t                 : 1;
24706             __IOM uint16_t ATTCH     : 1; /*!< [11..11] ATTCH Interrupt Status                                           */
24707             __IOM uint16_t DTCH      : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status                     */
24708             uint16_t                 : 1;
24709             __IOM uint16_t BCHG      : 1; /*!< [14..14] USB Bus Change Interrupt Status                                  */
24710             __IOM uint16_t OVRCR     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status                        */
24711         } INTSTS1_b;
24712     };
24713     __IM uint16_t RESERVED8;
24714 
24715     union
24716     {
24717         __IOM uint16_t BRDYSTS;           /*!< (@ 0x00000046) BRDY Interrupt Status Register                             */
24718 
24719         struct
24720         {
24721             __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE                                     */
24722             __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE                                     */
24723             __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE                                     */
24724             __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE                                     */
24725             __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE                                     */
24726             __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE                                     */
24727             __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE                                     */
24728             __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE                                     */
24729             __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE                                     */
24730             __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE                                     */
24731         } BRDYSTS_b;
24732     };
24733 
24734     union
24735     {
24736         __IOM uint16_t NRDYSTS;           /*!< (@ 0x00000048) NRDY Interrupt Status Register                             */
24737 
24738         struct
24739         {
24740             __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE                                     */
24741             __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE                                     */
24742             __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE                                     */
24743             __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE                                     */
24744             __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE                                     */
24745             __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE                                     */
24746             __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE                                     */
24747             __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE                                     */
24748             __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE                                     */
24749             __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE                                     */
24750         } NRDYSTS_b;
24751     };
24752 
24753     union
24754     {
24755         __IOM uint16_t BEMPSTS;           /*!< (@ 0x0000004A) BEMP Interrupt Status Register                             */
24756 
24757         struct
24758         {
24759             __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE                                     */
24760             __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE                                     */
24761             __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE                                     */
24762             __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE                                     */
24763             __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE                                     */
24764             __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE                                     */
24765             __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE                                     */
24766             __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE                                     */
24767             __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE                                     */
24768             __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE                                     */
24769         } BEMPSTS_b;
24770     };
24771 
24772     union
24773     {
24774         __IOM uint16_t FRMNUM;         /*!< (@ 0x0000004C) Frame Number Register                                      */
24775 
24776         struct
24777         {
24778             __IM uint16_t FRNM  : 11;  /*!< [10..0] Frame NumberLatest frame number                                   */
24779             uint16_t            : 3;
24780             __IOM uint16_t CRCE : 1;   /*!< [14..14] Receive Data Error                                               */
24781             __IOM uint16_t OVRN : 1;   /*!< [15..15] Overrun/Underrun Detection Status                                */
24782         } FRMNUM_b;
24783     };
24784 
24785     union
24786     {
24787         __IOM uint16_t UFRMNUM;        /*!< (@ 0x0000004E) uFrame Number Register                                     */
24788 
24789         struct
24790         {
24791             __IM uint16_t UFRNM  : 3;  /*!< [2..0] MicroframeIndicate the microframe number.                          */
24792             uint16_t             : 12;
24793             __IOM uint16_t DVCHG : 1;  /*!< [15..15] Device State Change                                              */
24794         } UFRMNUM_b;
24795     };
24796 
24797     union
24798     {
24799         __IOM uint16_t USBADDR;           /*!< (@ 0x00000050) USB Address Register                                       */
24800 
24801         struct
24802         {
24803             __IM uint16_t USBADDR : 7;    /*!< [6..0] USB Address In device controller mode, these flags indicate
24804                                            *   the USB address assigned by the host when the USBHS processed
24805                                            *   the SET_ADDRESS request successfully.                                     */
24806             uint16_t                 : 1;
24807             __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery                                                   */
24808         } USBADDR_b;
24809     };
24810     __IM uint16_t RESERVED9;
24811 
24812     union
24813     {
24814         __IOM uint16_t USBREQ;                /*!< (@ 0x00000054) USB Request Type Register                                  */
24815 
24816         struct
24817         {
24818             __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType
24819                                                *   value.                                                                    */
24820             __IOM uint16_t BREQUEST : 8;      /*!< [15..8] RequestThese bits store the USB request bRequest value.           */
24821         } USBREQ_b;
24822     };
24823 
24824     union
24825     {
24826         __IOM uint16_t USBVAL;          /*!< (@ 0x00000056) USB Request Value Register                                 */
24827 
24828         struct
24829         {
24830             __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value.                */
24831         } USBVAL_b;
24832     };
24833 
24834     union
24835     {
24836         __IOM uint16_t USBINDX;         /*!< (@ 0x00000058) USB Request Index Register                                 */
24837 
24838         struct
24839         {
24840             __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value.               */
24841         } USBINDX_b;
24842     };
24843 
24844     union
24845     {
24846         __IOM uint16_t USBLENG;          /*!< (@ 0x0000005A) USB Request Length Register                                */
24847 
24848         struct
24849         {
24850             __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value.             */
24851         } USBLENG_b;
24852     };
24853 
24854     union
24855     {
24856         __IOM uint16_t DCPCFG;         /*!< (@ 0x0000005C) DCP Configuration Register                                 */
24857 
24858         struct
24859         {
24860             uint16_t              : 4;
24861             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
24862             uint16_t              : 2;
24863             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
24864             __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
24865         } DCPCFG_b;
24866     };
24867 
24868     union
24869     {
24870         __IOM uint16_t DCPMAXP;        /*!< (@ 0x0000005E) DCP Maximum Packet Size Register                           */
24871 
24872         struct
24873         {
24874             __IOM uint16_t MXPS : 7;   /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount
24875                                         *   of data (maximum packet size) in payloads for the DCP.                    */
24876             uint16_t              : 5;
24877             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
24878         } DCPMAXP_b;
24879     };
24880 
24881     union
24882     {
24883         __IOM uint16_t DCPCTR;           /*!< (@ 0x00000060) DCP Control Register                                       */
24884 
24885         struct
24886         {
24887             __IOM uint16_t PID      : 2; /*!< [1..0] Response PID                                                       */
24888             __IOM uint16_t CCPL     : 1; /*!< [2..2] Control Transfer End Enable                                        */
24889             uint16_t                : 1;
24890             __IOM uint16_t PINGE    : 1; /*!< [4..4] PING Token Issue Enable                                            */
24891             __IM uint16_t  PBUSY    : 1; /*!< [5..5] Pipe Busy                                                          */
24892             __IM uint16_t  SQMON    : 1; /*!< [6..6] Sequence Toggle Bit Monitor                                        */
24893             __IOM uint16_t SQSET    : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
24894             __IOM uint16_t SQCLR    : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
24895             uint16_t                : 2;
24896             __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear                                                  */
24897             __IM uint16_t  CSSTS    : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status                                                  */
24898             __IOM uint16_t CSCLR    : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear                                                  */
24899             __IOM uint16_t SUREQ    : 1; /*!< [14..14] Setup Token Transmission                                         */
24900             __IM uint16_t  BSTS     : 1; /*!< [15..15] Buffer Status                                                    */
24901         } DCPCTR_b;
24902     };
24903     __IM uint16_t RESERVED10;
24904 
24905     union
24906     {
24907         __IOM uint16_t PIPESEL;         /*!< (@ 0x00000064) Pipe Window Select Register                                */
24908 
24909         struct
24910         {
24911             __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select                                                 */
24912         } PIPESEL_b;
24913     };
24914     __IM uint16_t RESERVED11;
24915 
24916     union
24917     {
24918         __IOM uint16_t PIPECFG;        /*!< (@ 0x00000068) Pipe Configuration Register                                */
24919 
24920         struct
24921         {
24922             __IOM uint16_t EPNUM : 4;  /*!< [3..0] Endpoint NumberThese bits specify the endpoint number
24923                                         *   for the selected pipe.Setting 0000b means unused pipe.                    */
24924             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
24925             uint16_t              : 2;
24926             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
24927             __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                   */
24928             __IOM uint16_t DBLB   : 1; /*!< [9..9] Double Buffer Mode                                                 */
24929             __IOM uint16_t BFRE   : 1; /*!< [10..10] BRDY Interrupt Operation Specification                           */
24930             uint16_t              : 3;
24931             __IOM uint16_t TYPE   : 2; /*!< [15..14] Transfer Type                                                    */
24932         } PIPECFG_b;
24933     };
24934 
24935     union
24936     {
24937         __IOM uint16_t PIPEBUF;          /*!< (@ 0x0000006A)Pipe Buffer Register                                         */
24938 
24939         struct
24940         {
24941             __IOM uint16_t BUFNMB :  8;  /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number of the
24942                                           *   selected pipe (04h to 87h).                                         */
24943             uint16_t               :  2;
24944             __IOM uint16_t BUFSIZE :  5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes   */
24945         } PIPEBUF_b;                     /*!< BitSize                                                             */
24946     };
24947 
24948     union
24949     {
24950         __IOM uint16_t PIPEMAXP;       /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register                          */
24951 
24952         struct
24953         {
24954             __IOM uint16_t MXPS : 11;  /*!< [10..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to
24955                                         *   1024 bytes (400h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes
24956                                         *   (010h), 32 bytes (020h), 64 bytes (040h),512bytes(200h) ([2:0] are not
24957                                         *   provided.)PIPE6 to PIPE9: 1 byte (001h) to
24958                                         *   64 bytes (040h) (Bits [10:7] are not provided.)                      */
24959             uint16_t              : 1;
24960             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
24961         } PIPEMAXP_b;
24962     };
24963 
24964     union
24965     {
24966         __IOM uint16_t PIPEPERI;       /*!< (@ 0x0000006E) Pipe Cycle Control Register                                */
24967 
24968         struct
24969         {
24970             __IOM uint16_t IITV : 3;   /*!< [2..0] Interval Error Detection IntervalSpecifies the interval
24971                                         *   error detection timing for the selected pipe in terms of
24972                                         *   frames, which is expressed as nth power of 2.                             */
24973             uint16_t            : 9;
24974             __IOM uint16_t IFIS : 1;   /*!< [12..12] Isochronous IN Buffer Flush                                      */
24975         } PIPEPERI_b;
24976     };
24977 
24978     union
24979     {
24980         __IOM uint16_t PIPE_CTR[9];    /*!< (@ 0x00000070) Pipe [0..8] Control Register                               */
24981 
24982         struct
24983         {
24984             __IOM uint16_t PID    : 2; /*!< [1..0] Response PID                                                       */
24985             uint16_t              : 3;
24986             __IM uint16_t  PBUSY  : 1; /*!< [5..5] Pipe Busy                                                          */
24987             __IM uint16_t  SQMON  : 1; /*!< [6..6] Sequence Toggle Bit Confirmation                                   */
24988             __IOM uint16_t SQSET  : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
24989             __IOM uint16_t SQCLR  : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
24990             __IOM uint16_t ACLRM  : 1; /*!< [9..9] Auto Buffer Clear Mode                                             */
24991             __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode                                               */
24992             uint16_t              : 1;
24993             __IM uint16_t CSSTS   : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
24994                                         *   Split Transaction of the relevant pipe                                    */
24995             __IOM uint16_t CSCLR : 1;  /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
24996                                         *   the CSSTS bit of the relevant pipe                                        */
24997             __IM uint16_t INBUFM : 1;  /*!< [14..14] Transmit Buffer Monitor                                          */
24998             __IM uint16_t BSTS   : 1;  /*!< [15..15] Buffer Status                                                    */
24999         } PIPE_CTR_b[9];
25000     };
25001     __IM uint16_t                RESERVED13;
25002     __IM uint32_t                RESERVED14[3];
25003     __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers                         */
25004     __IM uint32_t                RESERVED15[11];
25005 
25006     union
25007     {
25008         __IOM uint16_t DEVADD[10];     /*!< (@ 0x000000D0) Device Address Configuration Register                      */
25009 
25010         struct
25011         {
25012             uint16_t               : 6;
25013             __IOM uint16_t USBSPD  : 2; /*!< [7..6] Transfer Speed of Communication Target Device                      */
25014             __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port                          */
25015             __IOM uint16_t UPPHUB  : 4; /*!< [14..11] Communication Target Connecting Hub Register                     */
25016         } DEVADD_b[10];
25017     };
25018     __IM uint16_t RESERVED16;
25019     __IM uint32_t RESERVED17[6];
25020 
25021     union
25022     {
25023         __IOM uint16_t LPCTRL;         /*!< (@ 0x00000100) Low Power Control Register                                 */
25024 
25025         struct
25026         {
25027             uint16_t             : 7;
25028             __IOM uint16_t HWUPM : 1;  /*!< [7..7] Resume Return Mode Setting                                         */
25029         } LPCTRL_b;
25030     };
25031 
25032     union
25033     {
25034         __IOM uint16_t LPSTS;          /*!< (@ 0x00000102) Low Power Status Register                                  */
25035 
25036         struct
25037         {
25038             uint16_t                : 14;
25039             __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control                                            */
25040         } LPSTS_b;
25041     };
25042     __IM uint32_t RESERVED18[15];
25043 
25044     union
25045     {
25046         __IOM uint16_t BCCTRL;           /*!< (@ 0x00000140) Battery Charging Control Register                          */
25047 
25048         struct
25049         {
25050             __IOM uint16_t IDPSRCE  : 1; /*!< [0..0] IDPSRC Control                                                     */
25051             __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control                                                    */
25052             __IOM uint16_t VDPSRCE  : 1; /*!< [2..2] VDPSRC Control                                                     */
25053             __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control                                                    */
25054             __IOM uint16_t VDMSRCE  : 1; /*!< [4..4] VDMSRC Control                                                     */
25055             __IOM uint16_t DCPMODE  : 1; /*!< [5..5] DCP Mode Control                                                   */
25056             uint16_t                : 2;
25057             __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status                                                      */
25058             __IM uint16_t PDDETSTS  : 1; /*!< [9..9] PDDET Status                                                       */
25059         } BCCTRL_b;
25060     };
25061     __IM uint16_t RESERVED19;
25062 
25063     union
25064     {
25065         __IOM uint16_t PL1CTRL1;         /*!< (@ 0x00000144) Function L1 Control Register 1                             */
25066 
25067         struct
25068         {
25069             __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable                                                 */
25070             __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode                                                   */
25071             __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
25072                                           *   only when the L1RESPMD[1:0] value is 2'b11.                               */
25073             __IM uint16_t DVSQ : 4;      /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
25074                                           *   the L1 state together with the device state bits DVSQ[2:0].               */
25075             __IOM uint16_t HIRDTHR : 4;  /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
25076                                           *   value used for L1NEGOMD.The format is the same as the HIRD
25077                                           *   field in HL1CTRL.                                                         */
25078             uint16_t               : 2;
25079             __IOM uint16_t L1EXTMD : 1;  /*!< [14..14] PHY Control Mode at L1 Return                                    */
25080         } PL1CTRL1_b;
25081     };
25082 
25083     union
25084     {
25085         __IOM uint16_t PL1CTRL2;       /*!< (@ 0x00000146) Function L1 Control Register 2                             */
25086 
25087         struct
25088         {
25089             uint16_t               : 8;
25090             __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor                                                */
25091             __IOM uint16_t RWEMON  : 1; /*!< [12..12] RWE Value Monitor                                                */
25092         } PL1CTRL2_b;
25093     };
25094 
25095     union
25096     {
25097         __IOM uint16_t HL1CTRL1;         /*!< (@ 0x00000148) Host L1 Control Register 1                                 */
25098 
25099         struct
25100         {
25101             __IOM uint16_t L1REQ    : 1; /*!< [0..0] L1 Transition Request                                              */
25102             __IM uint16_t  L1STATUS : 2; /*!< [2..1] L1 Request Completion Status                                       */
25103         } HL1CTRL1_b;
25104     };
25105 
25106     union
25107     {
25108         __IOM uint16_t HL1CTRL2;       /*!< (@ 0x0000014A) Host L1 Control Register 2                                 */
25109 
25110         struct
25111         {
25112             __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
25113                                         *   be set in the ADDR field of LPM token.                                    */
25114             uint16_t             : 4;
25115             __IOM uint16_t HIRD  : 4;  /*!< [11..8] LPM Token HIRD                                                    */
25116             __IOM uint16_t L1RWE : 1;  /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
25117                                         *   value to be set in the RWE field of LPM token.                            */
25118             uint16_t            : 2;
25119             __IOM uint16_t BESL : 1;   /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
25120                                         *   period at the time of L1 Resume.                                          */
25121         } HL1CTRL2_b;
25122     };
25123     __IM uint32_t RESERVED20;
25124 
25125     union
25126     {
25127         __IOM uint16_t PHYTRIM1;           /*!< (@ 0x00000150)PHY Timing Register 1                                                 */
25128 
25129         struct
25130         {
25131             __IOM uint16_t DRISE     :  2; /*!< [1..0]FS/LS Rising-Edge Output Waveform Adjustment Function                 */
25132             __IOM uint16_t DFALL     :  2; /*!< [3..2]FS/LS Falling-Edge Output Waveform Adjustment Function                */
25133             uint16_t                 :  3;
25134             __IOM uint16_t PCOMPENB  :  1; /*!< [7..7]PVDD Start-up Detection                                               */
25135             __IOM uint16_t HSIUP     :  4; /*!< [11..8]HS Output Level Setting                                               */
25136             __IOM uint16_t IMPOFFSET :  3; /*!< [14..12]terminating resistance offset value setting.Offset value for
25137                                             * adjusting the terminating resistance.                                 */
25138         } PHYTRIM1_b;                      /*!< BitSize                                                               */
25139     };
25140 
25141     union
25142     {
25143         __IOM uint16_t PHYTRIM2;          /*!< (@ 0x00000152)PHY Timing Register 2                                                 */
25144 
25145         struct
25146         {
25147             __IOM uint16_t SQU      :  4; /*!< [3..0]Squelch Detection Level                                               */
25148             uint16_t                :  3;
25149             __IOM uint16_t HSRXENMO :  1; /*!< [7..7]HS Receive Enable Control Mode                                        */
25150             __IOM uint16_t PDR      :  2; /*!< [9..8]HS Output Adjustment Function                                         */
25151             uint16_t                :  2;
25152             __IOM uint16_t DIS      :  3; /*!< [14..12]Disconnect Detection Level                                            */
25153         } PHYTRIM2_b;                     /*!< BitSize                                                               */
25154     };
25155     __IM uint32_t RESERVED21[3];
25156 
25157     union
25158     {
25159         __IM uint32_t DPUSR0R;         /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
25160                                         *                  Register                                                   */
25161 
25162         struct
25163         {
25164             uint32_t              : 20;
25165             __IM uint32_t DOVCAHM : 1;  /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
25166                                          *   HS side of USB port.                                                      */
25167             __IM uint32_t DOVCBHM : 1;  /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
25168                                          *   HS side of USB port.                                                      */
25169             uint32_t               : 1;
25170             __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
25171                                          *   of USB port.                                                              */
25172         } DPUSR0R_b;
25173     };
25174 
25175     union
25176     {
25177         __IOM uint32_t DPUSR1R;        /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register         */
25178 
25179         struct
25180         {
25181             uint32_t                : 4;
25182             __IOM uint32_t DOVCAHE  : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear                                     */
25183             __IOM uint32_t DOVCBHE  : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear                                     */
25184             uint32_t                : 1;
25185             __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear                                        */
25186             uint32_t                : 12;
25187             __IM uint32_t DOVCAH    : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source               */
25188             __IM uint32_t DOVCBH    : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source               */
25189             uint32_t                : 1;
25190             __IM uint32_t DVBSTSH   : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source                  */
25191         } DPUSR1R_b;
25192     };
25193 
25194     union
25195     {
25196         __IOM uint16_t DPUSR2R;        /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register         */
25197 
25198         struct
25199         {
25200             __IM uint16_t DPINT : 1;   /*!< [0..0] Indication of Return from DP Interrupt Source                      */
25201             __IM uint16_t DMINT : 1;   /*!< [1..1] Indication of Return from DM Interrupt Source                      */
25202             uint16_t            : 2;
25203             __IM uint16_t DPVAL : 1;   /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
25204                                         *   port.                                                                     */
25205             __IM uint16_t DMVAL : 1;   /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
25206                                         *   port.                                                                     */
25207             uint16_t              : 2;
25208             __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear                                          */
25209             __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear                                          */
25210         } DPUSR2R_b;
25211     };
25212 
25213     union
25214     {
25215         __IOM uint16_t DPUSRCR;          /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register           */
25216 
25217         struct
25218         {
25219             __IOM uint16_t FIXPHY   : 1; /*!< [0..0] USB Transceiver Control Fix                                        */
25220             __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL                                */
25221         } DPUSRCR_b;
25222     };
25223 } R_USB_HS0_Type;                        /*!< Size = 1032 (0x408)                                                       */
25224 
25225 /* =========================================================================================================================== */
25226 /* ================                                           R_WDT                                           ================ */
25227 /* =========================================================================================================================== */
25228 
25229 /**
25230  * @brief Watchdog Timer (R_WDT)
25231  */
25232 
25233 typedef struct                         /*!< (@ 0x40044200) R_WDT Structure                                            */
25234 {
25235     union
25236     {
25237         __IOM uint8_t WDTRR;           /*!< (@ 0x00000000) WDT Refresh Register                                       */
25238 
25239         struct
25240         {
25241             __IOM uint8_t WDTRR : 8;   /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter
25242                                         *   of the WDT.                                                               */
25243         } WDTRR_b;
25244     };
25245     __IM uint8_t RESERVED;
25246 
25247     union
25248     {
25249         __IOM uint16_t WDTCR;          /*!< (@ 0x00000002) WDT Control Register                                       */
25250 
25251         struct
25252         {
25253             __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
25254             uint16_t            : 2;
25255             __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
25256             __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
25257             uint16_t            : 2;
25258             __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
25259             uint16_t            : 2;
25260         } WDTCR_b;
25261     };
25262 
25263     union
25264     {
25265         __IOM uint16_t WDTSR;           /*!< (@ 0x00000004) WDT Status Register                                        */
25266 
25267         struct
25268         {
25269             __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
25270             __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
25271             __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
25272         } WDTSR_b;
25273     };
25274 
25275     union
25276     {
25277         __IOM uint8_t WDTRCR;          /*!< (@ 0x00000006) WDT Reset Control Register                                 */
25278 
25279         struct
25280         {
25281             uint8_t               : 7;
25282             __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
25283         } WDTRCR_b;
25284     };
25285     __IM uint8_t RESERVED1;
25286 
25287     union
25288     {
25289         __IOM uint8_t WDTCSTPR;        /*!< (@ 0x00000008) WDT Count Stop Control Register                            */
25290 
25291         struct
25292         {
25293             uint8_t              : 7;
25294             __IOM uint8_t SLCSTP : 1;  /*!< [7..7] Sleep-Mode Count Stop Control                                      */
25295         } WDTCSTPR_b;
25296     };
25297     __IM uint8_t  RESERVED2;
25298     __IM uint16_t RESERVED3;
25299 } R_WDT_Type;                          /*!< Size = 12 (0xc)                                                           */
25300 
25301 /* =========================================================================================================================== */
25302 /* ================                                           R_TZF                                           ================ */
25303 /* =========================================================================================================================== */
25304 
25305 /**
25306  * @brief TrustZone Filter (R_TZF)
25307  */
25308 
25309 typedef struct                         /*!< (@ 0x40000E00) R_TZF Structure                                            */
25310 {
25311     union
25312     {
25313         __IOM uint16_t TZFOAD;         /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register        */
25314 
25315         struct
25316         {
25317             __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
25318             uint16_t           : 7;
25319             __OM uint16_t KEY  : 8;    /*!< [15..8] KeyCode                                                           */
25320         } TZFOAD_b;
25321     };
25322     __IM uint16_t RESERVED;
25323 
25324     union
25325     {
25326         __IOM uint16_t TZFPT;           /*!< (@ 0x00000004) TrustZone Filter Protect Register                          */
25327 
25328         struct
25329         {
25330             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
25331             uint16_t               : 7;
25332             __OM uint16_t KEY      : 8; /*!< [15..8] KeyCode                                                           */
25333         } TZFPT_b;
25334     };
25335     __IM uint16_t RESERVED1;
25336     __IM uint32_t RESERVED2[94];
25337 
25338     union
25339     {
25340         __IOM uint32_t TZFSAR;         /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register             */
25341 
25342         struct
25343         {
25344             __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter              */
25345             uint32_t              : 31;
25346         } TZFSAR_b;
25347     };
25348 } R_TZF_Type;                          /*!< Size = 388 (0x184)                                                        */
25349 
25350 /* =========================================================================================================================== */
25351 /* ================                                          R_CACHE                                          ================ */
25352 /* =========================================================================================================================== */
25353 
25354 /**
25355  * @brief R_CACHE (R_CACHE)
25356  */
25357 
25358 typedef struct                         /*!< (@ 0x40007000) R_CACHE Structure                                          */
25359 {
25360     union
25361     {
25362         __IOM uint32_t CCACTL;         /*!< (@ 0x00000000) C-Cache Control Register                                   */
25363 
25364         struct
25365         {
25366             __IOM uint32_t ENC : 1;    /*!< [0..0] C-Cache Enable                                                     */
25367             uint32_t           : 31;
25368         } CCACTL_b;
25369     };
25370 
25371     union
25372     {
25373         __IOM uint32_t CCAFCT;         /*!< (@ 0x00000004) C-Cache Flush Control Register                             */
25374 
25375         struct
25376         {
25377             __IOM uint32_t FC : 1;     /*!< [0..0] C-Cache Flush                                                      */
25378             uint32_t          : 31;
25379         } CCAFCT_b;
25380     };
25381 
25382     union
25383     {
25384         __IOM uint32_t CCALCF;         /*!< (@ 0x00000008) C-Cache Line Configuration Register                        */
25385 
25386         struct
25387         {
25388             __IOM uint32_t CC : 2;     /*!< [1..0] C-Cache Line Size                                                  */
25389             uint32_t          : 30;
25390         } CCALCF_b;
25391     };
25392     __IM uint32_t RESERVED[13];
25393 
25394     union
25395     {
25396         __IOM uint32_t SCACTL;         /*!< (@ 0x00000040) S-Cache Control Register                                   */
25397 
25398         struct
25399         {
25400             __IOM uint32_t ENS : 1;    /*!< [0..0] S-Cache Enable                                                     */
25401             uint32_t           : 31;
25402         } SCACTL_b;
25403     };
25404 
25405     union
25406     {
25407         __IOM uint32_t SCAFCT;         /*!< (@ 0x00000044) S-Cache Flush Control Register                             */
25408 
25409         struct
25410         {
25411             __IOM uint32_t FS : 1;     /*!< [0..0] S-Cache Flush                                                      */
25412             uint32_t          : 31;
25413         } SCAFCT_b;
25414     };
25415 
25416     union
25417     {
25418         __IOM uint32_t SCALCF;         /*!< (@ 0x00000048) S-Cache Line Configuration Register                        */
25419 
25420         struct
25421         {
25422             __IOM uint32_t CS : 2;     /*!< [1..0] S-Cache Line Size                                                  */
25423             uint32_t          : 30;
25424         } SCALCF_b;
25425     };
25426     __IM uint32_t RESERVED1[109];
25427 
25428     union
25429     {
25430         __IOM uint32_t CAPOAD;         /*!< (@ 0x00000200) Cache Parity Error Operation After Detection
25431                                         *                  Register                                                   */
25432 
25433         struct
25434         {
25435             __IOM uint32_t OAD : 1;    /*!< [0..0] Operation after Detection                                          */
25436             uint32_t           : 31;
25437         } CAPOAD_b;
25438     };
25439 
25440     union
25441     {
25442         __IOM uint32_t CAPRCR;         /*!< (@ 0x00000204) Cache Protection Register                                  */
25443 
25444         struct
25445         {
25446             __IOM uint32_t PRCR : 1;   /*!< [0..0] Register Write Control                                             */
25447             __IOM uint32_t KW   : 7;   /*!< [7..1] Write key code                                                     */
25448             uint32_t            : 24;
25449         } CAPRCR_b;
25450     };
25451 } R_CACHE_Type;                        /*!< Size = 520 (0x208)                                                        */
25452 
25453 /* =========================================================================================================================== */
25454 /* ================                                          R_CPSCU                                          ================ */
25455 /* =========================================================================================================================== */
25456 
25457 /**
25458  * @brief CPU System Security Control Unit (R_CPSCU)
25459  */
25460 
25461 typedef struct                           /*!< (@ 0x40008000) R_CPSCU Structure                                          */
25462 {
25463     union
25464     {
25465         __IOM uint32_t CSAR;             /*!< (@ 0x00000000) Cache Security Attribution Register                        */
25466 
25467         struct
25468         {
25469             __IOM uint32_t CACHESA  : 1; /*!< [0..0] Security Attributes of Registers for Cache Control                 */
25470             __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration      */
25471             __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error                   */
25472             uint32_t                : 29;
25473         } CSAR_b;
25474     };
25475     __IM uint32_t RESERVED[3];
25476 
25477     union
25478     {
25479         __IOM uint32_t SRAMSAR;         /*!< (@ 0x00000010) SRAM Security Attribution Register                         */
25480 
25481         struct
25482         {
25483             __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection               */
25484             __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection
25485                                          *   2                                                                         */
25486             __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation                  */
25487             uint32_t               : 29;
25488         } SRAMSAR_b;
25489     };
25490 
25491     union
25492     {
25493         __IOM uint32_t STBRAMSAR;       /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register           */
25494 
25495         struct
25496         {
25497             __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM                 */
25498             uint32_t               : 28;
25499         } STBRAMSAR_b;
25500     };
25501     __IM uint32_t RESERVED1[6];
25502 
25503     union
25504     {
25505         __IOM uint32_t DTCSAR;          /*!< (@ 0x00000030) DTC Controller Security Attribution Register               */
25506 
25507         struct
25508         {
25509             __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution                                           */
25510             uint32_t               : 31;
25511         } DTCSAR_b;
25512     };
25513 
25514     union
25515     {
25516         __IOM uint32_t DMACSAR;         /*!< (@ 0x00000034) DMAC Controller Security Attribution Register              */
25517 
25518         struct
25519         {
25520             __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution                                         */
25521             uint32_t               : 31;
25522         } DMACSAR_b;
25523     };
25524     __IM uint32_t RESERVED2[2];
25525 
25526     union
25527     {
25528         __IOM uint32_t ICUSARA;           /*!< (@ 0x00000040) ICU Security Attribution Register A                        */
25529 
25530         struct
25531         {
25532             __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers         */
25533             uint32_t                : 16;
25534         } ICUSARA_b;
25535     };
25536 
25537     union
25538     {
25539         __IOM uint32_t ICUSARB;        /*!< (@ 0x00000044) ICU Security Attribution Register B                        */
25540 
25541         struct
25542         {
25543             __IOM uint32_t SANMI : 1;  /*!< [0..0] Security Attributes of nonmaskable interrupt                       */
25544             uint32_t             : 31;
25545         } ICUSARB_b;
25546     };
25547 
25548     union
25549     {
25550         __IOM uint32_t ICUSARC;         /*!< (@ 0x00000048) ICU Security Attribution Register C                        */
25551 
25552         struct
25553         {
25554             __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel                  */
25555             uint32_t               : 24;
25556         } ICUSARC_b;
25557     };
25558 
25559     union
25560     {
25561         __IOM uint32_t ICUSARD;          /*!< (@ 0x0000004C) ICU Security Attribution Register D                        */
25562 
25563         struct
25564         {
25565             __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0                        */
25566             uint32_t                : 31;
25567         } ICUSARD_b;
25568     };
25569 
25570     union
25571     {
25572         __IOM uint32_t ICUSARE;        /*!< (@ 0x00000050) ICU Security Attribution Register E                        */
25573 
25574         struct
25575         {
25576             uint32_t                   : 16;
25577             __IOM uint32_t SAIWDTWUP   : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16                 */
25578             uint32_t                   : 1;
25579             __IOM uint32_t SALVD1WUP   : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18                 */
25580             __IOM uint32_t SALVD2WUP   : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19                 */
25581             uint32_t                   : 4;
25582             __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24                 */
25583             __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25                 */
25584             uint32_t                   : 1;
25585             __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27                 */
25586             __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28                 */
25587             __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29                 */
25588             __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30                 */
25589             __IOM uint32_t SAIIC0WUP   : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31                 */
25590         } ICUSARE_b;
25591     };
25592 
25593     union
25594     {
25595         __IOM uint32_t ICUSARF;             /*!< (@ 0x00000054) ICU Security Attribution Register F                        */
25596 
25597         struct
25598         {
25599             __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0                    */
25600             __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1                    */
25601             __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2                    */
25602             uint32_t                   : 29;
25603         } ICUSARF_b;
25604     };
25605     __IM uint32_t RESERVED3[6];
25606 
25607     union
25608     {
25609         __IOM uint32_t ICUSARG;           /*!< (@ 0x00000070) ICU Security Attribution Register G                        */
25610 
25611         struct
25612         {
25613             __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0            */
25614         } ICUSARG_b;
25615     };
25616 
25617     union
25618     {
25619         __IOM uint32_t ICUSARH;           /*!< (@ 0x00000074) ICU Security Attribution Register H                        */
25620 
25621         struct
25622         {
25623             __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32           */
25624         } ICUSARH_b;
25625     };
25626 
25627     union
25628     {
25629         __IOM uint32_t ICUSARI;           /*!< (@ 0x00000078) ICU Security Attribution Register I                        */
25630 
25631         struct
25632         {
25633             __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64           */
25634         } ICUSARI_b;
25635     };
25636     __IM uint32_t RESERVED4[33];
25637 
25638     union
25639     {
25640         __IOM uint32_t BUSSARA;        /*!< (@ 0x00000100) Bus Security Attribution Register A                        */
25641 
25642         struct
25643         {
25644             __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0                                        */
25645             uint32_t              : 31;
25646         } BUSSARA_b;
25647     };
25648 
25649     union
25650     {
25651         __IOM uint32_t BUSSARB;        /*!< (@ 0x00000104) Bus Security Attribution Register B                        */
25652 
25653         struct
25654         {
25655             __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0                                        */
25656             uint32_t              : 31;
25657         } BUSSARB_b;
25658     };
25659     __IM uint32_t RESERVED5[10];
25660 
25661     union
25662     {
25663         __IOM uint32_t MMPUSARA;         /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution
25664                                           *                  Register A                                                 */
25665 
25666         struct
25667         {
25668             __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7)                           */
25669             uint32_t                : 24;
25670         } MMPUSARA_b;
25671     };
25672 
25673     union
25674     {
25675         __IOM uint32_t MMPUSARB;         /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution
25676                                           *                  Register B                                                 */
25677 
25678         struct
25679         {
25680             __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution                                        */
25681             uint32_t                : 31;
25682         } MMPUSARB_b;
25683     };
25684     __IM uint32_t RESERVED6[30];
25685 
25686     union
25687     {
25688         __IOM uint32_t CPUDSAR;         /*!< (@ 0x000001B0) CPU Debug Security Attribution Register                    */
25689 
25690         struct
25691         {
25692             __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0                                   */
25693             uint32_t               : 31;
25694         } CPUDSAR_b;
25695     };
25696 } R_CPSCU_Type;                         /*!< Size = 436 (0x1b4)                                                        */
25697 
25698 /* =========================================================================================================================== */
25699 /* ================                                           R_CEC                                           ================ */
25700 /* =========================================================================================================================== */
25701 
25702 /**
25703  * @brief Consumer Electronics Control (R_CEC)
25704  */
25705 
25706 typedef struct                         /*!< (@ 0x400AC000) R_CEC Structure                                            */
25707 {
25708     union
25709     {
25710         __IOM uint16_t CADR;           /*!< (@ 0x00000000) CEC Local Address Setting Register                         */
25711 
25712         struct
25713         {
25714             __IOM uint16_t ADR00 : 1;  /*!< [0..0] Local Address at Address 0 (TV)                                    */
25715             __IOM uint16_t ADR01 : 1;  /*!< [1..1] Local Address Setting at Address 1 (recording device
25716                                         *   1)                                                                        */
25717             __IOM uint16_t ADR02 : 1;  /*!< [2..2] Local Address Setting at Address 2 (recording device
25718                                         *   2)                                                                        */
25719             __IOM uint16_t ADR03 : 1;  /*!< [3..3] Local Address Setting at Address 3 (tuner 1)                       */
25720             __IOM uint16_t ADR04 : 1;  /*!< [4..4] Local Address Setting at Address 4 (playback device 1)             */
25721             __IOM uint16_t ADR05 : 1;  /*!< [5..5] Local Address Setting at Address 5 (audio system)                  */
25722             __IOM uint16_t ADR06 : 1;  /*!< [6..6] Local Address Setting at Address 6 (tuner 2)                       */
25723             __IOM uint16_t ADR07 : 1;  /*!< [7..7] Local Address Setting at Address 7 (tuner 3)                       */
25724             __IOM uint16_t ADR08 : 1;  /*!< [8..8] Local Address Setting at Address 8 (playback device 2)             */
25725             __IOM uint16_t ADR09 : 1;  /*!< [9..9] Local Address Setting at Address 9 (recording device
25726                                         *   3)                                                                        */
25727             __IOM uint16_t ADR10 : 1;  /*!< [10..10] Local Address Setting at Address 10 (tuner 4)                    */
25728             __IOM uint16_t ADR11 : 1;  /*!< [11..11] Local Address Setting at Address 11 (playback device
25729                                         *   3)                                                                        */
25730             __IOM uint16_t ADR12 : 1;  /*!< [12..12] Local Address Setting at Address 12 (reserved)                   */
25731             __IOM uint16_t ADR13 : 1;  /*!< [13..13] Local Address Setting at Address 13 (reserved)                   */
25732             __IOM uint16_t ADR14 : 1;  /*!< [14..14] Local Address Setting at Address 14 (specific use)               */
25733             uint16_t             : 1;
25734         } CADR_b;
25735     };
25736 
25737     union
25738     {
25739         __IOM uint8_t CECCTL1;         /*!< (@ 0x00000002) CEC Control Register 1                                     */
25740 
25741         struct
25742         {
25743             __IOM uint8_t SFT   : 2;   /*!< [1..0] Signal-Free Time Data Bit Width Select                             */
25744             __IOM uint8_t CESEL : 2;   /*!< [3..2] Communication Complete Interrupt (INTCE) Generation Timing
25745                                         *   Select                                                                    */
25746             __IOM uint8_t STERRD : 1;  /*!< [4..4] Start Bit Error Detection Select                                   */
25747             __IOM uint8_t BLERRD : 1;  /*!< [5..5] Bus Lock Detection Select                                          */
25748             __IOM uint8_t CINTMK : 1;  /*!< [6..6] CEC Data Interrupt (INTDA) Generation Select                       */
25749             __IOM uint8_t CDFC   : 1;  /*!< [7..7] Digital Filter Select                                              */
25750         } CECCTL1_b;
25751     };
25752     __IM uint8_t RESERVED;
25753 
25754     union
25755     {
25756         __IOM uint16_t STATB;          /*!< (@ 0x00000004) CEC Transmission Start Bit Width Setting Register          */
25757 
25758         struct
25759         {
25760             __IOM uint16_t STATB : 9;  /*!< [8..0] CEC Transmission Start Bit Width Setting                           */
25761             uint16_t             : 7;
25762         } STATB_b;
25763     };
25764 
25765     union
25766     {
25767         __IOM uint16_t STATL;          /*!< (@ 0x00000006) CEC Transmission Start Bit Low Width Setting
25768                                         *                  Register                                                   */
25769 
25770         struct
25771         {
25772             __IOM uint16_t STATL : 9;  /*!< [8..0] CEC Transmission Start Bit Low Width Setting                       */
25773             uint16_t             : 7;
25774         } STATL_b;
25775     };
25776 
25777     union
25778     {
25779         __IOM uint16_t LGC0L;          /*!< (@ 0x00000008) CEC Transmission Logical 0 Low Width Setting
25780                                         *                  Register                                                   */
25781 
25782         struct
25783         {
25784             __IOM uint16_t LGC0L : 9;  /*!< [8..0] CEC Transmission Logical 0 Low Width Setting                       */
25785             uint16_t             : 7;
25786         } LGC0L_b;
25787     };
25788 
25789     union
25790     {
25791         __IOM uint16_t LGC1L;          /*!< (@ 0x0000000A) CEC Transmission Logical 1 Low Width Setting
25792                                         *                  Register                                                   */
25793 
25794         struct
25795         {
25796             __IOM uint16_t LGC1L : 9;  /*!< [8..0] CEC Transmission Logical 1 Low Width Setting                       */
25797             uint16_t             : 7;
25798         } LGC1L_b;
25799     };
25800 
25801     union
25802     {
25803         __IOM uint16_t DATB;           /*!< (@ 0x0000000C) CEC Transmission Data Bit Width Setting Register           */
25804 
25805         struct
25806         {
25807             __IOM uint16_t DATB : 9;   /*!< [8..0] CEC Transmission Data Bit Width Setting                            */
25808             uint16_t            : 7;
25809         } DATB_b;
25810     };
25811 
25812     union
25813     {
25814         __IOM uint16_t NOMT;           /*!< (@ 0x0000000E) CEC Reception Data Sampling Time Setting Register          */
25815 
25816         struct
25817         {
25818             __IOM uint16_t NOMT : 9;   /*!< [8..0] CEC Reception Data Sampling Time Setting,                          */
25819             uint16_t            : 7;
25820         } NOMT_b;
25821     };
25822 
25823     union
25824     {
25825         __IOM uint16_t STATLL;         /*!< (@ 0x00000010) CEC Reception Start Bit Minimum Low Width Setting
25826                                         *                  Register                                                   */
25827 
25828         struct
25829         {
25830             __IOM uint16_t STATLL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Low Width Setting                  */
25831             uint16_t              : 7;
25832         } STATLL_b;
25833     };
25834 
25835     union
25836     {
25837         __IOM uint16_t STATLH;         /*!< (@ 0x00000012) CEC Reception Start Bit Maximum Low Width Setting
25838                                         *                  Register                                                   */
25839 
25840         struct
25841         {
25842             __IOM uint16_t STATLH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting                  */
25843             uint16_t              : 7;
25844         } STATLH_b;
25845     };
25846 
25847     union
25848     {
25849         __IOM uint16_t STATBL;         /*!< (@ 0x00000014) CEC Reception Start Bit Minimum Bit Width Setting
25850                                         *                  Register                                                   */
25851 
25852         struct
25853         {
25854             __IOM uint16_t STATBL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Bit Width Setting                  */
25855             uint16_t              : 7;
25856         } STATBL_b;
25857     };
25858 
25859     union
25860     {
25861         __IOM uint16_t STATBH;         /*!< (@ 0x00000016) CEC Reception Start Bit Maximum Bit Width Setting
25862                                         *                  Register                                                   */
25863 
25864         struct
25865         {
25866             __IOM uint16_t STATBH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting                  */
25867             uint16_t              : 7;
25868         } STATBH_b;
25869     };
25870 
25871     union
25872     {
25873         __IOM uint16_t LGC0LL;         /*!< (@ 0x00000018) CEC Reception Logical 0 Minimum Low Width Setting
25874                                         *                  Register                                                   */
25875 
25876         struct
25877         {
25878             __IOM uint16_t LGC0LL : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting                  */
25879             uint16_t              : 7;
25880         } LGC0LL_b;
25881     };
25882 
25883     union
25884     {
25885         __IOM uint16_t LGC0LH;         /*!< (@ 0x0000001A) CEC Reception Logical 0 Maximum Low Width Setting
25886                                         *                  Register                                                   */
25887 
25888         struct
25889         {
25890             __IOM uint16_t LGC0LH : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting                  */
25891             uint16_t              : 7;
25892         } LGC0LH_b;
25893     };
25894 
25895     union
25896     {
25897         __IOM uint16_t LGC1LL;         /*!< (@ 0x0000001C) CEC Reception Logical 1 Minimum Low Width Setting
25898                                         *                  Register                                                   */
25899 
25900         struct
25901         {
25902             __IOM uint16_t LGC1LL : 9; /*!< [8..0] CEC Reception Logical 1 Minimum Low Width Setting                  */
25903             uint16_t              : 7;
25904         } LGC1LL_b;
25905     };
25906 
25907     union
25908     {
25909         __IOM uint16_t LGC1LH;         /*!< (@ 0x0000001E) CEC Reception Logical 1 Maximum Low Width Setting
25910                                         *                  Register                                                   */
25911 
25912         struct
25913         {
25914             __IOM uint16_t LGC1LH : 9; /*!< [8..0] CEC Reception Logical 1 Maximum Low Width Setting                  */
25915             uint16_t              : 7;
25916         } LGC1LH_b;
25917     };
25918 
25919     union
25920     {
25921         __IOM uint16_t DATBL;          /*!< (@ 0x00000020) CEC Reception Data Bit Minimum Bit Width Setting
25922                                         *                  Register                                                   */
25923 
25924         struct
25925         {
25926             __IOM uint16_t DATBL : 9;  /*!< [8..0] CEC Reception Data Bit Minimum Bit Width Setting                   */
25927             uint16_t             : 7;
25928         } DATBL_b;
25929     };
25930 
25931     union
25932     {
25933         __IOM uint16_t DATBH;          /*!< (@ 0x00000022) CEC Reception Data Bit Maximum Bit Width Setting
25934                                         *                  Register                                                   */
25935 
25936         struct
25937         {
25938             __IOM uint16_t DATBH : 9;  /*!< [8..0] CEC Reception Data Bit Maximum Bit Width Setting                   */
25939             uint16_t             : 7;
25940         } DATBH_b;
25941     };
25942 
25943     union
25944     {
25945         __IOM uint16_t NOMP;           /*!< (@ 0x00000024) CEC Data Bit Reference Width Setting Register              */
25946 
25947         struct
25948         {
25949             __IOM uint16_t NOMP : 9;   /*!< [8..0] CEC Data Bit Reference Width Setting                               */
25950             uint16_t            : 7;
25951         } NOMP_b;
25952     };
25953     __IM uint16_t RESERVED1;
25954 
25955     union
25956     {
25957         __IOM uint8_t CECEXMD;         /*!< (@ 0x00000028) CEC Extension Mode Register                                */
25958 
25959         struct
25960         {
25961             uint8_t                  : 4;
25962             __IOM uint8_t LERPLEN    : 1; /*!< [4..4] Pulse Output Function Enable by Long Bit Width Error               */
25963             __IOM uint8_t RERCVEN    : 1; /*!< [5..5] Start Detection Reception Restart Enable                           */
25964             uint8_t                  : 1;
25965             __IOM uint8_t RCVINTDSEL : 1; /*!< [7..7] INTDA Reception Interrupt Timing Change                            */
25966         } CECEXMD_b;
25967     };
25968     __IM uint8_t RESERVED2;
25969 
25970     union
25971     {
25972         __IOM uint8_t CECEXMON;        /*!< (@ 0x0000002A) CEC Extension Monitor Register                             */
25973 
25974         struct
25975         {
25976             __IM uint8_t CECLNMON : 1; /*!< [0..0] CEC Line Monitor                                                   */
25977             __IM uint8_t ACKF     : 1; /*!< [1..1] ACK Flag                                                           */
25978             uint8_t               : 6;
25979         } CECEXMON_b;
25980     };
25981     __IM uint8_t  RESERVED3;
25982     __IM uint16_t RESERVED4[10];
25983     __IOM uint8_t CTXD;                /*!< (@ 0x00000040) CEC Transmission Buffer Register                           */
25984     __IOM uint8_t CRXD;                /*!< (@ 0x00000041) CEC Reception Buffer Register                              */
25985 
25986     union
25987     {
25988         __IOM uint8_t CECES;           /*!< (@ 0x00000042) CEC Communication Error Status Register                    */
25989 
25990         struct
25991         {
25992             __IM uint8_t OERR   : 1;   /*!< [0..0] Overrun Error Detection Flag                                       */
25993             __IM uint8_t UERR   : 1;   /*!< [1..1] Underrun Error Detection Flag                                      */
25994             __IM uint8_t ACKERR : 1;   /*!< [2..2] ACK Error Detection Flag                                           */
25995             __IM uint8_t TERR   : 1;   /*!< [3..3] Timing Error Detection Flag                                        */
25996             __IM uint8_t TXERR  : 1;   /*!< [4..4] Transmission Error Detection Flag                                  */
25997             __IM uint8_t AERR   : 1;   /*!< [5..5] Arbitration Loss Detection Flag                                    */
25998             __IM uint8_t BLERR  : 1;   /*!< [6..6] Bus Lock Error Detection Flag                                      */
25999             uint8_t             : 1;
26000         } CECES_b;
26001     };
26002 
26003     union
26004     {
26005         __IOM uint8_t CECS;            /*!< (@ 0x00000043) CEC Communication Status Register                          */
26006 
26007         struct
26008         {
26009             __IM uint8_t ADRF  : 1;    /*!< [0..0] Address Match Detection Flag                                       */
26010             __IM uint8_t BUSST : 1;    /*!< [1..1] Bus Busy Detection Flag                                            */
26011             __IM uint8_t TXST  : 1;    /*!< [2..2] Transmission Status Flag                                           */
26012             __IM uint8_t EOMF  : 1;    /*!< [3..3] EOM Flag                                                           */
26013             __IM uint8_t ITCEF : 1;    /*!< [4..4] INTCE Generation Source Flag                                       */
26014             uint8_t            : 2;
26015             __IM uint8_t SFTST : 1;    /*!< [7..7] Signal-Free Time Rewrite Disable Report Flag                       */
26016         } CECS_b;
26017     };
26018 
26019     union
26020     {
26021         __IOM uint8_t CECFC;           /*!< (@ 0x00000044) CEC Communication Error Flag Clear Trigger Register        */
26022 
26023         struct
26024         {
26025             __OM uint8_t OCTRG   : 1;  /*!< [0..0] Overrun Error Detection Flag Clear Trigger                         */
26026             __OM uint8_t UCTRG   : 1;  /*!< [1..1] Underrun Error Detection Flag Clear Trigger                        */
26027             __OM uint8_t ACKCTRG : 1;  /*!< [2..2] ACK Error Detection Flag Clear Trigger                             */
26028             __OM uint8_t TCTRG   : 1;  /*!< [3..3] Timing Error Detection Flag Clear Trigger                          */
26029             __OM uint8_t TXCTRG  : 1;  /*!< [4..4] Transmission Error Detection Flag Clear Trigger                    */
26030             __OM uint8_t ACTRG   : 1;  /*!< [5..5] Arbitration Loss Detection Flag Clear Trigger                      */
26031             __OM uint8_t BLCTRG  : 1;  /*!< [6..6] Bus Lock Error Detection Flag Clear Trigger                        */
26032             uint8_t              : 1;
26033         } CECFC_b;
26034     };
26035 
26036     union
26037     {
26038         __IOM uint8_t CECCTL0;         /*!< (@ 0x00000045) CEC Control Register 0                                     */
26039 
26040         struct
26041         {
26042             __IOM uint8_t EOM     : 1; /*!< [0..0] EOM Setting                                                        */
26043             __IOM uint8_t CECRXEN : 1; /*!< [1..1] Reception Enable Control                                           */
26044             __OM uint8_t  TXTRG   : 1; /*!< [2..2] Transmission Start Trigger                                         */
26045             __IOM uint8_t CCL     : 3; /*!< [5..3] CEC Clock (CECCLK) Select                                          */
26046             __IOM uint8_t ACKTEN  : 1; /*!< [6..6] ACK Bit Timing Error (Bit Width) Check Enable                      */
26047             __IOM uint8_t CECE    : 1; /*!< [7..7] CEC Operation Enable Flag                                          */
26048         } CECCTL0_b;
26049     };
26050 } R_CEC_Type;                          /*!< Size = 70 (0x46)                                                          */
26051 
26052 /* =========================================================================================================================== */
26053 /* ================                                          R_OSPI                                           ================ */
26054 /* =========================================================================================================================== */
26055 
26056 /**
26057  * @brief Octa Serial Peripheral Interface (R_OSPI)
26058  */
26059 
26060 typedef struct                         /*!< (@ 0x400A6000) R_OSPI Structure                                           */
26061 {
26062     union
26063     {
26064         __IOM uint32_t DCR;            /*!< (@ 0x00000000) Device Command Register                                    */
26065 
26066         struct
26067         {
26068             __IOM uint32_t DVCMD0 : 8; /*!< [7..0] Device Command data                                                */
26069             __IOM uint32_t DVCMD1 : 8; /*!< [15..8] Device Command data                                               */
26070             uint32_t              : 16;
26071         } DCR_b;
26072     };
26073 
26074     union
26075     {
26076         __IOM uint32_t DAR;            /*!< (@ 0x00000004) Device Address Register                                    */
26077 
26078         struct
26079         {
26080             __IOM uint32_t DVAD0 : 8;  /*!< [7..0] Device Address data 0                                              */
26081             __IOM uint32_t DVAD1 : 8;  /*!< [15..8] Device Address data 1                                             */
26082             __IOM uint32_t DVAD2 : 8;  /*!< [23..16] Device Address data 2                                            */
26083             __IOM uint32_t DVAD3 : 8;  /*!< [31..24] Device Address data 3                                            */
26084         } DAR_b;
26085     };
26086 
26087     union
26088     {
26089         __IOM uint32_t DCSR;           /*!< (@ 0x00000008) Device Command Setting Register                            */
26090 
26091         struct
26092         {
26093             __IOM uint32_t DALEN  : 8; /*!< [7..0] Transfer data length setting                                       */
26094             __IOM uint32_t DMLEN  : 8; /*!< [15..8] Dummy cycle setting                                               */
26095             uint32_t              : 3;
26096             __IOM uint32_t ACDV   : 1; /*!< [19..19] Access Device setting                                            */
26097             __IOM uint32_t CMDLEN : 3; /*!< [22..20] Transfer command length setting                                  */
26098             __IOM uint32_t DAOR   : 1; /*!< [23..23] Data order setting                                               */
26099             __IOM uint32_t ADLEN  : 3; /*!< [26..24] Transfer address length setting                                  */
26100             __IOM uint32_t DOPI   : 1; /*!< [27..27] DOPI single byte setting                                         */
26101             __IOM uint32_t ACDA   : 1; /*!< [28..28] Data Access Control                                              */
26102             __IOM uint32_t PREN   : 1; /*!< [29..29] Preamble bit enable for OctaRAM                                  */
26103             uint32_t              : 2;
26104         } DCSR_b;
26105     };
26106 
26107     union
26108     {
26109         __IOM uint32_t DSR[2];         /*!< (@ 0x0000000C) Device Size Register 0                                     */
26110 
26111         struct
26112         {
26113             __IOM uint32_t DVSZ  : 30; /*!< [29..0] Device size setting                                               */
26114             __IOM uint32_t DVTYP : 2;  /*!< [31..30] Device type setting                                              */
26115         } DSR_b[2];
26116     };
26117 
26118     union
26119     {
26120         __IOM uint32_t MDTR;             /*!< (@ 0x00000014) Memory Delay Trim Register                                 */
26121 
26122         struct
26123         {
26124             __IOM uint32_t DV0DEL   : 8; /*!< [7..0] Device 0 delay setting                                             */
26125             __IOM uint32_t DQSERAM  : 4; /*!< [11..8] OM_DQS enable counter                                             */
26126             __IOM uint32_t DQSESOPI : 4; /*!< [15..12] OM_DQS enable counter                                            */
26127             __IOM uint32_t DV1DEL   : 8; /*!< [23..16] Device 1 delay setting                                           */
26128             __IOM uint32_t DQSEDOPI : 4; /*!< [27..24] OM_DQS enable counter                                            */
26129             uint32_t                : 4;
26130         } MDTR_b;
26131     };
26132 
26133     union
26134     {
26135         __IOM uint32_t ACTR;           /*!< (@ 0x00000018) Auto-Calibration Timer Register                            */
26136 
26137         struct
26138         {
26139             __IOM uint32_t CTP : 32;   /*!< [31..0] Automatic calibration cycle time setting                          */
26140         } ACTR_b;
26141     };
26142 
26143     union
26144     {
26145         __IOM uint32_t ACAR[2];        /*!< (@ 0x0000001C) Auto-Calibration Address Register                          */
26146 
26147         struct
26148         {
26149             __IOM uint32_t CAD : 32;   /*!< [31..0] Automatic calibration address                                     */
26150         } ACAR_b[2];
26151     };
26152     __IM uint32_t RESERVED[4];
26153 
26154     union
26155     {
26156         __IOM uint32_t DRCSTR;           /*!< (@ 0x00000034) Device Memory Map Read Chip Select Timing Setting
26157                                           *                  Register                                                   */
26158 
26159         struct
26160         {
26161             __IOM uint32_t CTRW0 : 7;    /*!< [6..0] Device 0 single continuous read waiting cycle setting
26162                                           *   in PCLKH units                                                            */
26163             __IOM uint32_t CTR0     : 1; /*!< [7..7] Device 0 single continuous read mode setting                       */
26164             __IOM uint32_t DVRDCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting                       */
26165             __IOM uint32_t DVRDHI0  : 3; /*!< [13..11] Device 0 select signal pull-up timing setting                    */
26166             __IOM uint32_t DVRDLO0  : 2; /*!< [15..14] Device 0 select signal pull-down timing setting                  */
26167             __IOM uint32_t CTRW1    : 7; /*!< [22..16] Device 1 single continuous read waiting cycle setting
26168                                           *   in PCLKH units                                                            */
26169             __IOM uint32_t CTR1     : 1; /*!< [23..23] Device 1 single continuous read mode setting                     */
26170             __IOM uint32_t DVRDCMD1 : 3; /*!< [26..24] Device 1 Command execution interval                              */
26171             __IOM uint32_t DVRDHI1  : 3; /*!< [29..27] Device 1 select signal High timing setting                       */
26172             __IOM uint32_t DVRDLO1  : 2; /*!< [31..30] Device 1 select signal pull-down timing setting                  */
26173         } DRCSTR_b;
26174     };
26175 
26176     union
26177     {
26178         __IOM uint32_t DWCSTR;          /*!< (@ 0x00000038) Device Memory Map Write Chip Select Timing Setting
26179                                          *                  Register                                                   */
26180 
26181         struct
26182         {
26183             __IOM uint32_t CTWW0 : 7;   /*!< [6..0] Device 0 single continuous write waiting cycle setting
26184                                          *   in PCLKH units                                                            */
26185             __IOM uint32_t CTW0    : 1; /*!< [7..7] Device 0 single continuous write mode setting                      */
26186             __IOM uint32_t DVWCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting                       */
26187             __IOM uint32_t DVWHI0  : 3; /*!< [13..11] Device 0 select signal pull-up timing setting                    */
26188             __IOM uint32_t DVWLO0  : 2; /*!< [15..14] Device 0 select signal pull-down timing setting                  */
26189             __IOM uint32_t CTWW1   : 7; /*!< [22..16] Device 1 single continuous write waiting cycle setting
26190                                          *   in PCLKH units                                                            */
26191             __IOM uint32_t CTW1    : 1; /*!< [23..23] Device 1 single continuous write mode setting                    */
26192             __IOM uint32_t DVWCMD1 : 3; /*!< [26..24] Device 1 Command execution interval setting                      */
26193             __IOM uint32_t DVWHI1  : 3; /*!< [29..27] Device 1 select signal pull-up timing setting                    */
26194             __IOM uint32_t DVWLO1  : 2; /*!< [31..30] Device 1 select signal pull-down timing setting                  */
26195         } DWCSTR_b;
26196     };
26197 
26198     union
26199     {
26200         __IOM uint32_t DCSTR;          /*!< (@ 0x0000003C) Device Chip Select Timing Setting Register                 */
26201 
26202         struct
26203         {
26204             uint32_t                : 8;
26205             __IOM uint32_t DVSELCMD : 3; /*!< [10..8] Device Command execution interval setting                         */
26206             __IOM uint32_t DVSELHI  : 3; /*!< [13..11] Device select signal pull-up timing setting                      */
26207             __IOM uint32_t DVSELLO  : 2; /*!< [15..14] Device select signal pull-down timing setting                    */
26208             uint32_t                : 16;
26209         } DCSTR_b;
26210     };
26211 
26212     union
26213     {
26214         __IOM uint32_t CDSR;            /*!< (@ 0x00000040) Controller and Device Setting Register                     */
26215 
26216         struct
26217         {
26218             __IOM uint32_t DV0TTYP : 2; /*!< [1..0] Device0_transfer_type setting                                      */
26219             __IOM uint32_t DV1TTYP : 2; /*!< [3..2] Device1_transfer_type setting                                      */
26220             __IOM uint32_t DV0PC   : 1; /*!< [4..4] Device0_memory precycle setting                                    */
26221             __IOM uint32_t DV1PC   : 1; /*!< [5..5] Device1_memory precycle setting                                    */
26222             uint32_t               : 4;
26223             __IOM uint32_t ACMEME0 : 1; /*!< [10..10] Automatic calibration memory enable setting for device
26224                                          *   0                                                                         */
26225             __IOM uint32_t ACMEME1 : 1; /*!< [11..11] Automatic calibration memory enable setting for device
26226                                          *   1                                                                         */
26227             __IOM uint32_t ACMODE : 2;  /*!< [13..12] Automatic calibration mode                                       */
26228             uint32_t              : 17;
26229             __IOM uint32_t DLFT   : 1;  /*!< [31..31] Deadlock Free Timer Enable                                       */
26230         } CDSR_b;
26231     };
26232 
26233     union
26234     {
26235         __IOM uint32_t MDLR;           /*!< (@ 0x00000044) Memory Map Dummy Length Register                           */
26236 
26237         struct
26238         {
26239             __IOM uint32_t DV0RDL : 8; /*!< [7..0] Device 0 Read dummy length setting                                 */
26240             __IOM uint32_t DV0WDL : 8; /*!< [15..8] Device 0 Write dummy length setting                               */
26241             __IOM uint32_t DV1RDL : 8; /*!< [23..16] Device 1 Read dummy length setting                               */
26242             __IOM uint32_t DV1WDL : 8; /*!< [31..24] Device 1 Write dummy length setting                              */
26243         } MDLR_b;
26244     };
26245 
26246     union
26247     {
26248         __IOM uint32_t MRWCR[2];        /*!< (@ 0x00000048) Memory Map Read/Write Command Register                     */
26249 
26250         struct
26251         {
26252             __IOM uint32_t DMRCMD0 : 8; /*!< [7..0] Memory map read command 0 setting                                  */
26253             __IOM uint32_t DMRCMD1 : 8; /*!< [15..8] Memory map read command 1 setting                                 */
26254             __IOM uint32_t DMWCMD0 : 8; /*!< [23..16] Memory map write command 0 setting                               */
26255             __IOM uint32_t DMWCMD1 : 8; /*!< [31..24] Memory map write command 1 setting                               */
26256         } MRWCR_b[2];
26257     };
26258 
26259     union
26260     {
26261         __IOM uint32_t MRWCSR;         /*!< (@ 0x00000050) Memory Map Read/Write Setting Register                     */
26262 
26263         struct
26264         {
26265             __IOM uint32_t MRAL0 : 3;  /*!< [2..0] Device 0 read address length setting                               */
26266             __IOM uint32_t MRCL0 : 3;  /*!< [5..3] Device 0 read command length setting                               */
26267             __IOM uint32_t MRO0  : 1;  /*!< [6..6] Device 0 read order setting                                        */
26268             __IOM uint32_t PREN0 : 1;  /*!< [7..7] Preamble bit enable for mem0 memory-map read                       */
26269             __IOM uint32_t MWAL0 : 3;  /*!< [10..8] Device 0 write address length setting                             */
26270             __IOM uint32_t MWCL0 : 3;  /*!< [13..11] Device 0 write command length setting                            */
26271             __IOM uint32_t MWO0  : 1;  /*!< [14..14] Device 0 write order setting                                     */
26272             uint32_t             : 1;
26273             __IOM uint32_t MRAL1 : 3;  /*!< [18..16] Device 1 read address length setting                             */
26274             __IOM uint32_t MRCL1 : 3;  /*!< [21..19] Device 1 read command length setting                             */
26275             __IOM uint32_t MRO1  : 1;  /*!< [22..22] Device 1 read order setting                                      */
26276             __IOM uint32_t PREN1 : 1;  /*!< [23..23] Preamble bit enable for mem1 memory-map read                     */
26277             __IOM uint32_t MWAL1 : 3;  /*!< [26..24] Device 1 write address length setting                            */
26278             __IOM uint32_t MWCL1 : 3;  /*!< [29..27] Device 1 write command length setting                            */
26279             __IOM uint32_t MWO1  : 1;  /*!< [30..30] Device 1 write order setting                                     */
26280             uint32_t             : 1;
26281         } MRWCSR_b;
26282     };
26283 
26284     union
26285     {
26286         __IM uint32_t ESR;             /*!< (@ 0x00000054) Error Status Register                                      */
26287 
26288         struct
26289         {
26290             __IM uint32_t MRESR : 8;   /*!< [7..0] Memory map read error status                                       */
26291             __IM uint32_t MWESR : 8;   /*!< [15..8] Memory map write error status                                     */
26292             uint32_t            : 16;
26293         } ESR_b;
26294     };
26295 
26296     union
26297     {
26298         __OM uint32_t CWNDR;           /*!< (@ 0x00000058) Configure Write without Data Register                      */
26299 
26300         struct
26301         {
26302             __OM uint32_t WND : 32;    /*!< [31..0] The write value should be 0.                                      */
26303         } CWNDR_b;
26304     };
26305 
26306     union
26307     {
26308         __OM uint32_t CWDR;            /*!< (@ 0x0000005C) Configure Write Data Register                              */
26309 
26310         struct
26311         {
26312             __OM uint32_t WD0 : 8;     /*!< [7..0] Write data 0                                                       */
26313             __OM uint32_t WD1 : 8;     /*!< [15..8] Write data 1                                                      */
26314             __OM uint32_t WD2 : 8;     /*!< [23..16] Write data 2                                                     */
26315             __OM uint32_t WD3 : 8;     /*!< [31..24] Write data 3                                                     */
26316         } CWDR_b;
26317     };
26318 
26319     union
26320     {
26321         __IM uint32_t CRR;             /*!< (@ 0x00000060) Configure Read Register                                    */
26322 
26323         struct
26324         {
26325             __IM uint32_t RD0 : 8;     /*!< [7..0] Read data 0                                                        */
26326             __IM uint32_t RD1 : 8;     /*!< [15..8] Read data 1                                                       */
26327             __IM uint32_t RD2 : 8;     /*!< [23..16] Read data 2                                                      */
26328             __IM uint32_t RD3 : 8;     /*!< [31..24] Read data 3                                                      */
26329         } CRR_b;
26330     };
26331 
26332     union
26333     {
26334         __IOM uint32_t ACSR;           /*!< (@ 0x00000064) Auto-Calibration Status Register                           */
26335 
26336         struct
26337         {
26338             __IOM uint32_t ACSR0 : 3;  /*!< [2..0] Auto-calibration status of device 0                                */
26339             __IOM uint32_t ACSR1 : 3;  /*!< [5..3] Auto-calibration status of device 1                                */
26340             uint32_t             : 26;
26341         } ACSR_b;
26342     };
26343     __IM uint32_t RESERVED1[5];
26344 
26345     union
26346     {
26347         __IOM uint32_t DCSMXR;         /*!< (@ 0x0000007C) Device Chip Select Maximum Period Register                 */
26348 
26349         struct
26350         {
26351             __IOM uint32_t CTWMX0 : 9; /*!< [8..0] Indicates the maximum period that OM_CS0 and OM_CS1 are
26352                                         *   Low in single continuous write of OctaRAM.                                */
26353             uint32_t              : 7;
26354             __IOM uint32_t CTWMX1 : 9; /*!< [24..16] Indicates the maximum period that OM_CS0 and OM_CS1
26355                                         *   are Low in single continuous read of OctaRAM.                             */
26356             uint32_t : 7;
26357         } DCSMXR_b;
26358     };
26359 
26360     union
26361     {
26362         __IOM uint32_t DWSCTSR;        /*!< (@ 0x00000080) Device Memory Map Write single continuous translating
26363                                         *                  size Register                                              */
26364 
26365         struct
26366         {
26367             __IOM uint32_t CTSN0 : 11; /*!< [10..0] Indicates the number of bytes to translate in single
26368                                         *   continuous write of device 0.                                             */
26369             uint32_t             : 5;
26370             __IOM uint32_t CTSN1 : 11; /*!< [26..16] Indicates the number of bytes to translate in single
26371                                         *   continuous write of device 1.                                             */
26372             uint32_t : 5;
26373         } DWSCTSR_b;
26374     };
26375 } R_OSPI_Type;                         /*!< Size = 132 (0x84)                                                         */
26376 
26377 /* =========================================================================================================================== */
26378 /* ================                                         R_ADC_B0                                          ================ */
26379 /* =========================================================================================================================== */
26380 
26381 /**
26382  * @brief 12-bit A/D Converter (R_ADC_B0)
26383  */
26384 
26385 typedef struct                         /*!< (@ 0x40170000) R_ADC_B0 Structure                                         */
26386 {
26387     union
26388     {
26389         __IOM uint32_t ADCLKENR;       /*!< (@ 0x00000000) A/D Conversion Clock Enable Register                       */
26390 
26391         struct
26392         {
26393             __IOM uint32_t CLKEN : 1;  /*!< [0..0] ADCLK Operating Enable bit                                         */
26394             uint32_t             : 31;
26395         } ADCLKENR_b;
26396     };
26397 
26398     union
26399     {
26400         __IM uint32_t ADCLKSR;         /*!< (@ 0x00000004) A/D Conversion Clock Status Register                       */
26401 
26402         struct
26403         {
26404             __IM uint32_t CLKSR : 1;   /*!< [0..0] ADCLK status bit                                                   */
26405             uint32_t            : 31;
26406         } ADCLKSR_b;
26407     };
26408 
26409     union
26410     {
26411         __IOM uint32_t ADCLKCR;        /*!< (@ 0x00000008) A/D Conversion Clock Control Register                      */
26412 
26413         struct
26414         {
26415             __IOM uint32_t CLKSEL : 2; /*!< [1..0] ADCLK Clock Source Select                                          */
26416             uint32_t              : 14;
26417             __IOM uint32_t DIVR   : 3; /*!< [18..16] Clock Division Ratio Select                                      */
26418             uint32_t              : 13;
26419         } ADCLKCR_b;
26420     };
26421 
26422     union
26423     {
26424         __IOM uint32_t ADSYCR;            /*!< (@ 0x0000000C) A/D Converter Synchronous Operation Control Register       */
26425 
26426         struct
26427         {
26428             __IOM uint32_t ADSYCYC  : 11; /*!< [10..0] A/D Converter Synchronous Operation Period Cycle                  */
26429             uint32_t                : 5;
26430             __IOM uint32_t ADSYDIS0 : 1;  /*!< [16..16] ADC0 Synchronous Operation Select                                */
26431             __IOM uint32_t ADSYDIS1 : 1;  /*!< [17..17] ADC1 Synchronous Operation Select                                */
26432             uint32_t                : 14;
26433         } ADSYCR_b;
26434     };
26435     __IM uint32_t RESERVED[4];
26436 
26437     union
26438     {
26439         __IOM uint32_t ADERINTCR;      /*!< (@ 0x00000020) A/D Conversion Error Interrupt Enable Register             */
26440 
26441         struct
26442         {
26443             __IOM uint32_t ADEIE0 : 1; /*!< [0..0] ADC0 A/D Conversion Error Interrupt Enable                         */
26444             __IOM uint32_t ADEIE1 : 1; /*!< [1..1] ADC1 A/D Conversion Error Interrupt Enable                         */
26445             uint32_t              : 30;
26446         } ADERINTCR_b;
26447     };
26448 
26449     union
26450     {
26451         __IOM uint32_t ADOVFINTCR;       /*!< (@ 0x00000024) A/D Conversion Overflow Interrupt Enable Register          */
26452 
26453         struct
26454         {
26455             __IOM uint32_t ADOVFIE0 : 1; /*!< [0..0] ADC0 A/D Conversion Overflow Interrupt Enable                      */
26456             __IOM uint32_t ADOVFIE1 : 1; /*!< [1..1] ADC1 A/D Conversion Overflow Interrupt Enable                      */
26457             uint32_t                : 30;
26458         } ADOVFINTCR_b;
26459     };
26460 
26461     union
26462     {
26463         __IOM uint32_t ADCALINTCR;     /*!< (@ 0x00000028) Calibration interrupt Enable Register                      */
26464 
26465         struct
26466         {
26467             uint32_t                 : 16;
26468             __IOM uint32_t CALENDIE0 : 1; /*!< [16..16] ADC0 Calibration End Interrupt Enable                            */
26469             __IOM uint32_t CALENDIE1 : 1; /*!< [17..17] ADC1 Calibration End Interrupt Enable                            */
26470             uint32_t                 : 14;
26471         } ADCALINTCR_b;
26472     };
26473     __IM uint32_t RESERVED1[5];
26474 
26475     union
26476     {
26477         __IOM uint32_t ADMDR;          /*!< (@ 0x00000040) A/D Converter Mode Selection Register                      */
26478 
26479         struct
26480         {
26481             __IOM uint32_t ADMD0 : 4;  /*!< [3..0] ADC0 Mode Selection                                                */
26482             uint32_t             : 4;
26483             __IOM uint32_t ADMD1 : 4;  /*!< [11..8] ADC1 Mode Selection                                               */
26484             uint32_t             : 20;
26485         } ADMDR_b;
26486     };
26487 
26488     union
26489     {
26490         __IOM uint32_t ADGSPCR;        /*!< (@ 0x00000044) A/D Group scan Priority Control Register                   */
26491 
26492         struct
26493         {
26494             __IOM uint32_t PGS0   : 1; /*!< [0..0] ADC0 Group Priority Control Setting                                */
26495             __IOM uint32_t RSCN0  : 1; /*!< [1..1] ADC0 Group Priority Control Setting 2                              */
26496             __IOM uint32_t LGRRS0 : 1; /*!< [2..2] ADC0 Group Priority Control Setting 3                              */
26497             __IOM uint32_t GRP0   : 1; /*!< [3..3] ADC0 Group Priority Control Setting 4                              */
26498             uint32_t              : 4;
26499             __IOM uint32_t PGS1   : 1; /*!< [8..8] ADC1 Group Priority Control Setting                                */
26500             __IOM uint32_t RSCN1  : 1; /*!< [9..9] ADC1 Group Priority Control Setting 2                              */
26501             __IOM uint32_t LGRRS1 : 1; /*!< [10..10] ADC1 Group Priority Control Setting 3                            */
26502             __IOM uint32_t GRP1   : 1; /*!< [11..11] ADC1 Group Priority Control Setting 4                            */
26503             uint32_t              : 20;
26504         } ADGSPCR_b;
26505     };
26506 
26507     union
26508     {
26509         __IOM uint32_t ADSGER;         /*!< (@ 0x00000048) Scan Group Enable Register                                 */
26510 
26511         struct
26512         {
26513             __IOM uint32_t SGREn : 9;  /*!< [8..0] Scan Group n Enable                                                */
26514             uint32_t             : 23;
26515         } ADSGER_b;
26516     };
26517 
26518     union
26519     {
26520         __IOM uint32_t ADSGCR0;        /*!< (@ 0x0000004C) Scan Group Control Register 0                              */
26521 
26522         struct
26523         {
26524             __IOM uint32_t SGADS0 : 2; /*!< [1..0] Scan Group 0 A/D Converter Selection                               */
26525             uint32_t              : 6;
26526             __IOM uint32_t SGADS1 : 2; /*!< [9..8] Scan Group 1 A/D Converter Selection                               */
26527             uint32_t              : 6;
26528             __IOM uint32_t SGADS2 : 2; /*!< [17..16] Scan Group 2 A/D Converter Selection                             */
26529             uint32_t              : 6;
26530             __IOM uint32_t SGADS3 : 2; /*!< [25..24] Scan Group 3 A/D Converter Selection                             */
26531             uint32_t              : 6;
26532         } ADSGCR0_b;
26533     };
26534 
26535     union
26536     {
26537         __IOM uint32_t ADSGCR1;        /*!< (@ 0x00000050) Scan Group Control Register 1                              */
26538 
26539         struct
26540         {
26541             __IOM uint32_t SGADS4 : 2; /*!< [1..0] Scan Group 4 A/D Converter Selection                               */
26542             uint32_t              : 6;
26543             __IOM uint32_t SGADS5 : 2; /*!< [9..8] Scan Group 5 A/D Converter Selection                               */
26544             uint32_t              : 6;
26545             __IOM uint32_t SGADS6 : 2; /*!< [17..16] Scan Group 6 A/D Converter Selection                             */
26546             uint32_t              : 6;
26547             __IOM uint32_t SGADS7 : 2; /*!< [25..24] Scan Group 7 A/D Converter Selection                             */
26548             uint32_t              : 6;
26549         } ADSGCR1_b;
26550     };
26551 
26552     union
26553     {
26554         __IOM uint32_t ADSGCR2;        /*!< (@ 0x00000054) Scan Group Control Register 2                              */
26555 
26556         struct
26557         {
26558             __IOM uint32_t SGADS8 : 2; /*!< [1..0] Scan Group 8 A/D Converter Selection                               */
26559             uint32_t              : 30;
26560         } ADSGCR2_b;
26561     };
26562     __IM uint32_t RESERVED2;
26563 
26564     union
26565     {
26566         __IOM uint32_t ADINTCR;        /*!< (@ 0x0000005C) Scan End Interrupt Enable Register                         */
26567 
26568         struct
26569         {
26570             __IOM uint32_t ADIEn : 10; /*!< [9..0] Scan Group n Scan End Interrupt Enable                             */
26571             uint32_t             : 22;
26572         } ADINTCR_b;
26573     };
26574     __IM uint32_t RESERVED3[24];
26575 
26576     union
26577     {
26578         __IOM uint32_t ADTRGEXT0;       /*!< (@ 0x000000C0) External Trigger Enable Register 0                         */
26579 
26580         struct
26581         {
26582             __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable                           */
26583             __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable                           */
26584             uint32_t               : 30;
26585         } ADTRGEXT0_b;
26586     };
26587 
26588     union
26589     {
26590         __IOM uint32_t ADTRGELC0;       /*!< (@ 0x000000C4) ELC Trigger Enable Register 0                              */
26591 
26592         struct
26593         {
26594             __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable                                               */
26595             uint32_t               : 26;
26596         } ADTRGELC0_b;
26597     };
26598 
26599     union
26600     {
26601         __IOM uint32_t ADTRGGPT0;         /*!< (@ 0x000000C8) GPT Trigger Enable Register 0                              */
26602 
26603         struct
26604         {
26605             __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable             */
26606             uint32_t                : 6;
26607             __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable           */
26608             uint32_t                : 6;
26609         } ADTRGGPT0_b;
26610     };
26611     __IM uint32_t RESERVED4;
26612 
26613     union
26614     {
26615         __IOM uint32_t ADTRGEXT1;       /*!< (@ 0x000000D0) External Trigger Enable Register 1                         */
26616 
26617         struct
26618         {
26619             __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable                           */
26620             __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable                           */
26621             uint32_t               : 30;
26622         } ADTRGEXT1_b;
26623     };
26624 
26625     union
26626     {
26627         __IOM uint32_t ADTRGELC1;       /*!< (@ 0x000000D4) ELC Trigger Enable Register 1                              */
26628 
26629         struct
26630         {
26631             __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable                                               */
26632             uint32_t               : 26;
26633         } ADTRGELC1_b;
26634     };
26635 
26636     union
26637     {
26638         __IOM uint32_t ADTRGGPT1;         /*!< (@ 0x000000D8) GPT Trigger Enable Register 1                              */
26639 
26640         struct
26641         {
26642             __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable             */
26643             uint32_t                : 6;
26644             __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable           */
26645             uint32_t                : 6;
26646         } ADTRGGPT1_b;
26647     };
26648     __IM uint32_t RESERVED5;
26649 
26650     union
26651     {
26652         __IOM uint32_t ADTRGEXT2;       /*!< (@ 0x000000E0) External Trigger Enable Register 2                         */
26653 
26654         struct
26655         {
26656             __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable                           */
26657             __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable                           */
26658             uint32_t               : 30;
26659         } ADTRGEXT2_b;
26660     };
26661 
26662     union
26663     {
26664         __IOM uint32_t ADTRGELC2;       /*!< (@ 0x000000E4) ELC Trigger Enable Register 2                              */
26665 
26666         struct
26667         {
26668             __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable                                               */
26669             uint32_t               : 26;
26670         } ADTRGELC2_b;
26671     };
26672 
26673     union
26674     {
26675         __IOM uint32_t ADTRGGPT2;         /*!< (@ 0x000000E8) GPT Trigger Enable Register 2                              */
26676 
26677         struct
26678         {
26679             __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable             */
26680             uint32_t                : 6;
26681             __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable           */
26682             uint32_t                : 6;
26683         } ADTRGGPT2_b;
26684     };
26685     __IM uint32_t RESERVED6;
26686 
26687     union
26688     {
26689         __IOM uint32_t ADTRGEXT3;       /*!< (@ 0x000000F0) External Trigger Enable Register 3                         */
26690 
26691         struct
26692         {
26693             __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable                           */
26694             __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable                           */
26695             uint32_t               : 30;
26696         } ADTRGEXT3_b;
26697     };
26698 
26699     union
26700     {
26701         __IOM uint32_t ADTRGELC3;       /*!< (@ 0x000000F4) ELC Trigger Enable Register 3                              */
26702 
26703         struct
26704         {
26705             __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable                                               */
26706             uint32_t               : 26;
26707         } ADTRGELC3_b;
26708     };
26709 
26710     union
26711     {
26712         __IOM uint32_t ADTRGGPT3;         /*!< (@ 0x000000F8) GPT Trigger Enable Register 3                              */
26713 
26714         struct
26715         {
26716             __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable             */
26717             uint32_t                : 6;
26718             __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable           */
26719             uint32_t                : 6;
26720         } ADTRGGPT3_b;
26721     };
26722     __IM uint32_t RESERVED7;
26723 
26724     union
26725     {
26726         __IOM uint32_t ADTRGEXT4;       /*!< (@ 0x00000100) External Trigger Enable Register 4                         */
26727 
26728         struct
26729         {
26730             __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable                           */
26731             __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable                           */
26732             uint32_t               : 30;
26733         } ADTRGEXT4_b;
26734     };
26735 
26736     union
26737     {
26738         __IOM uint32_t ADTRGELC4;       /*!< (@ 0x00000104) ELC Trigger Enable Register 4                              */
26739 
26740         struct
26741         {
26742             __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable                                               */
26743             uint32_t               : 26;
26744         } ADTRGELC4_b;
26745     };
26746 
26747     union
26748     {
26749         __IOM uint32_t ADTRGGPT4;         /*!< (@ 0x00000108) GPT Trigger Enable Register 4                              */
26750 
26751         struct
26752         {
26753             __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable             */
26754             uint32_t                : 6;
26755             __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable           */
26756             uint32_t                : 6;
26757         } ADTRGGPT4_b;
26758     };
26759     __IM uint32_t RESERVED8;
26760 
26761     union
26762     {
26763         __IOM uint32_t ADTRGEXT5;       /*!< (@ 0x00000110) External Trigger Enable Register 5                         */
26764 
26765         struct
26766         {
26767             __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable                           */
26768             __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable                           */
26769             uint32_t               : 30;
26770         } ADTRGEXT5_b;
26771     };
26772 
26773     union
26774     {
26775         __IOM uint32_t ADTRGELC5;       /*!< (@ 0x00000114) ELC Trigger Enable Register 5                              */
26776 
26777         struct
26778         {
26779             __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable                                               */
26780             uint32_t               : 26;
26781         } ADTRGELC5_b;
26782     };
26783 
26784     union
26785     {
26786         __IOM uint32_t ADTRGGPT5;         /*!< (@ 0x00000118) GPT Trigger Enable Register 5                              */
26787 
26788         struct
26789         {
26790             __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable             */
26791             uint32_t                : 6;
26792             __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable           */
26793             uint32_t                : 6;
26794         } ADTRGGPT5_b;
26795     };
26796     __IM uint32_t RESERVED9;
26797 
26798     union
26799     {
26800         __IOM uint32_t ADTRGEXT6;       /*!< (@ 0x00000120) External Trigger Enable Register 6                         */
26801 
26802         struct
26803         {
26804             __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable                           */
26805             __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable                           */
26806             uint32_t               : 30;
26807         } ADTRGEXT6_b;
26808     };
26809 
26810     union
26811     {
26812         __IOM uint32_t ADTRGELC6;       /*!< (@ 0x00000124) ELC Trigger Enable Register 6                              */
26813 
26814         struct
26815         {
26816             __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable                                               */
26817             uint32_t               : 26;
26818         } ADTRGELC6_b;
26819     };
26820 
26821     union
26822     {
26823         __IOM uint32_t ADTRGGPT6;         /*!< (@ 0x00000128) GPT Trigger Enable Register 6                              */
26824 
26825         struct
26826         {
26827             __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable             */
26828             uint32_t                : 6;
26829             __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable           */
26830             uint32_t                : 6;
26831         } ADTRGGPT6_b;
26832     };
26833     __IM uint32_t RESERVED10;
26834 
26835     union
26836     {
26837         __IOM uint32_t ADTRGEXT7;       /*!< (@ 0x00000130) External Trigger Enable Register 7                         */
26838 
26839         struct
26840         {
26841             __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable                           */
26842             __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable                           */
26843             uint32_t               : 30;
26844         } ADTRGEXT7_b;
26845     };
26846 
26847     union
26848     {
26849         __IOM uint32_t ADTRGELC7;       /*!< (@ 0x00000134) ELC Trigger Enable Register 7                              */
26850 
26851         struct
26852         {
26853             __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable                                               */
26854             uint32_t               : 26;
26855         } ADTRGELC7_b;
26856     };
26857 
26858     union
26859     {
26860         __IOM uint32_t ADTRGGPT7;         /*!< (@ 0x00000138) GPT Trigger Enable Register 7                              */
26861 
26862         struct
26863         {
26864             __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable             */
26865             uint32_t                : 6;
26866             __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable           */
26867             uint32_t                : 6;
26868         } ADTRGGPT7_b;
26869     };
26870     __IM uint32_t RESERVED11;
26871 
26872     union
26873     {
26874         __IOM uint32_t ADTRGEXT8;       /*!< (@ 0x00000140) External Trigger Enable Register 8                         */
26875 
26876         struct
26877         {
26878             __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable                           */
26879             __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable                           */
26880             uint32_t               : 30;
26881         } ADTRGEXT8_b;
26882     };
26883 
26884     union
26885     {
26886         __IOM uint32_t ADTRGELC8;       /*!< (@ 0x00000144) ELC Trigger Enable Register 8                              */
26887 
26888         struct
26889         {
26890             __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable                                               */
26891             uint32_t               : 26;
26892         } ADTRGELC8_b;
26893     };
26894 
26895     union
26896     {
26897         __IOM uint32_t ADTRGGPT8;         /*!< (@ 0x00000148) GPT Trigger Enable Register 8                              */
26898 
26899         struct
26900         {
26901             __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable             */
26902             uint32_t                : 6;
26903             __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable           */
26904             uint32_t                : 6;
26905         } ADTRGGPT8_b;
26906     };
26907     __IM uint32_t RESERVED12[29];
26908 
26909     union
26910     {
26911         __IOM uint32_t ADTRGDLR0;       /*!< (@ 0x000001C0) A/D Conversion Start Trigger Delay Register 0              */
26912 
26913         struct
26914         {
26915             __IOM uint32_t TRGDLY0 : 8; /*!< [7..0] Scan Group 0 Trigger Input Delay Configuration                     */
26916             uint32_t               : 8;
26917             __IOM uint32_t TRGDLY1 : 8; /*!< [23..16] Scan Group 1 Trigger Input Delay Configuration                   */
26918             uint32_t               : 8;
26919         } ADTRGDLR0_b;
26920     };
26921 
26922     union
26923     {
26924         __IOM uint32_t ADTRGDLR1;       /*!< (@ 0x000001C4) A/D Conversion Start Trigger Delay Register 1              */
26925 
26926         struct
26927         {
26928             __IOM uint32_t TRGDLY2 : 8; /*!< [7..0] Scan Group 2 Trigger Input Delay Configuration                     */
26929             uint32_t               : 8;
26930             __IOM uint32_t TRGDLY3 : 8; /*!< [23..16] Scan Group 3 Trigger Input Delay Configuration                   */
26931             uint32_t               : 8;
26932         } ADTRGDLR1_b;
26933     };
26934 
26935     union
26936     {
26937         __IOM uint32_t ADTRGDLR2;       /*!< (@ 0x000001C8) A/D Conversion Start Trigger Delay Register 2              */
26938 
26939         struct
26940         {
26941             __IOM uint32_t TRGDLY4 : 8; /*!< [7..0] Scan Group 4 Trigger Input Delay Configuration                     */
26942             uint32_t               : 8;
26943             __IOM uint32_t TRGDLY5 : 8; /*!< [23..16] Scan Group 5 Trigger Input Delay Configuration                   */
26944             uint32_t               : 8;
26945         } ADTRGDLR2_b;
26946     };
26947 
26948     union
26949     {
26950         __IOM uint32_t ADTRGDLR3;       /*!< (@ 0x000001CC) A/D Conversion Start Trigger Delay Register 3              */
26951 
26952         struct
26953         {
26954             __IOM uint32_t TRGDLY6 : 8; /*!< [7..0] Scan Group 6 Trigger Input Delay Configuration                     */
26955             uint32_t               : 8;
26956             __IOM uint32_t TRGDLY7 : 8; /*!< [23..16] Scan Group 7 Trigger Input Delay Configuration                   */
26957             uint32_t               : 8;
26958         } ADTRGDLR3_b;
26959     };
26960 
26961     union
26962     {
26963         __IOM uint32_t ADTRGDLR4;       /*!< (@ 0x000001D0) A/D Conversion Start Trigger Delay Register 4              */
26964 
26965         struct
26966         {
26967             __IOM uint32_t TRGDLY8 : 8; /*!< [7..0] Scan Group 8 Trigger Input Delay Configuration                     */
26968             uint32_t               : 24;
26969         } ADTRGDLR4_b;
26970     };
26971     __IM uint32_t RESERVED13[11];
26972 
26973     union
26974     {
26975         __IOM uint32_t ADSGDCR0;        /*!< (@ 0x00000200) Scan Group Diagnosis Function Control Register
26976                                          *                  0                                                          */
26977 
26978         struct
26979         {
26980             __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection                                   */
26981             uint32_t               : 13;
26982             __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable                            */
26983             uint32_t               : 3;
26984             __IOM uint32_t ADDISP  : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection                    */
26985             __IOM uint32_t ADDISN  : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection                    */
26986             uint32_t               : 2;
26987             __IOM uint32_t ADNDIS  : 4; /*!< [27..24] Disconnection Detection Assist Period                            */
26988             uint32_t               : 4;
26989         } ADSGDCR0_b;
26990     };
26991 
26992     union
26993     {
26994         __IOM uint32_t ADSGDCR1;        /*!< (@ 0x00000204) Scan Group Diagnosis Function Control Register
26995                                          *                  1                                                          */
26996 
26997         struct
26998         {
26999             __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection                                   */
27000             uint32_t               : 13;
27001             __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable                            */
27002             uint32_t               : 3;
27003             __IOM uint32_t ADDISP  : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection                    */
27004             __IOM uint32_t ADDISN  : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection                    */
27005             uint32_t               : 2;
27006             __IOM uint32_t ADNDIS  : 4; /*!< [27..24] Disconnection Detection Assist Period                            */
27007             uint32_t               : 4;
27008         } ADSGDCR1_b;
27009     };
27010 
27011     union
27012     {
27013         __IOM uint32_t ADSGDCR2;        /*!< (@ 0x00000208) Scan Group Diagnosis Function Control Register
27014                                          *                  2                                                          */
27015 
27016         struct
27017         {
27018             __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection                                   */
27019             uint32_t               : 13;
27020             __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable                            */
27021             uint32_t               : 3;
27022             __IOM uint32_t ADDISP  : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection                    */
27023             __IOM uint32_t ADDISN  : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection                    */
27024             uint32_t               : 2;
27025             __IOM uint32_t ADNDIS  : 4; /*!< [27..24] Disconnection Detection Assist Period                            */
27026             uint32_t               : 4;
27027         } ADSGDCR2_b;
27028     };
27029 
27030     union
27031     {
27032         __IOM uint32_t ADSGDCR3;        /*!< (@ 0x0000020C) Scan Group Diagnosis Function Control Register
27033                                          *                  3                                                          */
27034 
27035         struct
27036         {
27037             __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection                                   */
27038             uint32_t               : 13;
27039             __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable                            */
27040             uint32_t               : 3;
27041             __IOM uint32_t ADDISP  : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection                    */
27042             __IOM uint32_t ADDISN  : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection                    */
27043             uint32_t               : 2;
27044             __IOM uint32_t ADNDIS  : 4; /*!< [27..24] Disconnection Detection Assist Period                            */
27045             uint32_t               : 4;
27046         } ADSGDCR3_b;
27047     };
27048 
27049     union
27050     {
27051         __IOM uint32_t ADSGDCR4;        /*!< (@ 0x00000210) Scan Group Diagnosis Function Control Register
27052                                          *                  4                                                          */
27053 
27054         struct
27055         {
27056             __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection                                   */
27057             uint32_t               : 13;
27058             __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable                            */
27059             uint32_t               : 3;
27060             __IOM uint32_t ADDISP  : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection                    */
27061             __IOM uint32_t ADDISN  : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection                    */
27062             uint32_t               : 2;
27063             __IOM uint32_t ADNDIS  : 4; /*!< [27..24] Disconnection Detection Assist Period                            */
27064             uint32_t               : 4;
27065         } ADSGDCR4_b;
27066     };
27067 
27068     union
27069     {
27070         __IOM uint32_t ADSGDCR5;        /*!< (@ 0x00000214) Scan Group Diagnosis Function Control Register
27071                                          *                  5                                                          */
27072 
27073         struct
27074         {
27075             __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection                                   */
27076             uint32_t               : 13;
27077             __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable                            */
27078             uint32_t               : 3;
27079             __IOM uint32_t ADDISP  : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection                    */
27080             __IOM uint32_t ADDISN  : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection                    */
27081             uint32_t               : 2;
27082             __IOM uint32_t ADNDIS  : 4; /*!< [27..24] Disconnection Detection Assist Period                            */
27083             uint32_t               : 4;
27084         } ADSGDCR5_b;
27085     };
27086 
27087     union
27088     {
27089         __IOM uint32_t ADSGDCR6;        /*!< (@ 0x00000218) Scan Group Diagnosis Function Control Register
27090                                          *                  6                                                          */
27091 
27092         struct
27093         {
27094             __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection                                   */
27095             uint32_t               : 13;
27096             __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable                            */
27097             uint32_t               : 3;
27098             __IOM uint32_t ADDISP  : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection                    */
27099             __IOM uint32_t ADDISN  : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection                    */
27100             uint32_t               : 2;
27101             __IOM uint32_t ADNDIS  : 4; /*!< [27..24] Disconnection Detection Assist Period                            */
27102             uint32_t               : 4;
27103         } ADSGDCR6_b;
27104     };
27105 
27106     union
27107     {
27108         __IOM uint32_t ADSGDCR7;        /*!< (@ 0x0000021C) Scan Group Diagnosis Function Control Register
27109                                          *                  7                                                          */
27110 
27111         struct
27112         {
27113             __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection                                   */
27114             uint32_t               : 13;
27115             __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable                            */
27116             uint32_t               : 3;
27117             __IOM uint32_t ADDISP  : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection                    */
27118             __IOM uint32_t ADDISN  : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection                    */
27119             uint32_t               : 2;
27120             __IOM uint32_t ADNDIS  : 4; /*!< [27..24] Disconnection Detection Assist Period                            */
27121             uint32_t               : 4;
27122         } ADSGDCR7_b;
27123     };
27124 
27125     union
27126     {
27127         __IOM uint32_t ADSGDCR8;        /*!< (@ 0x00000220) Scan Group Diagnosis Function Control Register
27128                                          *                  8                                                          */
27129 
27130         struct
27131         {
27132             __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection                                   */
27133             uint32_t               : 13;
27134             __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable                            */
27135             uint32_t               : 3;
27136             __IOM uint32_t ADDISP  : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection                    */
27137             __IOM uint32_t ADDISN  : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection                    */
27138             uint32_t               : 2;
27139             __IOM uint32_t ADNDIS  : 4; /*!< [27..24] Disconnection Detection Assist Period                            */
27140             uint32_t               : 4;
27141         } ADSGDCR8_b;
27142     };
27143     __IM uint32_t RESERVED14[7];
27144 
27145     union
27146     {
27147         __IOM uint32_t ADSSTR0;        /*!< (@ 0x00000240) Sampling State Table Register 0                            */
27148 
27149         struct
27150         {
27151             __IOM uint32_t SST0 : 10;  /*!< [9..0] Sampling State Table 0                                             */
27152             uint32_t            : 6;
27153             __IOM uint32_t SST1 : 10;  /*!< [25..16] Sampling State Table 1                                           */
27154             uint32_t            : 6;
27155         } ADSSTR0_b;
27156     };
27157 
27158     union
27159     {
27160         __IOM uint32_t ADSSTR1;        /*!< (@ 0x00000244) Sampling State Table Register 1                            */
27161 
27162         struct
27163         {
27164             __IOM uint32_t SST2 : 10;  /*!< [9..0] Sampling State Table 2                                             */
27165             uint32_t            : 6;
27166             __IOM uint32_t SST3 : 10;  /*!< [25..16] Sampling State Table 3                                           */
27167             uint32_t            : 6;
27168         } ADSSTR1_b;
27169     };
27170 
27171     union
27172     {
27173         __IOM uint32_t ADSSTR2;        /*!< (@ 0x00000248) Sampling State Table Register 2                            */
27174 
27175         struct
27176         {
27177             __IOM uint32_t SST4 : 10;  /*!< [9..0] Sampling State Table 4                                             */
27178             uint32_t            : 6;
27179             __IOM uint32_t SST5 : 10;  /*!< [25..16] Sampling State Table 5                                           */
27180             uint32_t            : 6;
27181         } ADSSTR2_b;
27182     };
27183 
27184     union
27185     {
27186         __IOM uint32_t ADSSTR3;        /*!< (@ 0x0000024C) Sampling State Table Register 3                            */
27187 
27188         struct
27189         {
27190             __IOM uint32_t SST6 : 10;  /*!< [9..0] Sampling State Table 6                                             */
27191             uint32_t            : 6;
27192             __IOM uint32_t SST7 : 10;  /*!< [25..16] Sampling State Table 7                                           */
27193             uint32_t            : 6;
27194         } ADSSTR3_b;
27195     };
27196 
27197     union
27198     {
27199         __IOM uint32_t ADSSTR4;        /*!< (@ 0x00000250) Sampling State Table Register 4                            */
27200 
27201         struct
27202         {
27203             __IOM uint32_t SST8 : 10;  /*!< [9..0] Sampling State Table 8                                             */
27204             uint32_t            : 6;
27205             __IOM uint32_t SST9 : 10;  /*!< [25..16] Sampling State Table 9                                           */
27206             uint32_t            : 6;
27207         } ADSSTR4_b;
27208     };
27209 
27210     union
27211     {
27212         __IOM uint32_t ADSSTR5;        /*!< (@ 0x00000254) Sampling State Table Register 5                            */
27213 
27214         struct
27215         {
27216             __IOM uint32_t SST10 : 10; /*!< [9..0] Sampling State Table 10                                            */
27217             uint32_t             : 6;
27218             __IOM uint32_t SST11 : 10; /*!< [25..16] Sampling State Table 11                                          */
27219             uint32_t             : 6;
27220         } ADSSTR5_b;
27221     };
27222 
27223     union
27224     {
27225         __IOM uint32_t ADSSTR6;        /*!< (@ 0x00000258) Sampling State Table Register 6                            */
27226 
27227         struct
27228         {
27229             __IOM uint32_t SST12 : 10; /*!< [9..0] Sampling State Table 12                                            */
27230             uint32_t             : 6;
27231             __IOM uint32_t SST13 : 10; /*!< [25..16] Sampling State Table 13                                          */
27232             uint32_t             : 6;
27233         } ADSSTR6_b;
27234     };
27235 
27236     union
27237     {
27238         __IOM uint32_t ADSSTR7;        /*!< (@ 0x0000025C) Sampling State Table Register 7                            */
27239 
27240         struct
27241         {
27242             __IOM uint32_t SST14 : 10; /*!< [9..0] Sampling State Table 14                                            */
27243             uint32_t             : 6;
27244             __IOM uint32_t SST15 : 10; /*!< [25..16] Sampling State Table 15                                          */
27245             uint32_t             : 6;
27246         } ADSSTR7_b;
27247     };
27248 
27249     union
27250     {
27251         __IOM uint32_t ADCNVSTR;       /*!< (@ 0x00000260) A/D Conversion State Register                              */
27252 
27253         struct
27254         {
27255             __IOM uint32_t CST0 : 6;   /*!< [5..0] A/D Converter Unit 0 (ADC0)                                        */
27256             uint32_t            : 2;
27257             __IOM uint32_t CST1 : 6;   /*!< [13..8] A/D Converter Unit 1 (ADC1)                                       */
27258             uint32_t            : 18;
27259         } ADCNVSTR_b;
27260     };
27261 
27262     union
27263     {
27264         __IOM uint32_t ADCALSTCR;         /*!< (@ 0x00000264) A/D Converter Calibration State Register                   */
27265 
27266         struct
27267         {
27268             __IOM uint32_t CALADSST : 10; /*!< [9..0] A/D Converter Calibration Sampling Time Configuration              */
27269             uint32_t                : 6;
27270             __IOM uint32_t CALADCST : 6;  /*!< [21..16] A/D Converter Calibration Conversion Time Configuration.         */
27271             uint32_t                : 10;
27272         } ADCALSTCR_b;
27273     };
27274     __IM uint32_t RESERVED15[6];
27275 
27276     union
27277     {
27278         __IOM uint32_t ADSHCR0;        /*!< (@ 0x00000280) Channel-Dedicated Sample-and-Hold Circuit Control
27279                                         *                  Register 0                                                 */
27280 
27281         struct
27282         {
27283             __IOM uint32_t SHEN0 : 1;  /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Unit 0 Select            */
27284             __IOM uint32_t SHEN1 : 1;  /*!< [1..1] Channel-Dedicated Sample-and-Hold Circuit Unit 1 Select            */
27285             __IOM uint32_t SHEN2 : 1;  /*!< [2..2] Channel-Dedicated Sample-and-Hold Circuit Unit 2 Select            */
27286             uint32_t             : 29;
27287         } ADSHCR0_b;
27288     };
27289     __IM uint32_t RESERVED16;
27290 
27291     union
27292     {
27293         __IOM uint32_t ADSHSTR0;       /*!< (@ 0x00000288) Channel-Dedicated Sample & Hold Circuit State
27294                                         *                  Register 0                                                 */
27295 
27296         struct
27297         {
27298             __IOM uint32_t SHSST : 8;  /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Unit 0 to 2              */
27299             uint32_t             : 8;
27300             __IOM uint32_t SHHST : 3;  /*!< [18..16] Channel-Dedicated Sample-and-Hold Circuit Unit 0 to
27301                                         *   2                                                                         */
27302             uint32_t : 13;
27303         } ADSHSTR0_b;
27304     };
27305 
27306     union
27307     {
27308         __IOM uint32_t ADSHCR1;        /*!< (@ 0x0000028C) Channel-Dedicated Sample-and-Hold Circuit Control
27309                                         *                  Register 1                                                 */
27310 
27311         struct
27312         {
27313             __IOM uint32_t SHEN4 : 1;  /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Unit 4 Select            */
27314             __IOM uint32_t SHEN5 : 1;  /*!< [1..1] Channel-Dedicated Sample-and-Hold Circuit Unit 5 Select            */
27315             __IOM uint32_t SHEN6 : 1;  /*!< [2..2] Channel-Dedicated Sample-and-Hold Circuit Unit 6 Select            */
27316             uint32_t             : 29;
27317         } ADSHCR1_b;
27318     };
27319     __IM uint32_t RESERVED17;
27320 
27321     union
27322     {
27323         __IOM uint32_t ADSHSTR1;       /*!< (@ 0x00000294) Channel-Dedicated Sample & Hold Circuit State
27324                                         *                  Register 1                                                 */
27325 
27326         struct
27327         {
27328             __IOM uint32_t SHSST : 8;  /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Unit 4 to 6              */
27329             uint32_t             : 8;
27330             __IOM uint32_t SHHST : 3;  /*!< [18..16] Channel-Dedicated Sample-and-Hold Circuit Unit 4 to
27331                                         *   6                                                                         */
27332             uint32_t : 13;
27333         } ADSHSTR1_b;
27334     };
27335     __IM uint32_t RESERVED18[6];
27336 
27337     union
27338     {
27339         __IOM uint32_t ADCALSHCR;        /*!< (@ 0x000002B0) Channel-Dedicated Sample & Hold Circuit Calibration
27340                                           *                  State Register                                             */
27341 
27342         struct
27343         {
27344             __IOM uint32_t CALSHSST : 8; /*!< [7..0] Channel-Dedicated Sample & Hold Circuit Calibration Sampling
27345                                           *   Time Configuration                                                        */
27346             uint32_t                : 8;
27347             __IOM uint32_t CALSHHST : 3; /*!< [18..16] Channel-Dedicated Sample & Hold Circuit Calibration
27348                                           *   Holding Time Configuration                                                */
27349             uint32_t : 13;
27350         } ADCALSHCR_b;
27351     };
27352     __IM uint32_t RESERVED19[3];
27353 
27354     union
27355     {
27356         __IOM uint32_t ADPGACR[4];     /*!< (@ 0x000002C0) Programmable Gain Amplifier Control Register
27357                                         *                  [0..3]                                                     */
27358 
27359         struct
27360         {
27361             uint32_t                : 1;
27362             __IOM uint32_t PGADEN   : 1; /*!< [1..1] PGA Unit n Input Mode Select                                       */
27363             __IOM uint32_t PGASEL1  : 1; /*!< [2..2] PGA Unit n Transit Enable                                          */
27364             __IOM uint32_t PGAENAMP : 1; /*!< [3..3] PGA Unit n Enable                                                  */
27365             uint32_t                : 12;
27366             __IOM uint32_t PGAGEN   : 1; /*!< [16..16] PGA Unit n Gain Setting Enable                                   */
27367             uint32_t                : 3;
27368             __IOM uint32_t PGADG    : 2; /*!< [21..20] PGA Unit n Differential Input Gain Setting                       */
27369             uint32_t                : 2;
27370             __IOM uint32_t PGAGAIN  : 4; /*!< [27..24] PGA Unit n Gain Setting                                          */
27371             uint32_t                : 4;
27372         } ADPGACR_b[4];
27373     };
27374     __IM uint32_t RESERVED20[12];
27375 
27376     union
27377     {
27378         __IOM uint32_t ADPGAMONCR;      /*!< (@ 0x00000300) Programable Gain Amp Monitor Output Control Register       */
27379 
27380         struct
27381         {
27382             __IOM uint32_t PGAMON  : 3; /*!< [2..0] PGA Monitor Signal Selection                                       */
27383             uint32_t               : 13;
27384             __IOM uint32_t MONSEL0 : 1; /*!< [16..16] PGA Unit 0 Monitor Output Enable                                 */
27385             __IOM uint32_t MONSEL1 : 1; /*!< [17..17] PGA Unit 1 Monitor Output Enable                                 */
27386             __IOM uint32_t MONSEL2 : 1; /*!< [18..18] PGA Unit 2 Monitor Output Enable                                 */
27387             __IOM uint32_t MONSEL3 : 1; /*!< [19..19] PGA Unit 3 Monitor Output Enable                                 */
27388             uint32_t               : 12;
27389         } ADPGAMONCR_b;
27390     };
27391     __IM uint32_t RESERVED21[7];
27392 
27393     union
27394     {
27395         __IOM uint32_t ADREFCR;        /*!< (@ 0x00000320) Internal Reference Voltage Monitor Enable Register         */
27396 
27397         struct
27398         {
27399             __IOM uint32_t VDE : 1;    /*!< [0..0] Internal Reference Voltage A/D Conversion Select                   */
27400             uint32_t           : 31;
27401         } ADREFCR_b;
27402     };
27403     __IM uint32_t RESERVED22[15];
27404 
27405     union
27406     {
27407         __IOM uint32_t ADUOFTR0;        /*!< (@ 0x00000360) User Offset Table Register 0                               */
27408 
27409         struct
27410         {
27411             __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n                                               */
27412             uint32_t              : 16;
27413         } ADUOFTR0_b;
27414     };
27415 
27416     union
27417     {
27418         __IOM uint32_t ADUOFTR1;        /*!< (@ 0x00000364) User Offset Table Register 1                               */
27419 
27420         struct
27421         {
27422             __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n                                               */
27423             uint32_t              : 16;
27424         } ADUOFTR1_b;
27425     };
27426 
27427     union
27428     {
27429         __IOM uint32_t ADUOFTR2;        /*!< (@ 0x00000368) User Offset Table Register 2                               */
27430 
27431         struct
27432         {
27433             __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n                                               */
27434             uint32_t              : 16;
27435         } ADUOFTR2_b;
27436     };
27437 
27438     union
27439     {
27440         __IOM uint32_t ADUOFTR3;        /*!< (@ 0x0000036C) User Offset Table Register 3                               */
27441 
27442         struct
27443         {
27444             __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n                                               */
27445             uint32_t              : 16;
27446         } ADUOFTR3_b;
27447     };
27448 
27449     union
27450     {
27451         __IOM uint32_t ADUOFTR4;        /*!< (@ 0x00000370) User Offset Table Register 4                               */
27452 
27453         struct
27454         {
27455             __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n                                               */
27456             uint32_t              : 16;
27457         } ADUOFTR4_b;
27458     };
27459 
27460     union
27461     {
27462         __IOM uint32_t ADUOFTR5;        /*!< (@ 0x00000374) User Offset Table Register 5                               */
27463 
27464         struct
27465         {
27466             __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n                                               */
27467             uint32_t              : 16;
27468         } ADUOFTR5_b;
27469     };
27470 
27471     union
27472     {
27473         __IOM uint32_t ADUOFTR6;        /*!< (@ 0x00000378) User Offset Table Register 6                               */
27474 
27475         struct
27476         {
27477             __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n                                               */
27478             uint32_t              : 16;
27479         } ADUOFTR6_b;
27480     };
27481 
27482     union
27483     {
27484         __IOM uint32_t ADUOFTR7;        /*!< (@ 0x0000037C) User Offset Table Register 7                               */
27485 
27486         struct
27487         {
27488             __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n                                               */
27489             uint32_t              : 16;
27490         } ADUOFTR7_b;
27491     };
27492 
27493     union
27494     {
27495         __IOM uint32_t ADUGTR0;        /*!< (@ 0x00000380) User Gain Table Register 0                                 */
27496 
27497         struct
27498         {
27499             __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n                                                 */
27500             uint32_t             : 8;
27501         } ADUGTR0_b;
27502     };
27503 
27504     union
27505     {
27506         __IOM uint32_t ADUGTR1;        /*!< (@ 0x00000384) User Gain Table Register 1                                 */
27507 
27508         struct
27509         {
27510             __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n                                                 */
27511             uint32_t             : 8;
27512         } ADUGTR1_b;
27513     };
27514 
27515     union
27516     {
27517         __IOM uint32_t ADUGTR2;        /*!< (@ 0x00000388) User Gain Table Register 2                                 */
27518 
27519         struct
27520         {
27521             __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n                                                 */
27522             uint32_t             : 8;
27523         } ADUGTR2_b;
27524     };
27525 
27526     union
27527     {
27528         __IOM uint32_t ADUGTR3;        /*!< (@ 0x0000038C) User Gain Table Register 3                                 */
27529 
27530         struct
27531         {
27532             __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n                                                 */
27533             uint32_t             : 8;
27534         } ADUGTR3_b;
27535     };
27536 
27537     union
27538     {
27539         __IOM uint32_t ADUGTR4;        /*!< (@ 0x00000390) User Gain Table Register 4                                 */
27540 
27541         struct
27542         {
27543             __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n                                                 */
27544             uint32_t             : 8;
27545         } ADUGTR4_b;
27546     };
27547 
27548     union
27549     {
27550         __IOM uint32_t ADUGTR5;        /*!< (@ 0x00000394) User Gain Table Register 5                                 */
27551 
27552         struct
27553         {
27554             __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n                                                 */
27555             uint32_t             : 8;
27556         } ADUGTR5_b;
27557     };
27558 
27559     union
27560     {
27561         __IOM uint32_t ADUGTR6;        /*!< (@ 0x00000398) User Gain Table Register 6                                 */
27562 
27563         struct
27564         {
27565             __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n                                                 */
27566             uint32_t             : 8;
27567         } ADUGTR6_b;
27568     };
27569 
27570     union
27571     {
27572         __IOM uint32_t ADUGTR7;        /*!< (@ 0x0000039C) User Gain Table Register 7                                 */
27573 
27574         struct
27575         {
27576             __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n                                                 */
27577             uint32_t             : 8;
27578         } ADUGTR7_b;
27579     };
27580 
27581     union
27582     {
27583         __IOM uint32_t ADLIMINTCR;     /*!< (@ 0x000003A0) Limiter Clip Interrupt Enable Register                     */
27584 
27585         struct
27586         {
27587             __IOM uint32_t LIMIEn : 9; /*!< [8..0] Limiter Clip Interrupt n Enable bit                                */
27588             uint32_t              : 23;
27589         } ADLIMINTCR_b;
27590     };
27591 
27592     union
27593     {
27594         __IOM uint32_t ADLIMTR0;       /*!< (@ 0x000003A4) Limiter Clip Table Register 0                              */
27595 
27596         struct
27597         {
27598             __IOM uint32_t LIML : 16;  /*!< [15..0] Limiter clip table n : Lower-side limit value                     */
27599             __IOM uint32_t LIMU : 16;  /*!< [31..16] Limiter clip table n : Upper-side limit value                    */
27600         } ADLIMTR0_b;
27601     };
27602 
27603     union
27604     {
27605         __IOM uint32_t ADLIMTR1;       /*!< (@ 0x000003A8) Limiter Clip Table Register 1                              */
27606 
27607         struct
27608         {
27609             __IOM uint32_t LIML : 16;  /*!< [15..0] Limiter clip table n : Lower-side limit value                     */
27610             __IOM uint32_t LIMU : 16;  /*!< [31..16] Limiter clip table n : Upper-side limit value                    */
27611         } ADLIMTR1_b;
27612     };
27613 
27614     union
27615     {
27616         __IOM uint32_t ADLIMTR2;       /*!< (@ 0x000003AC) Limiter Clip Table Register 2                              */
27617 
27618         struct
27619         {
27620             __IOM uint32_t LIML : 16;  /*!< [15..0] Limiter clip table n : Lower-side limit value                     */
27621             __IOM uint32_t LIMU : 16;  /*!< [31..16] Limiter clip table n : Upper-side limit value                    */
27622         } ADLIMTR2_b;
27623     };
27624 
27625     union
27626     {
27627         __IOM uint32_t ADLIMTR3;       /*!< (@ 0x000003B0) Limiter Clip Table Register 3                              */
27628 
27629         struct
27630         {
27631             __IOM uint32_t LIML : 16;  /*!< [15..0] Limiter clip table n : Lower-side limit value                     */
27632             __IOM uint32_t LIMU : 16;  /*!< [31..16] Limiter clip table n : Upper-side limit value                    */
27633         } ADLIMTR3_b;
27634     };
27635 
27636     union
27637     {
27638         __IOM uint32_t ADLIMTR4;       /*!< (@ 0x000003B4) Limiter Clip Table Register 4                              */
27639 
27640         struct
27641         {
27642             __IOM uint32_t LIML : 16;  /*!< [15..0] Limiter clip table n : Lower-side limit value                     */
27643             __IOM uint32_t LIMU : 16;  /*!< [31..16] Limiter clip table n : Upper-side limit value                    */
27644         } ADLIMTR4_b;
27645     };
27646 
27647     union
27648     {
27649         __IOM uint32_t ADLIMTR5;       /*!< (@ 0x000003B8) Limiter Clip Table Register 5                              */
27650 
27651         struct
27652         {
27653             __IOM uint32_t LIML : 16;  /*!< [15..0] Limiter clip table n : Lower-side limit value                     */
27654             __IOM uint32_t LIMU : 16;  /*!< [31..16] Limiter clip table n : Upper-side limit value                    */
27655         } ADLIMTR5_b;
27656     };
27657 
27658     union
27659     {
27660         __IOM uint32_t ADLIMTR6;       /*!< (@ 0x000003BC) Limiter Clip Table Register 6                              */
27661 
27662         struct
27663         {
27664             __IOM uint32_t LIML : 16;  /*!< [15..0] Limiter clip table n : Lower-side limit value                     */
27665             __IOM uint32_t LIMU : 16;  /*!< [31..16] Limiter clip table n : Upper-side limit value                    */
27666         } ADLIMTR6_b;
27667     };
27668 
27669     union
27670     {
27671         __IOM uint32_t ADLIMTR7;       /*!< (@ 0x000003C0) Limiter Clip Table Register 7                              */
27672 
27673         struct
27674         {
27675             __IOM uint32_t LIML : 16;  /*!< [15..0] Limiter clip table n : Lower-side limit value                     */
27676             __IOM uint32_t LIMU : 16;  /*!< [31..16] Limiter clip table n : Upper-side limit value                    */
27677         } ADLIMTR7_b;
27678     };
27679     __IM uint32_t RESERVED23[15];
27680 
27681     union
27682     {
27683         __IOM uint32_t ADCMPENR;       /*!< (@ 0x00000400) Compare Match Enable Register                              */
27684 
27685         struct
27686         {
27687             __IOM uint32_t CMPENn : 8; /*!< [7..0] Compare Match n Enable                                             */
27688             uint32_t              : 24;
27689         } ADCMPENR_b;
27690     };
27691 
27692     union
27693     {
27694         __IOM uint32_t ADCMPINTCR;     /*!< (@ 0x00000404) Compare Match Interrupt Enable Register                    */
27695 
27696         struct
27697         {
27698             __IOM uint32_t CMPIEn : 4; /*!< [3..0] Compare Match Interrupt n Enable                                   */
27699             uint32_t              : 28;
27700         } ADCMPINTCR_b;
27701     };
27702 
27703     union
27704     {
27705         __IOM uint32_t ADCCMPCR0;        /*!< (@ 0x00000408) Composite Compare Match Configuration Register
27706                                           *                  0                                                          */
27707 
27708         struct
27709         {
27710             __IOM uint32_t CCMPCND  : 2; /*!< [1..0] Composite Compare Match Condition Selection                        */
27711             uint32_t                : 14;
27712             __IOM uint32_t CCMPTBLm : 8; /*!< [23..16] Composite Compare Match Condition Table Selection                */
27713             uint32_t                : 8;
27714         } ADCCMPCR0_b;
27715     };
27716 
27717     union
27718     {
27719         __IOM uint32_t ADCCMPCR1;        /*!< (@ 0x0000040C) Composite Compare Match Configuration Register
27720                                           *                  1                                                          */
27721 
27722         struct
27723         {
27724             __IOM uint32_t CCMPCND  : 2; /*!< [1..0] Composite Compare Match Condition Selection                        */
27725             uint32_t                : 14;
27726             __IOM uint32_t CCMPTBLm : 8; /*!< [23..16] Composite Compare Match Condition Table Selection                */
27727             uint32_t                : 8;
27728         } ADCCMPCR1_b;
27729     };
27730     __IM uint32_t RESERVED24[14];
27731 
27732     union
27733     {
27734         __IOM uint32_t ADCMPMDR0;      /*!< (@ 0x00000448) Compare Match Mode Selection Register 0                    */
27735 
27736         struct
27737         {
27738             __IOM uint32_t CMPMD0 : 2; /*!< [1..0] Compare Match 0 : Match Mode Selection                             */
27739             uint32_t              : 6;
27740             __IOM uint32_t CMPMD1 : 2; /*!< [9..8] Compare Match 1 : Match Mode Selection                             */
27741             uint32_t              : 6;
27742             __IOM uint32_t CMPMD2 : 2; /*!< [17..16] Compare Match 2 : Match Mode Selection                           */
27743             uint32_t              : 6;
27744             __IOM uint32_t CMPMD3 : 2; /*!< [25..24] Compare Match 3 : Match Mode Selection                           */
27745             uint32_t              : 6;
27746         } ADCMPMDR0_b;
27747     };
27748 
27749     union
27750     {
27751         __IOM uint32_t ADCMPMDR1;      /*!< (@ 0x0000044C) Compare Match Mode Selection Register 1                    */
27752 
27753         struct
27754         {
27755             __IOM uint32_t CMPMD4 : 2; /*!< [1..0] Compare Match 4 : Match Mode Selection                             */
27756             uint32_t              : 6;
27757             __IOM uint32_t CMPMD5 : 2; /*!< [9..8] Compare Match 5 : Match Mode Selection                             */
27758             uint32_t              : 6;
27759             __IOM uint32_t CMPMD6 : 2; /*!< [17..16] Compare Match 6 : Match Mode Selection                           */
27760             uint32_t              : 6;
27761             __IOM uint32_t CMPMD7 : 2; /*!< [25..24] Compare Match 7 : Match Mode Selection                           */
27762             uint32_t              : 6;
27763         } ADCMPMDR1_b;
27764     };
27765     __IM uint32_t RESERVED25[2];
27766 
27767     union
27768     {
27769         __IOM uint32_t ADCMPTBR0;       /*!< (@ 0x00000458) Compare Match Table Register 0                             */
27770 
27771         struct
27772         {
27773             __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level                            */
27774             __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level                          */
27775         } ADCMPTBR0_b;
27776     };
27777 
27778     union
27779     {
27780         __IOM uint32_t ADCMPTBR1;       /*!< (@ 0x0000045C) Compare Match Table Register 1                             */
27781 
27782         struct
27783         {
27784             __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level                            */
27785             __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level                          */
27786         } ADCMPTBR1_b;
27787     };
27788 
27789     union
27790     {
27791         __IOM uint32_t ADCMPTBR2;       /*!< (@ 0x00000460) Compare Match Table Register 2                             */
27792 
27793         struct
27794         {
27795             __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level                            */
27796             __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level                          */
27797         } ADCMPTBR2_b;
27798     };
27799 
27800     union
27801     {
27802         __IOM uint32_t ADCMPTBR3;       /*!< (@ 0x00000464) Compare Match Table Register 3                             */
27803 
27804         struct
27805         {
27806             __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level                            */
27807             __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level                          */
27808         } ADCMPTBR3_b;
27809     };
27810 
27811     union
27812     {
27813         __IOM uint32_t ADCMPTBR4;       /*!< (@ 0x00000468) Compare Match Table Register 4                             */
27814 
27815         struct
27816         {
27817             __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level                            */
27818             __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level                          */
27819         } ADCMPTBR4_b;
27820     };
27821 
27822     union
27823     {
27824         __IOM uint32_t ADCMPTBR5;       /*!< (@ 0x0000046C) Compare Match Table Register 5                             */
27825 
27826         struct
27827         {
27828             __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level                            */
27829             __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level                          */
27830         } ADCMPTBR5_b;
27831     };
27832 
27833     union
27834     {
27835         __IOM uint32_t ADCMPTBR6;       /*!< (@ 0x00000470) Compare Match Table Register 6                             */
27836 
27837         struct
27838         {
27839             __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level                            */
27840             __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level                          */
27841         } ADCMPTBR6_b;
27842     };
27843 
27844     union
27845     {
27846         __IOM uint32_t ADCMPTBR7;       /*!< (@ 0x00000474) Compare Match Table Register 7                             */
27847 
27848         struct
27849         {
27850             __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level                            */
27851             __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level                          */
27852         } ADCMPTBR7_b;
27853     };
27854     __IM uint32_t RESERVED26[18];
27855 
27856     union
27857     {
27858         __IOM uint32_t ADFIFOCR;        /*!< (@ 0x000004C0) FIFO Control Register                                      */
27859 
27860         struct
27861         {
27862             __IOM uint32_t FIFOEN0 : 1; /*!< [0..0] Scan Group 0 FIFO Enable                                           */
27863             __IOM uint32_t FIFOEN1 : 1; /*!< [1..1] Scan Group 1 FIFO Enable                                           */
27864             __IOM uint32_t FIFOEN2 : 1; /*!< [2..2] Scan Group 2 FIFO Enable                                           */
27865             __IOM uint32_t FIFOEN3 : 1; /*!< [3..3] Scan Group 3 FIFO Enable                                           */
27866             __IOM uint32_t FIFOEN4 : 1; /*!< [4..4] Scan Group 4 FIFO Enable                                           */
27867             __IOM uint32_t FIFOEN5 : 1; /*!< [5..5] Scan Group 5 FIFO Enable                                           */
27868             __IOM uint32_t FIFOEN6 : 1; /*!< [6..6] Scan Group 6 FIFO Enable                                           */
27869             __IOM uint32_t FIFOEN7 : 1; /*!< [7..7] Scan Group 7 FIFO Enable                                           */
27870             __IOM uint32_t FIFOEN8 : 1; /*!< [8..8] Scan Group 8 FIFO Enable                                           */
27871             uint32_t               : 23;
27872         } ADFIFOCR_b;
27873     };
27874 
27875     union
27876     {
27877         __IOM uint32_t ADFIFOINTCR;     /*!< (@ 0x000004C4) FIFO Interrupt Control Register                            */
27878 
27879         struct
27880         {
27881             __IOM uint32_t FIFOIE0 : 1; /*!< [0..0] Scan Group 0 FIFO Interrupt Enable                                 */
27882             __IOM uint32_t FIFOIE1 : 1; /*!< [1..1] Scan Group 1 FIFO Interrupt Enable                                 */
27883             __IOM uint32_t FIFOIE2 : 1; /*!< [2..2] Scan Group 2 FIFO Interrupt Enable                                 */
27884             __IOM uint32_t FIFOIE3 : 1; /*!< [3..3] Scan Group 3 FIFO Interrupt Enable                                 */
27885             __IOM uint32_t FIFOIE4 : 1; /*!< [4..4] Scan Group 4 FIFO Interrupt Enable                                 */
27886             __IOM uint32_t FIFOIE5 : 1; /*!< [5..5] Scan Group 5 FIFO Interrupt Enable                                 */
27887             __IOM uint32_t FIFOIE6 : 1; /*!< [6..6] Scan Group 6 FIFO Interrupt Enable                                 */
27888             __IOM uint32_t FIFOIE7 : 1; /*!< [7..7] Scan Group 7 FIFO Interrupt Enable                                 */
27889             __IOM uint32_t FIFOIE8 : 1; /*!< [8..8] Scan Group 8 FIFO Interrupt Enable                                 */
27890             uint32_t               : 23;
27891         } ADFIFOINTCR_b;
27892     };
27893 
27894     union
27895     {
27896         __IOM uint32_t ADFIFOINTLR0;     /*!< (@ 0x000004C8) FIFO Interrupt Generation Level Register 0                 */
27897 
27898         struct
27899         {
27900             __IOM uint32_t FIFOILV0 : 4; /*!< [3..0] Scan Group 0 FIFO Interrupt Output Timing Setting                  */
27901             uint32_t                : 12;
27902             __IOM uint32_t FIFOILV1 : 4; /*!< [19..16] Scan Group 1 FIFO Interrupt Output Timing Setting                */
27903             uint32_t                : 12;
27904         } ADFIFOINTLR0_b;
27905     };
27906 
27907     union
27908     {
27909         __IOM uint32_t ADFIFOINTLR1;     /*!< (@ 0x000004CC) FIFO Interrupt Generation Level Register 1                 */
27910 
27911         struct
27912         {
27913             __IOM uint32_t FIFOILV2 : 4; /*!< [3..0] Scan Group 2 FIFO Interrupt Output Timing Setting                  */
27914             uint32_t                : 12;
27915             __IOM uint32_t FIFOILV3 : 4; /*!< [19..16] Scan Group 3 FIFO Interrupt Output Timing Setting                */
27916             uint32_t                : 12;
27917         } ADFIFOINTLR1_b;
27918     };
27919 
27920     union
27921     {
27922         __IOM uint32_t ADFIFOINTLR2;     /*!< (@ 0x000004D0) FIFO Interrupt Generation Level Register 2                 */
27923 
27924         struct
27925         {
27926             __IOM uint32_t FIFOILV4 : 4; /*!< [3..0] Scan Group 4 FIFO Interrupt Output Timing Setting                  */
27927             uint32_t                : 12;
27928             __IOM uint32_t FIFOILV5 : 4; /*!< [19..16] Scan Group 5 FIFO Interrupt Output Timing Setting                */
27929             uint32_t                : 12;
27930         } ADFIFOINTLR2_b;
27931     };
27932 
27933     union
27934     {
27935         __IOM uint32_t ADFIFOINTLR3;     /*!< (@ 0x000004D4) FIFO Interrupt Generation Level Register 3                 */
27936 
27937         struct
27938         {
27939             __IOM uint32_t FIFOILV6 : 4; /*!< [3..0] Scan Group 6 FIFO Interrupt Output Timing Setting                  */
27940             uint32_t                : 12;
27941             __IOM uint32_t FIFOILV7 : 4; /*!< [19..16] Scan Group 7 FIFO Interrupt Output Timing Setting                */
27942             uint32_t                : 12;
27943         } ADFIFOINTLR3_b;
27944     };
27945 
27946     union
27947     {
27948         __IOM uint32_t ADFIFOINTLR4;     /*!< (@ 0x000004D8) FIFO Interrupt Generation Level Register 4                 */
27949 
27950         struct
27951         {
27952             __IOM uint32_t FIFOILV8 : 4; /*!< [3..0] Scan Group 8 FIFO Interrupt Output Timing Setting                  */
27953             uint32_t                : 28;
27954         } ADFIFOINTLR4_b;
27955     };
27956     __IM uint32_t RESERVED27[73];
27957 
27958     union
27959     {
27960         __IOM uint32_t ADCHCR0;        /*!< (@ 0x00000600) A/D Conversion Channel Configuration Register
27961                                         *                  0                                                          */
27962 
27963         struct
27964         {
27965             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
27966             uint32_t              : 3;
27967             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
27968             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
27969             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
27970             uint32_t              : 12;
27971         } ADCHCR0_b;
27972     };
27973 
27974     union
27975     {
27976         __IOM uint32_t ADDOPCRA0;      /*!< (@ 0x00000604) A/D Conversion Data Operation Control A Register
27977                                         *                  0                                                          */
27978 
27979         struct
27980         {
27981             uint32_t                : 16;
27982             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
27983             uint32_t                : 4;
27984             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
27985             uint32_t                : 4;
27986         } ADDOPCRA0_b;
27987     };
27988 
27989     union
27990     {
27991         __IOM uint32_t ADDOPCRB0;        /*!< (@ 0x00000608) A/D Conversion Data Operation Control B Register
27992                                           *                  0                                                          */
27993 
27994         struct
27995         {
27996             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
27997             uint32_t                : 6;
27998             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
27999             uint32_t                : 4;
28000             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
28001             uint32_t                : 8;
28002         } ADDOPCRB0_b;
28003     };
28004 
28005     union
28006     {
28007         __IOM uint32_t ADDOPCRC0;       /*!< (@ 0x0000060C) A/D Conversion Data Operation Control C Register
28008                                          *                  0                                                          */
28009 
28010         struct
28011         {
28012             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
28013             uint32_t               : 12;
28014             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
28015             uint32_t               : 2;
28016             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
28017             uint32_t               : 11;
28018         } ADDOPCRC0_b;
28019     };
28020 
28021     union
28022     {
28023         __IOM uint32_t ADCHCR1;        /*!< (@ 0x00000610) A/D Conversion Channel Configuration Register
28024                                         *                  1                                                          */
28025 
28026         struct
28027         {
28028             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
28029             uint32_t              : 3;
28030             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
28031             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
28032             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
28033             uint32_t              : 12;
28034         } ADCHCR1_b;
28035     };
28036 
28037     union
28038     {
28039         __IOM uint32_t ADDOPCRA1;      /*!< (@ 0x00000614) A/D Conversion Data Operation Control A Register
28040                                         *                  1                                                          */
28041 
28042         struct
28043         {
28044             uint32_t                : 16;
28045             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
28046             uint32_t                : 4;
28047             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
28048             uint32_t                : 4;
28049         } ADDOPCRA1_b;
28050     };
28051 
28052     union
28053     {
28054         __IOM uint32_t ADDOPCRB1;        /*!< (@ 0x00000618) A/D Conversion Data Operation Control B Register
28055                                           *                  1                                                          */
28056 
28057         struct
28058         {
28059             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
28060             uint32_t                : 6;
28061             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
28062             uint32_t                : 4;
28063             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
28064             uint32_t                : 8;
28065         } ADDOPCRB1_b;
28066     };
28067 
28068     union
28069     {
28070         __IOM uint32_t ADDOPCRC1;       /*!< (@ 0x0000061C) A/D Conversion Data Operation Control C Register
28071                                          *                  1                                                          */
28072 
28073         struct
28074         {
28075             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
28076             uint32_t               : 12;
28077             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
28078             uint32_t               : 2;
28079             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
28080             uint32_t               : 11;
28081         } ADDOPCRC1_b;
28082     };
28083 
28084     union
28085     {
28086         __IOM uint32_t ADCHCR2;        /*!< (@ 0x00000620) A/D Conversion Channel Configuration Register
28087                                         *                  2                                                          */
28088 
28089         struct
28090         {
28091             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
28092             uint32_t              : 3;
28093             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
28094             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
28095             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
28096             uint32_t              : 12;
28097         } ADCHCR2_b;
28098     };
28099 
28100     union
28101     {
28102         __IOM uint32_t ADDOPCRA2;      /*!< (@ 0x00000624) A/D Conversion Data Operation Control A Register
28103                                         *                  2                                                          */
28104 
28105         struct
28106         {
28107             uint32_t                : 16;
28108             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
28109             uint32_t                : 4;
28110             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
28111             uint32_t                : 4;
28112         } ADDOPCRA2_b;
28113     };
28114 
28115     union
28116     {
28117         __IOM uint32_t ADDOPCRB2;        /*!< (@ 0x00000628) A/D Conversion Data Operation Control B Register
28118                                           *                  2                                                          */
28119 
28120         struct
28121         {
28122             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
28123             uint32_t                : 6;
28124             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
28125             uint32_t                : 4;
28126             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
28127             uint32_t                : 8;
28128         } ADDOPCRB2_b;
28129     };
28130 
28131     union
28132     {
28133         __IOM uint32_t ADDOPCRC2;       /*!< (@ 0x0000062C) A/D Conversion Data Operation Control C Register
28134                                          *                  2                                                          */
28135 
28136         struct
28137         {
28138             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
28139             uint32_t               : 12;
28140             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
28141             uint32_t               : 2;
28142             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
28143             uint32_t               : 11;
28144         } ADDOPCRC2_b;
28145     };
28146 
28147     union
28148     {
28149         __IOM uint32_t ADCHCR3;        /*!< (@ 0x00000630) A/D Conversion Channel Configuration Register
28150                                         *                  3                                                          */
28151 
28152         struct
28153         {
28154             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
28155             uint32_t              : 3;
28156             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
28157             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
28158             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
28159             uint32_t              : 12;
28160         } ADCHCR3_b;
28161     };
28162 
28163     union
28164     {
28165         __IOM uint32_t ADDOPCRA3;      /*!< (@ 0x00000634) A/D Conversion Data Operation Control A Register
28166                                         *                  3                                                          */
28167 
28168         struct
28169         {
28170             uint32_t                : 16;
28171             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
28172             uint32_t                : 4;
28173             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
28174             uint32_t                : 4;
28175         } ADDOPCRA3_b;
28176     };
28177 
28178     union
28179     {
28180         __IOM uint32_t ADDOPCRB3;        /*!< (@ 0x00000638) A/D Conversion Data Operation Control B Register
28181                                           *                  3                                                          */
28182 
28183         struct
28184         {
28185             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
28186             uint32_t                : 6;
28187             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
28188             uint32_t                : 4;
28189             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
28190             uint32_t                : 8;
28191         } ADDOPCRB3_b;
28192     };
28193 
28194     union
28195     {
28196         __IOM uint32_t ADDOPCRC3;       /*!< (@ 0x0000063C) A/D Conversion Data Operation Control C Register
28197                                          *                  3                                                          */
28198 
28199         struct
28200         {
28201             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
28202             uint32_t               : 12;
28203             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
28204             uint32_t               : 2;
28205             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
28206             uint32_t               : 11;
28207         } ADDOPCRC3_b;
28208     };
28209 
28210     union
28211     {
28212         __IOM uint32_t ADCHCR4;        /*!< (@ 0x00000640) A/D Conversion Channel Configuration Register
28213                                         *                  4                                                          */
28214 
28215         struct
28216         {
28217             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
28218             uint32_t              : 3;
28219             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
28220             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
28221             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
28222             uint32_t              : 12;
28223         } ADCHCR4_b;
28224     };
28225 
28226     union
28227     {
28228         __IOM uint32_t ADDOPCRA4;      /*!< (@ 0x00000644) A/D Conversion Data Operation Control A Register
28229                                         *                  4                                                          */
28230 
28231         struct
28232         {
28233             uint32_t                : 16;
28234             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
28235             uint32_t                : 4;
28236             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
28237             uint32_t                : 4;
28238         } ADDOPCRA4_b;
28239     };
28240 
28241     union
28242     {
28243         __IOM uint32_t ADDOPCRB4;        /*!< (@ 0x00000648) A/D Conversion Data Operation Control B Register
28244                                           *                  4                                                          */
28245 
28246         struct
28247         {
28248             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
28249             uint32_t                : 6;
28250             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
28251             uint32_t                : 4;
28252             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
28253             uint32_t                : 8;
28254         } ADDOPCRB4_b;
28255     };
28256 
28257     union
28258     {
28259         __IOM uint32_t ADDOPCRC4;       /*!< (@ 0x0000064C) A/D Conversion Data Operation Control C Register
28260                                          *                  4                                                          */
28261 
28262         struct
28263         {
28264             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
28265             uint32_t               : 12;
28266             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
28267             uint32_t               : 2;
28268             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
28269             uint32_t               : 11;
28270         } ADDOPCRC4_b;
28271     };
28272 
28273     union
28274     {
28275         __IOM uint32_t ADCHCR5;        /*!< (@ 0x00000650) A/D Conversion Channel Configuration Register
28276                                         *                  5                                                          */
28277 
28278         struct
28279         {
28280             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
28281             uint32_t              : 3;
28282             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
28283             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
28284             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
28285             uint32_t              : 12;
28286         } ADCHCR5_b;
28287     };
28288 
28289     union
28290     {
28291         __IOM uint32_t ADDOPCRA5;      /*!< (@ 0x00000654) A/D Conversion Data Operation Control A Register
28292                                         *                  5                                                          */
28293 
28294         struct
28295         {
28296             uint32_t                : 16;
28297             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
28298             uint32_t                : 4;
28299             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
28300             uint32_t                : 4;
28301         } ADDOPCRA5_b;
28302     };
28303 
28304     union
28305     {
28306         __IOM uint32_t ADDOPCRB5;        /*!< (@ 0x00000658) A/D Conversion Data Operation Control B Register
28307                                           *                  5                                                          */
28308 
28309         struct
28310         {
28311             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
28312             uint32_t                : 6;
28313             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
28314             uint32_t                : 4;
28315             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
28316             uint32_t                : 8;
28317         } ADDOPCRB5_b;
28318     };
28319 
28320     union
28321     {
28322         __IOM uint32_t ADDOPCRC5;       /*!< (@ 0x0000065C) A/D Conversion Data Operation Control C Register
28323                                          *                  5                                                          */
28324 
28325         struct
28326         {
28327             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
28328             uint32_t               : 12;
28329             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
28330             uint32_t               : 2;
28331             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
28332             uint32_t               : 11;
28333         } ADDOPCRC5_b;
28334     };
28335 
28336     union
28337     {
28338         __IOM uint32_t ADCHCR6;        /*!< (@ 0x00000660) A/D Conversion Channel Configuration Register
28339                                         *                  6                                                          */
28340 
28341         struct
28342         {
28343             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
28344             uint32_t              : 3;
28345             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
28346             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
28347             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
28348             uint32_t              : 12;
28349         } ADCHCR6_b;
28350     };
28351 
28352     union
28353     {
28354         __IOM uint32_t ADDOPCRA6;      /*!< (@ 0x00000664) A/D Conversion Data Operation Control A Register
28355                                         *                  6                                                          */
28356 
28357         struct
28358         {
28359             uint32_t                : 16;
28360             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
28361             uint32_t                : 4;
28362             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
28363             uint32_t                : 4;
28364         } ADDOPCRA6_b;
28365     };
28366 
28367     union
28368     {
28369         __IOM uint32_t ADDOPCRB6;        /*!< (@ 0x00000668) A/D Conversion Data Operation Control B Register
28370                                           *                  6                                                          */
28371 
28372         struct
28373         {
28374             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
28375             uint32_t                : 6;
28376             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
28377             uint32_t                : 4;
28378             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
28379             uint32_t                : 8;
28380         } ADDOPCRB6_b;
28381     };
28382 
28383     union
28384     {
28385         __IOM uint32_t ADDOPCRC6;       /*!< (@ 0x0000066C) A/D Conversion Data Operation Control C Register
28386                                          *                  6                                                          */
28387 
28388         struct
28389         {
28390             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
28391             uint32_t               : 12;
28392             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
28393             uint32_t               : 2;
28394             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
28395             uint32_t               : 11;
28396         } ADDOPCRC6_b;
28397     };
28398 
28399     union
28400     {
28401         __IOM uint32_t ADCHCR7;        /*!< (@ 0x00000670) A/D Conversion Channel Configuration Register
28402                                         *                  7                                                          */
28403 
28404         struct
28405         {
28406             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
28407             uint32_t              : 3;
28408             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
28409             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
28410             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
28411             uint32_t              : 12;
28412         } ADCHCR7_b;
28413     };
28414 
28415     union
28416     {
28417         __IOM uint32_t ADDOPCRA7;      /*!< (@ 0x00000674) A/D Conversion Data Operation Control A Register
28418                                         *                  7                                                          */
28419 
28420         struct
28421         {
28422             uint32_t                : 16;
28423             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
28424             uint32_t                : 4;
28425             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
28426             uint32_t                : 4;
28427         } ADDOPCRA7_b;
28428     };
28429 
28430     union
28431     {
28432         __IOM uint32_t ADDOPCRB7;        /*!< (@ 0x00000678) A/D Conversion Data Operation Control B Register
28433                                           *                  7                                                          */
28434 
28435         struct
28436         {
28437             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
28438             uint32_t                : 6;
28439             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
28440             uint32_t                : 4;
28441             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
28442             uint32_t                : 8;
28443         } ADDOPCRB7_b;
28444     };
28445 
28446     union
28447     {
28448         __IOM uint32_t ADDOPCRC7;       /*!< (@ 0x0000067C) A/D Conversion Data Operation Control C Register
28449                                          *                  7                                                          */
28450 
28451         struct
28452         {
28453             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
28454             uint32_t               : 12;
28455             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
28456             uint32_t               : 2;
28457             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
28458             uint32_t               : 11;
28459         } ADDOPCRC7_b;
28460     };
28461 
28462     union
28463     {
28464         __IOM uint32_t ADCHCR8;        /*!< (@ 0x00000680) A/D Conversion Channel Configuration Register
28465                                         *                  8                                                          */
28466 
28467         struct
28468         {
28469             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
28470             uint32_t              : 3;
28471             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
28472             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
28473             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
28474             uint32_t              : 12;
28475         } ADCHCR8_b;
28476     };
28477 
28478     union
28479     {
28480         __IOM uint32_t ADDOPCRA8;      /*!< (@ 0x00000684) A/D Conversion Data Operation Control A Register
28481                                         *                  8                                                          */
28482 
28483         struct
28484         {
28485             uint32_t                : 16;
28486             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
28487             uint32_t                : 4;
28488             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
28489             uint32_t                : 4;
28490         } ADDOPCRA8_b;
28491     };
28492 
28493     union
28494     {
28495         __IOM uint32_t ADDOPCRB8;        /*!< (@ 0x00000688) A/D Conversion Data Operation Control B Register
28496                                           *                  8                                                          */
28497 
28498         struct
28499         {
28500             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
28501             uint32_t                : 6;
28502             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
28503             uint32_t                : 4;
28504             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
28505             uint32_t                : 8;
28506         } ADDOPCRB8_b;
28507     };
28508 
28509     union
28510     {
28511         __IOM uint32_t ADDOPCRC8;       /*!< (@ 0x0000068C) A/D Conversion Data Operation Control C Register
28512                                          *                  8                                                          */
28513 
28514         struct
28515         {
28516             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
28517             uint32_t               : 12;
28518             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
28519             uint32_t               : 2;
28520             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
28521             uint32_t               : 11;
28522         } ADDOPCRC8_b;
28523     };
28524 
28525     union
28526     {
28527         __IOM uint32_t ADCHCR9;        /*!< (@ 0x00000690) A/D Conversion Channel Configuration Register
28528                                         *                  9                                                          */
28529 
28530         struct
28531         {
28532             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
28533             uint32_t              : 3;
28534             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
28535             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
28536             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
28537             uint32_t              : 12;
28538         } ADCHCR9_b;
28539     };
28540 
28541     union
28542     {
28543         __IOM uint32_t ADDOPCRA9;      /*!< (@ 0x00000694) A/D Conversion Data Operation Control A Register
28544                                         *                  9                                                          */
28545 
28546         struct
28547         {
28548             uint32_t                : 16;
28549             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
28550             uint32_t                : 4;
28551             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
28552             uint32_t                : 4;
28553         } ADDOPCRA9_b;
28554     };
28555 
28556     union
28557     {
28558         __IOM uint32_t ADDOPCRB9;        /*!< (@ 0x00000698) A/D Conversion Data Operation Control B Register
28559                                           *                  9                                                          */
28560 
28561         struct
28562         {
28563             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
28564             uint32_t                : 6;
28565             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
28566             uint32_t                : 4;
28567             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
28568             uint32_t                : 8;
28569         } ADDOPCRB9_b;
28570     };
28571 
28572     union
28573     {
28574         __IOM uint32_t ADDOPCRC9;       /*!< (@ 0x0000069C) A/D Conversion Data Operation Control C Register
28575                                          *                  9                                                          */
28576 
28577         struct
28578         {
28579             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
28580             uint32_t               : 12;
28581             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
28582             uint32_t               : 2;
28583             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
28584             uint32_t               : 11;
28585         } ADDOPCRC9_b;
28586     };
28587 
28588     union
28589     {
28590         __IOM uint32_t ADCHCR10;       /*!< (@ 0x000006A0) A/D Conversion Channel Configuration Register
28591                                         *                  10                                                         */
28592 
28593         struct
28594         {
28595             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
28596             uint32_t              : 3;
28597             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
28598             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
28599             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
28600             uint32_t              : 12;
28601         } ADCHCR10_b;
28602     };
28603 
28604     union
28605     {
28606         __IOM uint32_t ADDOPCRA10;     /*!< (@ 0x000006A4) A/D Conversion Data Operation Control A Register
28607                                         *                  10                                                         */
28608 
28609         struct
28610         {
28611             uint32_t                : 16;
28612             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
28613             uint32_t                : 4;
28614             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
28615             uint32_t                : 4;
28616         } ADDOPCRA10_b;
28617     };
28618 
28619     union
28620     {
28621         __IOM uint32_t ADDOPCRB10;       /*!< (@ 0x000006A8) A/D Conversion Data Operation Control B Register
28622                                           *                  10                                                         */
28623 
28624         struct
28625         {
28626             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
28627             uint32_t                : 6;
28628             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
28629             uint32_t                : 4;
28630             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
28631             uint32_t                : 8;
28632         } ADDOPCRB10_b;
28633     };
28634 
28635     union
28636     {
28637         __IOM uint32_t ADDOPCRC10;      /*!< (@ 0x000006AC) A/D Conversion Data Operation Control C Register
28638                                          *                  10                                                         */
28639 
28640         struct
28641         {
28642             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
28643             uint32_t               : 12;
28644             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
28645             uint32_t               : 2;
28646             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
28647             uint32_t               : 11;
28648         } ADDOPCRC10_b;
28649     };
28650 
28651     union
28652     {
28653         __IOM uint32_t ADCHCR11;       /*!< (@ 0x000006B0) A/D Conversion Channel Configuration Register
28654                                         *                  11                                                         */
28655 
28656         struct
28657         {
28658             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
28659             uint32_t              : 3;
28660             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
28661             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
28662             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
28663             uint32_t              : 12;
28664         } ADCHCR11_b;
28665     };
28666 
28667     union
28668     {
28669         __IOM uint32_t ADDOPCRA11;     /*!< (@ 0x000006B4) A/D Conversion Data Operation Control A Register
28670                                         *                  11                                                         */
28671 
28672         struct
28673         {
28674             uint32_t                : 16;
28675             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
28676             uint32_t                : 4;
28677             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
28678             uint32_t                : 4;
28679         } ADDOPCRA11_b;
28680     };
28681 
28682     union
28683     {
28684         __IOM uint32_t ADDOPCRB11;       /*!< (@ 0x000006B8) A/D Conversion Data Operation Control B Register
28685                                           *                  11                                                         */
28686 
28687         struct
28688         {
28689             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
28690             uint32_t                : 6;
28691             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
28692             uint32_t                : 4;
28693             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
28694             uint32_t                : 8;
28695         } ADDOPCRB11_b;
28696     };
28697 
28698     union
28699     {
28700         __IOM uint32_t ADDOPCRC11;      /*!< (@ 0x000006BC) A/D Conversion Data Operation Control C Register
28701                                          *                  11                                                         */
28702 
28703         struct
28704         {
28705             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
28706             uint32_t               : 12;
28707             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
28708             uint32_t               : 2;
28709             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
28710             uint32_t               : 11;
28711         } ADDOPCRC11_b;
28712     };
28713 
28714     union
28715     {
28716         __IOM uint32_t ADCHCR12;       /*!< (@ 0x000006C0) A/D Conversion Channel Configuration Register
28717                                         *                  12                                                         */
28718 
28719         struct
28720         {
28721             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
28722             uint32_t              : 3;
28723             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
28724             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
28725             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
28726             uint32_t              : 12;
28727         } ADCHCR12_b;
28728     };
28729 
28730     union
28731     {
28732         __IOM uint32_t ADDOPCRA12;     /*!< (@ 0x000006C4) A/D Conversion Data Operation Control A Register
28733                                         *                  12                                                         */
28734 
28735         struct
28736         {
28737             uint32_t                : 16;
28738             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
28739             uint32_t                : 4;
28740             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
28741             uint32_t                : 4;
28742         } ADDOPCRA12_b;
28743     };
28744 
28745     union
28746     {
28747         __IOM uint32_t ADDOPCRB12;       /*!< (@ 0x000006C8) A/D Conversion Data Operation Control B Register
28748                                           *                  12                                                         */
28749 
28750         struct
28751         {
28752             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
28753             uint32_t                : 6;
28754             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
28755             uint32_t                : 4;
28756             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
28757             uint32_t                : 8;
28758         } ADDOPCRB12_b;
28759     };
28760 
28761     union
28762     {
28763         __IOM uint32_t ADDOPCRC12;      /*!< (@ 0x000006CC) A/D Conversion Data Operation Control C Register
28764                                          *                  12                                                         */
28765 
28766         struct
28767         {
28768             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
28769             uint32_t               : 12;
28770             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
28771             uint32_t               : 2;
28772             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
28773             uint32_t               : 11;
28774         } ADDOPCRC12_b;
28775     };
28776 
28777     union
28778     {
28779         __IOM uint32_t ADCHCR13;       /*!< (@ 0x000006D0) A/D Conversion Channel Configuration Register
28780                                         *                  13                                                         */
28781 
28782         struct
28783         {
28784             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
28785             uint32_t              : 3;
28786             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
28787             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
28788             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
28789             uint32_t              : 12;
28790         } ADCHCR13_b;
28791     };
28792 
28793     union
28794     {
28795         __IOM uint32_t ADDOPCRA13;     /*!< (@ 0x000006D4) A/D Conversion Data Operation Control A Register
28796                                         *                  13                                                         */
28797 
28798         struct
28799         {
28800             uint32_t                : 16;
28801             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
28802             uint32_t                : 4;
28803             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
28804             uint32_t                : 4;
28805         } ADDOPCRA13_b;
28806     };
28807 
28808     union
28809     {
28810         __IOM uint32_t ADDOPCRB13;       /*!< (@ 0x000006D8) A/D Conversion Data Operation Control B Register
28811                                           *                  13                                                         */
28812 
28813         struct
28814         {
28815             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
28816             uint32_t                : 6;
28817             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
28818             uint32_t                : 4;
28819             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
28820             uint32_t                : 8;
28821         } ADDOPCRB13_b;
28822     };
28823 
28824     union
28825     {
28826         __IOM uint32_t ADDOPCRC13;      /*!< (@ 0x000006DC) A/D Conversion Data Operation Control C Register
28827                                          *                  13                                                         */
28828 
28829         struct
28830         {
28831             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
28832             uint32_t               : 12;
28833             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
28834             uint32_t               : 2;
28835             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
28836             uint32_t               : 11;
28837         } ADDOPCRC13_b;
28838     };
28839 
28840     union
28841     {
28842         __IOM uint32_t ADCHCR14;       /*!< (@ 0x000006E0) A/D Conversion Channel Configuration Register
28843                                         *                  14                                                         */
28844 
28845         struct
28846         {
28847             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
28848             uint32_t              : 3;
28849             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
28850             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
28851             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
28852             uint32_t              : 12;
28853         } ADCHCR14_b;
28854     };
28855 
28856     union
28857     {
28858         __IOM uint32_t ADDOPCRA14;     /*!< (@ 0x000006E4) A/D Conversion Data Operation Control A Register
28859                                         *                  14                                                         */
28860 
28861         struct
28862         {
28863             uint32_t                : 16;
28864             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
28865             uint32_t                : 4;
28866             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
28867             uint32_t                : 4;
28868         } ADDOPCRA14_b;
28869     };
28870 
28871     union
28872     {
28873         __IOM uint32_t ADDOPCRB14;       /*!< (@ 0x000006E8) A/D Conversion Data Operation Control B Register
28874                                           *                  14                                                         */
28875 
28876         struct
28877         {
28878             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
28879             uint32_t                : 6;
28880             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
28881             uint32_t                : 4;
28882             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
28883             uint32_t                : 8;
28884         } ADDOPCRB14_b;
28885     };
28886 
28887     union
28888     {
28889         __IOM uint32_t ADDOPCRC14;      /*!< (@ 0x000006EC) A/D Conversion Data Operation Control C Register
28890                                          *                  14                                                         */
28891 
28892         struct
28893         {
28894             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
28895             uint32_t               : 12;
28896             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
28897             uint32_t               : 2;
28898             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
28899             uint32_t               : 11;
28900         } ADDOPCRC14_b;
28901     };
28902 
28903     union
28904     {
28905         __IOM uint32_t ADCHCR15;       /*!< (@ 0x000006F0) A/D Conversion Channel Configuration Register
28906                                         *                  15                                                         */
28907 
28908         struct
28909         {
28910             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
28911             uint32_t              : 3;
28912             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
28913             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
28914             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
28915             uint32_t              : 12;
28916         } ADCHCR15_b;
28917     };
28918 
28919     union
28920     {
28921         __IOM uint32_t ADDOPCRA15;     /*!< (@ 0x000006F4) A/D Conversion Data Operation Control A Register
28922                                         *                  15                                                         */
28923 
28924         struct
28925         {
28926             uint32_t                : 16;
28927             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
28928             uint32_t                : 4;
28929             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
28930             uint32_t                : 4;
28931         } ADDOPCRA15_b;
28932     };
28933 
28934     union
28935     {
28936         __IOM uint32_t ADDOPCRB15;       /*!< (@ 0x000006F8) A/D Conversion Data Operation Control B Register
28937                                           *                  15                                                         */
28938 
28939         struct
28940         {
28941             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
28942             uint32_t                : 6;
28943             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
28944             uint32_t                : 4;
28945             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
28946             uint32_t                : 8;
28947         } ADDOPCRB15_b;
28948     };
28949 
28950     union
28951     {
28952         __IOM uint32_t ADDOPCRC15;      /*!< (@ 0x000006FC) A/D Conversion Data Operation Control C Register
28953                                          *                  15                                                         */
28954 
28955         struct
28956         {
28957             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
28958             uint32_t               : 12;
28959             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
28960             uint32_t               : 2;
28961             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
28962             uint32_t               : 11;
28963         } ADDOPCRC15_b;
28964     };
28965 
28966     union
28967     {
28968         __IOM uint32_t ADCHCR16;       /*!< (@ 0x00000700) A/D Conversion Channel Configuration Register
28969                                         *                  16                                                         */
28970 
28971         struct
28972         {
28973             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
28974             uint32_t              : 3;
28975             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
28976             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
28977             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
28978             uint32_t              : 12;
28979         } ADCHCR16_b;
28980     };
28981 
28982     union
28983     {
28984         __IOM uint32_t ADDOPCRA16;     /*!< (@ 0x00000704) A/D Conversion Data Operation Control A Register
28985                                         *                  16                                                         */
28986 
28987         struct
28988         {
28989             uint32_t                : 16;
28990             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
28991             uint32_t                : 4;
28992             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
28993             uint32_t                : 4;
28994         } ADDOPCRA16_b;
28995     };
28996 
28997     union
28998     {
28999         __IOM uint32_t ADDOPCRB16;       /*!< (@ 0x00000708) A/D Conversion Data Operation Control B Register
29000                                           *                  16                                                         */
29001 
29002         struct
29003         {
29004             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
29005             uint32_t                : 6;
29006             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
29007             uint32_t                : 4;
29008             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
29009             uint32_t                : 8;
29010         } ADDOPCRB16_b;
29011     };
29012 
29013     union
29014     {
29015         __IOM uint32_t ADDOPCRC16;      /*!< (@ 0x0000070C) A/D Conversion Data Operation Control C Register
29016                                          *                  16                                                         */
29017 
29018         struct
29019         {
29020             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
29021             uint32_t               : 12;
29022             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
29023             uint32_t               : 2;
29024             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
29025             uint32_t               : 11;
29026         } ADDOPCRC16_b;
29027     };
29028 
29029     union
29030     {
29031         __IOM uint32_t ADCHCR17;       /*!< (@ 0x00000710) A/D Conversion Channel Configuration Register
29032                                         *                  17                                                         */
29033 
29034         struct
29035         {
29036             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
29037             uint32_t              : 3;
29038             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
29039             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
29040             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
29041             uint32_t              : 12;
29042         } ADCHCR17_b;
29043     };
29044 
29045     union
29046     {
29047         __IOM uint32_t ADDOPCRA17;     /*!< (@ 0x00000714) A/D Conversion Data Operation Control A Register
29048                                         *                  17                                                         */
29049 
29050         struct
29051         {
29052             uint32_t                : 16;
29053             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
29054             uint32_t                : 4;
29055             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
29056             uint32_t                : 4;
29057         } ADDOPCRA17_b;
29058     };
29059 
29060     union
29061     {
29062         __IOM uint32_t ADDOPCRB17;       /*!< (@ 0x00000718) A/D Conversion Data Operation Control B Register
29063                                           *                  17                                                         */
29064 
29065         struct
29066         {
29067             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
29068             uint32_t                : 6;
29069             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
29070             uint32_t                : 4;
29071             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
29072             uint32_t                : 8;
29073         } ADDOPCRB17_b;
29074     };
29075 
29076     union
29077     {
29078         __IOM uint32_t ADDOPCRC17;      /*!< (@ 0x0000071C) A/D Conversion Data Operation Control C Register
29079                                          *                  17                                                         */
29080 
29081         struct
29082         {
29083             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
29084             uint32_t               : 12;
29085             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
29086             uint32_t               : 2;
29087             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
29088             uint32_t               : 11;
29089         } ADDOPCRC17_b;
29090     };
29091 
29092     union
29093     {
29094         __IOM uint32_t ADCHCR18;       /*!< (@ 0x00000720) A/D Conversion Channel Configuration Register
29095                                         *                  18                                                         */
29096 
29097         struct
29098         {
29099             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
29100             uint32_t              : 3;
29101             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
29102             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
29103             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
29104             uint32_t              : 12;
29105         } ADCHCR18_b;
29106     };
29107 
29108     union
29109     {
29110         __IOM uint32_t ADDOPCRA18;     /*!< (@ 0x00000724) A/D Conversion Data Operation Control A Register
29111                                         *                  18                                                         */
29112 
29113         struct
29114         {
29115             uint32_t                : 16;
29116             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
29117             uint32_t                : 4;
29118             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
29119             uint32_t                : 4;
29120         } ADDOPCRA18_b;
29121     };
29122 
29123     union
29124     {
29125         __IOM uint32_t ADDOPCRB18;       /*!< (@ 0x00000728) A/D Conversion Data Operation Control B Register
29126                                           *                  18                                                         */
29127 
29128         struct
29129         {
29130             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
29131             uint32_t                : 6;
29132             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
29133             uint32_t                : 4;
29134             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
29135             uint32_t                : 8;
29136         } ADDOPCRB18_b;
29137     };
29138 
29139     union
29140     {
29141         __IOM uint32_t ADDOPCRC18;      /*!< (@ 0x0000072C) A/D Conversion Data Operation Control C Register
29142                                          *                  18                                                         */
29143 
29144         struct
29145         {
29146             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
29147             uint32_t               : 12;
29148             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
29149             uint32_t               : 2;
29150             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
29151             uint32_t               : 11;
29152         } ADDOPCRC18_b;
29153     };
29154 
29155     union
29156     {
29157         __IOM uint32_t ADCHCR19;       /*!< (@ 0x00000730) A/D Conversion Channel Configuration Register
29158                                         *                  19                                                         */
29159 
29160         struct
29161         {
29162             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
29163             uint32_t              : 3;
29164             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
29165             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
29166             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
29167             uint32_t              : 12;
29168         } ADCHCR19_b;
29169     };
29170 
29171     union
29172     {
29173         __IOM uint32_t ADDOPCRA19;     /*!< (@ 0x00000734) A/D Conversion Data Operation Control A Register
29174                                         *                  19                                                         */
29175 
29176         struct
29177         {
29178             uint32_t                : 16;
29179             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
29180             uint32_t                : 4;
29181             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
29182             uint32_t                : 4;
29183         } ADDOPCRA19_b;
29184     };
29185 
29186     union
29187     {
29188         __IOM uint32_t ADDOPCRB19;       /*!< (@ 0x00000738) A/D Conversion Data Operation Control B Register
29189                                           *                  19                                                         */
29190 
29191         struct
29192         {
29193             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
29194             uint32_t                : 6;
29195             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
29196             uint32_t                : 4;
29197             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
29198             uint32_t                : 8;
29199         } ADDOPCRB19_b;
29200     };
29201 
29202     union
29203     {
29204         __IOM uint32_t ADDOPCRC19;      /*!< (@ 0x0000073C) A/D Conversion Data Operation Control C Register
29205                                          *                  19                                                         */
29206 
29207         struct
29208         {
29209             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
29210             uint32_t               : 12;
29211             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
29212             uint32_t               : 2;
29213             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
29214             uint32_t               : 11;
29215         } ADDOPCRC19_b;
29216     };
29217 
29218     union
29219     {
29220         __IOM uint32_t ADCHCR20;       /*!< (@ 0x00000740) A/D Conversion Channel Configuration Register
29221                                         *                  20                                                         */
29222 
29223         struct
29224         {
29225             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
29226             uint32_t              : 3;
29227             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
29228             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
29229             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
29230             uint32_t              : 12;
29231         } ADCHCR20_b;
29232     };
29233 
29234     union
29235     {
29236         __IOM uint32_t ADDOPCRA20;     /*!< (@ 0x00000744) A/D Conversion Data Operation Control A Register
29237                                         *                  20                                                         */
29238 
29239         struct
29240         {
29241             uint32_t                : 16;
29242             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
29243             uint32_t                : 4;
29244             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
29245             uint32_t                : 4;
29246         } ADDOPCRA20_b;
29247     };
29248 
29249     union
29250     {
29251         __IOM uint32_t ADDOPCRB20;       /*!< (@ 0x00000748) A/D Conversion Data Operation Control B Register
29252                                           *                  20                                                         */
29253 
29254         struct
29255         {
29256             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
29257             uint32_t                : 6;
29258             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
29259             uint32_t                : 4;
29260             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
29261             uint32_t                : 8;
29262         } ADDOPCRB20_b;
29263     };
29264 
29265     union
29266     {
29267         __IOM uint32_t ADDOPCRC20;      /*!< (@ 0x0000074C) A/D Conversion Data Operation Control C Register
29268                                          *                  20                                                         */
29269 
29270         struct
29271         {
29272             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
29273             uint32_t               : 12;
29274             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
29275             uint32_t               : 2;
29276             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
29277             uint32_t               : 11;
29278         } ADDOPCRC20_b;
29279     };
29280 
29281     union
29282     {
29283         __IOM uint32_t ADCHCR21;       /*!< (@ 0x00000750) A/D Conversion Channel Configuration Register
29284                                         *                  21                                                         */
29285 
29286         struct
29287         {
29288             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
29289             uint32_t              : 3;
29290             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
29291             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
29292             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
29293             uint32_t              : 12;
29294         } ADCHCR21_b;
29295     };
29296 
29297     union
29298     {
29299         __IOM uint32_t ADDOPCRA21;     /*!< (@ 0x00000754) A/D Conversion Data Operation Control A Register
29300                                         *                  21                                                         */
29301 
29302         struct
29303         {
29304             uint32_t                : 16;
29305             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
29306             uint32_t                : 4;
29307             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
29308             uint32_t                : 4;
29309         } ADDOPCRA21_b;
29310     };
29311 
29312     union
29313     {
29314         __IOM uint32_t ADDOPCRB21;       /*!< (@ 0x00000758) A/D Conversion Data Operation Control B Register
29315                                           *                  21                                                         */
29316 
29317         struct
29318         {
29319             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
29320             uint32_t                : 6;
29321             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
29322             uint32_t                : 4;
29323             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
29324             uint32_t                : 8;
29325         } ADDOPCRB21_b;
29326     };
29327 
29328     union
29329     {
29330         __IOM uint32_t ADDOPCRC21;      /*!< (@ 0x0000075C) A/D Conversion Data Operation Control C Register
29331                                          *                  21                                                         */
29332 
29333         struct
29334         {
29335             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
29336             uint32_t               : 12;
29337             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
29338             uint32_t               : 2;
29339             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
29340             uint32_t               : 11;
29341         } ADDOPCRC21_b;
29342     };
29343 
29344     union
29345     {
29346         __IOM uint32_t ADCHCR22;       /*!< (@ 0x00000760) A/D Conversion Channel Configuration Register
29347                                         *                  22                                                         */
29348 
29349         struct
29350         {
29351             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
29352             uint32_t              : 3;
29353             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
29354             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
29355             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
29356             uint32_t              : 12;
29357         } ADCHCR22_b;
29358     };
29359 
29360     union
29361     {
29362         __IOM uint32_t ADDOPCRA22;     /*!< (@ 0x00000764) A/D Conversion Data Operation Control A Register
29363                                         *                  22                                                         */
29364 
29365         struct
29366         {
29367             uint32_t                : 16;
29368             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
29369             uint32_t                : 4;
29370             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
29371             uint32_t                : 4;
29372         } ADDOPCRA22_b;
29373     };
29374 
29375     union
29376     {
29377         __IOM uint32_t ADDOPCRB22;       /*!< (@ 0x00000768) A/D Conversion Data Operation Control B Register
29378                                           *                  22                                                         */
29379 
29380         struct
29381         {
29382             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
29383             uint32_t                : 6;
29384             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
29385             uint32_t                : 4;
29386             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
29387             uint32_t                : 8;
29388         } ADDOPCRB22_b;
29389     };
29390 
29391     union
29392     {
29393         __IOM uint32_t ADDOPCRC22;      /*!< (@ 0x0000076C) A/D Conversion Data Operation Control C Register
29394                                          *                  22                                                         */
29395 
29396         struct
29397         {
29398             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
29399             uint32_t               : 12;
29400             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
29401             uint32_t               : 2;
29402             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
29403             uint32_t               : 11;
29404         } ADDOPCRC22_b;
29405     };
29406 
29407     union
29408     {
29409         __IOM uint32_t ADCHCR23;       /*!< (@ 0x00000770) A/D Conversion Channel Configuration Register
29410                                         *                  23                                                         */
29411 
29412         struct
29413         {
29414             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
29415             uint32_t              : 3;
29416             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
29417             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
29418             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
29419             uint32_t              : 12;
29420         } ADCHCR23_b;
29421     };
29422 
29423     union
29424     {
29425         __IOM uint32_t ADDOPCRA23;     /*!< (@ 0x00000774) A/D Conversion Data Operation Control A Register
29426                                         *                  23                                                         */
29427 
29428         struct
29429         {
29430             uint32_t                : 16;
29431             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
29432             uint32_t                : 4;
29433             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
29434             uint32_t                : 4;
29435         } ADDOPCRA23_b;
29436     };
29437 
29438     union
29439     {
29440         __IOM uint32_t ADDOPCRB23;       /*!< (@ 0x00000778) A/D Conversion Data Operation Control B Register
29441                                           *                  23                                                         */
29442 
29443         struct
29444         {
29445             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
29446             uint32_t                : 6;
29447             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
29448             uint32_t                : 4;
29449             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
29450             uint32_t                : 8;
29451         } ADDOPCRB23_b;
29452     };
29453 
29454     union
29455     {
29456         __IOM uint32_t ADDOPCRC23;      /*!< (@ 0x0000077C) A/D Conversion Data Operation Control C Register
29457                                          *                  23                                                         */
29458 
29459         struct
29460         {
29461             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
29462             uint32_t               : 12;
29463             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
29464             uint32_t               : 2;
29465             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
29466             uint32_t               : 11;
29467         } ADDOPCRC23_b;
29468     };
29469 
29470     union
29471     {
29472         __IOM uint32_t ADCHCR24;       /*!< (@ 0x00000780) A/D Conversion Channel Configuration Register
29473                                         *                  24                                                         */
29474 
29475         struct
29476         {
29477             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
29478             uint32_t              : 3;
29479             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
29480             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
29481             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
29482             uint32_t              : 12;
29483         } ADCHCR24_b;
29484     };
29485 
29486     union
29487     {
29488         __IOM uint32_t ADDOPCRA24;     /*!< (@ 0x00000784) A/D Conversion Data Operation Control A Register
29489                                         *                  24                                                         */
29490 
29491         struct
29492         {
29493             uint32_t                : 16;
29494             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
29495             uint32_t                : 4;
29496             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
29497             uint32_t                : 4;
29498         } ADDOPCRA24_b;
29499     };
29500 
29501     union
29502     {
29503         __IOM uint32_t ADDOPCRB24;       /*!< (@ 0x00000788) A/D Conversion Data Operation Control B Register
29504                                           *                  24                                                         */
29505 
29506         struct
29507         {
29508             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
29509             uint32_t                : 6;
29510             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
29511             uint32_t                : 4;
29512             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
29513             uint32_t                : 8;
29514         } ADDOPCRB24_b;
29515     };
29516 
29517     union
29518     {
29519         __IOM uint32_t ADDOPCRC24;      /*!< (@ 0x0000078C) A/D Conversion Data Operation Control C Register
29520                                          *                  24                                                         */
29521 
29522         struct
29523         {
29524             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
29525             uint32_t               : 12;
29526             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
29527             uint32_t               : 2;
29528             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
29529             uint32_t               : 11;
29530         } ADDOPCRC24_b;
29531     };
29532 
29533     union
29534     {
29535         __IOM uint32_t ADCHCR25;       /*!< (@ 0x00000790) A/D Conversion Channel Configuration Register
29536                                         *                  25                                                         */
29537 
29538         struct
29539         {
29540             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
29541             uint32_t              : 3;
29542             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
29543             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
29544             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
29545             uint32_t              : 12;
29546         } ADCHCR25_b;
29547     };
29548 
29549     union
29550     {
29551         __IOM uint32_t ADDOPCRA25;     /*!< (@ 0x00000794) A/D Conversion Data Operation Control A Register
29552                                         *                  25                                                         */
29553 
29554         struct
29555         {
29556             uint32_t                : 16;
29557             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
29558             uint32_t                : 4;
29559             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
29560             uint32_t                : 4;
29561         } ADDOPCRA25_b;
29562     };
29563 
29564     union
29565     {
29566         __IOM uint32_t ADDOPCRB25;       /*!< (@ 0x00000798) A/D Conversion Data Operation Control B Register
29567                                           *                  25                                                         */
29568 
29569         struct
29570         {
29571             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
29572             uint32_t                : 6;
29573             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
29574             uint32_t                : 4;
29575             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
29576             uint32_t                : 8;
29577         } ADDOPCRB25_b;
29578     };
29579 
29580     union
29581     {
29582         __IOM uint32_t ADDOPCRC25;      /*!< (@ 0x0000079C) A/D Conversion Data Operation Control C Register
29583                                          *                  25                                                         */
29584 
29585         struct
29586         {
29587             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
29588             uint32_t               : 12;
29589             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
29590             uint32_t               : 2;
29591             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
29592             uint32_t               : 11;
29593         } ADDOPCRC25_b;
29594     };
29595 
29596     union
29597     {
29598         __IOM uint32_t ADCHCR26;       /*!< (@ 0x000007A0) A/D Conversion Channel Configuration Register
29599                                         *                  26                                                         */
29600 
29601         struct
29602         {
29603             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
29604             uint32_t              : 3;
29605             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
29606             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
29607             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
29608             uint32_t              : 12;
29609         } ADCHCR26_b;
29610     };
29611 
29612     union
29613     {
29614         __IOM uint32_t ADDOPCRA26;     /*!< (@ 0x000007A4) A/D Conversion Data Operation Control A Register
29615                                         *                  26                                                         */
29616 
29617         struct
29618         {
29619             uint32_t                : 16;
29620             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
29621             uint32_t                : 4;
29622             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
29623             uint32_t                : 4;
29624         } ADDOPCRA26_b;
29625     };
29626 
29627     union
29628     {
29629         __IOM uint32_t ADDOPCRB26;       /*!< (@ 0x000007A8) A/D Conversion Data Operation Control B Register
29630                                           *                  26                                                         */
29631 
29632         struct
29633         {
29634             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
29635             uint32_t                : 6;
29636             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
29637             uint32_t                : 4;
29638             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
29639             uint32_t                : 8;
29640         } ADDOPCRB26_b;
29641     };
29642 
29643     union
29644     {
29645         __IOM uint32_t ADDOPCRC26;      /*!< (@ 0x000007AC) A/D Conversion Data Operation Control C Register
29646                                          *                  26                                                         */
29647 
29648         struct
29649         {
29650             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
29651             uint32_t               : 12;
29652             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
29653             uint32_t               : 2;
29654             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
29655             uint32_t               : 11;
29656         } ADDOPCRC26_b;
29657     };
29658 
29659     union
29660     {
29661         __IOM uint32_t ADCHCR27;       /*!< (@ 0x000007B0) A/D Conversion Channel Configuration Register
29662                                         *                  27                                                         */
29663 
29664         struct
29665         {
29666             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
29667             uint32_t              : 3;
29668             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
29669             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
29670             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
29671             uint32_t              : 12;
29672         } ADCHCR27_b;
29673     };
29674 
29675     union
29676     {
29677         __IOM uint32_t ADDOPCRA27;     /*!< (@ 0x000007B4) A/D Conversion Data Operation Control A Register
29678                                         *                  27                                                         */
29679 
29680         struct
29681         {
29682             uint32_t                : 16;
29683             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
29684             uint32_t                : 4;
29685             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
29686             uint32_t                : 4;
29687         } ADDOPCRA27_b;
29688     };
29689 
29690     union
29691     {
29692         __IOM uint32_t ADDOPCRB27;       /*!< (@ 0x000007B8) A/D Conversion Data Operation Control B Register
29693                                           *                  27                                                         */
29694 
29695         struct
29696         {
29697             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
29698             uint32_t                : 6;
29699             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
29700             uint32_t                : 4;
29701             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
29702             uint32_t                : 8;
29703         } ADDOPCRB27_b;
29704     };
29705 
29706     union
29707     {
29708         __IOM uint32_t ADDOPCRC27;      /*!< (@ 0x000007BC) A/D Conversion Data Operation Control C Register
29709                                          *                  27                                                         */
29710 
29711         struct
29712         {
29713             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
29714             uint32_t               : 12;
29715             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
29716             uint32_t               : 2;
29717             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
29718             uint32_t               : 11;
29719         } ADDOPCRC27_b;
29720     };
29721 
29722     union
29723     {
29724         __IOM uint32_t ADCHCR28;       /*!< (@ 0x000007C0) A/D Conversion Channel Configuration Register
29725                                         *                  28                                                         */
29726 
29727         struct
29728         {
29729             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
29730             uint32_t              : 3;
29731             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
29732             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
29733             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
29734             uint32_t              : 12;
29735         } ADCHCR28_b;
29736     };
29737 
29738     union
29739     {
29740         __IOM uint32_t ADDOPCRA28;     /*!< (@ 0x000007C4) A/D Conversion Data Operation Control A Register
29741                                         *                  28                                                         */
29742 
29743         struct
29744         {
29745             uint32_t                : 16;
29746             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
29747             uint32_t                : 4;
29748             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
29749             uint32_t                : 4;
29750         } ADDOPCRA28_b;
29751     };
29752 
29753     union
29754     {
29755         __IOM uint32_t ADDOPCRB28;       /*!< (@ 0x000007C8) A/D Conversion Data Operation Control B Register
29756                                           *                  28                                                         */
29757 
29758         struct
29759         {
29760             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
29761             uint32_t                : 6;
29762             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
29763             uint32_t                : 4;
29764             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
29765             uint32_t                : 8;
29766         } ADDOPCRB28_b;
29767     };
29768 
29769     union
29770     {
29771         __IOM uint32_t ADDOPCRC28;      /*!< (@ 0x000007CC) A/D Conversion Data Operation Control C Register
29772                                          *                  28                                                         */
29773 
29774         struct
29775         {
29776             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
29777             uint32_t               : 12;
29778             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
29779             uint32_t               : 2;
29780             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
29781             uint32_t               : 11;
29782         } ADDOPCRC28_b;
29783     };
29784 
29785     union
29786     {
29787         __IOM uint32_t ADCHCR29;       /*!< (@ 0x000007D0) A/D Conversion Channel Configuration Register
29788                                         *                  29                                                         */
29789 
29790         struct
29791         {
29792             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
29793             uint32_t              : 3;
29794             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
29795             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
29796             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
29797             uint32_t              : 12;
29798         } ADCHCR29_b;
29799     };
29800 
29801     union
29802     {
29803         __IOM uint32_t ADDOPCRA29;     /*!< (@ 0x000007D4) A/D Conversion Data Operation Control A Register
29804                                         *                  29                                                         */
29805 
29806         struct
29807         {
29808             uint32_t                : 16;
29809             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
29810             uint32_t                : 4;
29811             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
29812             uint32_t                : 4;
29813         } ADDOPCRA29_b;
29814     };
29815 
29816     union
29817     {
29818         __IOM uint32_t ADDOPCRB29;       /*!< (@ 0x000007D8) A/D Conversion Data Operation Control B Register
29819                                           *                  29                                                         */
29820 
29821         struct
29822         {
29823             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
29824             uint32_t                : 6;
29825             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
29826             uint32_t                : 4;
29827             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
29828             uint32_t                : 8;
29829         } ADDOPCRB29_b;
29830     };
29831 
29832     union
29833     {
29834         __IOM uint32_t ADDOPCRC29;      /*!< (@ 0x000007DC) A/D Conversion Data Operation Control C Register
29835                                          *                  29                                                         */
29836 
29837         struct
29838         {
29839             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
29840             uint32_t               : 12;
29841             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
29842             uint32_t               : 2;
29843             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
29844             uint32_t               : 11;
29845         } ADDOPCRC29_b;
29846     };
29847 
29848     union
29849     {
29850         __IOM uint32_t ADCHCR30;       /*!< (@ 0x000007E0) A/D Conversion Channel Configuration Register
29851                                         *                  30                                                         */
29852 
29853         struct
29854         {
29855             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
29856             uint32_t              : 3;
29857             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
29858             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
29859             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
29860             uint32_t              : 12;
29861         } ADCHCR30_b;
29862     };
29863 
29864     union
29865     {
29866         __IOM uint32_t ADDOPCRA30;     /*!< (@ 0x000007E4) A/D Conversion Data Operation Control A Register
29867                                         *                  30                                                         */
29868 
29869         struct
29870         {
29871             uint32_t                : 16;
29872             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
29873             uint32_t                : 4;
29874             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
29875             uint32_t                : 4;
29876         } ADDOPCRA30_b;
29877     };
29878 
29879     union
29880     {
29881         __IOM uint32_t ADDOPCRB30;       /*!< (@ 0x000007E8) A/D Conversion Data Operation Control B Register
29882                                           *                  30                                                         */
29883 
29884         struct
29885         {
29886             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
29887             uint32_t                : 6;
29888             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
29889             uint32_t                : 4;
29890             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
29891             uint32_t                : 8;
29892         } ADDOPCRB30_b;
29893     };
29894 
29895     union
29896     {
29897         __IOM uint32_t ADDOPCRC30;      /*!< (@ 0x000007EC) A/D Conversion Data Operation Control C Register
29898                                          *                  30                                                         */
29899 
29900         struct
29901         {
29902             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
29903             uint32_t               : 12;
29904             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
29905             uint32_t               : 2;
29906             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
29907             uint32_t               : 11;
29908         } ADDOPCRC30_b;
29909     };
29910 
29911     union
29912     {
29913         __IOM uint32_t ADCHCR31;       /*!< (@ 0x000007F0) A/D Conversion Channel Configuration Register
29914                                         *                  31                                                         */
29915 
29916         struct
29917         {
29918             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
29919             uint32_t              : 3;
29920             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
29921             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
29922             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
29923             uint32_t              : 12;
29924         } ADCHCR31_b;
29925     };
29926 
29927     union
29928     {
29929         __IOM uint32_t ADDOPCRA31;     /*!< (@ 0x000007F4) A/D Conversion Data Operation Control A Register
29930                                         *                  31                                                         */
29931 
29932         struct
29933         {
29934             uint32_t                : 16;
29935             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
29936             uint32_t                : 4;
29937             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
29938             uint32_t                : 4;
29939         } ADDOPCRA31_b;
29940     };
29941 
29942     union
29943     {
29944         __IOM uint32_t ADDOPCRB31;       /*!< (@ 0x000007F8) A/D Conversion Data Operation Control B Register
29945                                           *                  31                                                         */
29946 
29947         struct
29948         {
29949             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
29950             uint32_t                : 6;
29951             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
29952             uint32_t                : 4;
29953             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
29954             uint32_t                : 8;
29955         } ADDOPCRB31_b;
29956     };
29957 
29958     union
29959     {
29960         __IOM uint32_t ADDOPCRC31;      /*!< (@ 0x000007FC) A/D Conversion Data Operation Control C Register
29961                                          *                  31                                                         */
29962 
29963         struct
29964         {
29965             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
29966             uint32_t               : 12;
29967             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
29968             uint32_t               : 2;
29969             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
29970             uint32_t               : 11;
29971         } ADDOPCRC31_b;
29972     };
29973 
29974     union
29975     {
29976         __IOM uint32_t ADCHCR32;       /*!< (@ 0x00000800) A/D Conversion Channel Configuration Register
29977                                         *                  32                                                         */
29978 
29979         struct
29980         {
29981             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
29982             uint32_t              : 3;
29983             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
29984             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
29985             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
29986             uint32_t              : 12;
29987         } ADCHCR32_b;
29988     };
29989 
29990     union
29991     {
29992         __IOM uint32_t ADDOPCRA32;     /*!< (@ 0x00000804) A/D Conversion Data Operation Control A Register
29993                                         *                  32                                                         */
29994 
29995         struct
29996         {
29997             uint32_t                : 16;
29998             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
29999             uint32_t                : 4;
30000             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
30001             uint32_t                : 4;
30002         } ADDOPCRA32_b;
30003     };
30004 
30005     union
30006     {
30007         __IOM uint32_t ADDOPCRB32;       /*!< (@ 0x00000808) A/D Conversion Data Operation Control B Register
30008                                           *                  32                                                         */
30009 
30010         struct
30011         {
30012             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
30013             uint32_t                : 6;
30014             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
30015             uint32_t                : 4;
30016             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
30017             uint32_t                : 8;
30018         } ADDOPCRB32_b;
30019     };
30020 
30021     union
30022     {
30023         __IOM uint32_t ADDOPCRC32;      /*!< (@ 0x0000080C) A/D Conversion Data Operation Control C Register
30024                                          *                  32                                                         */
30025 
30026         struct
30027         {
30028             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
30029             uint32_t               : 12;
30030             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
30031             uint32_t               : 2;
30032             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
30033             uint32_t               : 11;
30034         } ADDOPCRC32_b;
30035     };
30036 
30037     union
30038     {
30039         __IOM uint32_t ADCHCR33;       /*!< (@ 0x00000810) A/D Conversion Channel Configuration Register
30040                                         *                  33                                                         */
30041 
30042         struct
30043         {
30044             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
30045             uint32_t              : 3;
30046             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
30047             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
30048             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
30049             uint32_t              : 12;
30050         } ADCHCR33_b;
30051     };
30052 
30053     union
30054     {
30055         __IOM uint32_t ADDOPCRA33;     /*!< (@ 0x00000814) A/D Conversion Data Operation Control A Register
30056                                         *                  33                                                         */
30057 
30058         struct
30059         {
30060             uint32_t                : 16;
30061             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
30062             uint32_t                : 4;
30063             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
30064             uint32_t                : 4;
30065         } ADDOPCRA33_b;
30066     };
30067 
30068     union
30069     {
30070         __IOM uint32_t ADDOPCRB33;       /*!< (@ 0x00000818) A/D Conversion Data Operation Control B Register
30071                                           *                  33                                                         */
30072 
30073         struct
30074         {
30075             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
30076             uint32_t                : 6;
30077             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
30078             uint32_t                : 4;
30079             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
30080             uint32_t                : 8;
30081         } ADDOPCRB33_b;
30082     };
30083 
30084     union
30085     {
30086         __IOM uint32_t ADDOPCRC33;      /*!< (@ 0x0000081C) A/D Conversion Data Operation Control C Register
30087                                          *                  33                                                         */
30088 
30089         struct
30090         {
30091             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
30092             uint32_t               : 12;
30093             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
30094             uint32_t               : 2;
30095             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
30096             uint32_t               : 11;
30097         } ADDOPCRC33_b;
30098     };
30099 
30100     union
30101     {
30102         __IOM uint32_t ADCHCR34;       /*!< (@ 0x00000820) A/D Conversion Channel Configuration Register
30103                                         *                  34                                                         */
30104 
30105         struct
30106         {
30107             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
30108             uint32_t              : 3;
30109             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
30110             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
30111             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
30112             uint32_t              : 12;
30113         } ADCHCR34_b;
30114     };
30115 
30116     union
30117     {
30118         __IOM uint32_t ADDOPCRA34;     /*!< (@ 0x00000824) A/D Conversion Data Operation Control A Register
30119                                         *                  34                                                         */
30120 
30121         struct
30122         {
30123             uint32_t                : 16;
30124             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
30125             uint32_t                : 4;
30126             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
30127             uint32_t                : 4;
30128         } ADDOPCRA34_b;
30129     };
30130 
30131     union
30132     {
30133         __IOM uint32_t ADDOPCRB34;       /*!< (@ 0x00000828) A/D Conversion Data Operation Control B Register
30134                                           *                  34                                                         */
30135 
30136         struct
30137         {
30138             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
30139             uint32_t                : 6;
30140             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
30141             uint32_t                : 4;
30142             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
30143             uint32_t                : 8;
30144         } ADDOPCRB34_b;
30145     };
30146 
30147     union
30148     {
30149         __IOM uint32_t ADDOPCRC34;      /*!< (@ 0x0000082C) A/D Conversion Data Operation Control C Register
30150                                          *                  34                                                         */
30151 
30152         struct
30153         {
30154             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
30155             uint32_t               : 12;
30156             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
30157             uint32_t               : 2;
30158             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
30159             uint32_t               : 11;
30160         } ADDOPCRC34_b;
30161     };
30162 
30163     union
30164     {
30165         __IOM uint32_t ADCHCR35;       /*!< (@ 0x00000830) A/D Conversion Channel Configuration Register
30166                                         *                  35                                                         */
30167 
30168         struct
30169         {
30170             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
30171             uint32_t              : 3;
30172             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
30173             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
30174             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
30175             uint32_t              : 12;
30176         } ADCHCR35_b;
30177     };
30178 
30179     union
30180     {
30181         __IOM uint32_t ADDOPCRA35;     /*!< (@ 0x00000834) A/D Conversion Data Operation Control A Register
30182                                         *                  35                                                         */
30183 
30184         struct
30185         {
30186             uint32_t                : 16;
30187             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
30188             uint32_t                : 4;
30189             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
30190             uint32_t                : 4;
30191         } ADDOPCRA35_b;
30192     };
30193 
30194     union
30195     {
30196         __IOM uint32_t ADDOPCRB35;       /*!< (@ 0x00000838) A/D Conversion Data Operation Control B Register
30197                                           *                  35                                                         */
30198 
30199         struct
30200         {
30201             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
30202             uint32_t                : 6;
30203             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
30204             uint32_t                : 4;
30205             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
30206             uint32_t                : 8;
30207         } ADDOPCRB35_b;
30208     };
30209 
30210     union
30211     {
30212         __IOM uint32_t ADDOPCRC35;      /*!< (@ 0x0000083C) A/D Conversion Data Operation Control C Register
30213                                          *                  35                                                         */
30214 
30215         struct
30216         {
30217             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
30218             uint32_t               : 12;
30219             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
30220             uint32_t               : 2;
30221             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
30222             uint32_t               : 11;
30223         } ADDOPCRC35_b;
30224     };
30225 
30226     union
30227     {
30228         __IOM uint32_t ADCHCR36;       /*!< (@ 0x00000840) A/D Conversion Channel Configuration Register
30229                                         *                  36                                                         */
30230 
30231         struct
30232         {
30233             __IOM uint32_t SGSEL  : 5; /*!< [4..0] Scan Group Selection                                               */
30234             uint32_t              : 3;
30235             __IOM uint32_t CNVCS  : 7; /*!< [14..8] A/D Conversion Channel Selection                                  */
30236             __IOM uint32_t AINMD  : 1; /*!< [15..15] Analog Input mode selection                                      */
30237             __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection                                   */
30238             uint32_t              : 12;
30239         } ADCHCR36_b;
30240     };
30241 
30242     union
30243     {
30244         __IOM uint32_t ADDOPCRA36;     /*!< (@ 0x00000844) A/D Conversion Data Operation Control A Register
30245                                         *                  36                                                         */
30246 
30247         struct
30248         {
30249             uint32_t                : 16;
30250             __IOM uint32_t GAINSEL  : 4; /*!< [19..16] User Gain Table Selection                                        */
30251             uint32_t                : 4;
30252             __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection                                      */
30253             uint32_t                : 4;
30254         } ADDOPCRA36_b;
30255     };
30256 
30257     union
30258     {
30259         __IOM uint32_t ADDOPCRB36;       /*!< (@ 0x00000848) A/D Conversion Data Operation Control B Register
30260                                           *                  36                                                         */
30261 
30262         struct
30263         {
30264             __IOM uint32_t AVEMD    : 2; /*!< [1..0] Addition/Averaging Mode Selection                                  */
30265             uint32_t                : 6;
30266             __IOM uint32_t ADC      : 4; /*!< [11..8] Addition/Averaging Times Selection                                */
30267             uint32_t                : 4;
30268             __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable                                             */
30269             uint32_t                : 8;
30270         } ADDOPCRB36_b;
30271     };
30272 
30273     union
30274     {
30275         __IOM uint32_t ADDOPCRC36;      /*!< (@ 0x0000084C) A/D Conversion Data Operation Control C Register
30276                                          *                  36                                                         */
30277 
30278         struct
30279         {
30280             __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection                                       */
30281             uint32_t               : 12;
30282             __IOM uint32_t ADPRC   : 2; /*!< [17..16] A/D Conversion Data Format Selection                             */
30283             uint32_t               : 2;
30284             __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection                               */
30285             uint32_t               : 11;
30286         } ADDOPCRC36_b;
30287     };
30288     __IM uint32_t RESERVED28[236];
30289 
30290     union
30291     {
30292         __OM uint32_t ADCALSTR;         /*!< (@ 0x00000C00) A/D Converter Calibration Start Register                   */
30293 
30294         struct
30295         {
30296             __OM uint32_t ADCALST0 : 3; /*!< [2..0] A/D Converter Unit 0 (ADC0) Calibration Start Control
30297                                          *   bits                                                                      */
30298             uint32_t               : 5;
30299             __OM uint32_t ADCALST1 : 3; /*!< [10..8] A/D Converter Unit 1 (ADC1) Calibration Start Control
30300                                          *   bits                                                                      */
30301             uint32_t : 21;
30302         } ADCALSTR_b;
30303     };
30304     __IM uint32_t RESERVED29;
30305 
30306     union
30307     {
30308         __IOM uint32_t ADTRGENR;         /*!< (@ 0x00000C08) A/D Conversion Start Trigger Enable Register               */
30309 
30310         struct
30311         {
30312             __IOM uint32_t STTRGENn : 9; /*!< [8..0] Scan Group n A/D Conversion Start Trigger Enable                   */
30313             uint32_t                : 23;
30314         } ADTRGENR_b;
30315     };
30316     __IM uint32_t RESERVED30;
30317 
30318     union
30319     {
30320         __OM uint32_t ADSYSTR;         /*!< (@ 0x00000C10) A/D Conversion Synchronous Software Start Register         */
30321 
30322         struct
30323         {
30324             __OM uint32_t ADSYSTn : 9; /*!< [8..0] Scan Group n : A/D Conversion start                                */
30325             uint32_t              : 23;
30326         } ADSYSTR_b;
30327     };
30328     __IM uint32_t RESERVED31[3];
30329 
30330     union
30331     {
30332         __OM uint32_t ADSTR[9];        /*!< (@ 0x00000C20) A/D Conversion Software Start Register [0..8]              */
30333 
30334         struct
30335         {
30336             __OM uint32_t ADST : 1;    /*!< [0..0] Scan Group n A/D Conversion Start                                  */
30337             uint32_t           : 31;
30338         } ADSTR_b[9];
30339     };
30340     __IM uint32_t RESERVED32[7];
30341 
30342     union
30343     {
30344         __OM uint32_t ADSTOPR;         /*!< (@ 0x00000C60) A/D Conversion Stop Register                               */
30345 
30346         struct
30347         {
30348             __OM uint32_t ADSTOP0 : 1; /*!< [0..0] A/D Converter Unit 0 Force Stop bit                                */
30349             uint32_t              : 7;
30350             __OM uint32_t ADSTOP1 : 1; /*!< [8..8] A/D Converter Unit 1 Force Stop bit                                */
30351             uint32_t              : 23;
30352         } ADSTOPR_b;
30353     };
30354     __IM uint32_t RESERVED33[7];
30355 
30356     union
30357     {
30358         __IM uint32_t ADSR;            /*!< (@ 0x00000C80) A/D Conversion Status Register                             */
30359 
30360         struct
30361         {
30362             __IM uint32_t ADACT0  : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) A/D Conversion Status                  */
30363             __IM uint32_t ADACT1  : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) A/D Conversion Status                  */
30364             uint32_t              : 14;
30365             __IM uint32_t CALACT0 : 1; /*!< [16..16] A/D Converter Unit 0 (ADC0) : Calibration Status                 */
30366             __IM uint32_t CALACT1 : 1; /*!< [17..17] A/D Converter Unit 1 (ADC1) : Calibration Status                 */
30367             uint32_t              : 14;
30368         } ADSR_b;
30369     };
30370 
30371     union
30372     {
30373         __IM uint32_t ADGRSR;          /*!< (@ 0x00000C84) Scan Group Status Register                                 */
30374 
30375         struct
30376         {
30377             __IM uint32_t ACTGRn : 9;  /*!< [8..0] Scan Group n Status                                                */
30378             uint32_t             : 23;
30379         } ADGRSR_b;
30380     };
30381 
30382     union
30383     {
30384         __IM uint32_t ADERSR;          /*!< (@ 0x00000C88) A/D Conversion Error Status Register                       */
30385 
30386         struct
30387         {
30388             __IM uint32_t ADERF0 : 1;  /*!< [0..0] A/D Converter Unit 0 (ADC0) Error Flag                             */
30389             __IM uint32_t ADERF1 : 1;  /*!< [1..1] A/D Converter Unit 1 (ADC1) Error Flag                             */
30390             uint32_t             : 30;
30391         } ADERSR_b;
30392     };
30393 
30394     union
30395     {
30396         __OM uint32_t ADERSCR;          /*!< (@ 0x00000C8C) A/D Conversion Error Status Clear Register                 */
30397 
30398         struct
30399         {
30400             __OM uint32_t ADERCLR0 : 1; /*!< [0..0] A/D Converter Unit 0 Error Flag Clear                              */
30401             __OM uint32_t ADERCLR1 : 1; /*!< [1..1] A/D Converter Unit 1 Error Flag Clear                              */
30402             uint32_t               : 30;
30403         } ADERSCR_b;
30404     };
30405     __IM uint32_t RESERVED34[2];
30406 
30407     union
30408     {
30409         __IM uint32_t ADCALENDSR;       /*!< (@ 0x00000C98) A/D Converter Calibration End Status Register              */
30410 
30411         struct
30412         {
30413             __IM uint32_t CALENDF0 : 1; /*!< [0..0] A/D Converter Unit 0 Calibration End flag                          */
30414             __IM uint32_t CALENDF1 : 1; /*!< [1..1] A/D Converter Unit 1 Calibration End flag                          */
30415             uint32_t               : 30;
30416         } ADCALENDSR_b;
30417     };
30418 
30419     union
30420     {
30421         __OM uint32_t ADCALENDSCR;      /*!< (@ 0x00000C9C) A/D Converter Calibration End Status Clear Register        */
30422 
30423         struct
30424         {
30425             __OM uint32_t CALENDC0 : 1; /*!< [0..0] A/D Converter Unit 0 Calibration End Flag Clear                    */
30426             __OM uint32_t CALENDC1 : 1; /*!< [1..1] A/D Converter Unit 1 Calibration End Flag Clear                    */
30427             uint32_t               : 30;
30428         } ADCALENDSCR_b;
30429     };
30430 
30431     union
30432     {
30433         __IM uint32_t ADOVFERSR;        /*!< (@ 0x00000CA0) A/D Conversion Overflow Error Status Register              */
30434 
30435         struct
30436         {
30437             __IM uint32_t ADOVFEF0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Overflow Error Flag                    */
30438             __IM uint32_t ADOVFEF1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Overflow Error Flag                    */
30439             uint32_t               : 30;
30440         } ADOVFERSR_b;
30441     };
30442 
30443     union
30444     {
30445         __IM uint32_t ADOVFCHSR0;       /*!< (@ 0x00000CA4) A/D Conversion Overflow Channel Status Register
30446                                          *                  0                                                          */
30447 
30448         struct
30449         {
30450             __IM uint32_t OFVCHFn : 29; /*!< [28..0] Analog Input Channel No. n : Overflow Flag                        */
30451             uint32_t              : 3;
30452         } ADOVFCHSR0_b;
30453     };
30454     __IM uint32_t RESERVED35[2];
30455 
30456     union
30457     {
30458         __IM uint32_t ADOVFEXSR;       /*!< (@ 0x00000CB0) Extended Analog A/D Conversion Overflow Status
30459                                         *                  Register                                                   */
30460 
30461         struct
30462         {
30463             __IM uint32_t OVFEXF0 : 1; /*!< [0..0] Self-Diagnosis Channel : Overflow Flag bit                         */
30464             __IM uint32_t OVFEXF1 : 1; /*!< [1..1] Temperature Sensor Channel : Overflow Flag bit                     */
30465             __IM uint32_t OVFEXF2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Overflow Flag bit             */
30466             uint32_t              : 2;
30467             __IM uint32_t OVFEXF5 : 1; /*!< [5..5] D/A Converter 0 Channel : Overflow Flag bit                        */
30468             __IM uint32_t OVFEXF6 : 1; /*!< [6..6] D/A Converter 1 Channel : Overflow Flag bit                        */
30469             __IM uint32_t OVFEXF7 : 1; /*!< [7..7] D/A Converter 2 Channel : Overflow Flag bit                        */
30470             __IM uint32_t OVFEXF8 : 1; /*!< [8..8] D/A Converter 3 Channel : Overflow Flag bit                        */
30471             uint32_t              : 23;
30472         } ADOVFEXSR_b;
30473     };
30474 
30475     union
30476     {
30477         __OM uint32_t ADOVFERSCR;       /*!< (@ 0x00000CB4) A/D Conversion Overflow Error Status Clear Register        */
30478 
30479         struct
30480         {
30481             __OM uint32_t ADOVFEC0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Overflow Error Flag Clear              */
30482             __OM uint32_t ADOVFEC1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Overflow Error Flag Clear              */
30483             uint32_t               : 30;
30484         } ADOVFERSCR_b;
30485     };
30486 
30487     union
30488     {
30489         __OM uint32_t ADOVFCHSCR0;      /*!< (@ 0x00000CB8) A/D Conversion Overflow Channel Status Clear
30490                                          *                  Register 0                                                 */
30491 
30492         struct
30493         {
30494             __OM uint32_t OVFCHCn : 29; /*!< [28..0] Analog Input Channel No. n : Overflow Flag Clear                  */
30495             uint32_t              : 3;
30496         } ADOVFCHSCR0_b;
30497     };
30498     __IM uint32_t RESERVED36[2];
30499 
30500     union
30501     {
30502         __OM uint32_t ADOVFEXSCR;      /*!< (@ 0x00000CC4) Extended Analog A/D Conversion Overflow Status
30503                                         *                  Clear Register                                             */
30504 
30505         struct
30506         {
30507             __OM uint32_t OVFEXC0 : 1; /*!< [0..0] Self-Diagnosis Channel : Overflow Flag Clear                       */
30508             __OM uint32_t OVFEXC1 : 1; /*!< [1..1] Temperature Sensor Channel : Overflow Flag Clear                   */
30509             __OM uint32_t OVFEXC2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Overflow Flag Clear           */
30510             uint32_t              : 2;
30511             __OM uint32_t OVFEXC5 : 1; /*!< [5..5] D/A Converter 0 Channel : Overflow Flag Clear                      */
30512             __OM uint32_t OVFEXC6 : 1; /*!< [6..6] D/A Converter 1 Channel : Overflow Flag Clear                      */
30513             __OM uint32_t OVFEXC7 : 1; /*!< [7..7] D/A Converter 2 Channel : Overflow Flag Clear                      */
30514             __OM uint32_t OVFEXC8 : 1; /*!< [8..8] D/A Converter 3 Channel : Overflow Flag Clear                      */
30515             uint32_t              : 23;
30516         } ADOVFEXSCR_b;
30517     };
30518     __IM uint32_t RESERVED37[2];
30519 
30520     union
30521     {
30522         __IM uint32_t ADFIFOSR0;       /*!< (@ 0x00000CD0) FIFO Status Register 0                                     */
30523 
30524         struct
30525         {
30526             __IM uint32_t FIFOST0 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 0                */
30527             uint32_t              : 12;
30528             __IM uint32_t FIFOST1 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 1              */
30529             uint32_t              : 12;
30530         } ADFIFOSR0_b;
30531     };
30532 
30533     union
30534     {
30535         __IM uint32_t ADFIFOSR1;       /*!< (@ 0x00000CD4) FIFO Status Register 1                                     */
30536 
30537         struct
30538         {
30539             __IM uint32_t FIFOST2 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 2                */
30540             uint32_t              : 12;
30541             __IM uint32_t FIFOST3 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 3              */
30542             uint32_t              : 12;
30543         } ADFIFOSR1_b;
30544     };
30545 
30546     union
30547     {
30548         __IM uint32_t ADFIFOSR2;       /*!< (@ 0x00000CD8) FIFO Status Register 2                                     */
30549 
30550         struct
30551         {
30552             __IM uint32_t FIFOST4 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 4                */
30553             uint32_t              : 12;
30554             __IM uint32_t FIFOST5 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 5              */
30555             uint32_t              : 12;
30556         } ADFIFOSR2_b;
30557     };
30558 
30559     union
30560     {
30561         __IM uint32_t ADFIFOSR3;       /*!< (@ 0x00000CDC) FIFO Status Register 3                                     */
30562 
30563         struct
30564         {
30565             __IM uint32_t FIFOST6 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 6                */
30566             uint32_t              : 12;
30567             __IM uint32_t FIFOST7 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 7              */
30568             uint32_t              : 12;
30569         } ADFIFOSR3_b;
30570     };
30571 
30572     union
30573     {
30574         __IM uint32_t ADFIFOSR4;       /*!< (@ 0x00000CE0) FIFO Status Register 4                                     */
30575 
30576         struct
30577         {
30578             __IM uint32_t FIFOST8 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 8                */
30579             uint32_t              : 28;
30580         } ADFIFOSR4_b;
30581     };
30582     __IM uint32_t RESERVED38[3];
30583 
30584     union
30585     {
30586         __OM uint32_t ADFIFODCR;       /*!< (@ 0x00000CF0) FIFO Data Clear Register                                   */
30587 
30588         struct
30589         {
30590             __OM uint32_t FIFODCn : 9; /*!< [8..0] Scan Group n FIFO Data Clear                                       */
30591             uint32_t              : 23;
30592         } ADFIFODCR_b;
30593     };
30594 
30595     union
30596     {
30597         __IM uint32_t ADFIFOERSR;       /*!< (@ 0x00000CF4) FIFO Error Status Register                                 */
30598 
30599         struct
30600         {
30601             __IM uint32_t FIFOOVFn : 9; /*!< [8..0] Scan Group n FIFO Overflow Flag                                    */
30602             uint32_t               : 7;
30603             __IM uint32_t FIFOFLFn : 9; /*!< [24..16] Scan Group n FIFO Data Full Flag                                 */
30604             uint32_t               : 7;
30605         } ADFIFOERSR_b;
30606     };
30607 
30608     union
30609     {
30610         __OM uint32_t ADFIFOERSCR;       /*!< (@ 0x00000CF8) FIFO Error Status Clear Register                           */
30611 
30612         struct
30613         {
30614             __OM uint32_t FIFOOVFCn : 9; /*!< [8..0] Scan Group n FIFO Overflow Flag Clear                              */
30615             uint32_t                : 7;
30616             __OM uint32_t FIFOFLCn  : 9; /*!< [24..16] Scan Group n FIFO Data Full Flag Clear                           */
30617             uint32_t                : 7;
30618         } ADFIFOERSCR_b;
30619     };
30620     __IM uint32_t RESERVED39;
30621 
30622     union
30623     {
30624         __IM uint32_t ADCMPTBSR;       /*!< (@ 0x00000D00) Compare Match Table Status Register                        */
30625 
30626         struct
30627         {
30628             __IM uint32_t CMPTBFn : 8; /*!< [7..0] Compare Match Table n Match Flag                                   */
30629             uint32_t              : 24;
30630         } ADCMPTBSR_b;
30631     };
30632 
30633     union
30634     {
30635         __OM uint32_t ADCMPTBSCR;      /*!< (@ 0x00000D04) Compare Match Table Status Clear Register                  */
30636 
30637         struct
30638         {
30639             __OM uint32_t CMPTBCn : 8; /*!< [7..0] Compare Match Table n : Match Flag Clear                           */
30640             uint32_t              : 24;
30641         } ADCMPTBSCR_b;
30642     };
30643 
30644     union
30645     {
30646         __IM uint32_t ADCMPCHSR0;       /*!< (@ 0x00000D08) Compare Match Channel Status Register 0                    */
30647 
30648         struct
30649         {
30650             __IM uint32_t CMPCHFn : 29; /*!< [28..0] Analog Channel No. n : Compare Match Flag                         */
30651             uint32_t              : 3;
30652         } ADCMPCHSR0_b;
30653     };
30654     __IM uint32_t RESERVED40[2];
30655 
30656     union
30657     {
30658         __IM uint32_t ADCMPEXSR;       /*!< (@ 0x00000D14) Extended Analog Compare Match Status Register              */
30659 
30660         struct
30661         {
30662             __IM uint32_t CMPEXF0 : 1; /*!< [0..0] Self-Diagnosis Channel : Compare Match Flag                        */
30663             __IM uint32_t CMPEXF1 : 1; /*!< [1..1] Temperature Sensor Channel : Compare Match Flag                    */
30664             __IM uint32_t CMPEXF2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Compare Match Flag            */
30665             uint32_t              : 2;
30666             __IM uint32_t CMPEXF5 : 1; /*!< [5..5] D/A Converter 0 Channel : Compare Match Flag                       */
30667             __IM uint32_t CMPEXF6 : 1; /*!< [6..6] D/A Converter 1 Channel : Compare Match Flag                       */
30668             __IM uint32_t CMPEXF7 : 1; /*!< [7..7] D/A Converter 2 Channel : Compare Match Flag                       */
30669             __IM uint32_t CMPEXF8 : 1; /*!< [8..8] D/A Converter 3 Channel : Compare Match Flag                       */
30670             uint32_t              : 23;
30671         } ADCMPEXSR_b;
30672     };
30673 
30674     union
30675     {
30676         __OM uint32_t ADCMPCHSCR0;      /*!< (@ 0x00000D18) Compare Match Channel Status Clear Register 0              */
30677 
30678         struct
30679         {
30680             __OM uint32_t CMPCHCn : 29; /*!< [28..0] Analog Channel No. n : Compare Match Flag Clear bit               */
30681             uint32_t              : 3;
30682         } ADCMPCHSCR0_b;
30683     };
30684     __IM uint32_t RESERVED41[2];
30685 
30686     union
30687     {
30688         __OM uint32_t ADCMPEXSCR;      /*!< (@ 0x00000D24) Extended Analog Compare Match Status Clear Register        */
30689 
30690         struct
30691         {
30692             __OM uint32_t CMPEXC0 : 1; /*!< [0..0] Self-Diagnosis Channel : Compare Match Flag Clear bit              */
30693             __OM uint32_t CMPEXC1 : 1; /*!< [1..1] Temperature Sensor Channel : Compare Match Flag Clear
30694                                         *   bit                                                                       */
30695             __OM uint32_t CMPEXC2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Compare Match Flag
30696                                         *   Clear bit                                                                 */
30697             uint32_t              : 2;
30698             __OM uint32_t CMPEXC5 : 1; /*!< [5..5] D/A Converter 0 Channel : Compare Match Flag Clear bit             */
30699             __OM uint32_t CMPEXC6 : 1; /*!< [6..6] D/A Converter 1 Channel : Compare Match Flag Clear bit             */
30700             __OM uint32_t CMPEXC7 : 1; /*!< [7..7] D/A Converter 2 Channel : Compare Match Flag Clear bit             */
30701             __OM uint32_t CMPEXC8 : 1; /*!< [8..8] D/A Converter 3 Channel : Compare Match Flag Clear bit             */
30702             uint32_t              : 23;
30703         } ADCMPEXSCR_b;
30704     };
30705 
30706     union
30707     {
30708         __IM uint32_t ADLIMGRSR;       /*!< (@ 0x00000D28) Limiter Clip Scan Group Status Register                    */
30709 
30710         struct
30711         {
30712             __IM uint32_t LIMGRFn : 9; /*!< [8..0] Scan Group n Limiter Clip Flag                                     */
30713             uint32_t              : 23;
30714         } ADLIMGRSR_b;
30715     };
30716 
30717     union
30718     {
30719         __IM uint32_t ADLIMCHSR0;       /*!< (@ 0x00000D2C) Limiter Clip Channel Status Register 0                     */
30720 
30721         struct
30722         {
30723             __IM uint32_t LIMCHFn : 29; /*!< [28..0] Analog Channel No. n : Limiter Clip Flag bit                      */
30724             uint32_t              : 3;
30725         } ADLIMCHSR0_b;
30726     };
30727     __IM uint32_t RESERVED42[2];
30728 
30729     union
30730     {
30731         __IM uint32_t ADLIMEXSR;       /*!< (@ 0x00000D38) Extended Analog Limiter Clip Status Register               */
30732 
30733         struct
30734         {
30735             __IM uint32_t LIMEXF0 : 1; /*!< [0..0] Self-Diagnosis Channel : Limiter Clip Flag bit                     */
30736             __IM uint32_t LIMEXF1 : 1; /*!< [1..1] Temperature Sensor Channel : Limiter Clip Flag bit                 */
30737             __IM uint32_t LIMEXF2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Limiter Clip Flag
30738                                         *   bit                                                                       */
30739             uint32_t              : 2;
30740             __IM uint32_t LIMEXF5 : 1; /*!< [5..5] D/A Converter 0 Channel : Limiter Clip Flag bit                    */
30741             __IM uint32_t LIMEXF6 : 1; /*!< [6..6] D/A Converter 1 Channel : Limiter Clip Flag bit                    */
30742             __IM uint32_t LIMEXF7 : 1; /*!< [7..7] D/A Converter 2 Channel : Limiter Clip Flag bit                    */
30743             __IM uint32_t LIMEXF8 : 1; /*!< [8..8] D/A Converter 3 Channel : Limiter Clip Flag bit                    */
30744             uint32_t              : 23;
30745         } ADLIMEXSR_b;
30746     };
30747 
30748     union
30749     {
30750         __OM uint32_t ADLIMGRSCR;      /*!< (@ 0x00000D3C) Limiter Clip Scan Group Status Clear Register              */
30751 
30752         struct
30753         {
30754             __OM uint32_t LIMGRCn : 9; /*!< [8..0] Scan Group n Limiter Clip Flag Clear                               */
30755             uint32_t              : 23;
30756         } ADLIMGRSCR_b;
30757     };
30758 
30759     union
30760     {
30761         __OM uint32_t ADLIMCHSCR0;      /*!< (@ 0x00000D40) Limiter Clip Channel Status Clear Register 0               */
30762 
30763         struct
30764         {
30765             __OM uint32_t LIMCHCn : 29; /*!< [28..0] Analog Channel No. n Limiter Clip Flag Clear bit                  */
30766             uint32_t              : 3;
30767         } ADLIMCHSCR0_b;
30768     };
30769     __IM uint32_t RESERVED43[2];
30770 
30771     union
30772     {
30773         __OM uint32_t ADLIMEXSCR;      /*!< (@ 0x00000D4C) Extended Analog Limiter Clip Status Clear Register         */
30774 
30775         struct
30776         {
30777             __OM uint32_t LIMEXF0 : 1; /*!< [0..0] Self-Diagnosis Channel : Limiter Clip Flag Clear                   */
30778             __OM uint32_t LIMEXF1 : 1; /*!< [1..1] Temperature Sensor Channel : Limiter Clip Flag Clear               */
30779             __OM uint32_t LIMEXF2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Limiter Clip Flag
30780                                         *   Clear                                                                     */
30781             uint32_t              : 2;
30782             __OM uint32_t LIMEXF5 : 1; /*!< [5..5] D/A Converter 0 Channel : Limiter Clip Flag Clear                  */
30783             __OM uint32_t LIMEXF6 : 1; /*!< [6..6] D/A Converter 1 Channel : Limiter Clip Flag Clear                  */
30784             __OM uint32_t LIMEXF7 : 1; /*!< [7..7] D/A Converter 2 Channel : Limiter Clip Flag Clear                  */
30785             __OM uint32_t LIMEXF8 : 1; /*!< [8..8] D/A Converter 3 Channel : Limiter Clip Flag Clear                  */
30786             uint32_t              : 23;
30787         } ADLIMEXSCR_b;
30788     };
30789 
30790     union
30791     {
30792         __IM uint32_t ADSCANENDSR;     /*!< (@ 0x00000D50) Scan End Status Register                                   */
30793 
30794         struct
30795         {
30796             __IM uint32_t SCENDFn : 9; /*!< [8..0] Scan Group n Scan End Flag                                         */
30797             uint32_t              : 23;
30798         } ADSCANENDSR_b;
30799     };
30800 
30801     union
30802     {
30803         __OM uint32_t ADSCANENDSCR;    /*!< (@ 0x00000D54) Scan End Status Clear Register                             */
30804 
30805         struct
30806         {
30807             __OM uint32_t SCENDCn : 9; /*!< [8..0] Scan Group n Scan End Flag Clear                                   */
30808             uint32_t              : 23;
30809         } ADSCANENDSCR_b;
30810     };
30811     __IM uint32_t RESERVED44[170];
30812 
30813     union
30814     {
30815         __IM uint32_t ADDR[29];        /*!< (@ 0x00001000) A/D Data Register [0..28]                                  */
30816 
30817         struct
30818         {
30819             __IM uint32_t DATA : 16;   /*!< [15..0] A/D conversion data                                               */
30820             uint32_t           : 15;
30821             __IM uint32_t ERR  : 1;    /*!< [31..31] A/D conversion data error status                                 */
30822         } ADDR_b[29];
30823     };
30824     __IM uint32_t RESERVED45[67];
30825 
30826     union
30827     {
30828         __IM uint32_t ADEXDR[9];       /*!< (@ 0x00001180) A/D Extended Analog Data Register [0..8]                   */
30829 
30830         struct
30831         {
30832             __IM uint32_t DATA   : 16; /*!< [15..0] A/D conversion data                                               */
30833             uint32_t             : 8;
30834             __IM uint32_t DIAGSR : 3;  /*!< [26..24] Self-Diagnosis Status                                            */
30835             uint32_t             : 4;
30836             __IM uint32_t ERR    : 1;  /*!< [31..31] A/D Conversion Error Status                                      */
30837         } ADEXDR_b[9];
30838     };
30839     __IM uint32_t RESERVED46[23];
30840 
30841     union
30842     {
30843         __IM uint32_t ADFIFODR0;       /*!< (@ 0x00001200) FIFO Data Register 0                                       */
30844 
30845         struct
30846         {
30847             __IM uint32_t DATA : 16;   /*!< [15..0] A/D Conversion Data                                               */
30848             uint32_t           : 8;
30849             __IM uint32_t CH   : 7;    /*!< [30..24] A/D Conversion Channel Number                                    */
30850             __IM uint32_t ERR  : 1;    /*!< [31..31] A/D Conversion Data Error Status                                 */
30851         } ADFIFODR0_b;
30852     };
30853 
30854     union
30855     {
30856         __IM uint32_t ADFIFODR1;       /*!< (@ 0x00001204) FIFO Data Register 1                                       */
30857 
30858         struct
30859         {
30860             __IM uint32_t DATA : 16;   /*!< [15..0] A/D Conversion Data                                               */
30861             uint32_t           : 8;
30862             __IM uint32_t CH   : 7;    /*!< [30..24] A/D Conversion Channel Number                                    */
30863             __IM uint32_t ERR  : 1;    /*!< [31..31] A/D Conversion Data Error Status                                 */
30864         } ADFIFODR1_b;
30865     };
30866 
30867     union
30868     {
30869         __IM uint32_t ADFIFODR2;       /*!< (@ 0x00001208) FIFO Data Register 2                                       */
30870 
30871         struct
30872         {
30873             __IM uint32_t DATA : 16;   /*!< [15..0] A/D Conversion Data                                               */
30874             uint32_t           : 8;
30875             __IM uint32_t CH   : 7;    /*!< [30..24] A/D Conversion Channel Number                                    */
30876             __IM uint32_t ERR  : 1;    /*!< [31..31] A/D Conversion Data Error Status                                 */
30877         } ADFIFODR2_b;
30878     };
30879 
30880     union
30881     {
30882         __IM uint32_t ADFIFODR3;       /*!< (@ 0x0000120C) FIFO Data Register 3                                       */
30883 
30884         struct
30885         {
30886             __IM uint32_t DATA : 16;   /*!< [15..0] A/D Conversion Data                                               */
30887             uint32_t           : 8;
30888             __IM uint32_t CH   : 7;    /*!< [30..24] A/D Conversion Channel Number                                    */
30889             __IM uint32_t ERR  : 1;    /*!< [31..31] A/D Conversion Data Error Status                                 */
30890         } ADFIFODR3_b;
30891     };
30892 
30893     union
30894     {
30895         __IM uint32_t ADFIFODR4;       /*!< (@ 0x00001210) FIFO Data Register 4                                       */
30896 
30897         struct
30898         {
30899             __IM uint32_t DATA : 16;   /*!< [15..0] A/D Conversion Data                                               */
30900             uint32_t           : 8;
30901             __IM uint32_t CH   : 7;    /*!< [30..24] A/D Conversion Channel Number                                    */
30902             __IM uint32_t ERR  : 1;    /*!< [31..31] A/D Conversion Data Error Status                                 */
30903         } ADFIFODR4_b;
30904     };
30905 
30906     union
30907     {
30908         __IM uint32_t ADFIFODR5;       /*!< (@ 0x00001214) FIFO Data Register 5                                       */
30909 
30910         struct
30911         {
30912             __IM uint32_t DATA : 16;   /*!< [15..0] A/D Conversion Data                                               */
30913             uint32_t           : 8;
30914             __IM uint32_t CH   : 7;    /*!< [30..24] A/D Conversion Channel Number                                    */
30915             __IM uint32_t ERR  : 1;    /*!< [31..31] A/D Conversion Data Error Status                                 */
30916         } ADFIFODR5_b;
30917     };
30918 
30919     union
30920     {
30921         __IM uint32_t ADFIFODR6;       /*!< (@ 0x00001218) FIFO Data Register 6                                       */
30922 
30923         struct
30924         {
30925             __IM uint32_t DATA : 16;   /*!< [15..0] A/D Conversion Data                                               */
30926             uint32_t           : 8;
30927             __IM uint32_t CH   : 7;    /*!< [30..24] A/D Conversion Channel Number                                    */
30928             __IM uint32_t ERR  : 1;    /*!< [31..31] A/D Conversion Data Error Status                                 */
30929         } ADFIFODR6_b;
30930     };
30931 
30932     union
30933     {
30934         __IM uint32_t ADFIFODR7;       /*!< (@ 0x0000121C) FIFO Data Register 7                                       */
30935 
30936         struct
30937         {
30938             __IM uint32_t DATA : 16;   /*!< [15..0] A/D Conversion Data                                               */
30939             uint32_t           : 8;
30940             __IM uint32_t CH   : 7;    /*!< [30..24] A/D Conversion Channel Number                                    */
30941             __IM uint32_t ERR  : 1;    /*!< [31..31] A/D Conversion Data Error Status                                 */
30942         } ADFIFODR7_b;
30943     };
30944 
30945     union
30946     {
30947         __IM uint32_t ADFIFODR8;       /*!< (@ 0x00001220) FIFO Data Register 8                                       */
30948 
30949         struct
30950         {
30951             __IM uint32_t DATA : 16;   /*!< [15..0] A/D Conversion Data                                               */
30952             uint32_t           : 8;
30953             __IM uint32_t CH   : 7;    /*!< [30..24] A/D Conversion Channel Number                                    */
30954             __IM uint32_t ERR  : 1;    /*!< [31..31] A/D Conversion Data Error Status                                 */
30955         } ADFIFODR8_b;
30956     };
30957 } R_ADC_B0_Type;                       /*!< Size = 4644 (0x1224)                                                      */
30958 
30959 /* =========================================================================================================================== */
30960 /* ================                                          R_DOC_B                                          ================ */
30961 /* =========================================================================================================================== */
30962 
30963 /**
30964  * @brief Data Operation Circuit (R_DOC_B)
30965  */
30966 
30967 typedef struct                         /*!< (@ 0x40109000) R_DOC_B Structure                                          */
30968 {
30969     union
30970     {
30971         __IOM uint8_t DOCR;            /*!< (@ 0x00000000) DOC Control Register                                       */
30972 
30973         struct
30974         {
30975             __IOM uint8_t OMS    : 2;  /*!< [1..0] Operating Mode Select                                              */
30976             uint8_t              : 1;
30977             __IOM uint8_t DOBW   : 1;  /*!< [3..3] Data Operation Bit Width Select                                    */
30978             __IOM uint8_t DCSEL  : 3;  /*!< [6..4] Detection Condition Select                                         */
30979             __IOM uint8_t DOPCIE : 1;  /*!< [7..7] Data Operation Circuit Interrupt Enable                            */
30980         } DOCR_b;
30981     };
30982     __IM uint8_t  RESERVED;
30983     __IM uint16_t RESERVED1;
30984 
30985     union
30986     {
30987         __IOM uint8_t DOSR;            /*!< (@ 0x00000004) DOC Flag Status Register                                   */
30988 
30989         struct
30990         {
30991             __IM uint8_t DOPCF : 1;    /*!< [0..0] Data Operation Circuit Flag                                        */
30992             uint8_t            : 7;
30993         } DOSR_b;
30994     };
30995     __IM uint8_t  RESERVED2;
30996     __IM uint16_t RESERVED3;
30997 
30998     union
30999     {
31000         __IOM uint8_t DOSCR;           /*!< (@ 0x00000008) DOC Flag Status Clear Register                             */
31001 
31002         struct
31003         {
31004             __OM uint8_t DOPCFCL : 1;  /*!< [0..0] DOPCF Clear                                                        */
31005             uint8_t              : 7;
31006         } DOSCR_b;
31007     };
31008     __IM uint8_t   RESERVED4;
31009     __IM uint16_t  RESERVED5;
31010     __IOM uint32_t DODIR;              /*!< (@ 0x0000000C) DOC Data Input Register                                    */
31011     __IOM uint32_t DODSR0;             /*!< (@ 0x00000010) DOC Data Setting Register 0                                */
31012     __IOM uint32_t DODSR1;             /*!< (@ 0x00000014) DOC Data Setting Register 1                                */
31013 } R_DOC_B_Type;                        /*!< Size = 24 (0x18)                                                          */
31014 
31015 /* =========================================================================================================================== */
31016 /* ================                                         R_SCI_B0                                          ================ */
31017 /* =========================================================================================================================== */
31018 
31019 /**
31020  * @brief Serial Communication Interface 0 (R_SCI_B0)
31021  */
31022 
31023 typedef struct                         /*!< (@ 0x40118000) R_SCI_B0 Structure                                         */
31024 {
31025     union
31026     {
31027         __IM uint32_t RDR;             /*!< (@ 0x00000000) Receive Data Register                                      */
31028 
31029         struct
31030         {
31031             __IM uint32_t RDAT : 9;    /*!< [8..0] Serial receive data                                                */
31032             __IM uint32_t MPB  : 1;    /*!< [9..9] Multi-processor flag                                               */
31033             __IM uint32_t DR   : 1;    /*!< [10..10] Receive data ready flag                                          */
31034             __IM uint32_t FPER : 1;    /*!< [11..11] FIFO parity error flag                                           */
31035             __IM uint32_t FFER : 1;    /*!< [12..12] FIFO framing error flag                                          */
31036             uint32_t           : 11;
31037             __IM uint32_t ORER : 1;    /*!< [24..24] Overrun Error flag                                               */
31038             uint32_t           : 2;
31039             __IM uint32_t PER  : 1;    /*!< [27..27] Parity error flag                                                */
31040             __IM uint32_t FER  : 1;    /*!< [28..28] Framing error flag                                               */
31041             uint32_t           : 3;
31042         } RDR_b;
31043     };
31044 
31045     union
31046     {
31047         __IOM uint32_t TDR;            /*!< (@ 0x00000004) Transmit Data Register                                     */
31048 
31049         struct
31050         {
31051             __IOM uint32_t TDAT  : 9;  /*!< [8..0] Serial transmit data                                               */
31052             __IOM uint32_t MPBT  : 1;  /*!< [9..9] Multi-processor transfer bit flag                                  */
31053             uint32_t             : 2;
31054             __IOM uint32_t TSYNC : 1;  /*!< [12..12] Transmit SYNC data                                               */
31055             uint32_t             : 19;
31056         } TDR_b;
31057     };
31058 
31059     union
31060     {
31061         __IOM uint32_t CCR0;           /*!< (@ 0x00000008) Common Control Register 0                                  */
31062 
31063         struct
31064         {
31065             __IOM uint32_t RE    : 1;  /*!< [0..0] Receive Enable                                                     */
31066             uint32_t             : 3;
31067             __IOM uint32_t TE    : 1;  /*!< [4..4] Transmit Enable                                                    */
31068             uint32_t             : 3;
31069             __IOM uint32_t MPIE  : 1;  /*!< [8..8] Multi-Processor Interrupt Enable                                   */
31070             __IOM uint32_t DCME  : 1;  /*!< [9..9] Data Compare Match Enable                                          */
31071             __IOM uint32_t IDSEL : 1;  /*!< [10..10] ID frame select                                                  */
31072             uint32_t             : 5;
31073             __IOM uint32_t RIE   : 1;  /*!< [16..16] Receive Interrupt Enable                                         */
31074             uint32_t             : 3;
31075             __IOM uint32_t TIE   : 1;  /*!< [20..20] Transmit Interrupt Enable                                        */
31076             __IOM uint32_t TEIE  : 1;  /*!< [21..21] Transmit End Interrupt Enable                                    */
31077             uint32_t             : 2;
31078             __IOM uint32_t SSE   : 1;  /*!< [24..24] SSn Pin Function Enable                                          */
31079             uint32_t             : 7;
31080         } CCR0_b;
31081     };
31082 
31083     union
31084     {
31085         __IOM uint32_t CCR1;           /*!< (@ 0x0000000C) Common Control Register 1                                  */
31086 
31087         struct
31088         {
31089             __IOM uint32_t CTSE   : 1; /*!< [0..0] CTS Enable                                                         */
31090             __IOM uint32_t CTSPEN : 1; /*!< [1..1] CTS external pin Enable                                            */
31091             uint32_t              : 2;
31092             __IOM uint32_t SPB2DT : 1; /*!< [4..4] Serial port break data select                                      */
31093             __IOM uint32_t SPB2IO : 1; /*!< [5..5] Serial port break I/O                                              */
31094             uint32_t              : 2;
31095             __IOM uint32_t PE     : 1; /*!< [8..8] Parity Enable                                                      */
31096             __IOM uint32_t PM     : 1; /*!< [9..9] Parity Mode                                                        */
31097             uint32_t              : 2;
31098             __IOM uint32_t TINV   : 1; /*!< [12..12] TXD invert                                                       */
31099             __IOM uint32_t RINV   : 1; /*!< [13..13] RXD invert                                                       */
31100             uint32_t              : 2;
31101             __IOM uint32_t SPLP   : 1; /*!< [16..16] Loopback Control                                                 */
31102             uint32_t              : 3;
31103             __IOM uint32_t SHARPS : 1; /*!< [20..20] Half-duplex communication select                                 */
31104             uint32_t              : 3;
31105             __IOM uint32_t NFCS   : 3; /*!< [26..24] Noise Filter Clock Select                                        */
31106             uint32_t              : 1;
31107             __IOM uint32_t NFEN   : 1; /*!< [28..28] Digital Noise Filter Function Enable                             */
31108             uint32_t              : 3;
31109         } CCR1_b;
31110     };
31111 
31112     union
31113     {
31114         __IOM uint32_t CCR2;           /*!< (@ 0x00000010) Common Control Register 2                                  */
31115 
31116         struct
31117         {
31118             __IOM uint32_t BCP   : 3;  /*!< [2..0] Base Clock Pulse                                                   */
31119             uint32_t             : 1;
31120             __IOM uint32_t BGDM  : 1;  /*!< [4..4] Baud Rate Generator Double-Speed Mode Select                       */
31121             __IOM uint32_t ABCS  : 1;  /*!< [5..5] Asynchronous Mode Base Clock Select                                */
31122             __IOM uint32_t ABCSE : 1;  /*!< [6..6] Asynchronous Mode Extended Base Clock Select                       */
31123             uint32_t             : 1;
31124             __IOM uint32_t BRR   : 8;  /*!< [15..8] Bit rate setting                                                  */
31125             __IOM uint32_t BRME  : 1;  /*!< [16..16] Bit Modulation Enable                                            */
31126             uint32_t             : 3;
31127             __IOM uint32_t CKS   : 2;  /*!< [21..20] Clock Select                                                     */
31128             uint32_t             : 2;
31129             __IOM uint32_t MDDR  : 8;  /*!< [31..24] Modulation Duty Setting                                          */
31130         } CCR2_b;
31131     };
31132 
31133     union
31134     {
31135         __IOM uint32_t CCR3;            /*!< (@ 0x00000014) Common Control Register 3                                  */
31136 
31137         struct
31138         {
31139             __IOM uint32_t CPHA    : 1; /*!< [0..0] Clock Phase Select                                                 */
31140             __IOM uint32_t CPOL    : 1; /*!< [1..1] Clock Polarity Select                                              */
31141             uint32_t               : 5;
31142             __IOM uint32_t BPEN    : 1; /*!< [7..7] Synchronizer bypass enable                                         */
31143             __IOM uint32_t CHR     : 2; /*!< [9..8] Character Length                                                   */
31144             uint32_t               : 2;
31145             __IOM uint32_t LSBF    : 1; /*!< [12..12] LSB First select                                                 */
31146             __IOM uint32_t SINV    : 1; /*!< [13..13] Transmitted/Received Data Invert                                 */
31147             __IOM uint32_t STP     : 1; /*!< [14..14] Stop Bit Length                                                  */
31148             __IOM uint32_t RXDESEL : 1; /*!< [15..15] Asynchronous Start Bit Edge Detection Select                     */
31149             __IOM uint32_t MOD     : 3; /*!< [18..16] Communication mode select                                        */
31150             __IOM uint32_t MP      : 1; /*!< [19..19] Multi-Processor Mode                                             */
31151             __IOM uint32_t FM      : 1; /*!< [20..20] FIFO Mode select                                                 */
31152             __IOM uint32_t DEN     : 1; /*!< [21..21] Driver enable                                                    */
31153             uint32_t               : 2;
31154             __IOM uint32_t CKE     : 2; /*!< [25..24] Clock enable                                                     */
31155             uint32_t               : 2;
31156             __IOM uint32_t GM      : 1; /*!< [28..28] GSM Mode                                                         */
31157             __IOM uint32_t BLK     : 1; /*!< [29..29] Block Transfer Mode                                              */
31158             uint32_t               : 2;
31159         } CCR3_b;
31160     };
31161 
31162     union
31163     {
31164         __IOM uint32_t CCR4;           /*!< (@ 0x00000018) Common Control Register 4                                  */
31165 
31166         struct
31167         {
31168             __IOM uint32_t CMPD : 9;   /*!< [8..0] Compare Match Data                                                 */
31169             uint32_t            : 7;
31170             __IOM uint32_t ASEN : 1;   /*!< [16..16] Adjust receive sampling timing enable                            */
31171             __IOM uint32_t ATEN : 1;   /*!< [17..17] Adjust transmit timing enable                                    */
31172             uint32_t            : 6;
31173             __IOM uint32_t AST  : 3;   /*!< [26..24] Adjustment value for receive Sampling Timing                     */
31174             __IOM uint32_t AJD  : 1;   /*!< [27..27] Adjustment Direction for receive sampling timing                 */
31175             __IOM uint32_t ATT  : 3;   /*!< [30..28] Adjustment value for Transmit timing                             */
31176             __IOM uint32_t AET  : 1;   /*!< [31..31] Adjustment edge for transmit timing                              */
31177         } CCR4_b;
31178     };
31179 
31180     union
31181     {
31182         __IM uint8_t CESR;             /*!< (@ 0x0000001C) Communication Enable Status Register                       */
31183 
31184         struct
31185         {
31186             __IM uint8_t RIST : 1;     /*!< [0..0] RE Internal status                                                 */
31187             uint8_t           : 3;
31188             __IM uint8_t TIST : 1;     /*!< [4..4] TE Internal status                                                 */
31189             uint8_t           : 3;
31190         } CESR_b;
31191     };
31192     __IM uint8_t  RESERVED;
31193     __IM uint16_t RESERVED1;
31194 
31195     union
31196     {
31197         __IOM uint32_t ICR;                /*!< (@ 0x00000020) Simple I2C Control Register                                */
31198 
31199         struct
31200         {
31201             __IOM uint32_t IICDL      : 5; /*!< [4..0] SDA Delay Output Select                                            */
31202             uint32_t                  : 3;
31203             __IOM uint32_t IICINTM    : 1; /*!< [8..8] IIC Interrupt Mode Select                                          */
31204             __IOM uint32_t IICCSC     : 1; /*!< [9..9] Clock Synchronization                                              */
31205             uint32_t                  : 3;
31206             __IOM uint32_t IICACKT    : 1; /*!< [13..13] ACK Transmission Data                                            */
31207             uint32_t                  : 2;
31208             __IOM uint32_t IICSTAREQ  : 1; /*!< [16..16] Start Condition Generation                                       */
31209             __IOM uint32_t IICRSTAREQ : 1; /*!< [17..17] Restart Condition Generation                                     */
31210             __IOM uint32_t IICSTPREQ  : 1; /*!< [18..18] Stop Condition Generation                                        */
31211             uint32_t                  : 1;
31212             __IOM uint32_t IICSDAS    : 2; /*!< [21..20] SDA Output Select                                                */
31213             __IOM uint32_t IICSCLS    : 2; /*!< [23..22] SCL Output Select                                                */
31214             uint32_t                  : 8;
31215         } ICR_b;
31216     };
31217 
31218     union
31219     {
31220         __IOM uint32_t FCR;            /*!< (@ 0x00000024) FIFO Control Register                                      */
31221 
31222         struct
31223         {
31224             __IOM uint32_t DRES  : 1;  /*!< [0..0] Receive data ready error select bit                                */
31225             uint32_t             : 7;
31226             __IOM uint32_t TTRG  : 5;  /*!< [12..8] Transmit FIFO data trigger number                                 */
31227             uint32_t             : 2;
31228             __OM uint32_t  TFRST : 1;  /*!< [15..15] Transmit FIFO Data Register Reset                                */
31229             __IOM uint32_t RTRG  : 5;  /*!< [20..16] Receive FIFO data trigger number                                 */
31230             uint32_t             : 2;
31231             __OM uint32_t  RFRST : 1;  /*!< [23..23] Receive FIFO Data Register Reset                                 */
31232             __IOM uint32_t RSTRG : 5;  /*!< [28..24] RTS Output Active Trigger Number Select                          */
31233             uint32_t             : 3;
31234         } FCR_b;
31235     };
31236     __IM uint32_t RESERVED2;
31237 
31238     union
31239     {
31240         __IOM uint32_t MCR;            /*!< (@ 0x0000002C) Manchester Control Register                                */
31241 
31242         struct
31243         {
31244             __IOM uint32_t RMPOL  : 1; /*!< [0..0] Polarity of Received Manchester Code                               */
31245             __IOM uint32_t TMPOL  : 1; /*!< [1..1] Polarity of Transmit Manchester Code                               */
31246             __IOM uint32_t ERTEN  : 1; /*!< [2..2] Manchester Edge Retiming Enable                                    */
31247             uint32_t              : 1;
31248             __IOM uint32_t SYNVAL : 1; /*!< [4..4] SYNC value Setting                                                 */
31249             __IOM uint32_t SYNSEL : 1; /*!< [5..5] SYNC Select                                                        */
31250             __IOM uint32_t SBSEL  : 1; /*!< [6..6] Start Bit Select                                                   */
31251             uint32_t              : 1;
31252             __IOM uint32_t TPLEN  : 4; /*!< [11..8] Transmit preface length                                           */
31253             __IOM uint32_t TPPAT  : 2; /*!< [13..12] Transmit preface pattern                                         */
31254             uint32_t              : 2;
31255             __IOM uint32_t RPLEN  : 4; /*!< [19..16] Receive Preface Length                                           */
31256             __IOM uint32_t RPPAT  : 2; /*!< [21..20] Receive Preface Pattern                                          */
31257             uint32_t              : 2;
31258             __IOM uint32_t PFEREN : 1; /*!< [24..24] Preface Error Enable                                             */
31259             __IOM uint32_t SYEREN : 1; /*!< [25..25] Receive SYNC Error Enable                                        */
31260             __IOM uint32_t SBEREN : 1; /*!< [26..26] Start Bit Error Enable                                           */
31261             uint32_t              : 5;
31262         } MCR_b;
31263     };
31264 
31265     union
31266     {
31267         __IOM uint32_t DCR;            /*!< (@ 0x00000030) Driver Control Register                                    */
31268 
31269         struct
31270         {
31271             __IOM uint32_t DEPOL : 1;  /*!< [0..0] Driver effective polarity select                                   */
31272             uint32_t             : 7;
31273             __IOM uint32_t DEAST : 5;  /*!< [12..8] Driver Assertion Time                                             */
31274             uint32_t             : 3;
31275             __IOM uint32_t DENGT : 5;  /*!< [20..16] Driver negate time                                               */
31276             uint32_t             : 11;
31277         } DCR_b;
31278     };
31279 
31280     union
31281     {
31282         __IOM uint32_t XCR0;           /*!< (@ 0x00000034) Simple LIN(SCIX) Control Register 0                        */
31283 
31284         struct
31285         {
31286             __IOM uint32_t TCSS  : 2;  /*!< [1..0] Timer count clock source selection                                 */
31287             uint32_t             : 6;
31288             __IOM uint32_t BFE   : 1;  /*!< [8..8] Break Field enable                                                 */
31289             __IOM uint32_t CF0RE : 1;  /*!< [9..9] Control Field 0 enable                                             */
31290             __IOM uint32_t CF1DS : 2;  /*!< [11..10] Control Field1 compare data select                               */
31291             __IOM uint32_t PIBE  : 1;  /*!< [12..12] Priority interrupt bit enable                                    */
31292             __IOM uint32_t PIBS  : 3;  /*!< [15..13] Priority interrupt bit select                                    */
31293             __IOM uint32_t BFOIE : 1;  /*!< [16..16] Break Field output completion interrupt enable                   */
31294             __IOM uint32_t BCDIE : 1;  /*!< [17..17] Bus conflict detection interrupt enable                          */
31295             uint32_t             : 2;
31296             __IOM uint32_t BFDIE : 1;  /*!< [20..20] Break Field detection interrupt enable                           */
31297             __IOM uint32_t COFIE : 1;  /*!< [21..21] Counter overflow interrupt enable                                */
31298             __IOM uint32_t AEDIE : 1;  /*!< [22..22] Active edge detection interrupt enable                           */
31299             uint32_t             : 1;
31300             __IOM uint32_t BCCS  : 2;  /*!< [25..24] Bus conflict detection clock selection                           */
31301             uint32_t             : 6;
31302         } XCR0_b;
31303     };
31304 
31305     union
31306     {
31307         __IOM uint32_t XCR1;           /*!< (@ 0x00000038) Simple LIN(SCIX) Control Register 1                        */
31308 
31309         struct
31310         {
31311             __IOM uint32_t TCST  : 1;  /*!< [0..0] Break Field output timer count start trigger                       */
31312             uint32_t             : 3;
31313             __IOM uint32_t SDST  : 1;  /*!< [4..4] Start Frame detection enable                                       */
31314             __IOM uint32_t BMEN  : 1;  /*!< [5..5] Bit rate measurement enable                                        */
31315             uint32_t             : 2;
31316             __IOM uint32_t PCF1D : 8;  /*!< [15..8] Priority compare data for Control Field 1                         */
31317             __IOM uint32_t SCF1D : 8;  /*!< [23..16] Secondary compare data for Control Field 1                       */
31318             __IOM uint32_t CF1CE : 8;  /*!< [31..24] Control Field 1 compare bit enable                               */
31319         } XCR1_b;
31320     };
31321 
31322     union
31323     {
31324         __IOM uint32_t XCR2;           /*!< (@ 0x0000003C) Simple LIN(SCIX) Control Register 2                        */
31325 
31326         struct
31327         {
31328             __IOM uint32_t CF0D  : 8;  /*!< [7..0] Control Field 0compare data                                        */
31329             __IOM uint32_t CF0CE : 8;  /*!< [15..8] Control Field 0 compare bit enable                                */
31330             __IOM uint32_t BFLW  : 16; /*!< [31..16] Break Field length setting                                       */
31331         } XCR2_b;
31332     };
31333     __IM uint32_t RESERVED3[2];
31334 
31335     union
31336     {
31337         __IM uint32_t CSR;             /*!< (@ 0x00000048) Common Status Register                                     */
31338 
31339         struct
31340         {
31341             uint32_t             : 4;
31342             __IM uint32_t ERS    : 1;  /*!< [4..4] Error Signal Status Flag                                           */
31343             uint32_t             : 10;
31344             __IM uint32_t RXDMON : 1;  /*!< [15..15] Serial input data monitor bit                                    */
31345             __IM uint32_t DCMF   : 1;  /*!< [16..16] Data Compare Match Flag                                          */
31346             __IM uint32_t DPER   : 1;  /*!< [17..17] Data Compare Match Parity Error Flag                             */
31347             __IM uint32_t DFER   : 1;  /*!< [18..18] Data Compare Match Framing Error Flag                            */
31348             uint32_t             : 5;
31349             __IM uint32_t ORER   : 1;  /*!< [24..24] Overrun Error Flag                                               */
31350             uint32_t             : 1;
31351             __IM uint32_t MFF    : 1;  /*!< [26..26] Mode Fault Flag                                                  */
31352             __IM uint32_t PER    : 1;  /*!< [27..27] Parity Error Flag                                                */
31353             __IM uint32_t FER    : 1;  /*!< [28..28] Framing Error Flag                                               */
31354             __IM uint32_t TDRE   : 1;  /*!< [29..29] Transmit Data Empty Flag                                         */
31355             __IM uint32_t TEND   : 1;  /*!< [30..30] Transmit End Flag                                                */
31356             __IM uint32_t RDRF   : 1;  /*!< [31..31] Receive Data Full Flag                                           */
31357         } CSR_b;
31358     };
31359 
31360     union
31361     {
31362         __IM uint32_t ISR;             /*!< (@ 0x0000004C) Simple I2C Status Register                                 */
31363 
31364         struct
31365         {
31366             __IM uint32_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag                                            */
31367             uint32_t              : 2;
31368             __IM uint32_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
31369                                         *   Flag                                                                      */
31370             uint32_t : 28;
31371         } ISR_b;
31372     };
31373 
31374     union
31375     {
31376         __IM uint32_t FRSR;            /*!< (@ 0x00000050) FIFO Receive Status Register                               */
31377 
31378         struct
31379         {
31380             __IM uint32_t DR   : 1;    /*!< [0..0] Receive Data Ready flag                                            */
31381             uint32_t           : 7;
31382             __IM uint32_t R    : 6;    /*!< [13..8] Receive-FIFO Data Count                                           */
31383             uint32_t           : 2;
31384             __IM uint32_t PNUM : 6;    /*!< [21..16] Parity Error Count                                               */
31385             uint32_t           : 2;
31386             __IM uint32_t FNUM : 6;    /*!< [29..24] Framing Error Count                                              */
31387             uint32_t           : 2;
31388         } FRSR_b;
31389     };
31390 
31391     union
31392     {
31393         __IM uint32_t FTSR;            /*!< (@ 0x00000054) FIFO Transmit Status Register                              */
31394 
31395         struct
31396         {
31397             __IM uint32_t T : 6;       /*!< [5..0] Transmit-FIFO Data Count                                           */
31398             uint32_t        : 26;
31399         } FTSR_b;
31400     };
31401 
31402     union
31403     {
31404         __IM uint32_t MSR;             /*!< (@ 0x00000058) Manchester Status Register                                 */
31405 
31406         struct
31407         {
31408             __IM uint32_t PFER  : 1;   /*!< [0..0] Preface Error flag                                                 */
31409             __IM uint32_t SYER  : 1;   /*!< [1..1] SYNC Error flag                                                    */
31410             __IM uint32_t SBER  : 1;   /*!< [2..2] Start Bit Error flag                                               */
31411             uint32_t            : 1;
31412             __IM uint32_t MER   : 1;   /*!< [4..4] Manchester Error Flag                                              */
31413             uint32_t            : 1;
31414             __IM uint32_t RSYNC : 1;   /*!< [6..6] Receive SYNC data bit                                              */
31415             uint32_t            : 25;
31416         } MSR_b;
31417     };
31418 
31419     union
31420     {
31421         __IM uint32_t XSR0;            /*!< (@ 0x0000005C) Simple LIN (SCIX) Status Register 0                        */
31422 
31423         struct
31424         {
31425             __IM uint32_t SFSF  : 1;   /*!< [0..0] Start Frame Status flag                                            */
31426             __IM uint32_t RXDSF : 1;   /*!< [1..1] RXDn input status flag                                             */
31427             uint32_t            : 6;
31428             __IM uint32_t BFOF  : 1;   /*!< [8..8] Break Field Output completion flag                                 */
31429             __IM uint32_t BCDF  : 1;   /*!< [9..9] Bus Conflict detection flag                                        */
31430             __IM uint32_t BFDF  : 1;   /*!< [10..10] Break Field detection flag                                       */
31431             __IM uint32_t CF0MF : 1;   /*!< [11..11] Control Field 0 compare match flag                               */
31432             __IM uint32_t CF1MF : 1;   /*!< [12..12] Control Field 1 compare match flag                               */
31433             __IM uint32_t PIBDF : 1;   /*!< [13..13] Priority interrupt bit detection flag                            */
31434             __IM uint32_t COF   : 1;   /*!< [14..14] Counter Overflow flag                                            */
31435             __IM uint32_t AEDF  : 1;   /*!< [15..15] Active Edge detection flag                                       */
31436             __IM uint32_t CF0RD : 8;   /*!< [23..16] Control Field 0 received data                                    */
31437             __IM uint32_t CF1RD : 8;   /*!< [31..24] Control Field 1 received data                                    */
31438         } XSR0_b;
31439     };
31440 
31441     union
31442     {
31443         __IM uint32_t XSR1;            /*!< (@ 0x00000060) Simple LIN(SCIX) Status Register 1                         */
31444 
31445         struct
31446         {
31447             __IM uint32_t TCNT : 16;   /*!< [15..0] Timer Count Capture value                                         */
31448             uint32_t           : 16;
31449         } XSR1_b;
31450     };
31451     __IM uint32_t RESERVED4;
31452 
31453     union
31454     {
31455         __OM uint32_t CFCLR;           /*!< (@ 0x00000068) Common Flag Clear Register                                 */
31456 
31457         struct
31458         {
31459             uint32_t            : 4;
31460             __OM uint32_t ERSC  : 1;   /*!< [4..4] ERS clear bit                                                      */
31461             uint32_t            : 11;
31462             __OM uint32_t DCMFC : 1;   /*!< [16..16] DCMF clear bit                                                   */
31463             __OM uint32_t DPERC : 1;   /*!< [17..17] DPER clear bit                                                   */
31464             __OM uint32_t DFERC : 1;   /*!< [18..18] DFER clear bit                                                   */
31465             uint32_t            : 5;
31466             __OM uint32_t ORERC : 1;   /*!< [24..24] ORER clear bit                                                   */
31467             uint32_t            : 1;
31468             __OM uint32_t MFFC  : 1;   /*!< [26..26] MFF clear bit                                                    */
31469             __OM uint32_t PERC  : 1;   /*!< [27..27] PER clear bit                                                    */
31470             __OM uint32_t FERC  : 1;   /*!< [28..28] FER clear bit                                                    */
31471             __OM uint32_t TDREC : 1;   /*!< [29..29] TDRE clear bit                                                   */
31472             uint32_t            : 1;
31473             __OM uint32_t RDRFC : 1;   /*!< [31..31] RDRF clear bit                                                   */
31474         } CFCLR_b;
31475     };
31476 
31477     union
31478     {
31479         __OM uint32_t ICFCLR;          /*!< (@ 0x0000006C) Simple I2C Flag Clear Register                             */
31480 
31481         struct
31482         {
31483             uint32_t               : 3;
31484             __OM uint32_t IICSTIFC : 1; /*!< [3..3] IICSTIF clear bit                                                  */
31485             uint32_t               : 28;
31486         } ICFCLR_b;
31487     };
31488 
31489     union
31490     {
31491         __OM uint32_t FFCLR;           /*!< (@ 0x00000070) FIFO Flag Clear Register                                   */
31492 
31493         struct
31494         {
31495             __OM uint32_t DRC : 1;     /*!< [0..0] DR clear bit                                                       */
31496             uint32_t          : 31;
31497         } FFCLR_b;
31498     };
31499 
31500     union
31501     {
31502         __OM uint32_t MFCLR;           /*!< (@ 0x00000074) Manchester Flag Clear Register                             */
31503 
31504         struct
31505         {
31506             __OM uint32_t PFERC : 1;   /*!< [0..0] PFER clear bit                                                     */
31507             __OM uint32_t SYERC : 1;   /*!< [1..1] SYER clear bit                                                     */
31508             __OM uint32_t SBERC : 1;   /*!< [2..2] SBER clear bit                                                     */
31509             uint32_t            : 1;
31510             __OM uint32_t MERC  : 1;   /*!< [4..4] MER clear bit                                                      */
31511             uint32_t            : 27;
31512         } MFCLR_b;
31513     };
31514 
31515     union
31516     {
31517         __OM uint32_t XFCLR;           /*!< (@ 0x00000078) Simple LIN(SCIX) Flag Clear Register                       */
31518 
31519         struct
31520         {
31521             uint32_t            : 8;
31522             __OM uint32_t BFOC  : 1;   /*!< [8..8] BFOF clear bit                                                     */
31523             __OM uint32_t BCDC  : 1;   /*!< [9..9] BCDF clear bit                                                     */
31524             __OM uint32_t BFDC  : 1;   /*!< [10..10] BFDF clear bit                                                   */
31525             __OM uint32_t CF0MC : 1;   /*!< [11..11] CF0MF clear bit                                                  */
31526             __OM uint32_t CF1MC : 1;   /*!< [12..12] CF1MF clear bit                                                  */
31527             __OM uint32_t PIBDC : 1;   /*!< [13..13] PIBDF clear bit                                                  */
31528             __OM uint32_t COFC  : 1;   /*!< [14..14] COFF clear bit                                                   */
31529             __OM uint32_t AEDC  : 1;   /*!< [15..15] AEDF clear bit                                                   */
31530             uint32_t            : 16;
31531         } XFCLR_b;
31532     };
31533 } R_SCI_B0_Type;                       /*!< Size = 124 (0x7c)                                                         */
31534 
31535 /* =========================================================================================================================== */
31536 /* ================                                         R_SPI_B0                                          ================ */
31537 /* =========================================================================================================================== */
31538 
31539 /**
31540  * @brief Serial Peripheral Interface 0 (R_SPI_B0)
31541  */
31542 
31543 typedef struct                         /*!< (@ 0x4011A000) R_SPI_B0 Structure                                         */
31544 {
31545     __IOM uint32_t SPDR;               /*!< (@ 0x00000000) RSPI Data Register                                         */
31546 
31547     union
31548     {
31549         __IOM uint32_t SPDECR;         /*!< (@ 0x00000004) RSPI Delay Control Register                                */
31550 
31551         struct
31552         {
31553             __IOM uint32_t SCKDL : 3;  /*!< [2..0] RSPCK Delay                                                        */
31554             uint32_t             : 5;
31555             __IOM uint32_t SLNDL : 3;  /*!< [10..8] SSL Negation Delay                                                */
31556             uint32_t             : 5;
31557             __IOM uint32_t SPNDL : 3;  /*!< [18..16] RSPI Next-Access Delay                                           */
31558             uint32_t             : 5;
31559             __IOM uint32_t ARST  : 3;  /*!< [26..24] Receive Sampling Timing Adjustment bits                          */
31560             uint32_t             : 5;
31561         } SPDECR_b;
31562     };
31563 
31564     union
31565     {
31566         __IOM uint32_t SPCR;             /*!< (@ 0x00000008) RSPI Control Register                                      */
31567 
31568         struct
31569         {
31570             __IOM uint32_t SPE      : 1; /*!< [0..0] RSPI Function Enable                                               */
31571             uint32_t                : 6;
31572             __IOM uint32_t SPSCKSEL : 1; /*!< [7..7] RSPI Master Receive Clock Select                                   */
31573             __IOM uint32_t SPPE     : 1; /*!< [8..8] Parity Enable                                                      */
31574             __IOM uint32_t SPOE     : 1; /*!< [9..9] Parity Mode                                                        */
31575             uint32_t                : 1;
31576             __IOM uint32_t PTE      : 1; /*!< [11..11] Parity Self-Diagnosis Enable                                     */
31577             __IOM uint32_t SCKASE   : 1; /*!< [12..12] RSPCK Auto-Stop Function Enable                                  */
31578             __IOM uint32_t BFDS     : 1; /*!< [13..13] Between Burst Transfer Frames Delay Select                       */
31579             __IOM uint32_t MODFEN   : 1; /*!< [14..14] Mode Fault Error Detection Enable                                */
31580             uint32_t                : 1;
31581             __IOM uint32_t SPEIE    : 1; /*!< [16..16] RSPI Error Interrupt Enable                                      */
31582             __IOM uint32_t SPRIE    : 1; /*!< [17..17] RSPI Receive Buffer Full Interrupt Enable                        */
31583             __IOM uint32_t SPIIE    : 1; /*!< [18..18] RSPI Idle Interrupt Enable                                       */
31584             __IOM uint32_t SPDRES   : 1; /*!< [19..19] RSPI receive data ready error select                             */
31585             __IOM uint32_t SPTIE    : 1; /*!< [20..20] RSPI Transmit Buffer Empty Interrupt Enable                      */
31586             __IOM uint32_t CENDIE   : 1; /*!< [21..21] RSPI Communication End Interrupt Enable                          */
31587             uint32_t                : 2;
31588             __IOM uint32_t SPMS     : 1; /*!< [24..24] RSPI Mode Select                                                 */
31589             __IOM uint32_t SPFRF    : 1; /*!< [25..25] RSPI Frame Format Select                                         */
31590             uint32_t                : 2;
31591             __IOM uint32_t TXMD     : 2; /*!< [29..28] Communication Mode Select                                        */
31592             __IOM uint32_t MSTR     : 1; /*!< [30..30] RSPI Master/Slave Mode Select                                    */
31593             __IOM uint32_t BPEN     : 1; /*!< [31..31] Synchronization Circuit Bypass Enable                            */
31594         } SPCR_b;
31595     };
31596 
31597     union
31598     {
31599         __IOM uint32_t SPCR2;          /*!< (@ 0x0000000C) RSPI Control Register 2                                    */
31600 
31601         struct
31602         {
31603             __IOM uint32_t RMFM   : 5; /*!< [4..0] Frame processing count setting in Master Receive only              */
31604             uint32_t              : 1;
31605             __OM uint32_t  RMEDTG : 1; /*!< [6..6] End Trigger in Master Receive only                                 */
31606             __OM uint32_t  RMSTTG : 1; /*!< [7..7] Start Trigger in Master Receive only                               */
31607             __IOM uint32_t SPDRC  : 8; /*!< [15..8] RSPI received data ready detect adjustment                        */
31608             __IOM uint32_t SPLP   : 1; /*!< [16..16] RSPI Loopback                                                    */
31609             __IOM uint32_t SPLP2  : 1; /*!< [17..17] RSPI Loopback 2                                                  */
31610             uint32_t              : 2;
31611             __IOM uint32_t MOIFV  : 1; /*!< [20..20] MOSI Idle Fixed Value                                            */
31612             __IOM uint32_t MOIFE  : 1; /*!< [21..21] MOSI Idle Fixed Value Enable                                     */
31613             uint32_t              : 10;
31614         } SPCR2_b;
31615     };
31616 
31617     union
31618     {
31619         __IOM uint32_t SPCR3;          /*!< (@ 0x00000010) RSPI Control Register 3                                    */
31620 
31621         struct
31622         {
31623             __IOM uint32_t SSL0P : 1;  /*!< [0..0] SSL0 Signal Polarity                                               */
31624             __IOM uint32_t SSL1P : 1;  /*!< [1..1] SSL1 Signal Polarity                                               */
31625             __IOM uint32_t SSL2P : 1;  /*!< [2..2] SSL2 Signal Polarity                                               */
31626             __IOM uint32_t SSL3P : 1;  /*!< [3..3] SSL3 Signal Polarity                                               */
31627             uint32_t             : 4;
31628             __IOM uint32_t SPBR  : 8;  /*!< [15..8] SPI Bit Rate                                                      */
31629             uint32_t             : 8;
31630             __IOM uint32_t SPSLN : 3;  /*!< [26..24] RSPI Sequence Length                                             */
31631             uint32_t             : 5;
31632         } SPCR3_b;
31633     };
31634 
31635     union
31636     {
31637         __IOM uint32_t SPCMD0;         /*!< (@ 0x00000014) RSPI Command Register                                      */
31638 
31639         struct
31640         {
31641             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
31642             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
31643             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
31644             uint32_t              : 3;
31645             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
31646             uint32_t              : 4;
31647             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
31648             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
31649             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
31650             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
31651             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
31652             uint32_t              : 3;
31653             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
31654             uint32_t              : 5;
31655         } SPCMD0_b;
31656     };
31657 
31658     union
31659     {
31660         __IOM uint32_t SPCMD1;         /*!< (@ 0x00000018) RSPI Command Register                                      */
31661 
31662         struct
31663         {
31664             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
31665             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
31666             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
31667             uint32_t              : 3;
31668             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
31669             uint32_t              : 4;
31670             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
31671             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
31672             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
31673             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
31674             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
31675             uint32_t              : 3;
31676             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
31677             uint32_t              : 5;
31678         } SPCMD1_b;
31679     };
31680 
31681     union
31682     {
31683         __IOM uint32_t SPCMD2;         /*!< (@ 0x0000001C) RSPI Command Register                                      */
31684 
31685         struct
31686         {
31687             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
31688             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
31689             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
31690             uint32_t              : 3;
31691             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
31692             uint32_t              : 4;
31693             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
31694             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
31695             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
31696             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
31697             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
31698             uint32_t              : 3;
31699             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
31700             uint32_t              : 5;
31701         } SPCMD2_b;
31702     };
31703 
31704     union
31705     {
31706         __IOM uint32_t SPCMD3;         /*!< (@ 0x00000020) RSPI Command Register                                      */
31707 
31708         struct
31709         {
31710             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
31711             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
31712             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
31713             uint32_t              : 3;
31714             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
31715             uint32_t              : 4;
31716             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
31717             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
31718             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
31719             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
31720             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
31721             uint32_t              : 3;
31722             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
31723             uint32_t              : 5;
31724         } SPCMD3_b;
31725     };
31726 
31727     union
31728     {
31729         __IOM uint32_t SPCMD4;         /*!< (@ 0x00000024) RSPI Command Register                                      */
31730 
31731         struct
31732         {
31733             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
31734             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
31735             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
31736             uint32_t              : 3;
31737             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
31738             uint32_t              : 4;
31739             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
31740             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
31741             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
31742             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
31743             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
31744             uint32_t              : 3;
31745             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
31746             uint32_t              : 5;
31747         } SPCMD4_b;
31748     };
31749 
31750     union
31751     {
31752         __IOM uint32_t SPCMD5;         /*!< (@ 0x00000028) RSPI Command Register                                      */
31753 
31754         struct
31755         {
31756             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
31757             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
31758             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
31759             uint32_t              : 3;
31760             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
31761             uint32_t              : 4;
31762             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
31763             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
31764             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
31765             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
31766             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
31767             uint32_t              : 3;
31768             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
31769             uint32_t              : 5;
31770         } SPCMD5_b;
31771     };
31772 
31773     union
31774     {
31775         __IOM uint32_t SPCMD6;         /*!< (@ 0x0000002C) RSPI Command Register                                      */
31776 
31777         struct
31778         {
31779             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
31780             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
31781             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
31782             uint32_t              : 3;
31783             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
31784             uint32_t              : 4;
31785             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
31786             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
31787             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
31788             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
31789             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
31790             uint32_t              : 3;
31791             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
31792             uint32_t              : 5;
31793         } SPCMD6_b;
31794     };
31795 
31796     union
31797     {
31798         __IOM uint32_t SPCMD7;         /*!< (@ 0x00000030) RSPI Command Register                                      */
31799 
31800         struct
31801         {
31802             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
31803             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
31804             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
31805             uint32_t              : 3;
31806             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
31807             uint32_t              : 4;
31808             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
31809             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
31810             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
31811             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
31812             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
31813             uint32_t              : 3;
31814             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
31815             uint32_t              : 5;
31816         } SPCMD7_b;
31817     };
31818     __IM uint32_t RESERVED[3];
31819 
31820     union
31821     {
31822         __IOM uint32_t SPDCR;          /*!< (@ 0x00000040) RSPI Data Control Register                                 */
31823 
31824         struct
31825         {
31826             __IOM uint32_t BYSW   : 1; /*!< [0..0] Byte Swap Operating Mode Select                                    */
31827             uint32_t              : 2;
31828             __IOM uint32_t SPRDTD : 1; /*!< [3..3] RSPI Receive Data or Transmit Data Select                          */
31829             __IOM uint32_t SINV   : 1; /*!< [4..4] Serial data invert bit                                             */
31830             uint32_t              : 3;
31831             __IOM uint32_t SPFC   : 2; /*!< [9..8] Frame Count                                                        */
31832             uint32_t              : 22;
31833         } SPDCR_b;
31834     };
31835 
31836     union
31837     {
31838         __IOM uint32_t SPDCR2;         /*!< (@ 0x00000044) RSPI Data Control Register 2                               */
31839 
31840         struct
31841         {
31842             __IOM uint32_t RTRG : 2;   /*!< [1..0] Receive FIFO threshold setting                                     */
31843             uint32_t            : 6;
31844             __IOM uint32_t TTRG : 2;   /*!< [9..8] Transmission FIFO threshold setting                                */
31845             uint32_t            : 22;
31846         } SPDCR2_b;
31847     };
31848     __IM uint32_t RESERVED1[2];
31849 
31850     union
31851     {
31852         __IM uint32_t SPSR;            /*!< (@ 0x00000050) SPI Status Register                                        */
31853 
31854         struct
31855         {
31856             uint32_t            : 8;
31857             __IM uint32_t SPCP  : 3;   /*!< [10..8] RSPI Command Pointer                                              */
31858             uint32_t            : 1;
31859             __IM uint32_t SPECM : 3;   /*!< [14..12] RSPI Error Command                                               */
31860             uint32_t            : 8;
31861             __IM uint32_t SPDRF : 1;   /*!< [23..23] RSPI Receive Data Ready Flag                                     */
31862             __IM uint32_t OVRF  : 1;   /*!< [24..24] Overrun Error Flag                                               */
31863             __IM uint32_t IDLNF : 1;   /*!< [25..25] RSPI Idle Flag                                                   */
31864             __IM uint32_t MODF  : 1;   /*!< [26..26] Mode Fault Error Flag                                            */
31865             __IM uint32_t PERF  : 1;   /*!< [27..27] Parity Error Flag                                                */
31866             __IM uint32_t UDRF  : 1;   /*!< [28..28] Underrun Error Flag                                              */
31867             __IM uint32_t SPTEF : 1;   /*!< [29..29] RSPI Transmit Buffer Empty Flag                                  */
31868             __IM uint32_t CENDF : 1;   /*!< [30..30] Communication End Flag                                           */
31869             __IM uint32_t SPRF  : 1;   /*!< [31..31] RSPI Receive Buffer Full Flag                                    */
31870         } SPSR_b;
31871     };
31872     __IM uint32_t RESERVED2;
31873 
31874     union
31875     {
31876         __IM uint32_t SPTFSR;          /*!< (@ 0x00000058) RSPI Transfer FIFO Status Register                         */
31877 
31878         struct
31879         {
31880             __IM uint32_t TFDN : 3;    /*!< [2..0] Transmit FIFO data empty stage number                              */
31881             uint32_t           : 29;
31882         } SPTFSR_b;
31883     };
31884 
31885     union
31886     {
31887         __IM uint32_t SPRFSR;          /*!< (@ 0x0000005C) RSPI Receive FIFO Status Register                          */
31888 
31889         struct
31890         {
31891             __IM uint32_t RFDN : 3;    /*!< [2..0] Receive FIFO data store stage number                               */
31892             uint32_t           : 29;
31893         } SPRFSR_b;
31894     };
31895 
31896     union
31897     {
31898         __IM uint32_t SPPSR;           /*!< (@ 0x00000060) RSPI Poling Register                                       */
31899 
31900         struct
31901         {
31902             __IM uint32_t SPEPS : 1;   /*!< [0..0] RSPI Poling Status                                                 */
31903             uint32_t            : 31;
31904         } SPPSR_b;
31905     };
31906     __IM uint32_t RESERVED3;
31907 
31908     union
31909     {
31910         __IOM uint32_t SPSRC;          /*!< (@ 0x00000068) RSPI Status Clear Register                                 */
31911 
31912         struct
31913         {
31914             uint32_t             : 23;
31915             __OM uint32_t SPDRFC : 1;  /*!< [23..23] RSPI Receive Data Ready Flag Clear                               */
31916             __OM uint32_t OVRFC  : 1;  /*!< [24..24] Overrun Error Flag Clear                                         */
31917             uint32_t             : 1;
31918             __OM uint32_t MODFC  : 1;  /*!< [26..26] Mode Fault Error Flag Clear                                      */
31919             __OM uint32_t PERFC  : 1;  /*!< [27..27] Parity Error Flag Clear                                          */
31920             __OM uint32_t UDRFC  : 1;  /*!< [28..28] Underrun Error Flag Clear                                        */
31921             __OM uint32_t SPTEFC : 1;  /*!< [29..29] RSPI Transmit Buffer Empty Flag Clear                            */
31922             __OM uint32_t CENDFC : 1;  /*!< [30..30] Communication End Flag Clear                                     */
31923             __OM uint32_t SPRFC  : 1;  /*!< [31..31] RSPI Receive Buffer Full Flag Clear                              */
31924         } SPSRC_b;
31925     };
31926 
31927     union
31928     {
31929         __IOM uint32_t SPFCR;          /*!< (@ 0x0000006C) RSPI FIFO Clear Register                                   */
31930 
31931         struct
31932         {
31933             __OM uint32_t SPFRST : 1;  /*!< [0..0] RSPI FIFO clear                                                    */
31934             uint32_t             : 31;
31935         } SPFCR_b;
31936     };
31937 } R_SPI_B0_Type;                       /*!< Size = 112 (0x70)                                                         */
31938 
31939 /* =========================================================================================================================== */
31940 /* ================                                           R_TFU                                           ================ */
31941 /* =========================================================================================================================== */
31942 
31943 /**
31944  * @brief Trigonometric Function Unit (TFU) (R_TFU)
31945  */
31946 
31947 typedef struct                         /*!< (@ 0x90003000) R_TFU Structure                                            */
31948 {
31949     __IM uint32_t RESERVED[4];
31950 
31951     union
31952     {
31953         __IOM float SCDT0;             /*!< (@ 0x00000010) TBD                                                        */
31954 
31955         struct
31956         {
31957             __IOM uint32_t SCDT0 : 32; /*!< [31..0] TBD                                                               */
31958         } SCDT0_b;
31959     };
31960 
31961     union
31962     {
31963         __IOM float SCDT1;             /*!< (@ 0x00000014) TBD                                                        */
31964 
31965         struct
31966         {
31967             __IOM uint32_t SCDT1 : 32; /*!< [31..0] TBD                                                               */
31968         } SCDT1_b;
31969     };
31970 
31971     union
31972     {
31973         __IOM float ATDT0;             /*!< (@ 0x00000018) TBD                                                        */
31974 
31975         struct
31976         {
31977             __IOM uint32_t ATDT0 : 32; /*!< [31..0] TBD                                                               */
31978         } ATDT0_b;
31979     };
31980 
31981     union
31982     {
31983         __IOM float ATDT1;             /*!< (@ 0x0000001C) TBD                                                        */
31984 
31985         struct
31986         {
31987             __IOM uint32_t ATDT1 : 32; /*!< [31..0] TBD                                                               */
31988         } ATDT1_b;
31989     };
31990 } R_TFU_Type;                          /*!< Size = 32 (0x20)                                                          */
31991 
31992 /** @} */ /* End of group Device_Peripheral_peripherals */
31993 
31994  #ifdef BSP_OVERRIDE_REG_HEADER
31995   #include BSP_OVERRIDE_REG_HEADER
31996  #endif
31997 
31998  #include "base_addresses.h"
31999 
32000 /* =========================================  End of section using anonymous unions  ========================================= */
32001  #if defined(__CC_ARM)
32002   #pragma pop
32003  #elif defined(__ICCARM__)
32004 
32005 /* leave anonymous unions enabled */
32006  #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
32007   #pragma clang diagnostic pop
32008  #elif defined(__GNUC__)
32009 
32010 /* anonymous unions are enabled by default */
32011  #elif defined(__TMS470__)
32012 
32013 /* anonymous unions are enabled by default */
32014  #elif defined(__TASKING__)
32015   #pragma warning restore
32016  #elif defined(__CSMC__)
32017 
32018 /* anonymous unions are enabled by default */
32019  #endif
32020 
32021 /* =========================================================================================================================== */
32022 /* ================                                 Pos/Mask Cluster Section                                  ================ */
32023 /* =========================================================================================================================== */
32024 
32025 /** @addtogroup PosMask_clusters
32026  * @{
32027  */
32028 
32029 /* =========================================================================================================================== */
32030 /* ================                                            CSa                                            ================ */
32031 /* =========================================================================================================================== */
32032 
32033 /* ==========================================================  MOD  ========================================================== */
32034  #define R_BUS_CSa_MOD_PRMOD_Pos        (15UL)         /*!< PRMOD (Bit 15)                                        */
32035  #define R_BUS_CSa_MOD_PRMOD_Msk        (0x8000UL)     /*!< PRMOD (Bitfield-Mask: 0x01)                           */
32036  #define R_BUS_CSa_MOD_PWENB_Pos        (9UL)          /*!< PWENB (Bit 9)                                         */
32037  #define R_BUS_CSa_MOD_PWENB_Msk        (0x200UL)      /*!< PWENB (Bitfield-Mask: 0x01)                           */
32038  #define R_BUS_CSa_MOD_PRENB_Pos        (8UL)          /*!< PRENB (Bit 8)                                         */
32039  #define R_BUS_CSa_MOD_PRENB_Msk        (0x100UL)      /*!< PRENB (Bitfield-Mask: 0x01)                           */
32040  #define R_BUS_CSa_MOD_EWENB_Pos        (3UL)          /*!< EWENB (Bit 3)                                         */
32041  #define R_BUS_CSa_MOD_EWENB_Msk        (0x8UL)        /*!< EWENB (Bitfield-Mask: 0x01)                           */
32042  #define R_BUS_CSa_MOD_WRMOD_Pos        (0UL)          /*!< WRMOD (Bit 0)                                         */
32043  #define R_BUS_CSa_MOD_WRMOD_Msk        (0x1UL)        /*!< WRMOD (Bitfield-Mask: 0x01)                           */
32044 /* =========================================================  WCR1  ========================================================== */
32045  #define R_BUS_CSa_WCR1_CSRWAIT_Pos     (24UL)         /*!< CSRWAIT (Bit 24)                                      */
32046  #define R_BUS_CSa_WCR1_CSRWAIT_Msk     (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f)                         */
32047  #define R_BUS_CSa_WCR1_CSWWAIT_Pos     (16UL)         /*!< CSWWAIT (Bit 16)                                      */
32048  #define R_BUS_CSa_WCR1_CSWWAIT_Msk     (0x1f0000UL)   /*!< CSWWAIT (Bitfield-Mask: 0x1f)                         */
32049  #define R_BUS_CSa_WCR1_CSPRWAIT_Pos    (8UL)          /*!< CSPRWAIT (Bit 8)                                      */
32050  #define R_BUS_CSa_WCR1_CSPRWAIT_Msk    (0x700UL)      /*!< CSPRWAIT (Bitfield-Mask: 0x07)                        */
32051  #define R_BUS_CSa_WCR1_CSPWWAIT_Pos    (0UL)          /*!< CSPWWAIT (Bit 0)                                      */
32052  #define R_BUS_CSa_WCR1_CSPWWAIT_Msk    (0x7UL)        /*!< CSPWWAIT (Bitfield-Mask: 0x07)                        */
32053 /* =========================================================  WCR2  ========================================================== */
32054  #define R_BUS_CSa_WCR2_CSON_Pos        (28UL)         /*!< CSON (Bit 28)                                         */
32055  #define R_BUS_CSa_WCR2_CSON_Msk        (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07)                            */
32056  #define R_BUS_CSa_WCR2_WDON_Pos        (24UL)         /*!< WDON (Bit 24)                                         */
32057  #define R_BUS_CSa_WCR2_WDON_Msk        (0x7000000UL)  /*!< WDON (Bitfield-Mask: 0x07)                            */
32058  #define R_BUS_CSa_WCR2_WRON_Pos        (20UL)         /*!< WRON (Bit 20)                                         */
32059  #define R_BUS_CSa_WCR2_WRON_Msk        (0x700000UL)   /*!< WRON (Bitfield-Mask: 0x07)                            */
32060  #define R_BUS_CSa_WCR2_RDON_Pos        (16UL)         /*!< RDON (Bit 16)                                         */
32061  #define R_BUS_CSa_WCR2_RDON_Msk        (0x70000UL)    /*!< RDON (Bitfield-Mask: 0x07)                            */
32062  #define R_BUS_CSa_WCR2_AWAIT_Pos       (12UL)         /*!< AWAIT (Bit 12)                                        */
32063  #define R_BUS_CSa_WCR2_AWAIT_Msk       (0x3000UL)     /*!< AWAIT (Bitfield-Mask: 0x03)                           */
32064  #define R_BUS_CSa_WCR2_WDOFF_Pos       (8UL)          /*!< WDOFF (Bit 8)                                         */
32065  #define R_BUS_CSa_WCR2_WDOFF_Msk       (0x700UL)      /*!< WDOFF (Bitfield-Mask: 0x07)                           */
32066  #define R_BUS_CSa_WCR2_CSWOFF_Pos      (4UL)          /*!< CSWOFF (Bit 4)                                        */
32067  #define R_BUS_CSa_WCR2_CSWOFF_Msk      (0x70UL)       /*!< CSWOFF (Bitfield-Mask: 0x07)                          */
32068  #define R_BUS_CSa_WCR2_CSROFF_Pos      (0UL)          /*!< CSROFF (Bit 0)                                        */
32069  #define R_BUS_CSa_WCR2_CSROFF_Msk      (0x7UL)        /*!< CSROFF (Bitfield-Mask: 0x07)                          */
32070 
32071 /* =========================================================================================================================== */
32072 /* ================                                            CSb                                            ================ */
32073 /* =========================================================================================================================== */
32074 
32075 /* ==========================================================  CR  =========================================================== */
32076  #define R_BUS_CSb_CR_MPXEN_Pos    (12UL)     /*!< MPXEN (Bit 12)                                        */
32077  #define R_BUS_CSb_CR_MPXEN_Msk    (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01)                           */
32078  #define R_BUS_CSb_CR_EMODE_Pos    (8UL)      /*!< EMODE (Bit 8)                                         */
32079  #define R_BUS_CSb_CR_EMODE_Msk    (0x100UL)  /*!< EMODE (Bitfield-Mask: 0x01)                           */
32080  #define R_BUS_CSb_CR_BSIZE_Pos    (4UL)      /*!< BSIZE (Bit 4)                                         */
32081  #define R_BUS_CSb_CR_BSIZE_Msk    (0x30UL)   /*!< BSIZE (Bitfield-Mask: 0x03)                           */
32082  #define R_BUS_CSb_CR_EXENB_Pos    (0UL)      /*!< EXENB (Bit 0)                                         */
32083  #define R_BUS_CSb_CR_EXENB_Msk    (0x1UL)    /*!< EXENB (Bitfield-Mask: 0x01)                           */
32084 /* ==========================================================  REC  ========================================================== */
32085  #define R_BUS_CSb_REC_WRCV_Pos    (8UL)      /*!< WRCV (Bit 8)                                          */
32086  #define R_BUS_CSb_REC_WRCV_Msk    (0xf00UL)  /*!< WRCV (Bitfield-Mask: 0x0f)                            */
32087  #define R_BUS_CSb_REC_RRCV_Pos    (0UL)      /*!< RRCV (Bit 0)                                          */
32088  #define R_BUS_CSb_REC_RRCV_Msk    (0xfUL)    /*!< RRCV (Bitfield-Mask: 0x0f)                            */
32089 
32090 /* =========================================================================================================================== */
32091 /* ================                                           SDRAM                                           ================ */
32092 /* =========================================================================================================================== */
32093 
32094 /* =========================================================  SDCCR  ========================================================= */
32095  #define R_BUS_SDRAM_SDCCR_BSIZE_Pos     (4UL)       /*!< BSIZE (Bit 4)                                         */
32096  #define R_BUS_SDRAM_SDCCR_BSIZE_Msk     (0x30UL)    /*!< BSIZE (Bitfield-Mask: 0x03)                           */
32097  #define R_BUS_SDRAM_SDCCR_EXENB_Pos     (0UL)       /*!< EXENB (Bit 0)                                         */
32098  #define R_BUS_SDRAM_SDCCR_EXENB_Msk     (0x1UL)     /*!< EXENB (Bitfield-Mask: 0x01)                           */
32099 /* ========================================================  SDCMOD  ========================================================= */
32100  #define R_BUS_SDRAM_SDCMOD_EMODE_Pos    (0UL)       /*!< EMODE (Bit 0)                                         */
32101  #define R_BUS_SDRAM_SDCMOD_EMODE_Msk    (0x1UL)     /*!< EMODE (Bitfield-Mask: 0x01)                           */
32102 /* ========================================================  SDAMOD  ========================================================= */
32103  #define R_BUS_SDRAM_SDAMOD_BE_Pos       (0UL)       /*!< BE (Bit 0)                                            */
32104  #define R_BUS_SDRAM_SDAMOD_BE_Msk       (0x1UL)     /*!< BE (Bitfield-Mask: 0x01)                              */
32105 /* ========================================================  SDSELF  ========================================================= */
32106  #define R_BUS_SDRAM_SDSELF_SFEN_Pos     (0UL)       /*!< SFEN (Bit 0)                                          */
32107  #define R_BUS_SDRAM_SDSELF_SFEN_Msk     (0x1UL)     /*!< SFEN (Bitfield-Mask: 0x01)                            */
32108 /* ========================================================  SDRFCR  ========================================================= */
32109  #define R_BUS_SDRAM_SDRFCR_REFW_Pos     (12UL)      /*!< REFW (Bit 12)                                         */
32110  #define R_BUS_SDRAM_SDRFCR_REFW_Msk     (0xf000UL)  /*!< REFW (Bitfield-Mask: 0x0f)                            */
32111  #define R_BUS_SDRAM_SDRFCR_RFC_Pos      (0UL)       /*!< RFC (Bit 0)                                           */
32112  #define R_BUS_SDRAM_SDRFCR_RFC_Msk      (0xfffUL)   /*!< RFC (Bitfield-Mask: 0xfff)                            */
32113 /* ========================================================  SDRFEN  ========================================================= */
32114  #define R_BUS_SDRAM_SDRFEN_RFEN_Pos     (0UL)       /*!< RFEN (Bit 0)                                          */
32115  #define R_BUS_SDRAM_SDRFEN_RFEN_Msk     (0x1UL)     /*!< RFEN (Bitfield-Mask: 0x01)                            */
32116 /* =========================================================  SDICR  ========================================================= */
32117  #define R_BUS_SDRAM_SDICR_INIRQ_Pos     (0UL)       /*!< INIRQ (Bit 0)                                         */
32118  #define R_BUS_SDRAM_SDICR_INIRQ_Msk     (0x1UL)     /*!< INIRQ (Bitfield-Mask: 0x01)                           */
32119 /* =========================================================  SDIR  ========================================================== */
32120  #define R_BUS_SDRAM_SDIR_PRC_Pos        (8UL)       /*!< PRC (Bit 8)                                           */
32121  #define R_BUS_SDRAM_SDIR_PRC_Msk        (0x700UL)   /*!< PRC (Bitfield-Mask: 0x07)                             */
32122  #define R_BUS_SDRAM_SDIR_ARFC_Pos       (4UL)       /*!< ARFC (Bit 4)                                          */
32123  #define R_BUS_SDRAM_SDIR_ARFC_Msk       (0xf0UL)    /*!< ARFC (Bitfield-Mask: 0x0f)                            */
32124  #define R_BUS_SDRAM_SDIR_ARFI_Pos       (0UL)       /*!< ARFI (Bit 0)                                          */
32125  #define R_BUS_SDRAM_SDIR_ARFI_Msk       (0xfUL)     /*!< ARFI (Bitfield-Mask: 0x0f)                            */
32126 /* =========================================================  SDADR  ========================================================= */
32127  #define R_BUS_SDRAM_SDADR_MXC_Pos       (0UL)       /*!< MXC (Bit 0)                                           */
32128  #define R_BUS_SDRAM_SDADR_MXC_Msk       (0x3UL)     /*!< MXC (Bitfield-Mask: 0x03)                             */
32129 /* =========================================================  SDTR  ========================================================== */
32130  #define R_BUS_SDRAM_SDTR_RAS_Pos        (16UL)      /*!< RAS (Bit 16)                                          */
32131  #define R_BUS_SDRAM_SDTR_RAS_Msk        (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07)                             */
32132  #define R_BUS_SDRAM_SDTR_RCD_Pos        (12UL)      /*!< RCD (Bit 12)                                          */
32133  #define R_BUS_SDRAM_SDTR_RCD_Msk        (0x3000UL)  /*!< RCD (Bitfield-Mask: 0x03)                             */
32134  #define R_BUS_SDRAM_SDTR_RP_Pos         (9UL)       /*!< RP (Bit 9)                                            */
32135  #define R_BUS_SDRAM_SDTR_RP_Msk         (0xe00UL)   /*!< RP (Bitfield-Mask: 0x07)                              */
32136  #define R_BUS_SDRAM_SDTR_WR_Pos         (8UL)       /*!< WR (Bit 8)                                            */
32137  #define R_BUS_SDRAM_SDTR_WR_Msk         (0x100UL)   /*!< WR (Bitfield-Mask: 0x01)                              */
32138  #define R_BUS_SDRAM_SDTR_CL_Pos         (0UL)       /*!< CL (Bit 0)                                            */
32139  #define R_BUS_SDRAM_SDTR_CL_Msk         (0x7UL)     /*!< CL (Bitfield-Mask: 0x07)                              */
32140 /* =========================================================  SDMOD  ========================================================= */
32141  #define R_BUS_SDRAM_SDMOD_MR_Pos        (0UL)       /*!< MR (Bit 0)                                            */
32142  #define R_BUS_SDRAM_SDMOD_MR_Msk        (0x7fffUL)  /*!< MR (Bitfield-Mask: 0x7fff)                            */
32143 /* =========================================================  SDSR  ========================================================== */
32144  #define R_BUS_SDRAM_SDSR_SRFST_Pos      (4UL)       /*!< SRFST (Bit 4)                                         */
32145  #define R_BUS_SDRAM_SDSR_SRFST_Msk      (0x10UL)    /*!< SRFST (Bitfield-Mask: 0x01)                           */
32146  #define R_BUS_SDRAM_SDSR_INIST_Pos      (3UL)       /*!< INIST (Bit 3)                                         */
32147  #define R_BUS_SDRAM_SDSR_INIST_Msk      (0x8UL)     /*!< INIST (Bitfield-Mask: 0x01)                           */
32148  #define R_BUS_SDRAM_SDSR_MRSST_Pos      (0UL)       /*!< MRSST (Bit 0)                                         */
32149  #define R_BUS_SDRAM_SDSR_MRSST_Msk      (0x1UL)     /*!< MRSST (Bitfield-Mask: 0x01)                           */
32150 
32151 /* =========================================================================================================================== */
32152 /* ================                                          BUSERR                                           ================ */
32153 /* =========================================================================================================================== */
32154 
32155 /* ==========================================================  ADD  ========================================================== */
32156  #define R_BUS_BUSERR_ADD_BERAD_Pos       (0UL)          /*!< BERAD (Bit 0)                                         */
32157  #define R_BUS_BUSERR_ADD_BERAD_Msk       (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff)                     */
32158 /* =========================================================  STAT  ========================================================== */
32159  #define R_BUS_BUSERR_STAT_ERRSTAT_Pos    (7UL)          /*!< ERRSTAT (Bit 7)                                       */
32160  #define R_BUS_BUSERR_STAT_ERRSTAT_Msk    (0x80UL)       /*!< ERRSTAT (Bitfield-Mask: 0x01)                         */
32161  #define R_BUS_BUSERR_STAT_ACCSTAT_Pos    (0UL)          /*!< ACCSTAT (Bit 0)                                       */
32162  #define R_BUS_BUSERR_STAT_ACCSTAT_Msk    (0x1UL)        /*!< ACCSTAT (Bitfield-Mask: 0x01)                         */
32163 
32164 /* =========================================================================================================================== */
32165 /* ================                                           BUSM                                            ================ */
32166 /* =========================================================================================================================== */
32167 
32168 /* ==========================================================  CNT  ========================================================== */
32169  #define R_BUS_BUSM_CNT_IERES_Pos    (15UL)     /*!< IERES (Bit 15)                                        */
32170  #define R_BUS_BUSM_CNT_IERES_Msk    (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01)                           */
32171 
32172 /* =========================================================================================================================== */
32173 /* ================                                           BUSS                                            ================ */
32174 /* =========================================================================================================================== */
32175 
32176 /* ==========================================================  CNT  ========================================================== */
32177  #define R_BUS_BUSS_CNT_ARBMET_Pos    (4UL)    /*!< ARBMET (Bit 4)                                        */
32178  #define R_BUS_BUSS_CNT_ARBMET_Msk    (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03)                          */
32179 
32180 /* =========================================================================================================================== */
32181 /* ================                                            MB                                             ================ */
32182 /* =========================================================================================================================== */
32183 
32184 /* ==========================================================  ID  =========================================================== */
32185  #define R_CAN0_MB_ID_IDE_Pos    (31UL)         /*!< IDE (Bit 31)                                          */
32186  #define R_CAN0_MB_ID_IDE_Msk    (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01)                             */
32187  #define R_CAN0_MB_ID_RTR_Pos    (30UL)         /*!< RTR (Bit 30)                                          */
32188  #define R_CAN0_MB_ID_RTR_Msk    (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01)                             */
32189  #define R_CAN0_MB_ID_SID_Pos    (18UL)         /*!< SID (Bit 18)                                          */
32190  #define R_CAN0_MB_ID_SID_Msk    (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff)                            */
32191  #define R_CAN0_MB_ID_EID_Pos    (0UL)          /*!< EID (Bit 0)                                           */
32192  #define R_CAN0_MB_ID_EID_Msk    (0x3ffffUL)    /*!< EID (Bitfield-Mask: 0x3ffff)                          */
32193 /* ==========================================================  DL  =========================================================== */
32194  #define R_CAN0_MB_DL_DLC_Pos    (0UL)          /*!< DLC (Bit 0)                                           */
32195  #define R_CAN0_MB_DL_DLC_Msk    (0xfUL)        /*!< DLC (Bitfield-Mask: 0x0f)                             */
32196 /* ===========================================================  D  =========================================================== */
32197  #define R_CAN0_MB_D_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
32198  #define R_CAN0_MB_D_DATA_Msk    (0xffUL)       /*!< DATA (Bitfield-Mask: 0xff)                            */
32199 /* ==========================================================  TS  =========================================================== */
32200  #define R_CAN0_MB_TS_TSH_Pos    (8UL)          /*!< TSH (Bit 8)                                           */
32201  #define R_CAN0_MB_TS_TSH_Msk    (0xff00UL)     /*!< TSH (Bitfield-Mask: 0xff)                             */
32202  #define R_CAN0_MB_TS_TSL_Pos    (0UL)          /*!< TSL (Bit 0)                                           */
32203  #define R_CAN0_MB_TS_TSL_Msk    (0xffUL)       /*!< TSL (Bitfield-Mask: 0xff)                             */
32204 
32205 /* =========================================================================================================================== */
32206 /* ================                                           CFDC                                            ================ */
32207 /* =========================================================================================================================== */
32208 
32209 /* =========================================================  NCFG  ========================================================== */
32210  #define R_CANFD_CFDC_NCFG_NBRP_Pos      (0UL)          /*!< NBRP (Bit 0)                                          */
32211  #define R_CANFD_CFDC_NCFG_NBRP_Msk      (0x3ffUL)      /*!< NBRP (Bitfield-Mask: 0x3ff)                           */
32212  #define R_CANFD_CFDC_NCFG_NSJW_Pos      (10UL)         /*!< NSJW (Bit 10)                                         */
32213  #define R_CANFD_CFDC_NCFG_NSJW_Msk      (0x1fc00UL)    /*!< NSJW (Bitfield-Mask: 0x7f)                            */
32214  #define R_CANFD_CFDC_NCFG_NTSEG1_Pos    (17UL)         /*!< NTSEG1 (Bit 17)                                       */
32215  #define R_CANFD_CFDC_NCFG_NTSEG1_Msk    (0x1fe0000UL)  /*!< NTSEG1 (Bitfield-Mask: 0xff)                          */
32216  #define R_CANFD_CFDC_NCFG_NTSEG2_Pos    (25UL)         /*!< NTSEG2 (Bit 25)                                       */
32217  #define R_CANFD_CFDC_NCFG_NTSEG2_Msk    (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f)                          */
32218 /* ==========================================================  CTR  ========================================================== */
32219  #define R_CANFD_CFDC_CTR_CHMDC_Pos      (0UL)          /*!< CHMDC (Bit 0)                                         */
32220  #define R_CANFD_CFDC_CTR_CHMDC_Msk      (0x3UL)        /*!< CHMDC (Bitfield-Mask: 0x03)                           */
32221  #define R_CANFD_CFDC_CTR_CSLPR_Pos      (2UL)          /*!< CSLPR (Bit 2)                                         */
32222  #define R_CANFD_CFDC_CTR_CSLPR_Msk      (0x4UL)        /*!< CSLPR (Bitfield-Mask: 0x01)                           */
32223  #define R_CANFD_CFDC_CTR_RTBO_Pos       (3UL)          /*!< RTBO (Bit 3)                                          */
32224  #define R_CANFD_CFDC_CTR_RTBO_Msk       (0x8UL)        /*!< RTBO (Bitfield-Mask: 0x01)                            */
32225  #define R_CANFD_CFDC_CTR_BEIE_Pos       (8UL)          /*!< BEIE (Bit 8)                                          */
32226  #define R_CANFD_CFDC_CTR_BEIE_Msk       (0x100UL)      /*!< BEIE (Bitfield-Mask: 0x01)                            */
32227  #define R_CANFD_CFDC_CTR_EWIE_Pos       (9UL)          /*!< EWIE (Bit 9)                                          */
32228  #define R_CANFD_CFDC_CTR_EWIE_Msk       (0x200UL)      /*!< EWIE (Bitfield-Mask: 0x01)                            */
32229  #define R_CANFD_CFDC_CTR_EPIE_Pos       (10UL)         /*!< EPIE (Bit 10)                                         */
32230  #define R_CANFD_CFDC_CTR_EPIE_Msk       (0x400UL)      /*!< EPIE (Bitfield-Mask: 0x01)                            */
32231  #define R_CANFD_CFDC_CTR_BOEIE_Pos      (11UL)         /*!< BOEIE (Bit 11)                                        */
32232  #define R_CANFD_CFDC_CTR_BOEIE_Msk      (0x800UL)      /*!< BOEIE (Bitfield-Mask: 0x01)                           */
32233  #define R_CANFD_CFDC_CTR_BORIE_Pos      (12UL)         /*!< BORIE (Bit 12)                                        */
32234  #define R_CANFD_CFDC_CTR_BORIE_Msk      (0x1000UL)     /*!< BORIE (Bitfield-Mask: 0x01)                           */
32235  #define R_CANFD_CFDC_CTR_OLIE_Pos       (13UL)         /*!< OLIE (Bit 13)                                         */
32236  #define R_CANFD_CFDC_CTR_OLIE_Msk       (0x2000UL)     /*!< OLIE (Bitfield-Mask: 0x01)                            */
32237  #define R_CANFD_CFDC_CTR_BLIE_Pos       (14UL)         /*!< BLIE (Bit 14)                                         */
32238  #define R_CANFD_CFDC_CTR_BLIE_Msk       (0x4000UL)     /*!< BLIE (Bitfield-Mask: 0x01)                            */
32239  #define R_CANFD_CFDC_CTR_ALIE_Pos       (15UL)         /*!< ALIE (Bit 15)                                         */
32240  #define R_CANFD_CFDC_CTR_ALIE_Msk       (0x8000UL)     /*!< ALIE (Bitfield-Mask: 0x01)                            */
32241  #define R_CANFD_CFDC_CTR_TAIE_Pos       (16UL)         /*!< TAIE (Bit 16)                                         */
32242  #define R_CANFD_CFDC_CTR_TAIE_Msk       (0x10000UL)    /*!< TAIE (Bitfield-Mask: 0x01)                            */
32243  #define R_CANFD_CFDC_CTR_EOCOIE_Pos     (17UL)         /*!< EOCOIE (Bit 17)                                       */
32244  #define R_CANFD_CFDC_CTR_EOCOIE_Msk     (0x20000UL)    /*!< EOCOIE (Bitfield-Mask: 0x01)                          */
32245  #define R_CANFD_CFDC_CTR_SOCOIE_Pos     (18UL)         /*!< SOCOIE (Bit 18)                                       */
32246  #define R_CANFD_CFDC_CTR_SOCOIE_Msk     (0x40000UL)    /*!< SOCOIE (Bitfield-Mask: 0x01)                          */
32247  #define R_CANFD_CFDC_CTR_TDCVFIE_Pos    (19UL)         /*!< TDCVFIE (Bit 19)                                      */
32248  #define R_CANFD_CFDC_CTR_TDCVFIE_Msk    (0x80000UL)    /*!< TDCVFIE (Bitfield-Mask: 0x01)                         */
32249  #define R_CANFD_CFDC_CTR_BOM_Pos        (21UL)         /*!< BOM (Bit 21)                                          */
32250  #define R_CANFD_CFDC_CTR_BOM_Msk        (0x600000UL)   /*!< BOM (Bitfield-Mask: 0x03)                             */
32251  #define R_CANFD_CFDC_CTR_ERRD_Pos       (23UL)         /*!< ERRD (Bit 23)                                         */
32252  #define R_CANFD_CFDC_CTR_ERRD_Msk       (0x800000UL)   /*!< ERRD (Bitfield-Mask: 0x01)                            */
32253  #define R_CANFD_CFDC_CTR_CTME_Pos       (24UL)         /*!< CTME (Bit 24)                                         */
32254  #define R_CANFD_CFDC_CTR_CTME_Msk       (0x1000000UL)  /*!< CTME (Bitfield-Mask: 0x01)                            */
32255  #define R_CANFD_CFDC_CTR_CTMS_Pos       (25UL)         /*!< CTMS (Bit 25)                                         */
32256  #define R_CANFD_CFDC_CTR_CTMS_Msk       (0x6000000UL)  /*!< CTMS (Bitfield-Mask: 0x03)                            */
32257  #define R_CANFD_CFDC_CTR_TRWE_Pos       (27UL)         /*!< TRWE (Bit 27)                                         */
32258  #define R_CANFD_CFDC_CTR_TRWE_Msk       (0x8000000UL)  /*!< TRWE (Bitfield-Mask: 0x01)                            */
32259  #define R_CANFD_CFDC_CTR_TRH_Pos        (28UL)         /*!< TRH (Bit 28)                                          */
32260  #define R_CANFD_CFDC_CTR_TRH_Msk        (0x10000000UL) /*!< TRH (Bitfield-Mask: 0x01)                             */
32261  #define R_CANFD_CFDC_CTR_TRR_Pos        (29UL)         /*!< TRR (Bit 29)                                          */
32262  #define R_CANFD_CFDC_CTR_TRR_Msk        (0x20000000UL) /*!< TRR (Bitfield-Mask: 0x01)                             */
32263  #define R_CANFD_CFDC_CTR_CRCT_Pos       (30UL)         /*!< CRCT (Bit 30)                                         */
32264  #define R_CANFD_CFDC_CTR_CRCT_Msk       (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01)                            */
32265  #define R_CANFD_CFDC_CTR_ROM_Pos        (31UL)         /*!< ROM (Bit 31)                                          */
32266  #define R_CANFD_CFDC_CTR_ROM_Msk        (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01)                             */
32267 /* ==========================================================  STS  ========================================================== */
32268  #define R_CANFD_CFDC_STS_CRSTSTS_Pos    (0UL)          /*!< CRSTSTS (Bit 0)                                       */
32269  #define R_CANFD_CFDC_STS_CRSTSTS_Msk    (0x1UL)        /*!< CRSTSTS (Bitfield-Mask: 0x01)                         */
32270  #define R_CANFD_CFDC_STS_CHLTSTS_Pos    (1UL)          /*!< CHLTSTS (Bit 1)                                       */
32271  #define R_CANFD_CFDC_STS_CHLTSTS_Msk    (0x2UL)        /*!< CHLTSTS (Bitfield-Mask: 0x01)                         */
32272  #define R_CANFD_CFDC_STS_CSLPSTS_Pos    (2UL)          /*!< CSLPSTS (Bit 2)                                       */
32273  #define R_CANFD_CFDC_STS_CSLPSTS_Msk    (0x4UL)        /*!< CSLPSTS (Bitfield-Mask: 0x01)                         */
32274  #define R_CANFD_CFDC_STS_EPSTS_Pos      (3UL)          /*!< EPSTS (Bit 3)                                         */
32275  #define R_CANFD_CFDC_STS_EPSTS_Msk      (0x8UL)        /*!< EPSTS (Bitfield-Mask: 0x01)                           */
32276  #define R_CANFD_CFDC_STS_BOSTS_Pos      (4UL)          /*!< BOSTS (Bit 4)                                         */
32277  #define R_CANFD_CFDC_STS_BOSTS_Msk      (0x10UL)       /*!< BOSTS (Bitfield-Mask: 0x01)                           */
32278  #define R_CANFD_CFDC_STS_TRMSTS_Pos     (5UL)          /*!< TRMSTS (Bit 5)                                        */
32279  #define R_CANFD_CFDC_STS_TRMSTS_Msk     (0x20UL)       /*!< TRMSTS (Bitfield-Mask: 0x01)                          */
32280  #define R_CANFD_CFDC_STS_RECSTS_Pos     (6UL)          /*!< RECSTS (Bit 6)                                        */
32281  #define R_CANFD_CFDC_STS_RECSTS_Msk     (0x40UL)       /*!< RECSTS (Bitfield-Mask: 0x01)                          */
32282  #define R_CANFD_CFDC_STS_COMSTS_Pos     (7UL)          /*!< COMSTS (Bit 7)                                        */
32283  #define R_CANFD_CFDC_STS_COMSTS_Msk     (0x80UL)       /*!< COMSTS (Bitfield-Mask: 0x01)                          */
32284  #define R_CANFD_CFDC_STS_ESIF_Pos       (8UL)          /*!< ESIF (Bit 8)                                          */
32285  #define R_CANFD_CFDC_STS_ESIF_Msk       (0x100UL)      /*!< ESIF (Bitfield-Mask: 0x01)                            */
32286  #define R_CANFD_CFDC_STS_REC_Pos        (16UL)         /*!< REC (Bit 16)                                          */
32287  #define R_CANFD_CFDC_STS_REC_Msk        (0xff0000UL)   /*!< REC (Bitfield-Mask: 0xff)                             */
32288  #define R_CANFD_CFDC_STS_TEC_Pos        (24UL)         /*!< TEC (Bit 24)                                          */
32289  #define R_CANFD_CFDC_STS_TEC_Msk        (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff)                             */
32290 /* =========================================================  ERFL  ========================================================== */
32291  #define R_CANFD_CFDC_ERFL_BEF_Pos       (0UL)          /*!< BEF (Bit 0)                                           */
32292  #define R_CANFD_CFDC_ERFL_BEF_Msk       (0x1UL)        /*!< BEF (Bitfield-Mask: 0x01)                             */
32293  #define R_CANFD_CFDC_ERFL_EWF_Pos       (1UL)          /*!< EWF (Bit 1)                                           */
32294  #define R_CANFD_CFDC_ERFL_EWF_Msk       (0x2UL)        /*!< EWF (Bitfield-Mask: 0x01)                             */
32295  #define R_CANFD_CFDC_ERFL_EPF_Pos       (2UL)          /*!< EPF (Bit 2)                                           */
32296  #define R_CANFD_CFDC_ERFL_EPF_Msk       (0x4UL)        /*!< EPF (Bitfield-Mask: 0x01)                             */
32297  #define R_CANFD_CFDC_ERFL_BOEF_Pos      (3UL)          /*!< BOEF (Bit 3)                                          */
32298  #define R_CANFD_CFDC_ERFL_BOEF_Msk      (0x8UL)        /*!< BOEF (Bitfield-Mask: 0x01)                            */
32299  #define R_CANFD_CFDC_ERFL_BORF_Pos      (4UL)          /*!< BORF (Bit 4)                                          */
32300  #define R_CANFD_CFDC_ERFL_BORF_Msk      (0x10UL)       /*!< BORF (Bitfield-Mask: 0x01)                            */
32301  #define R_CANFD_CFDC_ERFL_OVLF_Pos      (5UL)          /*!< OVLF (Bit 5)                                          */
32302  #define R_CANFD_CFDC_ERFL_OVLF_Msk      (0x20UL)       /*!< OVLF (Bitfield-Mask: 0x01)                            */
32303  #define R_CANFD_CFDC_ERFL_BLF_Pos       (6UL)          /*!< BLF (Bit 6)                                           */
32304  #define R_CANFD_CFDC_ERFL_BLF_Msk       (0x40UL)       /*!< BLF (Bitfield-Mask: 0x01)                             */
32305  #define R_CANFD_CFDC_ERFL_ALF_Pos       (7UL)          /*!< ALF (Bit 7)                                           */
32306  #define R_CANFD_CFDC_ERFL_ALF_Msk       (0x80UL)       /*!< ALF (Bitfield-Mask: 0x01)                             */
32307  #define R_CANFD_CFDC_ERFL_SERR_Pos      (8UL)          /*!< SERR (Bit 8)                                          */
32308  #define R_CANFD_CFDC_ERFL_SERR_Msk      (0x100UL)      /*!< SERR (Bitfield-Mask: 0x01)                            */
32309  #define R_CANFD_CFDC_ERFL_FERR_Pos      (9UL)          /*!< FERR (Bit 9)                                          */
32310  #define R_CANFD_CFDC_ERFL_FERR_Msk      (0x200UL)      /*!< FERR (Bitfield-Mask: 0x01)                            */
32311  #define R_CANFD_CFDC_ERFL_AERR_Pos      (10UL)         /*!< AERR (Bit 10)                                         */
32312  #define R_CANFD_CFDC_ERFL_AERR_Msk      (0x400UL)      /*!< AERR (Bitfield-Mask: 0x01)                            */
32313  #define R_CANFD_CFDC_ERFL_CERR_Pos      (11UL)         /*!< CERR (Bit 11)                                         */
32314  #define R_CANFD_CFDC_ERFL_CERR_Msk      (0x800UL)      /*!< CERR (Bitfield-Mask: 0x01)                            */
32315  #define R_CANFD_CFDC_ERFL_B1ERR_Pos     (12UL)         /*!< B1ERR (Bit 12)                                        */
32316  #define R_CANFD_CFDC_ERFL_B1ERR_Msk     (0x1000UL)     /*!< B1ERR (Bitfield-Mask: 0x01)                           */
32317  #define R_CANFD_CFDC_ERFL_B0ERR_Pos     (13UL)         /*!< B0ERR (Bit 13)                                        */
32318  #define R_CANFD_CFDC_ERFL_B0ERR_Msk     (0x2000UL)     /*!< B0ERR (Bitfield-Mask: 0x01)                           */
32319  #define R_CANFD_CFDC_ERFL_ADERR_Pos     (14UL)         /*!< ADERR (Bit 14)                                        */
32320  #define R_CANFD_CFDC_ERFL_ADERR_Msk     (0x4000UL)     /*!< ADERR (Bitfield-Mask: 0x01)                           */
32321  #define R_CANFD_CFDC_ERFL_CRCREG_Pos    (16UL)         /*!< CRCREG (Bit 16)                                       */
32322  #define R_CANFD_CFDC_ERFL_CRCREG_Msk    (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff)                        */
32323 
32324 /* =========================================================================================================================== */
32325 /* ================                                           CFDC2                                           ================ */
32326 /* =========================================================================================================================== */
32327 
32328 /* =========================================================  DCFG  ========================================================== */
32329  #define R_CANFD_CFDC2_DCFG_DBRP_Pos       (0UL)          /*!< DBRP (Bit 0)                                          */
32330  #define R_CANFD_CFDC2_DCFG_DBRP_Msk       (0xffUL)       /*!< DBRP (Bitfield-Mask: 0xff)                            */
32331  #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos     (8UL)          /*!< DTSEG1 (Bit 8)                                        */
32332  #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk     (0x1f00UL)     /*!< DTSEG1 (Bitfield-Mask: 0x1f)                          */
32333  #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos     (16UL)         /*!< DTSEG2 (Bit 16)                                       */
32334  #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk     (0xf0000UL)    /*!< DTSEG2 (Bitfield-Mask: 0x0f)                          */
32335  #define R_CANFD_CFDC2_DCFG_DSJW_Pos       (24UL)         /*!< DSJW (Bit 24)                                         */
32336  #define R_CANFD_CFDC2_DCFG_DSJW_Msk       (0xf000000UL)  /*!< DSJW (Bitfield-Mask: 0x0f)                            */
32337 /* =========================================================  FDCFG  ========================================================= */
32338  #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos    (0UL)          /*!< EOCCFG (Bit 0)                                        */
32339  #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk    (0x7UL)        /*!< EOCCFG (Bitfield-Mask: 0x07)                          */
32340  #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos     (8UL)          /*!< TDCOC (Bit 8)                                         */
32341  #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk     (0x100UL)      /*!< TDCOC (Bitfield-Mask: 0x01)                           */
32342  #define R_CANFD_CFDC2_FDCFG_TDCE_Pos      (9UL)          /*!< TDCE (Bit 9)                                          */
32343  #define R_CANFD_CFDC2_FDCFG_TDCE_Msk      (0x200UL)      /*!< TDCE (Bitfield-Mask: 0x01)                            */
32344  #define R_CANFD_CFDC2_FDCFG_ESIC_Pos      (10UL)         /*!< ESIC (Bit 10)                                         */
32345  #define R_CANFD_CFDC2_FDCFG_ESIC_Msk      (0x400UL)      /*!< ESIC (Bitfield-Mask: 0x01)                            */
32346  #define R_CANFD_CFDC2_FDCFG_TDCO_Pos      (16UL)         /*!< TDCO (Bit 16)                                         */
32347  #define R_CANFD_CFDC2_FDCFG_TDCO_Msk      (0xff0000UL)   /*!< TDCO (Bitfield-Mask: 0xff)                            */
32348  #define R_CANFD_CFDC2_FDCFG_GWEN_Pos      (24UL)         /*!< GWEN (Bit 24)                                         */
32349  #define R_CANFD_CFDC2_FDCFG_GWEN_Msk      (0x1000000UL)  /*!< GWEN (Bitfield-Mask: 0x01)                            */
32350  #define R_CANFD_CFDC2_FDCFG_GWFDF_Pos     (25UL)         /*!< GWFDF (Bit 25)                                        */
32351  #define R_CANFD_CFDC2_FDCFG_GWFDF_Msk     (0x2000000UL)  /*!< GWFDF (Bitfield-Mask: 0x01)                           */
32352  #define R_CANFD_CFDC2_FDCFG_GWBRS_Pos     (26UL)         /*!< GWBRS (Bit 26)                                        */
32353  #define R_CANFD_CFDC2_FDCFG_GWBRS_Msk     (0x4000000UL)  /*!< GWBRS (Bitfield-Mask: 0x01)                           */
32354  #define R_CANFD_CFDC2_FDCFG_FDOE_Pos      (28UL)         /*!< FDOE (Bit 28)                                         */
32355  #define R_CANFD_CFDC2_FDCFG_FDOE_Msk      (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01)                            */
32356  #define R_CANFD_CFDC2_FDCFG_REFE_Pos      (29UL)         /*!< REFE (Bit 29)                                         */
32357  #define R_CANFD_CFDC2_FDCFG_REFE_Msk      (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01)                            */
32358  #define R_CANFD_CFDC2_FDCFG_CLOE_Pos      (30UL)         /*!< CLOE (Bit 30)                                         */
32359  #define R_CANFD_CFDC2_FDCFG_CLOE_Msk      (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01)                            */
32360  #define R_CANFD_CFDC2_FDCFG_CFDTE_Pos     (31UL)         /*!< CFDTE (Bit 31)                                        */
32361  #define R_CANFD_CFDC2_FDCFG_CFDTE_Msk     (0x80000000UL) /*!< CFDTE (Bitfield-Mask: 0x01)                           */
32362 /* =========================================================  FDCTR  ========================================================= */
32363  #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos    (0UL)          /*!< EOCCLR (Bit 0)                                        */
32364  #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk    (0x1UL)        /*!< EOCCLR (Bitfield-Mask: 0x01)                          */
32365  #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos    (1UL)          /*!< SOCCLR (Bit 1)                                        */
32366  #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk    (0x2UL)        /*!< SOCCLR (Bitfield-Mask: 0x01)                          */
32367 /* =========================================================  FDSTS  ========================================================= */
32368  #define R_CANFD_CFDC2_FDSTS_TDCR_Pos      (0UL)          /*!< TDCR (Bit 0)                                          */
32369  #define R_CANFD_CFDC2_FDSTS_TDCR_Msk      (0xffUL)       /*!< TDCR (Bitfield-Mask: 0xff)                            */
32370  #define R_CANFD_CFDC2_FDSTS_EOCO_Pos      (8UL)          /*!< EOCO (Bit 8)                                          */
32371  #define R_CANFD_CFDC2_FDSTS_EOCO_Msk      (0x100UL)      /*!< EOCO (Bitfield-Mask: 0x01)                            */
32372  #define R_CANFD_CFDC2_FDSTS_SOCO_Pos      (9UL)          /*!< SOCO (Bit 9)                                          */
32373  #define R_CANFD_CFDC2_FDSTS_SOCO_Msk      (0x200UL)      /*!< SOCO (Bitfield-Mask: 0x01)                            */
32374  #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos     (15UL)         /*!< TDCVF (Bit 15)                                        */
32375  #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk     (0x8000UL)     /*!< TDCVF (Bitfield-Mask: 0x01)                           */
32376  #define R_CANFD_CFDC2_FDSTS_EOC_Pos       (16UL)         /*!< EOC (Bit 16)                                          */
32377  #define R_CANFD_CFDC2_FDSTS_EOC_Msk       (0xff0000UL)   /*!< EOC (Bitfield-Mask: 0xff)                             */
32378  #define R_CANFD_CFDC2_FDSTS_SOC_Pos       (24UL)         /*!< SOC (Bit 24)                                          */
32379  #define R_CANFD_CFDC2_FDSTS_SOC_Msk       (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff)                             */
32380 /* =========================================================  FDCRC  ========================================================= */
32381  #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos    (0UL)          /*!< CRCREG (Bit 0)                                        */
32382  #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk    (0x1fffffUL)   /*!< CRCREG (Bitfield-Mask: 0x1fffff)                      */
32383  #define R_CANFD_CFDC2_FDCRC_SCNT_Pos      (24UL)         /*!< SCNT (Bit 24)                                         */
32384  #define R_CANFD_CFDC2_FDCRC_SCNT_Msk      (0xf000000UL)  /*!< SCNT (Bitfield-Mask: 0x0f)                            */
32385 /* =========================================================  BLCT  ========================================================== */
32386  #define R_CANFD_CFDC2_BLCT_BLCE_Pos       (0UL)          /*!< BLCE (Bit 0)                                          */
32387  #define R_CANFD_CFDC2_BLCT_BLCE_Msk       (0x1UL)        /*!< BLCE (Bitfield-Mask: 0x01)                            */
32388  #define R_CANFD_CFDC2_BLCT_BLCLD_Pos      (8UL)          /*!< BLCLD (Bit 8)                                         */
32389  #define R_CANFD_CFDC2_BLCT_BLCLD_Msk      (0x100UL)      /*!< BLCLD (Bitfield-Mask: 0x01)                           */
32390 /* =========================================================  BLSTS  ========================================================= */
32391  #define R_CANFD_CFDC2_BLSTS_BLC_Pos       (3UL)          /*!< BLC (Bit 3)                                           */
32392  #define R_CANFD_CFDC2_BLSTS_BLC_Msk       (0xfffffff8UL) /*!< BLC (Bitfield-Mask: 0x1fffffff)                       */
32393 
32394 /* =========================================================================================================================== */
32395 /* ================                                          CFDGAFL                                          ================ */
32396 /* =========================================================================================================================== */
32397 
32398 /* ==========================================================  ID  =========================================================== */
32399  #define R_CANFD_CFDGAFL_ID_GAFLID_Pos      (0UL)          /*!< GAFLID (Bit 0)                                        */
32400  #define R_CANFD_CFDGAFL_ID_GAFLID_Msk      (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff)                    */
32401  #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos      (29UL)         /*!< GAFLLB (Bit 29)                                       */
32402  #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk      (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01)                          */
32403  #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos     (30UL)         /*!< GAFLRTR (Bit 30)                                      */
32404  #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk     (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01)                         */
32405  #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos     (31UL)         /*!< GAFLIDE (Bit 31)                                      */
32406  #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk     (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01)                         */
32407 /* ===========================================================  M  =========================================================== */
32408  #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos      (0UL)          /*!< GAFLIDM (Bit 0)                                       */
32409  #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk      (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff)                   */
32410  #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos     (29UL)         /*!< GAFLIFL1 (Bit 29)                                     */
32411  #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk     (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01)                        */
32412  #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos     (30UL)         /*!< GAFLRTRM (Bit 30)                                     */
32413  #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk     (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01)                        */
32414  #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos     (31UL)         /*!< GAFLIDEM (Bit 31)                                     */
32415  #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk     (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01)                        */
32416 /* ==========================================================  P0  =========================================================== */
32417  #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos     (0UL)          /*!< GAFLDLC (Bit 0)                                       */
32418  #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk     (0xfUL)        /*!< GAFLDLC (Bitfield-Mask: 0x0f)                         */
32419  #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Pos    (4UL)          /*!< GAFLSRD0 (Bit 4)                                      */
32420  #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Msk    (0x10UL)       /*!< GAFLSRD0 (Bitfield-Mask: 0x01)                        */
32421  #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Pos    (5UL)          /*!< GAFLSRD1 (Bit 5)                                      */
32422  #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Msk    (0x20UL)       /*!< GAFLSRD1 (Bitfield-Mask: 0x01)                        */
32423  #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Pos    (6UL)          /*!< GAFLSRD2 (Bit 6)                                      */
32424  #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Msk    (0x40UL)       /*!< GAFLSRD2 (Bitfield-Mask: 0x01)                        */
32425  #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos    (7UL)          /*!< GAFLIFL0 (Bit 7)                                      */
32426  #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk    (0x80UL)       /*!< GAFLIFL0 (Bitfield-Mask: 0x01)                        */
32427  #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos    (8UL)          /*!< GAFLRMDP (Bit 8)                                      */
32428  #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk    (0x1f00UL)     /*!< GAFLRMDP (Bitfield-Mask: 0x1f)                        */
32429  #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos     (15UL)         /*!< GAFLRMV (Bit 15)                                      */
32430  #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk     (0x8000UL)     /*!< GAFLRMV (Bitfield-Mask: 0x01)                         */
32431  #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos     (16UL)         /*!< GAFLPTR (Bit 16)                                      */
32432  #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk     (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff)                       */
32433 /* ==========================================================  P1  =========================================================== */
32434  #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos     (0UL)          /*!< GAFLFDP (Bit 0)                                       */
32435  #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk     (0x3fffUL)     /*!< GAFLFDP (Bitfield-Mask: 0x3fff)                       */
32436 
32437 /* =========================================================================================================================== */
32438 /* ================                                          CFDTHL                                           ================ */
32439 /* =========================================================================================================================== */
32440 
32441 /* =========================================================  ACC0  ========================================================== */
32442  #define R_CANFD_CFDTHL_ACC0_BT_Pos      (0UL)          /*!< BT (Bit 0)                                            */
32443  #define R_CANFD_CFDTHL_ACC0_BT_Msk      (0x7UL)        /*!< BT (Bitfield-Mask: 0x07)                              */
32444  #define R_CANFD_CFDTHL_ACC0_BN_Pos      (3UL)          /*!< BN (Bit 3)                                            */
32445  #define R_CANFD_CFDTHL_ACC0_BN_Msk      (0x3f8UL)      /*!< BN (Bitfield-Mask: 0x7f)                              */
32446  #define R_CANFD_CFDTHL_ACC0_TGW_Pos     (15UL)         /*!< TGW (Bit 15)                                          */
32447  #define R_CANFD_CFDTHL_ACC0_TGW_Msk     (0x8000UL)     /*!< TGW (Bitfield-Mask: 0x01)                             */
32448  #define R_CANFD_CFDTHL_ACC0_TMTS_Pos    (16UL)         /*!< TMTS (Bit 16)                                         */
32449  #define R_CANFD_CFDTHL_ACC0_TMTS_Msk    (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff)                          */
32450 /* =========================================================  ACC1  ========================================================== */
32451  #define R_CANFD_CFDTHL_ACC1_TID_Pos     (0UL)          /*!< TID (Bit 0)                                           */
32452  #define R_CANFD_CFDTHL_ACC1_TID_Msk     (0xffffUL)     /*!< TID (Bitfield-Mask: 0xffff)                           */
32453  #define R_CANFD_CFDTHL_ACC1_TIFL_Pos    (16UL)         /*!< TIFL (Bit 16)                                         */
32454  #define R_CANFD_CFDTHL_ACC1_TIFL_Msk    (0x30000UL)    /*!< TIFL (Bitfield-Mask: 0x03)                            */
32455 
32456 /* =========================================================================================================================== */
32457 /* ================                                           CFDRM                                           ================ */
32458 /* =========================================================================================================================== */
32459 
32460 /* ==========================================================  ID  =========================================================== */
32461  #define R_CANFD_CFDRM_ID_RMID_Pos        (0UL)          /*!< RMID (Bit 0)                                          */
32462  #define R_CANFD_CFDRM_ID_RMID_Msk        (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff)                      */
32463  #define R_CANFD_CFDRM_ID_RMRTR_Pos       (30UL)         /*!< RMRTR (Bit 30)                                        */
32464  #define R_CANFD_CFDRM_ID_RMRTR_Msk       (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01)                           */
32465  #define R_CANFD_CFDRM_ID_RMIDE_Pos       (31UL)         /*!< RMIDE (Bit 31)                                        */
32466  #define R_CANFD_CFDRM_ID_RMIDE_Msk       (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01)                           */
32467 /* ==========================================================  PTR  ========================================================== */
32468  #define R_CANFD_CFDRM_PTR_RMTS_Pos       (0UL)          /*!< RMTS (Bit 0)                                          */
32469  #define R_CANFD_CFDRM_PTR_RMTS_Msk       (0xffffUL)     /*!< RMTS (Bitfield-Mask: 0xffff)                          */
32470  #define R_CANFD_CFDRM_PTR_RMDLC_Pos      (28UL)         /*!< RMDLC (Bit 28)                                        */
32471  #define R_CANFD_CFDRM_PTR_RMDLC_Msk      (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f)                           */
32472 /* =========================================================  FDSTS  ========================================================= */
32473  #define R_CANFD_CFDRM_FDSTS_RMESI_Pos    (0UL)          /*!< RMESI (Bit 0)                                         */
32474  #define R_CANFD_CFDRM_FDSTS_RMESI_Msk    (0x1UL)        /*!< RMESI (Bitfield-Mask: 0x01)                           */
32475  #define R_CANFD_CFDRM_FDSTS_RMBRS_Pos    (1UL)          /*!< RMBRS (Bit 1)                                         */
32476  #define R_CANFD_CFDRM_FDSTS_RMBRS_Msk    (0x2UL)        /*!< RMBRS (Bitfield-Mask: 0x01)                           */
32477  #define R_CANFD_CFDRM_FDSTS_RMFDF_Pos    (2UL)          /*!< RMFDF (Bit 2)                                         */
32478  #define R_CANFD_CFDRM_FDSTS_RMFDF_Msk    (0x4UL)        /*!< RMFDF (Bitfield-Mask: 0x01)                           */
32479  #define R_CANFD_CFDRM_FDSTS_RMIFL_Pos    (8UL)          /*!< RMIFL (Bit 8)                                         */
32480  #define R_CANFD_CFDRM_FDSTS_RMIFL_Msk    (0x300UL)      /*!< RMIFL (Bitfield-Mask: 0x03)                           */
32481  #define R_CANFD_CFDRM_FDSTS_RMPTR_Pos    (16UL)         /*!< RMPTR (Bit 16)                                        */
32482  #define R_CANFD_CFDRM_FDSTS_RMPTR_Msk    (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff)                         */
32483 /* ==========================================================  DF  =========================================================== */
32484  #define R_CANFD_CFDRM_DF_RMDB_Pos        (0UL)          /*!< RMDB (Bit 0)                                          */
32485  #define R_CANFD_CFDRM_DF_RMDB_Msk        (0xffUL)       /*!< RMDB (Bitfield-Mask: 0xff)                            */
32486 
32487 /* =========================================================================================================================== */
32488 /* ================                                           CFDRF                                           ================ */
32489 /* =========================================================================================================================== */
32490 
32491 /* ==========================================================  ID  =========================================================== */
32492  #define R_CANFD_CFDRF_ID_RFID_Pos        (0UL)          /*!< RFID (Bit 0)                                          */
32493  #define R_CANFD_CFDRF_ID_RFID_Msk        (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff)                      */
32494  #define R_CANFD_CFDRF_ID_RFRTR_Pos       (30UL)         /*!< RFRTR (Bit 30)                                        */
32495  #define R_CANFD_CFDRF_ID_RFRTR_Msk       (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01)                           */
32496  #define R_CANFD_CFDRF_ID_RFIDE_Pos       (31UL)         /*!< RFIDE (Bit 31)                                        */
32497  #define R_CANFD_CFDRF_ID_RFIDE_Msk       (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01)                           */
32498 /* ==========================================================  PTR  ========================================================== */
32499  #define R_CANFD_CFDRF_PTR_RFTS_Pos       (0UL)          /*!< RFTS (Bit 0)                                          */
32500  #define R_CANFD_CFDRF_PTR_RFTS_Msk       (0xffffUL)     /*!< RFTS (Bitfield-Mask: 0xffff)                          */
32501  #define R_CANFD_CFDRF_PTR_RFDLC_Pos      (28UL)         /*!< RFDLC (Bit 28)                                        */
32502  #define R_CANFD_CFDRF_PTR_RFDLC_Msk      (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f)                           */
32503 /* =========================================================  FDSTS  ========================================================= */
32504  #define R_CANFD_CFDRF_FDSTS_RFESI_Pos    (0UL)          /*!< RFESI (Bit 0)                                         */
32505  #define R_CANFD_CFDRF_FDSTS_RFESI_Msk    (0x1UL)        /*!< RFESI (Bitfield-Mask: 0x01)                           */
32506  #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos    (1UL)          /*!< RFBRS (Bit 1)                                         */
32507  #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk    (0x2UL)        /*!< RFBRS (Bitfield-Mask: 0x01)                           */
32508  #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos    (2UL)          /*!< RFFDF (Bit 2)                                         */
32509  #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk    (0x4UL)        /*!< RFFDF (Bitfield-Mask: 0x01)                           */
32510  #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos    (8UL)          /*!< RFIFL (Bit 8)                                         */
32511  #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk    (0x300UL)      /*!< RFIFL (Bitfield-Mask: 0x03)                           */
32512  #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos    (16UL)         /*!< RFPTR (Bit 16)                                        */
32513  #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk    (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff)                         */
32514 /* ==========================================================  DF  =========================================================== */
32515  #define R_CANFD_CFDRF_DF_RFDB_Pos        (0UL)          /*!< RFDB (Bit 0)                                          */
32516  #define R_CANFD_CFDRF_DF_RFDB_Msk        (0xffUL)       /*!< RFDB (Bitfield-Mask: 0xff)                            */
32517 
32518 /* =========================================================================================================================== */
32519 /* ================                                           CFDCF                                           ================ */
32520 /* =========================================================================================================================== */
32521 
32522 /* ==========================================================  ID  =========================================================== */
32523  #define R_CANFD_CFDCF_ID_CFID_Pos        (0UL)          /*!< CFID (Bit 0)                                          */
32524  #define R_CANFD_CFDCF_ID_CFID_Msk        (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff)                      */
32525  #define R_CANFD_CFDCF_ID_CFRTR_Pos       (30UL)         /*!< CFRTR (Bit 30)                                        */
32526  #define R_CANFD_CFDCF_ID_CFRTR_Msk       (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01)                           */
32527  #define R_CANFD_CFDCF_ID_CFIDE_Pos       (31UL)         /*!< CFIDE (Bit 31)                                        */
32528  #define R_CANFD_CFDCF_ID_CFIDE_Msk       (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01)                           */
32529 /* ==========================================================  PTR  ========================================================== */
32530  #define R_CANFD_CFDCF_PTR_CFTS_Pos       (0UL)          /*!< CFTS (Bit 0)                                          */
32531  #define R_CANFD_CFDCF_PTR_CFTS_Msk       (0xffffUL)     /*!< CFTS (Bitfield-Mask: 0xffff)                          */
32532  #define R_CANFD_CFDCF_PTR_CFDLC_Pos      (28UL)         /*!< CFDLC (Bit 28)                                        */
32533  #define R_CANFD_CFDCF_PTR_CFDLC_Msk      (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f)                           */
32534 /* =========================================================  FDSTS  ========================================================= */
32535  #define R_CANFD_CFDCF_FDSTS_CFESI_Pos    (0UL)          /*!< CFESI (Bit 0)                                         */
32536  #define R_CANFD_CFDCF_FDSTS_CFESI_Msk    (0x1UL)        /*!< CFESI (Bitfield-Mask: 0x01)                           */
32537  #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos    (1UL)          /*!< CFBRS (Bit 1)                                         */
32538  #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk    (0x2UL)        /*!< CFBRS (Bitfield-Mask: 0x01)                           */
32539  #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos    (2UL)          /*!< CFFDF (Bit 2)                                         */
32540  #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk    (0x4UL)        /*!< CFFDF (Bitfield-Mask: 0x01)                           */
32541  #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos    (8UL)          /*!< CFIFL (Bit 8)                                         */
32542  #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk    (0x300UL)      /*!< CFIFL (Bitfield-Mask: 0x03)                           */
32543  #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos    (16UL)         /*!< CFPTR (Bit 16)                                        */
32544  #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk    (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff)                         */
32545 /* ==========================================================  DF  =========================================================== */
32546  #define R_CANFD_CFDCF_DF_CFDB_Pos        (0UL)          /*!< CFDB (Bit 0)                                          */
32547  #define R_CANFD_CFDCF_DF_CFDB_Msk        (0xffUL)       /*!< CFDB (Bitfield-Mask: 0xff)                            */
32548 
32549 /* =========================================================================================================================== */
32550 /* ================                                           CFDTM                                           ================ */
32551 /* =========================================================================================================================== */
32552 
32553 /* ==========================================================  ID  =========================================================== */
32554  #define R_CANFD_CFDTM_ID_TMID_Pos        (0UL)          /*!< TMID (Bit 0)                                          */
32555  #define R_CANFD_CFDTM_ID_TMID_Msk        (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff)                      */
32556  #define R_CANFD_CFDTM_ID_TMRTR_Pos       (30UL)         /*!< TMRTR (Bit 30)                                        */
32557  #define R_CANFD_CFDTM_ID_TMRTR_Msk       (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01)                           */
32558  #define R_CANFD_CFDTM_ID_TMIDE_Pos       (31UL)         /*!< TMIDE (Bit 31)                                        */
32559  #define R_CANFD_CFDTM_ID_TMIDE_Msk       (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01)                           */
32560 /* ==========================================================  PTR  ========================================================== */
32561  #define R_CANFD_CFDTM_PTR_TMTS_Pos       (0UL)          /*!< TMTS (Bit 0)                                          */
32562  #define R_CANFD_CFDTM_PTR_TMTS_Msk       (0xffffUL)     /*!< TMTS (Bitfield-Mask: 0xffff)                          */
32563  #define R_CANFD_CFDTM_PTR_TMDLC_Pos      (28UL)         /*!< TMDLC (Bit 28)                                        */
32564  #define R_CANFD_CFDTM_PTR_TMDLC_Msk      (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f)                           */
32565 /* =========================================================  FDCTR  ========================================================= */
32566  #define R_CANFD_CFDTM_FDCTR_TMESI_Pos    (0UL)          /*!< TMESI (Bit 0)                                         */
32567  #define R_CANFD_CFDTM_FDCTR_TMESI_Msk    (0x1UL)        /*!< TMESI (Bitfield-Mask: 0x01)                           */
32568  #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos    (1UL)          /*!< TMBRS (Bit 1)                                         */
32569  #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk    (0x2UL)        /*!< TMBRS (Bitfield-Mask: 0x01)                           */
32570  #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos    (2UL)          /*!< TMFDF (Bit 2)                                         */
32571  #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk    (0x4UL)        /*!< TMFDF (Bitfield-Mask: 0x01)                           */
32572  #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos    (8UL)          /*!< TMIFL (Bit 8)                                         */
32573  #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk    (0x300UL)      /*!< TMIFL (Bitfield-Mask: 0x03)                           */
32574  #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos    (16UL)         /*!< TMPTR (Bit 16)                                        */
32575  #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk    (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff)                         */
32576 /* ==========================================================  DF  =========================================================== */
32577  #define R_CANFD_CFDTM_DF_TMDB_Pos        (0UL)          /*!< TMDB (Bit 0)                                          */
32578  #define R_CANFD_CFDTM_DF_TMDB_Msk        (0xffUL)       /*!< TMDB (Bitfield-Mask: 0xff)                            */
32579 
32580 /* =========================================================================================================================== */
32581 /* ================                                           CFDC                                            ================ */
32582 /* =========================================================================================================================== */
32583 
32584 /* =========================================================  NCFG  ========================================================== */
32585  #define R_CANFDL_CFDC_NCFG_NBRP_Pos      (0UL)          /*!< NBRP (Bit 0)                                          */
32586  #define R_CANFDL_CFDC_NCFG_NBRP_Msk      (0x3ffUL)      /*!< NBRP (Bitfield-Mask: 0x3ff)                           */
32587  #define R_CANFDL_CFDC_NCFG_NSJW_Pos      (10UL)         /*!< NSJW (Bit 10)                                         */
32588  #define R_CANFDL_CFDC_NCFG_NSJW_Msk      (0x1fc00UL)    /*!< NSJW (Bitfield-Mask: 0x7f)                            */
32589  #define R_CANFDL_CFDC_NCFG_NTSEG1_Pos    (17UL)         /*!< NTSEG1 (Bit 17)                                       */
32590  #define R_CANFDL_CFDC_NCFG_NTSEG1_Msk    (0x1fe0000UL)  /*!< NTSEG1 (Bitfield-Mask: 0xff)                          */
32591  #define R_CANFDL_CFDC_NCFG_NTSEG2_Pos    (25UL)         /*!< NTSEG2 (Bit 25)                                       */
32592  #define R_CANFDL_CFDC_NCFG_NTSEG2_Msk    (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f)                          */
32593 /* ==========================================================  CTR  ========================================================== */
32594  #define R_CANFDL_CFDC_CTR_CHMDC_Pos      (0UL)          /*!< CHMDC (Bit 0)                                         */
32595  #define R_CANFDL_CFDC_CTR_CHMDC_Msk      (0x3UL)        /*!< CHMDC (Bitfield-Mask: 0x03)                           */
32596  #define R_CANFDL_CFDC_CTR_CSLPR_Pos      (2UL)          /*!< CSLPR (Bit 2)                                         */
32597  #define R_CANFDL_CFDC_CTR_CSLPR_Msk      (0x4UL)        /*!< CSLPR (Bitfield-Mask: 0x01)                           */
32598  #define R_CANFDL_CFDC_CTR_RTBO_Pos       (3UL)          /*!< RTBO (Bit 3)                                          */
32599  #define R_CANFDL_CFDC_CTR_RTBO_Msk       (0x8UL)        /*!< RTBO (Bitfield-Mask: 0x01)                            */
32600  #define R_CANFDL_CFDC_CTR_BEIE_Pos       (8UL)          /*!< BEIE (Bit 8)                                          */
32601  #define R_CANFDL_CFDC_CTR_BEIE_Msk       (0x100UL)      /*!< BEIE (Bitfield-Mask: 0x01)                            */
32602  #define R_CANFDL_CFDC_CTR_EWIE_Pos       (9UL)          /*!< EWIE (Bit 9)                                          */
32603  #define R_CANFDL_CFDC_CTR_EWIE_Msk       (0x200UL)      /*!< EWIE (Bitfield-Mask: 0x01)                            */
32604  #define R_CANFDL_CFDC_CTR_EPIE_Pos       (10UL)         /*!< EPIE (Bit 10)                                         */
32605  #define R_CANFDL_CFDC_CTR_EPIE_Msk       (0x400UL)      /*!< EPIE (Bitfield-Mask: 0x01)                            */
32606  #define R_CANFDL_CFDC_CTR_BOEIE_Pos      (11UL)         /*!< BOEIE (Bit 11)                                        */
32607  #define R_CANFDL_CFDC_CTR_BOEIE_Msk      (0x800UL)      /*!< BOEIE (Bitfield-Mask: 0x01)                           */
32608  #define R_CANFDL_CFDC_CTR_BORIE_Pos      (12UL)         /*!< BORIE (Bit 12)                                        */
32609  #define R_CANFDL_CFDC_CTR_BORIE_Msk      (0x1000UL)     /*!< BORIE (Bitfield-Mask: 0x01)                           */
32610  #define R_CANFDL_CFDC_CTR_OLIE_Pos       (13UL)         /*!< OLIE (Bit 13)                                         */
32611  #define R_CANFDL_CFDC_CTR_OLIE_Msk       (0x2000UL)     /*!< OLIE (Bitfield-Mask: 0x01)                            */
32612  #define R_CANFDL_CFDC_CTR_BLIE_Pos       (14UL)         /*!< BLIE (Bit 14)                                         */
32613  #define R_CANFDL_CFDC_CTR_BLIE_Msk       (0x4000UL)     /*!< BLIE (Bitfield-Mask: 0x01)                            */
32614  #define R_CANFDL_CFDC_CTR_ALIE_Pos       (15UL)         /*!< ALIE (Bit 15)                                         */
32615  #define R_CANFDL_CFDC_CTR_ALIE_Msk       (0x8000UL)     /*!< ALIE (Bitfield-Mask: 0x01)                            */
32616  #define R_CANFDL_CFDC_CTR_TAIE_Pos       (16UL)         /*!< TAIE (Bit 16)                                         */
32617  #define R_CANFDL_CFDC_CTR_TAIE_Msk       (0x10000UL)    /*!< TAIE (Bitfield-Mask: 0x01)                            */
32618  #define R_CANFDL_CFDC_CTR_EOCOIE_Pos     (17UL)         /*!< EOCOIE (Bit 17)                                       */
32619  #define R_CANFDL_CFDC_CTR_EOCOIE_Msk     (0x20000UL)    /*!< EOCOIE (Bitfield-Mask: 0x01)                          */
32620  #define R_CANFDL_CFDC_CTR_SOCOIE_Pos     (18UL)         /*!< SOCOIE (Bit 18)                                       */
32621  #define R_CANFDL_CFDC_CTR_SOCOIE_Msk     (0x40000UL)    /*!< SOCOIE (Bitfield-Mask: 0x01)                          */
32622  #define R_CANFDL_CFDC_CTR_TDCVFIE_Pos    (19UL)         /*!< TDCVFIE (Bit 19)                                      */
32623  #define R_CANFDL_CFDC_CTR_TDCVFIE_Msk    (0x80000UL)    /*!< TDCVFIE (Bitfield-Mask: 0x01)                         */
32624  #define R_CANFDL_CFDC_CTR_BOM_Pos        (21UL)         /*!< BOM (Bit 21)                                          */
32625  #define R_CANFDL_CFDC_CTR_BOM_Msk        (0x600000UL)   /*!< BOM (Bitfield-Mask: 0x03)                             */
32626  #define R_CANFDL_CFDC_CTR_ERRD_Pos       (23UL)         /*!< ERRD (Bit 23)                                         */
32627  #define R_CANFDL_CFDC_CTR_ERRD_Msk       (0x800000UL)   /*!< ERRD (Bitfield-Mask: 0x01)                            */
32628  #define R_CANFDL_CFDC_CTR_CTME_Pos       (24UL)         /*!< CTME (Bit 24)                                         */
32629  #define R_CANFDL_CFDC_CTR_CTME_Msk       (0x1000000UL)  /*!< CTME (Bitfield-Mask: 0x01)                            */
32630  #define R_CANFDL_CFDC_CTR_CTMS_Pos       (25UL)         /*!< CTMS (Bit 25)                                         */
32631  #define R_CANFDL_CFDC_CTR_CTMS_Msk       (0x6000000UL)  /*!< CTMS (Bitfield-Mask: 0x03)                            */
32632  #define R_CANFDL_CFDC_CTR_CRCT_Pos       (30UL)         /*!< CRCT (Bit 30)                                         */
32633  #define R_CANFDL_CFDC_CTR_CRCT_Msk       (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01)                            */
32634  #define R_CANFDL_CFDC_CTR_ROM_Pos        (31UL)         /*!< ROM (Bit 31)                                          */
32635  #define R_CANFDL_CFDC_CTR_ROM_Msk        (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01)                             */
32636 /* ==========================================================  STS  ========================================================== */
32637  #define R_CANFDL_CFDC_STS_CRSTSTS_Pos    (0UL)          /*!< CRSTSTS (Bit 0)                                       */
32638  #define R_CANFDL_CFDC_STS_CRSTSTS_Msk    (0x1UL)        /*!< CRSTSTS (Bitfield-Mask: 0x01)                         */
32639  #define R_CANFDL_CFDC_STS_CHLTSTS_Pos    (1UL)          /*!< CHLTSTS (Bit 1)                                       */
32640  #define R_CANFDL_CFDC_STS_CHLTSTS_Msk    (0x2UL)        /*!< CHLTSTS (Bitfield-Mask: 0x01)                         */
32641  #define R_CANFDL_CFDC_STS_CSLPSTS_Pos    (2UL)          /*!< CSLPSTS (Bit 2)                                       */
32642  #define R_CANFDL_CFDC_STS_CSLPSTS_Msk    (0x4UL)        /*!< CSLPSTS (Bitfield-Mask: 0x01)                         */
32643  #define R_CANFDL_CFDC_STS_EPSTS_Pos      (3UL)          /*!< EPSTS (Bit 3)                                         */
32644  #define R_CANFDL_CFDC_STS_EPSTS_Msk      (0x8UL)        /*!< EPSTS (Bitfield-Mask: 0x01)                           */
32645  #define R_CANFDL_CFDC_STS_BOSTS_Pos      (4UL)          /*!< BOSTS (Bit 4)                                         */
32646  #define R_CANFDL_CFDC_STS_BOSTS_Msk      (0x10UL)       /*!< BOSTS (Bitfield-Mask: 0x01)                           */
32647  #define R_CANFDL_CFDC_STS_TRMSTS_Pos     (5UL)          /*!< TRMSTS (Bit 5)                                        */
32648  #define R_CANFDL_CFDC_STS_TRMSTS_Msk     (0x20UL)       /*!< TRMSTS (Bitfield-Mask: 0x01)                          */
32649  #define R_CANFDL_CFDC_STS_RECSTS_Pos     (6UL)          /*!< RECSTS (Bit 6)                                        */
32650  #define R_CANFDL_CFDC_STS_RECSTS_Msk     (0x40UL)       /*!< RECSTS (Bitfield-Mask: 0x01)                          */
32651  #define R_CANFDL_CFDC_STS_COMSTS_Pos     (7UL)          /*!< COMSTS (Bit 7)                                        */
32652  #define R_CANFDL_CFDC_STS_COMSTS_Msk     (0x80UL)       /*!< COMSTS (Bitfield-Mask: 0x01)                          */
32653  #define R_CANFDL_CFDC_STS_ESIF_Pos       (8UL)          /*!< ESIF (Bit 8)                                          */
32654  #define R_CANFDL_CFDC_STS_ESIF_Msk       (0x100UL)      /*!< ESIF (Bitfield-Mask: 0x01)                            */
32655  #define R_CANFDL_CFDC_STS_REC_Pos        (16UL)         /*!< REC (Bit 16)                                          */
32656  #define R_CANFDL_CFDC_STS_REC_Msk        (0xff0000UL)   /*!< REC (Bitfield-Mask: 0xff)                             */
32657  #define R_CANFDL_CFDC_STS_TEC_Pos        (24UL)         /*!< TEC (Bit 24)                                          */
32658  #define R_CANFDL_CFDC_STS_TEC_Msk        (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff)                             */
32659 /* =========================================================  ERFL  ========================================================== */
32660  #define R_CANFDL_CFDC_ERFL_BEF_Pos       (0UL)          /*!< BEF (Bit 0)                                           */
32661  #define R_CANFDL_CFDC_ERFL_BEF_Msk       (0x1UL)        /*!< BEF (Bitfield-Mask: 0x01)                             */
32662  #define R_CANFDL_CFDC_ERFL_EWF_Pos       (1UL)          /*!< EWF (Bit 1)                                           */
32663  #define R_CANFDL_CFDC_ERFL_EWF_Msk       (0x2UL)        /*!< EWF (Bitfield-Mask: 0x01)                             */
32664  #define R_CANFDL_CFDC_ERFL_EPF_Pos       (2UL)          /*!< EPF (Bit 2)                                           */
32665  #define R_CANFDL_CFDC_ERFL_EPF_Msk       (0x4UL)        /*!< EPF (Bitfield-Mask: 0x01)                             */
32666  #define R_CANFDL_CFDC_ERFL_BOEF_Pos      (3UL)          /*!< BOEF (Bit 3)                                          */
32667  #define R_CANFDL_CFDC_ERFL_BOEF_Msk      (0x8UL)        /*!< BOEF (Bitfield-Mask: 0x01)                            */
32668  #define R_CANFDL_CFDC_ERFL_BORF_Pos      (4UL)          /*!< BORF (Bit 4)                                          */
32669  #define R_CANFDL_CFDC_ERFL_BORF_Msk      (0x10UL)       /*!< BORF (Bitfield-Mask: 0x01)                            */
32670  #define R_CANFDL_CFDC_ERFL_OVLF_Pos      (5UL)          /*!< OVLF (Bit 5)                                          */
32671  #define R_CANFDL_CFDC_ERFL_OVLF_Msk      (0x20UL)       /*!< OVLF (Bitfield-Mask: 0x01)                            */
32672  #define R_CANFDL_CFDC_ERFL_BLF_Pos       (6UL)          /*!< BLF (Bit 6)                                           */
32673  #define R_CANFDL_CFDC_ERFL_BLF_Msk       (0x40UL)       /*!< BLF (Bitfield-Mask: 0x01)                             */
32674  #define R_CANFDL_CFDC_ERFL_ALF_Pos       (7UL)          /*!< ALF (Bit 7)                                           */
32675  #define R_CANFDL_CFDC_ERFL_ALF_Msk       (0x80UL)       /*!< ALF (Bitfield-Mask: 0x01)                             */
32676  #define R_CANFDL_CFDC_ERFL_SERR_Pos      (8UL)          /*!< SERR (Bit 8)                                          */
32677  #define R_CANFDL_CFDC_ERFL_SERR_Msk      (0x100UL)      /*!< SERR (Bitfield-Mask: 0x01)                            */
32678  #define R_CANFDL_CFDC_ERFL_FERR_Pos      (9UL)          /*!< FERR (Bit 9)                                          */
32679  #define R_CANFDL_CFDC_ERFL_FERR_Msk      (0x200UL)      /*!< FERR (Bitfield-Mask: 0x01)                            */
32680  #define R_CANFDL_CFDC_ERFL_AERR_Pos      (10UL)         /*!< AERR (Bit 10)                                         */
32681  #define R_CANFDL_CFDC_ERFL_AERR_Msk      (0x400UL)      /*!< AERR (Bitfield-Mask: 0x01)                            */
32682  #define R_CANFDL_CFDC_ERFL_CERR_Pos      (11UL)         /*!< CERR (Bit 11)                                         */
32683  #define R_CANFDL_CFDC_ERFL_CERR_Msk      (0x800UL)      /*!< CERR (Bitfield-Mask: 0x01)                            */
32684  #define R_CANFDL_CFDC_ERFL_B1ERR_Pos     (12UL)         /*!< B1ERR (Bit 12)                                        */
32685  #define R_CANFDL_CFDC_ERFL_B1ERR_Msk     (0x1000UL)     /*!< B1ERR (Bitfield-Mask: 0x01)                           */
32686  #define R_CANFDL_CFDC_ERFL_B0ERR_Pos     (13UL)         /*!< B0ERR (Bit 13)                                        */
32687  #define R_CANFDL_CFDC_ERFL_B0ERR_Msk     (0x2000UL)     /*!< B0ERR (Bitfield-Mask: 0x01)                           */
32688  #define R_CANFDL_CFDC_ERFL_ADERR_Pos     (14UL)         /*!< ADERR (Bit 14)                                        */
32689  #define R_CANFDL_CFDC_ERFL_ADERR_Msk     (0x4000UL)     /*!< ADERR (Bitfield-Mask: 0x01)                           */
32690  #define R_CANFDL_CFDC_ERFL_CRCREG_Pos    (16UL)         /*!< CRCREG (Bit 16)                                       */
32691  #define R_CANFDL_CFDC_ERFL_CRCREG_Msk    (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff)                        */
32692 
32693 /* =========================================================================================================================== */
32694 /* ================                                           CFDC2                                           ================ */
32695 /* =========================================================================================================================== */
32696 
32697 /* =========================================================  DCFG  ========================================================== */
32698  #define R_CANFDL_CFDC2_DCFG_DBRP_Pos       (0UL)          /*!< DBRP (Bit 0)                                          */
32699  #define R_CANFDL_CFDC2_DCFG_DBRP_Msk       (0xffUL)       /*!< DBRP (Bitfield-Mask: 0xff)                            */
32700  #define R_CANFDL_CFDC2_DCFG_DTSEG1_Pos     (8UL)          /*!< DTSEG1 (Bit 8)                                        */
32701  #define R_CANFDL_CFDC2_DCFG_DTSEG1_Msk     (0x1f00UL)     /*!< DTSEG1 (Bitfield-Mask: 0x1f)                          */
32702  #define R_CANFDL_CFDC2_DCFG_DTSEG2_Pos     (16UL)         /*!< DTSEG2 (Bit 16)                                       */
32703  #define R_CANFDL_CFDC2_DCFG_DTSEG2_Msk     (0xf0000UL)    /*!< DTSEG2 (Bitfield-Mask: 0x0f)                          */
32704  #define R_CANFDL_CFDC2_DCFG_DSJW_Pos       (24UL)         /*!< DSJW (Bit 24)                                         */
32705  #define R_CANFDL_CFDC2_DCFG_DSJW_Msk       (0xf000000UL)  /*!< DSJW (Bitfield-Mask: 0x0f)                            */
32706 /* =========================================================  FDCFG  ========================================================= */
32707  #define R_CANFDL_CFDC2_FDCFG_EOCCFG_Pos    (0UL)          /*!< EOCCFG (Bit 0)                                        */
32708  #define R_CANFDL_CFDC2_FDCFG_EOCCFG_Msk    (0x7UL)        /*!< EOCCFG (Bitfield-Mask: 0x07)                          */
32709  #define R_CANFDL_CFDC2_FDCFG_TDCOC_Pos     (8UL)          /*!< TDCOC (Bit 8)                                         */
32710  #define R_CANFDL_CFDC2_FDCFG_TDCOC_Msk     (0x100UL)      /*!< TDCOC (Bitfield-Mask: 0x01)                           */
32711  #define R_CANFDL_CFDC2_FDCFG_TDCE_Pos      (9UL)          /*!< TDCE (Bit 9)                                          */
32712  #define R_CANFDL_CFDC2_FDCFG_TDCE_Msk      (0x200UL)      /*!< TDCE (Bitfield-Mask: 0x01)                            */
32713  #define R_CANFDL_CFDC2_FDCFG_ESIC_Pos      (10UL)         /*!< ESIC (Bit 10)                                         */
32714  #define R_CANFDL_CFDC2_FDCFG_ESIC_Msk      (0x400UL)      /*!< ESIC (Bitfield-Mask: 0x01)                            */
32715  #define R_CANFDL_CFDC2_FDCFG_TDCO_Pos      (16UL)         /*!< TDCO (Bit 16)                                         */
32716  #define R_CANFDL_CFDC2_FDCFG_TDCO_Msk      (0xff0000UL)   /*!< TDCO (Bitfield-Mask: 0xff)                            */
32717  #define R_CANFDL_CFDC2_FDCFG_FDOE_Pos      (28UL)         /*!< FDOE (Bit 28)                                         */
32718  #define R_CANFDL_CFDC2_FDCFG_FDOE_Msk      (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01)                            */
32719  #define R_CANFDL_CFDC2_FDCFG_REFE_Pos      (29UL)         /*!< REFE (Bit 29)                                         */
32720  #define R_CANFDL_CFDC2_FDCFG_REFE_Msk      (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01)                            */
32721  #define R_CANFDL_CFDC2_FDCFG_CLOE_Pos      (30UL)         /*!< CLOE (Bit 30)                                         */
32722  #define R_CANFDL_CFDC2_FDCFG_CLOE_Msk      (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01)                            */
32723 /* =========================================================  FDCTR  ========================================================= */
32724  #define R_CANFDL_CFDC2_FDCTR_EOCCLR_Pos    (0UL)          /*!< EOCCLR (Bit 0)                                        */
32725  #define R_CANFDL_CFDC2_FDCTR_EOCCLR_Msk    (0x1UL)        /*!< EOCCLR (Bitfield-Mask: 0x01)                          */
32726  #define R_CANFDL_CFDC2_FDCTR_SOCCLR_Pos    (1UL)          /*!< SOCCLR (Bit 1)                                        */
32727  #define R_CANFDL_CFDC2_FDCTR_SOCCLR_Msk    (0x2UL)        /*!< SOCCLR (Bitfield-Mask: 0x01)                          */
32728 /* =========================================================  FDSTS  ========================================================= */
32729  #define R_CANFDL_CFDC2_FDSTS_TDCR_Pos      (0UL)          /*!< TDCR (Bit 0)                                          */
32730  #define R_CANFDL_CFDC2_FDSTS_TDCR_Msk      (0xffUL)       /*!< TDCR (Bitfield-Mask: 0xff)                            */
32731  #define R_CANFDL_CFDC2_FDSTS_EOCO_Pos      (8UL)          /*!< EOCO (Bit 8)                                          */
32732  #define R_CANFDL_CFDC2_FDSTS_EOCO_Msk      (0x100UL)      /*!< EOCO (Bitfield-Mask: 0x01)                            */
32733  #define R_CANFDL_CFDC2_FDSTS_SOCO_Pos      (9UL)          /*!< SOCO (Bit 9)                                          */
32734  #define R_CANFDL_CFDC2_FDSTS_SOCO_Msk      (0x200UL)      /*!< SOCO (Bitfield-Mask: 0x01)                            */
32735  #define R_CANFDL_CFDC2_FDSTS_TDCVF_Pos     (15UL)         /*!< TDCVF (Bit 15)                                        */
32736  #define R_CANFDL_CFDC2_FDSTS_TDCVF_Msk     (0x8000UL)     /*!< TDCVF (Bitfield-Mask: 0x01)                           */
32737  #define R_CANFDL_CFDC2_FDSTS_EOC_Pos       (16UL)         /*!< EOC (Bit 16)                                          */
32738  #define R_CANFDL_CFDC2_FDSTS_EOC_Msk       (0xff0000UL)   /*!< EOC (Bitfield-Mask: 0xff)                             */
32739  #define R_CANFDL_CFDC2_FDSTS_SOC_Pos       (24UL)         /*!< SOC (Bit 24)                                          */
32740  #define R_CANFDL_CFDC2_FDSTS_SOC_Msk       (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff)                             */
32741 /* =========================================================  FDCRC  ========================================================= */
32742  #define R_CANFDL_CFDC2_FDCRC_CRCREG_Pos    (0UL)          /*!< CRCREG (Bit 0)                                        */
32743  #define R_CANFDL_CFDC2_FDCRC_CRCREG_Msk    (0x1fffffUL)   /*!< CRCREG (Bitfield-Mask: 0x1fffff)                      */
32744  #define R_CANFDL_CFDC2_FDCRC_SCNT_Pos      (24UL)         /*!< SCNT (Bit 24)                                         */
32745  #define R_CANFDL_CFDC2_FDCRC_SCNT_Msk      (0xf000000UL)  /*!< SCNT (Bitfield-Mask: 0x0f)                            */
32746 
32747 /* =========================================================================================================================== */
32748 /* ================                                          CFDGAFL                                          ================ */
32749 /* =========================================================================================================================== */
32750 
32751 /* ==========================================================  ID  =========================================================== */
32752  #define R_CANFDL_CFDGAFL_ID_GAFLID_Pos      (0UL)          /*!< GAFLID (Bit 0)                                        */
32753  #define R_CANFDL_CFDGAFL_ID_GAFLID_Msk      (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff)                    */
32754  #define R_CANFDL_CFDGAFL_ID_GAFLLB_Pos      (29UL)         /*!< GAFLLB (Bit 29)                                       */
32755  #define R_CANFDL_CFDGAFL_ID_GAFLLB_Msk      (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01)                          */
32756  #define R_CANFDL_CFDGAFL_ID_GAFLRTR_Pos     (30UL)         /*!< GAFLRTR (Bit 30)                                      */
32757  #define R_CANFDL_CFDGAFL_ID_GAFLRTR_Msk     (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01)                         */
32758  #define R_CANFDL_CFDGAFL_ID_GAFLIDE_Pos     (31UL)         /*!< GAFLIDE (Bit 31)                                      */
32759  #define R_CANFDL_CFDGAFL_ID_GAFLIDE_Msk     (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01)                         */
32760 /* ===========================================================  M  =========================================================== */
32761  #define R_CANFDL_CFDGAFL_M_GAFLIDM_Pos      (0UL)          /*!< GAFLIDM (Bit 0)                                       */
32762  #define R_CANFDL_CFDGAFL_M_GAFLIDM_Msk      (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff)                   */
32763  #define R_CANFDL_CFDGAFL_M_GAFLIFL1_Pos     (29UL)         /*!< GAFLIFL1 (Bit 29)                                     */
32764  #define R_CANFDL_CFDGAFL_M_GAFLIFL1_Msk     (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01)                        */
32765  #define R_CANFDL_CFDGAFL_M_GAFLRTRM_Pos     (30UL)         /*!< GAFLRTRM (Bit 30)                                     */
32766  #define R_CANFDL_CFDGAFL_M_GAFLRTRM_Msk     (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01)                        */
32767  #define R_CANFDL_CFDGAFL_M_GAFLIDEM_Pos     (31UL)         /*!< GAFLIDEM (Bit 31)                                     */
32768  #define R_CANFDL_CFDGAFL_M_GAFLIDEM_Msk     (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01)                        */
32769 /* ==========================================================  P0  =========================================================== */
32770  #define R_CANFDL_CFDGAFL_P0_GAFLDLC_Pos     (0UL)          /*!< GAFLDLC (Bit 0)                                       */
32771  #define R_CANFDL_CFDGAFL_P0_GAFLDLC_Msk     (0xfUL)        /*!< GAFLDLC (Bitfield-Mask: 0x0f)                         */
32772  #define R_CANFDL_CFDGAFL_P0_GAFLIFL0_Pos    (7UL)          /*!< GAFLIFL0 (Bit 7)                                      */
32773  #define R_CANFDL_CFDGAFL_P0_GAFLIFL0_Msk    (0x80UL)       /*!< GAFLIFL0 (Bitfield-Mask: 0x01)                        */
32774  #define R_CANFDL_CFDGAFL_P0_GAFLRMDP_Pos    (8UL)          /*!< GAFLRMDP (Bit 8)                                      */
32775  #define R_CANFDL_CFDGAFL_P0_GAFLRMDP_Msk    (0x1f00UL)     /*!< GAFLRMDP (Bitfield-Mask: 0x1f)                        */
32776  #define R_CANFDL_CFDGAFL_P0_GAFLRMV_Pos     (15UL)         /*!< GAFLRMV (Bit 15)                                      */
32777  #define R_CANFDL_CFDGAFL_P0_GAFLRMV_Msk     (0x8000UL)     /*!< GAFLRMV (Bitfield-Mask: 0x01)                         */
32778  #define R_CANFDL_CFDGAFL_P0_GAFLPTR_Pos     (16UL)         /*!< GAFLPTR (Bit 16)                                      */
32779  #define R_CANFDL_CFDGAFL_P0_GAFLPTR_Msk     (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff)                       */
32780 /* ==========================================================  P1  =========================================================== */
32781  #define R_CANFDL_CFDGAFL_P1_GAFLFDP_Pos     (0UL)          /*!< GAFLFDP (Bit 0)                                       */
32782  #define R_CANFDL_CFDGAFL_P1_GAFLFDP_Msk     (0x1ffUL)      /*!< GAFLFDP (Bitfield-Mask: 0x1ff)                        */
32783 
32784 /* =========================================================================================================================== */
32785 /* ================                                          CFDTHL                                           ================ */
32786 /* =========================================================================================================================== */
32787 
32788 /* =========================================================  ACC0  ========================================================== */
32789  #define R_CANFDL_CFDTHL_ACC0_BT_Pos      (0UL)          /*!< BT (Bit 0)                                            */
32790  #define R_CANFDL_CFDTHL_ACC0_BT_Msk      (0x7UL)        /*!< BT (Bitfield-Mask: 0x07)                              */
32791  #define R_CANFDL_CFDTHL_ACC0_BN_Pos      (3UL)          /*!< BN (Bit 3)                                            */
32792  #define R_CANFDL_CFDTHL_ACC0_BN_Msk      (0x3f8UL)      /*!< BN (Bitfield-Mask: 0x7f)                              */
32793  #define R_CANFDL_CFDTHL_ACC0_TMTS_Pos    (16UL)         /*!< TMTS (Bit 16)                                         */
32794  #define R_CANFDL_CFDTHL_ACC0_TMTS_Msk    (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff)                          */
32795 /* =========================================================  ACC1  ========================================================== */
32796  #define R_CANFDL_CFDTHL_ACC1_TID_Pos     (0UL)          /*!< TID (Bit 0)                                           */
32797  #define R_CANFDL_CFDTHL_ACC1_TID_Msk     (0xffffUL)     /*!< TID (Bitfield-Mask: 0xffff)                           */
32798  #define R_CANFDL_CFDTHL_ACC1_TIFL_Pos    (16UL)         /*!< TIFL (Bit 16)                                         */
32799  #define R_CANFDL_CFDTHL_ACC1_TIFL_Msk    (0x30000UL)    /*!< TIFL (Bitfield-Mask: 0x03)                            */
32800 
32801 /* =========================================================================================================================== */
32802 /* ================                                           CFDRF                                           ================ */
32803 /* =========================================================================================================================== */
32804 
32805 /* ==========================================================  ID  =========================================================== */
32806  #define R_CANFDL_CFDRF_ID_RFID_Pos        (0UL)          /*!< RFID (Bit 0)                                          */
32807  #define R_CANFDL_CFDRF_ID_RFID_Msk        (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff)                      */
32808  #define R_CANFDL_CFDRF_ID_RFRTR_Pos       (30UL)         /*!< RFRTR (Bit 30)                                        */
32809  #define R_CANFDL_CFDRF_ID_RFRTR_Msk       (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01)                           */
32810  #define R_CANFDL_CFDRF_ID_RFIDE_Pos       (31UL)         /*!< RFIDE (Bit 31)                                        */
32811  #define R_CANFDL_CFDRF_ID_RFIDE_Msk       (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01)                           */
32812 /* ==========================================================  PTR  ========================================================== */
32813  #define R_CANFDL_CFDRF_PTR_RFTS_Pos       (0UL)          /*!< RFTS (Bit 0)                                          */
32814  #define R_CANFDL_CFDRF_PTR_RFTS_Msk       (0xffffUL)     /*!< RFTS (Bitfield-Mask: 0xffff)                          */
32815  #define R_CANFDL_CFDRF_PTR_RFDLC_Pos      (28UL)         /*!< RFDLC (Bit 28)                                        */
32816  #define R_CANFDL_CFDRF_PTR_RFDLC_Msk      (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f)                           */
32817 /* =========================================================  FDSTS  ========================================================= */
32818  #define R_CANFDL_CFDRF_FDSTS_RFESI_Pos    (0UL)          /*!< RFESI (Bit 0)                                         */
32819  #define R_CANFDL_CFDRF_FDSTS_RFESI_Msk    (0x1UL)        /*!< RFESI (Bitfield-Mask: 0x01)                           */
32820  #define R_CANFDL_CFDRF_FDSTS_RFBRS_Pos    (1UL)          /*!< RFBRS (Bit 1)                                         */
32821  #define R_CANFDL_CFDRF_FDSTS_RFBRS_Msk    (0x2UL)        /*!< RFBRS (Bitfield-Mask: 0x01)                           */
32822  #define R_CANFDL_CFDRF_FDSTS_RFFDF_Pos    (2UL)          /*!< RFFDF (Bit 2)                                         */
32823  #define R_CANFDL_CFDRF_FDSTS_RFFDF_Msk    (0x4UL)        /*!< RFFDF (Bitfield-Mask: 0x01)                           */
32824  #define R_CANFDL_CFDRF_FDSTS_RFIFL_Pos    (8UL)          /*!< RFIFL (Bit 8)                                         */
32825  #define R_CANFDL_CFDRF_FDSTS_RFIFL_Msk    (0x300UL)      /*!< RFIFL (Bitfield-Mask: 0x03)                           */
32826  #define R_CANFDL_CFDRF_FDSTS_RFPTR_Pos    (16UL)         /*!< RFPTR (Bit 16)                                        */
32827  #define R_CANFDL_CFDRF_FDSTS_RFPTR_Msk    (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff)                         */
32828 /* ==========================================================  DF  =========================================================== */
32829  #define R_CANFDL_CFDRF_DF_RFDB_Pos        (0UL)          /*!< RFDB (Bit 0)                                          */
32830  #define R_CANFDL_CFDRF_DF_RFDB_Msk        (0xffUL)       /*!< RFDB (Bitfield-Mask: 0xff)                            */
32831 
32832 /* =========================================================================================================================== */
32833 /* ================                                           CFDCF                                           ================ */
32834 /* =========================================================================================================================== */
32835 
32836 /* ==========================================================  ID  =========================================================== */
32837  #define R_CANFDL_CFDCF_ID_CFID_Pos        (0UL)          /*!< CFID (Bit 0)                                          */
32838  #define R_CANFDL_CFDCF_ID_CFID_Msk        (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff)                      */
32839  #define R_CANFDL_CFDCF_ID_CFRTR_Pos       (30UL)         /*!< CFRTR (Bit 30)                                        */
32840  #define R_CANFDL_CFDCF_ID_CFRTR_Msk       (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01)                           */
32841  #define R_CANFDL_CFDCF_ID_CFIDE_Pos       (31UL)         /*!< CFIDE (Bit 31)                                        */
32842  #define R_CANFDL_CFDCF_ID_CFIDE_Msk       (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01)                           */
32843 /* ==========================================================  PTR  ========================================================== */
32844  #define R_CANFDL_CFDCF_PTR_CFTS_Pos       (0UL)          /*!< CFTS (Bit 0)                                          */
32845  #define R_CANFDL_CFDCF_PTR_CFTS_Msk       (0xffffUL)     /*!< CFTS (Bitfield-Mask: 0xffff)                          */
32846  #define R_CANFDL_CFDCF_PTR_CFDLC_Pos      (28UL)         /*!< CFDLC (Bit 28)                                        */
32847  #define R_CANFDL_CFDCF_PTR_CFDLC_Msk      (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f)                           */
32848 /* =========================================================  FDSTS  ========================================================= */
32849  #define R_CANFDL_CFDCF_FDSTS_CFESI_Pos    (0UL)          /*!< CFESI (Bit 0)                                         */
32850  #define R_CANFDL_CFDCF_FDSTS_CFESI_Msk    (0x1UL)        /*!< CFESI (Bitfield-Mask: 0x01)                           */
32851  #define R_CANFDL_CFDCF_FDSTS_CFBRS_Pos    (1UL)          /*!< CFBRS (Bit 1)                                         */
32852  #define R_CANFDL_CFDCF_FDSTS_CFBRS_Msk    (0x2UL)        /*!< CFBRS (Bitfield-Mask: 0x01)                           */
32853  #define R_CANFDL_CFDCF_FDSTS_CFFDF_Pos    (2UL)          /*!< CFFDF (Bit 2)                                         */
32854  #define R_CANFDL_CFDCF_FDSTS_CFFDF_Msk    (0x4UL)        /*!< CFFDF (Bitfield-Mask: 0x01)                           */
32855  #define R_CANFDL_CFDCF_FDSTS_CFIFL_Pos    (8UL)          /*!< CFIFL (Bit 8)                                         */
32856  #define R_CANFDL_CFDCF_FDSTS_CFIFL_Msk    (0x300UL)      /*!< CFIFL (Bitfield-Mask: 0x03)                           */
32857  #define R_CANFDL_CFDCF_FDSTS_CFPTR_Pos    (16UL)         /*!< CFPTR (Bit 16)                                        */
32858  #define R_CANFDL_CFDCF_FDSTS_CFPTR_Msk    (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff)                         */
32859 /* ==========================================================  DF  =========================================================== */
32860  #define R_CANFDL_CFDCF_DF_CFDB_Pos        (0UL)          /*!< CFDB (Bit 0)                                          */
32861  #define R_CANFDL_CFDCF_DF_CFDB_Msk        (0xffUL)       /*!< CFDB (Bitfield-Mask: 0xff)                            */
32862 
32863 /* =========================================================================================================================== */
32864 /* ================                                           CFDTM                                           ================ */
32865 /* =========================================================================================================================== */
32866 
32867 /* ==========================================================  ID  =========================================================== */
32868  #define R_CANFDL_CFDTM_ID_TMID_Pos        (0UL)          /*!< TMID (Bit 0)                                          */
32869  #define R_CANFDL_CFDTM_ID_TMID_Msk        (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff)                      */
32870  #define R_CANFDL_CFDTM_ID_TMRTR_Pos       (30UL)         /*!< TMRTR (Bit 30)                                        */
32871  #define R_CANFDL_CFDTM_ID_TMRTR_Msk       (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01)                           */
32872  #define R_CANFDL_CFDTM_ID_TMIDE_Pos       (31UL)         /*!< TMIDE (Bit 31)                                        */
32873  #define R_CANFDL_CFDTM_ID_TMIDE_Msk       (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01)                           */
32874 /* ==========================================================  PTR  ========================================================== */
32875  #define R_CANFDL_CFDTM_PTR_TMTS_Pos       (0UL)          /*!< TMTS (Bit 0)                                          */
32876  #define R_CANFDL_CFDTM_PTR_TMTS_Msk       (0xffffUL)     /*!< TMTS (Bitfield-Mask: 0xffff)                          */
32877  #define R_CANFDL_CFDTM_PTR_TMDLC_Pos      (28UL)         /*!< TMDLC (Bit 28)                                        */
32878  #define R_CANFDL_CFDTM_PTR_TMDLC_Msk      (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f)                           */
32879 /* =========================================================  FDCTR  ========================================================= */
32880  #define R_CANFDL_CFDTM_FDCTR_TMESI_Pos    (0UL)          /*!< TMESI (Bit 0)                                         */
32881  #define R_CANFDL_CFDTM_FDCTR_TMESI_Msk    (0x1UL)        /*!< TMESI (Bitfield-Mask: 0x01)                           */
32882  #define R_CANFDL_CFDTM_FDCTR_TMBRS_Pos    (1UL)          /*!< TMBRS (Bit 1)                                         */
32883  #define R_CANFDL_CFDTM_FDCTR_TMBRS_Msk    (0x2UL)        /*!< TMBRS (Bitfield-Mask: 0x01)                           */
32884  #define R_CANFDL_CFDTM_FDCTR_TMFDF_Pos    (2UL)          /*!< TMFDF (Bit 2)                                         */
32885  #define R_CANFDL_CFDTM_FDCTR_TMFDF_Msk    (0x4UL)        /*!< TMFDF (Bitfield-Mask: 0x01)                           */
32886  #define R_CANFDL_CFDTM_FDCTR_TMIFL_Pos    (8UL)          /*!< TMIFL (Bit 8)                                         */
32887  #define R_CANFDL_CFDTM_FDCTR_TMIFL_Msk    (0x300UL)      /*!< TMIFL (Bitfield-Mask: 0x03)                           */
32888  #define R_CANFDL_CFDTM_FDCTR_TMPTR_Pos    (16UL)         /*!< TMPTR (Bit 16)                                        */
32889  #define R_CANFDL_CFDTM_FDCTR_TMPTR_Msk    (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff)                         */
32890 /* ==========================================================  DF  =========================================================== */
32891  #define R_CANFDL_CFDTM_DF_TMDB_Pos        (0UL)          /*!< TMDB (Bit 0)                                          */
32892  #define R_CANFDL_CFDTM_DF_TMDB_Msk        (0xffUL)       /*!< TMDB (Bitfield-Mask: 0xff)                            */
32893 
32894 /* =========================================================================================================================== */
32895 /* ================                                            RM                                             ================ */
32896 /* =========================================================================================================================== */
32897 
32898 /* ==========================================================  ID  =========================================================== */
32899  #define R_CANFDL_CFDRMC_RM_ID_RMID_Pos        (0UL)          /*!< RMID (Bit 0)                                          */
32900  #define R_CANFDL_CFDRMC_RM_ID_RMID_Msk        (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff)                      */
32901  #define R_CANFDL_CFDRMC_RM_ID_RMRTR_Pos       (30UL)         /*!< RMRTR (Bit 30)                                        */
32902  #define R_CANFDL_CFDRMC_RM_ID_RMRTR_Msk       (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01)                           */
32903  #define R_CANFDL_CFDRMC_RM_ID_RMIDE_Pos       (31UL)         /*!< RMIDE (Bit 31)                                        */
32904  #define R_CANFDL_CFDRMC_RM_ID_RMIDE_Msk       (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01)                           */
32905 /* ==========================================================  PTR  ========================================================== */
32906  #define R_CANFDL_CFDRMC_RM_PTR_RMTS_Pos       (0UL)          /*!< RMTS (Bit 0)                                          */
32907  #define R_CANFDL_CFDRMC_RM_PTR_RMTS_Msk       (0xffffUL)     /*!< RMTS (Bitfield-Mask: 0xffff)                          */
32908  #define R_CANFDL_CFDRMC_RM_PTR_RMDLC_Pos      (28UL)         /*!< RMDLC (Bit 28)                                        */
32909  #define R_CANFDL_CFDRMC_RM_PTR_RMDLC_Msk      (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f)                           */
32910 /* =========================================================  FDSTS  ========================================================= */
32911  #define R_CANFDL_CFDRMC_RM_FDSTS_RMESI_Pos    (0UL)          /*!< RMESI (Bit 0)                                         */
32912  #define R_CANFDL_CFDRMC_RM_FDSTS_RMESI_Msk    (0x1UL)        /*!< RMESI (Bitfield-Mask: 0x01)                           */
32913  #define R_CANFDL_CFDRMC_RM_FDSTS_RMBRS_Pos    (1UL)          /*!< RMBRS (Bit 1)                                         */
32914  #define R_CANFDL_CFDRMC_RM_FDSTS_RMBRS_Msk    (0x2UL)        /*!< RMBRS (Bitfield-Mask: 0x01)                           */
32915  #define R_CANFDL_CFDRMC_RM_FDSTS_RMFDF_Pos    (2UL)          /*!< RMFDF (Bit 2)                                         */
32916  #define R_CANFDL_CFDRMC_RM_FDSTS_RMFDF_Msk    (0x4UL)        /*!< RMFDF (Bitfield-Mask: 0x01)                           */
32917  #define R_CANFDL_CFDRMC_RM_FDSTS_RMIFL_Pos    (8UL)          /*!< RMIFL (Bit 8)                                         */
32918  #define R_CANFDL_CFDRMC_RM_FDSTS_RMIFL_Msk    (0x300UL)      /*!< RMIFL (Bitfield-Mask: 0x03)                           */
32919  #define R_CANFDL_CFDRMC_RM_FDSTS_RMPTR_Pos    (16UL)         /*!< RMPTR (Bit 16)                                        */
32920  #define R_CANFDL_CFDRMC_RM_FDSTS_RMPTR_Msk    (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff)                         */
32921 /* ==========================================================  DF  =========================================================== */
32922  #define R_CANFDL_CFDRMC_RM_DF_RMDB_Pos        (0UL)          /*!< RMDB (Bit 0)                                          */
32923  #define R_CANFDL_CFDRMC_RM_DF_RMDB_Msk        (0xffUL)       /*!< RMDB (Bitfield-Mask: 0xff)                            */
32924 
32925 /* =========================================================================================================================== */
32926 /* ================                                          CFDRMC                                           ================ */
32927 /* =========================================================================================================================== */
32928 
32929 /* =========================================================================================================================== */
32930 /* ================                                          ELSEGR                                           ================ */
32931 /* =========================================================================================================================== */
32932 
32933 /* ==========================================================  BY  =========================================================== */
32934  #define R_ELC_ELSEGR_BY_WI_Pos     (7UL)    /*!< WI (Bit 7)                                            */
32935  #define R_ELC_ELSEGR_BY_WI_Msk     (0x80UL) /*!< WI (Bitfield-Mask: 0x01)                              */
32936  #define R_ELC_ELSEGR_BY_WE_Pos     (6UL)    /*!< WE (Bit 6)                                            */
32937  #define R_ELC_ELSEGR_BY_WE_Msk     (0x40UL) /*!< WE (Bitfield-Mask: 0x01)                              */
32938  #define R_ELC_ELSEGR_BY_SEG_Pos    (0UL)    /*!< SEG (Bit 0)                                           */
32939  #define R_ELC_ELSEGR_BY_SEG_Msk    (0x1UL)  /*!< SEG (Bitfield-Mask: 0x01)                             */
32940 
32941 /* =========================================================================================================================== */
32942 /* ================                                           ELSR                                            ================ */
32943 /* =========================================================================================================================== */
32944 
32945 /* ==========================================================  HA  =========================================================== */
32946  #define R_ELC_ELSR_HA_ELS_Pos    (0UL)     /*!< ELS (Bit 0)                                           */
32947  #define R_ELC_ELSR_HA_ELS_Msk    (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff)                            */
32948 
32949 /* =========================================================================================================================== */
32950 /* ================                                            TM                                             ================ */
32951 /* =========================================================================================================================== */
32952 
32953 /* =========================================================  STTRU  ========================================================= */
32954  #define R_ETHERC_EPTPC_COMMON_TM_STTRU_TMSTTRU_Pos    (0UL)          /*!< TMSTTRU (Bit 0)                                       */
32955  #define R_ETHERC_EPTPC_COMMON_TM_STTRU_TMSTTRU_Msk    (0xffffffffUL) /*!< TMSTTRU (Bitfield-Mask: 0xffffffff)                   */
32956 /* =========================================================  STTRL  ========================================================= */
32957  #define R_ETHERC_EPTPC_COMMON_TM_STTRL_TMSTTRL_Pos    (0UL)          /*!< TMSTTRL (Bit 0)                                       */
32958  #define R_ETHERC_EPTPC_COMMON_TM_STTRL_TMSTTRL_Msk    (0xffffffffUL) /*!< TMSTTRL (Bitfield-Mask: 0xffffffff)                   */
32959 /* =========================================================  CYCR  ========================================================== */
32960  #define R_ETHERC_EPTPC_COMMON_TM_CYCR_TMCYCR_Pos      (0UL)          /*!< TMCYCR (Bit 0)                                        */
32961  #define R_ETHERC_EPTPC_COMMON_TM_CYCR_TMCYCR_Msk      (0x3fffffffUL) /*!< TMCYCR (Bitfield-Mask: 0x3fffffff)                    */
32962 /* =========================================================  PLSR  ========================================================== */
32963  #define R_ETHERC_EPTPC_COMMON_TM_PLSR_TMPLSR_Pos      (0UL)          /*!< TMPLSR (Bit 0)                                        */
32964  #define R_ETHERC_EPTPC_COMMON_TM_PLSR_TMPLSR_Msk      (0x1fffffffUL) /*!< TMPLSR (Bitfield-Mask: 0x1fffffff)                    */
32965 
32966 /* =========================================================================================================================== */
32967 /* ================                                            PR                                             ================ */
32968 /* =========================================================================================================================== */
32969 
32970 /* =========================================================  MACRU  ========================================================= */
32971  #define R_ETHERC_EPTPC_COMMON_PR_MACRU_PRMACRU_Pos    (0UL)        /*!< PRMACRU (Bit 0)                                       */
32972  #define R_ETHERC_EPTPC_COMMON_PR_MACRU_PRMACRU_Msk    (0xffffffUL) /*!< PRMACRU (Bitfield-Mask: 0xffffff)                     */
32973 /* =========================================================  MACRL  ========================================================= */
32974  #define R_ETHERC_EPTPC_COMMON_PR_MACRL_PRMACRL_Pos    (0UL)        /*!< PRMACRL (Bit 0)                                       */
32975  #define R_ETHERC_EPTPC_COMMON_PR_MACRL_PRMACRL_Msk    (0xffffffUL) /*!< PRMACRL (Bitfield-Mask: 0xffffff)                     */
32976 
32977 /* =========================================================================================================================== */
32978 /* ================                                            BG                                             ================ */
32979 /* =========================================================================================================================== */
32980 
32981 /* ==========================================================  EN  =========================================================== */
32982  #define R_GLCDC_BG_EN_SWRST_Pos     (16UL)        /*!< SWRST (Bit 16)                                        */
32983  #define R_GLCDC_BG_EN_SWRST_Msk     (0x10000UL)   /*!< SWRST (Bitfield-Mask: 0x01)                           */
32984  #define R_GLCDC_BG_EN_VEN_Pos       (8UL)         /*!< VEN (Bit 8)                                           */
32985  #define R_GLCDC_BG_EN_VEN_Msk       (0x100UL)     /*!< VEN (Bitfield-Mask: 0x01)                             */
32986  #define R_GLCDC_BG_EN_EN_Pos        (0UL)         /*!< EN (Bit 0)                                            */
32987  #define R_GLCDC_BG_EN_EN_Msk        (0x1UL)       /*!< EN (Bitfield-Mask: 0x01)                              */
32988 /* =========================================================  PERI  ========================================================== */
32989  #define R_GLCDC_BG_PERI_FV_Pos      (16UL)        /*!< FV (Bit 16)                                           */
32990  #define R_GLCDC_BG_PERI_FV_Msk      (0x7ff0000UL) /*!< FV (Bitfield-Mask: 0x7ff)                             */
32991  #define R_GLCDC_BG_PERI_FH_Pos      (0UL)         /*!< FH (Bit 0)                                            */
32992  #define R_GLCDC_BG_PERI_FH_Msk      (0x7ffUL)     /*!< FH (Bitfield-Mask: 0x7ff)                             */
32993 /* =========================================================  SYNC  ========================================================== */
32994  #define R_GLCDC_BG_SYNC_VP_Pos      (16UL)        /*!< VP (Bit 16)                                           */
32995  #define R_GLCDC_BG_SYNC_VP_Msk      (0xf0000UL)   /*!< VP (Bitfield-Mask: 0x0f)                              */
32996  #define R_GLCDC_BG_SYNC_HP_Pos      (0UL)         /*!< HP (Bit 0)                                            */
32997  #define R_GLCDC_BG_SYNC_HP_Msk      (0xfUL)       /*!< HP (Bitfield-Mask: 0x0f)                              */
32998 /* =========================================================  VSIZE  ========================================================= */
32999  #define R_GLCDC_BG_VSIZE_VP_Pos     (16UL)        /*!< VP (Bit 16)                                           */
33000  #define R_GLCDC_BG_VSIZE_VP_Msk     (0x7ff0000UL) /*!< VP (Bitfield-Mask: 0x7ff)                             */
33001  #define R_GLCDC_BG_VSIZE_VW_Pos     (0UL)         /*!< VW (Bit 0)                                            */
33002  #define R_GLCDC_BG_VSIZE_VW_Msk     (0x7ffUL)     /*!< VW (Bitfield-Mask: 0x7ff)                             */
33003 /* =========================================================  HSIZE  ========================================================= */
33004  #define R_GLCDC_BG_HSIZE_HP_Pos     (16UL)        /*!< HP (Bit 16)                                           */
33005  #define R_GLCDC_BG_HSIZE_HP_Msk     (0x7ff0000UL) /*!< HP (Bitfield-Mask: 0x7ff)                             */
33006  #define R_GLCDC_BG_HSIZE_HW_Pos     (0UL)         /*!< HW (Bit 0)                                            */
33007  #define R_GLCDC_BG_HSIZE_HW_Msk     (0x7ffUL)     /*!< HW (Bitfield-Mask: 0x7ff)                             */
33008 /* ==========================================================  BGC  ========================================================== */
33009  #define R_GLCDC_BG_BGC_R_Pos        (16UL)        /*!< R (Bit 16)                                            */
33010  #define R_GLCDC_BG_BGC_R_Msk        (0xff0000UL)  /*!< R (Bitfield-Mask: 0xff)                               */
33011  #define R_GLCDC_BG_BGC_G_Pos        (8UL)         /*!< G (Bit 8)                                             */
33012  #define R_GLCDC_BG_BGC_G_Msk        (0xff00UL)    /*!< G (Bitfield-Mask: 0xff)                               */
33013  #define R_GLCDC_BG_BGC_B_Pos        (0UL)         /*!< B (Bit 0)                                             */
33014  #define R_GLCDC_BG_BGC_B_Msk        (0xffUL)      /*!< B (Bitfield-Mask: 0xff)                               */
33015 /* ==========================================================  MON  ========================================================== */
33016  #define R_GLCDC_BG_MON_SWRST_Pos    (16UL)        /*!< SWRST (Bit 16)                                        */
33017  #define R_GLCDC_BG_MON_SWRST_Msk    (0x10000UL)   /*!< SWRST (Bitfield-Mask: 0x01)                           */
33018  #define R_GLCDC_BG_MON_VEN_Pos      (8UL)         /*!< VEN (Bit 8)                                           */
33019  #define R_GLCDC_BG_MON_VEN_Msk      (0x100UL)     /*!< VEN (Bitfield-Mask: 0x01)                             */
33020  #define R_GLCDC_BG_MON_EN_Pos       (0UL)         /*!< EN (Bit 0)                                            */
33021  #define R_GLCDC_BG_MON_EN_Msk       (0x1UL)       /*!< EN (Bitfield-Mask: 0x01)                              */
33022 
33023 /* =========================================================================================================================== */
33024 /* ================                                            GR                                             ================ */
33025 /* =========================================================================================================================== */
33026 
33027 /* ==========================================================  VEN  ========================================================== */
33028  #define R_GLCDC_GR_VEN_PVEN_Pos         (0UL)          /*!< PVEN (Bit 0)                                          */
33029  #define R_GLCDC_GR_VEN_PVEN_Msk         (0x1UL)        /*!< PVEN (Bitfield-Mask: 0x01)                            */
33030 /* =========================================================  FLMRD  ========================================================= */
33031  #define R_GLCDC_GR_FLMRD_RENB_Pos       (0UL)          /*!< RENB (Bit 0)                                          */
33032  #define R_GLCDC_GR_FLMRD_RENB_Msk       (0x1UL)        /*!< RENB (Bitfield-Mask: 0x01)                            */
33033 /* =========================================================  FLM1  ========================================================== */
33034  #define R_GLCDC_GR_FLM1_BSTMD_Pos       (0UL)          /*!< BSTMD (Bit 0)                                         */
33035  #define R_GLCDC_GR_FLM1_BSTMD_Msk       (0x3UL)        /*!< BSTMD (Bitfield-Mask: 0x03)                           */
33036 /* =========================================================  FLM2  ========================================================== */
33037  #define R_GLCDC_GR_FLM2_BASE_Pos        (0UL)          /*!< BASE (Bit 0)                                          */
33038  #define R_GLCDC_GR_FLM2_BASE_Msk        (0xffffffffUL) /*!< BASE (Bitfield-Mask: 0xffffffff)                      */
33039 /* =========================================================  FLM3  ========================================================== */
33040  #define R_GLCDC_GR_FLM3_LNOFF_Pos       (16UL)         /*!< LNOFF (Bit 16)                                        */
33041  #define R_GLCDC_GR_FLM3_LNOFF_Msk       (0xffff0000UL) /*!< LNOFF (Bitfield-Mask: 0xffff)                         */
33042 /* =========================================================  FLM5  ========================================================== */
33043  #define R_GLCDC_GR_FLM5_LNNUM_Pos       (16UL)         /*!< LNNUM (Bit 16)                                        */
33044  #define R_GLCDC_GR_FLM5_LNNUM_Msk       (0x7ff0000UL)  /*!< LNNUM (Bitfield-Mask: 0x7ff)                          */
33045  #define R_GLCDC_GR_FLM5_DATANUM_Pos     (0UL)          /*!< DATANUM (Bit 0)                                       */
33046  #define R_GLCDC_GR_FLM5_DATANUM_Msk     (0xffffUL)     /*!< DATANUM (Bitfield-Mask: 0xffff)                       */
33047 /* =========================================================  FLM6  ========================================================== */
33048  #define R_GLCDC_GR_FLM6_FORMAT_Pos      (28UL)         /*!< FORMAT (Bit 28)                                       */
33049  #define R_GLCDC_GR_FLM6_FORMAT_Msk      (0x70000000UL) /*!< FORMAT (Bitfield-Mask: 0x07)                          */
33050 /* ==========================================================  AB1  ========================================================== */
33051  #define R_GLCDC_GR_AB1_ARCON_Pos        (12UL)         /*!< ARCON (Bit 12)                                        */
33052  #define R_GLCDC_GR_AB1_ARCON_Msk        (0x1000UL)     /*!< ARCON (Bitfield-Mask: 0x01)                           */
33053  #define R_GLCDC_GR_AB1_ARCDISPON_Pos    (8UL)          /*!< ARCDISPON (Bit 8)                                     */
33054  #define R_GLCDC_GR_AB1_ARCDISPON_Msk    (0x100UL)      /*!< ARCDISPON (Bitfield-Mask: 0x01)                       */
33055  #define R_GLCDC_GR_AB1_GRCDISPON_Pos    (4UL)          /*!< GRCDISPON (Bit 4)                                     */
33056  #define R_GLCDC_GR_AB1_GRCDISPON_Msk    (0x10UL)       /*!< GRCDISPON (Bitfield-Mask: 0x01)                       */
33057  #define R_GLCDC_GR_AB1_DISPSEL_Pos      (0UL)          /*!< DISPSEL (Bit 0)                                       */
33058  #define R_GLCDC_GR_AB1_DISPSEL_Msk      (0x3UL)        /*!< DISPSEL (Bitfield-Mask: 0x03)                         */
33059 /* ==========================================================  AB2  ========================================================== */
33060  #define R_GLCDC_GR_AB2_GRCVS_Pos        (16UL)         /*!< GRCVS (Bit 16)                                        */
33061  #define R_GLCDC_GR_AB2_GRCVS_Msk        (0x7ff0000UL)  /*!< GRCVS (Bitfield-Mask: 0x7ff)                          */
33062  #define R_GLCDC_GR_AB2_GRCVW_Pos        (0UL)          /*!< GRCVW (Bit 0)                                         */
33063  #define R_GLCDC_GR_AB2_GRCVW_Msk        (0x7ffUL)      /*!< GRCVW (Bitfield-Mask: 0x7ff)                          */
33064 /* ==========================================================  AB3  ========================================================== */
33065  #define R_GLCDC_GR_AB3_GRCHS_Pos        (16UL)         /*!< GRCHS (Bit 16)                                        */
33066  #define R_GLCDC_GR_AB3_GRCHS_Msk        (0x7ff0000UL)  /*!< GRCHS (Bitfield-Mask: 0x7ff)                          */
33067  #define R_GLCDC_GR_AB3_GRCHW_Pos        (0UL)          /*!< GRCHW (Bit 0)                                         */
33068  #define R_GLCDC_GR_AB3_GRCHW_Msk        (0x7ffUL)      /*!< GRCHW (Bitfield-Mask: 0x7ff)                          */
33069 /* ==========================================================  AB4  ========================================================== */
33070  #define R_GLCDC_GR_AB4_ARCVS_Pos        (16UL)         /*!< ARCVS (Bit 16)                                        */
33071  #define R_GLCDC_GR_AB4_ARCVS_Msk        (0x7ff0000UL)  /*!< ARCVS (Bitfield-Mask: 0x7ff)                          */
33072  #define R_GLCDC_GR_AB4_ARCVW_Pos        (0UL)          /*!< ARCVW (Bit 0)                                         */
33073  #define R_GLCDC_GR_AB4_ARCVW_Msk        (0x7ffUL)      /*!< ARCVW (Bitfield-Mask: 0x7ff)                          */
33074 /* ==========================================================  AB5  ========================================================== */
33075  #define R_GLCDC_GR_AB5_ARCHS_Pos        (16UL)         /*!< ARCHS (Bit 16)                                        */
33076  #define R_GLCDC_GR_AB5_ARCHS_Msk        (0x7ff0000UL)  /*!< ARCHS (Bitfield-Mask: 0x7ff)                          */
33077  #define R_GLCDC_GR_AB5_ARCHW_Pos        (0UL)          /*!< ARCHW (Bit 0)                                         */
33078  #define R_GLCDC_GR_AB5_ARCHW_Msk        (0x7ffUL)      /*!< ARCHW (Bitfield-Mask: 0x7ff)                          */
33079 /* ==========================================================  AB6  ========================================================== */
33080  #define R_GLCDC_GR_AB6_ARCCOEF_Pos      (16UL)         /*!< ARCCOEF (Bit 16)                                      */
33081  #define R_GLCDC_GR_AB6_ARCCOEF_Msk      (0x1ff0000UL)  /*!< ARCCOEF (Bitfield-Mask: 0x1ff)                        */
33082  #define R_GLCDC_GR_AB6_ARCRATE_Pos      (0UL)          /*!< ARCRATE (Bit 0)                                       */
33083  #define R_GLCDC_GR_AB6_ARCRATE_Msk      (0xffUL)       /*!< ARCRATE (Bitfield-Mask: 0xff)                         */
33084 /* ==========================================================  AB7  ========================================================== */
33085  #define R_GLCDC_GR_AB7_ARCDEF_Pos       (16UL)         /*!< ARCDEF (Bit 16)                                       */
33086  #define R_GLCDC_GR_AB7_ARCDEF_Msk       (0xff0000UL)   /*!< ARCDEF (Bitfield-Mask: 0xff)                          */
33087  #define R_GLCDC_GR_AB7_CKON_Pos         (0UL)          /*!< CKON (Bit 0)                                          */
33088  #define R_GLCDC_GR_AB7_CKON_Msk         (0x1UL)        /*!< CKON (Bitfield-Mask: 0x01)                            */
33089 /* ==========================================================  AB8  ========================================================== */
33090  #define R_GLCDC_GR_AB8_CKKG_Pos         (16UL)         /*!< CKKG (Bit 16)                                         */
33091  #define R_GLCDC_GR_AB8_CKKG_Msk         (0xff0000UL)   /*!< CKKG (Bitfield-Mask: 0xff)                            */
33092  #define R_GLCDC_GR_AB8_CKKB_Pos         (8UL)          /*!< CKKB (Bit 8)                                          */
33093  #define R_GLCDC_GR_AB8_CKKB_Msk         (0xff00UL)     /*!< CKKB (Bitfield-Mask: 0xff)                            */
33094  #define R_GLCDC_GR_AB8_CKKR_Pos         (0UL)          /*!< CKKR (Bit 0)                                          */
33095  #define R_GLCDC_GR_AB8_CKKR_Msk         (0xffUL)       /*!< CKKR (Bitfield-Mask: 0xff)                            */
33096 /* ==========================================================  AB9  ========================================================== */
33097  #define R_GLCDC_GR_AB9_CKA_Pos          (24UL)         /*!< CKA (Bit 24)                                          */
33098  #define R_GLCDC_GR_AB9_CKA_Msk          (0xff000000UL) /*!< CKA (Bitfield-Mask: 0xff)                             */
33099  #define R_GLCDC_GR_AB9_CKG_Pos          (16UL)         /*!< CKG (Bit 16)                                          */
33100  #define R_GLCDC_GR_AB9_CKG_Msk          (0xff0000UL)   /*!< CKG (Bitfield-Mask: 0xff)                             */
33101  #define R_GLCDC_GR_AB9_CKB_Pos          (8UL)          /*!< CKB (Bit 8)                                           */
33102  #define R_GLCDC_GR_AB9_CKB_Msk          (0xff00UL)     /*!< CKB (Bitfield-Mask: 0xff)                             */
33103  #define R_GLCDC_GR_AB9_CKR_Pos          (0UL)          /*!< CKR (Bit 0)                                           */
33104  #define R_GLCDC_GR_AB9_CKR_Msk          (0xffUL)       /*!< CKR (Bitfield-Mask: 0xff)                             */
33105 /* =========================================================  BASE  ========================================================== */
33106  #define R_GLCDC_GR_BASE_G_Pos           (16UL)         /*!< G (Bit 16)                                            */
33107  #define R_GLCDC_GR_BASE_G_Msk           (0xff0000UL)   /*!< G (Bitfield-Mask: 0xff)                               */
33108  #define R_GLCDC_GR_BASE_B_Pos           (8UL)          /*!< B (Bit 8)                                             */
33109  #define R_GLCDC_GR_BASE_B_Msk           (0xff00UL)     /*!< B (Bitfield-Mask: 0xff)                               */
33110  #define R_GLCDC_GR_BASE_R_Pos           (0UL)          /*!< R (Bit 0)                                             */
33111  #define R_GLCDC_GR_BASE_R_Msk           (0xffUL)       /*!< R (Bitfield-Mask: 0xff)                               */
33112 /* ========================================================  CLUTINT  ======================================================== */
33113  #define R_GLCDC_GR_CLUTINT_SEL_Pos      (16UL)         /*!< SEL (Bit 16)                                          */
33114  #define R_GLCDC_GR_CLUTINT_SEL_Msk      (0x10000UL)    /*!< SEL (Bitfield-Mask: 0x01)                             */
33115  #define R_GLCDC_GR_CLUTINT_LINE_Pos     (0UL)          /*!< LINE (Bit 0)                                          */
33116  #define R_GLCDC_GR_CLUTINT_LINE_Msk     (0x7ffUL)      /*!< LINE (Bitfield-Mask: 0x7ff)                           */
33117 /* ==========================================================  MON  ========================================================== */
33118  #define R_GLCDC_GR_MON_UNDFLST_Pos      (16UL)         /*!< UNDFLST (Bit 16)                                      */
33119  #define R_GLCDC_GR_MON_UNDFLST_Msk      (0x10000UL)    /*!< UNDFLST (Bitfield-Mask: 0x01)                         */
33120  #define R_GLCDC_GR_MON_ARCST_Pos        (0UL)          /*!< ARCST (Bit 0)                                         */
33121  #define R_GLCDC_GR_MON_ARCST_Msk        (0x1UL)        /*!< ARCST (Bitfield-Mask: 0x01)                           */
33122 
33123 /* =========================================================================================================================== */
33124 /* ================                                            GAM                                            ================ */
33125 /* =========================================================================================================================== */
33126 
33127 /* =========================================================  LATCH  ========================================================= */
33128  #define R_GLCDC_GAM_LATCH_VEN_Pos       (0UL)     /*!< VEN (Bit 0)                                           */
33129  #define R_GLCDC_GAM_LATCH_VEN_Msk       (0x1UL)   /*!< VEN (Bitfield-Mask: 0x01)                             */
33130 /* ========================================================  GAM_SW  ========================================================= */
33131  #define R_GLCDC_GAM_GAM_SW_GAMON_Pos    (0UL)     /*!< GAMON (Bit 0)                                         */
33132  #define R_GLCDC_GAM_GAM_SW_GAMON_Msk    (0x1UL)   /*!< GAMON (Bitfield-Mask: 0x01)                           */
33133 /* ==========================================================  LUT  ========================================================== */
33134  #define R_GLCDC_GAM_LUT___Pos           (0UL)     /*!< _ (Bit 0)                                             */
33135  #define R_GLCDC_GAM_LUT___Msk           (0x7ffUL) /*!< _ (Bitfield-Mask: 0x7ff)                              */
33136 /* =========================================================  AREA  ========================================================== */
33137  #define R_GLCDC_GAM_AREA___Pos          (0UL)     /*!< _ (Bit 0)                                             */
33138  #define R_GLCDC_GAM_AREA___Msk          (0x3ffUL) /*!< _ (Bitfield-Mask: 0x3ff)                              */
33139 
33140 /* =========================================================================================================================== */
33141 /* ================                                            OUT                                            ================ */
33142 /* =========================================================================================================================== */
33143 
33144 /* ========================================================  VLATCH  ========================================================= */
33145  #define R_GLCDC_OUT_VLATCH_VEN_Pos            (0UL)          /*!< VEN (Bit 0)                                           */
33146  #define R_GLCDC_OUT_VLATCH_VEN_Msk            (0x1UL)        /*!< VEN (Bitfield-Mask: 0x01)                             */
33147 /* ==========================================================  SET  ========================================================== */
33148  #define R_GLCDC_OUT_SET_ENDIANON_Pos          (28UL)         /*!< ENDIANON (Bit 28)                                     */
33149  #define R_GLCDC_OUT_SET_ENDIANON_Msk          (0x10000000UL) /*!< ENDIANON (Bitfield-Mask: 0x01)                        */
33150  #define R_GLCDC_OUT_SET_SWAPON_Pos            (24UL)         /*!< SWAPON (Bit 24)                                       */
33151  #define R_GLCDC_OUT_SET_SWAPON_Msk            (0x1000000UL)  /*!< SWAPON (Bitfield-Mask: 0x01)                          */
33152  #define R_GLCDC_OUT_SET_FORMAT_Pos            (12UL)         /*!< FORMAT (Bit 12)                                       */
33153  #define R_GLCDC_OUT_SET_FORMAT_Msk            (0x3000UL)     /*!< FORMAT (Bitfield-Mask: 0x03)                          */
33154  #define R_GLCDC_OUT_SET_FRQSEL_Pos            (8UL)          /*!< FRQSEL (Bit 8)                                        */
33155  #define R_GLCDC_OUT_SET_FRQSEL_Msk            (0x300UL)      /*!< FRQSEL (Bitfield-Mask: 0x03)                          */
33156  #define R_GLCDC_OUT_SET_DIRSEL_Pos            (4UL)          /*!< DIRSEL (Bit 4)                                        */
33157  #define R_GLCDC_OUT_SET_DIRSEL_Msk            (0x10UL)       /*!< DIRSEL (Bitfield-Mask: 0x01)                          */
33158  #define R_GLCDC_OUT_SET_PHASE_Pos             (0UL)          /*!< PHASE (Bit 0)                                         */
33159  #define R_GLCDC_OUT_SET_PHASE_Msk             (0x3UL)        /*!< PHASE (Bitfield-Mask: 0x03)                           */
33160 /* ========================================================  BRIGHT1  ======================================================== */
33161  #define R_GLCDC_OUT_BRIGHT1_BRTG_Pos          (0UL)          /*!< BRTG (Bit 0)                                          */
33162  #define R_GLCDC_OUT_BRIGHT1_BRTG_Msk          (0x3ffUL)      /*!< BRTG (Bitfield-Mask: 0x3ff)                           */
33163 /* ========================================================  BRIGHT2  ======================================================== */
33164  #define R_GLCDC_OUT_BRIGHT2_BRTB_Pos          (16UL)         /*!< BRTB (Bit 16)                                         */
33165  #define R_GLCDC_OUT_BRIGHT2_BRTB_Msk          (0x3ff0000UL)  /*!< BRTB (Bitfield-Mask: 0x3ff)                           */
33166  #define R_GLCDC_OUT_BRIGHT2_BRTR_Pos          (0UL)          /*!< BRTR (Bit 0)                                          */
33167  #define R_GLCDC_OUT_BRIGHT2_BRTR_Msk          (0x3ffUL)      /*!< BRTR (Bitfield-Mask: 0x3ff)                           */
33168 /* =======================================================  CONTRAST  ======================================================== */
33169  #define R_GLCDC_OUT_CONTRAST_CONTG_Pos        (16UL)         /*!< CONTG (Bit 16)                                        */
33170  #define R_GLCDC_OUT_CONTRAST_CONTG_Msk        (0xff0000UL)   /*!< CONTG (Bitfield-Mask: 0xff)                           */
33171  #define R_GLCDC_OUT_CONTRAST_CONTB_Pos        (8UL)          /*!< CONTB (Bit 8)                                         */
33172  #define R_GLCDC_OUT_CONTRAST_CONTB_Msk        (0xff00UL)     /*!< CONTB (Bitfield-Mask: 0xff)                           */
33173  #define R_GLCDC_OUT_CONTRAST_CONTR_Pos        (0UL)          /*!< CONTR (Bit 0)                                         */
33174  #define R_GLCDC_OUT_CONTRAST_CONTR_Msk        (0xffUL)       /*!< CONTR (Bitfield-Mask: 0xff)                           */
33175 /* =========================================================  PDTHA  ========================================================= */
33176  #define R_GLCDC_OUT_PDTHA_SEL_Pos             (20UL)         /*!< SEL (Bit 20)                                          */
33177  #define R_GLCDC_OUT_PDTHA_SEL_Msk             (0x300000UL)   /*!< SEL (Bitfield-Mask: 0x03)                             */
33178  #define R_GLCDC_OUT_PDTHA_FORM_Pos            (16UL)         /*!< FORM (Bit 16)                                         */
33179  #define R_GLCDC_OUT_PDTHA_FORM_Msk            (0x30000UL)    /*!< FORM (Bitfield-Mask: 0x03)                            */
33180  #define R_GLCDC_OUT_PDTHA_PA_Pos              (12UL)         /*!< PA (Bit 12)                                           */
33181  #define R_GLCDC_OUT_PDTHA_PA_Msk              (0x3000UL)     /*!< PA (Bitfield-Mask: 0x03)                              */
33182  #define R_GLCDC_OUT_PDTHA_PB_Pos              (8UL)          /*!< PB (Bit 8)                                            */
33183  #define R_GLCDC_OUT_PDTHA_PB_Msk              (0x300UL)      /*!< PB (Bitfield-Mask: 0x03)                              */
33184  #define R_GLCDC_OUT_PDTHA_PC_Pos              (4UL)          /*!< PC (Bit 4)                                            */
33185  #define R_GLCDC_OUT_PDTHA_PC_Msk              (0x30UL)       /*!< PC (Bitfield-Mask: 0x03)                              */
33186  #define R_GLCDC_OUT_PDTHA_PD_Pos              (0UL)          /*!< PD (Bit 0)                                            */
33187  #define R_GLCDC_OUT_PDTHA_PD_Msk              (0x3UL)        /*!< PD (Bitfield-Mask: 0x03)                              */
33188 /* =======================================================  CLKPHASE  ======================================================== */
33189  #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Pos     (12UL)         /*!< FRONTGAM (Bit 12)                                     */
33190  #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Msk     (0x1000UL)     /*!< FRONTGAM (Bitfield-Mask: 0x01)                        */
33191  #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Pos      (8UL)          /*!< LCDEDGE (Bit 8)                                       */
33192  #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Msk      (0x100UL)      /*!< LCDEDGE (Bitfield-Mask: 0x01)                         */
33193  #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Pos    (6UL)          /*!< TCON0EDGE (Bit 6)                                     */
33194  #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Msk    (0x40UL)       /*!< TCON0EDGE (Bitfield-Mask: 0x01)                       */
33195  #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Pos    (5UL)          /*!< TCON1EDGE (Bit 5)                                     */
33196  #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Msk    (0x20UL)       /*!< TCON1EDGE (Bitfield-Mask: 0x01)                       */
33197  #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Pos    (4UL)          /*!< TCON2EDGE (Bit 4)                                     */
33198  #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Msk    (0x10UL)       /*!< TCON2EDGE (Bitfield-Mask: 0x01)                       */
33199  #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Pos    (3UL)          /*!< TCON3EDGE (Bit 3)                                     */
33200  #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Msk    (0x8UL)        /*!< TCON3EDGE (Bitfield-Mask: 0x01)                       */
33201 
33202 /* =========================================================================================================================== */
33203 /* ================                                           TCON                                            ================ */
33204 /* =========================================================================================================================== */
33205 
33206 /* ==========================================================  TIM  ========================================================== */
33207  #define R_GLCDC_TCON_TIM_HALF_Pos       (16UL)        /*!< HALF (Bit 16)                                         */
33208  #define R_GLCDC_TCON_TIM_HALF_Msk       (0x7ff0000UL) /*!< HALF (Bitfield-Mask: 0x7ff)                           */
33209  #define R_GLCDC_TCON_TIM_OFFSET_Pos     (0UL)         /*!< OFFSET (Bit 0)                                        */
33210  #define R_GLCDC_TCON_TIM_OFFSET_Msk     (0x7ffUL)     /*!< OFFSET (Bitfield-Mask: 0x7ff)                         */
33211 /* =========================================================  STVA1  ========================================================= */
33212  #define R_GLCDC_TCON_STVA1_VS_Pos       (16UL)        /*!< VS (Bit 16)                                           */
33213  #define R_GLCDC_TCON_STVA1_VS_Msk       (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff)                             */
33214  #define R_GLCDC_TCON_STVA1_VW_Pos       (0UL)         /*!< VW (Bit 0)                                            */
33215  #define R_GLCDC_TCON_STVA1_VW_Msk       (0x7ffUL)     /*!< VW (Bitfield-Mask: 0x7ff)                             */
33216 /* =========================================================  STVB1  ========================================================= */
33217  #define R_GLCDC_TCON_STVB1_VS_Pos       (16UL)        /*!< VS (Bit 16)                                           */
33218  #define R_GLCDC_TCON_STVB1_VS_Msk       (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff)                             */
33219  #define R_GLCDC_TCON_STVB1_VW_Pos       (0UL)         /*!< VW (Bit 0)                                            */
33220  #define R_GLCDC_TCON_STVB1_VW_Msk       (0x7ffUL)     /*!< VW (Bitfield-Mask: 0x7ff)                             */
33221 /* =========================================================  STVA2  ========================================================= */
33222  #define R_GLCDC_TCON_STVA2_INV_Pos      (4UL)         /*!< INV (Bit 4)                                           */
33223  #define R_GLCDC_TCON_STVA2_INV_Msk      (0x10UL)      /*!< INV (Bitfield-Mask: 0x01)                             */
33224  #define R_GLCDC_TCON_STVA2_SEL_Pos      (0UL)         /*!< SEL (Bit 0)                                           */
33225  #define R_GLCDC_TCON_STVA2_SEL_Msk      (0x7UL)       /*!< SEL (Bitfield-Mask: 0x07)                             */
33226 /* =========================================================  STVB2  ========================================================= */
33227  #define R_GLCDC_TCON_STVB2_INV_Pos      (4UL)         /*!< INV (Bit 4)                                           */
33228  #define R_GLCDC_TCON_STVB2_INV_Msk      (0x10UL)      /*!< INV (Bitfield-Mask: 0x01)                             */
33229  #define R_GLCDC_TCON_STVB2_SEL_Pos      (0UL)         /*!< SEL (Bit 0)                                           */
33230  #define R_GLCDC_TCON_STVB2_SEL_Msk      (0x7UL)       /*!< SEL (Bitfield-Mask: 0x07)                             */
33231 /* =========================================================  STHA1  ========================================================= */
33232  #define R_GLCDC_TCON_STHA1_HS_Pos       (16UL)        /*!< HS (Bit 16)                                           */
33233  #define R_GLCDC_TCON_STHA1_HS_Msk       (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff)                             */
33234  #define R_GLCDC_TCON_STHA1_HW_Pos       (0UL)         /*!< HW (Bit 0)                                            */
33235  #define R_GLCDC_TCON_STHA1_HW_Msk       (0x7ffUL)     /*!< HW (Bitfield-Mask: 0x7ff)                             */
33236 /* =========================================================  STHB1  ========================================================= */
33237  #define R_GLCDC_TCON_STHB1_HS_Pos       (16UL)        /*!< HS (Bit 16)                                           */
33238  #define R_GLCDC_TCON_STHB1_HS_Msk       (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff)                             */
33239  #define R_GLCDC_TCON_STHB1_HW_Pos       (0UL)         /*!< HW (Bit 0)                                            */
33240  #define R_GLCDC_TCON_STHB1_HW_Msk       (0x7ffUL)     /*!< HW (Bitfield-Mask: 0x7ff)                             */
33241 /* =========================================================  STHA2  ========================================================= */
33242  #define R_GLCDC_TCON_STHA2_HSSEL_Pos    (8UL)         /*!< HSSEL (Bit 8)                                         */
33243  #define R_GLCDC_TCON_STHA2_HSSEL_Msk    (0x100UL)     /*!< HSSEL (Bitfield-Mask: 0x01)                           */
33244  #define R_GLCDC_TCON_STHA2_INV_Pos      (4UL)         /*!< INV (Bit 4)                                           */
33245  #define R_GLCDC_TCON_STHA2_INV_Msk      (0x10UL)      /*!< INV (Bitfield-Mask: 0x01)                             */
33246  #define R_GLCDC_TCON_STHA2_SEL_Pos      (0UL)         /*!< SEL (Bit 0)                                           */
33247  #define R_GLCDC_TCON_STHA2_SEL_Msk      (0x7UL)       /*!< SEL (Bitfield-Mask: 0x07)                             */
33248 /* =========================================================  STHB2  ========================================================= */
33249  #define R_GLCDC_TCON_STHB2_HSSEL_Pos    (8UL)         /*!< HSSEL (Bit 8)                                         */
33250  #define R_GLCDC_TCON_STHB2_HSSEL_Msk    (0x100UL)     /*!< HSSEL (Bitfield-Mask: 0x01)                           */
33251  #define R_GLCDC_TCON_STHB2_INV_Pos      (4UL)         /*!< INV (Bit 4)                                           */
33252  #define R_GLCDC_TCON_STHB2_INV_Msk      (0x10UL)      /*!< INV (Bitfield-Mask: 0x01)                             */
33253  #define R_GLCDC_TCON_STHB2_SEL_Pos      (0UL)         /*!< SEL (Bit 0)                                           */
33254  #define R_GLCDC_TCON_STHB2_SEL_Msk      (0x7UL)       /*!< SEL (Bitfield-Mask: 0x07)                             */
33255 /* ==========================================================  DE  =========================================================== */
33256  #define R_GLCDC_TCON_DE_INV_Pos         (0UL)         /*!< INV (Bit 0)                                           */
33257  #define R_GLCDC_TCON_DE_INV_Msk         (0x1UL)       /*!< INV (Bitfield-Mask: 0x01)                             */
33258 
33259 /* =========================================================================================================================== */
33260 /* ================                                          SYSCNT                                           ================ */
33261 /* =========================================================================================================================== */
33262 
33263 /* ========================================================  DTCTEN  ========================================================= */
33264  #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Pos     (2UL)          /*!< L2UNDFDTC (Bit 2)                                     */
33265  #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Msk     (0x4UL)        /*!< L2UNDFDTC (Bitfield-Mask: 0x01)                       */
33266  #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Pos     (1UL)          /*!< L1UNDFDTC (Bit 1)                                     */
33267  #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Msk     (0x2UL)        /*!< L1UNDFDTC (Bitfield-Mask: 0x01)                       */
33268  #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Pos       (0UL)          /*!< VPOSDTC (Bit 0)                                       */
33269  #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Msk       (0x1UL)        /*!< VPOSDTC (Bitfield-Mask: 0x01)                         */
33270 /* =========================================================  INTEN  ========================================================= */
33271  #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Pos    (2UL)          /*!< L2UNDFINTEN (Bit 2)                                   */
33272  #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Msk    (0x4UL)        /*!< L2UNDFINTEN (Bitfield-Mask: 0x01)                     */
33273  #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Pos    (1UL)          /*!< L1UNDFINTEN (Bit 1)                                   */
33274  #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Msk    (0x2UL)        /*!< L1UNDFINTEN (Bitfield-Mask: 0x01)                     */
33275  #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Pos      (0UL)          /*!< VPOSINTEN (Bit 0)                                     */
33276  #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Msk      (0x1UL)        /*!< VPOSINTEN (Bitfield-Mask: 0x01)                       */
33277 /* =========================================================  STCLR  ========================================================= */
33278  #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Pos      (2UL)          /*!< L2UNDFCLR (Bit 2)                                     */
33279  #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Msk      (0x4UL)        /*!< L2UNDFCLR (Bitfield-Mask: 0x01)                       */
33280  #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Pos      (1UL)          /*!< L1UNDFCLR (Bit 1)                                     */
33281  #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Msk      (0x2UL)        /*!< L1UNDFCLR (Bitfield-Mask: 0x01)                       */
33282  #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Pos        (0UL)          /*!< VPOSCLR (Bit 0)                                       */
33283  #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Msk        (0x1UL)        /*!< VPOSCLR (Bitfield-Mask: 0x01)                         */
33284 /* =========================================================  STMON  ========================================================= */
33285  #define R_GLCDC_SYSCNT_STMON_L2UNDF_Pos         (2UL)          /*!< L2UNDF (Bit 2)                                        */
33286  #define R_GLCDC_SYSCNT_STMON_L2UNDF_Msk         (0x4UL)        /*!< L2UNDF (Bitfield-Mask: 0x01)                          */
33287  #define R_GLCDC_SYSCNT_STMON_L1UNDF_Pos         (1UL)          /*!< L1UNDF (Bit 1)                                        */
33288  #define R_GLCDC_SYSCNT_STMON_L1UNDF_Msk         (0x2UL)        /*!< L1UNDF (Bitfield-Mask: 0x01)                          */
33289  #define R_GLCDC_SYSCNT_STMON_VPOS_Pos           (0UL)          /*!< VPOS (Bit 0)                                          */
33290  #define R_GLCDC_SYSCNT_STMON_VPOS_Msk           (0x1UL)        /*!< VPOS (Bitfield-Mask: 0x01)                            */
33291 /* =======================================================  PANEL_CLK  ======================================================= */
33292  #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Pos        (16UL)         /*!< VER (Bit 16)                                          */
33293  #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Msk        (0xffff0000UL) /*!< VER (Bitfield-Mask: 0xffff)                           */
33294  #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Pos     (12UL)         /*!< PIXSEL (Bit 12)                                       */
33295  #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Msk     (0x1000UL)     /*!< PIXSEL (Bitfield-Mask: 0x01)                          */
33296  #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Pos     (8UL)          /*!< CLKSEL (Bit 8)                                        */
33297  #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Msk     (0x100UL)      /*!< CLKSEL (Bitfield-Mask: 0x01)                          */
33298  #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Pos      (6UL)          /*!< CLKEN (Bit 6)                                         */
33299  #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Msk      (0x40UL)       /*!< CLKEN (Bitfield-Mask: 0x01)                           */
33300  #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Pos       (0UL)          /*!< DCDR (Bit 0)                                          */
33301  #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Msk       (0x3fUL)       /*!< DCDR (Bitfield-Mask: 0x3f)                            */
33302 
33303 /* =========================================================================================================================== */
33304 /* ================                                          GTDLYR                                           ================ */
33305 /* =========================================================================================================================== */
33306 
33307 /* ===========================================================  A  =========================================================== */
33308  #define R_GPT_ODC_GTDLYR_A_DLY_Pos    (0UL)    /*!< DLY (Bit 0)                                           */
33309  #define R_GPT_ODC_GTDLYR_A_DLY_Msk    (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f)                             */
33310 /* ===========================================================  B  =========================================================== */
33311  #define R_GPT_ODC_GTDLYR_B_DLY_Pos    (0UL)    /*!< DLY (Bit 0)                                           */
33312  #define R_GPT_ODC_GTDLYR_B_DLY_Msk    (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f)                             */
33313 
33314 /* =========================================================================================================================== */
33315 /* ================                                            SAR                                            ================ */
33316 /* =========================================================================================================================== */
33317 
33318 /* ===========================================================  L  =========================================================== */
33319  #define R_IIC0_SAR_L_SVA_Pos     (0UL)    /*!< SVA (Bit 0)                                           */
33320  #define R_IIC0_SAR_L_SVA_Msk     (0xffUL) /*!< SVA (Bitfield-Mask: 0xff)                             */
33321 /* ===========================================================  U  =========================================================== */
33322  #define R_IIC0_SAR_U_SVA9_Pos    (2UL)    /*!< SVA9 (Bit 2)                                          */
33323  #define R_IIC0_SAR_U_SVA9_Msk    (0x4UL)  /*!< SVA9 (Bitfield-Mask: 0x01)                            */
33324  #define R_IIC0_SAR_U_SVA8_Pos    (1UL)    /*!< SVA8 (Bit 1)                                          */
33325  #define R_IIC0_SAR_U_SVA8_Msk    (0x2UL)  /*!< SVA8 (Bitfield-Mask: 0x01)                            */
33326  #define R_IIC0_SAR_U_FS_Pos      (0UL)    /*!< FS (Bit 0)                                            */
33327  #define R_IIC0_SAR_U_FS_Msk      (0x1UL)  /*!< FS (Bitfield-Mask: 0x01)                              */
33328 
33329 /* =========================================================================================================================== */
33330 /* ================                                           IIRCH                                           ================ */
33331 /* =========================================================================================================================== */
33332 
33333 /* ==========================================================  INP  ========================================================== */
33334 /* ==========================================================  OUT  ========================================================== */
33335 /* ==========================================================  CNT  ========================================================== */
33336  #define R_IIRFA_IIRCH_CNT_STGSEL_Pos        (0UL)          /*!< STGSEL (Bit 0)                                        */
33337  #define R_IIRFA_IIRCH_CNT_STGSEL_Msk        (0xffffffffUL) /*!< STGSEL (Bitfield-Mask: 0xffffffff)                    */
33338 /* ==========================================================  INT  ========================================================== */
33339  #define R_IIRFA_IIRCH_INT_CPRCFIE_Pos       (1UL)          /*!< CPRCFIE (Bit 1)                                       */
33340  #define R_IIRFA_IIRCH_INT_CPRCFIE_Msk       (0x2UL)        /*!< CPRCFIE (Bitfield-Mask: 0x01)                         */
33341  #define R_IIRFA_IIRCH_INT_ORDYIE_Pos        (2UL)          /*!< ORDYIE (Bit 2)                                        */
33342  #define R_IIRFA_IIRCH_INT_ORDYIE_Msk        (0x4UL)        /*!< ORDYIE (Bitfield-Mask: 0x01)                          */
33343  #define R_IIRFA_IIRCH_INT_CERRIE_Pos        (3UL)          /*!< CERRIE (Bit 3)                                        */
33344  #define R_IIRFA_IIRCH_INT_CERRIE_Msk        (0x8UL)        /*!< CERRIE (Bitfield-Mask: 0x01)                          */
33345 /* ==========================================================  STS  ========================================================== */
33346  #define R_IIRFA_IIRCH_STS_CPRCS_Pos         (0UL)          /*!< CPRCS (Bit 0)                                         */
33347  #define R_IIRFA_IIRCH_STS_CPRCS_Msk         (0x1UL)        /*!< CPRCS (Bitfield-Mask: 0x01)                           */
33348  #define R_IIRFA_IIRCH_STS_CPRCFF_Pos        (1UL)          /*!< CPRCFF (Bit 1)                                        */
33349  #define R_IIRFA_IIRCH_STS_CPRCFF_Msk        (0x2UL)        /*!< CPRCFF (Bitfield-Mask: 0x01)                          */
33350  #define R_IIRFA_IIRCH_STS_ORDYF_Pos         (2UL)          /*!< ORDYF (Bit 2)                                         */
33351  #define R_IIRFA_IIRCH_STS_ORDYF_Msk         (0x4UL)        /*!< ORDYF (Bitfield-Mask: 0x01)                           */
33352  #define R_IIRFA_IIRCH_STS_CERRF_Pos         (3UL)          /*!< CERRF (Bit 3)                                         */
33353  #define R_IIRFA_IIRCH_STS_CERRF_Msk         (0x8UL)        /*!< CERRF (Bitfield-Mask: 0x01)                           */
33354 /* =========================================================  FCLR  ========================================================== */
33355  #define R_IIRFA_IIRCH_FCLR_CPRCFFCLR_Pos    (1UL)          /*!< CPRCFFCLR (Bit 1)                                     */
33356  #define R_IIRFA_IIRCH_FCLR_CPRCFFCLR_Msk    (0x2UL)        /*!< CPRCFFCLR (Bitfield-Mask: 0x01)                       */
33357  #define R_IIRFA_IIRCH_FCLR_CERRFCLR_Pos     (3UL)          /*!< CERRFCLR (Bit 3)                                      */
33358  #define R_IIRFA_IIRCH_FCLR_CERRFCLR_Msk     (0x8UL)        /*!< CERRFCLR (Bitfield-Mask: 0x01)                        */
33359 
33360 /* =========================================================================================================================== */
33361 /* ================                                          IIRSTG                                           ================ */
33362 /* =========================================================================================================================== */
33363 
33364 /* ==========================================================  B0  =========================================================== */
33365 /* ==========================================================  B1  =========================================================== */
33366 /* ==========================================================  B2  =========================================================== */
33367 /* ==========================================================  A1  =========================================================== */
33368 /* ==========================================================  A2  =========================================================== */
33369 /* ==========================================================  D0  =========================================================== */
33370 /* ==========================================================  D1  =========================================================== */
33371 
33372 /* =========================================================================================================================== */
33373 /* ================                                          REGION                                           ================ */
33374 /* =========================================================================================================================== */
33375 
33376 /* ===========================================================  C  =========================================================== */
33377  #define R_MPU_MMPU_MMPU_REGION_C_WP_Pos         (2UL)          /*!< WP (Bit 2)                                            */
33378  #define R_MPU_MMPU_MMPU_REGION_C_WP_Msk         (0x4UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
33379  #define R_MPU_MMPU_MMPU_REGION_C_RP_Pos         (1UL)          /*!< RP (Bit 1)                                            */
33380  #define R_MPU_MMPU_MMPU_REGION_C_RP_Msk         (0x2UL)        /*!< RP (Bitfield-Mask: 0x01)                              */
33381  #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Pos     (0UL)          /*!< ENABLE (Bit 0)                                        */
33382  #define R_MPU_MMPU_MMPU_REGION_C_ENABLE_Msk     (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
33383 /* ===========================================================  S  =========================================================== */
33384  #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Pos    (0UL)          /*!< MMPUSmn (Bit 0)                                       */
33385  #define R_MPU_MMPU_MMPU_REGION_S_MMPUSmn_Msk    (0xffffffffUL) /*!< MMPUSmn (Bitfield-Mask: 0xffffffff)                   */
33386 /* ===========================================================  E  =========================================================== */
33387  #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Pos    (0UL)          /*!< MMPUEmn (Bit 0)                                       */
33388  #define R_MPU_MMPU_MMPU_REGION_E_MMPUEmn_Msk    (0xffffffffUL) /*!< MMPUEmn (Bitfield-Mask: 0xffffffff)                   */
33389 
33390 /* =========================================================================================================================== */
33391 /* ================                                           MMPU                                            ================ */
33392 /* =========================================================================================================================== */
33393 
33394 /* ==========================================================  CTL  ========================================================== */
33395  #define R_MPU_MMPU_MMPU_CTL_KEY_Pos       (8UL)      /*!< KEY (Bit 8)                                           */
33396  #define R_MPU_MMPU_MMPU_CTL_KEY_Msk       (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
33397  #define R_MPU_MMPU_MMPU_CTL_OAD_Pos       (1UL)      /*!< OAD (Bit 1)                                           */
33398  #define R_MPU_MMPU_MMPU_CTL_OAD_Msk       (0x2UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
33399  #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos    (0UL)      /*!< ENABLE (Bit 0)                                        */
33400  #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk    (0x1UL)    /*!< ENABLE (Bitfield-Mask: 0x01)                          */
33401 /* ==========================================================  PT  =========================================================== */
33402  #define R_MPU_MMPU_MMPU_PT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
33403  #define R_MPU_MMPU_MMPU_PT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
33404  #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
33405  #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
33406 
33407 /* =========================================================================================================================== */
33408 /* ================                                           SMPU                                            ================ */
33409 /* =========================================================================================================================== */
33410 
33411 /* ===========================================================  R  =========================================================== */
33412  #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos    (15UL)     /*!< WPSRAMHS (Bit 15)                                     */
33413  #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk    (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01)                        */
33414  #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos    (14UL)     /*!< RPSRAMHS (Bit 14)                                     */
33415  #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk    (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01)                        */
33416  #define R_MPU_SMPU_SMPU_R_WPFLI_Pos       (13UL)     /*!< WPFLI (Bit 13)                                        */
33417  #define R_MPU_SMPU_SMPU_R_WPFLI_Msk       (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01)                           */
33418  #define R_MPU_SMPU_SMPU_R_RPFLI_Pos       (12UL)     /*!< RPFLI (Bit 12)                                        */
33419  #define R_MPU_SMPU_SMPU_R_RPFLI_Msk       (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01)                           */
33420  #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos      (7UL)      /*!< WPGRPC (Bit 7)                                        */
33421  #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk      (0x80UL)   /*!< WPGRPC (Bitfield-Mask: 0x01)                          */
33422  #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos      (6UL)      /*!< RPGRPC (Bit 6)                                        */
33423  #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk      (0x40UL)   /*!< RPGRPC (Bitfield-Mask: 0x01)                          */
33424  #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos      (5UL)      /*!< WPGRPB (Bit 5)                                        */
33425  #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk      (0x20UL)   /*!< WPGRPB (Bitfield-Mask: 0x01)                          */
33426  #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos      (4UL)      /*!< RPGRPB (Bit 4)                                        */
33427  #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk      (0x10UL)   /*!< RPGRPB (Bitfield-Mask: 0x01)                          */
33428  #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos      (3UL)      /*!< WPGRPA (Bit 3)                                        */
33429  #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk      (0x8UL)    /*!< WPGRPA (Bitfield-Mask: 0x01)                          */
33430  #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos      (2UL)      /*!< RPGRPA (Bit 2)                                        */
33431  #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk      (0x4UL)    /*!< RPGRPA (Bitfield-Mask: 0x01)                          */
33432 
33433 /* =========================================================================================================================== */
33434 /* ================                                            SP                                             ================ */
33435 /* =========================================================================================================================== */
33436 
33437 /* ==========================================================  OAD  ========================================================== */
33438  #define R_MPU_SPMON_SP_OAD_KEY_Pos        (8UL)          /*!< KEY (Bit 8)                                           */
33439  #define R_MPU_SPMON_SP_OAD_KEY_Msk        (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
33440  #define R_MPU_SPMON_SP_OAD_OAD_Pos        (0UL)          /*!< OAD (Bit 0)                                           */
33441  #define R_MPU_SPMON_SP_OAD_OAD_Msk        (0x1UL)        /*!< OAD (Bitfield-Mask: 0x01)                             */
33442 /* ==========================================================  CTL  ========================================================== */
33443  #define R_MPU_SPMON_SP_CTL_ERROR_Pos      (8UL)          /*!< ERROR (Bit 8)                                         */
33444  #define R_MPU_SPMON_SP_CTL_ERROR_Msk      (0x100UL)      /*!< ERROR (Bitfield-Mask: 0x01)                           */
33445  #define R_MPU_SPMON_SP_CTL_ENABLE_Pos     (0UL)          /*!< ENABLE (Bit 0)                                        */
33446  #define R_MPU_SPMON_SP_CTL_ENABLE_Msk     (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
33447 /* ==========================================================  PT  =========================================================== */
33448  #define R_MPU_SPMON_SP_PT_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
33449  #define R_MPU_SPMON_SP_PT_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
33450  #define R_MPU_SPMON_SP_PT_PROTECT_Pos     (0UL)          /*!< PROTECT (Bit 0)                                       */
33451  #define R_MPU_SPMON_SP_PT_PROTECT_Msk     (0x1UL)        /*!< PROTECT (Bitfield-Mask: 0x01)                         */
33452 /* ==========================================================  SA  =========================================================== */
33453  #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos    (0UL)          /*!< MSPMPUSA (Bit 0)                                      */
33454  #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk    (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff)                  */
33455 /* ==========================================================  EA  =========================================================== */
33456  #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos    (0UL)          /*!< MSPMPUEA (Bit 0)                                      */
33457  #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk    (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff)                  */
33458 
33459 /* =========================================================================================================================== */
33460 /* ================                                            AMP                                            ================ */
33461 /* =========================================================================================================================== */
33462 
33463 /* ==========================================================  OS  =========================================================== */
33464 /* ==========================================================  PS  =========================================================== */
33465 /* ==========================================================  MS  =========================================================== */
33466 
33467 /* =========================================================================================================================== */
33468 /* ================                                           AMPOT                                           ================ */
33469 /* =========================================================================================================================== */
33470 
33471 /* ===========================================================  P  =========================================================== */
33472  #define R_OPAMP_AMPOT_P_TRMP_Pos    (0UL)    /*!< TRMP (Bit 0)                                          */
33473  #define R_OPAMP_AMPOT_P_TRMP_Msk    (0x1fUL) /*!< TRMP (Bitfield-Mask: 0x1f)                            */
33474 /* ===========================================================  N  =========================================================== */
33475  #define R_OPAMP_AMPOT_N_TRMN_Pos    (0UL)    /*!< TRMN (Bit 0)                                          */
33476  #define R_OPAMP_AMPOT_N_TRMN_Msk    (0x1fUL) /*!< TRMN (Bitfield-Mask: 0x1f)                            */
33477 
33478 /* =========================================================================================================================== */
33479 /* ================                                            PIN                                            ================ */
33480 /* =========================================================================================================================== */
33481 
33482 /* =======================================================  PmnPFS_BY  ======================================================= */
33483  #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
33484  #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
33485  #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos      (5UL)          /*!< PIM (Bit 5)                                           */
33486  #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk      (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
33487  #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
33488  #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
33489  #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
33490  #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
33491  #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
33492  #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
33493  #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
33494  #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
33495 /* =======================================================  PmnPFS_HA  ======================================================= */
33496  #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
33497  #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
33498  #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos      (5UL)          /*!< PIM (Bit 5)                                           */
33499  #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk      (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
33500  #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
33501  #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
33502  #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
33503  #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
33504  #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
33505  #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
33506  #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
33507  #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
33508  #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos     (15UL)         /*!< ASEL (Bit 15)                                         */
33509  #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk     (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
33510  #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos     (14UL)         /*!< ISEL (Bit 14)                                         */
33511  #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk     (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
33512  #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos     (12UL)         /*!< EOFR (Bit 12)                                         */
33513  #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk     (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
33514  #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos     (10UL)         /*!< DSCR (Bit 10)                                         */
33515  #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk     (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
33516 /* ========================================================  PmnPFS  ========================================================= */
33517  #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos       (6UL)          /*!< NCODR (Bit 6)                                         */
33518  #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk       (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
33519  #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos         (5UL)          /*!< PIM (Bit 5)                                           */
33520  #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk         (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
33521  #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos         (4UL)          /*!< PCR (Bit 4)                                           */
33522  #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk         (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
33523  #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos         (2UL)          /*!< PDR (Bit 2)                                           */
33524  #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk         (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
33525  #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos        (1UL)          /*!< PIDR (Bit 1)                                          */
33526  #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk        (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
33527  #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos        (0UL)          /*!< PODR (Bit 0)                                          */
33528  #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk        (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
33529  #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos        (15UL)         /*!< ASEL (Bit 15)                                         */
33530  #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk        (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
33531  #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos        (14UL)         /*!< ISEL (Bit 14)                                         */
33532  #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk        (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
33533  #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos        (12UL)         /*!< EOFR (Bit 12)                                         */
33534  #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk        (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
33535  #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos        (10UL)         /*!< DSCR (Bit 10)                                         */
33536  #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk        (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
33537  #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos        (24UL)         /*!< PSEL (Bit 24)                                         */
33538  #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk        (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f)                            */
33539  #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos         (16UL)         /*!< PMR (Bit 16)                                          */
33540  #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk         (0x10000UL)    /*!< PMR (Bitfield-Mask: 0x01)                             */
33541 
33542 /* =========================================================================================================================== */
33543 /* ================                                           PORT                                            ================ */
33544 /* =========================================================================================================================== */
33545 
33546 /* =========================================================================================================================== */
33547 /* ================                                           PMSAR                                           ================ */
33548 /* =========================================================================================================================== */
33549 
33550 /* =========================================================  PMSAR  ========================================================= */
33551 
33552 /* =========================================================================================================================== */
33553 /* ================                                           RTCCR                                           ================ */
33554 /* =========================================================================================================================== */
33555 
33556 /* =========================================================  RTCCR  ========================================================= */
33557  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
33558  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
33559  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
33560  #define R_RTC_RTCCR_RTCCR_TCST_Msk    (0x4UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
33561  #define R_RTC_RTCCR_RTCCR_TCCT_Pos    (0UL)    /*!< TCCT (Bit 0)                                          */
33562  #define R_RTC_RTCCR_RTCCR_TCCT_Msk    (0x3UL)  /*!< TCCT (Bitfield-Mask: 0x03)                            */
33563 
33564 /* =========================================================================================================================== */
33565 /* ================                                            CP                                             ================ */
33566 /* =========================================================================================================================== */
33567 
33568 /* =========================================================  RSEC  ========================================================== */
33569  #define R_RTC_CP_RSEC_SEC10_Pos       (4UL)    /*!< SEC10 (Bit 4)                                         */
33570  #define R_RTC_CP_RSEC_SEC10_Msk       (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07)                           */
33571  #define R_RTC_CP_RSEC_SEC1_Pos        (0UL)    /*!< SEC1 (Bit 0)                                          */
33572  #define R_RTC_CP_RSEC_SEC1_Msk        (0xfUL)  /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
33573 /* =========================================================  BCNT0  ========================================================= */
33574  #define R_RTC_CP_BCNT0_BCNT0CP_Pos    (0UL)    /*!< BCNT0CP (Bit 0)                                       */
33575  #define R_RTC_CP_BCNT0_BCNT0CP_Msk    (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff)                         */
33576 /* =========================================================  RMIN  ========================================================== */
33577  #define R_RTC_CP_RMIN_MIN10_Pos       (4UL)    /*!< MIN10 (Bit 4)                                         */
33578  #define R_RTC_CP_RMIN_MIN10_Msk       (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07)                           */
33579  #define R_RTC_CP_RMIN_MIN1_Pos        (0UL)    /*!< MIN1 (Bit 0)                                          */
33580  #define R_RTC_CP_RMIN_MIN1_Msk        (0xfUL)  /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
33581 /* =========================================================  BCNT1  ========================================================= */
33582  #define R_RTC_CP_BCNT1_BCNT1CP_Pos    (0UL)    /*!< BCNT1CP (Bit 0)                                       */
33583  #define R_RTC_CP_BCNT1_BCNT1CP_Msk    (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff)                         */
33584 /* ==========================================================  RHR  ========================================================== */
33585  #define R_RTC_CP_RHR_PM_Pos           (6UL)    /*!< PM (Bit 6)                                            */
33586  #define R_RTC_CP_RHR_PM_Msk           (0x40UL) /*!< PM (Bitfield-Mask: 0x01)                              */
33587  #define R_RTC_CP_RHR_HR10_Pos         (4UL)    /*!< HR10 (Bit 4)                                          */
33588  #define R_RTC_CP_RHR_HR10_Msk         (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03)                            */
33589  #define R_RTC_CP_RHR_HR1_Pos          (0UL)    /*!< HR1 (Bit 0)                                           */
33590  #define R_RTC_CP_RHR_HR1_Msk          (0xfUL)  /*!< HR1 (Bitfield-Mask: 0x0f)                             */
33591 /* =========================================================  BCNT2  ========================================================= */
33592  #define R_RTC_CP_BCNT2_BCNT2CP_Pos    (0UL)    /*!< BCNT2CP (Bit 0)                                       */
33593  #define R_RTC_CP_BCNT2_BCNT2CP_Msk    (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff)                         */
33594 /* =========================================================  RDAY  ========================================================== */
33595  #define R_RTC_CP_RDAY_DATE10_Pos      (4UL)    /*!< DATE10 (Bit 4)                                        */
33596  #define R_RTC_CP_RDAY_DATE10_Msk      (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03)                          */
33597  #define R_RTC_CP_RDAY_DATE1_Pos       (0UL)    /*!< DATE1 (Bit 0)                                         */
33598  #define R_RTC_CP_RDAY_DATE1_Msk       (0xfUL)  /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
33599 /* =========================================================  BCNT3  ========================================================= */
33600  #define R_RTC_CP_BCNT3_BCNT3CP_Pos    (0UL)    /*!< BCNT3CP (Bit 0)                                       */
33601  #define R_RTC_CP_BCNT3_BCNT3CP_Msk    (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff)                         */
33602 /* =========================================================  RMON  ========================================================== */
33603  #define R_RTC_CP_RMON_MON10_Pos       (4UL)    /*!< MON10 (Bit 4)                                         */
33604  #define R_RTC_CP_RMON_MON10_Msk       (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01)                           */
33605  #define R_RTC_CP_RMON_MON1_Pos        (0UL)    /*!< MON1 (Bit 0)                                          */
33606  #define R_RTC_CP_RMON_MON1_Msk        (0xfUL)  /*!< MON1 (Bitfield-Mask: 0x0f)                            */
33607 
33608 /* =========================================================================================================================== */
33609 /* ================                                            CSa                                            ================ */
33610 /* =========================================================================================================================== */
33611 
33612 /* ==========================================================  MOD  ========================================================== */
33613  #define R_BUS_B_CSa_MOD_PRMOD_Pos        (15UL)         /*!< PRMOD (Bit 15)                                        */
33614  #define R_BUS_B_CSa_MOD_PRMOD_Msk        (0x8000UL)     /*!< PRMOD (Bitfield-Mask: 0x01)                           */
33615  #define R_BUS_B_CSa_MOD_PWENB_Pos        (9UL)          /*!< PWENB (Bit 9)                                         */
33616  #define R_BUS_B_CSa_MOD_PWENB_Msk        (0x200UL)      /*!< PWENB (Bitfield-Mask: 0x01)                           */
33617  #define R_BUS_B_CSa_MOD_PRENB_Pos        (8UL)          /*!< PRENB (Bit 8)                                         */
33618  #define R_BUS_B_CSa_MOD_PRENB_Msk        (0x100UL)      /*!< PRENB (Bitfield-Mask: 0x01)                           */
33619  #define R_BUS_B_CSa_MOD_EWENB_Pos        (3UL)          /*!< EWENB (Bit 3)                                         */
33620  #define R_BUS_B_CSa_MOD_EWENB_Msk        (0x8UL)        /*!< EWENB (Bitfield-Mask: 0x01)                           */
33621  #define R_BUS_B_CSa_MOD_WRMOD_Pos        (0UL)          /*!< WRMOD (Bit 0)                                         */
33622  #define R_BUS_B_CSa_MOD_WRMOD_Msk        (0x1UL)        /*!< WRMOD (Bitfield-Mask: 0x01)                           */
33623 /* =========================================================  WCR1  ========================================================== */
33624  #define R_BUS_B_CSa_WCR1_CSRWAIT_Pos     (24UL)         /*!< CSRWAIT (Bit 24)                                      */
33625  #define R_BUS_B_CSa_WCR1_CSRWAIT_Msk     (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f)                         */
33626  #define R_BUS_B_CSa_WCR1_CSWWAIT_Pos     (16UL)         /*!< CSWWAIT (Bit 16)                                      */
33627  #define R_BUS_B_CSa_WCR1_CSWWAIT_Msk     (0x1f0000UL)   /*!< CSWWAIT (Bitfield-Mask: 0x1f)                         */
33628  #define R_BUS_B_CSa_WCR1_CSPRWAIT_Pos    (8UL)          /*!< CSPRWAIT (Bit 8)                                      */
33629  #define R_BUS_B_CSa_WCR1_CSPRWAIT_Msk    (0x700UL)      /*!< CSPRWAIT (Bitfield-Mask: 0x07)                        */
33630  #define R_BUS_B_CSa_WCR1_CSPWWAIT_Pos    (0UL)          /*!< CSPWWAIT (Bit 0)                                      */
33631  #define R_BUS_B_CSa_WCR1_CSPWWAIT_Msk    (0x7UL)        /*!< CSPWWAIT (Bitfield-Mask: 0x07)                        */
33632 /* =========================================================  WCR2  ========================================================== */
33633  #define R_BUS_B_CSa_WCR2_CSON_Pos        (28UL)         /*!< CSON (Bit 28)                                         */
33634  #define R_BUS_B_CSa_WCR2_CSON_Msk        (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07)                            */
33635  #define R_BUS_B_CSa_WCR2_WDON_Pos        (24UL)         /*!< WDON (Bit 24)                                         */
33636  #define R_BUS_B_CSa_WCR2_WDON_Msk        (0x7000000UL)  /*!< WDON (Bitfield-Mask: 0x07)                            */
33637  #define R_BUS_B_CSa_WCR2_WRON_Pos        (20UL)         /*!< WRON (Bit 20)                                         */
33638  #define R_BUS_B_CSa_WCR2_WRON_Msk        (0x700000UL)   /*!< WRON (Bitfield-Mask: 0x07)                            */
33639  #define R_BUS_B_CSa_WCR2_RDON_Pos        (16UL)         /*!< RDON (Bit 16)                                         */
33640  #define R_BUS_B_CSa_WCR2_RDON_Msk        (0x70000UL)    /*!< RDON (Bitfield-Mask: 0x07)                            */
33641  #define R_BUS_B_CSa_WCR2_AWAIT_Pos       (12UL)         /*!< AWAIT (Bit 12)                                        */
33642  #define R_BUS_B_CSa_WCR2_AWAIT_Msk       (0x3000UL)     /*!< AWAIT (Bitfield-Mask: 0x03)                           */
33643  #define R_BUS_B_CSa_WCR2_WDOFF_Pos       (8UL)          /*!< WDOFF (Bit 8)                                         */
33644  #define R_BUS_B_CSa_WCR2_WDOFF_Msk       (0x700UL)      /*!< WDOFF (Bitfield-Mask: 0x07)                           */
33645  #define R_BUS_B_CSa_WCR2_CSWOFF_Pos      (4UL)          /*!< CSWOFF (Bit 4)                                        */
33646  #define R_BUS_B_CSa_WCR2_CSWOFF_Msk      (0x70UL)       /*!< CSWOFF (Bitfield-Mask: 0x07)                          */
33647  #define R_BUS_B_CSa_WCR2_CSROFF_Pos      (0UL)          /*!< CSROFF (Bit 0)                                        */
33648  #define R_BUS_B_CSa_WCR2_CSROFF_Msk      (0x7UL)        /*!< CSROFF (Bitfield-Mask: 0x07)                          */
33649 
33650 /* =========================================================================================================================== */
33651 /* ================                                            CSb                                            ================ */
33652 /* =========================================================================================================================== */
33653 
33654 /* ==========================================================  CR  =========================================================== */
33655  #define R_BUS_B_CSb_CR_MPXEN_Pos    (12UL)     /*!< MPXEN (Bit 12)                                        */
33656  #define R_BUS_B_CSb_CR_MPXEN_Msk    (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01)                           */
33657  #define R_BUS_B_CSb_CR_EMODE_Pos    (8UL)      /*!< EMODE (Bit 8)                                         */
33658  #define R_BUS_B_CSb_CR_EMODE_Msk    (0x100UL)  /*!< EMODE (Bitfield-Mask: 0x01)                           */
33659  #define R_BUS_B_CSb_CR_BSIZE_Pos    (4UL)      /*!< BSIZE (Bit 4)                                         */
33660  #define R_BUS_B_CSb_CR_BSIZE_Msk    (0x30UL)   /*!< BSIZE (Bitfield-Mask: 0x03)                           */
33661  #define R_BUS_B_CSb_CR_EXENB_Pos    (0UL)      /*!< EXENB (Bit 0)                                         */
33662  #define R_BUS_B_CSb_CR_EXENB_Msk    (0x1UL)    /*!< EXENB (Bitfield-Mask: 0x01)                           */
33663 /* ==========================================================  REC  ========================================================== */
33664  #define R_BUS_B_CSb_REC_WRCV_Pos    (8UL)      /*!< WRCV (Bit 8)                                          */
33665  #define R_BUS_B_CSb_REC_WRCV_Msk    (0xf00UL)  /*!< WRCV (Bitfield-Mask: 0x0f)                            */
33666  #define R_BUS_B_CSb_REC_RRCV_Pos    (0UL)      /*!< RRCV (Bit 0)                                          */
33667  #define R_BUS_B_CSb_REC_RRCV_Msk    (0xfUL)    /*!< RRCV (Bitfield-Mask: 0x0f)                            */
33668 
33669 /* =========================================================================================================================== */
33670 /* ================                                          BUSERR                                           ================ */
33671 /* =========================================================================================================================== */
33672 
33673 /* ==========================================================  ADD  ========================================================== */
33674  #define R_BUS_B_BUSERR_ADD_BERAD_Pos       (0UL)          /*!< BERAD (Bit 0)                                         */
33675  #define R_BUS_B_BUSERR_ADD_BERAD_Msk       (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff)                     */
33676 /* =========================================================  ERRRW  ========================================================= */
33677  #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Pos    (0UL)          /*!< RWSTAT (Bit 0)                                        */
33678  #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Msk    (0x1UL)        /*!< RWSTAT (Bitfield-Mask: 0x01)                          */
33679 
33680 /* =========================================================================================================================== */
33681 /* ================                                         BUSTZFERR                                         ================ */
33682 /* =========================================================================================================================== */
33683 
33684 /* ========================================================  TZFADD  ========================================================= */
33685  #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Pos     (0UL)          /*!< BTZFERAD (Bit 0)                                      */
33686  #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Msk     (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff)                  */
33687 /* =======================================================  TZFERRRW  ======================================================== */
33688  #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos    (0UL)          /*!< TRWSTAT (Bit 0)                                       */
33689  #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk    (0x1UL)        /*!< TRWSTAT (Bitfield-Mask: 0x01)                         */
33690 
33691 /* =========================================================================================================================== */
33692 /* ================                                          PIPE_TR                                          ================ */
33693 /* =========================================================================================================================== */
33694 
33695 /* ===========================================================  E  =========================================================== */
33696  #define R_USB_FS0_PIPE_TR_E_TRENB_Pos     (9UL)      /*!< TRENB (Bit 9)                                         */
33697  #define R_USB_FS0_PIPE_TR_E_TRENB_Msk     (0x200UL)  /*!< TRENB (Bitfield-Mask: 0x01)                           */
33698  #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos     (8UL)      /*!< TRCLR (Bit 8)                                         */
33699  #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk     (0x100UL)  /*!< TRCLR (Bitfield-Mask: 0x01)                           */
33700 /* ===========================================================  N  =========================================================== */
33701  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
33702  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
33703 
33704 /** @} */ /* End of group PosMask_clusters */
33705 
33706 /* =========================================================================================================================== */
33707 /* ================                                Pos/Mask Peripheral Section                                ================ */
33708 /* =========================================================================================================================== */
33709 
33710 /** @addtogroup PosMask_peripherals
33711  * @{
33712  */
33713 
33714 /* =========================================================================================================================== */
33715 /* ================                                         R_ACMPHS0                                         ================ */
33716 /* =========================================================================================================================== */
33717 
33718 /* ========================================================  CMPCTL  ========================================================= */
33719  #define R_ACMPHS0_CMPCTL_HCMPON_Pos     (7UL)    /*!< HCMPON (Bit 7)                                        */
33720  #define R_ACMPHS0_CMPCTL_HCMPON_Msk     (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01)                          */
33721  #define R_ACMPHS0_CMPCTL_CDFS_Pos       (5UL)    /*!< CDFS (Bit 5)                                          */
33722  #define R_ACMPHS0_CMPCTL_CDFS_Msk       (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03)                            */
33723  #define R_ACMPHS0_CMPCTL_CEG_Pos        (3UL)    /*!< CEG (Bit 3)                                           */
33724  #define R_ACMPHS0_CMPCTL_CEG_Msk        (0x18UL) /*!< CEG (Bitfield-Mask: 0x03)                             */
33725  #define R_ACMPHS0_CMPCTL_CSTEN_Pos      (2UL)    /*!< CSTEN (Bit 2)                                         */
33726  #define R_ACMPHS0_CMPCTL_CSTEN_Msk      (0x4UL)  /*!< CSTEN (Bitfield-Mask: 0x01)                           */
33727  #define R_ACMPHS0_CMPCTL_COE_Pos        (1UL)    /*!< COE (Bit 1)                                           */
33728  #define R_ACMPHS0_CMPCTL_COE_Msk        (0x2UL)  /*!< COE (Bitfield-Mask: 0x01)                             */
33729  #define R_ACMPHS0_CMPCTL_CINV_Pos       (0UL)    /*!< CINV (Bit 0)                                          */
33730  #define R_ACMPHS0_CMPCTL_CINV_Msk       (0x1UL)  /*!< CINV (Bitfield-Mask: 0x01)                            */
33731 /* ========================================================  CMPSEL0  ======================================================== */
33732  #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos    (0UL)    /*!< CMPSEL (Bit 0)                                        */
33733  #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk    (0xfUL)  /*!< CMPSEL (Bitfield-Mask: 0x0f)                          */
33734 /* ========================================================  CMPSEL1  ======================================================== */
33735  #define R_ACMPHS0_CMPSEL1_CRVS_Pos      (0UL)    /*!< CRVS (Bit 0)                                          */
33736  #define R_ACMPHS0_CMPSEL1_CRVS_Msk      (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f)                            */
33737 /* ========================================================  CMPMON  ========================================================= */
33738  #define R_ACMPHS0_CMPMON_CMPMON_Pos     (0UL)    /*!< CMPMON (Bit 0)                                        */
33739  #define R_ACMPHS0_CMPMON_CMPMON_Msk     (0x1UL)  /*!< CMPMON (Bitfield-Mask: 0x01)                          */
33740 /* =========================================================  CPIOC  ========================================================= */
33741  #define R_ACMPHS0_CPIOC_VREFEN_Pos      (7UL)    /*!< VREFEN (Bit 7)                                        */
33742  #define R_ACMPHS0_CPIOC_VREFEN_Msk      (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01)                          */
33743  #define R_ACMPHS0_CPIOC_CPOE_Pos        (0UL)    /*!< CPOE (Bit 0)                                          */
33744  #define R_ACMPHS0_CPIOC_CPOE_Msk        (0x1UL)  /*!< CPOE (Bitfield-Mask: 0x01)                            */
33745 
33746 /* =========================================================================================================================== */
33747 /* ================                                         R_ACMPLP                                          ================ */
33748 /* =========================================================================================================================== */
33749 
33750 /* ========================================================  COMPMDR  ======================================================== */
33751  #define R_ACMPLP_COMPMDR_C1MON_Pos      (7UL)    /*!< C1MON (Bit 7)                                         */
33752  #define R_ACMPLP_COMPMDR_C1MON_Msk      (0x80UL) /*!< C1MON (Bitfield-Mask: 0x01)                           */
33753  #define R_ACMPLP_COMPMDR_C1VRF_Pos      (6UL)    /*!< C1VRF (Bit 6)                                         */
33754  #define R_ACMPLP_COMPMDR_C1VRF_Msk      (0x40UL) /*!< C1VRF (Bitfield-Mask: 0x01)                           */
33755  #define R_ACMPLP_COMPMDR_C1WDE_Pos      (5UL)    /*!< C1WDE (Bit 5)                                         */
33756  #define R_ACMPLP_COMPMDR_C1WDE_Msk      (0x20UL) /*!< C1WDE (Bitfield-Mask: 0x01)                           */
33757  #define R_ACMPLP_COMPMDR_C1ENB_Pos      (4UL)    /*!< C1ENB (Bit 4)                                         */
33758  #define R_ACMPLP_COMPMDR_C1ENB_Msk      (0x10UL) /*!< C1ENB (Bitfield-Mask: 0x01)                           */
33759  #define R_ACMPLP_COMPMDR_C0MON_Pos      (3UL)    /*!< C0MON (Bit 3)                                         */
33760  #define R_ACMPLP_COMPMDR_C0MON_Msk      (0x8UL)  /*!< C0MON (Bitfield-Mask: 0x01)                           */
33761  #define R_ACMPLP_COMPMDR_C0WDE_Pos      (1UL)    /*!< C0WDE (Bit 1)                                         */
33762  #define R_ACMPLP_COMPMDR_C0WDE_Msk      (0x2UL)  /*!< C0WDE (Bitfield-Mask: 0x01)                           */
33763  #define R_ACMPLP_COMPMDR_C0VRF_Pos      (2UL)    /*!< C0VRF (Bit 2)                                         */
33764  #define R_ACMPLP_COMPMDR_C0VRF_Msk      (0x4UL)  /*!< C0VRF (Bitfield-Mask: 0x01)                           */
33765  #define R_ACMPLP_COMPMDR_C0ENB_Pos      (0UL)    /*!< C0ENB (Bit 0)                                         */
33766  #define R_ACMPLP_COMPMDR_C0ENB_Msk      (0x1UL)  /*!< C0ENB (Bitfield-Mask: 0x01)                           */
33767 /* ========================================================  COMPFIR  ======================================================== */
33768  #define R_ACMPLP_COMPFIR_C1EDG_Pos      (7UL)    /*!< C1EDG (Bit 7)                                         */
33769  #define R_ACMPLP_COMPFIR_C1EDG_Msk      (0x80UL) /*!< C1EDG (Bitfield-Mask: 0x01)                           */
33770  #define R_ACMPLP_COMPFIR_C1EPO_Pos      (6UL)    /*!< C1EPO (Bit 6)                                         */
33771  #define R_ACMPLP_COMPFIR_C1EPO_Msk      (0x40UL) /*!< C1EPO (Bitfield-Mask: 0x01)                           */
33772  #define R_ACMPLP_COMPFIR_C1FCK_Pos      (4UL)    /*!< C1FCK (Bit 4)                                         */
33773  #define R_ACMPLP_COMPFIR_C1FCK_Msk      (0x30UL) /*!< C1FCK (Bitfield-Mask: 0x03)                           */
33774  #define R_ACMPLP_COMPFIR_C0EDG_Pos      (3UL)    /*!< C0EDG (Bit 3)                                         */
33775  #define R_ACMPLP_COMPFIR_C0EDG_Msk      (0x8UL)  /*!< C0EDG (Bitfield-Mask: 0x01)                           */
33776  #define R_ACMPLP_COMPFIR_C0EPO_Pos      (2UL)    /*!< C0EPO (Bit 2)                                         */
33777  #define R_ACMPLP_COMPFIR_C0EPO_Msk      (0x4UL)  /*!< C0EPO (Bitfield-Mask: 0x01)                           */
33778  #define R_ACMPLP_COMPFIR_C0FCK_Pos      (0UL)    /*!< C0FCK (Bit 0)                                         */
33779  #define R_ACMPLP_COMPFIR_C0FCK_Msk      (0x3UL)  /*!< C0FCK (Bitfield-Mask: 0x03)                           */
33780 /* ========================================================  COMPOCR  ======================================================== */
33781  #define R_ACMPLP_COMPOCR_SPDMD_Pos      (7UL)    /*!< SPDMD (Bit 7)                                         */
33782  #define R_ACMPLP_COMPOCR_SPDMD_Msk      (0x80UL) /*!< SPDMD (Bitfield-Mask: 0x01)                           */
33783  #define R_ACMPLP_COMPOCR_C1OP_Pos       (6UL)    /*!< C1OP (Bit 6)                                          */
33784  #define R_ACMPLP_COMPOCR_C1OP_Msk       (0x40UL) /*!< C1OP (Bitfield-Mask: 0x01)                            */
33785  #define R_ACMPLP_COMPOCR_C1OE_Pos       (5UL)    /*!< C1OE (Bit 5)                                          */
33786  #define R_ACMPLP_COMPOCR_C1OE_Msk       (0x20UL) /*!< C1OE (Bitfield-Mask: 0x01)                            */
33787  #define R_ACMPLP_COMPOCR_C0OP_Pos       (2UL)    /*!< C0OP (Bit 2)                                          */
33788  #define R_ACMPLP_COMPOCR_C0OP_Msk       (0x4UL)  /*!< C0OP (Bitfield-Mask: 0x01)                            */
33789  #define R_ACMPLP_COMPOCR_C0OE_Pos       (1UL)    /*!< C0OE (Bit 1)                                          */
33790  #define R_ACMPLP_COMPOCR_C0OE_Msk       (0x2UL)  /*!< C0OE (Bitfield-Mask: 0x01)                            */
33791 /* =======================================================  COMPSEL0  ======================================================== */
33792  #define R_ACMPLP_COMPSEL0_IVCMP1_Pos    (4UL)    /*!< IVCMP1 (Bit 4)                                        */
33793  #define R_ACMPLP_COMPSEL0_IVCMP1_Msk    (0x70UL) /*!< IVCMP1 (Bitfield-Mask: 0x07)                          */
33794  #define R_ACMPLP_COMPSEL0_IVCMP0_Pos    (0UL)    /*!< IVCMP0 (Bit 0)                                        */
33795  #define R_ACMPLP_COMPSEL0_IVCMP0_Msk    (0x7UL)  /*!< IVCMP0 (Bitfield-Mask: 0x07)                          */
33796 /* =======================================================  COMPSEL1  ======================================================== */
33797  #define R_ACMPLP_COMPSEL1_C1VRF2_Pos    (7UL)    /*!< C1VRF2 (Bit 7)                                        */
33798  #define R_ACMPLP_COMPSEL1_C1VRF2_Msk    (0x80UL) /*!< C1VRF2 (Bitfield-Mask: 0x01)                          */
33799  #define R_ACMPLP_COMPSEL1_IVREF1_Pos    (4UL)    /*!< IVREF1 (Bit 4)                                        */
33800  #define R_ACMPLP_COMPSEL1_IVREF1_Msk    (0x70UL) /*!< IVREF1 (Bitfield-Mask: 0x07)                          */
33801  #define R_ACMPLP_COMPSEL1_IVREF0_Pos    (0UL)    /*!< IVREF0 (Bit 0)                                        */
33802  #define R_ACMPLP_COMPSEL1_IVREF0_Msk    (0x7UL)  /*!< IVREF0 (Bitfield-Mask: 0x07)                          */
33803 
33804 /* =========================================================================================================================== */
33805 /* ================                                          R_ADC0                                           ================ */
33806 /* =========================================================================================================================== */
33807 
33808 /* =========================================================  ADCSR  ========================================================= */
33809  #define R_ADC0_ADCSR_ADST_Pos              (15UL)     /*!< ADST (Bit 15)                                         */
33810  #define R_ADC0_ADCSR_ADST_Msk              (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01)                            */
33811  #define R_ADC0_ADCSR_ADCS_Pos              (13UL)     /*!< ADCS (Bit 13)                                         */
33812  #define R_ADC0_ADCSR_ADCS_Msk              (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03)                            */
33813  #define R_ADC0_ADCSR_ADHSC_Pos             (10UL)     /*!< ADHSC (Bit 10)                                        */
33814  #define R_ADC0_ADCSR_ADHSC_Msk             (0x400UL)  /*!< ADHSC (Bitfield-Mask: 0x01)                           */
33815  #define R_ADC0_ADCSR_TRGE_Pos              (9UL)      /*!< TRGE (Bit 9)                                          */
33816  #define R_ADC0_ADCSR_TRGE_Msk              (0x200UL)  /*!< TRGE (Bitfield-Mask: 0x01)                            */
33817  #define R_ADC0_ADCSR_EXTRG_Pos             (8UL)      /*!< EXTRG (Bit 8)                                         */
33818  #define R_ADC0_ADCSR_EXTRG_Msk             (0x100UL)  /*!< EXTRG (Bitfield-Mask: 0x01)                           */
33819  #define R_ADC0_ADCSR_DBLE_Pos              (7UL)      /*!< DBLE (Bit 7)                                          */
33820  #define R_ADC0_ADCSR_DBLE_Msk              (0x80UL)   /*!< DBLE (Bitfield-Mask: 0x01)                            */
33821  #define R_ADC0_ADCSR_GBADIE_Pos            (6UL)      /*!< GBADIE (Bit 6)                                        */
33822  #define R_ADC0_ADCSR_GBADIE_Msk            (0x40UL)   /*!< GBADIE (Bitfield-Mask: 0x01)                          */
33823  #define R_ADC0_ADCSR_DBLANS_Pos            (0UL)      /*!< DBLANS (Bit 0)                                        */
33824  #define R_ADC0_ADCSR_DBLANS_Msk            (0x1fUL)   /*!< DBLANS (Bitfield-Mask: 0x1f)                          */
33825  #define R_ADC0_ADCSR_ADIE_Pos              (12UL)     /*!< ADIE (Bit 12)                                         */
33826  #define R_ADC0_ADCSR_ADIE_Msk              (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01)                            */
33827 /* ========================================================  ADANSA  ========================================================= */
33828  #define R_ADC0_ADANSA_ANSA_Pos             (0UL)      /*!< ANSA (Bit 0)                                          */
33829  #define R_ADC0_ADANSA_ANSA_Msk             (0x1UL)    /*!< ANSA (Bitfield-Mask: 0x01)                            */
33830 /* =========================================================  ADADS  ========================================================= */
33831  #define R_ADC0_ADADS_ADS_Pos               (0UL)      /*!< ADS (Bit 0)                                           */
33832  #define R_ADC0_ADADS_ADS_Msk               (0x1UL)    /*!< ADS (Bitfield-Mask: 0x01)                             */
33833 /* =========================================================  ADADC  ========================================================= */
33834  #define R_ADC0_ADADC_ADC_Pos               (0UL)      /*!< ADC (Bit 0)                                           */
33835  #define R_ADC0_ADADC_ADC_Msk               (0x7UL)    /*!< ADC (Bitfield-Mask: 0x07)                             */
33836  #define R_ADC0_ADADC_AVEE_Pos              (7UL)      /*!< AVEE (Bit 7)                                          */
33837  #define R_ADC0_ADADC_AVEE_Msk              (0x80UL)   /*!< AVEE (Bitfield-Mask: 0x01)                            */
33838 /* =========================================================  ADCER  ========================================================= */
33839  #define R_ADC0_ADCER_ADRFMT_Pos            (15UL)     /*!< ADRFMT (Bit 15)                                       */
33840  #define R_ADC0_ADCER_ADRFMT_Msk            (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01)                          */
33841  #define R_ADC0_ADCER_ADINV_Pos             (14UL)     /*!< ADINV (Bit 14)                                        */
33842  #define R_ADC0_ADCER_ADINV_Msk             (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01)                           */
33843  #define R_ADC0_ADCER_DIAGM_Pos             (11UL)     /*!< DIAGM (Bit 11)                                        */
33844  #define R_ADC0_ADCER_DIAGM_Msk             (0x800UL)  /*!< DIAGM (Bitfield-Mask: 0x01)                           */
33845  #define R_ADC0_ADCER_DIAGLD_Pos            (10UL)     /*!< DIAGLD (Bit 10)                                       */
33846  #define R_ADC0_ADCER_DIAGLD_Msk            (0x400UL)  /*!< DIAGLD (Bitfield-Mask: 0x01)                          */
33847  #define R_ADC0_ADCER_DIAGVAL_Pos           (8UL)      /*!< DIAGVAL (Bit 8)                                       */
33848  #define R_ADC0_ADCER_DIAGVAL_Msk           (0x300UL)  /*!< DIAGVAL (Bitfield-Mask: 0x03)                         */
33849  #define R_ADC0_ADCER_ACE_Pos               (5UL)      /*!< ACE (Bit 5)                                           */
33850  #define R_ADC0_ADCER_ACE_Msk               (0x20UL)   /*!< ACE (Bitfield-Mask: 0x01)                             */
33851  #define R_ADC0_ADCER_ADPRC_Pos             (1UL)      /*!< ADPRC (Bit 1)                                         */
33852  #define R_ADC0_ADCER_ADPRC_Msk             (0x6UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
33853  #define R_ADC0_ADCER_DCE_Pos               (4UL)      /*!< DCE (Bit 4)                                           */
33854  #define R_ADC0_ADCER_DCE_Msk               (0x10UL)   /*!< DCE (Bitfield-Mask: 0x01)                             */
33855 /* ========================================================  ADSTRGR  ======================================================== */
33856  #define R_ADC0_ADSTRGR_TRSA_Pos            (8UL)      /*!< TRSA (Bit 8)                                          */
33857  #define R_ADC0_ADSTRGR_TRSA_Msk            (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f)                            */
33858  #define R_ADC0_ADSTRGR_TRSB_Pos            (0UL)      /*!< TRSB (Bit 0)                                          */
33859  #define R_ADC0_ADSTRGR_TRSB_Msk            (0x3fUL)   /*!< TRSB (Bitfield-Mask: 0x3f)                            */
33860 /* ========================================================  ADEXICR  ======================================================== */
33861  #define R_ADC0_ADEXICR_OCSB_Pos            (11UL)     /*!< OCSB (Bit 11)                                         */
33862  #define R_ADC0_ADEXICR_OCSB_Msk            (0x800UL)  /*!< OCSB (Bitfield-Mask: 0x01)                            */
33863  #define R_ADC0_ADEXICR_TSSB_Pos            (10UL)     /*!< TSSB (Bit 10)                                         */
33864  #define R_ADC0_ADEXICR_TSSB_Msk            (0x400UL)  /*!< TSSB (Bitfield-Mask: 0x01)                            */
33865  #define R_ADC0_ADEXICR_OCSA_Pos            (9UL)      /*!< OCSA (Bit 9)                                          */
33866  #define R_ADC0_ADEXICR_OCSA_Msk            (0x200UL)  /*!< OCSA (Bitfield-Mask: 0x01)                            */
33867  #define R_ADC0_ADEXICR_TSSA_Pos            (8UL)      /*!< TSSA (Bit 8)                                          */
33868  #define R_ADC0_ADEXICR_TSSA_Msk            (0x100UL)  /*!< TSSA (Bitfield-Mask: 0x01)                            */
33869  #define R_ADC0_ADEXICR_OCSAD_Pos           (1UL)      /*!< OCSAD (Bit 1)                                         */
33870  #define R_ADC0_ADEXICR_OCSAD_Msk           (0x2UL)    /*!< OCSAD (Bitfield-Mask: 0x01)                           */
33871  #define R_ADC0_ADEXICR_TSSAD_Pos           (0UL)      /*!< TSSAD (Bit 0)                                         */
33872  #define R_ADC0_ADEXICR_TSSAD_Msk           (0x1UL)    /*!< TSSAD (Bitfield-Mask: 0x01)                           */
33873  #define R_ADC0_ADEXICR_EXSEL_Pos           (14UL)     /*!< EXSEL (Bit 14)                                        */
33874  #define R_ADC0_ADEXICR_EXSEL_Msk           (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01)                           */
33875  #define R_ADC0_ADEXICR_EXOEN_Pos           (15UL)     /*!< EXOEN (Bit 15)                                        */
33876  #define R_ADC0_ADEXICR_EXOEN_Msk           (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01)                           */
33877 /* ========================================================  ADANSB  ========================================================= */
33878  #define R_ADC0_ADANSB_ANSB_Pos             (0UL)      /*!< ANSB (Bit 0)                                          */
33879  #define R_ADC0_ADANSB_ANSB_Msk             (0x1UL)    /*!< ANSB (Bitfield-Mask: 0x01)                            */
33880 /* ========================================================  ADDBLDR  ======================================================== */
33881  #define R_ADC0_ADDBLDR_ADDBLDR_Pos         (0UL)      /*!< ADDBLDR (Bit 0)                                       */
33882  #define R_ADC0_ADDBLDR_ADDBLDR_Msk         (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff)                       */
33883 /* ========================================================  ADTSDR  ========================================================= */
33884  #define R_ADC0_ADTSDR_ADTSDR_Pos           (0UL)      /*!< ADTSDR (Bit 0)                                        */
33885  #define R_ADC0_ADTSDR_ADTSDR_Msk           (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff)                        */
33886 /* ========================================================  ADOCDR  ========================================================= */
33887  #define R_ADC0_ADOCDR_ADOCDR_Pos           (0UL)      /*!< ADOCDR (Bit 0)                                        */
33888  #define R_ADC0_ADOCDR_ADOCDR_Msk           (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff)                        */
33889 /* ======================================================  ADRD_RIGHT  ======================================================= */
33890  #define R_ADC0_ADRD_RIGHT_DIAGST_Pos       (14UL)     /*!< DIAGST (Bit 14)                                       */
33891  #define R_ADC0_ADRD_RIGHT_DIAGST_Msk       (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03)                          */
33892  #define R_ADC0_ADRD_RIGHT_AD_Pos           (0UL)      /*!< AD (Bit 0)                                            */
33893  #define R_ADC0_ADRD_RIGHT_AD_Msk           (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff)                            */
33894 /* =======================================================  ADRD_LEFT  ======================================================= */
33895  #define R_ADC0_ADRD_LEFT_AD_Pos            (2UL)      /*!< AD (Bit 2)                                            */
33896  #define R_ADC0_ADRD_LEFT_AD_Msk            (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff)                            */
33897  #define R_ADC0_ADRD_LEFT_DIAGST_Pos        (0UL)      /*!< DIAGST (Bit 0)                                        */
33898  #define R_ADC0_ADRD_LEFT_DIAGST_Msk        (0x3UL)    /*!< DIAGST (Bitfield-Mask: 0x03)                          */
33899 /* =========================================================  ADDR  ========================================================== */
33900  #define R_ADC0_ADDR_ADDR_Pos               (0UL)      /*!< ADDR (Bit 0)                                          */
33901  #define R_ADC0_ADDR_ADDR_Msk               (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff)                          */
33902 /* ========================================================  ADSHCR  ========================================================= */
33903  #define R_ADC0_ADSHCR_SHANS2_Pos           (10UL)     /*!< SHANS2 (Bit 10)                                       */
33904  #define R_ADC0_ADSHCR_SHANS2_Msk           (0x400UL)  /*!< SHANS2 (Bitfield-Mask: 0x01)                          */
33905  #define R_ADC0_ADSHCR_SHANS1_Pos           (9UL)      /*!< SHANS1 (Bit 9)                                        */
33906  #define R_ADC0_ADSHCR_SHANS1_Msk           (0x200UL)  /*!< SHANS1 (Bitfield-Mask: 0x01)                          */
33907  #define R_ADC0_ADSHCR_SHANS0_Pos           (8UL)      /*!< SHANS0 (Bit 8)                                        */
33908  #define R_ADC0_ADSHCR_SHANS0_Msk           (0x100UL)  /*!< SHANS0 (Bitfield-Mask: 0x01)                          */
33909  #define R_ADC0_ADSHCR_SSTSH_Pos            (0UL)      /*!< SSTSH (Bit 0)                                         */
33910  #define R_ADC0_ADSHCR_SSTSH_Msk            (0xffUL)   /*!< SSTSH (Bitfield-Mask: 0xff)                           */
33911 /* ========================================================  ADDISCR  ======================================================== */
33912  #define R_ADC0_ADDISCR_CHARGE_Pos          (4UL)      /*!< CHARGE (Bit 4)                                        */
33913  #define R_ADC0_ADDISCR_CHARGE_Msk          (0x10UL)   /*!< CHARGE (Bitfield-Mask: 0x01)                          */
33914  #define R_ADC0_ADDISCR_ADNDIS_Pos          (0UL)      /*!< ADNDIS (Bit 0)                                        */
33915  #define R_ADC0_ADDISCR_ADNDIS_Msk          (0xfUL)    /*!< ADNDIS (Bitfield-Mask: 0x0f)                          */
33916 /* ========================================================  ADSHMSR  ======================================================== */
33917  #define R_ADC0_ADSHMSR_SHMD_Pos            (0UL)      /*!< SHMD (Bit 0)                                          */
33918  #define R_ADC0_ADSHMSR_SHMD_Msk            (0x1UL)    /*!< SHMD (Bitfield-Mask: 0x01)                            */
33919 /* ========================================================  ADACSR  ========================================================= */
33920  #define R_ADC0_ADACSR_ADSAC_Pos            (1UL)      /*!< ADSAC (Bit 1)                                         */
33921  #define R_ADC0_ADACSR_ADSAC_Msk            (0x2UL)    /*!< ADSAC (Bitfield-Mask: 0x01)                           */
33922 /* ========================================================  ADGSPCR  ======================================================== */
33923  #define R_ADC0_ADGSPCR_GBRP_Pos            (15UL)     /*!< GBRP (Bit 15)                                         */
33924  #define R_ADC0_ADGSPCR_GBRP_Msk            (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01)                            */
33925  #define R_ADC0_ADGSPCR_GBRSCN_Pos          (1UL)      /*!< GBRSCN (Bit 1)                                        */
33926  #define R_ADC0_ADGSPCR_GBRSCN_Msk          (0x2UL)    /*!< GBRSCN (Bitfield-Mask: 0x01)                          */
33927  #define R_ADC0_ADGSPCR_PGS_Pos             (0UL)      /*!< PGS (Bit 0)                                           */
33928  #define R_ADC0_ADGSPCR_PGS_Msk             (0x1UL)    /*!< PGS (Bitfield-Mask: 0x01)                             */
33929  #define R_ADC0_ADGSPCR_GBEXTRG_Pos         (8UL)      /*!< GBEXTRG (Bit 8)                                       */
33930  #define R_ADC0_ADGSPCR_GBEXTRG_Msk         (0x100UL)  /*!< GBEXTRG (Bitfield-Mask: 0x01)                         */
33931 /* =========================================================  ADICR  ========================================================= */
33932  #define R_ADC0_ADICR_ADIC_Pos              (0UL)      /*!< ADIC (Bit 0)                                          */
33933  #define R_ADC0_ADICR_ADIC_Msk              (0x3UL)    /*!< ADIC (Bitfield-Mask: 0x03)                            */
33934 /* =======================================================  ADDBLDRA  ======================================================== */
33935  #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos       (0UL)      /*!< ADDBLDRA (Bit 0)                                      */
33936  #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk       (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff)                      */
33937 /* =======================================================  ADDBLDRB  ======================================================== */
33938  #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos       (0UL)      /*!< ADDBLDRB (Bit 0)                                      */
33939  #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk       (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff)                      */
33940 /* ======================================================  ADHVREFCNT  ======================================================= */
33941  #define R_ADC0_ADHVREFCNT_ADSLP_Pos        (7UL)      /*!< ADSLP (Bit 7)                                         */
33942  #define R_ADC0_ADHVREFCNT_ADSLP_Msk        (0x80UL)   /*!< ADSLP (Bitfield-Mask: 0x01)                           */
33943  #define R_ADC0_ADHVREFCNT_LVSEL_Pos        (4UL)      /*!< LVSEL (Bit 4)                                         */
33944  #define R_ADC0_ADHVREFCNT_LVSEL_Msk        (0x10UL)   /*!< LVSEL (Bitfield-Mask: 0x01)                           */
33945  #define R_ADC0_ADHVREFCNT_HVSEL_Pos        (0UL)      /*!< HVSEL (Bit 0)                                         */
33946  #define R_ADC0_ADHVREFCNT_HVSEL_Msk        (0x3UL)    /*!< HVSEL (Bitfield-Mask: 0x03)                           */
33947 /* =======================================================  ADWINMON  ======================================================== */
33948  #define R_ADC0_ADWINMON_MONCMPB_Pos        (5UL)      /*!< MONCMPB (Bit 5)                                       */
33949  #define R_ADC0_ADWINMON_MONCMPB_Msk        (0x20UL)   /*!< MONCMPB (Bitfield-Mask: 0x01)                         */
33950  #define R_ADC0_ADWINMON_MONCMPA_Pos        (4UL)      /*!< MONCMPA (Bit 4)                                       */
33951  #define R_ADC0_ADWINMON_MONCMPA_Msk        (0x10UL)   /*!< MONCMPA (Bitfield-Mask: 0x01)                         */
33952  #define R_ADC0_ADWINMON_MONCOMB_Pos        (0UL)      /*!< MONCOMB (Bit 0)                                       */
33953  #define R_ADC0_ADWINMON_MONCOMB_Msk        (0x1UL)    /*!< MONCOMB (Bitfield-Mask: 0x01)                         */
33954 /* ========================================================  ADCMPCR  ======================================================== */
33955  #define R_ADC0_ADCMPCR_CMPAIE_Pos          (15UL)     /*!< CMPAIE (Bit 15)                                       */
33956  #define R_ADC0_ADCMPCR_CMPAIE_Msk          (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01)                          */
33957  #define R_ADC0_ADCMPCR_WCMPE_Pos           (14UL)     /*!< WCMPE (Bit 14)                                        */
33958  #define R_ADC0_ADCMPCR_WCMPE_Msk           (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01)                           */
33959  #define R_ADC0_ADCMPCR_CMPBIE_Pos          (13UL)     /*!< CMPBIE (Bit 13)                                       */
33960  #define R_ADC0_ADCMPCR_CMPBIE_Msk          (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01)                          */
33961  #define R_ADC0_ADCMPCR_CMPAE_Pos           (11UL)     /*!< CMPAE (Bit 11)                                        */
33962  #define R_ADC0_ADCMPCR_CMPAE_Msk           (0x800UL)  /*!< CMPAE (Bitfield-Mask: 0x01)                           */
33963  #define R_ADC0_ADCMPCR_CMPBE_Pos           (9UL)      /*!< CMPBE (Bit 9)                                         */
33964  #define R_ADC0_ADCMPCR_CMPBE_Msk           (0x200UL)  /*!< CMPBE (Bitfield-Mask: 0x01)                           */
33965  #define R_ADC0_ADCMPCR_CMPAB_Pos           (0UL)      /*!< CMPAB (Bit 0)                                         */
33966  #define R_ADC0_ADCMPCR_CMPAB_Msk           (0x3UL)    /*!< CMPAB (Bitfield-Mask: 0x03)                           */
33967 /* ======================================================  ADCMPANSER  ======================================================= */
33968  #define R_ADC0_ADCMPANSER_CMPOCA_Pos       (1UL)      /*!< CMPOCA (Bit 1)                                        */
33969  #define R_ADC0_ADCMPANSER_CMPOCA_Msk       (0x2UL)    /*!< CMPOCA (Bitfield-Mask: 0x01)                          */
33970  #define R_ADC0_ADCMPANSER_CMPTSA_Pos       (0UL)      /*!< CMPTSA (Bit 0)                                        */
33971  #define R_ADC0_ADCMPANSER_CMPTSA_Msk       (0x1UL)    /*!< CMPTSA (Bitfield-Mask: 0x01)                          */
33972 /* =======================================================  ADCMPLER  ======================================================== */
33973  #define R_ADC0_ADCMPLER_CMPLOCA_Pos        (1UL)      /*!< CMPLOCA (Bit 1)                                       */
33974  #define R_ADC0_ADCMPLER_CMPLOCA_Msk        (0x2UL)    /*!< CMPLOCA (Bitfield-Mask: 0x01)                         */
33975  #define R_ADC0_ADCMPLER_CMPLTSA_Pos        (0UL)      /*!< CMPLTSA (Bit 0)                                       */
33976  #define R_ADC0_ADCMPLER_CMPLTSA_Msk        (0x1UL)    /*!< CMPLTSA (Bitfield-Mask: 0x01)                         */
33977 /* =======================================================  ADCMPANSR  ======================================================= */
33978  #define R_ADC0_ADCMPANSR_CMPCHA_Pos        (0UL)      /*!< CMPCHA (Bit 0)                                        */
33979  #define R_ADC0_ADCMPANSR_CMPCHA_Msk        (0x1UL)    /*!< CMPCHA (Bitfield-Mask: 0x01)                          */
33980 /* ========================================================  ADCMPLR  ======================================================== */
33981  #define R_ADC0_ADCMPLR_CMPLCHA_Pos         (0UL)      /*!< CMPLCHA (Bit 0)                                       */
33982  #define R_ADC0_ADCMPLR_CMPLCHA_Msk         (0x1UL)    /*!< CMPLCHA (Bitfield-Mask: 0x01)                         */
33983 /* =======================================================  ADCMPDR0  ======================================================== */
33984  #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos       (0UL)      /*!< ADCMPDR0 (Bit 0)                                      */
33985  #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk       (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff)                      */
33986 /* =======================================================  ADCMPDR1  ======================================================== */
33987  #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos       (0UL)      /*!< ADCMPDR1 (Bit 0)                                      */
33988  #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk       (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff)                      */
33989 /* ========================================================  ADCMPSR  ======================================================== */
33990  #define R_ADC0_ADCMPSR_CMPSTCHA_Pos        (0UL)      /*!< CMPSTCHA (Bit 0)                                      */
33991  #define R_ADC0_ADCMPSR_CMPSTCHA_Msk        (0x1UL)    /*!< CMPSTCHA (Bitfield-Mask: 0x01)                        */
33992 /* =======================================================  ADCMPSER  ======================================================== */
33993  #define R_ADC0_ADCMPSER_CMPSTOCA_Pos       (1UL)      /*!< CMPSTOCA (Bit 1)                                      */
33994  #define R_ADC0_ADCMPSER_CMPSTOCA_Msk       (0x2UL)    /*!< CMPSTOCA (Bitfield-Mask: 0x01)                        */
33995  #define R_ADC0_ADCMPSER_CMPSTTSA_Pos       (0UL)      /*!< CMPSTTSA (Bit 0)                                      */
33996  #define R_ADC0_ADCMPSER_CMPSTTSA_Msk       (0x1UL)    /*!< CMPSTTSA (Bitfield-Mask: 0x01)                        */
33997 /* =======================================================  ADCMPBNSR  ======================================================= */
33998  #define R_ADC0_ADCMPBNSR_CMPLB_Pos         (7UL)      /*!< CMPLB (Bit 7)                                         */
33999  #define R_ADC0_ADCMPBNSR_CMPLB_Msk         (0x80UL)   /*!< CMPLB (Bitfield-Mask: 0x01)                           */
34000  #define R_ADC0_ADCMPBNSR_CMPCHB_Pos        (0UL)      /*!< CMPCHB (Bit 0)                                        */
34001  #define R_ADC0_ADCMPBNSR_CMPCHB_Msk        (0x3fUL)   /*!< CMPCHB (Bitfield-Mask: 0x3f)                          */
34002 /* =======================================================  ADWINLLB  ======================================================== */
34003  #define R_ADC0_ADWINLLB_ADWINLLB_Pos       (0UL)      /*!< ADWINLLB (Bit 0)                                      */
34004  #define R_ADC0_ADWINLLB_ADWINLLB_Msk       (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff)                      */
34005 /* =======================================================  ADWINULB  ======================================================== */
34006  #define R_ADC0_ADWINULB_ADWINULB_Pos       (0UL)      /*!< ADWINULB (Bit 0)                                      */
34007  #define R_ADC0_ADWINULB_ADWINULB_Msk       (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff)                      */
34008 /* =======================================================  ADCMPBSR  ======================================================== */
34009  #define R_ADC0_ADCMPBSR_CMPSTB_Pos         (0UL)      /*!< CMPSTB (Bit 0)                                        */
34010  #define R_ADC0_ADCMPBSR_CMPSTB_Msk         (0x1UL)    /*!< CMPSTB (Bitfield-Mask: 0x01)                          */
34011 /* ========================================================  ADSSTRL  ======================================================== */
34012  #define R_ADC0_ADSSTRL_SST_Pos             (0UL)      /*!< SST (Bit 0)                                           */
34013  #define R_ADC0_ADSSTRL_SST_Msk             (0xffUL)   /*!< SST (Bitfield-Mask: 0xff)                             */
34014 /* ========================================================  ADSSTRT  ======================================================== */
34015  #define R_ADC0_ADSSTRT_SST_Pos             (0UL)      /*!< SST (Bit 0)                                           */
34016  #define R_ADC0_ADSSTRT_SST_Msk             (0xffUL)   /*!< SST (Bitfield-Mask: 0xff)                             */
34017 /* ========================================================  ADSSTRO  ======================================================== */
34018  #define R_ADC0_ADSSTRO_SST_Pos             (0UL)      /*!< SST (Bit 0)                                           */
34019  #define R_ADC0_ADSSTRO_SST_Msk             (0xffUL)   /*!< SST (Bitfield-Mask: 0xff)                             */
34020 /* ========================================================  ADSSTR  ========================================================= */
34021  #define R_ADC0_ADSSTR_SST_Pos              (0UL)      /*!< SST (Bit 0)                                           */
34022  #define R_ADC0_ADSSTR_SST_Msk              (0xffUL)   /*!< SST (Bitfield-Mask: 0xff)                             */
34023 /* ========================================================  ADPGACR  ======================================================== */
34024  #define R_ADC0_ADPGACR_P002GEN_Pos         (11UL)     /*!< P002GEN (Bit 11)                                      */
34025  #define R_ADC0_ADPGACR_P002GEN_Msk         (0x800UL)  /*!< P002GEN (Bitfield-Mask: 0x01)                         */
34026  #define R_ADC0_ADPGACR_P002ENAMP_Pos       (10UL)     /*!< P002ENAMP (Bit 10)                                    */
34027  #define R_ADC0_ADPGACR_P002ENAMP_Msk       (0x400UL)  /*!< P002ENAMP (Bitfield-Mask: 0x01)                       */
34028  #define R_ADC0_ADPGACR_P002SEL1_Pos        (9UL)      /*!< P002SEL1 (Bit 9)                                      */
34029  #define R_ADC0_ADPGACR_P002SEL1_Msk        (0x200UL)  /*!< P002SEL1 (Bitfield-Mask: 0x01)                        */
34030  #define R_ADC0_ADPGACR_P002SEL0_Pos        (8UL)      /*!< P002SEL0 (Bit 8)                                      */
34031  #define R_ADC0_ADPGACR_P002SEL0_Msk        (0x100UL)  /*!< P002SEL0 (Bitfield-Mask: 0x01)                        */
34032  #define R_ADC0_ADPGACR_P001GEN_Pos         (7UL)      /*!< P001GEN (Bit 7)                                       */
34033  #define R_ADC0_ADPGACR_P001GEN_Msk         (0x80UL)   /*!< P001GEN (Bitfield-Mask: 0x01)                         */
34034  #define R_ADC0_ADPGACR_P001ENAMP_Pos       (6UL)      /*!< P001ENAMP (Bit 6)                                     */
34035  #define R_ADC0_ADPGACR_P001ENAMP_Msk       (0x40UL)   /*!< P001ENAMP (Bitfield-Mask: 0x01)                       */
34036  #define R_ADC0_ADPGACR_P001SEL1_Pos        (5UL)      /*!< P001SEL1 (Bit 5)                                      */
34037  #define R_ADC0_ADPGACR_P001SEL1_Msk        (0x20UL)   /*!< P001SEL1 (Bitfield-Mask: 0x01)                        */
34038  #define R_ADC0_ADPGACR_P001SEL0_Pos        (4UL)      /*!< P001SEL0 (Bit 4)                                      */
34039  #define R_ADC0_ADPGACR_P001SEL0_Msk        (0x10UL)   /*!< P001SEL0 (Bitfield-Mask: 0x01)                        */
34040  #define R_ADC0_ADPGACR_P000GEN_Pos         (3UL)      /*!< P000GEN (Bit 3)                                       */
34041  #define R_ADC0_ADPGACR_P000GEN_Msk         (0x8UL)    /*!< P000GEN (Bitfield-Mask: 0x01)                         */
34042  #define R_ADC0_ADPGACR_P000ENAMP_Pos       (2UL)      /*!< P000ENAMP (Bit 2)                                     */
34043  #define R_ADC0_ADPGACR_P000ENAMP_Msk       (0x4UL)    /*!< P000ENAMP (Bitfield-Mask: 0x01)                       */
34044  #define R_ADC0_ADPGACR_P000SEL1_Pos        (1UL)      /*!< P000SEL1 (Bit 1)                                      */
34045  #define R_ADC0_ADPGACR_P000SEL1_Msk        (0x2UL)    /*!< P000SEL1 (Bitfield-Mask: 0x01)                        */
34046  #define R_ADC0_ADPGACR_P000SEL0_Pos        (0UL)      /*!< P000SEL0 (Bit 0)                                      */
34047  #define R_ADC0_ADPGACR_P000SEL0_Msk        (0x1UL)    /*!< P000SEL0 (Bitfield-Mask: 0x01)                        */
34048  #define R_ADC0_ADPGACR_P003SEL0_Pos        (12UL)     /*!< P003SEL0 (Bit 12)                                     */
34049  #define R_ADC0_ADPGACR_P003SEL0_Msk        (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01)                        */
34050  #define R_ADC0_ADPGACR_P003SEL1_Pos        (13UL)     /*!< P003SEL1 (Bit 13)                                     */
34051  #define R_ADC0_ADPGACR_P003SEL1_Msk        (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01)                        */
34052  #define R_ADC0_ADPGACR_P003ENAMP_Pos       (14UL)     /*!< P003ENAMP (Bit 14)                                    */
34053  #define R_ADC0_ADPGACR_P003ENAMP_Msk       (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01)                       */
34054  #define R_ADC0_ADPGACR_P003GEN_Pos         (15UL)     /*!< P003GEN (Bit 15)                                      */
34055  #define R_ADC0_ADPGACR_P003GEN_Msk         (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01)                         */
34056 /* =========================================================  ADRD  ========================================================== */
34057  #define R_ADC0_ADRD_AD_Pos                 (0UL)      /*!< AD (Bit 0)                                            */
34058  #define R_ADC0_ADRD_AD_Msk                 (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff)                            */
34059 /* =========================================================  ADRST  ========================================================= */
34060  #define R_ADC0_ADRST_DIAGST_Pos            (0UL)      /*!< DIAGST (Bit 0)                                        */
34061  #define R_ADC0_ADRST_DIAGST_Msk            (0x3UL)    /*!< DIAGST (Bitfield-Mask: 0x03)                          */
34062 /* ======================================================  VREFAMPCNT  ======================================================= */
34063  #define R_ADC0_VREFAMPCNT_VREFADCG_Pos     (1UL)      /*!< VREFADCG (Bit 1)                                      */
34064  #define R_ADC0_VREFAMPCNT_VREFADCG_Msk     (0x6UL)    /*!< VREFADCG (Bitfield-Mask: 0x03)                        */
34065  #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos    (3UL)      /*!< VREFADCEN (Bit 3)                                     */
34066  #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk    (0x8UL)    /*!< VREFADCEN (Bitfield-Mask: 0x01)                       */
34067  #define R_ADC0_VREFAMPCNT_ADSLP_Pos        (7UL)      /*!< ADSLP (Bit 7)                                         */
34068  #define R_ADC0_VREFAMPCNT_ADSLP_Msk        (0x80UL)   /*!< ADSLP (Bitfield-Mask: 0x01)                           */
34069  #define R_ADC0_VREFAMPCNT_OLDETEN_Pos      (0UL)      /*!< OLDETEN (Bit 0)                                       */
34070  #define R_ADC0_VREFAMPCNT_OLDETEN_Msk      (0x1UL)    /*!< OLDETEN (Bitfield-Mask: 0x01)                         */
34071  #define R_ADC0_VREFAMPCNT_BGREN_Pos        (4UL)      /*!< BGREN (Bit 4)                                         */
34072  #define R_ADC0_VREFAMPCNT_BGREN_Msk        (0x10UL)   /*!< BGREN (Bitfield-Mask: 0x01)                           */
34073 /* =======================================================  ADCALEXE  ======================================================== */
34074  #define R_ADC0_ADCALEXE_CALEXE_Pos         (7UL)      /*!< CALEXE (Bit 7)                                        */
34075  #define R_ADC0_ADCALEXE_CALEXE_Msk         (0x80UL)   /*!< CALEXE (Bitfield-Mask: 0x01)                          */
34076  #define R_ADC0_ADCALEXE_CALMON_Pos         (6UL)      /*!< CALMON (Bit 6)                                        */
34077  #define R_ADC0_ADCALEXE_CALMON_Msk         (0x40UL)   /*!< CALMON (Bitfield-Mask: 0x01)                          */
34078 /* ========================================================  ADANIM  ========================================================= */
34079  #define R_ADC0_ADANIM_ANIM_Pos             (0UL)      /*!< ANIM (Bit 0)                                          */
34080  #define R_ADC0_ADANIM_ANIM_Msk             (0x1UL)    /*!< ANIM (Bitfield-Mask: 0x01)                            */
34081 /* =======================================================  ADPGAGS0  ======================================================== */
34082  #define R_ADC0_ADPGAGS0_P002GAIN_Pos       (8UL)      /*!< P002GAIN (Bit 8)                                      */
34083  #define R_ADC0_ADPGAGS0_P002GAIN_Msk       (0xf00UL)  /*!< P002GAIN (Bitfield-Mask: 0x0f)                        */
34084  #define R_ADC0_ADPGAGS0_P001GAIN_Pos       (4UL)      /*!< P001GAIN (Bit 4)                                      */
34085  #define R_ADC0_ADPGAGS0_P001GAIN_Msk       (0xf0UL)   /*!< P001GAIN (Bitfield-Mask: 0x0f)                        */
34086  #define R_ADC0_ADPGAGS0_P000GAIN_Pos       (0UL)      /*!< P000GAIN (Bit 0)                                      */
34087  #define R_ADC0_ADPGAGS0_P000GAIN_Msk       (0xfUL)    /*!< P000GAIN (Bitfield-Mask: 0x0f)                        */
34088  #define R_ADC0_ADPGAGS0_P003GAIN_Pos       (12UL)     /*!< P003GAIN (Bit 12)                                     */
34089  #define R_ADC0_ADPGAGS0_P003GAIN_Msk       (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f)                        */
34090 /* =======================================================  ADPGADCR0  ======================================================= */
34091  #define R_ADC0_ADPGADCR0_P003DG_Pos        (12UL)     /*!< P003DG (Bit 12)                                       */
34092  #define R_ADC0_ADPGADCR0_P003DG_Msk        (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03)                          */
34093  #define R_ADC0_ADPGADCR0_P002DEN_Pos       (11UL)     /*!< P002DEN (Bit 11)                                      */
34094  #define R_ADC0_ADPGADCR0_P002DEN_Msk       (0x800UL)  /*!< P002DEN (Bitfield-Mask: 0x01)                         */
34095  #define R_ADC0_ADPGADCR0_P002DG_Pos        (8UL)      /*!< P002DG (Bit 8)                                        */
34096  #define R_ADC0_ADPGADCR0_P002DG_Msk        (0x300UL)  /*!< P002DG (Bitfield-Mask: 0x03)                          */
34097  #define R_ADC0_ADPGADCR0_P001DEN_Pos       (7UL)      /*!< P001DEN (Bit 7)                                       */
34098  #define R_ADC0_ADPGADCR0_P001DEN_Msk       (0x80UL)   /*!< P001DEN (Bitfield-Mask: 0x01)                         */
34099  #define R_ADC0_ADPGADCR0_P001DG_Pos        (4UL)      /*!< P001DG (Bit 4)                                        */
34100  #define R_ADC0_ADPGADCR0_P001DG_Msk        (0x30UL)   /*!< P001DG (Bitfield-Mask: 0x03)                          */
34101  #define R_ADC0_ADPGADCR0_P000DEN_Pos       (3UL)      /*!< P000DEN (Bit 3)                                       */
34102  #define R_ADC0_ADPGADCR0_P000DEN_Msk       (0x8UL)    /*!< P000DEN (Bitfield-Mask: 0x01)                         */
34103  #define R_ADC0_ADPGADCR0_P000DG_Pos        (0UL)      /*!< P000DG (Bit 0)                                        */
34104  #define R_ADC0_ADPGADCR0_P000DG_Msk        (0x3UL)    /*!< P000DG (Bitfield-Mask: 0x03)                          */
34105  #define R_ADC0_ADPGADCR0_P003DEN_Pos       (15UL)     /*!< P003DEN (Bit 15)                                      */
34106  #define R_ADC0_ADPGADCR0_P003DEN_Msk       (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01)                         */
34107 /* =========================================================  ADREF  ========================================================= */
34108  #define R_ADC0_ADREF_ADF_Pos               (0UL)      /*!< ADF (Bit 0)                                           */
34109  #define R_ADC0_ADREF_ADF_Msk               (0x1UL)    /*!< ADF (Bitfield-Mask: 0x01)                             */
34110  #define R_ADC0_ADREF_ADSCACT_Pos           (7UL)      /*!< ADSCACT (Bit 7)                                       */
34111  #define R_ADC0_ADREF_ADSCACT_Msk           (0x80UL)   /*!< ADSCACT (Bitfield-Mask: 0x01)                         */
34112 /* ========================================================  ADEXREF  ======================================================== */
34113  #define R_ADC0_ADEXREF_GBADF_Pos           (0UL)      /*!< GBADF (Bit 0)                                         */
34114  #define R_ADC0_ADEXREF_GBADF_Msk           (0x1UL)    /*!< GBADF (Bitfield-Mask: 0x01)                           */
34115 /* =======================================================  ADAMPOFF  ======================================================== */
34116  #define R_ADC0_ADAMPOFF_OPOFF_Pos          (0UL)      /*!< OPOFF (Bit 0)                                         */
34117  #define R_ADC0_ADAMPOFF_OPOFF_Msk          (0xffUL)   /*!< OPOFF (Bitfield-Mask: 0xff)                           */
34118 /* ========================================================  ADTSTPR  ======================================================== */
34119  #define R_ADC0_ADTSTPR_PRO_Pos             (0UL)      /*!< PRO (Bit 0)                                           */
34120  #define R_ADC0_ADTSTPR_PRO_Msk             (0x1UL)    /*!< PRO (Bitfield-Mask: 0x01)                             */
34121  #define R_ADC0_ADTSTPR_B0WI_Pos            (1UL)      /*!< B0WI (Bit 1)                                          */
34122  #define R_ADC0_ADTSTPR_B0WI_Msk            (0x2UL)    /*!< B0WI (Bitfield-Mask: 0x01)                            */
34123 /* =======================================================  ADDDACER  ======================================================== */
34124  #define R_ADC0_ADDDACER_WRION_Pos          (0UL)      /*!< WRION (Bit 0)                                         */
34125  #define R_ADC0_ADDDACER_WRION_Msk          (0x1fUL)   /*!< WRION (Bitfield-Mask: 0x1f)                           */
34126  #define R_ADC0_ADDDACER_WRIOFF_Pos         (8UL)      /*!< WRIOFF (Bit 8)                                        */
34127  #define R_ADC0_ADDDACER_WRIOFF_Msk         (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f)                          */
34128  #define R_ADC0_ADDDACER_ADHS_Pos           (15UL)     /*!< ADHS (Bit 15)                                         */
34129  #define R_ADC0_ADDDACER_ADHS_Msk           (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01)                            */
34130 /* =======================================================  ADEXTSTR  ======================================================== */
34131  #define R_ADC0_ADEXTSTR_SHTEST_Pos         (0UL)      /*!< SHTEST (Bit 0)                                        */
34132  #define R_ADC0_ADEXTSTR_SHTEST_Msk         (0x7UL)    /*!< SHTEST (Bitfield-Mask: 0x07)                          */
34133  #define R_ADC0_ADEXTSTR_SWTST_Pos          (4UL)      /*!< SWTST (Bit 4)                                         */
34134  #define R_ADC0_ADEXTSTR_SWTST_Msk          (0x30UL)   /*!< SWTST (Bitfield-Mask: 0x03)                           */
34135  #define R_ADC0_ADEXTSTR_SHTRM_Pos          (8UL)      /*!< SHTRM (Bit 8)                                         */
34136  #define R_ADC0_ADEXTSTR_SHTRM_Msk          (0x300UL)  /*!< SHTRM (Bitfield-Mask: 0x03)                           */
34137  #define R_ADC0_ADEXTSTR_ADTRM3_Pos         (11UL)     /*!< ADTRM3 (Bit 11)                                       */
34138  #define R_ADC0_ADEXTSTR_ADTRM3_Msk         (0x800UL)  /*!< ADTRM3 (Bitfield-Mask: 0x01)                          */
34139  #define R_ADC0_ADEXTSTR_ADTRM2_Pos         (12UL)     /*!< ADTRM2 (Bit 12)                                       */
34140  #define R_ADC0_ADEXTSTR_ADTRM2_Msk         (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03)                          */
34141  #define R_ADC0_ADEXTSTR_ADTRM1_Pos         (14UL)     /*!< ADTRM1 (Bit 14)                                       */
34142  #define R_ADC0_ADEXTSTR_ADTRM1_Msk         (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03)                          */
34143 /* ========================================================  ADTSTRA  ======================================================== */
34144  #define R_ADC0_ADTSTRA_ATBUSSEL_Pos        (0UL)      /*!< ATBUSSEL (Bit 0)                                      */
34145  #define R_ADC0_ADTSTRA_ATBUSSEL_Msk        (0x1UL)    /*!< ATBUSSEL (Bitfield-Mask: 0x01)                        */
34146  #define R_ADC0_ADTSTRA_TSTSWREF_Pos        (1UL)      /*!< TSTSWREF (Bit 1)                                      */
34147  #define R_ADC0_ADTSTRA_TSTSWREF_Msk        (0xeUL)    /*!< TSTSWREF (Bitfield-Mask: 0x07)                        */
34148  #define R_ADC0_ADTSTRA_OCSW_Pos            (5UL)      /*!< OCSW (Bit 5)                                          */
34149  #define R_ADC0_ADTSTRA_OCSW_Msk            (0x20UL)   /*!< OCSW (Bitfield-Mask: 0x01)                            */
34150  #define R_ADC0_ADTSTRA_TSSW_Pos            (6UL)      /*!< TSSW (Bit 6)                                          */
34151  #define R_ADC0_ADTSTRA_TSSW_Msk            (0x40UL)   /*!< TSSW (Bitfield-Mask: 0x01)                            */
34152  #define R_ADC0_ADTSTRA_ADTEST_AD_Pos       (8UL)      /*!< ADTEST_AD (Bit 8)                                     */
34153  #define R_ADC0_ADTSTRA_ADTEST_AD_Msk       (0xf00UL)  /*!< ADTEST_AD (Bitfield-Mask: 0x0f)                       */
34154  #define R_ADC0_ADTSTRA_ADTEST_IO_Pos       (12UL)     /*!< ADTEST_IO (Bit 12)                                    */
34155  #define R_ADC0_ADTSTRA_ADTEST_IO_Msk       (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f)                       */
34156 /* ========================================================  ADTSTRB  ======================================================== */
34157  #define R_ADC0_ADTSTRB_ADVAL_Pos           (0UL)      /*!< ADVAL (Bit 0)                                         */
34158  #define R_ADC0_ADTSTRB_ADVAL_Msk           (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff)                         */
34159 /* ========================================================  ADTSTRC  ======================================================== */
34160  #define R_ADC0_ADTSTRC_ADMD_Pos            (0UL)      /*!< ADMD (Bit 0)                                          */
34161  #define R_ADC0_ADTSTRC_ADMD_Msk            (0xffUL)   /*!< ADMD (Bitfield-Mask: 0xff)                            */
34162  #define R_ADC0_ADTSTRC_SYNCERR_Pos         (12UL)     /*!< SYNCERR (Bit 12)                                      */
34163  #define R_ADC0_ADTSTRC_SYNCERR_Msk         (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01)                         */
34164 /* ========================================================  ADTSTRD  ======================================================== */
34165  #define R_ADC0_ADTSTRD_ADVAL16_Pos         (0UL)      /*!< ADVAL16 (Bit 0)                                       */
34166  #define R_ADC0_ADTSTRD_ADVAL16_Msk         (0x1UL)    /*!< ADVAL16 (Bitfield-Mask: 0x01)                         */
34167 /* =======================================================  ADSWTSTR0  ======================================================= */
34168  #define R_ADC0_ADSWTSTR0_CHSW00_Pos        (0UL)      /*!< CHSW00 (Bit 0)                                        */
34169  #define R_ADC0_ADSWTSTR0_CHSW00_Msk        (0x1UL)    /*!< CHSW00 (Bitfield-Mask: 0x01)                          */
34170  #define R_ADC0_ADSWTSTR0_CHSW01_Pos        (1UL)      /*!< CHSW01 (Bit 1)                                        */
34171  #define R_ADC0_ADSWTSTR0_CHSW01_Msk        (0x2UL)    /*!< CHSW01 (Bitfield-Mask: 0x01)                          */
34172  #define R_ADC0_ADSWTSTR0_CHSW02_Pos        (2UL)      /*!< CHSW02 (Bit 2)                                        */
34173  #define R_ADC0_ADSWTSTR0_CHSW02_Msk        (0x4UL)    /*!< CHSW02 (Bitfield-Mask: 0x01)                          */
34174  #define R_ADC0_ADSWTSTR0_CHSW03_Pos        (3UL)      /*!< CHSW03 (Bit 3)                                        */
34175  #define R_ADC0_ADSWTSTR0_CHSW03_Msk        (0x8UL)    /*!< CHSW03 (Bitfield-Mask: 0x01)                          */
34176  #define R_ADC0_ADSWTSTR0_CHSW04_Pos        (4UL)      /*!< CHSW04 (Bit 4)                                        */
34177  #define R_ADC0_ADSWTSTR0_CHSW04_Msk        (0x10UL)   /*!< CHSW04 (Bitfield-Mask: 0x01)                          */
34178  #define R_ADC0_ADSWTSTR0_CHSW05_Pos        (5UL)      /*!< CHSW05 (Bit 5)                                        */
34179  #define R_ADC0_ADSWTSTR0_CHSW05_Msk        (0x20UL)   /*!< CHSW05 (Bitfield-Mask: 0x01)                          */
34180 /* =======================================================  ADSWTSTR1  ======================================================= */
34181  #define R_ADC0_ADSWTSTR1_CHSW16_Pos        (0UL)      /*!< CHSW16 (Bit 0)                                        */
34182  #define R_ADC0_ADSWTSTR1_CHSW16_Msk        (0x1UL)    /*!< CHSW16 (Bitfield-Mask: 0x01)                          */
34183  #define R_ADC0_ADSWTSTR1_CHSW17_Pos        (1UL)      /*!< CHSW17 (Bit 1)                                        */
34184  #define R_ADC0_ADSWTSTR1_CHSW17_Msk        (0x2UL)    /*!< CHSW17 (Bitfield-Mask: 0x01)                          */
34185  #define R_ADC0_ADSWTSTR1_CHSW18_Pos        (2UL)      /*!< CHSW18 (Bit 2)                                        */
34186  #define R_ADC0_ADSWTSTR1_CHSW18_Msk        (0x4UL)    /*!< CHSW18 (Bitfield-Mask: 0x01)                          */
34187  #define R_ADC0_ADSWTSTR1_CHSW19_Pos        (3UL)      /*!< CHSW19 (Bit 3)                                        */
34188  #define R_ADC0_ADSWTSTR1_CHSW19_Msk        (0x8UL)    /*!< CHSW19 (Bitfield-Mask: 0x01)                          */
34189  #define R_ADC0_ADSWTSTR1_CHSW20_Pos        (4UL)      /*!< CHSW20 (Bit 4)                                        */
34190  #define R_ADC0_ADSWTSTR1_CHSW20_Msk        (0x10UL)   /*!< CHSW20 (Bitfield-Mask: 0x01)                          */
34191  #define R_ADC0_ADSWTSTR1_CHSW21_Pos        (5UL)      /*!< CHSW21 (Bit 5)                                        */
34192  #define R_ADC0_ADSWTSTR1_CHSW21_Msk        (0x20UL)   /*!< CHSW21 (Bitfield-Mask: 0x01)                          */
34193 /* =======================================================  ADSWTSTR2  ======================================================= */
34194  #define R_ADC0_ADSWTSTR2_EX0SW_Pos         (0UL)      /*!< EX0SW (Bit 0)                                         */
34195  #define R_ADC0_ADSWTSTR2_EX0SW_Msk         (0x1UL)    /*!< EX0SW (Bitfield-Mask: 0x01)                           */
34196  #define R_ADC0_ADSWTSTR2_EX1SW_Pos         (1UL)      /*!< EX1SW (Bit 1)                                         */
34197  #define R_ADC0_ADSWTSTR2_EX1SW_Msk         (0x2UL)    /*!< EX1SW (Bitfield-Mask: 0x01)                           */
34198  #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos       (4UL)      /*!< SHBYPS0 (Bit 4)                                       */
34199  #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk       (0x10UL)   /*!< SHBYPS0 (Bitfield-Mask: 0x01)                         */
34200  #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos       (5UL)      /*!< SHBYPS1 (Bit 5)                                       */
34201  #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk       (0x20UL)   /*!< SHBYPS1 (Bitfield-Mask: 0x01)                         */
34202  #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos       (6UL)      /*!< SHBYPS2 (Bit 6)                                       */
34203  #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk       (0x40UL)   /*!< SHBYPS2 (Bitfield-Mask: 0x01)                         */
34204  #define R_ADC0_ADSWTSTR2_GRP0SW_Pos        (8UL)      /*!< GRP0SW (Bit 8)                                        */
34205  #define R_ADC0_ADSWTSTR2_GRP0SW_Msk        (0x100UL)  /*!< GRP0SW (Bitfield-Mask: 0x01)                          */
34206  #define R_ADC0_ADSWTSTR2_GRP1SW_Pos        (9UL)      /*!< GRP1SW (Bit 9)                                        */
34207  #define R_ADC0_ADSWTSTR2_GRP1SW_Msk        (0x200UL)  /*!< GRP1SW (Bitfield-Mask: 0x01)                          */
34208  #define R_ADC0_ADSWTSTR2_GRP2SW_Pos        (10UL)     /*!< GRP2SW (Bit 10)                                       */
34209  #define R_ADC0_ADSWTSTR2_GRP2SW_Msk        (0x400UL)  /*!< GRP2SW (Bitfield-Mask: 0x01)                          */
34210  #define R_ADC0_ADSWTSTR2_GRP3SW_Pos        (11UL)     /*!< GRP3SW (Bit 11)                                       */
34211  #define R_ADC0_ADSWTSTR2_GRP3SW_Msk        (0x800UL)  /*!< GRP3SW (Bitfield-Mask: 0x01)                          */
34212  #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos      (12UL)     /*!< GRPEX1SW (Bit 12)                                     */
34213  #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk      (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01)                        */
34214 /* ========================================================  ADSWCR  ========================================================= */
34215  #define R_ADC0_ADSWCR_ADSWREF_Pos          (0UL)      /*!< ADSWREF (Bit 0)                                       */
34216  #define R_ADC0_ADSWCR_ADSWREF_Msk          (0x7UL)    /*!< ADSWREF (Bitfield-Mask: 0x07)                         */
34217  #define R_ADC0_ADSWCR_SHSWREF_Pos          (4UL)      /*!< SHSWREF (Bit 4)                                       */
34218  #define R_ADC0_ADSWCR_SHSWREF_Msk          (0x70UL)   /*!< SHSWREF (Bitfield-Mask: 0x07)                         */
34219 /* ========================================================  ADGSCS  ========================================================= */
34220  #define R_ADC0_ADGSCS_CHSELGB_Pos          (0UL)      /*!< CHSELGB (Bit 0)                                       */
34221  #define R_ADC0_ADGSCS_CHSELGB_Msk          (0xffUL)   /*!< CHSELGB (Bitfield-Mask: 0xff)                         */
34222  #define R_ADC0_ADGSCS_CHSELGA_Pos          (8UL)      /*!< CHSELGA (Bit 8)                                       */
34223  #define R_ADC0_ADGSCS_CHSELGA_Msk          (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff)                         */
34224 /* =========================================================  ADSER  ========================================================= */
34225  #define R_ADC0_ADSER_SMPEX_Pos             (7UL)      /*!< SMPEX (Bit 7)                                         */
34226  #define R_ADC0_ADSER_SMPEX_Msk             (0x80UL)   /*!< SMPEX (Bitfield-Mask: 0x01)                           */
34227 /* ========================================================  ADBUF0  ========================================================= */
34228  #define R_ADC0_ADBUF0_ADBUF_Pos            (0UL)      /*!< ADBUF (Bit 0)                                         */
34229  #define R_ADC0_ADBUF0_ADBUF_Msk            (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
34230 /* ========================================================  ADBUF1  ========================================================= */
34231  #define R_ADC0_ADBUF1_ADBUF_Pos            (0UL)      /*!< ADBUF (Bit 0)                                         */
34232  #define R_ADC0_ADBUF1_ADBUF_Msk            (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
34233 /* ========================================================  ADBUF2  ========================================================= */
34234  #define R_ADC0_ADBUF2_ADBUF_Pos            (0UL)      /*!< ADBUF (Bit 0)                                         */
34235  #define R_ADC0_ADBUF2_ADBUF_Msk            (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
34236 /* ========================================================  ADBUF3  ========================================================= */
34237  #define R_ADC0_ADBUF3_ADBUF_Pos            (0UL)      /*!< ADBUF (Bit 0)                                         */
34238  #define R_ADC0_ADBUF3_ADBUF_Msk            (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
34239 /* ========================================================  ADBUF4  ========================================================= */
34240  #define R_ADC0_ADBUF4_ADBUF_Pos            (0UL)      /*!< ADBUF (Bit 0)                                         */
34241  #define R_ADC0_ADBUF4_ADBUF_Msk            (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
34242 /* ========================================================  ADBUF5  ========================================================= */
34243  #define R_ADC0_ADBUF5_ADBUF_Pos            (0UL)      /*!< ADBUF (Bit 0)                                         */
34244  #define R_ADC0_ADBUF5_ADBUF_Msk            (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
34245 /* ========================================================  ADBUF6  ========================================================= */
34246  #define R_ADC0_ADBUF6_ADBUF_Pos            (0UL)      /*!< ADBUF (Bit 0)                                         */
34247  #define R_ADC0_ADBUF6_ADBUF_Msk            (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
34248 /* ========================================================  ADBUF7  ========================================================= */
34249  #define R_ADC0_ADBUF7_ADBUF_Pos            (0UL)      /*!< ADBUF (Bit 0)                                         */
34250  #define R_ADC0_ADBUF7_ADBUF_Msk            (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
34251 /* ========================================================  ADBUF8  ========================================================= */
34252  #define R_ADC0_ADBUF8_ADBUF_Pos            (0UL)      /*!< ADBUF (Bit 0)                                         */
34253  #define R_ADC0_ADBUF8_ADBUF_Msk            (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
34254 /* ========================================================  ADBUF9  ========================================================= */
34255  #define R_ADC0_ADBUF9_ADBUF_Pos            (0UL)      /*!< ADBUF (Bit 0)                                         */
34256  #define R_ADC0_ADBUF9_ADBUF_Msk            (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
34257 /* ========================================================  ADBUF10  ======================================================== */
34258  #define R_ADC0_ADBUF10_ADBUF_Pos           (0UL)      /*!< ADBUF (Bit 0)                                         */
34259  #define R_ADC0_ADBUF10_ADBUF_Msk           (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
34260 /* ========================================================  ADBUF11  ======================================================== */
34261  #define R_ADC0_ADBUF11_ADBUF_Pos           (0UL)      /*!< ADBUF (Bit 0)                                         */
34262  #define R_ADC0_ADBUF11_ADBUF_Msk           (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
34263 /* ========================================================  ADBUF12  ======================================================== */
34264  #define R_ADC0_ADBUF12_ADBUF_Pos           (0UL)      /*!< ADBUF (Bit 0)                                         */
34265  #define R_ADC0_ADBUF12_ADBUF_Msk           (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
34266 /* ========================================================  ADBUF13  ======================================================== */
34267  #define R_ADC0_ADBUF13_ADBUF_Pos           (0UL)      /*!< ADBUF (Bit 0)                                         */
34268  #define R_ADC0_ADBUF13_ADBUF_Msk           (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
34269 /* ========================================================  ADBUF14  ======================================================== */
34270  #define R_ADC0_ADBUF14_ADBUF_Pos           (0UL)      /*!< ADBUF (Bit 0)                                         */
34271  #define R_ADC0_ADBUF14_ADBUF_Msk           (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
34272 /* ========================================================  ADBUF15  ======================================================== */
34273  #define R_ADC0_ADBUF15_ADBUF_Pos           (0UL)      /*!< ADBUF (Bit 0)                                         */
34274  #define R_ADC0_ADBUF15_ADBUF_Msk           (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
34275 /* ========================================================  ADBUFEN  ======================================================== */
34276  #define R_ADC0_ADBUFEN_BUFEN_Pos           (0UL)      /*!< BUFEN (Bit 0)                                         */
34277  #define R_ADC0_ADBUFEN_BUFEN_Msk           (0x1UL)    /*!< BUFEN (Bitfield-Mask: 0x01)                           */
34278 /* =======================================================  ADBUFPTR  ======================================================== */
34279  #define R_ADC0_ADBUFPTR_BUFPTR_Pos         (0UL)      /*!< BUFPTR (Bit 0)                                        */
34280  #define R_ADC0_ADBUFPTR_BUFPTR_Msk         (0xfUL)    /*!< BUFPTR (Bitfield-Mask: 0x0f)                          */
34281  #define R_ADC0_ADBUFPTR_PTROVF_Pos         (4UL)      /*!< PTROVF (Bit 4)                                        */
34282  #define R_ADC0_ADBUFPTR_PTROVF_Msk         (0x10UL)   /*!< PTROVF (Bitfield-Mask: 0x01)                          */
34283 /* =======================================================  ADPGADBS0  ======================================================= */
34284  #define R_ADC0_ADPGADBS0_P0BIAS_Pos        (0UL)      /*!< P0BIAS (Bit 0)                                        */
34285  #define R_ADC0_ADPGADBS0_P0BIAS_Msk        (0x1UL)    /*!< P0BIAS (Bitfield-Mask: 0x01)                          */
34286 /* =======================================================  ADPGADBS1  ======================================================= */
34287  #define R_ADC0_ADPGADBS1_P3BIAS_Pos        (0UL)      /*!< P3BIAS (Bit 0)                                        */
34288  #define R_ADC0_ADPGADBS1_P3BIAS_Msk        (0x1UL)    /*!< P3BIAS (Bitfield-Mask: 0x01)                          */
34289 /* =======================================================  ADREFMON  ======================================================== */
34290  #define R_ADC0_ADREFMON_PGAMON_Pos         (0UL)      /*!< PGAMON (Bit 0)                                        */
34291  #define R_ADC0_ADREFMON_PGAMON_Msk         (0x7UL)    /*!< PGAMON (Bitfield-Mask: 0x07)                          */
34292 
34293 /* =========================================================================================================================== */
34294 /* ================                                          R_PSCU                                           ================ */
34295 /* =========================================================================================================================== */
34296 
34297 /* =========================================================  PSARB  ========================================================= */
34298  #define R_PSCU_PSARB_PSARB1_Pos     (1UL)          /*!< PSARB1 (Bit 1)                                        */
34299  #define R_PSCU_PSARB_PSARB1_Msk     (0x2UL)        /*!< PSARB1 (Bitfield-Mask: 0x01)                          */
34300  #define R_PSCU_PSARB_PSARB2_Pos     (2UL)          /*!< PSARB2 (Bit 2)                                        */
34301  #define R_PSCU_PSARB_PSARB2_Msk     (0x4UL)        /*!< PSARB2 (Bitfield-Mask: 0x01)                          */
34302  #define R_PSCU_PSARB_PSARB3_Pos     (3UL)          /*!< PSARB3 (Bit 3)                                        */
34303  #define R_PSCU_PSARB_PSARB3_Msk     (0x8UL)        /*!< PSARB3 (Bitfield-Mask: 0x01)                          */
34304  #define R_PSCU_PSARB_PSARB6_Pos     (6UL)          /*!< PSARB6 (Bit 6)                                        */
34305  #define R_PSCU_PSARB_PSARB6_Msk     (0x40UL)       /*!< PSARB6 (Bitfield-Mask: 0x01)                          */
34306  #define R_PSCU_PSARB_PSARB7_Pos     (7UL)          /*!< PSARB7 (Bit 7)                                        */
34307  #define R_PSCU_PSARB_PSARB7_Msk     (0x80UL)       /*!< PSARB7 (Bitfield-Mask: 0x01)                          */
34308  #define R_PSCU_PSARB_PSARB8_Pos     (8UL)          /*!< PSARB8 (Bit 8)                                        */
34309  #define R_PSCU_PSARB_PSARB8_Msk     (0x100UL)      /*!< PSARB8 (Bitfield-Mask: 0x01)                          */
34310  #define R_PSCU_PSARB_PSARB9_Pos     (9UL)          /*!< PSARB9 (Bit 9)                                        */
34311  #define R_PSCU_PSARB_PSARB9_Msk     (0x200UL)      /*!< PSARB9 (Bitfield-Mask: 0x01)                          */
34312  #define R_PSCU_PSARB_PSARB11_Pos    (11UL)         /*!< PSARB11 (Bit 11)                                      */
34313  #define R_PSCU_PSARB_PSARB11_Msk    (0x800UL)      /*!< PSARB11 (Bitfield-Mask: 0x01)                         */
34314  #define R_PSCU_PSARB_PSARB12_Pos    (12UL)         /*!< PSARB12 (Bit 12)                                      */
34315  #define R_PSCU_PSARB_PSARB12_Msk    (0x1000UL)     /*!< PSARB12 (Bitfield-Mask: 0x01)                         */
34316  #define R_PSCU_PSARB_PSARB15_Pos    (15UL)         /*!< PSARB15 (Bit 15)                                      */
34317  #define R_PSCU_PSARB_PSARB15_Msk    (0x8000UL)     /*!< PSARB15 (Bitfield-Mask: 0x01)                         */
34318  #define R_PSCU_PSARB_PSARB16_Pos    (16UL)         /*!< PSARB16 (Bit 16)                                      */
34319  #define R_PSCU_PSARB_PSARB16_Msk    (0x10000UL)    /*!< PSARB16 (Bitfield-Mask: 0x01)                         */
34320  #define R_PSCU_PSARB_PSARB18_Pos    (18UL)         /*!< PSARB18 (Bit 18)                                      */
34321  #define R_PSCU_PSARB_PSARB18_Msk    (0x40000UL)    /*!< PSARB18 (Bitfield-Mask: 0x01)                         */
34322  #define R_PSCU_PSARB_PSARB19_Pos    (19UL)         /*!< PSARB19 (Bit 19)                                      */
34323  #define R_PSCU_PSARB_PSARB19_Msk    (0x80000UL)    /*!< PSARB19 (Bitfield-Mask: 0x01)                         */
34324  #define R_PSCU_PSARB_PSARB22_Pos    (22UL)         /*!< PSARB22 (Bit 22)                                      */
34325  #define R_PSCU_PSARB_PSARB22_Msk    (0x400000UL)   /*!< PSARB22 (Bitfield-Mask: 0x01)                         */
34326  #define R_PSCU_PSARB_PSARB23_Pos    (23UL)         /*!< PSARB23 (Bit 23)                                      */
34327  #define R_PSCU_PSARB_PSARB23_Msk    (0x800000UL)   /*!< PSARB23 (Bitfield-Mask: 0x01)                         */
34328  #define R_PSCU_PSARB_PSARB24_Pos    (24UL)         /*!< PSARB24 (Bit 24)                                      */
34329  #define R_PSCU_PSARB_PSARB24_Msk    (0x1000000UL)  /*!< PSARB24 (Bitfield-Mask: 0x01)                         */
34330  #define R_PSCU_PSARB_PSARB25_Pos    (25UL)         /*!< PSARB25 (Bit 25)                                      */
34331  #define R_PSCU_PSARB_PSARB25_Msk    (0x2000000UL)  /*!< PSARB25 (Bitfield-Mask: 0x01)                         */
34332  #define R_PSCU_PSARB_PSARB26_Pos    (26UL)         /*!< PSARB26 (Bit 26)                                      */
34333  #define R_PSCU_PSARB_PSARB26_Msk    (0x4000000UL)  /*!< PSARB26 (Bitfield-Mask: 0x01)                         */
34334  #define R_PSCU_PSARB_PSARB27_Pos    (27UL)         /*!< PSARB27 (Bit 27)                                      */
34335  #define R_PSCU_PSARB_PSARB27_Msk    (0x8000000UL)  /*!< PSARB27 (Bitfield-Mask: 0x01)                         */
34336  #define R_PSCU_PSARB_PSARB28_Pos    (28UL)         /*!< PSARB28 (Bit 28)                                      */
34337  #define R_PSCU_PSARB_PSARB28_Msk    (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01)                         */
34338  #define R_PSCU_PSARB_PSARB29_Pos    (29UL)         /*!< PSARB29 (Bit 29)                                      */
34339  #define R_PSCU_PSARB_PSARB29_Msk    (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01)                         */
34340  #define R_PSCU_PSARB_PSARB30_Pos    (30UL)         /*!< PSARB30 (Bit 30)                                      */
34341  #define R_PSCU_PSARB_PSARB30_Msk    (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01)                         */
34342  #define R_PSCU_PSARB_PSARB31_Pos    (31UL)         /*!< PSARB31 (Bit 31)                                      */
34343  #define R_PSCU_PSARB_PSARB31_Msk    (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01)                         */
34344 /* =========================================================  PSARC  ========================================================= */
34345  #define R_PSCU_PSARC_PSARC0_Pos     (0UL)          /*!< PSARC0 (Bit 0)                                        */
34346  #define R_PSCU_PSARC_PSARC0_Msk     (0x1UL)        /*!< PSARC0 (Bitfield-Mask: 0x01)                          */
34347  #define R_PSCU_PSARC_PSARC1_Pos     (1UL)          /*!< PSARC1 (Bit 1)                                        */
34348  #define R_PSCU_PSARC_PSARC1_Msk     (0x2UL)        /*!< PSARC1 (Bitfield-Mask: 0x01)                          */
34349  #define R_PSCU_PSARC_PSARC3_Pos     (3UL)          /*!< PSARC3 (Bit 3)                                        */
34350  #define R_PSCU_PSARC_PSARC3_Msk     (0x8UL)        /*!< PSARC3 (Bitfield-Mask: 0x01)                          */
34351  #define R_PSCU_PSARC_PSARC8_Pos     (8UL)          /*!< PSARC8 (Bit 8)                                        */
34352  #define R_PSCU_PSARC_PSARC8_Msk     (0x100UL)      /*!< PSARC8 (Bitfield-Mask: 0x01)                          */
34353  #define R_PSCU_PSARC_PSARC12_Pos    (12UL)         /*!< PSARC12 (Bit 12)                                      */
34354  #define R_PSCU_PSARC_PSARC12_Msk    (0x1000UL)     /*!< PSARC12 (Bitfield-Mask: 0x01)                         */
34355  #define R_PSCU_PSARC_PSARC13_Pos    (13UL)         /*!< PSARC13 (Bit 13)                                      */
34356  #define R_PSCU_PSARC_PSARC13_Msk    (0x2000UL)     /*!< PSARC13 (Bitfield-Mask: 0x01)                         */
34357  #define R_PSCU_PSARC_PSARC20_Pos    (20UL)         /*!< PSARC20 (Bit 20)                                      */
34358  #define R_PSCU_PSARC_PSARC20_Msk    (0x100000UL)   /*!< PSARC20 (Bitfield-Mask: 0x01)                         */
34359  #define R_PSCU_PSARC_PSARC27_Pos    (27UL)         /*!< PSARC27 (Bit 27)                                      */
34360  #define R_PSCU_PSARC_PSARC27_Msk    (0x8000000UL)  /*!< PSARC27 (Bitfield-Mask: 0x01)                         */
34361  #define R_PSCU_PSARC_PSARC31_Pos    (31UL)         /*!< PSARC31 (Bit 31)                                      */
34362  #define R_PSCU_PSARC_PSARC31_Msk    (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01)                         */
34363 /* =========================================================  PSARD  ========================================================= */
34364  #define R_PSCU_PSARD_PSARD0_Pos     (0UL)          /*!< PSARD0 (Bit 0)                                        */
34365  #define R_PSCU_PSARD_PSARD0_Msk     (0x1UL)        /*!< PSARD0 (Bitfield-Mask: 0x01)                          */
34366  #define R_PSCU_PSARD_PSARD1_Pos     (1UL)          /*!< PSARD1 (Bit 1)                                        */
34367  #define R_PSCU_PSARD_PSARD1_Msk     (0x2UL)        /*!< PSARD1 (Bitfield-Mask: 0x01)                          */
34368  #define R_PSCU_PSARD_PSARD2_Pos     (2UL)          /*!< PSARD2 (Bit 2)                                        */
34369  #define R_PSCU_PSARD_PSARD2_Msk     (0x4UL)        /*!< PSARD2 (Bitfield-Mask: 0x01)                          */
34370  #define R_PSCU_PSARD_PSARD3_Pos     (3UL)          /*!< PSARD3 (Bit 3)                                        */
34371  #define R_PSCU_PSARD_PSARD3_Msk     (0x8UL)        /*!< PSARD3 (Bitfield-Mask: 0x01)                          */
34372  #define R_PSCU_PSARD_PSARD11_Pos    (11UL)         /*!< PSARD11 (Bit 11)                                      */
34373  #define R_PSCU_PSARD_PSARD11_Msk    (0x800UL)      /*!< PSARD11 (Bitfield-Mask: 0x01)                         */
34374  #define R_PSCU_PSARD_PSARD12_Pos    (12UL)         /*!< PSARD12 (Bit 12)                                      */
34375  #define R_PSCU_PSARD_PSARD12_Msk    (0x1000UL)     /*!< PSARD12 (Bitfield-Mask: 0x01)                         */
34376  #define R_PSCU_PSARD_PSARD13_Pos    (13UL)         /*!< PSARD13 (Bit 13)                                      */
34377  #define R_PSCU_PSARD_PSARD13_Msk    (0x2000UL)     /*!< PSARD13 (Bitfield-Mask: 0x01)                         */
34378  #define R_PSCU_PSARD_PSARD14_Pos    (14UL)         /*!< PSARD14 (Bit 14)                                      */
34379  #define R_PSCU_PSARD_PSARD14_Msk    (0x4000UL)     /*!< PSARD14 (Bitfield-Mask: 0x01)                         */
34380  #define R_PSCU_PSARD_PSARD15_Pos    (15UL)         /*!< PSARD15 (Bit 15)                                      */
34381  #define R_PSCU_PSARD_PSARD15_Msk    (0x8000UL)     /*!< PSARD15 (Bitfield-Mask: 0x01)                         */
34382  #define R_PSCU_PSARD_PSARD16_Pos    (16UL)         /*!< PSARD16 (Bit 16)                                      */
34383  #define R_PSCU_PSARD_PSARD16_Msk    (0x10000UL)    /*!< PSARD16 (Bitfield-Mask: 0x01)                         */
34384  #define R_PSCU_PSARD_PSARD19_Pos    (19UL)         /*!< PSARD19 (Bit 19)                                      */
34385  #define R_PSCU_PSARD_PSARD19_Msk    (0x80000UL)    /*!< PSARD19 (Bitfield-Mask: 0x01)                         */
34386  #define R_PSCU_PSARD_PSARD20_Pos    (20UL)         /*!< PSARD20 (Bit 20)                                      */
34387  #define R_PSCU_PSARD_PSARD20_Msk    (0x100000UL)   /*!< PSARD20 (Bitfield-Mask: 0x01)                         */
34388  #define R_PSCU_PSARD_PSARD22_Pos    (22UL)         /*!< PSARD22 (Bit 22)                                      */
34389  #define R_PSCU_PSARD_PSARD22_Msk    (0x400000UL)   /*!< PSARD22 (Bitfield-Mask: 0x01)                         */
34390  #define R_PSCU_PSARD_PSARD25_Pos    (25UL)         /*!< PSARD25 (Bit 25)                                      */
34391  #define R_PSCU_PSARD_PSARD25_Msk    (0x2000000UL)  /*!< PSARD25 (Bitfield-Mask: 0x01)                         */
34392  #define R_PSCU_PSARD_PSARD26_Pos    (26UL)         /*!< PSARD26 (Bit 26)                                      */
34393  #define R_PSCU_PSARD_PSARD26_Msk    (0x4000000UL)  /*!< PSARD26 (Bitfield-Mask: 0x01)                         */
34394  #define R_PSCU_PSARD_PSARD27_Pos    (27UL)         /*!< PSARD27 (Bit 27)                                      */
34395  #define R_PSCU_PSARD_PSARD27_Msk    (0x8000000UL)  /*!< PSARD27 (Bitfield-Mask: 0x01)                         */
34396  #define R_PSCU_PSARD_PSARD28_Pos    (28UL)         /*!< PSARD28 (Bit 28)                                      */
34397  #define R_PSCU_PSARD_PSARD28_Msk    (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01)                         */
34398 /* =========================================================  PSARE  ========================================================= */
34399  #define R_PSCU_PSARE_PSARE0_Pos     (0UL)          /*!< PSARE0 (Bit 0)                                        */
34400  #define R_PSCU_PSARE_PSARE0_Msk     (0x1UL)        /*!< PSARE0 (Bitfield-Mask: 0x01)                          */
34401  #define R_PSCU_PSARE_PSARE1_Pos     (1UL)          /*!< PSARE1 (Bit 1)                                        */
34402  #define R_PSCU_PSARE_PSARE1_Msk     (0x2UL)        /*!< PSARE1 (Bitfield-Mask: 0x01)                          */
34403  #define R_PSCU_PSARE_PSARE2_Pos     (2UL)          /*!< PSARE2 (Bit 2)                                        */
34404  #define R_PSCU_PSARE_PSARE2_Msk     (0x4UL)        /*!< PSARE2 (Bitfield-Mask: 0x01)                          */
34405  #define R_PSCU_PSARE_PSARE14_Pos    (14UL)         /*!< PSARE14 (Bit 14)                                      */
34406  #define R_PSCU_PSARE_PSARE14_Msk    (0x4000UL)     /*!< PSARE14 (Bitfield-Mask: 0x01)                         */
34407  #define R_PSCU_PSARE_PSARE15_Pos    (15UL)         /*!< PSARE15 (Bit 15)                                      */
34408  #define R_PSCU_PSARE_PSARE15_Msk    (0x8000UL)     /*!< PSARE15 (Bitfield-Mask: 0x01)                         */
34409  #define R_PSCU_PSARE_PSARE22_Pos    (22UL)         /*!< PSARE22 (Bit 22)                                      */
34410  #define R_PSCU_PSARE_PSARE22_Msk    (0x400000UL)   /*!< PSARE22 (Bitfield-Mask: 0x01)                         */
34411  #define R_PSCU_PSARE_PSARE23_Pos    (23UL)         /*!< PSARE23 (Bit 23)                                      */
34412  #define R_PSCU_PSARE_PSARE23_Msk    (0x800000UL)   /*!< PSARE23 (Bitfield-Mask: 0x01)                         */
34413  #define R_PSCU_PSARE_PSARE24_Pos    (24UL)         /*!< PSARE24 (Bit 24)                                      */
34414  #define R_PSCU_PSARE_PSARE24_Msk    (0x1000000UL)  /*!< PSARE24 (Bitfield-Mask: 0x01)                         */
34415  #define R_PSCU_PSARE_PSARE25_Pos    (25UL)         /*!< PSARE25 (Bit 25)                                      */
34416  #define R_PSCU_PSARE_PSARE25_Msk    (0x2000000UL)  /*!< PSARE25 (Bitfield-Mask: 0x01)                         */
34417  #define R_PSCU_PSARE_PSARE26_Pos    (26UL)         /*!< PSARE26 (Bit 26)                                      */
34418  #define R_PSCU_PSARE_PSARE26_Msk    (0x4000000UL)  /*!< PSARE26 (Bitfield-Mask: 0x01)                         */
34419  #define R_PSCU_PSARE_PSARE27_Pos    (27UL)         /*!< PSARE27 (Bit 27)                                      */
34420  #define R_PSCU_PSARE_PSARE27_Msk    (0x8000000UL)  /*!< PSARE27 (Bitfield-Mask: 0x01)                         */
34421  #define R_PSCU_PSARE_PSARE28_Pos    (28UL)         /*!< PSARE28 (Bit 28)                                      */
34422  #define R_PSCU_PSARE_PSARE28_Msk    (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01)                         */
34423  #define R_PSCU_PSARE_PSARE29_Pos    (29UL)         /*!< PSARE29 (Bit 29)                                      */
34424  #define R_PSCU_PSARE_PSARE29_Msk    (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01)                         */
34425  #define R_PSCU_PSARE_PSARE30_Pos    (30UL)         /*!< PSARE30 (Bit 30)                                      */
34426  #define R_PSCU_PSARE_PSARE30_Msk    (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01)                         */
34427  #define R_PSCU_PSARE_PSARE31_Pos    (31UL)         /*!< PSARE31 (Bit 31)                                      */
34428  #define R_PSCU_PSARE_PSARE31_Msk    (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01)                         */
34429 /* =========================================================  MSSAR  ========================================================= */
34430  #define R_PSCU_MSSAR_MSSAR0_Pos     (0UL)          /*!< MSSAR0 (Bit 0)                                        */
34431  #define R_PSCU_MSSAR_MSSAR0_Msk     (0x1UL)        /*!< MSSAR0 (Bitfield-Mask: 0x01)                          */
34432  #define R_PSCU_MSSAR_MSSAR1_Pos     (1UL)          /*!< MSSAR1 (Bit 1)                                        */
34433  #define R_PSCU_MSSAR_MSSAR1_Msk     (0x2UL)        /*!< MSSAR1 (Bitfield-Mask: 0x01)                          */
34434  #define R_PSCU_MSSAR_MSSAR2_Pos     (2UL)          /*!< MSSAR2 (Bit 2)                                        */
34435  #define R_PSCU_MSSAR_MSSAR2_Msk     (0x4UL)        /*!< MSSAR2 (Bitfield-Mask: 0x01)                          */
34436  #define R_PSCU_MSSAR_MSSAR3_Pos     (3UL)          /*!< MSSAR3 (Bit 3)                                        */
34437  #define R_PSCU_MSSAR_MSSAR3_Msk     (0x8UL)        /*!< MSSAR3 (Bitfield-Mask: 0x01)                          */
34438 /* =======================================================  CFSAMONA  ======================================================== */
34439  #define R_PSCU_CFSAMONA_CFS2_Pos    (15UL)         /*!< CFS2 (Bit 15)                                         */
34440  #define R_PSCU_CFSAMONA_CFS2_Msk    (0xff8000UL)   /*!< CFS2 (Bitfield-Mask: 0x1ff)                           */
34441 /* =======================================================  CFSAMONB  ======================================================== */
34442  #define R_PSCU_CFSAMONB_CFS1_Pos    (10UL)         /*!< CFS1 (Bit 10)                                         */
34443  #define R_PSCU_CFSAMONB_CFS1_Msk    (0xfffc00UL)   /*!< CFS1 (Bitfield-Mask: 0x3fff)                          */
34444 /* ========================================================  DFSAMON  ======================================================== */
34445  #define R_PSCU_DFSAMON_DFS_Pos      (10UL)         /*!< DFS (Bit 10)                                          */
34446  #define R_PSCU_DFSAMON_DFS_Msk      (0xfc00UL)     /*!< DFS (Bitfield-Mask: 0x3f)                             */
34447 /* ========================================================  SSAMONA  ======================================================== */
34448  #define R_PSCU_SSAMONA_SS2_Pos      (13UL)         /*!< SS2 (Bit 13)                                          */
34449  #define R_PSCU_SSAMONA_SS2_Msk      (0x1fe000UL)   /*!< SS2 (Bitfield-Mask: 0xff)                             */
34450 /* ========================================================  SSAMONB  ======================================================== */
34451  #define R_PSCU_SSAMONB_SS1_Pos      (10UL)         /*!< SS1 (Bit 10)                                          */
34452  #define R_PSCU_SSAMONB_SS1_Msk      (0x1ffc00UL)   /*!< SS1 (Bitfield-Mask: 0x7ff)                            */
34453 /* ========================================================  DLMMON  ========================================================= */
34454  #define R_PSCU_DLMMON_DLMMON_Pos    (0UL)          /*!< DLMMON (Bit 0)                                        */
34455  #define R_PSCU_DLMMON_DLMMON_Msk    (0xfUL)        /*!< DLMMON (Bitfield-Mask: 0x0f)                          */
34456 
34457 /* =========================================================================================================================== */
34458 /* ================                                          R_AGT0                                           ================ */
34459 /* =========================================================================================================================== */
34460 
34461 /* ==========================================================  AGT  ========================================================== */
34462  #define R_AGT0_AGT_AGT_Pos           (0UL)      /*!< AGT (Bit 0)                                           */
34463  #define R_AGT0_AGT_AGT_Msk           (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
34464 /* ========================================================  AGTCMA  ========================================================= */
34465  #define R_AGT0_AGTCMA_AGTCMA_Pos     (0UL)      /*!< AGTCMA (Bit 0)                                        */
34466  #define R_AGT0_AGTCMA_AGTCMA_Msk     (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
34467 /* ========================================================  AGTCMB  ========================================================= */
34468  #define R_AGT0_AGTCMB_AGTCMB_Pos     (0UL)      /*!< AGTCMB (Bit 0)                                        */
34469  #define R_AGT0_AGTCMB_AGTCMB_Msk     (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
34470 /* =========================================================  AGTCR  ========================================================= */
34471  #define R_AGT0_AGTCR_TCMBF_Pos       (7UL)      /*!< TCMBF (Bit 7)                                         */
34472  #define R_AGT0_AGTCR_TCMBF_Msk       (0x80UL)   /*!< TCMBF (Bitfield-Mask: 0x01)                           */
34473  #define R_AGT0_AGTCR_TCMAF_Pos       (6UL)      /*!< TCMAF (Bit 6)                                         */
34474  #define R_AGT0_AGTCR_TCMAF_Msk       (0x40UL)   /*!< TCMAF (Bitfield-Mask: 0x01)                           */
34475  #define R_AGT0_AGTCR_TUNDF_Pos       (5UL)      /*!< TUNDF (Bit 5)                                         */
34476  #define R_AGT0_AGTCR_TUNDF_Msk       (0x20UL)   /*!< TUNDF (Bitfield-Mask: 0x01)                           */
34477  #define R_AGT0_AGTCR_TEDGF_Pos       (4UL)      /*!< TEDGF (Bit 4)                                         */
34478  #define R_AGT0_AGTCR_TEDGF_Msk       (0x10UL)   /*!< TEDGF (Bitfield-Mask: 0x01)                           */
34479  #define R_AGT0_AGTCR_TSTOP_Pos       (2UL)      /*!< TSTOP (Bit 2)                                         */
34480  #define R_AGT0_AGTCR_TSTOP_Msk       (0x4UL)    /*!< TSTOP (Bitfield-Mask: 0x01)                           */
34481  #define R_AGT0_AGTCR_TCSTF_Pos       (1UL)      /*!< TCSTF (Bit 1)                                         */
34482  #define R_AGT0_AGTCR_TCSTF_Msk       (0x2UL)    /*!< TCSTF (Bitfield-Mask: 0x01)                           */
34483  #define R_AGT0_AGTCR_TSTART_Pos      (0UL)      /*!< TSTART (Bit 0)                                        */
34484  #define R_AGT0_AGTCR_TSTART_Msk      (0x1UL)    /*!< TSTART (Bitfield-Mask: 0x01)                          */
34485 /* ========================================================  AGTMR1  ========================================================= */
34486  #define R_AGT0_AGTMR1_TCK_Pos        (4UL)      /*!< TCK (Bit 4)                                           */
34487  #define R_AGT0_AGTMR1_TCK_Msk        (0x70UL)   /*!< TCK (Bitfield-Mask: 0x07)                             */
34488  #define R_AGT0_AGTMR1_TEDGPL_Pos     (3UL)      /*!< TEDGPL (Bit 3)                                        */
34489  #define R_AGT0_AGTMR1_TEDGPL_Msk     (0x8UL)    /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
34490  #define R_AGT0_AGTMR1_TMOD_Pos       (0UL)      /*!< TMOD (Bit 0)                                          */
34491  #define R_AGT0_AGTMR1_TMOD_Msk       (0x7UL)    /*!< TMOD (Bitfield-Mask: 0x07)                            */
34492 /* ========================================================  AGTMR2  ========================================================= */
34493  #define R_AGT0_AGTMR2_LPM_Pos        (7UL)      /*!< LPM (Bit 7)                                           */
34494  #define R_AGT0_AGTMR2_LPM_Msk        (0x80UL)   /*!< LPM (Bitfield-Mask: 0x01)                             */
34495  #define R_AGT0_AGTMR2_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
34496  #define R_AGT0_AGTMR2_CKS_Msk        (0x7UL)    /*!< CKS (Bitfield-Mask: 0x07)                             */
34497 /* ========================================================  AGTIOC  ========================================================= */
34498  #define R_AGT0_AGTIOC_TIOGT_Pos      (6UL)      /*!< TIOGT (Bit 6)                                         */
34499  #define R_AGT0_AGTIOC_TIOGT_Msk      (0xc0UL)   /*!< TIOGT (Bitfield-Mask: 0x03)                           */
34500  #define R_AGT0_AGTIOC_TIPF_Pos       (4UL)      /*!< TIPF (Bit 4)                                          */
34501  #define R_AGT0_AGTIOC_TIPF_Msk       (0x30UL)   /*!< TIPF (Bitfield-Mask: 0x03)                            */
34502  #define R_AGT0_AGTIOC_TOE_Pos        (2UL)      /*!< TOE (Bit 2)                                           */
34503  #define R_AGT0_AGTIOC_TOE_Msk        (0x4UL)    /*!< TOE (Bitfield-Mask: 0x01)                             */
34504  #define R_AGT0_AGTIOC_TEDGSEL_Pos    (0UL)      /*!< TEDGSEL (Bit 0)                                       */
34505  #define R_AGT0_AGTIOC_TEDGSEL_Msk    (0x1UL)    /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
34506 /* ========================================================  AGTISR  ========================================================= */
34507  #define R_AGT0_AGTISR_EEPS_Pos       (2UL)      /*!< EEPS (Bit 2)                                          */
34508  #define R_AGT0_AGTISR_EEPS_Msk       (0x4UL)    /*!< EEPS (Bitfield-Mask: 0x01)                            */
34509 /* ========================================================  AGTCMSR  ======================================================== */
34510  #define R_AGT0_AGTCMSR_TOPOLB_Pos    (6UL)      /*!< TOPOLB (Bit 6)                                        */
34511  #define R_AGT0_AGTCMSR_TOPOLB_Msk    (0x40UL)   /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
34512  #define R_AGT0_AGTCMSR_TOEB_Pos      (5UL)      /*!< TOEB (Bit 5)                                          */
34513  #define R_AGT0_AGTCMSR_TOEB_Msk      (0x20UL)   /*!< TOEB (Bitfield-Mask: 0x01)                            */
34514  #define R_AGT0_AGTCMSR_TCMEB_Pos     (4UL)      /*!< TCMEB (Bit 4)                                         */
34515  #define R_AGT0_AGTCMSR_TCMEB_Msk     (0x10UL)   /*!< TCMEB (Bitfield-Mask: 0x01)                           */
34516  #define R_AGT0_AGTCMSR_TOPOLA_Pos    (2UL)      /*!< TOPOLA (Bit 2)                                        */
34517  #define R_AGT0_AGTCMSR_TOPOLA_Msk    (0x4UL)    /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
34518  #define R_AGT0_AGTCMSR_TOEA_Pos      (1UL)      /*!< TOEA (Bit 1)                                          */
34519  #define R_AGT0_AGTCMSR_TOEA_Msk      (0x2UL)    /*!< TOEA (Bitfield-Mask: 0x01)                            */
34520  #define R_AGT0_AGTCMSR_TCMEA_Pos     (0UL)      /*!< TCMEA (Bit 0)                                         */
34521  #define R_AGT0_AGTCMSR_TCMEA_Msk     (0x1UL)    /*!< TCMEA (Bitfield-Mask: 0x01)                           */
34522 /* =======================================================  AGTIOSEL  ======================================================== */
34523  #define R_AGT0_AGTIOSEL_TIES_Pos     (4UL)      /*!< TIES (Bit 4)                                          */
34524  #define R_AGT0_AGTIOSEL_TIES_Msk     (0x10UL)   /*!< TIES (Bitfield-Mask: 0x01)                            */
34525  #define R_AGT0_AGTIOSEL_SEL_Pos      (0UL)      /*!< SEL (Bit 0)                                           */
34526  #define R_AGT0_AGTIOSEL_SEL_Msk      (0x3UL)    /*!< SEL (Bitfield-Mask: 0x03)                             */
34527 
34528 /* =========================================================================================================================== */
34529 /* ================                                          R_AGTW0                                          ================ */
34530 /* =========================================================================================================================== */
34531 
34532 /* ==========================================================  AGT  ========================================================== */
34533  #define R_AGTW0_AGT_AGT_Pos           (0UL)          /*!< AGT (Bit 0)                                           */
34534  #define R_AGTW0_AGT_AGT_Msk           (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
34535 /* ========================================================  AGTCMA  ========================================================= */
34536  #define R_AGTW0_AGTCMA_AGTCMA_Pos     (0UL)          /*!< AGTCMA (Bit 0)                                        */
34537  #define R_AGTW0_AGTCMA_AGTCMA_Msk     (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
34538 /* ========================================================  AGTCMB  ========================================================= */
34539  #define R_AGTW0_AGTCMB_AGTCMB_Pos     (0UL)          /*!< AGTCMB (Bit 0)                                        */
34540  #define R_AGTW0_AGTCMB_AGTCMB_Msk     (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
34541 /* =========================================================  AGTCR  ========================================================= */
34542  #define R_AGTW0_AGTCR_TCMBF_Pos       (7UL)          /*!< TCMBF (Bit 7)                                         */
34543  #define R_AGTW0_AGTCR_TCMBF_Msk       (0x80UL)       /*!< TCMBF (Bitfield-Mask: 0x01)                           */
34544  #define R_AGTW0_AGTCR_TCMAF_Pos       (6UL)          /*!< TCMAF (Bit 6)                                         */
34545  #define R_AGTW0_AGTCR_TCMAF_Msk       (0x40UL)       /*!< TCMAF (Bitfield-Mask: 0x01)                           */
34546  #define R_AGTW0_AGTCR_TUNDF_Pos       (5UL)          /*!< TUNDF (Bit 5)                                         */
34547  #define R_AGTW0_AGTCR_TUNDF_Msk       (0x20UL)       /*!< TUNDF (Bitfield-Mask: 0x01)                           */
34548  #define R_AGTW0_AGTCR_TEDGF_Pos       (4UL)          /*!< TEDGF (Bit 4)                                         */
34549  #define R_AGTW0_AGTCR_TEDGF_Msk       (0x10UL)       /*!< TEDGF (Bitfield-Mask: 0x01)                           */
34550  #define R_AGTW0_AGTCR_TSTOP_Pos       (2UL)          /*!< TSTOP (Bit 2)                                         */
34551  #define R_AGTW0_AGTCR_TSTOP_Msk       (0x4UL)        /*!< TSTOP (Bitfield-Mask: 0x01)                           */
34552  #define R_AGTW0_AGTCR_TCSTF_Pos       (1UL)          /*!< TCSTF (Bit 1)                                         */
34553  #define R_AGTW0_AGTCR_TCSTF_Msk       (0x2UL)        /*!< TCSTF (Bitfield-Mask: 0x01)                           */
34554  #define R_AGTW0_AGTCR_TSTART_Pos      (0UL)          /*!< TSTART (Bit 0)                                        */
34555  #define R_AGTW0_AGTCR_TSTART_Msk      (0x1UL)        /*!< TSTART (Bitfield-Mask: 0x01)                          */
34556 /* ========================================================  AGTMR1  ========================================================= */
34557  #define R_AGTW0_AGTMR1_TCK_Pos        (4UL)          /*!< TCK (Bit 4)                                           */
34558  #define R_AGTW0_AGTMR1_TCK_Msk        (0x70UL)       /*!< TCK (Bitfield-Mask: 0x07)                             */
34559  #define R_AGTW0_AGTMR1_TEDGPL_Pos     (3UL)          /*!< TEDGPL (Bit 3)                                        */
34560  #define R_AGTW0_AGTMR1_TEDGPL_Msk     (0x8UL)        /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
34561  #define R_AGTW0_AGTMR1_TMOD_Pos       (0UL)          /*!< TMOD (Bit 0)                                          */
34562  #define R_AGTW0_AGTMR1_TMOD_Msk       (0x7UL)        /*!< TMOD (Bitfield-Mask: 0x07)                            */
34563 /* ========================================================  AGTMR2  ========================================================= */
34564  #define R_AGTW0_AGTMR2_LPM_Pos        (7UL)          /*!< LPM (Bit 7)                                           */
34565  #define R_AGTW0_AGTMR2_LPM_Msk        (0x80UL)       /*!< LPM (Bitfield-Mask: 0x01)                             */
34566  #define R_AGTW0_AGTMR2_CKS_Pos        (0UL)          /*!< CKS (Bit 0)                                           */
34567  #define R_AGTW0_AGTMR2_CKS_Msk        (0x7UL)        /*!< CKS (Bitfield-Mask: 0x07)                             */
34568 /* ========================================================  AGTIOC  ========================================================= */
34569  #define R_AGTW0_AGTIOC_TIOGT_Pos      (6UL)          /*!< TIOGT (Bit 6)                                         */
34570  #define R_AGTW0_AGTIOC_TIOGT_Msk      (0xc0UL)       /*!< TIOGT (Bitfield-Mask: 0x03)                           */
34571  #define R_AGTW0_AGTIOC_TIPF_Pos       (4UL)          /*!< TIPF (Bit 4)                                          */
34572  #define R_AGTW0_AGTIOC_TIPF_Msk       (0x30UL)       /*!< TIPF (Bitfield-Mask: 0x03)                            */
34573  #define R_AGTW0_AGTIOC_TOE_Pos        (2UL)          /*!< TOE (Bit 2)                                           */
34574  #define R_AGTW0_AGTIOC_TOE_Msk        (0x4UL)        /*!< TOE (Bitfield-Mask: 0x01)                             */
34575  #define R_AGTW0_AGTIOC_TEDGSEL_Pos    (0UL)          /*!< TEDGSEL (Bit 0)                                       */
34576  #define R_AGTW0_AGTIOC_TEDGSEL_Msk    (0x1UL)        /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
34577 /* ========================================================  AGTISR  ========================================================= */
34578  #define R_AGTW0_AGTISR_EEPS_Pos       (2UL)          /*!< EEPS (Bit 2)                                          */
34579  #define R_AGTW0_AGTISR_EEPS_Msk       (0x4UL)        /*!< EEPS (Bitfield-Mask: 0x01)                            */
34580 /* ========================================================  AGTCMSR  ======================================================== */
34581  #define R_AGTW0_AGTCMSR_TOPOLB_Pos    (6UL)          /*!< TOPOLB (Bit 6)                                        */
34582  #define R_AGTW0_AGTCMSR_TOPOLB_Msk    (0x40UL)       /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
34583  #define R_AGTW0_AGTCMSR_TOEB_Pos      (5UL)          /*!< TOEB (Bit 5)                                          */
34584  #define R_AGTW0_AGTCMSR_TOEB_Msk      (0x20UL)       /*!< TOEB (Bitfield-Mask: 0x01)                            */
34585  #define R_AGTW0_AGTCMSR_TCMEB_Pos     (4UL)          /*!< TCMEB (Bit 4)                                         */
34586  #define R_AGTW0_AGTCMSR_TCMEB_Msk     (0x10UL)       /*!< TCMEB (Bitfield-Mask: 0x01)                           */
34587  #define R_AGTW0_AGTCMSR_TOPOLA_Pos    (2UL)          /*!< TOPOLA (Bit 2)                                        */
34588  #define R_AGTW0_AGTCMSR_TOPOLA_Msk    (0x4UL)        /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
34589  #define R_AGTW0_AGTCMSR_TOEA_Pos      (1UL)          /*!< TOEA (Bit 1)                                          */
34590  #define R_AGTW0_AGTCMSR_TOEA_Msk      (0x2UL)        /*!< TOEA (Bitfield-Mask: 0x01)                            */
34591  #define R_AGTW0_AGTCMSR_TCMEA_Pos     (0UL)          /*!< TCMEA (Bit 0)                                         */
34592  #define R_AGTW0_AGTCMSR_TCMEA_Msk     (0x1UL)        /*!< TCMEA (Bitfield-Mask: 0x01)                           */
34593 /* =======================================================  AGTIOSEL  ======================================================== */
34594  #define R_AGTW0_AGTIOSEL_TIES_Pos     (4UL)          /*!< TIES (Bit 4)                                          */
34595  #define R_AGTW0_AGTIOSEL_TIES_Msk     (0x10UL)       /*!< TIES (Bitfield-Mask: 0x01)                            */
34596 
34597 /* =========================================================================================================================== */
34598 /* ================                                           R_BUS                                           ================ */
34599 /* =========================================================================================================================== */
34600 
34601 /* ========================================================  CSRECEN  ======================================================== */
34602  #define R_BUS_CSRECEN_RCVENM_Pos    (8UL)     /*!< RCVENM (Bit 8)                                        */
34603  #define R_BUS_CSRECEN_RCVENM_Msk    (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01)                          */
34604  #define R_BUS_CSRECEN_RCVEN_Pos     (0UL)     /*!< RCVEN (Bit 0)                                         */
34605  #define R_BUS_CSRECEN_RCVEN_Msk     (0x1UL)   /*!< RCVEN (Bitfield-Mask: 0x01)                           */
34606 
34607 /* =========================================================================================================================== */
34608 /* ================                                           R_CAC                                           ================ */
34609 /* =========================================================================================================================== */
34610 
34611 /* =========================================================  CACR0  ========================================================= */
34612  #define R_CAC_CACR0_CFME_Pos         (0UL)      /*!< CFME (Bit 0)                                          */
34613  #define R_CAC_CACR0_CFME_Msk         (0x1UL)    /*!< CFME (Bitfield-Mask: 0x01)                            */
34614 /* =========================================================  CACR1  ========================================================= */
34615  #define R_CAC_CACR1_EDGES_Pos        (6UL)      /*!< EDGES (Bit 6)                                         */
34616  #define R_CAC_CACR1_EDGES_Msk        (0xc0UL)   /*!< EDGES (Bitfield-Mask: 0x03)                           */
34617  #define R_CAC_CACR1_TCSS_Pos         (4UL)      /*!< TCSS (Bit 4)                                          */
34618  #define R_CAC_CACR1_TCSS_Msk         (0x30UL)   /*!< TCSS (Bitfield-Mask: 0x03)                            */
34619  #define R_CAC_CACR1_FMCS_Pos         (1UL)      /*!< FMCS (Bit 1)                                          */
34620  #define R_CAC_CACR1_FMCS_Msk         (0xeUL)    /*!< FMCS (Bitfield-Mask: 0x07)                            */
34621  #define R_CAC_CACR1_CACREFE_Pos      (0UL)      /*!< CACREFE (Bit 0)                                       */
34622  #define R_CAC_CACR1_CACREFE_Msk      (0x1UL)    /*!< CACREFE (Bitfield-Mask: 0x01)                         */
34623 /* =========================================================  CACR2  ========================================================= */
34624  #define R_CAC_CACR2_DFS_Pos          (6UL)      /*!< DFS (Bit 6)                                           */
34625  #define R_CAC_CACR2_DFS_Msk          (0xc0UL)   /*!< DFS (Bitfield-Mask: 0x03)                             */
34626  #define R_CAC_CACR2_RCDS_Pos         (4UL)      /*!< RCDS (Bit 4)                                          */
34627  #define R_CAC_CACR2_RCDS_Msk         (0x30UL)   /*!< RCDS (Bitfield-Mask: 0x03)                            */
34628  #define R_CAC_CACR2_RSCS_Pos         (1UL)      /*!< RSCS (Bit 1)                                          */
34629  #define R_CAC_CACR2_RSCS_Msk         (0xeUL)    /*!< RSCS (Bitfield-Mask: 0x07)                            */
34630  #define R_CAC_CACR2_RPS_Pos          (0UL)      /*!< RPS (Bit 0)                                           */
34631  #define R_CAC_CACR2_RPS_Msk          (0x1UL)    /*!< RPS (Bitfield-Mask: 0x01)                             */
34632 /* =========================================================  CAICR  ========================================================= */
34633  #define R_CAC_CAICR_OVFFCL_Pos       (6UL)      /*!< OVFFCL (Bit 6)                                        */
34634  #define R_CAC_CAICR_OVFFCL_Msk       (0x40UL)   /*!< OVFFCL (Bitfield-Mask: 0x01)                          */
34635  #define R_CAC_CAICR_MENDFCL_Pos      (5UL)      /*!< MENDFCL (Bit 5)                                       */
34636  #define R_CAC_CAICR_MENDFCL_Msk      (0x20UL)   /*!< MENDFCL (Bitfield-Mask: 0x01)                         */
34637  #define R_CAC_CAICR_FERRFCL_Pos      (4UL)      /*!< FERRFCL (Bit 4)                                       */
34638  #define R_CAC_CAICR_FERRFCL_Msk      (0x10UL)   /*!< FERRFCL (Bitfield-Mask: 0x01)                         */
34639  #define R_CAC_CAICR_OVFIE_Pos        (2UL)      /*!< OVFIE (Bit 2)                                         */
34640  #define R_CAC_CAICR_OVFIE_Msk        (0x4UL)    /*!< OVFIE (Bitfield-Mask: 0x01)                           */
34641  #define R_CAC_CAICR_MENDIE_Pos       (1UL)      /*!< MENDIE (Bit 1)                                        */
34642  #define R_CAC_CAICR_MENDIE_Msk       (0x2UL)    /*!< MENDIE (Bitfield-Mask: 0x01)                          */
34643  #define R_CAC_CAICR_FERRIE_Pos       (0UL)      /*!< FERRIE (Bit 0)                                        */
34644  #define R_CAC_CAICR_FERRIE_Msk       (0x1UL)    /*!< FERRIE (Bitfield-Mask: 0x01)                          */
34645 /* =========================================================  CASTR  ========================================================= */
34646  #define R_CAC_CASTR_OVFF_Pos         (2UL)      /*!< OVFF (Bit 2)                                          */
34647  #define R_CAC_CASTR_OVFF_Msk         (0x4UL)    /*!< OVFF (Bitfield-Mask: 0x01)                            */
34648  #define R_CAC_CASTR_MENDF_Pos        (1UL)      /*!< MENDF (Bit 1)                                         */
34649  #define R_CAC_CASTR_MENDF_Msk        (0x2UL)    /*!< MENDF (Bitfield-Mask: 0x01)                           */
34650  #define R_CAC_CASTR_FERRF_Pos        (0UL)      /*!< FERRF (Bit 0)                                         */
34651  #define R_CAC_CASTR_FERRF_Msk        (0x1UL)    /*!< FERRF (Bitfield-Mask: 0x01)                           */
34652 /* ========================================================  CAULVR  ========================================================= */
34653  #define R_CAC_CAULVR_CAULVR_Pos      (0UL)      /*!< CAULVR (Bit 0)                                        */
34654  #define R_CAC_CAULVR_CAULVR_Msk      (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff)                        */
34655 /* ========================================================  CALLVR  ========================================================= */
34656  #define R_CAC_CALLVR_CALLVR_Pos      (0UL)      /*!< CALLVR (Bit 0)                                        */
34657  #define R_CAC_CALLVR_CALLVR_Msk      (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff)                        */
34658 /* ========================================================  CACNTBR  ======================================================== */
34659  #define R_CAC_CACNTBR_CACNTBR_Pos    (0UL)      /*!< CACNTBR (Bit 0)                                       */
34660  #define R_CAC_CACNTBR_CACNTBR_Msk    (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff)                       */
34661 
34662 /* =========================================================================================================================== */
34663 /* ================                                          R_CAN0                                           ================ */
34664 /* =========================================================================================================================== */
34665 
34666 /* ==========================================================  MKR  ========================================================== */
34667  #define R_CAN0_MKR_SID_Pos              (18UL)         /*!< SID (Bit 18)                                          */
34668  #define R_CAN0_MKR_SID_Msk              (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff)                            */
34669  #define R_CAN0_MKR_EID_Pos              (0UL)          /*!< EID (Bit 0)                                           */
34670  #define R_CAN0_MKR_EID_Msk              (0x3ffffUL)    /*!< EID (Bitfield-Mask: 0x3ffff)                          */
34671 /* =========================================================  FIDCR  ========================================================= */
34672  #define R_CAN0_FIDCR_IDE_Pos            (31UL)         /*!< IDE (Bit 31)                                          */
34673  #define R_CAN0_FIDCR_IDE_Msk            (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01)                             */
34674  #define R_CAN0_FIDCR_RTR_Pos            (30UL)         /*!< RTR (Bit 30)                                          */
34675  #define R_CAN0_FIDCR_RTR_Msk            (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01)                             */
34676  #define R_CAN0_FIDCR_SID_Pos            (18UL)         /*!< SID (Bit 18)                                          */
34677  #define R_CAN0_FIDCR_SID_Msk            (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff)                            */
34678  #define R_CAN0_FIDCR_EID_Pos            (0UL)          /*!< EID (Bit 0)                                           */
34679  #define R_CAN0_FIDCR_EID_Msk            (0x3ffffUL)    /*!< EID (Bitfield-Mask: 0x3ffff)                          */
34680 /* ========================================================  MKIVLR  ========================================================= */
34681  #define R_CAN0_MKIVLR_MB31_Pos          (31UL)         /*!< MB31 (Bit 31)                                         */
34682  #define R_CAN0_MKIVLR_MB31_Msk          (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01)                            */
34683  #define R_CAN0_MKIVLR_MB30_Pos          (30UL)         /*!< MB30 (Bit 30)                                         */
34684  #define R_CAN0_MKIVLR_MB30_Msk          (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01)                            */
34685  #define R_CAN0_MKIVLR_MB29_Pos          (29UL)         /*!< MB29 (Bit 29)                                         */
34686  #define R_CAN0_MKIVLR_MB29_Msk          (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01)                            */
34687  #define R_CAN0_MKIVLR_MB28_Pos          (28UL)         /*!< MB28 (Bit 28)                                         */
34688  #define R_CAN0_MKIVLR_MB28_Msk          (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01)                            */
34689  #define R_CAN0_MKIVLR_MB27_Pos          (27UL)         /*!< MB27 (Bit 27)                                         */
34690  #define R_CAN0_MKIVLR_MB27_Msk          (0x8000000UL)  /*!< MB27 (Bitfield-Mask: 0x01)                            */
34691  #define R_CAN0_MKIVLR_MB26_Pos          (26UL)         /*!< MB26 (Bit 26)                                         */
34692  #define R_CAN0_MKIVLR_MB26_Msk          (0x4000000UL)  /*!< MB26 (Bitfield-Mask: 0x01)                            */
34693  #define R_CAN0_MKIVLR_MB25_Pos          (25UL)         /*!< MB25 (Bit 25)                                         */
34694  #define R_CAN0_MKIVLR_MB25_Msk          (0x2000000UL)  /*!< MB25 (Bitfield-Mask: 0x01)                            */
34695  #define R_CAN0_MKIVLR_MB24_Pos          (24UL)         /*!< MB24 (Bit 24)                                         */
34696  #define R_CAN0_MKIVLR_MB24_Msk          (0x1000000UL)  /*!< MB24 (Bitfield-Mask: 0x01)                            */
34697  #define R_CAN0_MKIVLR_MB23_Pos          (23UL)         /*!< MB23 (Bit 23)                                         */
34698  #define R_CAN0_MKIVLR_MB23_Msk          (0x800000UL)   /*!< MB23 (Bitfield-Mask: 0x01)                            */
34699  #define R_CAN0_MKIVLR_MB22_Pos          (22UL)         /*!< MB22 (Bit 22)                                         */
34700  #define R_CAN0_MKIVLR_MB22_Msk          (0x400000UL)   /*!< MB22 (Bitfield-Mask: 0x01)                            */
34701  #define R_CAN0_MKIVLR_MB21_Pos          (21UL)         /*!< MB21 (Bit 21)                                         */
34702  #define R_CAN0_MKIVLR_MB21_Msk          (0x200000UL)   /*!< MB21 (Bitfield-Mask: 0x01)                            */
34703  #define R_CAN0_MKIVLR_MB20_Pos          (20UL)         /*!< MB20 (Bit 20)                                         */
34704  #define R_CAN0_MKIVLR_MB20_Msk          (0x100000UL)   /*!< MB20 (Bitfield-Mask: 0x01)                            */
34705  #define R_CAN0_MKIVLR_MB19_Pos          (19UL)         /*!< MB19 (Bit 19)                                         */
34706  #define R_CAN0_MKIVLR_MB19_Msk          (0x80000UL)    /*!< MB19 (Bitfield-Mask: 0x01)                            */
34707  #define R_CAN0_MKIVLR_MB18_Pos          (18UL)         /*!< MB18 (Bit 18)                                         */
34708  #define R_CAN0_MKIVLR_MB18_Msk          (0x40000UL)    /*!< MB18 (Bitfield-Mask: 0x01)                            */
34709  #define R_CAN0_MKIVLR_MB17_Pos          (17UL)         /*!< MB17 (Bit 17)                                         */
34710  #define R_CAN0_MKIVLR_MB17_Msk          (0x20000UL)    /*!< MB17 (Bitfield-Mask: 0x01)                            */
34711  #define R_CAN0_MKIVLR_MB16_Pos          (16UL)         /*!< MB16 (Bit 16)                                         */
34712  #define R_CAN0_MKIVLR_MB16_Msk          (0x10000UL)    /*!< MB16 (Bitfield-Mask: 0x01)                            */
34713  #define R_CAN0_MKIVLR_MB15_Pos          (15UL)         /*!< MB15 (Bit 15)                                         */
34714  #define R_CAN0_MKIVLR_MB15_Msk          (0x8000UL)     /*!< MB15 (Bitfield-Mask: 0x01)                            */
34715  #define R_CAN0_MKIVLR_MB14_Pos          (14UL)         /*!< MB14 (Bit 14)                                         */
34716  #define R_CAN0_MKIVLR_MB14_Msk          (0x4000UL)     /*!< MB14 (Bitfield-Mask: 0x01)                            */
34717  #define R_CAN0_MKIVLR_MB13_Pos          (13UL)         /*!< MB13 (Bit 13)                                         */
34718  #define R_CAN0_MKIVLR_MB13_Msk          (0x2000UL)     /*!< MB13 (Bitfield-Mask: 0x01)                            */
34719  #define R_CAN0_MKIVLR_MB12_Pos          (12UL)         /*!< MB12 (Bit 12)                                         */
34720  #define R_CAN0_MKIVLR_MB12_Msk          (0x1000UL)     /*!< MB12 (Bitfield-Mask: 0x01)                            */
34721  #define R_CAN0_MKIVLR_MB11_Pos          (11UL)         /*!< MB11 (Bit 11)                                         */
34722  #define R_CAN0_MKIVLR_MB11_Msk          (0x800UL)      /*!< MB11 (Bitfield-Mask: 0x01)                            */
34723  #define R_CAN0_MKIVLR_MB10_Pos          (10UL)         /*!< MB10 (Bit 10)                                         */
34724  #define R_CAN0_MKIVLR_MB10_Msk          (0x400UL)      /*!< MB10 (Bitfield-Mask: 0x01)                            */
34725  #define R_CAN0_MKIVLR_MB9_Pos           (9UL)          /*!< MB9 (Bit 9)                                           */
34726  #define R_CAN0_MKIVLR_MB9_Msk           (0x200UL)      /*!< MB9 (Bitfield-Mask: 0x01)                             */
34727  #define R_CAN0_MKIVLR_MB8_Pos           (8UL)          /*!< MB8 (Bit 8)                                           */
34728  #define R_CAN0_MKIVLR_MB8_Msk           (0x100UL)      /*!< MB8 (Bitfield-Mask: 0x01)                             */
34729  #define R_CAN0_MKIVLR_MB7_Pos           (7UL)          /*!< MB7 (Bit 7)                                           */
34730  #define R_CAN0_MKIVLR_MB7_Msk           (0x80UL)       /*!< MB7 (Bitfield-Mask: 0x01)                             */
34731  #define R_CAN0_MKIVLR_MB6_Pos           (6UL)          /*!< MB6 (Bit 6)                                           */
34732  #define R_CAN0_MKIVLR_MB6_Msk           (0x40UL)       /*!< MB6 (Bitfield-Mask: 0x01)                             */
34733  #define R_CAN0_MKIVLR_MB5_Pos           (5UL)          /*!< MB5 (Bit 5)                                           */
34734  #define R_CAN0_MKIVLR_MB5_Msk           (0x20UL)       /*!< MB5 (Bitfield-Mask: 0x01)                             */
34735  #define R_CAN0_MKIVLR_MB4_Pos           (4UL)          /*!< MB4 (Bit 4)                                           */
34736  #define R_CAN0_MKIVLR_MB4_Msk           (0x10UL)       /*!< MB4 (Bitfield-Mask: 0x01)                             */
34737  #define R_CAN0_MKIVLR_MB3_Pos           (3UL)          /*!< MB3 (Bit 3)                                           */
34738  #define R_CAN0_MKIVLR_MB3_Msk           (0x8UL)        /*!< MB3 (Bitfield-Mask: 0x01)                             */
34739  #define R_CAN0_MKIVLR_MB2_Pos           (2UL)          /*!< MB2 (Bit 2)                                           */
34740  #define R_CAN0_MKIVLR_MB2_Msk           (0x4UL)        /*!< MB2 (Bitfield-Mask: 0x01)                             */
34741  #define R_CAN0_MKIVLR_MB1_Pos           (1UL)          /*!< MB1 (Bit 1)                                           */
34742  #define R_CAN0_MKIVLR_MB1_Msk           (0x2UL)        /*!< MB1 (Bitfield-Mask: 0x01)                             */
34743  #define R_CAN0_MKIVLR_MB0_Pos           (0UL)          /*!< MB0 (Bit 0)                                           */
34744  #define R_CAN0_MKIVLR_MB0_Msk           (0x1UL)        /*!< MB0 (Bitfield-Mask: 0x01)                             */
34745 /* =========================================================  MIER  ========================================================== */
34746  #define R_CAN0_MIER_MB31_Pos            (31UL)         /*!< MB31 (Bit 31)                                         */
34747  #define R_CAN0_MIER_MB31_Msk            (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01)                            */
34748  #define R_CAN0_MIER_MB30_Pos            (30UL)         /*!< MB30 (Bit 30)                                         */
34749  #define R_CAN0_MIER_MB30_Msk            (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01)                            */
34750  #define R_CAN0_MIER_MB29_Pos            (29UL)         /*!< MB29 (Bit 29)                                         */
34751  #define R_CAN0_MIER_MB29_Msk            (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01)                            */
34752  #define R_CAN0_MIER_MB28_Pos            (28UL)         /*!< MB28 (Bit 28)                                         */
34753  #define R_CAN0_MIER_MB28_Msk            (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01)                            */
34754  #define R_CAN0_MIER_MB27_Pos            (27UL)         /*!< MB27 (Bit 27)                                         */
34755  #define R_CAN0_MIER_MB27_Msk            (0x8000000UL)  /*!< MB27 (Bitfield-Mask: 0x01)                            */
34756  #define R_CAN0_MIER_MB26_Pos            (26UL)         /*!< MB26 (Bit 26)                                         */
34757  #define R_CAN0_MIER_MB26_Msk            (0x4000000UL)  /*!< MB26 (Bitfield-Mask: 0x01)                            */
34758  #define R_CAN0_MIER_MB25_Pos            (25UL)         /*!< MB25 (Bit 25)                                         */
34759  #define R_CAN0_MIER_MB25_Msk            (0x2000000UL)  /*!< MB25 (Bitfield-Mask: 0x01)                            */
34760  #define R_CAN0_MIER_MB24_Pos            (24UL)         /*!< MB24 (Bit 24)                                         */
34761  #define R_CAN0_MIER_MB24_Msk            (0x1000000UL)  /*!< MB24 (Bitfield-Mask: 0x01)                            */
34762  #define R_CAN0_MIER_MB23_Pos            (23UL)         /*!< MB23 (Bit 23)                                         */
34763  #define R_CAN0_MIER_MB23_Msk            (0x800000UL)   /*!< MB23 (Bitfield-Mask: 0x01)                            */
34764  #define R_CAN0_MIER_MB22_Pos            (22UL)         /*!< MB22 (Bit 22)                                         */
34765  #define R_CAN0_MIER_MB22_Msk            (0x400000UL)   /*!< MB22 (Bitfield-Mask: 0x01)                            */
34766  #define R_CAN0_MIER_MB21_Pos            (21UL)         /*!< MB21 (Bit 21)                                         */
34767  #define R_CAN0_MIER_MB21_Msk            (0x200000UL)   /*!< MB21 (Bitfield-Mask: 0x01)                            */
34768  #define R_CAN0_MIER_MB20_Pos            (20UL)         /*!< MB20 (Bit 20)                                         */
34769  #define R_CAN0_MIER_MB20_Msk            (0x100000UL)   /*!< MB20 (Bitfield-Mask: 0x01)                            */
34770  #define R_CAN0_MIER_MB19_Pos            (19UL)         /*!< MB19 (Bit 19)                                         */
34771  #define R_CAN0_MIER_MB19_Msk            (0x80000UL)    /*!< MB19 (Bitfield-Mask: 0x01)                            */
34772  #define R_CAN0_MIER_MB18_Pos            (18UL)         /*!< MB18 (Bit 18)                                         */
34773  #define R_CAN0_MIER_MB18_Msk            (0x40000UL)    /*!< MB18 (Bitfield-Mask: 0x01)                            */
34774  #define R_CAN0_MIER_MB17_Pos            (17UL)         /*!< MB17 (Bit 17)                                         */
34775  #define R_CAN0_MIER_MB17_Msk            (0x20000UL)    /*!< MB17 (Bitfield-Mask: 0x01)                            */
34776  #define R_CAN0_MIER_MB16_Pos            (16UL)         /*!< MB16 (Bit 16)                                         */
34777  #define R_CAN0_MIER_MB16_Msk            (0x10000UL)    /*!< MB16 (Bitfield-Mask: 0x01)                            */
34778  #define R_CAN0_MIER_MB15_Pos            (15UL)         /*!< MB15 (Bit 15)                                         */
34779  #define R_CAN0_MIER_MB15_Msk            (0x8000UL)     /*!< MB15 (Bitfield-Mask: 0x01)                            */
34780  #define R_CAN0_MIER_MB14_Pos            (14UL)         /*!< MB14 (Bit 14)                                         */
34781  #define R_CAN0_MIER_MB14_Msk            (0x4000UL)     /*!< MB14 (Bitfield-Mask: 0x01)                            */
34782  #define R_CAN0_MIER_MB13_Pos            (13UL)         /*!< MB13 (Bit 13)                                         */
34783  #define R_CAN0_MIER_MB13_Msk            (0x2000UL)     /*!< MB13 (Bitfield-Mask: 0x01)                            */
34784  #define R_CAN0_MIER_MB12_Pos            (12UL)         /*!< MB12 (Bit 12)                                         */
34785  #define R_CAN0_MIER_MB12_Msk            (0x1000UL)     /*!< MB12 (Bitfield-Mask: 0x01)                            */
34786  #define R_CAN0_MIER_MB11_Pos            (11UL)         /*!< MB11 (Bit 11)                                         */
34787  #define R_CAN0_MIER_MB11_Msk            (0x800UL)      /*!< MB11 (Bitfield-Mask: 0x01)                            */
34788  #define R_CAN0_MIER_MB10_Pos            (10UL)         /*!< MB10 (Bit 10)                                         */
34789  #define R_CAN0_MIER_MB10_Msk            (0x400UL)      /*!< MB10 (Bitfield-Mask: 0x01)                            */
34790  #define R_CAN0_MIER_MB9_Pos             (9UL)          /*!< MB9 (Bit 9)                                           */
34791  #define R_CAN0_MIER_MB9_Msk             (0x200UL)      /*!< MB9 (Bitfield-Mask: 0x01)                             */
34792  #define R_CAN0_MIER_MB8_Pos             (8UL)          /*!< MB8 (Bit 8)                                           */
34793  #define R_CAN0_MIER_MB8_Msk             (0x100UL)      /*!< MB8 (Bitfield-Mask: 0x01)                             */
34794  #define R_CAN0_MIER_MB7_Pos             (7UL)          /*!< MB7 (Bit 7)                                           */
34795  #define R_CAN0_MIER_MB7_Msk             (0x80UL)       /*!< MB7 (Bitfield-Mask: 0x01)                             */
34796  #define R_CAN0_MIER_MB6_Pos             (6UL)          /*!< MB6 (Bit 6)                                           */
34797  #define R_CAN0_MIER_MB6_Msk             (0x40UL)       /*!< MB6 (Bitfield-Mask: 0x01)                             */
34798  #define R_CAN0_MIER_MB5_Pos             (5UL)          /*!< MB5 (Bit 5)                                           */
34799  #define R_CAN0_MIER_MB5_Msk             (0x20UL)       /*!< MB5 (Bitfield-Mask: 0x01)                             */
34800  #define R_CAN0_MIER_MB4_Pos             (4UL)          /*!< MB4 (Bit 4)                                           */
34801  #define R_CAN0_MIER_MB4_Msk             (0x10UL)       /*!< MB4 (Bitfield-Mask: 0x01)                             */
34802  #define R_CAN0_MIER_MB3_Pos             (3UL)          /*!< MB3 (Bit 3)                                           */
34803  #define R_CAN0_MIER_MB3_Msk             (0x8UL)        /*!< MB3 (Bitfield-Mask: 0x01)                             */
34804  #define R_CAN0_MIER_MB2_Pos             (2UL)          /*!< MB2 (Bit 2)                                           */
34805  #define R_CAN0_MIER_MB2_Msk             (0x4UL)        /*!< MB2 (Bitfield-Mask: 0x01)                             */
34806  #define R_CAN0_MIER_MB1_Pos             (1UL)          /*!< MB1 (Bit 1)                                           */
34807  #define R_CAN0_MIER_MB1_Msk             (0x2UL)        /*!< MB1 (Bitfield-Mask: 0x01)                             */
34808  #define R_CAN0_MIER_MB0_Pos             (0UL)          /*!< MB0 (Bit 0)                                           */
34809  #define R_CAN0_MIER_MB0_Msk             (0x1UL)        /*!< MB0 (Bitfield-Mask: 0x01)                             */
34810 /* =======================================================  MIER_FIFO  ======================================================= */
34811  #define R_CAN0_MIER_FIFO_MB29_Pos       (29UL)         /*!< MB29 (Bit 29)                                         */
34812  #define R_CAN0_MIER_FIFO_MB29_Msk       (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01)                            */
34813  #define R_CAN0_MIER_FIFO_MB28_Pos       (28UL)         /*!< MB28 (Bit 28)                                         */
34814  #define R_CAN0_MIER_FIFO_MB28_Msk       (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01)                            */
34815  #define R_CAN0_MIER_FIFO_MB25_Pos       (25UL)         /*!< MB25 (Bit 25)                                         */
34816  #define R_CAN0_MIER_FIFO_MB25_Msk       (0x2000000UL)  /*!< MB25 (Bitfield-Mask: 0x01)                            */
34817  #define R_CAN0_MIER_FIFO_MB24_Pos       (24UL)         /*!< MB24 (Bit 24)                                         */
34818  #define R_CAN0_MIER_FIFO_MB24_Msk       (0x1000000UL)  /*!< MB24 (Bitfield-Mask: 0x01)                            */
34819  #define R_CAN0_MIER_FIFO_MB23_Pos       (23UL)         /*!< MB23 (Bit 23)                                         */
34820  #define R_CAN0_MIER_FIFO_MB23_Msk       (0x800000UL)   /*!< MB23 (Bitfield-Mask: 0x01)                            */
34821  #define R_CAN0_MIER_FIFO_MB22_Pos       (22UL)         /*!< MB22 (Bit 22)                                         */
34822  #define R_CAN0_MIER_FIFO_MB22_Msk       (0x400000UL)   /*!< MB22 (Bitfield-Mask: 0x01)                            */
34823  #define R_CAN0_MIER_FIFO_MB21_Pos       (21UL)         /*!< MB21 (Bit 21)                                         */
34824  #define R_CAN0_MIER_FIFO_MB21_Msk       (0x200000UL)   /*!< MB21 (Bitfield-Mask: 0x01)                            */
34825  #define R_CAN0_MIER_FIFO_MB20_Pos       (20UL)         /*!< MB20 (Bit 20)                                         */
34826  #define R_CAN0_MIER_FIFO_MB20_Msk       (0x100000UL)   /*!< MB20 (Bitfield-Mask: 0x01)                            */
34827  #define R_CAN0_MIER_FIFO_MB19_Pos       (19UL)         /*!< MB19 (Bit 19)                                         */
34828  #define R_CAN0_MIER_FIFO_MB19_Msk       (0x80000UL)    /*!< MB19 (Bitfield-Mask: 0x01)                            */
34829  #define R_CAN0_MIER_FIFO_MB18_Pos       (18UL)         /*!< MB18 (Bit 18)                                         */
34830  #define R_CAN0_MIER_FIFO_MB18_Msk       (0x40000UL)    /*!< MB18 (Bitfield-Mask: 0x01)                            */
34831  #define R_CAN0_MIER_FIFO_MB17_Pos       (17UL)         /*!< MB17 (Bit 17)                                         */
34832  #define R_CAN0_MIER_FIFO_MB17_Msk       (0x20000UL)    /*!< MB17 (Bitfield-Mask: 0x01)                            */
34833  #define R_CAN0_MIER_FIFO_MB16_Pos       (16UL)         /*!< MB16 (Bit 16)                                         */
34834  #define R_CAN0_MIER_FIFO_MB16_Msk       (0x10000UL)    /*!< MB16 (Bitfield-Mask: 0x01)                            */
34835  #define R_CAN0_MIER_FIFO_MB15_Pos       (15UL)         /*!< MB15 (Bit 15)                                         */
34836  #define R_CAN0_MIER_FIFO_MB15_Msk       (0x8000UL)     /*!< MB15 (Bitfield-Mask: 0x01)                            */
34837  #define R_CAN0_MIER_FIFO_MB14_Pos       (14UL)         /*!< MB14 (Bit 14)                                         */
34838  #define R_CAN0_MIER_FIFO_MB14_Msk       (0x4000UL)     /*!< MB14 (Bitfield-Mask: 0x01)                            */
34839  #define R_CAN0_MIER_FIFO_MB13_Pos       (13UL)         /*!< MB13 (Bit 13)                                         */
34840  #define R_CAN0_MIER_FIFO_MB13_Msk       (0x2000UL)     /*!< MB13 (Bitfield-Mask: 0x01)                            */
34841  #define R_CAN0_MIER_FIFO_MB12_Pos       (12UL)         /*!< MB12 (Bit 12)                                         */
34842  #define R_CAN0_MIER_FIFO_MB12_Msk       (0x1000UL)     /*!< MB12 (Bitfield-Mask: 0x01)                            */
34843  #define R_CAN0_MIER_FIFO_MB11_Pos       (11UL)         /*!< MB11 (Bit 11)                                         */
34844  #define R_CAN0_MIER_FIFO_MB11_Msk       (0x800UL)      /*!< MB11 (Bitfield-Mask: 0x01)                            */
34845  #define R_CAN0_MIER_FIFO_MB10_Pos       (10UL)         /*!< MB10 (Bit 10)                                         */
34846  #define R_CAN0_MIER_FIFO_MB10_Msk       (0x400UL)      /*!< MB10 (Bitfield-Mask: 0x01)                            */
34847  #define R_CAN0_MIER_FIFO_MB9_Pos        (9UL)          /*!< MB9 (Bit 9)                                           */
34848  #define R_CAN0_MIER_FIFO_MB9_Msk        (0x200UL)      /*!< MB9 (Bitfield-Mask: 0x01)                             */
34849  #define R_CAN0_MIER_FIFO_MB8_Pos        (8UL)          /*!< MB8 (Bit 8)                                           */
34850  #define R_CAN0_MIER_FIFO_MB8_Msk        (0x100UL)      /*!< MB8 (Bitfield-Mask: 0x01)                             */
34851  #define R_CAN0_MIER_FIFO_MB7_Pos        (7UL)          /*!< MB7 (Bit 7)                                           */
34852  #define R_CAN0_MIER_FIFO_MB7_Msk        (0x80UL)       /*!< MB7 (Bitfield-Mask: 0x01)                             */
34853  #define R_CAN0_MIER_FIFO_MB6_Pos        (6UL)          /*!< MB6 (Bit 6)                                           */
34854  #define R_CAN0_MIER_FIFO_MB6_Msk        (0x40UL)       /*!< MB6 (Bitfield-Mask: 0x01)                             */
34855  #define R_CAN0_MIER_FIFO_MB5_Pos        (5UL)          /*!< MB5 (Bit 5)                                           */
34856  #define R_CAN0_MIER_FIFO_MB5_Msk        (0x20UL)       /*!< MB5 (Bitfield-Mask: 0x01)                             */
34857  #define R_CAN0_MIER_FIFO_MB4_Pos        (4UL)          /*!< MB4 (Bit 4)                                           */
34858  #define R_CAN0_MIER_FIFO_MB4_Msk        (0x10UL)       /*!< MB4 (Bitfield-Mask: 0x01)                             */
34859  #define R_CAN0_MIER_FIFO_MB3_Pos        (3UL)          /*!< MB3 (Bit 3)                                           */
34860  #define R_CAN0_MIER_FIFO_MB3_Msk        (0x8UL)        /*!< MB3 (Bitfield-Mask: 0x01)                             */
34861  #define R_CAN0_MIER_FIFO_MB2_Pos        (2UL)          /*!< MB2 (Bit 2)                                           */
34862  #define R_CAN0_MIER_FIFO_MB2_Msk        (0x4UL)        /*!< MB2 (Bitfield-Mask: 0x01)                             */
34863  #define R_CAN0_MIER_FIFO_MB1_Pos        (1UL)          /*!< MB1 (Bit 1)                                           */
34864  #define R_CAN0_MIER_FIFO_MB1_Msk        (0x2UL)        /*!< MB1 (Bitfield-Mask: 0x01)                             */
34865  #define R_CAN0_MIER_FIFO_MB0_Pos        (0UL)          /*!< MB0 (Bit 0)                                           */
34866  #define R_CAN0_MIER_FIFO_MB0_Msk        (0x1UL)        /*!< MB0 (Bitfield-Mask: 0x01)                             */
34867 /* ========================================================  MCTL_TX  ======================================================== */
34868  #define R_CAN0_MCTL_TX_TRMREQ_Pos       (7UL)          /*!< TRMREQ (Bit 7)                                        */
34869  #define R_CAN0_MCTL_TX_TRMREQ_Msk       (0x80UL)       /*!< TRMREQ (Bitfield-Mask: 0x01)                          */
34870  #define R_CAN0_MCTL_TX_RECREQ_Pos       (6UL)          /*!< RECREQ (Bit 6)                                        */
34871  #define R_CAN0_MCTL_TX_RECREQ_Msk       (0x40UL)       /*!< RECREQ (Bitfield-Mask: 0x01)                          */
34872  #define R_CAN0_MCTL_TX_ONESHOT_Pos      (4UL)          /*!< ONESHOT (Bit 4)                                       */
34873  #define R_CAN0_MCTL_TX_ONESHOT_Msk      (0x10UL)       /*!< ONESHOT (Bitfield-Mask: 0x01)                         */
34874  #define R_CAN0_MCTL_TX_TRMABT_Pos       (2UL)          /*!< TRMABT (Bit 2)                                        */
34875  #define R_CAN0_MCTL_TX_TRMABT_Msk       (0x4UL)        /*!< TRMABT (Bitfield-Mask: 0x01)                          */
34876  #define R_CAN0_MCTL_TX_TRMACTIVE_Pos    (1UL)          /*!< TRMACTIVE (Bit 1)                                     */
34877  #define R_CAN0_MCTL_TX_TRMACTIVE_Msk    (0x2UL)        /*!< TRMACTIVE (Bitfield-Mask: 0x01)                       */
34878  #define R_CAN0_MCTL_TX_SENTDATA_Pos     (0UL)          /*!< SENTDATA (Bit 0)                                      */
34879  #define R_CAN0_MCTL_TX_SENTDATA_Msk     (0x1UL)        /*!< SENTDATA (Bitfield-Mask: 0x01)                        */
34880 /* ========================================================  MCTL_RX  ======================================================== */
34881  #define R_CAN0_MCTL_RX_TRMREQ_Pos       (7UL)          /*!< TRMREQ (Bit 7)                                        */
34882  #define R_CAN0_MCTL_RX_TRMREQ_Msk       (0x80UL)       /*!< TRMREQ (Bitfield-Mask: 0x01)                          */
34883  #define R_CAN0_MCTL_RX_RECREQ_Pos       (6UL)          /*!< RECREQ (Bit 6)                                        */
34884  #define R_CAN0_MCTL_RX_RECREQ_Msk       (0x40UL)       /*!< RECREQ (Bitfield-Mask: 0x01)                          */
34885  #define R_CAN0_MCTL_RX_ONESHOT_Pos      (4UL)          /*!< ONESHOT (Bit 4)                                       */
34886  #define R_CAN0_MCTL_RX_ONESHOT_Msk      (0x10UL)       /*!< ONESHOT (Bitfield-Mask: 0x01)                         */
34887  #define R_CAN0_MCTL_RX_MSGLOST_Pos      (2UL)          /*!< MSGLOST (Bit 2)                                       */
34888  #define R_CAN0_MCTL_RX_MSGLOST_Msk      (0x4UL)        /*!< MSGLOST (Bitfield-Mask: 0x01)                         */
34889  #define R_CAN0_MCTL_RX_INVALDATA_Pos    (1UL)          /*!< INVALDATA (Bit 1)                                     */
34890  #define R_CAN0_MCTL_RX_INVALDATA_Msk    (0x2UL)        /*!< INVALDATA (Bitfield-Mask: 0x01)                       */
34891  #define R_CAN0_MCTL_RX_NEWDATA_Pos      (0UL)          /*!< NEWDATA (Bit 0)                                       */
34892  #define R_CAN0_MCTL_RX_NEWDATA_Msk      (0x1UL)        /*!< NEWDATA (Bitfield-Mask: 0x01)                         */
34893 /* =========================================================  CTLR  ========================================================== */
34894  #define R_CAN0_CTLR_RBOC_Pos            (13UL)         /*!< RBOC (Bit 13)                                         */
34895  #define R_CAN0_CTLR_RBOC_Msk            (0x2000UL)     /*!< RBOC (Bitfield-Mask: 0x01)                            */
34896  #define R_CAN0_CTLR_BOM_Pos             (11UL)         /*!< BOM (Bit 11)                                          */
34897  #define R_CAN0_CTLR_BOM_Msk             (0x1800UL)     /*!< BOM (Bitfield-Mask: 0x03)                             */
34898  #define R_CAN0_CTLR_SLPM_Pos            (10UL)         /*!< SLPM (Bit 10)                                         */
34899  #define R_CAN0_CTLR_SLPM_Msk            (0x400UL)      /*!< SLPM (Bitfield-Mask: 0x01)                            */
34900  #define R_CAN0_CTLR_CANM_Pos            (8UL)          /*!< CANM (Bit 8)                                          */
34901  #define R_CAN0_CTLR_CANM_Msk            (0x300UL)      /*!< CANM (Bitfield-Mask: 0x03)                            */
34902  #define R_CAN0_CTLR_TSPS_Pos            (6UL)          /*!< TSPS (Bit 6)                                          */
34903  #define R_CAN0_CTLR_TSPS_Msk            (0xc0UL)       /*!< TSPS (Bitfield-Mask: 0x03)                            */
34904  #define R_CAN0_CTLR_TSRC_Pos            (5UL)          /*!< TSRC (Bit 5)                                          */
34905  #define R_CAN0_CTLR_TSRC_Msk            (0x20UL)       /*!< TSRC (Bitfield-Mask: 0x01)                            */
34906  #define R_CAN0_CTLR_TPM_Pos             (4UL)          /*!< TPM (Bit 4)                                           */
34907  #define R_CAN0_CTLR_TPM_Msk             (0x10UL)       /*!< TPM (Bitfield-Mask: 0x01)                             */
34908  #define R_CAN0_CTLR_MLM_Pos             (3UL)          /*!< MLM (Bit 3)                                           */
34909  #define R_CAN0_CTLR_MLM_Msk             (0x8UL)        /*!< MLM (Bitfield-Mask: 0x01)                             */
34910  #define R_CAN0_CTLR_IDFM_Pos            (1UL)          /*!< IDFM (Bit 1)                                          */
34911  #define R_CAN0_CTLR_IDFM_Msk            (0x6UL)        /*!< IDFM (Bitfield-Mask: 0x03)                            */
34912  #define R_CAN0_CTLR_MBM_Pos             (0UL)          /*!< MBM (Bit 0)                                           */
34913  #define R_CAN0_CTLR_MBM_Msk             (0x1UL)        /*!< MBM (Bitfield-Mask: 0x01)                             */
34914 /* ==========================================================  STR  ========================================================== */
34915  #define R_CAN0_STR_RECST_Pos            (14UL)         /*!< RECST (Bit 14)                                        */
34916  #define R_CAN0_STR_RECST_Msk            (0x4000UL)     /*!< RECST (Bitfield-Mask: 0x01)                           */
34917  #define R_CAN0_STR_TRMST_Pos            (13UL)         /*!< TRMST (Bit 13)                                        */
34918  #define R_CAN0_STR_TRMST_Msk            (0x2000UL)     /*!< TRMST (Bitfield-Mask: 0x01)                           */
34919  #define R_CAN0_STR_BOST_Pos             (12UL)         /*!< BOST (Bit 12)                                         */
34920  #define R_CAN0_STR_BOST_Msk             (0x1000UL)     /*!< BOST (Bitfield-Mask: 0x01)                            */
34921  #define R_CAN0_STR_EPST_Pos             (11UL)         /*!< EPST (Bit 11)                                         */
34922  #define R_CAN0_STR_EPST_Msk             (0x800UL)      /*!< EPST (Bitfield-Mask: 0x01)                            */
34923  #define R_CAN0_STR_SLPST_Pos            (10UL)         /*!< SLPST (Bit 10)                                        */
34924  #define R_CAN0_STR_SLPST_Msk            (0x400UL)      /*!< SLPST (Bitfield-Mask: 0x01)                           */
34925  #define R_CAN0_STR_HLTST_Pos            (9UL)          /*!< HLTST (Bit 9)                                         */
34926  #define R_CAN0_STR_HLTST_Msk            (0x200UL)      /*!< HLTST (Bitfield-Mask: 0x01)                           */
34927  #define R_CAN0_STR_RSTST_Pos            (8UL)          /*!< RSTST (Bit 8)                                         */
34928  #define R_CAN0_STR_RSTST_Msk            (0x100UL)      /*!< RSTST (Bitfield-Mask: 0x01)                           */
34929  #define R_CAN0_STR_EST_Pos              (7UL)          /*!< EST (Bit 7)                                           */
34930  #define R_CAN0_STR_EST_Msk              (0x80UL)       /*!< EST (Bitfield-Mask: 0x01)                             */
34931  #define R_CAN0_STR_TABST_Pos            (6UL)          /*!< TABST (Bit 6)                                         */
34932  #define R_CAN0_STR_TABST_Msk            (0x40UL)       /*!< TABST (Bitfield-Mask: 0x01)                           */
34933  #define R_CAN0_STR_FMLST_Pos            (5UL)          /*!< FMLST (Bit 5)                                         */
34934  #define R_CAN0_STR_FMLST_Msk            (0x20UL)       /*!< FMLST (Bitfield-Mask: 0x01)                           */
34935  #define R_CAN0_STR_NMLST_Pos            (4UL)          /*!< NMLST (Bit 4)                                         */
34936  #define R_CAN0_STR_NMLST_Msk            (0x10UL)       /*!< NMLST (Bitfield-Mask: 0x01)                           */
34937  #define R_CAN0_STR_TFST_Pos             (3UL)          /*!< TFST (Bit 3)                                          */
34938  #define R_CAN0_STR_TFST_Msk             (0x8UL)        /*!< TFST (Bitfield-Mask: 0x01)                            */
34939  #define R_CAN0_STR_RFST_Pos             (2UL)          /*!< RFST (Bit 2)                                          */
34940  #define R_CAN0_STR_RFST_Msk             (0x4UL)        /*!< RFST (Bitfield-Mask: 0x01)                            */
34941  #define R_CAN0_STR_SDST_Pos             (1UL)          /*!< SDST (Bit 1)                                          */
34942  #define R_CAN0_STR_SDST_Msk             (0x2UL)        /*!< SDST (Bitfield-Mask: 0x01)                            */
34943  #define R_CAN0_STR_NDST_Pos             (0UL)          /*!< NDST (Bit 0)                                          */
34944  #define R_CAN0_STR_NDST_Msk             (0x1UL)        /*!< NDST (Bitfield-Mask: 0x01)                            */
34945 /* ==========================================================  BCR  ========================================================== */
34946  #define R_CAN0_BCR_TSEG1_Pos            (28UL)         /*!< TSEG1 (Bit 28)                                        */
34947  #define R_CAN0_BCR_TSEG1_Msk            (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f)                           */
34948  #define R_CAN0_BCR_BRP_Pos              (16UL)         /*!< BRP (Bit 16)                                          */
34949  #define R_CAN0_BCR_BRP_Msk              (0x3ff0000UL)  /*!< BRP (Bitfield-Mask: 0x3ff)                            */
34950  #define R_CAN0_BCR_SJW_Pos              (12UL)         /*!< SJW (Bit 12)                                          */
34951  #define R_CAN0_BCR_SJW_Msk              (0x3000UL)     /*!< SJW (Bitfield-Mask: 0x03)                             */
34952  #define R_CAN0_BCR_TSEG2_Pos            (8UL)          /*!< TSEG2 (Bit 8)                                         */
34953  #define R_CAN0_BCR_TSEG2_Msk            (0x700UL)      /*!< TSEG2 (Bitfield-Mask: 0x07)                           */
34954  #define R_CAN0_BCR_CCLKS_Pos            (0UL)          /*!< CCLKS (Bit 0)                                         */
34955  #define R_CAN0_BCR_CCLKS_Msk            (0x1UL)        /*!< CCLKS (Bitfield-Mask: 0x01)                           */
34956 /* =========================================================  RFCR  ========================================================== */
34957  #define R_CAN0_RFCR_RFEST_Pos           (7UL)          /*!< RFEST (Bit 7)                                         */
34958  #define R_CAN0_RFCR_RFEST_Msk           (0x80UL)       /*!< RFEST (Bitfield-Mask: 0x01)                           */
34959  #define R_CAN0_RFCR_RFWST_Pos           (6UL)          /*!< RFWST (Bit 6)                                         */
34960  #define R_CAN0_RFCR_RFWST_Msk           (0x40UL)       /*!< RFWST (Bitfield-Mask: 0x01)                           */
34961  #define R_CAN0_RFCR_RFFST_Pos           (5UL)          /*!< RFFST (Bit 5)                                         */
34962  #define R_CAN0_RFCR_RFFST_Msk           (0x20UL)       /*!< RFFST (Bitfield-Mask: 0x01)                           */
34963  #define R_CAN0_RFCR_RFMLF_Pos           (4UL)          /*!< RFMLF (Bit 4)                                         */
34964  #define R_CAN0_RFCR_RFMLF_Msk           (0x10UL)       /*!< RFMLF (Bitfield-Mask: 0x01)                           */
34965  #define R_CAN0_RFCR_RFUST_Pos           (1UL)          /*!< RFUST (Bit 1)                                         */
34966  #define R_CAN0_RFCR_RFUST_Msk           (0xeUL)        /*!< RFUST (Bitfield-Mask: 0x07)                           */
34967  #define R_CAN0_RFCR_RFE_Pos             (0UL)          /*!< RFE (Bit 0)                                           */
34968  #define R_CAN0_RFCR_RFE_Msk             (0x1UL)        /*!< RFE (Bitfield-Mask: 0x01)                             */
34969 /* =========================================================  RFPCR  ========================================================= */
34970  #define R_CAN0_RFPCR_RFPCR_Pos          (0UL)          /*!< RFPCR (Bit 0)                                         */
34971  #define R_CAN0_RFPCR_RFPCR_Msk          (0xffUL)       /*!< RFPCR (Bitfield-Mask: 0xff)                           */
34972 /* =========================================================  TFCR  ========================================================== */
34973  #define R_CAN0_TFCR_TFEST_Pos           (7UL)          /*!< TFEST (Bit 7)                                         */
34974  #define R_CAN0_TFCR_TFEST_Msk           (0x80UL)       /*!< TFEST (Bitfield-Mask: 0x01)                           */
34975  #define R_CAN0_TFCR_TFFST_Pos           (6UL)          /*!< TFFST (Bit 6)                                         */
34976  #define R_CAN0_TFCR_TFFST_Msk           (0x40UL)       /*!< TFFST (Bitfield-Mask: 0x01)                           */
34977  #define R_CAN0_TFCR_TFUST_Pos           (1UL)          /*!< TFUST (Bit 1)                                         */
34978  #define R_CAN0_TFCR_TFUST_Msk           (0xeUL)        /*!< TFUST (Bitfield-Mask: 0x07)                           */
34979  #define R_CAN0_TFCR_TFE_Pos             (0UL)          /*!< TFE (Bit 0)                                           */
34980  #define R_CAN0_TFCR_TFE_Msk             (0x1UL)        /*!< TFE (Bitfield-Mask: 0x01)                             */
34981 /* =========================================================  TFPCR  ========================================================= */
34982  #define R_CAN0_TFPCR_TFPCR_Pos          (0UL)          /*!< TFPCR (Bit 0)                                         */
34983  #define R_CAN0_TFPCR_TFPCR_Msk          (0xffUL)       /*!< TFPCR (Bitfield-Mask: 0xff)                           */
34984 /* =========================================================  EIER  ========================================================== */
34985  #define R_CAN0_EIER_BLIE_Pos            (7UL)          /*!< BLIE (Bit 7)                                          */
34986  #define R_CAN0_EIER_BLIE_Msk            (0x80UL)       /*!< BLIE (Bitfield-Mask: 0x01)                            */
34987  #define R_CAN0_EIER_OLIE_Pos            (6UL)          /*!< OLIE (Bit 6)                                          */
34988  #define R_CAN0_EIER_OLIE_Msk            (0x40UL)       /*!< OLIE (Bitfield-Mask: 0x01)                            */
34989  #define R_CAN0_EIER_ORIE_Pos            (5UL)          /*!< ORIE (Bit 5)                                          */
34990  #define R_CAN0_EIER_ORIE_Msk            (0x20UL)       /*!< ORIE (Bitfield-Mask: 0x01)                            */
34991  #define R_CAN0_EIER_BORIE_Pos           (4UL)          /*!< BORIE (Bit 4)                                         */
34992  #define R_CAN0_EIER_BORIE_Msk           (0x10UL)       /*!< BORIE (Bitfield-Mask: 0x01)                           */
34993  #define R_CAN0_EIER_BOEIE_Pos           (3UL)          /*!< BOEIE (Bit 3)                                         */
34994  #define R_CAN0_EIER_BOEIE_Msk           (0x8UL)        /*!< BOEIE (Bitfield-Mask: 0x01)                           */
34995  #define R_CAN0_EIER_EPIE_Pos            (2UL)          /*!< EPIE (Bit 2)                                          */
34996  #define R_CAN0_EIER_EPIE_Msk            (0x4UL)        /*!< EPIE (Bitfield-Mask: 0x01)                            */
34997  #define R_CAN0_EIER_EWIE_Pos            (1UL)          /*!< EWIE (Bit 1)                                          */
34998  #define R_CAN0_EIER_EWIE_Msk            (0x2UL)        /*!< EWIE (Bitfield-Mask: 0x01)                            */
34999  #define R_CAN0_EIER_BEIE_Pos            (0UL)          /*!< BEIE (Bit 0)                                          */
35000  #define R_CAN0_EIER_BEIE_Msk            (0x1UL)        /*!< BEIE (Bitfield-Mask: 0x01)                            */
35001 /* =========================================================  EIFR  ========================================================== */
35002  #define R_CAN0_EIFR_BLIF_Pos            (7UL)          /*!< BLIF (Bit 7)                                          */
35003  #define R_CAN0_EIFR_BLIF_Msk            (0x80UL)       /*!< BLIF (Bitfield-Mask: 0x01)                            */
35004  #define R_CAN0_EIFR_OLIF_Pos            (6UL)          /*!< OLIF (Bit 6)                                          */
35005  #define R_CAN0_EIFR_OLIF_Msk            (0x40UL)       /*!< OLIF (Bitfield-Mask: 0x01)                            */
35006  #define R_CAN0_EIFR_ORIF_Pos            (5UL)          /*!< ORIF (Bit 5)                                          */
35007  #define R_CAN0_EIFR_ORIF_Msk            (0x20UL)       /*!< ORIF (Bitfield-Mask: 0x01)                            */
35008  #define R_CAN0_EIFR_BORIF_Pos           (4UL)          /*!< BORIF (Bit 4)                                         */
35009  #define R_CAN0_EIFR_BORIF_Msk           (0x10UL)       /*!< BORIF (Bitfield-Mask: 0x01)                           */
35010  #define R_CAN0_EIFR_BOEIF_Pos           (3UL)          /*!< BOEIF (Bit 3)                                         */
35011  #define R_CAN0_EIFR_BOEIF_Msk           (0x8UL)        /*!< BOEIF (Bitfield-Mask: 0x01)                           */
35012  #define R_CAN0_EIFR_EPIF_Pos            (2UL)          /*!< EPIF (Bit 2)                                          */
35013  #define R_CAN0_EIFR_EPIF_Msk            (0x4UL)        /*!< EPIF (Bitfield-Mask: 0x01)                            */
35014  #define R_CAN0_EIFR_EWIF_Pos            (1UL)          /*!< EWIF (Bit 1)                                          */
35015  #define R_CAN0_EIFR_EWIF_Msk            (0x2UL)        /*!< EWIF (Bitfield-Mask: 0x01)                            */
35016  #define R_CAN0_EIFR_BEIF_Pos            (0UL)          /*!< BEIF (Bit 0)                                          */
35017  #define R_CAN0_EIFR_BEIF_Msk            (0x1UL)        /*!< BEIF (Bitfield-Mask: 0x01)                            */
35018 /* =========================================================  RECR  ========================================================== */
35019  #define R_CAN0_RECR_RECR_Pos            (0UL)          /*!< RECR (Bit 0)                                          */
35020  #define R_CAN0_RECR_RECR_Msk            (0xffUL)       /*!< RECR (Bitfield-Mask: 0xff)                            */
35021 /* =========================================================  TECR  ========================================================== */
35022  #define R_CAN0_TECR_TECR_Pos            (0UL)          /*!< TECR (Bit 0)                                          */
35023  #define R_CAN0_TECR_TECR_Msk            (0xffUL)       /*!< TECR (Bitfield-Mask: 0xff)                            */
35024 /* =========================================================  ECSR  ========================================================== */
35025  #define R_CAN0_ECSR_EDPM_Pos            (7UL)          /*!< EDPM (Bit 7)                                          */
35026  #define R_CAN0_ECSR_EDPM_Msk            (0x80UL)       /*!< EDPM (Bitfield-Mask: 0x01)                            */
35027  #define R_CAN0_ECSR_ADEF_Pos            (6UL)          /*!< ADEF (Bit 6)                                          */
35028  #define R_CAN0_ECSR_ADEF_Msk            (0x40UL)       /*!< ADEF (Bitfield-Mask: 0x01)                            */
35029  #define R_CAN0_ECSR_BE0F_Pos            (5UL)          /*!< BE0F (Bit 5)                                          */
35030  #define R_CAN0_ECSR_BE0F_Msk            (0x20UL)       /*!< BE0F (Bitfield-Mask: 0x01)                            */
35031  #define R_CAN0_ECSR_BE1F_Pos            (4UL)          /*!< BE1F (Bit 4)                                          */
35032  #define R_CAN0_ECSR_BE1F_Msk            (0x10UL)       /*!< BE1F (Bitfield-Mask: 0x01)                            */
35033  #define R_CAN0_ECSR_CEF_Pos             (3UL)          /*!< CEF (Bit 3)                                           */
35034  #define R_CAN0_ECSR_CEF_Msk             (0x8UL)        /*!< CEF (Bitfield-Mask: 0x01)                             */
35035  #define R_CAN0_ECSR_AEF_Pos             (2UL)          /*!< AEF (Bit 2)                                           */
35036  #define R_CAN0_ECSR_AEF_Msk             (0x4UL)        /*!< AEF (Bitfield-Mask: 0x01)                             */
35037  #define R_CAN0_ECSR_FEF_Pos             (1UL)          /*!< FEF (Bit 1)                                           */
35038  #define R_CAN0_ECSR_FEF_Msk             (0x2UL)        /*!< FEF (Bitfield-Mask: 0x01)                             */
35039  #define R_CAN0_ECSR_SEF_Pos             (0UL)          /*!< SEF (Bit 0)                                           */
35040  #define R_CAN0_ECSR_SEF_Msk             (0x1UL)        /*!< SEF (Bitfield-Mask: 0x01)                             */
35041 /* =========================================================  CSSR  ========================================================== */
35042  #define R_CAN0_CSSR_CSSR_Pos            (0UL)          /*!< CSSR (Bit 0)                                          */
35043  #define R_CAN0_CSSR_CSSR_Msk            (0xffUL)       /*!< CSSR (Bitfield-Mask: 0xff)                            */
35044 /* =========================================================  MSSR  ========================================================== */
35045  #define R_CAN0_MSSR_SEST_Pos            (7UL)          /*!< SEST (Bit 7)                                          */
35046  #define R_CAN0_MSSR_SEST_Msk            (0x80UL)       /*!< SEST (Bitfield-Mask: 0x01)                            */
35047  #define R_CAN0_MSSR_MBNST_Pos           (0UL)          /*!< MBNST (Bit 0)                                         */
35048  #define R_CAN0_MSSR_MBNST_Msk           (0x1fUL)       /*!< MBNST (Bitfield-Mask: 0x1f)                           */
35049 /* =========================================================  MSMR  ========================================================== */
35050  #define R_CAN0_MSMR_MBSM_Pos            (0UL)          /*!< MBSM (Bit 0)                                          */
35051  #define R_CAN0_MSMR_MBSM_Msk            (0x3UL)        /*!< MBSM (Bitfield-Mask: 0x03)                            */
35052 /* ==========================================================  TSR  ========================================================== */
35053  #define R_CAN0_TSR_TSR_Pos              (0UL)          /*!< TSR (Bit 0)                                           */
35054  #define R_CAN0_TSR_TSR_Msk              (0xffffUL)     /*!< TSR (Bitfield-Mask: 0xffff)                           */
35055 /* =========================================================  AFSR  ========================================================== */
35056  #define R_CAN0_AFSR_AFSR_Pos            (0UL)          /*!< AFSR (Bit 0)                                          */
35057  #define R_CAN0_AFSR_AFSR_Msk            (0xffffUL)     /*!< AFSR (Bitfield-Mask: 0xffff)                          */
35058 /* ==========================================================  TCR  ========================================================== */
35059  #define R_CAN0_TCR_TSTM_Pos             (1UL)          /*!< TSTM (Bit 1)                                          */
35060  #define R_CAN0_TCR_TSTM_Msk             (0x6UL)        /*!< TSTM (Bitfield-Mask: 0x03)                            */
35061  #define R_CAN0_TCR_TSTE_Pos             (0UL)          /*!< TSTE (Bit 0)                                          */
35062  #define R_CAN0_TCR_TSTE_Msk             (0x1UL)        /*!< TSTE (Bitfield-Mask: 0x01)                            */
35063 
35064 /* =========================================================================================================================== */
35065 /* ================                                          R_CANFD                                          ================ */
35066 /* =========================================================================================================================== */
35067 
35068 /* ========================================================  CFDGCFG  ======================================================== */
35069  #define R_CANFD_CFDGCFG_TPRI_Pos                (0UL)          /*!< TPRI (Bit 0)                                          */
35070  #define R_CANFD_CFDGCFG_TPRI_Msk                (0x1UL)        /*!< TPRI (Bitfield-Mask: 0x01)                            */
35071  #define R_CANFD_CFDGCFG_DCE_Pos                 (1UL)          /*!< DCE (Bit 1)                                           */
35072  #define R_CANFD_CFDGCFG_DCE_Msk                 (0x2UL)        /*!< DCE (Bitfield-Mask: 0x01)                             */
35073  #define R_CANFD_CFDGCFG_DRE_Pos                 (2UL)          /*!< DRE (Bit 2)                                           */
35074  #define R_CANFD_CFDGCFG_DRE_Msk                 (0x4UL)        /*!< DRE (Bitfield-Mask: 0x01)                             */
35075  #define R_CANFD_CFDGCFG_MME_Pos                 (3UL)          /*!< MME (Bit 3)                                           */
35076  #define R_CANFD_CFDGCFG_MME_Msk                 (0x8UL)        /*!< MME (Bitfield-Mask: 0x01)                             */
35077  #define R_CANFD_CFDGCFG_DCS_Pos                 (4UL)          /*!< DCS (Bit 4)                                           */
35078  #define R_CANFD_CFDGCFG_DCS_Msk                 (0x10UL)       /*!< DCS (Bitfield-Mask: 0x01)                             */
35079  #define R_CANFD_CFDGCFG_CMPOC_Pos               (5UL)          /*!< CMPOC (Bit 5)                                         */
35080  #define R_CANFD_CFDGCFG_CMPOC_Msk               (0x20UL)       /*!< CMPOC (Bitfield-Mask: 0x01)                           */
35081  #define R_CANFD_CFDGCFG_TSP_Pos                 (8UL)          /*!< TSP (Bit 8)                                           */
35082  #define R_CANFD_CFDGCFG_TSP_Msk                 (0xf00UL)      /*!< TSP (Bitfield-Mask: 0x0f)                             */
35083  #define R_CANFD_CFDGCFG_TSSS_Pos                (12UL)         /*!< TSSS (Bit 12)                                         */
35084  #define R_CANFD_CFDGCFG_TSSS_Msk                (0x1000UL)     /*!< TSSS (Bitfield-Mask: 0x01)                            */
35085  #define R_CANFD_CFDGCFG_TSBTCS_Pos              (13UL)         /*!< TSBTCS (Bit 13)                                       */
35086  #define R_CANFD_CFDGCFG_TSBTCS_Msk              (0xe000UL)     /*!< TSBTCS (Bitfield-Mask: 0x07)                          */
35087  #define R_CANFD_CFDGCFG_ITRCP_Pos               (16UL)         /*!< ITRCP (Bit 16)                                        */
35088  #define R_CANFD_CFDGCFG_ITRCP_Msk               (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff)                         */
35089 /* ========================================================  CFDGCTR  ======================================================== */
35090  #define R_CANFD_CFDGCTR_GMDC_Pos                (0UL)          /*!< GMDC (Bit 0)                                          */
35091  #define R_CANFD_CFDGCTR_GMDC_Msk                (0x3UL)        /*!< GMDC (Bitfield-Mask: 0x03)                            */
35092  #define R_CANFD_CFDGCTR_GSLPR_Pos               (2UL)          /*!< GSLPR (Bit 2)                                         */
35093  #define R_CANFD_CFDGCTR_GSLPR_Msk               (0x4UL)        /*!< GSLPR (Bitfield-Mask: 0x01)                           */
35094  #define R_CANFD_CFDGCTR_DEIE_Pos                (8UL)          /*!< DEIE (Bit 8)                                          */
35095  #define R_CANFD_CFDGCTR_DEIE_Msk                (0x100UL)      /*!< DEIE (Bitfield-Mask: 0x01)                            */
35096  #define R_CANFD_CFDGCTR_MEIE_Pos                (9UL)          /*!< MEIE (Bit 9)                                          */
35097  #define R_CANFD_CFDGCTR_MEIE_Msk                (0x200UL)      /*!< MEIE (Bitfield-Mask: 0x01)                            */
35098  #define R_CANFD_CFDGCTR_THLEIE_Pos              (10UL)         /*!< THLEIE (Bit 10)                                       */
35099  #define R_CANFD_CFDGCTR_THLEIE_Msk              (0x400UL)      /*!< THLEIE (Bitfield-Mask: 0x01)                          */
35100  #define R_CANFD_CFDGCTR_CMPOFIE_Pos             (11UL)         /*!< CMPOFIE (Bit 11)                                      */
35101  #define R_CANFD_CFDGCTR_CMPOFIE_Msk             (0x800UL)      /*!< CMPOFIE (Bitfield-Mask: 0x01)                         */
35102  #define R_CANFD_CFDGCTR_QMEIE_Pos               (14UL)         /*!< QMEIE (Bit 14)                                        */
35103  #define R_CANFD_CFDGCTR_QMEIE_Msk               (0x4000UL)     /*!< QMEIE (Bitfield-Mask: 0x01)                           */
35104  #define R_CANFD_CFDGCTR_MOWEIE_Pos              (15UL)         /*!< MOWEIE (Bit 15)                                       */
35105  #define R_CANFD_CFDGCTR_MOWEIE_Msk              (0x8000UL)     /*!< MOWEIE (Bitfield-Mask: 0x01)                          */
35106  #define R_CANFD_CFDGCTR_TSRST_Pos               (16UL)         /*!< TSRST (Bit 16)                                        */
35107  #define R_CANFD_CFDGCTR_TSRST_Msk               (0x10000UL)    /*!< TSRST (Bitfield-Mask: 0x01)                           */
35108  #define R_CANFD_CFDGCTR_TSWR_Pos                (17UL)         /*!< TSWR (Bit 17)                                         */
35109  #define R_CANFD_CFDGCTR_TSWR_Msk                (0x20000UL)    /*!< TSWR (Bitfield-Mask: 0x01)                            */
35110 /* ========================================================  CFDGSTS  ======================================================== */
35111  #define R_CANFD_CFDGSTS_GRSTSTS_Pos             (0UL)          /*!< GRSTSTS (Bit 0)                                       */
35112  #define R_CANFD_CFDGSTS_GRSTSTS_Msk             (0x1UL)        /*!< GRSTSTS (Bitfield-Mask: 0x01)                         */
35113  #define R_CANFD_CFDGSTS_GHLTSTS_Pos             (1UL)          /*!< GHLTSTS (Bit 1)                                       */
35114  #define R_CANFD_CFDGSTS_GHLTSTS_Msk             (0x2UL)        /*!< GHLTSTS (Bitfield-Mask: 0x01)                         */
35115  #define R_CANFD_CFDGSTS_GSLPSTS_Pos             (2UL)          /*!< GSLPSTS (Bit 2)                                       */
35116  #define R_CANFD_CFDGSTS_GSLPSTS_Msk             (0x4UL)        /*!< GSLPSTS (Bitfield-Mask: 0x01)                         */
35117  #define R_CANFD_CFDGSTS_GRAMINIT_Pos            (3UL)          /*!< GRAMINIT (Bit 3)                                      */
35118  #define R_CANFD_CFDGSTS_GRAMINIT_Msk            (0x8UL)        /*!< GRAMINIT (Bitfield-Mask: 0x01)                        */
35119 /* =======================================================  CFDGERFL  ======================================================== */
35120  #define R_CANFD_CFDGERFL_DEF_Pos                (0UL)          /*!< DEF (Bit 0)                                           */
35121  #define R_CANFD_CFDGERFL_DEF_Msk                (0x1UL)        /*!< DEF (Bitfield-Mask: 0x01)                             */
35122  #define R_CANFD_CFDGERFL_MES_Pos                (1UL)          /*!< MES (Bit 1)                                           */
35123  #define R_CANFD_CFDGERFL_MES_Msk                (0x2UL)        /*!< MES (Bitfield-Mask: 0x01)                             */
35124  #define R_CANFD_CFDGERFL_THLES_Pos              (2UL)          /*!< THLES (Bit 2)                                         */
35125  #define R_CANFD_CFDGERFL_THLES_Msk              (0x4UL)        /*!< THLES (Bitfield-Mask: 0x01)                           */
35126  #define R_CANFD_CFDGERFL_CMPOF_Pos              (3UL)          /*!< CMPOF (Bit 3)                                         */
35127  #define R_CANFD_CFDGERFL_CMPOF_Msk              (0x8UL)        /*!< CMPOF (Bitfield-Mask: 0x01)                           */
35128  #define R_CANFD_CFDGERFL_QOWES_Pos              (4UL)          /*!< QOWES (Bit 4)                                         */
35129  #define R_CANFD_CFDGERFL_QOWES_Msk              (0x10UL)       /*!< QOWES (Bitfield-Mask: 0x01)                           */
35130  #define R_CANFD_CFDGERFL_OTBMLTSTS_Pos          (5UL)          /*!< OTBMLTSTS (Bit 5)                                     */
35131  #define R_CANFD_CFDGERFL_OTBMLTSTS_Msk          (0x20UL)       /*!< OTBMLTSTS (Bitfield-Mask: 0x01)                       */
35132  #define R_CANFD_CFDGERFL_QMES_Pos               (6UL)          /*!< QMES (Bit 6)                                          */
35133  #define R_CANFD_CFDGERFL_QMES_Msk               (0x40UL)       /*!< QMES (Bitfield-Mask: 0x01)                            */
35134  #define R_CANFD_CFDGERFL_RXSFAIL0_Pos           (8UL)          /*!< RXSFAIL0 (Bit 8)                                      */
35135  #define R_CANFD_CFDGERFL_RXSFAIL0_Msk           (0x100UL)      /*!< RXSFAIL0 (Bitfield-Mask: 0x01)                        */
35136  #define R_CANFD_CFDGERFL_RXSFAIL1_Pos           (9UL)          /*!< RXSFAIL1 (Bit 9)                                      */
35137  #define R_CANFD_CFDGERFL_RXSFAIL1_Msk           (0x200UL)      /*!< RXSFAIL1 (Bitfield-Mask: 0x01)                        */
35138  #define R_CANFD_CFDGERFL_EEF0_Pos               (16UL)         /*!< EEF0 (Bit 16)                                         */
35139  #define R_CANFD_CFDGERFL_EEF0_Msk               (0x10000UL)    /*!< EEF0 (Bitfield-Mask: 0x01)                            */
35140  #define R_CANFD_CFDGERFL_EEF1_Pos               (17UL)         /*!< EEF1 (Bit 17)                                         */
35141  #define R_CANFD_CFDGERFL_EEF1_Msk               (0x20000UL)    /*!< EEF1 (Bitfield-Mask: 0x01)                            */
35142 /* ========================================================  CFDGTSC  ======================================================== */
35143  #define R_CANFD_CFDGTSC_TS_Pos                  (0UL)          /*!< TS (Bit 0)                                            */
35144  #define R_CANFD_CFDGTSC_TS_Msk                  (0xffffUL)     /*!< TS (Bitfield-Mask: 0xffff)                            */
35145 /* ======================================================  CFDGAFLECTR  ====================================================== */
35146  #define R_CANFD_CFDGAFLECTR_AFLPN_Pos           (0UL)          /*!< AFLPN (Bit 0)                                         */
35147  #define R_CANFD_CFDGAFLECTR_AFLPN_Msk           (0xfUL)        /*!< AFLPN (Bitfield-Mask: 0x0f)                           */
35148  #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos          (8UL)          /*!< AFLDAE (Bit 8)                                        */
35149  #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk          (0x100UL)      /*!< AFLDAE (Bitfield-Mask: 0x01)                          */
35150 /* ======================================================  CFDGAFLCFG0  ====================================================== */
35151  #define R_CANFD_CFDGAFLCFG0_RNC1_Pos            (0UL)          /*!< RNC1 (Bit 0)                                          */
35152  #define R_CANFD_CFDGAFLCFG0_RNC1_Msk            (0x1ffUL)      /*!< RNC1 (Bitfield-Mask: 0x1ff)                           */
35153  #define R_CANFD_CFDGAFLCFG0_RNC0_Pos            (16UL)         /*!< RNC0 (Bit 16)                                         */
35154  #define R_CANFD_CFDGAFLCFG0_RNC0_Msk            (0x1ff0000UL)  /*!< RNC0 (Bitfield-Mask: 0x1ff)                           */
35155 /* ========================================================  CFDRMNB  ======================================================== */
35156  #define R_CANFD_CFDRMNB_NRXMB_Pos               (0UL)          /*!< NRXMB (Bit 0)                                         */
35157  #define R_CANFD_CFDRMNB_NRXMB_Msk               (0xffUL)       /*!< NRXMB (Bitfield-Mask: 0xff)                           */
35158  #define R_CANFD_CFDRMNB_RMPLS_Pos               (8UL)          /*!< RMPLS (Bit 8)                                         */
35159  #define R_CANFD_CFDRMNB_RMPLS_Msk               (0x700UL)      /*!< RMPLS (Bitfield-Mask: 0x07)                           */
35160 /* =======================================================  CFDRMND0  ======================================================== */
35161  #define R_CANFD_CFDRMND0_RMNSu_Pos              (0UL)          /*!< RMNSu (Bit 0)                                         */
35162  #define R_CANFD_CFDRMND0_RMNSu_Msk              (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff)                     */
35163 /* ========================================================  CFDRFCC  ======================================================== */
35164  #define R_CANFD_CFDRFCC_RFE_Pos                 (0UL)          /*!< RFE (Bit 0)                                           */
35165  #define R_CANFD_CFDRFCC_RFE_Msk                 (0x1UL)        /*!< RFE (Bitfield-Mask: 0x01)                             */
35166  #define R_CANFD_CFDRFCC_RFIE_Pos                (1UL)          /*!< RFIE (Bit 1)                                          */
35167  #define R_CANFD_CFDRFCC_RFIE_Msk                (0x2UL)        /*!< RFIE (Bitfield-Mask: 0x01)                            */
35168  #define R_CANFD_CFDRFCC_RFPLS_Pos               (4UL)          /*!< RFPLS (Bit 4)                                         */
35169  #define R_CANFD_CFDRFCC_RFPLS_Msk               (0x70UL)       /*!< RFPLS (Bitfield-Mask: 0x07)                           */
35170  #define R_CANFD_CFDRFCC_RFDC_Pos                (8UL)          /*!< RFDC (Bit 8)                                          */
35171  #define R_CANFD_CFDRFCC_RFDC_Msk                (0x700UL)      /*!< RFDC (Bitfield-Mask: 0x07)                            */
35172  #define R_CANFD_CFDRFCC_RFIM_Pos                (12UL)         /*!< RFIM (Bit 12)                                         */
35173  #define R_CANFD_CFDRFCC_RFIM_Msk                (0x1000UL)     /*!< RFIM (Bitfield-Mask: 0x01)                            */
35174  #define R_CANFD_CFDRFCC_RFIGCV_Pos              (13UL)         /*!< RFIGCV (Bit 13)                                       */
35175  #define R_CANFD_CFDRFCC_RFIGCV_Msk              (0xe000UL)     /*!< RFIGCV (Bitfield-Mask: 0x07)                          */
35176  #define R_CANFD_CFDRFCC_RFFIE_Pos               (16UL)         /*!< RFFIE (Bit 16)                                        */
35177  #define R_CANFD_CFDRFCC_RFFIE_Msk               (0x10000UL)    /*!< RFFIE (Bitfield-Mask: 0x01)                           */
35178 /* =======================================================  CFDRFSTS  ======================================================== */
35179  #define R_CANFD_CFDRFSTS_RFEMP_Pos              (0UL)          /*!< RFEMP (Bit 0)                                         */
35180  #define R_CANFD_CFDRFSTS_RFEMP_Msk              (0x1UL)        /*!< RFEMP (Bitfield-Mask: 0x01)                           */
35181  #define R_CANFD_CFDRFSTS_RFFLL_Pos              (1UL)          /*!< RFFLL (Bit 1)                                         */
35182  #define R_CANFD_CFDRFSTS_RFFLL_Msk              (0x2UL)        /*!< RFFLL (Bitfield-Mask: 0x01)                           */
35183  #define R_CANFD_CFDRFSTS_RFMLT_Pos              (2UL)          /*!< RFMLT (Bit 2)                                         */
35184  #define R_CANFD_CFDRFSTS_RFMLT_Msk              (0x4UL)        /*!< RFMLT (Bitfield-Mask: 0x01)                           */
35185  #define R_CANFD_CFDRFSTS_RFIF_Pos               (3UL)          /*!< RFIF (Bit 3)                                          */
35186  #define R_CANFD_CFDRFSTS_RFIF_Msk               (0x8UL)        /*!< RFIF (Bitfield-Mask: 0x01)                            */
35187  #define R_CANFD_CFDRFSTS_RFMC_Pos               (8UL)          /*!< RFMC (Bit 8)                                          */
35188  #define R_CANFD_CFDRFSTS_RFMC_Msk               (0xff00UL)     /*!< RFMC (Bitfield-Mask: 0xff)                            */
35189  #define R_CANFD_CFDRFSTS_RFFIF_Pos              (16UL)         /*!< RFFIF (Bit 16)                                        */
35190  #define R_CANFD_CFDRFSTS_RFFIF_Msk              (0x10000UL)    /*!< RFFIF (Bitfield-Mask: 0x01)                           */
35191 /* =======================================================  CFDRFPCTR  ======================================================= */
35192  #define R_CANFD_CFDRFPCTR_RFPC_Pos              (0UL)          /*!< RFPC (Bit 0)                                          */
35193  #define R_CANFD_CFDRFPCTR_RFPC_Msk              (0xffUL)       /*!< RFPC (Bitfield-Mask: 0xff)                            */
35194 /* ========================================================  CFDCFCC  ======================================================== */
35195  #define R_CANFD_CFDCFCC_CFE_Pos                 (0UL)          /*!< CFE (Bit 0)                                           */
35196  #define R_CANFD_CFDCFCC_CFE_Msk                 (0x1UL)        /*!< CFE (Bitfield-Mask: 0x01)                             */
35197  #define R_CANFD_CFDCFCC_CFRXIE_Pos              (1UL)          /*!< CFRXIE (Bit 1)                                        */
35198  #define R_CANFD_CFDCFCC_CFRXIE_Msk              (0x2UL)        /*!< CFRXIE (Bitfield-Mask: 0x01)                          */
35199  #define R_CANFD_CFDCFCC_CFTXIE_Pos              (2UL)          /*!< CFTXIE (Bit 2)                                        */
35200  #define R_CANFD_CFDCFCC_CFTXIE_Msk              (0x4UL)        /*!< CFTXIE (Bitfield-Mask: 0x01)                          */
35201  #define R_CANFD_CFDCFCC_CFPLS_Pos               (4UL)          /*!< CFPLS (Bit 4)                                         */
35202  #define R_CANFD_CFDCFCC_CFPLS_Msk               (0x70UL)       /*!< CFPLS (Bitfield-Mask: 0x07)                           */
35203  #define R_CANFD_CFDCFCC_CFM_Pos                 (8UL)          /*!< CFM (Bit 8)                                           */
35204  #define R_CANFD_CFDCFCC_CFM_Msk                 (0x300UL)      /*!< CFM (Bitfield-Mask: 0x03)                             */
35205  #define R_CANFD_CFDCFCC_CFITSS_Pos              (10UL)         /*!< CFITSS (Bit 10)                                       */
35206  #define R_CANFD_CFDCFCC_CFITSS_Msk              (0x400UL)      /*!< CFITSS (Bitfield-Mask: 0x01)                          */
35207  #define R_CANFD_CFDCFCC_CFITR_Pos               (11UL)         /*!< CFITR (Bit 11)                                        */
35208  #define R_CANFD_CFDCFCC_CFITR_Msk               (0x800UL)      /*!< CFITR (Bitfield-Mask: 0x01)                           */
35209  #define R_CANFD_CFDCFCC_CFIM_Pos                (12UL)         /*!< CFIM (Bit 12)                                         */
35210  #define R_CANFD_CFDCFCC_CFIM_Msk                (0x1000UL)     /*!< CFIM (Bitfield-Mask: 0x01)                            */
35211  #define R_CANFD_CFDCFCC_CFIGCV_Pos              (13UL)         /*!< CFIGCV (Bit 13)                                       */
35212  #define R_CANFD_CFDCFCC_CFIGCV_Msk              (0xe000UL)     /*!< CFIGCV (Bitfield-Mask: 0x07)                          */
35213  #define R_CANFD_CFDCFCC_CFTML_Pos               (16UL)         /*!< CFTML (Bit 16)                                        */
35214  #define R_CANFD_CFDCFCC_CFTML_Msk               (0x1f0000UL)   /*!< CFTML (Bitfield-Mask: 0x1f)                           */
35215  #define R_CANFD_CFDCFCC_CFDC_Pos                (21UL)         /*!< CFDC (Bit 21)                                         */
35216  #define R_CANFD_CFDCFCC_CFDC_Msk                (0xe00000UL)   /*!< CFDC (Bitfield-Mask: 0x07)                            */
35217  #define R_CANFD_CFDCFCC_CFITT_Pos               (24UL)         /*!< CFITT (Bit 24)                                        */
35218  #define R_CANFD_CFDCFCC_CFITT_Msk               (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff)                           */
35219 /* =======================================================  CFDCFCCE  ======================================================== */
35220  #define R_CANFD_CFDCFCCE_CFFIE_Pos              (0UL)          /*!< CFFIE (Bit 0)                                         */
35221  #define R_CANFD_CFDCFCCE_CFFIE_Msk              (0x1UL)        /*!< CFFIE (Bitfield-Mask: 0x01)                           */
35222  #define R_CANFD_CFDCFCCE_CFOFRXIE_Pos           (1UL)          /*!< CFOFRXIE (Bit 1)                                      */
35223  #define R_CANFD_CFDCFCCE_CFOFRXIE_Msk           (0x2UL)        /*!< CFOFRXIE (Bitfield-Mask: 0x01)                        */
35224  #define R_CANFD_CFDCFCCE_CFOFTXIE_Pos           (2UL)          /*!< CFOFTXIE (Bit 2)                                      */
35225  #define R_CANFD_CFDCFCCE_CFOFTXIE_Msk           (0x4UL)        /*!< CFOFTXIE (Bitfield-Mask: 0x01)                        */
35226  #define R_CANFD_CFDCFCCE_CFMOWM_Pos             (8UL)          /*!< CFMOWM (Bit 8)                                        */
35227  #define R_CANFD_CFDCFCCE_CFMOWM_Msk             (0x100UL)      /*!< CFMOWM (Bitfield-Mask: 0x01)                          */
35228  #define R_CANFD_CFDCFCCE_CFBME_Pos              (16UL)         /*!< CFBME (Bit 16)                                        */
35229  #define R_CANFD_CFDCFCCE_CFBME_Msk              (0x10000UL)    /*!< CFBME (Bitfield-Mask: 0x01)                           */
35230 /* =======================================================  CFDCFSTS  ======================================================== */
35231  #define R_CANFD_CFDCFSTS_CFEMP_Pos              (0UL)          /*!< CFEMP (Bit 0)                                         */
35232  #define R_CANFD_CFDCFSTS_CFEMP_Msk              (0x1UL)        /*!< CFEMP (Bitfield-Mask: 0x01)                           */
35233  #define R_CANFD_CFDCFSTS_CFFLL_Pos              (1UL)          /*!< CFFLL (Bit 1)                                         */
35234  #define R_CANFD_CFDCFSTS_CFFLL_Msk              (0x2UL)        /*!< CFFLL (Bitfield-Mask: 0x01)                           */
35235  #define R_CANFD_CFDCFSTS_CFMLT_Pos              (2UL)          /*!< CFMLT (Bit 2)                                         */
35236  #define R_CANFD_CFDCFSTS_CFMLT_Msk              (0x4UL)        /*!< CFMLT (Bitfield-Mask: 0x01)                           */
35237  #define R_CANFD_CFDCFSTS_CFRXIF_Pos             (3UL)          /*!< CFRXIF (Bit 3)                                        */
35238  #define R_CANFD_CFDCFSTS_CFRXIF_Msk             (0x8UL)        /*!< CFRXIF (Bitfield-Mask: 0x01)                          */
35239  #define R_CANFD_CFDCFSTS_CFTXIF_Pos             (4UL)          /*!< CFTXIF (Bit 4)                                        */
35240  #define R_CANFD_CFDCFSTS_CFTXIF_Msk             (0x10UL)       /*!< CFTXIF (Bitfield-Mask: 0x01)                          */
35241  #define R_CANFD_CFDCFSTS_CFMC_Pos               (8UL)          /*!< CFMC (Bit 8)                                          */
35242  #define R_CANFD_CFDCFSTS_CFMC_Msk               (0xff00UL)     /*!< CFMC (Bitfield-Mask: 0xff)                            */
35243  #define R_CANFD_CFDCFSTS_CFFIF_Pos              (16UL)         /*!< CFFIF (Bit 16)                                        */
35244  #define R_CANFD_CFDCFSTS_CFFIF_Msk              (0x10000UL)    /*!< CFFIF (Bitfield-Mask: 0x01)                           */
35245  #define R_CANFD_CFDCFSTS_CFOFRXIF_Pos           (17UL)         /*!< CFOFRXIF (Bit 17)                                     */
35246  #define R_CANFD_CFDCFSTS_CFOFRXIF_Msk           (0x20000UL)    /*!< CFOFRXIF (Bitfield-Mask: 0x01)                        */
35247  #define R_CANFD_CFDCFSTS_CFOFTXIF_Pos           (18UL)         /*!< CFOFTXIF (Bit 18)                                     */
35248  #define R_CANFD_CFDCFSTS_CFOFTXIF_Msk           (0x40000UL)    /*!< CFOFTXIF (Bitfield-Mask: 0x01)                        */
35249  #define R_CANFD_CFDCFSTS_CFMOW_Pos              (24UL)         /*!< CFMOW (Bit 24)                                        */
35250  #define R_CANFD_CFDCFSTS_CFMOW_Msk              (0x1000000UL)  /*!< CFMOW (Bitfield-Mask: 0x01)                           */
35251 /* =======================================================  CFDCFPCTR  ======================================================= */
35252  #define R_CANFD_CFDCFPCTR_CFPC_Pos              (0UL)          /*!< CFPC (Bit 0)                                          */
35253  #define R_CANFD_CFDCFPCTR_CFPC_Msk              (0xffUL)       /*!< CFPC (Bitfield-Mask: 0xff)                            */
35254 /* =======================================================  CFDFESTS  ======================================================== */
35255  #define R_CANFD_CFDFESTS_RFXEMP_Pos             (0UL)          /*!< RFXEMP (Bit 0)                                        */
35256  #define R_CANFD_CFDFESTS_RFXEMP_Msk             (0xffUL)       /*!< RFXEMP (Bitfield-Mask: 0xff)                          */
35257  #define R_CANFD_CFDFESTS_CFXEMP_Pos             (8UL)          /*!< CFXEMP (Bit 8)                                        */
35258  #define R_CANFD_CFDFESTS_CFXEMP_Msk             (0x3f00UL)     /*!< CFXEMP (Bitfield-Mask: 0x3f)                          */
35259 /* =======================================================  CFDFFSTS  ======================================================== */
35260  #define R_CANFD_CFDFFSTS_RFXFLL_Pos             (0UL)          /*!< RFXFLL (Bit 0)                                        */
35261  #define R_CANFD_CFDFFSTS_RFXFLL_Msk             (0xffUL)       /*!< RFXFLL (Bitfield-Mask: 0xff)                          */
35262  #define R_CANFD_CFDFFSTS_CFXFLL_Pos             (8UL)          /*!< CFXFLL (Bit 8)                                        */
35263  #define R_CANFD_CFDFFSTS_CFXFLL_Msk             (0x3f00UL)     /*!< CFXFLL (Bitfield-Mask: 0x3f)                          */
35264 /* =======================================================  CFDFMSTS  ======================================================== */
35265  #define R_CANFD_CFDFMSTS_RFXMLT_Pos             (0UL)          /*!< RFXMLT (Bit 0)                                        */
35266  #define R_CANFD_CFDFMSTS_RFXMLT_Msk             (0xffUL)       /*!< RFXMLT (Bitfield-Mask: 0xff)                          */
35267  #define R_CANFD_CFDFMSTS_CFXMLT_Pos             (8UL)          /*!< CFXMLT (Bit 8)                                        */
35268  #define R_CANFD_CFDFMSTS_CFXMLT_Msk             (0x3f00UL)     /*!< CFXMLT (Bitfield-Mask: 0x3f)                          */
35269 /* =======================================================  CFDRFISTS  ======================================================= */
35270  #define R_CANFD_CFDRFISTS_RFXIF_Pos             (0UL)          /*!< RFXIF (Bit 0)                                         */
35271  #define R_CANFD_CFDRFISTS_RFXIF_Msk             (0xffUL)       /*!< RFXIF (Bitfield-Mask: 0xff)                           */
35272  #define R_CANFD_CFDRFISTS_RFXFFLL_Pos           (16UL)         /*!< RFXFFLL (Bit 16)                                      */
35273  #define R_CANFD_CFDRFISTS_RFXFFLL_Msk           (0xff0000UL)   /*!< RFXFFLL (Bitfield-Mask: 0xff)                         */
35274 /* ======================================================  CFDCFRISTS  ======================================================= */
35275  #define R_CANFD_CFDCFRISTS_CFXRXIF_Pos          (0UL)          /*!< CFXRXIF (Bit 0)                                       */
35276  #define R_CANFD_CFDCFRISTS_CFXRXIF_Msk          (0x3fUL)       /*!< CFXRXIF (Bitfield-Mask: 0x3f)                         */
35277 /* ======================================================  CFDCFTISTS  ======================================================= */
35278  #define R_CANFD_CFDCFTISTS_CFXTXIF_Pos          (0UL)          /*!< CFXTXIF (Bit 0)                                       */
35279  #define R_CANFD_CFDCFTISTS_CFXTXIF_Msk          (0x3fUL)       /*!< CFXTXIF (Bitfield-Mask: 0x3f)                         */
35280 /* =====================================================  CFDCFOFRISTS  ====================================================== */
35281  #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Pos      (0UL)          /*!< CFXOFRXIF (Bit 0)                                     */
35282  #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Msk      (0x3fUL)       /*!< CFXOFRXIF (Bitfield-Mask: 0x3f)                       */
35283 /* =====================================================  CFDCFOFTISTS  ====================================================== */
35284  #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Pos      (0UL)          /*!< CFXOFTXIF (Bit 0)                                     */
35285  #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Msk      (0x3fUL)       /*!< CFXOFTXIF (Bitfield-Mask: 0x3f)                       */
35286 /* ======================================================  CFDCFMOWSTS  ====================================================== */
35287  #define R_CANFD_CFDCFMOWSTS_CFXMOW_Pos          (0UL)          /*!< CFXMOW (Bit 0)                                        */
35288  #define R_CANFD_CFDCFMOWSTS_CFXMOW_Msk          (0x3fUL)       /*!< CFXMOW (Bitfield-Mask: 0x3f)                          */
35289 /* =======================================================  CFDFFFSTS  ======================================================= */
35290  #define R_CANFD_CFDFFFSTS_RFXFFLL_Pos           (0UL)          /*!< RFXFFLL (Bit 0)                                       */
35291  #define R_CANFD_CFDFFFSTS_RFXFFLL_Msk           (0xffUL)       /*!< RFXFFLL (Bitfield-Mask: 0xff)                         */
35292  #define R_CANFD_CFDFFFSTS_CFXFFLL_Pos           (8UL)          /*!< CFXFFLL (Bit 8)                                       */
35293  #define R_CANFD_CFDFFFSTS_CFXFFLL_Msk           (0x3f00UL)     /*!< CFXFFLL (Bitfield-Mask: 0x3f)                         */
35294 /* ========================================================  CFDTMC  ========================================================= */
35295  #define R_CANFD_CFDTMC_TMTR_Pos                 (0UL)          /*!< TMTR (Bit 0)                                          */
35296  #define R_CANFD_CFDTMC_TMTR_Msk                 (0x1UL)        /*!< TMTR (Bitfield-Mask: 0x01)                            */
35297  #define R_CANFD_CFDTMC_TMTAR_Pos                (1UL)          /*!< TMTAR (Bit 1)                                         */
35298  #define R_CANFD_CFDTMC_TMTAR_Msk                (0x2UL)        /*!< TMTAR (Bitfield-Mask: 0x01)                           */
35299  #define R_CANFD_CFDTMC_TMOM_Pos                 (2UL)          /*!< TMOM (Bit 2)                                          */
35300  #define R_CANFD_CFDTMC_TMOM_Msk                 (0x4UL)        /*!< TMOM (Bitfield-Mask: 0x01)                            */
35301 /* =======================================================  CFDTMSTS  ======================================================== */
35302  #define R_CANFD_CFDTMSTS_TMTSTS_Pos             (0UL)          /*!< TMTSTS (Bit 0)                                        */
35303  #define R_CANFD_CFDTMSTS_TMTSTS_Msk             (0x1UL)        /*!< TMTSTS (Bitfield-Mask: 0x01)                          */
35304  #define R_CANFD_CFDTMSTS_TMTRF_Pos              (1UL)          /*!< TMTRF (Bit 1)                                         */
35305  #define R_CANFD_CFDTMSTS_TMTRF_Msk              (0x6UL)        /*!< TMTRF (Bitfield-Mask: 0x03)                           */
35306  #define R_CANFD_CFDTMSTS_TMTRM_Pos              (3UL)          /*!< TMTRM (Bit 3)                                         */
35307  #define R_CANFD_CFDTMSTS_TMTRM_Msk              (0x8UL)        /*!< TMTRM (Bitfield-Mask: 0x01)                           */
35308  #define R_CANFD_CFDTMSTS_TMTARM_Pos             (4UL)          /*!< TMTARM (Bit 4)                                        */
35309  #define R_CANFD_CFDTMSTS_TMTARM_Msk             (0x10UL)       /*!< TMTARM (Bitfield-Mask: 0x01)                          */
35310 /* ======================================================  CFDTMTRSTS  ======================================================= */
35311  #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos      (0UL)          /*!< CFDTMTRSTSg (Bit 0)                                   */
35312  #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk      (0xffUL)       /*!< CFDTMTRSTSg (Bitfield-Mask: 0xff)                     */
35313 /* ======================================================  CFDTMTARSTS  ====================================================== */
35314  #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos    (0UL)          /*!< CFDTMTARSTSg (Bit 0)                                  */
35315  #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk    (0xffUL)       /*!< CFDTMTARSTSg (Bitfield-Mask: 0xff)                    */
35316 /* ======================================================  CFDTMTCSTS  ======================================================= */
35317  #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos      (0UL)          /*!< CFDTMTCSTSg (Bit 0)                                   */
35318  #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk      (0xffUL)       /*!< CFDTMTCSTSg (Bitfield-Mask: 0xff)                     */
35319 /* ======================================================  CFDTMTASTS  ======================================================= */
35320  #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos      (0UL)          /*!< CFDTMTASTSg (Bit 0)                                   */
35321  #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk      (0xffUL)       /*!< CFDTMTASTSg (Bitfield-Mask: 0xff)                     */
35322 /* =======================================================  CFDTMIEC  ======================================================== */
35323  #define R_CANFD_CFDTMIEC_TMIEg_Pos              (0UL)          /*!< TMIEg (Bit 0)                                         */
35324  #define R_CANFD_CFDTMIEC_TMIEg_Msk              (0xffUL)       /*!< TMIEg (Bitfield-Mask: 0xff)                           */
35325 /* =======================================================  CFDTXQCC0  ======================================================= */
35326  #define R_CANFD_CFDTXQCC0_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
35327  #define R_CANFD_CFDTXQCC0_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
35328  #define R_CANFD_CFDTXQCC0_TXQGWE_Pos            (1UL)          /*!< TXQGWE (Bit 1)                                        */
35329  #define R_CANFD_CFDTXQCC0_TXQGWE_Msk            (0x2UL)        /*!< TXQGWE (Bitfield-Mask: 0x01)                          */
35330  #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
35331  #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
35332  #define R_CANFD_CFDTXQCC0_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
35333  #define R_CANFD_CFDTXQCC0_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
35334  #define R_CANFD_CFDTXQCC0_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
35335  #define R_CANFD_CFDTXQCC0_TXQDC_Msk             (0x1f00UL)     /*!< TXQDC (Bitfield-Mask: 0x1f)                           */
35336  #define R_CANFD_CFDTXQCC0_TXQFIE_Pos            (16UL)         /*!< TXQFIE (Bit 16)                                       */
35337  #define R_CANFD_CFDTXQCC0_TXQFIE_Msk            (0x10000UL)    /*!< TXQFIE (Bitfield-Mask: 0x01)                          */
35338  #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Pos         (17UL)         /*!< TXQOFRXIE (Bit 17)                                    */
35339  #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Msk         (0x20000UL)    /*!< TXQOFRXIE (Bitfield-Mask: 0x01)                       */
35340  #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Pos         (18UL)         /*!< TXQOFTXIE (Bit 18)                                    */
35341  #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Msk         (0x40000UL)    /*!< TXQOFTXIE (Bitfield-Mask: 0x01)                       */
35342 /* ======================================================  CFDTXQSTS0  ======================================================= */
35343  #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
35344  #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
35345  #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
35346  #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
35347  #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
35348  #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
35349  #define R_CANFD_CFDTXQSTS0_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
35350  #define R_CANFD_CFDTXQSTS0_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
35351  #define R_CANFD_CFDTXQSTS0_TXQFIF_Pos           (16UL)         /*!< TXQFIF (Bit 16)                                       */
35352  #define R_CANFD_CFDTXQSTS0_TXQFIF_Msk           (0x10000UL)    /*!< TXQFIF (Bitfield-Mask: 0x01)                          */
35353  #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Pos        (17UL)         /*!< TXQOFRXIF (Bit 17)                                    */
35354  #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Msk        (0x20000UL)    /*!< TXQOFRXIF (Bitfield-Mask: 0x01)                       */
35355  #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Pos        (18UL)         /*!< TXQOFTXIF (Bit 18)                                    */
35356  #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Msk        (0x40000UL)    /*!< TXQOFTXIF (Bitfield-Mask: 0x01)                       */
35357  #define R_CANFD_CFDTXQSTS0_TXQMLT_Pos           (19UL)         /*!< TXQMLT (Bit 19)                                       */
35358  #define R_CANFD_CFDTXQSTS0_TXQMLT_Msk           (0x80000UL)    /*!< TXQMLT (Bitfield-Mask: 0x01)                          */
35359 /* ======================================================  CFDTXQPCTR0  ====================================================== */
35360  #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
35361  #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
35362 /* =======================================================  CFDTXQCC1  ======================================================= */
35363  #define R_CANFD_CFDTXQCC1_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
35364  #define R_CANFD_CFDTXQCC1_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
35365  #define R_CANFD_CFDTXQCC1_TXQGWE_Pos            (1UL)          /*!< TXQGWE (Bit 1)                                        */
35366  #define R_CANFD_CFDTXQCC1_TXQGWE_Msk            (0x2UL)        /*!< TXQGWE (Bitfield-Mask: 0x01)                          */
35367  #define R_CANFD_CFDTXQCC1_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
35368  #define R_CANFD_CFDTXQCC1_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
35369  #define R_CANFD_CFDTXQCC1_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
35370  #define R_CANFD_CFDTXQCC1_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
35371  #define R_CANFD_CFDTXQCC1_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
35372  #define R_CANFD_CFDTXQCC1_TXQDC_Msk             (0x1f00UL)     /*!< TXQDC (Bitfield-Mask: 0x1f)                           */
35373  #define R_CANFD_CFDTXQCC1_TXQFIE_Pos            (16UL)         /*!< TXQFIE (Bit 16)                                       */
35374  #define R_CANFD_CFDTXQCC1_TXQFIE_Msk            (0x10000UL)    /*!< TXQFIE (Bitfield-Mask: 0x01)                          */
35375  #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Pos         (17UL)         /*!< TXQOFRXIE (Bit 17)                                    */
35376  #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Msk         (0x20000UL)    /*!< TXQOFRXIE (Bitfield-Mask: 0x01)                       */
35377  #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Pos         (18UL)         /*!< TXQOFTXIE (Bit 18)                                    */
35378  #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Msk         (0x40000UL)    /*!< TXQOFTXIE (Bitfield-Mask: 0x01)                       */
35379 /* ======================================================  CFDTXQSTS1  ======================================================= */
35380  #define R_CANFD_CFDTXQSTS1_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
35381  #define R_CANFD_CFDTXQSTS1_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
35382  #define R_CANFD_CFDTXQSTS1_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
35383  #define R_CANFD_CFDTXQSTS1_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
35384  #define R_CANFD_CFDTXQSTS1_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
35385  #define R_CANFD_CFDTXQSTS1_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
35386  #define R_CANFD_CFDTXQSTS1_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
35387  #define R_CANFD_CFDTXQSTS1_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
35388  #define R_CANFD_CFDTXQSTS1_TXQFIF_Pos           (16UL)         /*!< TXQFIF (Bit 16)                                       */
35389  #define R_CANFD_CFDTXQSTS1_TXQFIF_Msk           (0x10000UL)    /*!< TXQFIF (Bitfield-Mask: 0x01)                          */
35390  #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Pos        (17UL)         /*!< TXQOFRXIF (Bit 17)                                    */
35391  #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Msk        (0x20000UL)    /*!< TXQOFRXIF (Bitfield-Mask: 0x01)                       */
35392  #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Pos        (18UL)         /*!< TXQOFTXIF (Bit 18)                                    */
35393  #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Msk        (0x40000UL)    /*!< TXQOFTXIF (Bitfield-Mask: 0x01)                       */
35394  #define R_CANFD_CFDTXQSTS1_TXQMLT_Pos           (19UL)         /*!< TXQMLT (Bit 19)                                       */
35395  #define R_CANFD_CFDTXQSTS1_TXQMLT_Msk           (0x80000UL)    /*!< TXQMLT (Bitfield-Mask: 0x01)                          */
35396 /* ======================================================  CFDTXQPCTR1  ====================================================== */
35397  #define R_CANFD_CFDTXQPCTR1_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
35398  #define R_CANFD_CFDTXQPCTR1_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
35399 /* =======================================================  CFDTXQCC2  ======================================================= */
35400  #define R_CANFD_CFDTXQCC2_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
35401  #define R_CANFD_CFDTXQCC2_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
35402  #define R_CANFD_CFDTXQCC2_TXQGWE_Pos            (1UL)          /*!< TXQGWE (Bit 1)                                        */
35403  #define R_CANFD_CFDTXQCC2_TXQGWE_Msk            (0x2UL)        /*!< TXQGWE (Bitfield-Mask: 0x01)                          */
35404  #define R_CANFD_CFDTXQCC2_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
35405  #define R_CANFD_CFDTXQCC2_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
35406  #define R_CANFD_CFDTXQCC2_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
35407  #define R_CANFD_CFDTXQCC2_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
35408  #define R_CANFD_CFDTXQCC2_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
35409  #define R_CANFD_CFDTXQCC2_TXQDC_Msk             (0x1f00UL)     /*!< TXQDC (Bitfield-Mask: 0x1f)                           */
35410  #define R_CANFD_CFDTXQCC2_TXQFIE_Pos            (16UL)         /*!< TXQFIE (Bit 16)                                       */
35411  #define R_CANFD_CFDTXQCC2_TXQFIE_Msk            (0x10000UL)    /*!< TXQFIE (Bitfield-Mask: 0x01)                          */
35412  #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Pos         (17UL)         /*!< TXQOFRXIE (Bit 17)                                    */
35413  #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Msk         (0x20000UL)    /*!< TXQOFRXIE (Bitfield-Mask: 0x01)                       */
35414  #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Pos         (18UL)         /*!< TXQOFTXIE (Bit 18)                                    */
35415  #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Msk         (0x40000UL)    /*!< TXQOFTXIE (Bitfield-Mask: 0x01)                       */
35416 /* ======================================================  CFDTXQSTS2  ======================================================= */
35417  #define R_CANFD_CFDTXQSTS2_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
35418  #define R_CANFD_CFDTXQSTS2_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
35419  #define R_CANFD_CFDTXQSTS2_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
35420  #define R_CANFD_CFDTXQSTS2_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
35421  #define R_CANFD_CFDTXQSTS2_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
35422  #define R_CANFD_CFDTXQSTS2_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
35423  #define R_CANFD_CFDTXQSTS2_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
35424  #define R_CANFD_CFDTXQSTS2_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
35425  #define R_CANFD_CFDTXQSTS2_TXQFIF_Pos           (16UL)         /*!< TXQFIF (Bit 16)                                       */
35426  #define R_CANFD_CFDTXQSTS2_TXQFIF_Msk           (0x10000UL)    /*!< TXQFIF (Bitfield-Mask: 0x01)                          */
35427  #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Pos        (17UL)         /*!< TXQOFRXIF (Bit 17)                                    */
35428  #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Msk        (0x20000UL)    /*!< TXQOFRXIF (Bitfield-Mask: 0x01)                       */
35429  #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Pos        (18UL)         /*!< TXQOFTXIF (Bit 18)                                    */
35430  #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Msk        (0x40000UL)    /*!< TXQOFTXIF (Bitfield-Mask: 0x01)                       */
35431  #define R_CANFD_CFDTXQSTS2_TXQMLT_Pos           (19UL)         /*!< TXQMLT (Bit 19)                                       */
35432  #define R_CANFD_CFDTXQSTS2_TXQMLT_Msk           (0x80000UL)    /*!< TXQMLT (Bitfield-Mask: 0x01)                          */
35433 /* ======================================================  CFDTXQPCTR2  ====================================================== */
35434  #define R_CANFD_CFDTXQPCTR2_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
35435  #define R_CANFD_CFDTXQPCTR2_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
35436 /* =======================================================  CFDTXQCC3  ======================================================= */
35437  #define R_CANFD_CFDTXQCC3_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
35438  #define R_CANFD_CFDTXQCC3_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
35439  #define R_CANFD_CFDTXQCC3_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
35440  #define R_CANFD_CFDTXQCC3_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
35441  #define R_CANFD_CFDTXQCC3_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
35442  #define R_CANFD_CFDTXQCC3_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
35443  #define R_CANFD_CFDTXQCC3_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
35444  #define R_CANFD_CFDTXQCC3_TXQDC_Msk             (0x1f00UL)     /*!< TXQDC (Bitfield-Mask: 0x1f)                           */
35445  #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Pos         (18UL)         /*!< TXQOFTXIE (Bit 18)                                    */
35446  #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Msk         (0x40000UL)    /*!< TXQOFTXIE (Bitfield-Mask: 0x01)                       */
35447 /* ======================================================  CFDTXQSTS3  ======================================================= */
35448  #define R_CANFD_CFDTXQSTS3_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
35449  #define R_CANFD_CFDTXQSTS3_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
35450  #define R_CANFD_CFDTXQSTS3_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
35451  #define R_CANFD_CFDTXQSTS3_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
35452  #define R_CANFD_CFDTXQSTS3_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
35453  #define R_CANFD_CFDTXQSTS3_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
35454  #define R_CANFD_CFDTXQSTS3_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
35455  #define R_CANFD_CFDTXQSTS3_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
35456  #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Pos        (18UL)         /*!< TXQOFTXIF (Bit 18)                                    */
35457  #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Msk        (0x40000UL)    /*!< TXQOFTXIF (Bitfield-Mask: 0x01)                       */
35458 /* ======================================================  CFDTXQPCTR3  ====================================================== */
35459  #define R_CANFD_CFDTXQPCTR3_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
35460  #define R_CANFD_CFDTXQPCTR3_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
35461 /* ======================================================  CFDTXQESTS  ======================================================= */
35462  #define R_CANFD_CFDTXQESTS_TXQxEMP_Pos          (0UL)          /*!< TXQxEMP (Bit 0)                                       */
35463  #define R_CANFD_CFDTXQESTS_TXQxEMP_Msk          (0xffUL)       /*!< TXQxEMP (Bitfield-Mask: 0xff)                         */
35464 /* ======================================================  CFDTXQFISTS  ====================================================== */
35465  #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Pos        (0UL)          /*!< TXQ0FULL (Bit 0)                                      */
35466  #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Msk        (0x7UL)        /*!< TXQ0FULL (Bitfield-Mask: 0x07)                        */
35467  #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Pos        (4UL)          /*!< TXQ1FULL (Bit 4)                                      */
35468  #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Msk        (0x70UL)       /*!< TXQ1FULL (Bitfield-Mask: 0x07)                        */
35469 /* ======================================================  CFDTXQMSTS  ======================================================= */
35470  #define R_CANFD_CFDTXQMSTS_TXQ0ML_Pos           (0UL)          /*!< TXQ0ML (Bit 0)                                        */
35471  #define R_CANFD_CFDTXQMSTS_TXQ0ML_Msk           (0x7UL)        /*!< TXQ0ML (Bitfield-Mask: 0x07)                          */
35472  #define R_CANFD_CFDTXQMSTS_TXQ1ML_Pos           (4UL)          /*!< TXQ1ML (Bit 4)                                        */
35473  #define R_CANFD_CFDTXQMSTS_TXQ1ML_Msk           (0x70UL)       /*!< TXQ1ML (Bitfield-Mask: 0x07)                          */
35474 /* ======================================================  CFDTXQISTS  ======================================================= */
35475  #define R_CANFD_CFDTXQISTS_TXQ0ISF_Pos          (0UL)          /*!< TXQ0ISF (Bit 0)                                       */
35476  #define R_CANFD_CFDTXQISTS_TXQ0ISF_Msk          (0xfUL)        /*!< TXQ0ISF (Bitfield-Mask: 0x0f)                         */
35477  #define R_CANFD_CFDTXQISTS_TXQ1ISF_Pos          (4UL)          /*!< TXQ1ISF (Bit 4)                                       */
35478  #define R_CANFD_CFDTXQISTS_TXQ1ISF_Msk          (0xf0UL)       /*!< TXQ1ISF (Bitfield-Mask: 0x0f)                         */
35479 /* =====================================================  CFDTXQOFTISTS  ===================================================== */
35480  #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Pos    (0UL)          /*!< TXQ0OFTISF (Bit 0)                                    */
35481  #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Msk    (0xfUL)        /*!< TXQ0OFTISF (Bitfield-Mask: 0x0f)                      */
35482  #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Pos    (4UL)          /*!< TXQ1OFTISF (Bit 4)                                    */
35483  #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Msk    (0xf0UL)       /*!< TXQ1OFTISF (Bitfield-Mask: 0x0f)                      */
35484 /* =====================================================  CFDTXQOFRISTS  ===================================================== */
35485  #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Pos    (0UL)          /*!< TXQ0OFRISF (Bit 0)                                    */
35486  #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Msk    (0x7UL)        /*!< TXQ0OFRISF (Bitfield-Mask: 0x07)                      */
35487  #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Pos    (4UL)          /*!< TXQ1OFRISF (Bit 4)                                    */
35488  #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Msk    (0x70UL)       /*!< TXQ1OFRISF (Bitfield-Mask: 0x07)                      */
35489 /* ======================================================  CFDTXQFSTS  ======================================================= */
35490  #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Pos          (0UL)          /*!< TXQ0FSF (Bit 0)                                       */
35491  #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Msk          (0xfUL)        /*!< TXQ0FSF (Bitfield-Mask: 0x0f)                         */
35492  #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Pos          (4UL)          /*!< TXQ1FSF (Bit 4)                                       */
35493  #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Msk          (0xf0UL)       /*!< TXQ1FSF (Bitfield-Mask: 0x0f)                         */
35494 /* =======================================================  CFDTHLCC  ======================================================== */
35495  #define R_CANFD_CFDTHLCC_THLE_Pos               (0UL)          /*!< THLE (Bit 0)                                          */
35496  #define R_CANFD_CFDTHLCC_THLE_Msk               (0x1UL)        /*!< THLE (Bitfield-Mask: 0x01)                            */
35497  #define R_CANFD_CFDTHLCC_THLIE_Pos              (8UL)          /*!< THLIE (Bit 8)                                         */
35498  #define R_CANFD_CFDTHLCC_THLIE_Msk              (0x100UL)      /*!< THLIE (Bitfield-Mask: 0x01)                           */
35499  #define R_CANFD_CFDTHLCC_THLIM_Pos              (9UL)          /*!< THLIM (Bit 9)                                         */
35500  #define R_CANFD_CFDTHLCC_THLIM_Msk              (0x200UL)      /*!< THLIM (Bitfield-Mask: 0x01)                           */
35501  #define R_CANFD_CFDTHLCC_THLDTE_Pos             (10UL)         /*!< THLDTE (Bit 10)                                       */
35502  #define R_CANFD_CFDTHLCC_THLDTE_Msk             (0x400UL)      /*!< THLDTE (Bitfield-Mask: 0x01)                          */
35503  #define R_CANFD_CFDTHLCC_THLDGE_Pos             (11UL)         /*!< THLDGE (Bit 11)                                       */
35504  #define R_CANFD_CFDTHLCC_THLDGE_Msk             (0x800UL)      /*!< THLDGE (Bitfield-Mask: 0x01)                          */
35505 /* =======================================================  CFDTHLSTS  ======================================================= */
35506  #define R_CANFD_CFDTHLSTS_THLEMP_Pos            (0UL)          /*!< THLEMP (Bit 0)                                        */
35507  #define R_CANFD_CFDTHLSTS_THLEMP_Msk            (0x1UL)        /*!< THLEMP (Bitfield-Mask: 0x01)                          */
35508  #define R_CANFD_CFDTHLSTS_THLFLL_Pos            (1UL)          /*!< THLFLL (Bit 1)                                        */
35509  #define R_CANFD_CFDTHLSTS_THLFLL_Msk            (0x2UL)        /*!< THLFLL (Bitfield-Mask: 0x01)                          */
35510  #define R_CANFD_CFDTHLSTS_THLELT_Pos            (2UL)          /*!< THLELT (Bit 2)                                        */
35511  #define R_CANFD_CFDTHLSTS_THLELT_Msk            (0x4UL)        /*!< THLELT (Bitfield-Mask: 0x01)                          */
35512  #define R_CANFD_CFDTHLSTS_THLIF_Pos             (3UL)          /*!< THLIF (Bit 3)                                         */
35513  #define R_CANFD_CFDTHLSTS_THLIF_Msk             (0x8UL)        /*!< THLIF (Bitfield-Mask: 0x01)                           */
35514  #define R_CANFD_CFDTHLSTS_THLMC_Pos             (8UL)          /*!< THLMC (Bit 8)                                         */
35515  #define R_CANFD_CFDTHLSTS_THLMC_Msk             (0x3f00UL)     /*!< THLMC (Bitfield-Mask: 0x3f)                           */
35516 /* ======================================================  CFDTHLPCTR  ======================================================= */
35517  #define R_CANFD_CFDTHLPCTR_THLPC_Pos            (0UL)          /*!< THLPC (Bit 0)                                         */
35518  #define R_CANFD_CFDTHLPCTR_THLPC_Msk            (0xffUL)       /*!< THLPC (Bitfield-Mask: 0xff)                           */
35519 /* =====================================================  CFDGTINTSTS0  ====================================================== */
35520  #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos          (0UL)          /*!< TSIF0 (Bit 0)                                         */
35521  #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk          (0x1UL)        /*!< TSIF0 (Bitfield-Mask: 0x01)                           */
35522  #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos          (1UL)          /*!< TAIF0 (Bit 1)                                         */
35523  #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk          (0x2UL)        /*!< TAIF0 (Bitfield-Mask: 0x01)                           */
35524  #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos          (2UL)          /*!< TQIF0 (Bit 2)                                         */
35525  #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk          (0x4UL)        /*!< TQIF0 (Bitfield-Mask: 0x01)                           */
35526  #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos         (3UL)          /*!< CFTIF0 (Bit 3)                                        */
35527  #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk         (0x8UL)        /*!< CFTIF0 (Bitfield-Mask: 0x01)                          */
35528  #define R_CANFD_CFDGTINTSTS0_THIF0_Pos          (4UL)          /*!< THIF0 (Bit 4)                                         */
35529  #define R_CANFD_CFDGTINTSTS0_THIF0_Msk          (0x10UL)       /*!< THIF0 (Bitfield-Mask: 0x01)                           */
35530  #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Pos        (5UL)          /*!< TQOFIF0 (Bit 5)                                       */
35531  #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Msk        (0x20UL)       /*!< TQOFIF0 (Bitfield-Mask: 0x01)                         */
35532  #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Pos        (6UL)          /*!< CFOTIF0 (Bit 6)                                       */
35533  #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Msk        (0x40UL)       /*!< CFOTIF0 (Bitfield-Mask: 0x01)                         */
35534  #define R_CANFD_CFDGTINTSTS0_TSIF1_Pos          (8UL)          /*!< TSIF1 (Bit 8)                                         */
35535  #define R_CANFD_CFDGTINTSTS0_TSIF1_Msk          (0x100UL)      /*!< TSIF1 (Bitfield-Mask: 0x01)                           */
35536  #define R_CANFD_CFDGTINTSTS0_TAIF1_Pos          (9UL)          /*!< TAIF1 (Bit 9)                                         */
35537  #define R_CANFD_CFDGTINTSTS0_TAIF1_Msk          (0x200UL)      /*!< TAIF1 (Bitfield-Mask: 0x01)                           */
35538  #define R_CANFD_CFDGTINTSTS0_TQIF1_Pos          (10UL)         /*!< TQIF1 (Bit 10)                                        */
35539  #define R_CANFD_CFDGTINTSTS0_TQIF1_Msk          (0x400UL)      /*!< TQIF1 (Bitfield-Mask: 0x01)                           */
35540  #define R_CANFD_CFDGTINTSTS0_CFTIF1_Pos         (11UL)         /*!< CFTIF1 (Bit 11)                                       */
35541  #define R_CANFD_CFDGTINTSTS0_CFTIF1_Msk         (0x800UL)      /*!< CFTIF1 (Bitfield-Mask: 0x01)                          */
35542  #define R_CANFD_CFDGTINTSTS0_THIF1_Pos          (12UL)         /*!< THIF1 (Bit 12)                                        */
35543  #define R_CANFD_CFDGTINTSTS0_THIF1_Msk          (0x1000UL)     /*!< THIF1 (Bitfield-Mask: 0x01)                           */
35544  #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Pos        (13UL)         /*!< TQOFIF1 (Bit 13)                                      */
35545  #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Msk        (0x2000UL)     /*!< TQOFIF1 (Bitfield-Mask: 0x01)                         */
35546  #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Pos        (14UL)         /*!< CFOTIF1 (Bit 14)                                      */
35547  #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Msk        (0x4000UL)     /*!< CFOTIF1 (Bitfield-Mask: 0x01)                         */
35548 /* ======================================================  CFDGTSTCFG  ======================================================= */
35549  #define R_CANFD_CFDGTSTCFG_ICBCE_Pos            (0UL)          /*!< ICBCE (Bit 0)                                         */
35550  #define R_CANFD_CFDGTSTCFG_ICBCE_Msk            (0x3UL)        /*!< ICBCE (Bitfield-Mask: 0x03)                           */
35551  #define R_CANFD_CFDGTSTCFG_RTMPS_Pos            (16UL)         /*!< RTMPS (Bit 16)                                        */
35552  #define R_CANFD_CFDGTSTCFG_RTMPS_Msk            (0x3ff0000UL)  /*!< RTMPS (Bitfield-Mask: 0x3ff)                          */
35553 /* ======================================================  CFDGTSTCTR  ======================================================= */
35554  #define R_CANFD_CFDGTSTCTR_ICBCTME_Pos          (0UL)          /*!< ICBCTME (Bit 0)                                       */
35555  #define R_CANFD_CFDGTSTCTR_ICBCTME_Msk          (0x1UL)        /*!< ICBCTME (Bitfield-Mask: 0x01)                         */
35556  #define R_CANFD_CFDGTSTCTR_RTME_Pos             (2UL)          /*!< RTME (Bit 2)                                          */
35557  #define R_CANFD_CFDGTSTCTR_RTME_Msk             (0x4UL)        /*!< RTME (Bitfield-Mask: 0x01)                            */
35558 /* =======================================================  CFDGFDCFG  ======================================================= */
35559  #define R_CANFD_CFDGFDCFG_RPED_Pos              (0UL)          /*!< RPED (Bit 0)                                          */
35560  #define R_CANFD_CFDGFDCFG_RPED_Msk              (0x1UL)        /*!< RPED (Bitfield-Mask: 0x01)                            */
35561  #define R_CANFD_CFDGFDCFG_TSCCFG_Pos            (8UL)          /*!< TSCCFG (Bit 8)                                        */
35562  #define R_CANFD_CFDGFDCFG_TSCCFG_Msk            (0x300UL)      /*!< TSCCFG (Bitfield-Mask: 0x03)                          */
35563 /* ======================================================  CFDGCRCCFG  ======================================================= */
35564  #define R_CANFD_CFDGCRCCFG_NIE_Pos              (0UL)          /*!< NIE (Bit 0)                                           */
35565  #define R_CANFD_CFDGCRCCFG_NIE_Msk              (0x1UL)        /*!< NIE (Bitfield-Mask: 0x01)                             */
35566 /* =======================================================  CFDGLOCKK  ======================================================= */
35567  #define R_CANFD_CFDGLOCKK_LOCK_Pos              (0UL)          /*!< LOCK (Bit 0)                                          */
35568  #define R_CANFD_CFDGLOCKK_LOCK_Msk              (0xffffUL)     /*!< LOCK (Bitfield-Mask: 0xffff)                          */
35569 /* =======================================================  CFDGLOTB  ======================================================== */
35570  #define R_CANFD_CFDGLOTB_OTBFE_Pos              (0UL)          /*!< OTBFE (Bit 0)                                         */
35571  #define R_CANFD_CFDGLOTB_OTBFE_Msk              (0x1UL)        /*!< OTBFE (Bitfield-Mask: 0x01)                           */
35572  #define R_CANFD_CFDGLOTB_OTBEMP_Pos             (8UL)          /*!< OTBEMP (Bit 8)                                        */
35573  #define R_CANFD_CFDGLOTB_OTBEMP_Msk             (0x100UL)      /*!< OTBEMP (Bitfield-Mask: 0x01)                          */
35574  #define R_CANFD_CFDGLOTB_OTBFLL_Pos             (9UL)          /*!< OTBFLL (Bit 9)                                        */
35575  #define R_CANFD_CFDGLOTB_OTBFLL_Msk             (0x200UL)      /*!< OTBFLL (Bitfield-Mask: 0x01)                          */
35576  #define R_CANFD_CFDGLOTB_OTBMLT_Pos             (10UL)         /*!< OTBMLT (Bit 10)                                       */
35577  #define R_CANFD_CFDGLOTB_OTBMLT_Msk             (0x400UL)      /*!< OTBMLT (Bitfield-Mask: 0x01)                          */
35578  #define R_CANFD_CFDGLOTB_OTBMC_Pos              (11UL)         /*!< OTBMC (Bit 11)                                        */
35579  #define R_CANFD_CFDGLOTB_OTBMC_Msk              (0xf800UL)     /*!< OTBMC (Bitfield-Mask: 0x1f)                           */
35580 /* =====================================================  CFDGAFLIGNENT  ===================================================== */
35581  #define R_CANFD_CFDGAFLIGNENT_IRN_Pos           (0UL)          /*!< IRN (Bit 0)                                           */
35582  #define R_CANFD_CFDGAFLIGNENT_IRN_Msk           (0x1ffUL)      /*!< IRN (Bitfield-Mask: 0x1ff)                            */
35583  #define R_CANFD_CFDGAFLIGNENT_ICN_Pos           (16UL)         /*!< ICN (Bit 16)                                          */
35584  #define R_CANFD_CFDGAFLIGNENT_ICN_Msk           (0x70000UL)    /*!< ICN (Bitfield-Mask: 0x07)                             */
35585 /* =====================================================  CFDGAFLIGNCTR  ===================================================== */
35586  #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos          (0UL)          /*!< IREN (Bit 0)                                          */
35587  #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk          (0x1UL)        /*!< IREN (Bitfield-Mask: 0x01)                            */
35588  #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos           (8UL)          /*!< KEY (Bit 8)                                           */
35589  #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk           (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
35590 /* =======================================================  CFDCDTCT  ======================================================== */
35591  #define R_CANFD_CFDCDTCT_RFDMAE0_Pos            (0UL)          /*!< RFDMAE0 (Bit 0)                                       */
35592  #define R_CANFD_CFDCDTCT_RFDMAE0_Msk            (0x1UL)        /*!< RFDMAE0 (Bitfield-Mask: 0x01)                         */
35593  #define R_CANFD_CFDCDTCT_RFDMAE1_Pos            (1UL)          /*!< RFDMAE1 (Bit 1)                                       */
35594  #define R_CANFD_CFDCDTCT_RFDMAE1_Msk            (0x2UL)        /*!< RFDMAE1 (Bitfield-Mask: 0x01)                         */
35595  #define R_CANFD_CFDCDTCT_RFDMAE2_Pos            (2UL)          /*!< RFDMAE2 (Bit 2)                                       */
35596  #define R_CANFD_CFDCDTCT_RFDMAE2_Msk            (0x4UL)        /*!< RFDMAE2 (Bitfield-Mask: 0x01)                         */
35597  #define R_CANFD_CFDCDTCT_RFDMAE3_Pos            (3UL)          /*!< RFDMAE3 (Bit 3)                                       */
35598  #define R_CANFD_CFDCDTCT_RFDMAE3_Msk            (0x8UL)        /*!< RFDMAE3 (Bitfield-Mask: 0x01)                         */
35599  #define R_CANFD_CFDCDTCT_RFDMAE4_Pos            (4UL)          /*!< RFDMAE4 (Bit 4)                                       */
35600  #define R_CANFD_CFDCDTCT_RFDMAE4_Msk            (0x10UL)       /*!< RFDMAE4 (Bitfield-Mask: 0x01)                         */
35601  #define R_CANFD_CFDCDTCT_RFDMAE5_Pos            (5UL)          /*!< RFDMAE5 (Bit 5)                                       */
35602  #define R_CANFD_CFDCDTCT_RFDMAE5_Msk            (0x20UL)       /*!< RFDMAE5 (Bitfield-Mask: 0x01)                         */
35603  #define R_CANFD_CFDCDTCT_RFDMAE6_Pos            (6UL)          /*!< RFDMAE6 (Bit 6)                                       */
35604  #define R_CANFD_CFDCDTCT_RFDMAE6_Msk            (0x40UL)       /*!< RFDMAE6 (Bitfield-Mask: 0x01)                         */
35605  #define R_CANFD_CFDCDTCT_RFDMAE7_Pos            (7UL)          /*!< RFDMAE7 (Bit 7)                                       */
35606  #define R_CANFD_CFDCDTCT_RFDMAE7_Msk            (0x80UL)       /*!< RFDMAE7 (Bitfield-Mask: 0x01)                         */
35607  #define R_CANFD_CFDCDTCT_CFDMAE0_Pos            (8UL)          /*!< CFDMAE0 (Bit 8)                                       */
35608  #define R_CANFD_CFDCDTCT_CFDMAE0_Msk            (0x100UL)      /*!< CFDMAE0 (Bitfield-Mask: 0x01)                         */
35609  #define R_CANFD_CFDCDTCT_CFDMAE1_Pos            (9UL)          /*!< CFDMAE1 (Bit 9)                                       */
35610  #define R_CANFD_CFDCDTCT_CFDMAE1_Msk            (0x200UL)      /*!< CFDMAE1 (Bitfield-Mask: 0x01)                         */
35611 /* =======================================================  CFDCDTSTS  ======================================================= */
35612  #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos         (0UL)          /*!< RFDMASTS0 (Bit 0)                                     */
35613  #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk         (0x1UL)        /*!< RFDMASTS0 (Bitfield-Mask: 0x01)                       */
35614  #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos         (1UL)          /*!< RFDMASTS1 (Bit 1)                                     */
35615  #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk         (0x2UL)        /*!< RFDMASTS1 (Bitfield-Mask: 0x01)                       */
35616  #define R_CANFD_CFDCDTSTS_RFDMASTS2_Pos         (2UL)          /*!< RFDMASTS2 (Bit 2)                                     */
35617  #define R_CANFD_CFDCDTSTS_RFDMASTS2_Msk         (0x4UL)        /*!< RFDMASTS2 (Bitfield-Mask: 0x01)                       */
35618  #define R_CANFD_CFDCDTSTS_RFDMASTS3_Pos         (3UL)          /*!< RFDMASTS3 (Bit 3)                                     */
35619  #define R_CANFD_CFDCDTSTS_RFDMASTS3_Msk         (0x8UL)        /*!< RFDMASTS3 (Bitfield-Mask: 0x01)                       */
35620  #define R_CANFD_CFDCDTSTS_RFDMASTS4_Pos         (4UL)          /*!< RFDMASTS4 (Bit 4)                                     */
35621  #define R_CANFD_CFDCDTSTS_RFDMASTS4_Msk         (0x10UL)       /*!< RFDMASTS4 (Bitfield-Mask: 0x01)                       */
35622  #define R_CANFD_CFDCDTSTS_RFDMASTS5_Pos         (5UL)          /*!< RFDMASTS5 (Bit 5)                                     */
35623  #define R_CANFD_CFDCDTSTS_RFDMASTS5_Msk         (0x20UL)       /*!< RFDMASTS5 (Bitfield-Mask: 0x01)                       */
35624  #define R_CANFD_CFDCDTSTS_RFDMASTS6_Pos         (6UL)          /*!< RFDMASTS6 (Bit 6)                                     */
35625  #define R_CANFD_CFDCDTSTS_RFDMASTS6_Msk         (0x40UL)       /*!< RFDMASTS6 (Bitfield-Mask: 0x01)                       */
35626  #define R_CANFD_CFDCDTSTS_RFDMASTS7_Pos         (7UL)          /*!< RFDMASTS7 (Bit 7)                                     */
35627  #define R_CANFD_CFDCDTSTS_RFDMASTS7_Msk         (0x80UL)       /*!< RFDMASTS7 (Bitfield-Mask: 0x01)                       */
35628  #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos         (8UL)          /*!< CFDMASTS0 (Bit 8)                                     */
35629  #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk         (0x100UL)      /*!< CFDMASTS0 (Bitfield-Mask: 0x01)                       */
35630  #define R_CANFD_CFDCDTSTS_CFDMASTS1_Pos         (9UL)          /*!< CFDMASTS1 (Bit 9)                                     */
35631  #define R_CANFD_CFDCDTSTS_CFDMASTS1_Msk         (0x200UL)      /*!< CFDMASTS1 (Bitfield-Mask: 0x01)                       */
35632 /* =======================================================  CFDCDTTCT  ======================================================= */
35633  #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Pos          (0UL)          /*!< TQ0DMAE0 (Bit 0)                                      */
35634  #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Msk          (0x1UL)        /*!< TQ0DMAE0 (Bitfield-Mask: 0x01)                        */
35635  #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Pos          (1UL)          /*!< TQ0DMAE1 (Bit 1)                                      */
35636  #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Msk          (0x2UL)        /*!< TQ0DMAE1 (Bitfield-Mask: 0x01)                        */
35637  #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Pos          (8UL)          /*!< TQ3DMAE0 (Bit 8)                                      */
35638  #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Msk          (0x100UL)      /*!< TQ3DMAE0 (Bitfield-Mask: 0x01)                        */
35639  #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Pos          (9UL)          /*!< TQ3DMAE1 (Bit 9)                                      */
35640  #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Msk          (0x200UL)      /*!< TQ3DMAE1 (Bitfield-Mask: 0x01)                        */
35641  #define R_CANFD_CFDCDTTCT_CFDMAE0_Pos           (16UL)         /*!< CFDMAE0 (Bit 16)                                      */
35642  #define R_CANFD_CFDCDTTCT_CFDMAE0_Msk           (0x10000UL)    /*!< CFDMAE0 (Bitfield-Mask: 0x01)                         */
35643  #define R_CANFD_CFDCDTTCT_CFDMAE1_Pos           (17UL)         /*!< CFDMAE1 (Bit 17)                                      */
35644  #define R_CANFD_CFDCDTTCT_CFDMAE1_Msk           (0x20000UL)    /*!< CFDMAE1 (Bitfield-Mask: 0x01)                         */
35645 /* ======================================================  CFDCDTTSTS  ======================================================= */
35646  #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Pos       (0UL)          /*!< TQ0DMASTS0 (Bit 0)                                    */
35647  #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Msk       (0x1UL)        /*!< TQ0DMASTS0 (Bitfield-Mask: 0x01)                      */
35648  #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Pos       (1UL)          /*!< TQ0DMASTS1 (Bit 1)                                    */
35649  #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Msk       (0x2UL)        /*!< TQ0DMASTS1 (Bitfield-Mask: 0x01)                      */
35650  #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Pos       (8UL)          /*!< TQ3DMASTS0 (Bit 8)                                    */
35651  #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Msk       (0x100UL)      /*!< TQ3DMASTS0 (Bitfield-Mask: 0x01)                      */
35652  #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Pos       (9UL)          /*!< TQ3DMASTS1 (Bit 9)                                    */
35653  #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Msk       (0x200UL)      /*!< TQ3DMASTS1 (Bitfield-Mask: 0x01)                      */
35654  #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Pos        (16UL)         /*!< CFDMASTS0 (Bit 16)                                    */
35655  #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Msk        (0x10000UL)    /*!< CFDMASTS0 (Bitfield-Mask: 0x01)                       */
35656  #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Pos        (17UL)         /*!< CFDMASTS1 (Bit 17)                                    */
35657  #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Msk        (0x20000UL)    /*!< CFDMASTS1 (Bitfield-Mask: 0x01)                       */
35658 /* ======================================================  CFDGRINTSTS  ====================================================== */
35659  #define R_CANFD_CFDGRINTSTS_QFIF_Pos            (0UL)          /*!< QFIF (Bit 0)                                          */
35660  #define R_CANFD_CFDGRINTSTS_QFIF_Msk            (0x7UL)        /*!< QFIF (Bitfield-Mask: 0x07)                            */
35661  #define R_CANFD_CFDGRINTSTS_QOFRIF_Pos          (8UL)          /*!< QOFRIF (Bit 8)                                        */
35662  #define R_CANFD_CFDGRINTSTS_QOFRIF_Msk          (0x700UL)      /*!< QOFRIF (Bitfield-Mask: 0x07)                          */
35663  #define R_CANFD_CFDGRINTSTS_CFRIF_Pos           (16UL)         /*!< CFRIF (Bit 16)                                        */
35664  #define R_CANFD_CFDGRINTSTS_CFRIF_Msk           (0x70000UL)    /*!< CFRIF (Bitfield-Mask: 0x07)                           */
35665  #define R_CANFD_CFDGRINTSTS_CFRFIF_Pos          (24UL)         /*!< CFRFIF (Bit 24)                                       */
35666  #define R_CANFD_CFDGRINTSTS_CFRFIF_Msk          (0x7000000UL)  /*!< CFRFIF (Bitfield-Mask: 0x07)                          */
35667  #define R_CANFD_CFDGRINTSTS_CFOFRIF_Pos         (28UL)         /*!< CFOFRIF (Bit 28)                                      */
35668  #define R_CANFD_CFDGRINTSTS_CFOFRIF_Msk         (0x70000000UL) /*!< CFOFRIF (Bitfield-Mask: 0x07)                         */
35669 /* =======================================================  CFDGRSTC  ======================================================== */
35670  #define R_CANFD_CFDGRSTC_SRST_Pos               (0UL)          /*!< SRST (Bit 0)                                          */
35671  #define R_CANFD_CFDGRSTC_SRST_Msk               (0x1UL)        /*!< SRST (Bitfield-Mask: 0x01)                            */
35672  #define R_CANFD_CFDGRSTC_KEY_Pos                (8UL)          /*!< KEY (Bit 8)                                           */
35673  #define R_CANFD_CFDGRSTC_KEY_Msk                (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
35674 /* =======================================================  CFDRPGACC  ======================================================= */
35675  #define R_CANFD_CFDRPGACC_RDTA_Pos              (0UL)          /*!< RDTA (Bit 0)                                          */
35676  #define R_CANFD_CFDRPGACC_RDTA_Msk              (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff)                      */
35677 
35678 /* =========================================================================================================================== */
35679 /* ================                                         R_CANFDL                                          ================ */
35680 /* =========================================================================================================================== */
35681 
35682 /* ========================================================  CFDGCFG  ======================================================== */
35683  #define R_CANFDL_CFDGCFG_TPRI_Pos                (0UL)          /*!< TPRI (Bit 0)                                          */
35684  #define R_CANFDL_CFDGCFG_TPRI_Msk                (0x1UL)        /*!< TPRI (Bitfield-Mask: 0x01)                            */
35685  #define R_CANFDL_CFDGCFG_DCE_Pos                 (1UL)          /*!< DCE (Bit 1)                                           */
35686  #define R_CANFDL_CFDGCFG_DCE_Msk                 (0x2UL)        /*!< DCE (Bitfield-Mask: 0x01)                             */
35687  #define R_CANFDL_CFDGCFG_DRE_Pos                 (2UL)          /*!< DRE (Bit 2)                                           */
35688  #define R_CANFDL_CFDGCFG_DRE_Msk                 (0x4UL)        /*!< DRE (Bitfield-Mask: 0x01)                             */
35689  #define R_CANFDL_CFDGCFG_MME_Pos                 (3UL)          /*!< MME (Bit 3)                                           */
35690  #define R_CANFDL_CFDGCFG_MME_Msk                 (0x8UL)        /*!< MME (Bitfield-Mask: 0x01)                             */
35691  #define R_CANFDL_CFDGCFG_DCS_Pos                 (4UL)          /*!< DCS (Bit 4)                                           */
35692  #define R_CANFDL_CFDGCFG_DCS_Msk                 (0x10UL)       /*!< DCS (Bitfield-Mask: 0x01)                             */
35693  #define R_CANFDL_CFDGCFG_CMPOC_Pos               (5UL)          /*!< CMPOC (Bit 5)                                         */
35694  #define R_CANFDL_CFDGCFG_CMPOC_Msk               (0x20UL)       /*!< CMPOC (Bitfield-Mask: 0x01)                           */
35695  #define R_CANFDL_CFDGCFG_TSP_Pos                 (8UL)          /*!< TSP (Bit 8)                                           */
35696  #define R_CANFDL_CFDGCFG_TSP_Msk                 (0xf00UL)      /*!< TSP (Bitfield-Mask: 0x0f)                             */
35697  #define R_CANFDL_CFDGCFG_TSSS_Pos                (12UL)         /*!< TSSS (Bit 12)                                         */
35698  #define R_CANFDL_CFDGCFG_TSSS_Msk                (0x1000UL)     /*!< TSSS (Bitfield-Mask: 0x01)                            */
35699  #define R_CANFDL_CFDGCFG_ITRCP_Pos               (16UL)         /*!< ITRCP (Bit 16)                                        */
35700  #define R_CANFDL_CFDGCFG_ITRCP_Msk               (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff)                         */
35701 /* ========================================================  CFDGCTR  ======================================================== */
35702  #define R_CANFDL_CFDGCTR_GMDC_Pos                (0UL)          /*!< GMDC (Bit 0)                                          */
35703  #define R_CANFDL_CFDGCTR_GMDC_Msk                (0x3UL)        /*!< GMDC (Bitfield-Mask: 0x03)                            */
35704  #define R_CANFDL_CFDGCTR_GSLPR_Pos               (2UL)          /*!< GSLPR (Bit 2)                                         */
35705  #define R_CANFDL_CFDGCTR_GSLPR_Msk               (0x4UL)        /*!< GSLPR (Bitfield-Mask: 0x01)                           */
35706  #define R_CANFDL_CFDGCTR_DEIE_Pos                (8UL)          /*!< DEIE (Bit 8)                                          */
35707  #define R_CANFDL_CFDGCTR_DEIE_Msk                (0x100UL)      /*!< DEIE (Bitfield-Mask: 0x01)                            */
35708  #define R_CANFDL_CFDGCTR_MEIE_Pos                (9UL)          /*!< MEIE (Bit 9)                                          */
35709  #define R_CANFDL_CFDGCTR_MEIE_Msk                (0x200UL)      /*!< MEIE (Bitfield-Mask: 0x01)                            */
35710  #define R_CANFDL_CFDGCTR_THLEIE_Pos              (10UL)         /*!< THLEIE (Bit 10)                                       */
35711  #define R_CANFDL_CFDGCTR_THLEIE_Msk              (0x400UL)      /*!< THLEIE (Bitfield-Mask: 0x01)                          */
35712  #define R_CANFDL_CFDGCTR_CMPOFIE_Pos             (11UL)         /*!< CMPOFIE (Bit 11)                                      */
35713  #define R_CANFDL_CFDGCTR_CMPOFIE_Msk             (0x800UL)      /*!< CMPOFIE (Bitfield-Mask: 0x01)                         */
35714  #define R_CANFDL_CFDGCTR_TSRST_Pos               (16UL)         /*!< TSRST (Bit 16)                                        */
35715  #define R_CANFDL_CFDGCTR_TSRST_Msk               (0x10000UL)    /*!< TSRST (Bitfield-Mask: 0x01)                           */
35716 /* ========================================================  CFDGSTS  ======================================================== */
35717  #define R_CANFDL_CFDGSTS_GRSTSTS_Pos             (0UL)          /*!< GRSTSTS (Bit 0)                                       */
35718  #define R_CANFDL_CFDGSTS_GRSTSTS_Msk             (0x1UL)        /*!< GRSTSTS (Bitfield-Mask: 0x01)                         */
35719  #define R_CANFDL_CFDGSTS_GHLTSTS_Pos             (1UL)          /*!< GHLTSTS (Bit 1)                                       */
35720  #define R_CANFDL_CFDGSTS_GHLTSTS_Msk             (0x2UL)        /*!< GHLTSTS (Bitfield-Mask: 0x01)                         */
35721  #define R_CANFDL_CFDGSTS_GSLPSTS_Pos             (2UL)          /*!< GSLPSTS (Bit 2)                                       */
35722  #define R_CANFDL_CFDGSTS_GSLPSTS_Msk             (0x4UL)        /*!< GSLPSTS (Bitfield-Mask: 0x01)                         */
35723  #define R_CANFDL_CFDGSTS_GRAMINIT_Pos            (3UL)          /*!< GRAMINIT (Bit 3)                                      */
35724  #define R_CANFDL_CFDGSTS_GRAMINIT_Msk            (0x8UL)        /*!< GRAMINIT (Bitfield-Mask: 0x01)                        */
35725 /* =======================================================  CFDGERFL  ======================================================== */
35726  #define R_CANFDL_CFDGERFL_DEF_Pos                (0UL)          /*!< DEF (Bit 0)                                           */
35727  #define R_CANFDL_CFDGERFL_DEF_Msk                (0x1UL)        /*!< DEF (Bitfield-Mask: 0x01)                             */
35728  #define R_CANFDL_CFDGERFL_MES_Pos                (1UL)          /*!< MES (Bit 1)                                           */
35729  #define R_CANFDL_CFDGERFL_MES_Msk                (0x2UL)        /*!< MES (Bitfield-Mask: 0x01)                             */
35730  #define R_CANFDL_CFDGERFL_THLES_Pos              (2UL)          /*!< THLES (Bit 2)                                         */
35731  #define R_CANFDL_CFDGERFL_THLES_Msk              (0x4UL)        /*!< THLES (Bitfield-Mask: 0x01)                           */
35732  #define R_CANFDL_CFDGERFL_CMPOF_Pos              (3UL)          /*!< CMPOF (Bit 3)                                         */
35733  #define R_CANFDL_CFDGERFL_CMPOF_Msk              (0x8UL)        /*!< CMPOF (Bitfield-Mask: 0x01)                           */
35734  #define R_CANFDL_CFDGERFL_EEF0_Pos               (16UL)         /*!< EEF0 (Bit 16)                                         */
35735  #define R_CANFDL_CFDGERFL_EEF0_Msk               (0x10000UL)    /*!< EEF0 (Bitfield-Mask: 0x01)                            */
35736 /* ========================================================  CFDGTSC  ======================================================== */
35737  #define R_CANFDL_CFDGTSC_TS_Pos                  (0UL)          /*!< TS (Bit 0)                                            */
35738  #define R_CANFDL_CFDGTSC_TS_Msk                  (0xffffUL)     /*!< TS (Bitfield-Mask: 0xffff)                            */
35739 /* ======================================================  CFDGAFLECTR  ====================================================== */
35740  #define R_CANFDL_CFDGAFLECTR_AFLPN_Pos           (0UL)          /*!< AFLPN (Bit 0)                                         */
35741  #define R_CANFDL_CFDGAFLECTR_AFLPN_Msk           (0xfUL)        /*!< AFLPN (Bitfield-Mask: 0x0f)                           */
35742  #define R_CANFDL_CFDGAFLECTR_AFLDAE_Pos          (8UL)          /*!< AFLDAE (Bit 8)                                        */
35743  #define R_CANFDL_CFDGAFLECTR_AFLDAE_Msk          (0x100UL)      /*!< AFLDAE (Bitfield-Mask: 0x01)                          */
35744 /* ======================================================  CFDGAFLCFG0  ====================================================== */
35745  #define R_CANFDL_CFDGAFLCFG0_RNC1_Pos            (0UL)          /*!< RNC1 (Bit 0)                                          */
35746  #define R_CANFDL_CFDGAFLCFG0_RNC1_Msk            (0x1ffUL)      /*!< RNC1 (Bitfield-Mask: 0x1ff)                           */
35747  #define R_CANFDL_CFDGAFLCFG0_RNC0_Pos            (16UL)         /*!< RNC0 (Bit 16)                                         */
35748  #define R_CANFDL_CFDGAFLCFG0_RNC0_Msk            (0x1ff0000UL)  /*!< RNC0 (Bitfield-Mask: 0x1ff)                           */
35749 /* ========================================================  CFDRMNB  ======================================================== */
35750  #define R_CANFDL_CFDRMNB_NRXMB_Pos               (0UL)          /*!< NRXMB (Bit 0)                                         */
35751  #define R_CANFDL_CFDRMNB_NRXMB_Msk               (0xffUL)       /*!< NRXMB (Bitfield-Mask: 0xff)                           */
35752  #define R_CANFDL_CFDRMNB_RMPLS_Pos               (8UL)          /*!< RMPLS (Bit 8)                                         */
35753  #define R_CANFDL_CFDRMNB_RMPLS_Msk               (0x700UL)      /*!< RMPLS (Bitfield-Mask: 0x07)                           */
35754 /* =======================================================  CFDRMND0  ======================================================== */
35755  #define R_CANFDL_CFDRMND0_RMNSu_Pos              (0UL)          /*!< RMNSu (Bit 0)                                         */
35756  #define R_CANFDL_CFDRMND0_RMNSu_Msk              (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff)                     */
35757 /* =======================================================  CFDRMIEC  ======================================================== */
35758  #define R_CANFDL_CFDRMIEC_RMIE_Pos               (0UL)          /*!< RMIE (Bit 0)                                          */
35759  #define R_CANFDL_CFDRMIEC_RMIE_Msk               (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff)                      */
35760 /* ========================================================  CFDRFCC  ======================================================== */
35761  #define R_CANFDL_CFDRFCC_RFE_Pos                 (0UL)          /*!< RFE (Bit 0)                                           */
35762  #define R_CANFDL_CFDRFCC_RFE_Msk                 (0x1UL)        /*!< RFE (Bitfield-Mask: 0x01)                             */
35763  #define R_CANFDL_CFDRFCC_RFIE_Pos                (1UL)          /*!< RFIE (Bit 1)                                          */
35764  #define R_CANFDL_CFDRFCC_RFIE_Msk                (0x2UL)        /*!< RFIE (Bitfield-Mask: 0x01)                            */
35765  #define R_CANFDL_CFDRFCC_RFPLS_Pos               (4UL)          /*!< RFPLS (Bit 4)                                         */
35766  #define R_CANFDL_CFDRFCC_RFPLS_Msk               (0x70UL)       /*!< RFPLS (Bitfield-Mask: 0x07)                           */
35767  #define R_CANFDL_CFDRFCC_RFDC_Pos                (8UL)          /*!< RFDC (Bit 8)                                          */
35768  #define R_CANFDL_CFDRFCC_RFDC_Msk                (0x700UL)      /*!< RFDC (Bitfield-Mask: 0x07)                            */
35769  #define R_CANFDL_CFDRFCC_RFIM_Pos                (12UL)         /*!< RFIM (Bit 12)                                         */
35770  #define R_CANFDL_CFDRFCC_RFIM_Msk                (0x1000UL)     /*!< RFIM (Bitfield-Mask: 0x01)                            */
35771  #define R_CANFDL_CFDRFCC_RFIGCV_Pos              (13UL)         /*!< RFIGCV (Bit 13)                                       */
35772  #define R_CANFDL_CFDRFCC_RFIGCV_Msk              (0xe000UL)     /*!< RFIGCV (Bitfield-Mask: 0x07)                          */
35773 /* =======================================================  CFDRFSTS  ======================================================== */
35774  #define R_CANFDL_CFDRFSTS_RFEMP_Pos              (0UL)          /*!< RFEMP (Bit 0)                                         */
35775  #define R_CANFDL_CFDRFSTS_RFEMP_Msk              (0x1UL)        /*!< RFEMP (Bitfield-Mask: 0x01)                           */
35776  #define R_CANFDL_CFDRFSTS_RFFLL_Pos              (1UL)          /*!< RFFLL (Bit 1)                                         */
35777  #define R_CANFDL_CFDRFSTS_RFFLL_Msk              (0x2UL)        /*!< RFFLL (Bitfield-Mask: 0x01)                           */
35778  #define R_CANFDL_CFDRFSTS_RFMLT_Pos              (2UL)          /*!< RFMLT (Bit 2)                                         */
35779  #define R_CANFDL_CFDRFSTS_RFMLT_Msk              (0x4UL)        /*!< RFMLT (Bitfield-Mask: 0x01)                           */
35780  #define R_CANFDL_CFDRFSTS_RFIF_Pos               (3UL)          /*!< RFIF (Bit 3)                                          */
35781  #define R_CANFDL_CFDRFSTS_RFIF_Msk               (0x8UL)        /*!< RFIF (Bitfield-Mask: 0x01)                            */
35782  #define R_CANFDL_CFDRFSTS_RFMC_Pos               (8UL)          /*!< RFMC (Bit 8)                                          */
35783  #define R_CANFDL_CFDRFSTS_RFMC_Msk               (0xff00UL)     /*!< RFMC (Bitfield-Mask: 0xff)                            */
35784 /* =======================================================  CFDRFPCTR  ======================================================= */
35785  #define R_CANFDL_CFDRFPCTR_RFPC_Pos              (0UL)          /*!< RFPC (Bit 0)                                          */
35786  #define R_CANFDL_CFDRFPCTR_RFPC_Msk              (0xffUL)       /*!< RFPC (Bitfield-Mask: 0xff)                            */
35787 /* ========================================================  CFDCFCC  ======================================================== */
35788  #define R_CANFDL_CFDCFCC_CFE_Pos                 (0UL)          /*!< CFE (Bit 0)                                           */
35789  #define R_CANFDL_CFDCFCC_CFE_Msk                 (0x1UL)        /*!< CFE (Bitfield-Mask: 0x01)                             */
35790  #define R_CANFDL_CFDCFCC_CFRXIE_Pos              (1UL)          /*!< CFRXIE (Bit 1)                                        */
35791  #define R_CANFDL_CFDCFCC_CFRXIE_Msk              (0x2UL)        /*!< CFRXIE (Bitfield-Mask: 0x01)                          */
35792  #define R_CANFDL_CFDCFCC_CFTXIE_Pos              (2UL)          /*!< CFTXIE (Bit 2)                                        */
35793  #define R_CANFDL_CFDCFCC_CFTXIE_Msk              (0x4UL)        /*!< CFTXIE (Bitfield-Mask: 0x01)                          */
35794  #define R_CANFDL_CFDCFCC_CFPLS_Pos               (4UL)          /*!< CFPLS (Bit 4)                                         */
35795  #define R_CANFDL_CFDCFCC_CFPLS_Msk               (0x70UL)       /*!< CFPLS (Bitfield-Mask: 0x07)                           */
35796  #define R_CANFDL_CFDCFCC_CFM_Pos                 (8UL)          /*!< CFM (Bit 8)                                           */
35797  #define R_CANFDL_CFDCFCC_CFM_Msk                 (0x300UL)      /*!< CFM (Bitfield-Mask: 0x03)                             */
35798  #define R_CANFDL_CFDCFCC_CFITSS_Pos              (10UL)         /*!< CFITSS (Bit 10)                                       */
35799  #define R_CANFDL_CFDCFCC_CFITSS_Msk              (0x400UL)      /*!< CFITSS (Bitfield-Mask: 0x01)                          */
35800  #define R_CANFDL_CFDCFCC_CFITR_Pos               (11UL)         /*!< CFITR (Bit 11)                                        */
35801  #define R_CANFDL_CFDCFCC_CFITR_Msk               (0x800UL)      /*!< CFITR (Bitfield-Mask: 0x01)                           */
35802  #define R_CANFDL_CFDCFCC_CFIM_Pos                (12UL)         /*!< CFIM (Bit 12)                                         */
35803  #define R_CANFDL_CFDCFCC_CFIM_Msk                (0x1000UL)     /*!< CFIM (Bitfield-Mask: 0x01)                            */
35804  #define R_CANFDL_CFDCFCC_CFIGCV_Pos              (13UL)         /*!< CFIGCV (Bit 13)                                       */
35805  #define R_CANFDL_CFDCFCC_CFIGCV_Msk              (0xe000UL)     /*!< CFIGCV (Bitfield-Mask: 0x07)                          */
35806  #define R_CANFDL_CFDCFCC_CFTML_Pos               (16UL)         /*!< CFTML (Bit 16)                                        */
35807  #define R_CANFDL_CFDCFCC_CFTML_Msk               (0x1f0000UL)   /*!< CFTML (Bitfield-Mask: 0x1f)                           */
35808  #define R_CANFDL_CFDCFCC_CFDC_Pos                (21UL)         /*!< CFDC (Bit 21)                                         */
35809  #define R_CANFDL_CFDCFCC_CFDC_Msk                (0xe00000UL)   /*!< CFDC (Bitfield-Mask: 0x07)                            */
35810  #define R_CANFDL_CFDCFCC_CFITT_Pos               (24UL)         /*!< CFITT (Bit 24)                                        */
35811  #define R_CANFDL_CFDCFCC_CFITT_Msk               (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff)                           */
35812 /* =======================================================  CFDCFSTS  ======================================================== */
35813  #define R_CANFDL_CFDCFSTS_CFEMP_Pos              (0UL)          /*!< CFEMP (Bit 0)                                         */
35814  #define R_CANFDL_CFDCFSTS_CFEMP_Msk              (0x1UL)        /*!< CFEMP (Bitfield-Mask: 0x01)                           */
35815  #define R_CANFDL_CFDCFSTS_CFFLL_Pos              (1UL)          /*!< CFFLL (Bit 1)                                         */
35816  #define R_CANFDL_CFDCFSTS_CFFLL_Msk              (0x2UL)        /*!< CFFLL (Bitfield-Mask: 0x01)                           */
35817  #define R_CANFDL_CFDCFSTS_CFMLT_Pos              (2UL)          /*!< CFMLT (Bit 2)                                         */
35818  #define R_CANFDL_CFDCFSTS_CFMLT_Msk              (0x4UL)        /*!< CFMLT (Bitfield-Mask: 0x01)                           */
35819  #define R_CANFDL_CFDCFSTS_CFRXIF_Pos             (3UL)          /*!< CFRXIF (Bit 3)                                        */
35820  #define R_CANFDL_CFDCFSTS_CFRXIF_Msk             (0x8UL)        /*!< CFRXIF (Bitfield-Mask: 0x01)                          */
35821  #define R_CANFDL_CFDCFSTS_CFTXIF_Pos             (4UL)          /*!< CFTXIF (Bit 4)                                        */
35822  #define R_CANFDL_CFDCFSTS_CFTXIF_Msk             (0x10UL)       /*!< CFTXIF (Bitfield-Mask: 0x01)                          */
35823  #define R_CANFDL_CFDCFSTS_CFMC_Pos               (8UL)          /*!< CFMC (Bit 8)                                          */
35824  #define R_CANFDL_CFDCFSTS_CFMC_Msk               (0xff00UL)     /*!< CFMC (Bitfield-Mask: 0xff)                            */
35825 /* =======================================================  CFDCFPCTR  ======================================================= */
35826  #define R_CANFDL_CFDCFPCTR_CFPC_Pos              (0UL)          /*!< CFPC (Bit 0)                                          */
35827  #define R_CANFDL_CFDCFPCTR_CFPC_Msk              (0xffUL)       /*!< CFPC (Bitfield-Mask: 0xff)                            */
35828 /* =======================================================  CFDFESTS  ======================================================== */
35829  #define R_CANFDL_CFDFESTS_RFXEMP_Pos             (0UL)          /*!< RFXEMP (Bit 0)                                        */
35830  #define R_CANFDL_CFDFESTS_RFXEMP_Msk             (0x3UL)        /*!< RFXEMP (Bitfield-Mask: 0x03)                          */
35831  #define R_CANFDL_CFDFESTS_CFXEMP_Pos             (8UL)          /*!< CFXEMP (Bit 8)                                        */
35832  #define R_CANFDL_CFDFESTS_CFXEMP_Msk             (0x100UL)      /*!< CFXEMP (Bitfield-Mask: 0x01)                          */
35833 /* =======================================================  CFDFFSTS  ======================================================== */
35834  #define R_CANFDL_CFDFFSTS_RFXFLL_Pos             (0UL)          /*!< RFXFLL (Bit 0)                                        */
35835  #define R_CANFDL_CFDFFSTS_RFXFLL_Msk             (0x3UL)        /*!< RFXFLL (Bitfield-Mask: 0x03)                          */
35836  #define R_CANFDL_CFDFFSTS_CFXFLL_Pos             (8UL)          /*!< CFXFLL (Bit 8)                                        */
35837  #define R_CANFDL_CFDFFSTS_CFXFLL_Msk             (0x100UL)      /*!< CFXFLL (Bitfield-Mask: 0x01)                          */
35838 /* =======================================================  CFDFMSTS  ======================================================== */
35839  #define R_CANFDL_CFDFMSTS_RFXMLT_Pos             (0UL)          /*!< RFXMLT (Bit 0)                                        */
35840  #define R_CANFDL_CFDFMSTS_RFXMLT_Msk             (0x3UL)        /*!< RFXMLT (Bitfield-Mask: 0x03)                          */
35841  #define R_CANFDL_CFDFMSTS_CFXMLT_Pos             (8UL)          /*!< CFXMLT (Bit 8)                                        */
35842  #define R_CANFDL_CFDFMSTS_CFXMLT_Msk             (0x100UL)      /*!< CFXMLT (Bitfield-Mask: 0x01)                          */
35843 /* =======================================================  CFDRFISTS  ======================================================= */
35844  #define R_CANFDL_CFDRFISTS_RFXIF_Pos             (0UL)          /*!< RFXIF (Bit 0)                                         */
35845  #define R_CANFDL_CFDRFISTS_RFXIF_Msk             (0x1UL)        /*!< RFXIF (Bitfield-Mask: 0x01)                           */
35846 /* ========================================================  CFDTMC  ========================================================= */
35847  #define R_CANFDL_CFDTMC_TMTR_Pos                 (0UL)          /*!< TMTR (Bit 0)                                          */
35848  #define R_CANFDL_CFDTMC_TMTR_Msk                 (0x1UL)        /*!< TMTR (Bitfield-Mask: 0x01)                            */
35849  #define R_CANFDL_CFDTMC_TMTAR_Pos                (1UL)          /*!< TMTAR (Bit 1)                                         */
35850  #define R_CANFDL_CFDTMC_TMTAR_Msk                (0x2UL)        /*!< TMTAR (Bitfield-Mask: 0x01)                           */
35851  #define R_CANFDL_CFDTMC_TMOM_Pos                 (2UL)          /*!< TMOM (Bit 2)                                          */
35852  #define R_CANFDL_CFDTMC_TMOM_Msk                 (0x4UL)        /*!< TMOM (Bitfield-Mask: 0x01)                            */
35853 /* =======================================================  CFDTMSTS  ======================================================== */
35854  #define R_CANFDL_CFDTMSTS_TMTSTS_Pos             (0UL)          /*!< TMTSTS (Bit 0)                                        */
35855  #define R_CANFDL_CFDTMSTS_TMTSTS_Msk             (0x1UL)        /*!< TMTSTS (Bitfield-Mask: 0x01)                          */
35856  #define R_CANFDL_CFDTMSTS_TMTRF_Pos              (1UL)          /*!< TMTRF (Bit 1)                                         */
35857  #define R_CANFDL_CFDTMSTS_TMTRF_Msk              (0x6UL)        /*!< TMTRF (Bitfield-Mask: 0x03)                           */
35858  #define R_CANFDL_CFDTMSTS_TMTRM_Pos              (3UL)          /*!< TMTRM (Bit 3)                                         */
35859  #define R_CANFDL_CFDTMSTS_TMTRM_Msk              (0x8UL)        /*!< TMTRM (Bitfield-Mask: 0x01)                           */
35860  #define R_CANFDL_CFDTMSTS_TMTARM_Pos             (4UL)          /*!< TMTARM (Bit 4)                                        */
35861  #define R_CANFDL_CFDTMSTS_TMTARM_Msk             (0x10UL)       /*!< TMTARM (Bitfield-Mask: 0x01)                          */
35862 /* ======================================================  CFDTMTRSTS  ======================================================= */
35863  #define R_CANFDL_CFDTMTRSTS_CFDTMTRSTSg_Pos      (0UL)          /*!< CFDTMTRSTSg (Bit 0)                                   */
35864  #define R_CANFDL_CFDTMTRSTS_CFDTMTRSTSg_Msk      (0xfUL)        /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f)                     */
35865 /* ======================================================  CFDTMTARSTS  ====================================================== */
35866  #define R_CANFDL_CFDTMTARSTS_CFDTMTARSTSg_Pos    (0UL)          /*!< CFDTMTARSTSg (Bit 0)                                  */
35867  #define R_CANFDL_CFDTMTARSTS_CFDTMTARSTSg_Msk    (0xfUL)        /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f)                    */
35868 /* ======================================================  CFDTMTCSTS  ======================================================= */
35869  #define R_CANFDL_CFDTMTCSTS_CFDTMTCSTSg_Pos      (0UL)          /*!< CFDTMTCSTSg (Bit 0)                                   */
35870  #define R_CANFDL_CFDTMTCSTS_CFDTMTCSTSg_Msk      (0xfUL)        /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f)                     */
35871 /* ======================================================  CFDTMTASTS  ======================================================= */
35872  #define R_CANFDL_CFDTMTASTS_CFDTMTASTSg_Pos      (0UL)          /*!< CFDTMTASTSg (Bit 0)                                   */
35873  #define R_CANFDL_CFDTMTASTS_CFDTMTASTSg_Msk      (0xfUL)        /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f)                     */
35874 /* =======================================================  CFDTMIEC  ======================================================== */
35875  #define R_CANFDL_CFDTMIEC_TMIEg_Pos              (0UL)          /*!< TMIEg (Bit 0)                                         */
35876  #define R_CANFDL_CFDTMIEC_TMIEg_Msk              (0xfUL)        /*!< TMIEg (Bitfield-Mask: 0x0f)                           */
35877 /* =======================================================  CFDTXQCC0  ======================================================= */
35878  #define R_CANFDL_CFDTXQCC0_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
35879  #define R_CANFDL_CFDTXQCC0_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
35880  #define R_CANFDL_CFDTXQCC0_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
35881  #define R_CANFDL_CFDTXQCC0_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
35882  #define R_CANFDL_CFDTXQCC0_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
35883  #define R_CANFDL_CFDTXQCC0_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
35884  #define R_CANFDL_CFDTXQCC0_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
35885  #define R_CANFDL_CFDTXQCC0_TXQDC_Msk             (0x300UL)      /*!< TXQDC (Bitfield-Mask: 0x03)                           */
35886 /* ======================================================  CFDTXQSTS0  ======================================================= */
35887  #define R_CANFDL_CFDTXQSTS0_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
35888  #define R_CANFDL_CFDTXQSTS0_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
35889  #define R_CANFDL_CFDTXQSTS0_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
35890  #define R_CANFDL_CFDTXQSTS0_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
35891  #define R_CANFDL_CFDTXQSTS0_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
35892  #define R_CANFDL_CFDTXQSTS0_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
35893  #define R_CANFDL_CFDTXQSTS0_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
35894  #define R_CANFDL_CFDTXQSTS0_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
35895 /* ======================================================  CFDTXQPCTR0  ====================================================== */
35896  #define R_CANFDL_CFDTXQPCTR0_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
35897  #define R_CANFDL_CFDTXQPCTR0_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
35898 /* =======================================================  CFDTHLCC  ======================================================== */
35899  #define R_CANFDL_CFDTHLCC_THLE_Pos               (0UL)          /*!< THLE (Bit 0)                                          */
35900  #define R_CANFDL_CFDTHLCC_THLE_Msk               (0x1UL)        /*!< THLE (Bitfield-Mask: 0x01)                            */
35901  #define R_CANFDL_CFDTHLCC_THLIE_Pos              (8UL)          /*!< THLIE (Bit 8)                                         */
35902  #define R_CANFDL_CFDTHLCC_THLIE_Msk              (0x100UL)      /*!< THLIE (Bitfield-Mask: 0x01)                           */
35903  #define R_CANFDL_CFDTHLCC_THLIM_Pos              (9UL)          /*!< THLIM (Bit 9)                                         */
35904  #define R_CANFDL_CFDTHLCC_THLIM_Msk              (0x200UL)      /*!< THLIM (Bitfield-Mask: 0x01)                           */
35905  #define R_CANFDL_CFDTHLCC_THLDTE_Pos             (10UL)         /*!< THLDTE (Bit 10)                                       */
35906  #define R_CANFDL_CFDTHLCC_THLDTE_Msk             (0x400UL)      /*!< THLDTE (Bitfield-Mask: 0x01)                          */
35907 /* =======================================================  CFDTHLSTS  ======================================================= */
35908  #define R_CANFDL_CFDTHLSTS_THLEMP_Pos            (0UL)          /*!< THLEMP (Bit 0)                                        */
35909  #define R_CANFDL_CFDTHLSTS_THLEMP_Msk            (0x1UL)        /*!< THLEMP (Bitfield-Mask: 0x01)                          */
35910  #define R_CANFDL_CFDTHLSTS_THLFLL_Pos            (1UL)          /*!< THLFLL (Bit 1)                                        */
35911  #define R_CANFDL_CFDTHLSTS_THLFLL_Msk            (0x2UL)        /*!< THLFLL (Bitfield-Mask: 0x01)                          */
35912  #define R_CANFDL_CFDTHLSTS_THLELT_Pos            (2UL)          /*!< THLELT (Bit 2)                                        */
35913  #define R_CANFDL_CFDTHLSTS_THLELT_Msk            (0x4UL)        /*!< THLELT (Bitfield-Mask: 0x01)                          */
35914  #define R_CANFDL_CFDTHLSTS_THLIF_Pos             (3UL)          /*!< THLIF (Bit 3)                                         */
35915  #define R_CANFDL_CFDTHLSTS_THLIF_Msk             (0x8UL)        /*!< THLIF (Bitfield-Mask: 0x01)                           */
35916  #define R_CANFDL_CFDTHLSTS_THLMC_Pos             (8UL)          /*!< THLMC (Bit 8)                                         */
35917  #define R_CANFDL_CFDTHLSTS_THLMC_Msk             (0x3f00UL)     /*!< THLMC (Bitfield-Mask: 0x3f)                           */
35918 /* ======================================================  CFDTHLPCTR  ======================================================= */
35919  #define R_CANFDL_CFDTHLPCTR_THLPC_Pos            (0UL)          /*!< THLPC (Bit 0)                                         */
35920  #define R_CANFDL_CFDTHLPCTR_THLPC_Msk            (0xffUL)       /*!< THLPC (Bitfield-Mask: 0xff)                           */
35921 /* =====================================================  CFDGTINTSTS0  ====================================================== */
35922  #define R_CANFDL_CFDGTINTSTS0_TSIF0_Pos          (0UL)          /*!< TSIF0 (Bit 0)                                         */
35923  #define R_CANFDL_CFDGTINTSTS0_TSIF0_Msk          (0x1UL)        /*!< TSIF0 (Bitfield-Mask: 0x01)                           */
35924  #define R_CANFDL_CFDGTINTSTS0_TAIF0_Pos          (1UL)          /*!< TAIF0 (Bit 1)                                         */
35925  #define R_CANFDL_CFDGTINTSTS0_TAIF0_Msk          (0x2UL)        /*!< TAIF0 (Bitfield-Mask: 0x01)                           */
35926  #define R_CANFDL_CFDGTINTSTS0_TQIF0_Pos          (2UL)          /*!< TQIF0 (Bit 2)                                         */
35927  #define R_CANFDL_CFDGTINTSTS0_TQIF0_Msk          (0x4UL)        /*!< TQIF0 (Bitfield-Mask: 0x01)                           */
35928  #define R_CANFDL_CFDGTINTSTS0_CFTIF0_Pos         (3UL)          /*!< CFTIF0 (Bit 3)                                        */
35929  #define R_CANFDL_CFDGTINTSTS0_CFTIF0_Msk         (0x8UL)        /*!< CFTIF0 (Bitfield-Mask: 0x01)                          */
35930  #define R_CANFDL_CFDGTINTSTS0_THIF0_Pos          (4UL)          /*!< THIF0 (Bit 4)                                         */
35931  #define R_CANFDL_CFDGTINTSTS0_THIF0_Msk          (0x10UL)       /*!< THIF0 (Bitfield-Mask: 0x01)                           */
35932 /* ======================================================  CFDGTSTCFG  ======================================================= */
35933  #define R_CANFDL_CFDGTSTCFG_RTMPS_Pos            (16UL)         /*!< RTMPS (Bit 16)                                        */
35934  #define R_CANFDL_CFDGTSTCFG_RTMPS_Msk            (0x3ff0000UL)  /*!< RTMPS (Bitfield-Mask: 0x3ff)                          */
35935 /* ======================================================  CFDGTSTCTR  ======================================================= */
35936  #define R_CANFDL_CFDGTSTCTR_RTME_Pos             (2UL)          /*!< RTME (Bit 2)                                          */
35937  #define R_CANFDL_CFDGTSTCTR_RTME_Msk             (0x4UL)        /*!< RTME (Bitfield-Mask: 0x01)                            */
35938 /* =======================================================  CFDGFDCFG  ======================================================= */
35939  #define R_CANFDL_CFDGFDCFG_RPED_Pos              (0UL)          /*!< RPED (Bit 0)                                          */
35940  #define R_CANFDL_CFDGFDCFG_RPED_Msk              (0x1UL)        /*!< RPED (Bitfield-Mask: 0x01)                            */
35941  #define R_CANFDL_CFDGFDCFG_TSCCFG_Pos            (8UL)          /*!< TSCCFG (Bit 8)                                        */
35942  #define R_CANFDL_CFDGFDCFG_TSCCFG_Msk            (0x300UL)      /*!< TSCCFG (Bitfield-Mask: 0x03)                          */
35943 /* =======================================================  CFDGLOCKK  ======================================================= */
35944  #define R_CANFDL_CFDGLOCKK_LOCK_Pos              (0UL)          /*!< LOCK (Bit 0)                                          */
35945  #define R_CANFDL_CFDGLOCKK_LOCK_Msk              (0xffffUL)     /*!< LOCK (Bitfield-Mask: 0xffff)                          */
35946 /* =====================================================  CFDGAFLIGNENT  ===================================================== */
35947  #define R_CANFDL_CFDGAFLIGNENT_IRN_Pos           (0UL)          /*!< IRN (Bit 0)                                           */
35948  #define R_CANFDL_CFDGAFLIGNENT_IRN_Msk           (0x1fUL)       /*!< IRN (Bitfield-Mask: 0x1f)                             */
35949 /* =====================================================  CFDGAFLIGNCTR  ===================================================== */
35950  #define R_CANFDL_CFDGAFLIGNCTR_IREN_Pos          (0UL)          /*!< IREN (Bit 0)                                          */
35951  #define R_CANFDL_CFDGAFLIGNCTR_IREN_Msk          (0x1UL)        /*!< IREN (Bitfield-Mask: 0x01)                            */
35952  #define R_CANFDL_CFDGAFLIGNCTR_KEY_Pos           (8UL)          /*!< KEY (Bit 8)                                           */
35953  #define R_CANFDL_CFDGAFLIGNCTR_KEY_Msk           (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
35954 /* =======================================================  CFDCDTCT  ======================================================== */
35955  #define R_CANFDL_CFDCDTCT_RFDMAE0_Pos            (0UL)          /*!< RFDMAE0 (Bit 0)                                       */
35956  #define R_CANFDL_CFDCDTCT_RFDMAE0_Msk            (0x1UL)        /*!< RFDMAE0 (Bitfield-Mask: 0x01)                         */
35957  #define R_CANFDL_CFDCDTCT_RFDMAE1_Pos            (1UL)          /*!< RFDMAE1 (Bit 1)                                       */
35958  #define R_CANFDL_CFDCDTCT_RFDMAE1_Msk            (0x2UL)        /*!< RFDMAE1 (Bitfield-Mask: 0x01)                         */
35959  #define R_CANFDL_CFDCDTCT_CFDMAE0_Pos            (8UL)          /*!< CFDMAE0 (Bit 8)                                       */
35960  #define R_CANFDL_CFDCDTCT_CFDMAE0_Msk            (0x100UL)      /*!< CFDMAE0 (Bitfield-Mask: 0x01)                         */
35961 /* =======================================================  CFDCDTSTS  ======================================================= */
35962  #define R_CANFDL_CFDCDTSTS_RFDMASTS0_Pos         (0UL)          /*!< RFDMASTS0 (Bit 0)                                     */
35963  #define R_CANFDL_CFDCDTSTS_RFDMASTS0_Msk         (0x1UL)        /*!< RFDMASTS0 (Bitfield-Mask: 0x01)                       */
35964  #define R_CANFDL_CFDCDTSTS_RFDMASTS1_Pos         (1UL)          /*!< RFDMASTS1 (Bit 1)                                     */
35965  #define R_CANFDL_CFDCDTSTS_RFDMASTS1_Msk         (0x2UL)        /*!< RFDMASTS1 (Bitfield-Mask: 0x01)                       */
35966  #define R_CANFDL_CFDCDTSTS_CFDMASTS0_Pos         (8UL)          /*!< CFDMASTS0 (Bit 8)                                     */
35967  #define R_CANFDL_CFDCDTSTS_CFDMASTS0_Msk         (0x100UL)      /*!< CFDMASTS0 (Bitfield-Mask: 0x01)                       */
35968 /* =======================================================  CFDGRSTC  ======================================================== */
35969  #define R_CANFDL_CFDGRSTC_SRST_Pos               (0UL)          /*!< SRST (Bit 0)                                          */
35970  #define R_CANFDL_CFDGRSTC_SRST_Msk               (0x1UL)        /*!< SRST (Bitfield-Mask: 0x01)                            */
35971  #define R_CANFDL_CFDGRSTC_KEY_Pos                (8UL)          /*!< KEY (Bit 8)                                           */
35972  #define R_CANFDL_CFDGRSTC_KEY_Msk                (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
35973 /* =======================================================  CFDRPGACC  ======================================================= */
35974  #define R_CANFDL_CFDRPGACC_RDTA_Pos              (0UL)          /*!< RDTA (Bit 0)                                          */
35975  #define R_CANFDL_CFDRPGACC_RDTA_Msk              (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff)                      */
35976 
35977 /* =========================================================================================================================== */
35978 /* ================                                           R_CRC                                           ================ */
35979 /* =========================================================================================================================== */
35980 
35981 /* ========================================================  CRCCR0  ========================================================= */
35982  #define R_CRC_CRCCR0_DORCLR_Pos          (7UL)          /*!< DORCLR (Bit 7)                                        */
35983  #define R_CRC_CRCCR0_DORCLR_Msk          (0x80UL)       /*!< DORCLR (Bitfield-Mask: 0x01)                          */
35984  #define R_CRC_CRCCR0_LMS_Pos             (6UL)          /*!< LMS (Bit 6)                                           */
35985  #define R_CRC_CRCCR0_LMS_Msk             (0x40UL)       /*!< LMS (Bitfield-Mask: 0x01)                             */
35986  #define R_CRC_CRCCR0_GPS_Pos             (0UL)          /*!< GPS (Bit 0)                                           */
35987  #define R_CRC_CRCCR0_GPS_Msk             (0x7UL)        /*!< GPS (Bitfield-Mask: 0x07)                             */
35988 /* ========================================================  CRCCR1  ========================================================= */
35989  #define R_CRC_CRCCR1_CRCSEN_Pos          (7UL)          /*!< CRCSEN (Bit 7)                                        */
35990  #define R_CRC_CRCCR1_CRCSEN_Msk          (0x80UL)       /*!< CRCSEN (Bitfield-Mask: 0x01)                          */
35991  #define R_CRC_CRCCR1_CRCSWR_Pos          (6UL)          /*!< CRCSWR (Bit 6)                                        */
35992  #define R_CRC_CRCCR1_CRCSWR_Msk          (0x40UL)       /*!< CRCSWR (Bitfield-Mask: 0x01)                          */
35993 /* ========================================================  CRCDIR  ========================================================= */
35994  #define R_CRC_CRCDIR_CRCDIR_Pos          (0UL)          /*!< CRCDIR (Bit 0)                                        */
35995  #define R_CRC_CRCDIR_CRCDIR_Msk          (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff)                    */
35996 /* =======================================================  CRCDIR_BY  ======================================================= */
35997  #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos    (0UL)          /*!< CRCDIR_BY (Bit 0)                                     */
35998  #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk    (0xffUL)       /*!< CRCDIR_BY (Bitfield-Mask: 0xff)                       */
35999 /* ========================================================  CRCDOR  ========================================================= */
36000  #define R_CRC_CRCDOR_CRCDOR_Pos          (0UL)          /*!< CRCDOR (Bit 0)                                        */
36001  #define R_CRC_CRCDOR_CRCDOR_Msk          (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff)                    */
36002 /* =======================================================  CRCDOR_HA  ======================================================= */
36003  #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos    (0UL)          /*!< CRCDOR_HA (Bit 0)                                     */
36004  #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk    (0xffffUL)     /*!< CRCDOR_HA (Bitfield-Mask: 0xffff)                     */
36005 /* =======================================================  CRCDOR_BY  ======================================================= */
36006  #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos    (0UL)          /*!< CRCDOR_BY (Bit 0)                                     */
36007  #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk    (0xffUL)       /*!< CRCDOR_BY (Bitfield-Mask: 0xff)                       */
36008 /* ========================================================  CRCSAR  ========================================================= */
36009  #define R_CRC_CRCSAR_CRCSA_Pos           (0UL)          /*!< CRCSA (Bit 0)                                         */
36010  #define R_CRC_CRCSAR_CRCSA_Msk           (0x3fffUL)     /*!< CRCSA (Bitfield-Mask: 0x3fff)                         */
36011 
36012 /* =========================================================================================================================== */
36013 /* ================                                          R_CTSU                                           ================ */
36014 /* =========================================================================================================================== */
36015 
36016 /* ========================================================  CTSUCR0  ======================================================== */
36017  #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos       (7UL)      /*!< CTSUTXVSEL (Bit 7)                                    */
36018  #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk       (0x80UL)   /*!< CTSUTXVSEL (Bitfield-Mask: 0x01)                      */
36019  #define R_CTSU_CTSUCR0_CTSUINIT_Pos         (4UL)      /*!< CTSUINIT (Bit 4)                                      */
36020  #define R_CTSU_CTSUCR0_CTSUINIT_Msk         (0x10UL)   /*!< CTSUINIT (Bitfield-Mask: 0x01)                        */
36021  #define R_CTSU_CTSUCR0_CTSUIOC_Pos          (3UL)      /*!< CTSUIOC (Bit 3)                                       */
36022  #define R_CTSU_CTSUCR0_CTSUIOC_Msk          (0x8UL)    /*!< CTSUIOC (Bitfield-Mask: 0x01)                         */
36023  #define R_CTSU_CTSUCR0_CTSUSNZ_Pos          (2UL)      /*!< CTSUSNZ (Bit 2)                                       */
36024  #define R_CTSU_CTSUCR0_CTSUSNZ_Msk          (0x4UL)    /*!< CTSUSNZ (Bitfield-Mask: 0x01)                         */
36025  #define R_CTSU_CTSUCR0_CTSUCAP_Pos          (1UL)      /*!< CTSUCAP (Bit 1)                                       */
36026  #define R_CTSU_CTSUCR0_CTSUCAP_Msk          (0x2UL)    /*!< CTSUCAP (Bitfield-Mask: 0x01)                         */
36027  #define R_CTSU_CTSUCR0_CTSUSTRT_Pos         (0UL)      /*!< CTSUSTRT (Bit 0)                                      */
36028  #define R_CTSU_CTSUCR0_CTSUSTRT_Msk         (0x1UL)    /*!< CTSUSTRT (Bitfield-Mask: 0x01)                        */
36029 /* ========================================================  CTSUCR1  ======================================================== */
36030  #define R_CTSU_CTSUCR1_CTSUMD_Pos           (6UL)      /*!< CTSUMD (Bit 6)                                        */
36031  #define R_CTSU_CTSUCR1_CTSUMD_Msk           (0xc0UL)   /*!< CTSUMD (Bitfield-Mask: 0x03)                          */
36032  #define R_CTSU_CTSUCR1_CTSUCLK_Pos          (4UL)      /*!< CTSUCLK (Bit 4)                                       */
36033  #define R_CTSU_CTSUCR1_CTSUCLK_Msk          (0x30UL)   /*!< CTSUCLK (Bitfield-Mask: 0x03)                         */
36034  #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos       (3UL)      /*!< CTSUATUNE1 (Bit 3)                                    */
36035  #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk       (0x8UL)    /*!< CTSUATUNE1 (Bitfield-Mask: 0x01)                      */
36036  #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos       (2UL)      /*!< CTSUATUNE0 (Bit 2)                                    */
36037  #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk       (0x4UL)    /*!< CTSUATUNE0 (Bitfield-Mask: 0x01)                      */
36038  #define R_CTSU_CTSUCR1_CTSUCSW_Pos          (1UL)      /*!< CTSUCSW (Bit 1)                                       */
36039  #define R_CTSU_CTSUCR1_CTSUCSW_Msk          (0x2UL)    /*!< CTSUCSW (Bitfield-Mask: 0x01)                         */
36040  #define R_CTSU_CTSUCR1_CTSUPON_Pos          (0UL)      /*!< CTSUPON (Bit 0)                                       */
36041  #define R_CTSU_CTSUCR1_CTSUPON_Msk          (0x1UL)    /*!< CTSUPON (Bitfield-Mask: 0x01)                         */
36042 /* =======================================================  CTSUSDPRS  ======================================================= */
36043  #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos       (6UL)      /*!< CTSUSOFF (Bit 6)                                      */
36044  #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk       (0x40UL)   /*!< CTSUSOFF (Bitfield-Mask: 0x01)                        */
36045  #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos     (4UL)      /*!< CTSUPRMODE (Bit 4)                                    */
36046  #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk     (0x30UL)   /*!< CTSUPRMODE (Bitfield-Mask: 0x03)                      */
36047  #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos    (0UL)      /*!< CTSUPRRATIO (Bit 0)                                   */
36048  #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk    (0xfUL)    /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f)                     */
36049 /* ========================================================  CTSUSST  ======================================================== */
36050  #define R_CTSU_CTSUSST_CTSUSST_Pos          (0UL)      /*!< CTSUSST (Bit 0)                                       */
36051  #define R_CTSU_CTSUSST_CTSUSST_Msk          (0xffUL)   /*!< CTSUSST (Bitfield-Mask: 0xff)                         */
36052 /* =======================================================  CTSUMCH0  ======================================================== */
36053  #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos        (0UL)      /*!< CTSUMCH0 (Bit 0)                                      */
36054  #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk        (0x3fUL)   /*!< CTSUMCH0 (Bitfield-Mask: 0x3f)                        */
36055 /* =======================================================  CTSUMCH1  ======================================================== */
36056  #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos        (0UL)      /*!< CTSUMCH1 (Bit 0)                                      */
36057  #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk        (0x3fUL)   /*!< CTSUMCH1 (Bitfield-Mask: 0x3f)                        */
36058 /* =======================================================  CTSUCHAC  ======================================================== */
36059  #define R_CTSU_CTSUCHAC_TS_Pos              (0UL)      /*!< TS (Bit 0)                                            */
36060  #define R_CTSU_CTSUCHAC_TS_Msk              (0x1UL)    /*!< TS (Bitfield-Mask: 0x01)                              */
36061 /* =======================================================  CTSUCHTRC  ======================================================= */
36062  #define R_CTSU_CTSUCHTRC_TS_Pos             (0UL)      /*!< TS (Bit 0)                                            */
36063  #define R_CTSU_CTSUCHTRC_TS_Msk             (0x1UL)    /*!< TS (Bitfield-Mask: 0x01)                              */
36064 /* =======================================================  CTSUDCLKC  ======================================================= */
36065  #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos      (4UL)      /*!< CTSUSSCNT (Bit 4)                                     */
36066  #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk      (0x30UL)   /*!< CTSUSSCNT (Bitfield-Mask: 0x03)                       */
36067  #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos      (0UL)      /*!< CTSUSSMOD (Bit 0)                                     */
36068  #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk      (0x3UL)    /*!< CTSUSSMOD (Bitfield-Mask: 0x03)                       */
36069 /* ========================================================  CTSUST  ========================================================= */
36070  #define R_CTSU_CTSUST_CTSUPS_Pos            (7UL)      /*!< CTSUPS (Bit 7)                                        */
36071  #define R_CTSU_CTSUST_CTSUPS_Msk            (0x80UL)   /*!< CTSUPS (Bitfield-Mask: 0x01)                          */
36072  #define R_CTSU_CTSUST_CTSUROVF_Pos          (6UL)      /*!< CTSUROVF (Bit 6)                                      */
36073  #define R_CTSU_CTSUST_CTSUROVF_Msk          (0x40UL)   /*!< CTSUROVF (Bitfield-Mask: 0x01)                        */
36074  #define R_CTSU_CTSUST_CTSUSOVF_Pos          (5UL)      /*!< CTSUSOVF (Bit 5)                                      */
36075  #define R_CTSU_CTSUST_CTSUSOVF_Msk          (0x20UL)   /*!< CTSUSOVF (Bitfield-Mask: 0x01)                        */
36076  #define R_CTSU_CTSUST_CTSUDTSR_Pos          (4UL)      /*!< CTSUDTSR (Bit 4)                                      */
36077  #define R_CTSU_CTSUST_CTSUDTSR_Msk          (0x10UL)   /*!< CTSUDTSR (Bitfield-Mask: 0x01)                        */
36078  #define R_CTSU_CTSUST_CTSUSTC_Pos           (0UL)      /*!< CTSUSTC (Bit 0)                                       */
36079  #define R_CTSU_CTSUST_CTSUSTC_Msk           (0x7UL)    /*!< CTSUSTC (Bitfield-Mask: 0x07)                         */
36080 /* ========================================================  CTSUSSC  ======================================================== */
36081  #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos        (8UL)      /*!< CTSUSSDIV (Bit 8)                                     */
36082  #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk        (0xf00UL)  /*!< CTSUSSDIV (Bitfield-Mask: 0x0f)                       */
36083 /* ========================================================  CTSUSO0  ======================================================== */
36084  #define R_CTSU_CTSUSO0_CTSUSNUM_Pos         (10UL)     /*!< CTSUSNUM (Bit 10)                                     */
36085  #define R_CTSU_CTSUSO0_CTSUSNUM_Msk         (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f)                        */
36086  #define R_CTSU_CTSUSO0_CTSUSO_Pos           (0UL)      /*!< CTSUSO (Bit 0)                                        */
36087  #define R_CTSU_CTSUSO0_CTSUSO_Msk           (0x3ffUL)  /*!< CTSUSO (Bitfield-Mask: 0x3ff)                         */
36088 /* ========================================================  CTSUSO1  ======================================================== */
36089  #define R_CTSU_CTSUSO1_CTSUICOG_Pos         (13UL)     /*!< CTSUICOG (Bit 13)                                     */
36090  #define R_CTSU_CTSUSO1_CTSUICOG_Msk         (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03)                        */
36091  #define R_CTSU_CTSUSO1_CTSUSDPA_Pos         (8UL)      /*!< CTSUSDPA (Bit 8)                                      */
36092  #define R_CTSU_CTSUSO1_CTSUSDPA_Msk         (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f)                        */
36093  #define R_CTSU_CTSUSO1_CTSURICOA_Pos        (0UL)      /*!< CTSURICOA (Bit 0)                                     */
36094  #define R_CTSU_CTSUSO1_CTSURICOA_Msk        (0xffUL)   /*!< CTSURICOA (Bitfield-Mask: 0xff)                       */
36095 /* ========================================================  CTSUSC  ========================================================= */
36096  #define R_CTSU_CTSUSC_CTSUSC_Pos            (0UL)      /*!< CTSUSC (Bit 0)                                        */
36097  #define R_CTSU_CTSUSC_CTSUSC_Msk            (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff)                        */
36098 /* ========================================================  CTSURC  ========================================================= */
36099  #define R_CTSU_CTSURC_CTSURC_Pos            (0UL)      /*!< CTSURC (Bit 0)                                        */
36100  #define R_CTSU_CTSURC_CTSURC_Msk            (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff)                        */
36101 /* =======================================================  CTSUERRS  ======================================================== */
36102  #define R_CTSU_CTSUERRS_CTSUICOMP_Pos       (15UL)     /*!< CTSUICOMP (Bit 15)                                    */
36103  #define R_CTSU_CTSUERRS_CTSUICOMP_Msk       (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01)                       */
36104  #define R_CTSU_CTSUERRS_CTSUSPMD_Pos        (0UL)      /*!< CTSUSPMD (Bit 0)                                      */
36105  #define R_CTSU_CTSUERRS_CTSUSPMD_Msk        (0x3UL)    /*!< CTSUSPMD (Bitfield-Mask: 0x03)                        */
36106  #define R_CTSU_CTSUERRS_CTSUTSOD_Pos        (2UL)      /*!< CTSUTSOD (Bit 2)                                      */
36107  #define R_CTSU_CTSUERRS_CTSUTSOD_Msk        (0x4UL)    /*!< CTSUTSOD (Bitfield-Mask: 0x01)                        */
36108  #define R_CTSU_CTSUERRS_CTSUDRV_Pos         (3UL)      /*!< CTSUDRV (Bit 3)                                       */
36109  #define R_CTSU_CTSUERRS_CTSUDRV_Msk         (0x8UL)    /*!< CTSUDRV (Bitfield-Mask: 0x01)                         */
36110  #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos     (6UL)      /*!< CTSUCLKSEL1 (Bit 6)                                   */
36111  #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk     (0x40UL)   /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01)                     */
36112  #define R_CTSU_CTSUERRS_CTSUTSOC_Pos        (7UL)      /*!< CTSUTSOC (Bit 7)                                      */
36113  #define R_CTSU_CTSUERRS_CTSUTSOC_Msk        (0x80UL)   /*!< CTSUTSOC (Bitfield-Mask: 0x01)                        */
36114 /* =======================================================  CTSUTRMR  ======================================================== */
36115 
36116 /* =========================================================================================================================== */
36117 /* ================                                          R_CTSU2                                          ================ */
36118 /* =========================================================================================================================== */
36119 
36120 /* ========================================================  CTSUCRA  ======================================================== */
36121  #define R_CTSU2_CTSUCRA_STRT_Pos      (0UL)          /*!< STRT (Bit 0)                                          */
36122  #define R_CTSU2_CTSUCRA_STRT_Msk      (0x1UL)        /*!< STRT (Bitfield-Mask: 0x01)                            */
36123  #define R_CTSU2_CTSUCRA_CAP_Pos       (1UL)          /*!< CAP (Bit 1)                                           */
36124  #define R_CTSU2_CTSUCRA_CAP_Msk       (0x2UL)        /*!< CAP (Bitfield-Mask: 0x01)                             */
36125  #define R_CTSU2_CTSUCRA_SNZ_Pos       (2UL)          /*!< SNZ (Bit 2)                                           */
36126  #define R_CTSU2_CTSUCRA_SNZ_Msk       (0x4UL)        /*!< SNZ (Bitfield-Mask: 0x01)                             */
36127  #define R_CTSU2_CTSUCRA_CFCON_Pos     (3UL)          /*!< CFCON (Bit 3)                                         */
36128  #define R_CTSU2_CTSUCRA_CFCON_Msk     (0x8UL)        /*!< CFCON (Bitfield-Mask: 0x01)                           */
36129  #define R_CTSU2_CTSUCRA_INIT_Pos      (4UL)          /*!< INIT (Bit 4)                                          */
36130  #define R_CTSU2_CTSUCRA_INIT_Msk      (0x10UL)       /*!< INIT (Bitfield-Mask: 0x01)                            */
36131  #define R_CTSU2_CTSUCRA_PUMPON_Pos    (5UL)          /*!< PUMPON (Bit 5)                                        */
36132  #define R_CTSU2_CTSUCRA_PUMPON_Msk    (0x20UL)       /*!< PUMPON (Bitfield-Mask: 0x01)                          */
36133  #define R_CTSU2_CTSUCRA_TXVSEL_Pos    (6UL)          /*!< TXVSEL (Bit 6)                                        */
36134  #define R_CTSU2_CTSUCRA_TXVSEL_Msk    (0xc0UL)       /*!< TXVSEL (Bitfield-Mask: 0x03)                          */
36135  #define R_CTSU2_CTSUCRA_PON_Pos       (8UL)          /*!< PON (Bit 8)                                           */
36136  #define R_CTSU2_CTSUCRA_PON_Msk       (0x100UL)      /*!< PON (Bitfield-Mask: 0x01)                             */
36137  #define R_CTSU2_CTSUCRA_CSW_Pos       (9UL)          /*!< CSW (Bit 9)                                           */
36138  #define R_CTSU2_CTSUCRA_CSW_Msk       (0x200UL)      /*!< CSW (Bitfield-Mask: 0x01)                             */
36139  #define R_CTSU2_CTSUCRA_ATUNE0_Pos    (10UL)         /*!< ATUNE0 (Bit 10)                                       */
36140  #define R_CTSU2_CTSUCRA_ATUNE0_Msk    (0x400UL)      /*!< ATUNE0 (Bitfield-Mask: 0x01)                          */
36141  #define R_CTSU2_CTSUCRA_ATUNE1_Pos    (11UL)         /*!< ATUNE1 (Bit 11)                                       */
36142  #define R_CTSU2_CTSUCRA_ATUNE1_Msk    (0x800UL)      /*!< ATUNE1 (Bitfield-Mask: 0x01)                          */
36143  #define R_CTSU2_CTSUCRA_CLK_Pos       (12UL)         /*!< CLK (Bit 12)                                          */
36144  #define R_CTSU2_CTSUCRA_CLK_Msk       (0x3000UL)     /*!< CLK (Bitfield-Mask: 0x03)                             */
36145  #define R_CTSU2_CTSUCRA_MD0_Pos       (14UL)         /*!< MD0 (Bit 14)                                          */
36146  #define R_CTSU2_CTSUCRA_MD0_Msk       (0x4000UL)     /*!< MD0 (Bitfield-Mask: 0x01)                             */
36147  #define R_CTSU2_CTSUCRA_MD1_Pos       (15UL)         /*!< MD1 (Bit 15)                                          */
36148  #define R_CTSU2_CTSUCRA_MD1_Msk       (0x8000UL)     /*!< MD1 (Bitfield-Mask: 0x01)                             */
36149  #define R_CTSU2_CTSUCRA_MD2_Pos       (16UL)         /*!< MD2 (Bit 16)                                          */
36150  #define R_CTSU2_CTSUCRA_MD2_Msk       (0x10000UL)    /*!< MD2 (Bitfield-Mask: 0x01)                             */
36151  #define R_CTSU2_CTSUCRA_ATUNE2_Pos    (17UL)         /*!< ATUNE2 (Bit 17)                                       */
36152  #define R_CTSU2_CTSUCRA_ATUNE2_Msk    (0x20000UL)    /*!< ATUNE2 (Bitfield-Mask: 0x01)                          */
36153  #define R_CTSU2_CTSUCRA_LOAD_Pos      (18UL)         /*!< LOAD (Bit 18)                                         */
36154  #define R_CTSU2_CTSUCRA_LOAD_Msk      (0xc0000UL)    /*!< LOAD (Bitfield-Mask: 0x03)                            */
36155  #define R_CTSU2_CTSUCRA_POSEL_Pos     (20UL)         /*!< POSEL (Bit 20)                                        */
36156  #define R_CTSU2_CTSUCRA_POSEL_Msk     (0x300000UL)   /*!< POSEL (Bitfield-Mask: 0x03)                           */
36157  #define R_CTSU2_CTSUCRA_SDPSEL_Pos    (22UL)         /*!< SDPSEL (Bit 22)                                       */
36158  #define R_CTSU2_CTSUCRA_SDPSEL_Msk    (0x400000UL)   /*!< SDPSEL (Bitfield-Mask: 0x01)                          */
36159  #define R_CTSU2_CTSUCRA_PCSEL_Pos     (23UL)         /*!< PCSEL (Bit 23)                                        */
36160  #define R_CTSU2_CTSUCRA_PCSEL_Msk     (0x800000UL)   /*!< PCSEL (Bitfield-Mask: 0x01)                           */
36161  #define R_CTSU2_CTSUCRA_STCLK_Pos     (24UL)         /*!< STCLK (Bit 24)                                        */
36162  #define R_CTSU2_CTSUCRA_STCLK_Msk     (0x3f000000UL) /*!< STCLK (Bitfield-Mask: 0x3f)                           */
36163  #define R_CTSU2_CTSUCRA_DCMODE_Pos    (30UL)         /*!< DCMODE (Bit 30)                                       */
36164  #define R_CTSU2_CTSUCRA_DCMODE_Msk    (0x40000000UL) /*!< DCMODE (Bitfield-Mask: 0x01)                          */
36165  #define R_CTSU2_CTSUCRA_DCBACK_Pos    (31UL)         /*!< DCBACK (Bit 31)                                       */
36166  #define R_CTSU2_CTSUCRA_DCBACK_Msk    (0x80000000UL) /*!< DCBACK (Bitfield-Mask: 0x01)                          */
36167 /* =======================================================  CTSUCRAL  ======================================================== */
36168 /* ========================================================  CTSUCR0  ======================================================== */
36169 /* ========================================================  CTSUCR1  ======================================================== */
36170 /* =======================================================  CTSUCRAH  ======================================================== */
36171 /* ========================================================  CTSUCR2  ======================================================== */
36172 /* ========================================================  CTSUCR3  ======================================================== */
36173 /* ========================================================  CTSUCRB  ======================================================== */
36174  #define R_CTSU2_CTSUCRB_PRRATIO_Pos    (0UL)          /*!< PRRATIO (Bit 0)                                       */
36175  #define R_CTSU2_CTSUCRB_PRRATIO_Msk    (0xfUL)        /*!< PRRATIO (Bitfield-Mask: 0x0f)                         */
36176  #define R_CTSU2_CTSUCRB_PRMODE_Pos     (4UL)          /*!< PRMODE (Bit 4)                                        */
36177  #define R_CTSU2_CTSUCRB_PRMODE_Msk     (0x30UL)       /*!< PRMODE (Bitfield-Mask: 0x03)                          */
36178  #define R_CTSU2_CTSUCRB_SOFF_Pos       (6UL)          /*!< SOFF (Bit 6)                                          */
36179  #define R_CTSU2_CTSUCRB_SOFF_Msk       (0x40UL)       /*!< SOFF (Bitfield-Mask: 0x01)                            */
36180  #define R_CTSU2_CTSUCRB_PROFF_Pos      (7UL)          /*!< PROFF (Bit 7)                                         */
36181  #define R_CTSU2_CTSUCRB_PROFF_Msk      (0x80UL)       /*!< PROFF (Bitfield-Mask: 0x01)                           */
36182  #define R_CTSU2_CTSUCRB_SST_Pos        (8UL)          /*!< SST (Bit 8)                                           */
36183  #define R_CTSU2_CTSUCRB_SST_Msk        (0xff00UL)     /*!< SST (Bitfield-Mask: 0xff)                             */
36184  #define R_CTSU2_CTSUCRB_SSMOD_Pos      (24UL)         /*!< SSMOD (Bit 24)                                        */
36185  #define R_CTSU2_CTSUCRB_SSMOD_Msk      (0x7000000UL)  /*!< SSMOD (Bitfield-Mask: 0x07)                           */
36186  #define R_CTSU2_CTSUCRB_SSCNT_Pos      (28UL)         /*!< SSCNT (Bit 28)                                        */
36187  #define R_CTSU2_CTSUCRB_SSCNT_Msk      (0x30000000UL) /*!< SSCNT (Bitfield-Mask: 0x03)                           */
36188 /* =======================================================  CTSUCRBL  ======================================================== */
36189 /* =======================================================  CTSUSDPRS  ======================================================= */
36190 /* ========================================================  CTSUSST  ======================================================== */
36191 /* =======================================================  CTSUCRBH  ======================================================== */
36192 /* =======================================================  CTSUDCLKC  ======================================================= */
36193 /* ========================================================  CTSUMCH  ======================================================== */
36194  #define R_CTSU2_CTSUMCH_MCH0_Pos    (0UL)       /*!< MCH0 (Bit 0)                                          */
36195  #define R_CTSU2_CTSUMCH_MCH0_Msk    (0x3fUL)    /*!< MCH0 (Bitfield-Mask: 0x3f)                            */
36196  #define R_CTSU2_CTSUMCH_MCH1_Pos    (8UL)       /*!< MCH1 (Bit 8)                                          */
36197  #define R_CTSU2_CTSUMCH_MCH1_Msk    (0x3f00UL)  /*!< MCH1 (Bitfield-Mask: 0x3f)                            */
36198  #define R_CTSU2_CTSUMCH_MCA0_Pos    (16UL)      /*!< MCA0 (Bit 16)                                         */
36199  #define R_CTSU2_CTSUMCH_MCA0_Msk    (0x10000UL) /*!< MCA0 (Bitfield-Mask: 0x01)                            */
36200  #define R_CTSU2_CTSUMCH_MCA1_Pos    (17UL)      /*!< MCA1 (Bit 17)                                         */
36201  #define R_CTSU2_CTSUMCH_MCA1_Msk    (0x20000UL) /*!< MCA1 (Bitfield-Mask: 0x01)                            */
36202  #define R_CTSU2_CTSUMCH_MCA2_Pos    (18UL)      /*!< MCA2 (Bit 18)                                         */
36203  #define R_CTSU2_CTSUMCH_MCA2_Msk    (0x40000UL) /*!< MCA2 (Bitfield-Mask: 0x01)                            */
36204  #define R_CTSU2_CTSUMCH_MCA3_Pos    (19UL)      /*!< MCA3 (Bit 19)                                         */
36205  #define R_CTSU2_CTSUMCH_MCA3_Msk    (0x80000UL) /*!< MCA3 (Bitfield-Mask: 0x01)                            */
36206 /* =======================================================  CTSUMCHL  ======================================================== */
36207 /* =======================================================  CTSUMCH0  ======================================================== */
36208 /* =======================================================  CTSUMCH1  ======================================================== */
36209 /* =======================================================  CTSUMCHH  ======================================================== */
36210 /* =======================================================  CTSUMFAF  ======================================================== */
36211 /* =======================================================  CTSUCHACA  ======================================================= */
36212  #define R_CTSU2_CTSUCHACA_CHAC00_Pos    (0UL)          /*!< CHAC00 (Bit 0)                                        */
36213  #define R_CTSU2_CTSUCHACA_CHAC00_Msk    (0x1UL)        /*!< CHAC00 (Bitfield-Mask: 0x01)                          */
36214  #define R_CTSU2_CTSUCHACA_CHAC02_Pos    (2UL)          /*!< CHAC02 (Bit 2)                                        */
36215  #define R_CTSU2_CTSUCHACA_CHAC02_Msk    (0x4UL)        /*!< CHAC02 (Bitfield-Mask: 0x01)                          */
36216  #define R_CTSU2_CTSUCHACA_CHAC04_Pos    (4UL)          /*!< CHAC04 (Bit 4)                                        */
36217  #define R_CTSU2_CTSUCHACA_CHAC04_Msk    (0x10UL)       /*!< CHAC04 (Bitfield-Mask: 0x01)                          */
36218  #define R_CTSU2_CTSUCHACA_CHAC05_Pos    (5UL)          /*!< CHAC05 (Bit 5)                                        */
36219  #define R_CTSU2_CTSUCHACA_CHAC05_Msk    (0x20UL)       /*!< CHAC05 (Bitfield-Mask: 0x01)                          */
36220  #define R_CTSU2_CTSUCHACA_CHAC06_Pos    (6UL)          /*!< CHAC06 (Bit 6)                                        */
36221  #define R_CTSU2_CTSUCHACA_CHAC06_Msk    (0x40UL)       /*!< CHAC06 (Bitfield-Mask: 0x01)                          */
36222  #define R_CTSU2_CTSUCHACA_CHAC07_Pos    (7UL)          /*!< CHAC07 (Bit 7)                                        */
36223  #define R_CTSU2_CTSUCHACA_CHAC07_Msk    (0x80UL)       /*!< CHAC07 (Bitfield-Mask: 0x01)                          */
36224  #define R_CTSU2_CTSUCHACA_CHAC08_Pos    (8UL)          /*!< CHAC08 (Bit 8)                                        */
36225  #define R_CTSU2_CTSUCHACA_CHAC08_Msk    (0x100UL)      /*!< CHAC08 (Bitfield-Mask: 0x01)                          */
36226  #define R_CTSU2_CTSUCHACA_CHAC09_Pos    (9UL)          /*!< CHAC09 (Bit 9)                                        */
36227  #define R_CTSU2_CTSUCHACA_CHAC09_Msk    (0x200UL)      /*!< CHAC09 (Bitfield-Mask: 0x01)                          */
36228  #define R_CTSU2_CTSUCHACA_CHAC10_Pos    (10UL)         /*!< CHAC10 (Bit 10)                                       */
36229  #define R_CTSU2_CTSUCHACA_CHAC10_Msk    (0x400UL)      /*!< CHAC10 (Bitfield-Mask: 0x01)                          */
36230  #define R_CTSU2_CTSUCHACA_CHAC11_Pos    (11UL)         /*!< CHAC11 (Bit 11)                                       */
36231  #define R_CTSU2_CTSUCHACA_CHAC11_Msk    (0x800UL)      /*!< CHAC11 (Bitfield-Mask: 0x01)                          */
36232  #define R_CTSU2_CTSUCHACA_CHAC12_Pos    (12UL)         /*!< CHAC12 (Bit 12)                                       */
36233  #define R_CTSU2_CTSUCHACA_CHAC12_Msk    (0x1000UL)     /*!< CHAC12 (Bitfield-Mask: 0x01)                          */
36234  #define R_CTSU2_CTSUCHACA_CHAC13_Pos    (13UL)         /*!< CHAC13 (Bit 13)                                       */
36235  #define R_CTSU2_CTSUCHACA_CHAC13_Msk    (0x2000UL)     /*!< CHAC13 (Bitfield-Mask: 0x01)                          */
36236  #define R_CTSU2_CTSUCHACA_CHAC14_Pos    (14UL)         /*!< CHAC14 (Bit 14)                                       */
36237  #define R_CTSU2_CTSUCHACA_CHAC14_Msk    (0x4000UL)     /*!< CHAC14 (Bitfield-Mask: 0x01)                          */
36238  #define R_CTSU2_CTSUCHACA_CHAC15_Pos    (15UL)         /*!< CHAC15 (Bit 15)                                       */
36239  #define R_CTSU2_CTSUCHACA_CHAC15_Msk    (0x8000UL)     /*!< CHAC15 (Bitfield-Mask: 0x01)                          */
36240  #define R_CTSU2_CTSUCHACA_CHAC16_Pos    (16UL)         /*!< CHAC16 (Bit 16)                                       */
36241  #define R_CTSU2_CTSUCHACA_CHAC16_Msk    (0x10000UL)    /*!< CHAC16 (Bitfield-Mask: 0x01)                          */
36242  #define R_CTSU2_CTSUCHACA_CHAC17_Pos    (17UL)         /*!< CHAC17 (Bit 17)                                       */
36243  #define R_CTSU2_CTSUCHACA_CHAC17_Msk    (0x20000UL)    /*!< CHAC17 (Bitfield-Mask: 0x01)                          */
36244  #define R_CTSU2_CTSUCHACA_CHAC18_Pos    (18UL)         /*!< CHAC18 (Bit 18)                                       */
36245  #define R_CTSU2_CTSUCHACA_CHAC18_Msk    (0x40000UL)    /*!< CHAC18 (Bitfield-Mask: 0x01)                          */
36246  #define R_CTSU2_CTSUCHACA_CHAC21_Pos    (21UL)         /*!< CHAC21 (Bit 21)                                       */
36247  #define R_CTSU2_CTSUCHACA_CHAC21_Msk    (0x200000UL)   /*!< CHAC21 (Bitfield-Mask: 0x01)                          */
36248  #define R_CTSU2_CTSUCHACA_CHAC22_Pos    (22UL)         /*!< CHAC22 (Bit 22)                                       */
36249  #define R_CTSU2_CTSUCHACA_CHAC22_Msk    (0x400000UL)   /*!< CHAC22 (Bitfield-Mask: 0x01)                          */
36250  #define R_CTSU2_CTSUCHACA_CHAC23_Pos    (23UL)         /*!< CHAC23 (Bit 23)                                       */
36251  #define R_CTSU2_CTSUCHACA_CHAC23_Msk    (0x800000UL)   /*!< CHAC23 (Bitfield-Mask: 0x01)                          */
36252  #define R_CTSU2_CTSUCHACA_CHAC24_Pos    (24UL)         /*!< CHAC24 (Bit 24)                                       */
36253  #define R_CTSU2_CTSUCHACA_CHAC24_Msk    (0x1000000UL)  /*!< CHAC24 (Bitfield-Mask: 0x01)                          */
36254  #define R_CTSU2_CTSUCHACA_CHAC25_Pos    (25UL)         /*!< CHAC25 (Bit 25)                                       */
36255  #define R_CTSU2_CTSUCHACA_CHAC25_Msk    (0x2000000UL)  /*!< CHAC25 (Bitfield-Mask: 0x01)                          */
36256  #define R_CTSU2_CTSUCHACA_CHAC26_Pos    (26UL)         /*!< CHAC26 (Bit 26)                                       */
36257  #define R_CTSU2_CTSUCHACA_CHAC26_Msk    (0x4000000UL)  /*!< CHAC26 (Bitfield-Mask: 0x01)                          */
36258  #define R_CTSU2_CTSUCHACA_CHAC27_Pos    (27UL)         /*!< CHAC27 (Bit 27)                                       */
36259  #define R_CTSU2_CTSUCHACA_CHAC27_Msk    (0x8000000UL)  /*!< CHAC27 (Bitfield-Mask: 0x01)                          */
36260  #define R_CTSU2_CTSUCHACA_CHAC28_Pos    (28UL)         /*!< CHAC28 (Bit 28)                                       */
36261  #define R_CTSU2_CTSUCHACA_CHAC28_Msk    (0x10000000UL) /*!< CHAC28 (Bitfield-Mask: 0x01)                          */
36262  #define R_CTSU2_CTSUCHACA_CHAC29_Pos    (29UL)         /*!< CHAC29 (Bit 29)                                       */
36263  #define R_CTSU2_CTSUCHACA_CHAC29_Msk    (0x20000000UL) /*!< CHAC29 (Bitfield-Mask: 0x01)                          */
36264  #define R_CTSU2_CTSUCHACA_CHAC30_Pos    (30UL)         /*!< CHAC30 (Bit 30)                                       */
36265  #define R_CTSU2_CTSUCHACA_CHAC30_Msk    (0x40000000UL) /*!< CHAC30 (Bitfield-Mask: 0x01)                          */
36266  #define R_CTSU2_CTSUCHACA_CHAC31_Pos    (31UL)         /*!< CHAC31 (Bit 31)                                       */
36267  #define R_CTSU2_CTSUCHACA_CHAC31_Msk    (0x80000000UL) /*!< CHAC31 (Bitfield-Mask: 0x01)                          */
36268 /* ======================================================  CTSUCHACAL  ======================================================= */
36269 /* =======================================================  CTSUCHAC0  ======================================================= */
36270 /* =======================================================  CTSUCHAC1  ======================================================= */
36271 /* ======================================================  CTSUCHACAH  ======================================================= */
36272 /* =======================================================  CTSUCHAC2  ======================================================= */
36273 /* =======================================================  CTSUCHAC3  ======================================================= */
36274 /* =======================================================  CTSUCHACB  ======================================================= */
36275  #define R_CTSU2_CTSUCHACB_CHAC32_Pos      (0UL)          /*!< CHAC32 (Bit 0)                                        */
36276  #define R_CTSU2_CTSUCHACB_CHAC32_Msk      (0x1UL)        /*!< CHAC32 (Bitfield-Mask: 0x01)                          */
36277  #define R_CTSU2_CTSUCHACB_CHAC33_Pos      (1UL)          /*!< CHAC33 (Bit 1)                                        */
36278  #define R_CTSU2_CTSUCHACB_CHAC33_Msk      (0x2UL)        /*!< CHAC33 (Bitfield-Mask: 0x01)                          */
36279  #define R_CTSU2_CTSUCHACB_CHAC34_Pos      (2UL)          /*!< CHAC34 (Bit 2)                                        */
36280  #define R_CTSU2_CTSUCHACB_CHAC34_Msk      (0x4UL)        /*!< CHAC34 (Bitfield-Mask: 0x01)                          */
36281  #define R_CTSU2_CTSUCHACB_CHAC35_Pos      (3UL)          /*!< CHAC35 (Bit 3)                                        */
36282  #define R_CTSU2_CTSUCHACB_CHAC35_Msk      (0x8UL)        /*!< CHAC35 (Bitfield-Mask: 0x01)                          */
36283 /* ======================================================  CTSUCHACBL  ======================================================= */
36284 /* =======================================================  CTSUCHAC4  ======================================================= */
36285 /* ======================================================  CTSUCHTRCA  ======================================================= */
36286  #define R_CTSU2_CTSUCHTRCA_CHTRC_Pos      (0UL)          /*!< CHTRC (Bit 0)                                         */
36287  #define R_CTSU2_CTSUCHTRCA_CHTRC_Msk      (0x1UL)        /*!< CHTRC (Bitfield-Mask: 0x01)                           */
36288  #define R_CTSU2_CTSUCHTRCA_CHTRC02_Pos    (2UL)          /*!< CHTRC02 (Bit 2)                                       */
36289  #define R_CTSU2_CTSUCHTRCA_CHTRC02_Msk    (0x4UL)        /*!< CHTRC02 (Bitfield-Mask: 0x01)                         */
36290  #define R_CTSU2_CTSUCHTRCA_CHTRC04_Pos    (4UL)          /*!< CHTRC04 (Bit 4)                                       */
36291  #define R_CTSU2_CTSUCHTRCA_CHTRC04_Msk    (0x10UL)       /*!< CHTRC04 (Bitfield-Mask: 0x01)                         */
36292  #define R_CTSU2_CTSUCHTRCA_CHTRC05_Pos    (5UL)          /*!< CHTRC05 (Bit 5)                                       */
36293  #define R_CTSU2_CTSUCHTRCA_CHTRC05_Msk    (0x20UL)       /*!< CHTRC05 (Bitfield-Mask: 0x01)                         */
36294  #define R_CTSU2_CTSUCHTRCA_CHTRC06_Pos    (6UL)          /*!< CHTRC06 (Bit 6)                                       */
36295  #define R_CTSU2_CTSUCHTRCA_CHTRC06_Msk    (0x40UL)       /*!< CHTRC06 (Bitfield-Mask: 0x01)                         */
36296  #define R_CTSU2_CTSUCHTRCA_CHTRC07_Pos    (7UL)          /*!< CHTRC07 (Bit 7)                                       */
36297  #define R_CTSU2_CTSUCHTRCA_CHTRC07_Msk    (0x80UL)       /*!< CHTRC07 (Bitfield-Mask: 0x01)                         */
36298  #define R_CTSU2_CTSUCHTRCA_CHTRC08_Pos    (8UL)          /*!< CHTRC08 (Bit 8)                                       */
36299  #define R_CTSU2_CTSUCHTRCA_CHTRC08_Msk    (0x100UL)      /*!< CHTRC08 (Bitfield-Mask: 0x01)                         */
36300  #define R_CTSU2_CTSUCHTRCA_CHTRC09_Pos    (9UL)          /*!< CHTRC09 (Bit 9)                                       */
36301  #define R_CTSU2_CTSUCHTRCA_CHTRC09_Msk    (0x200UL)      /*!< CHTRC09 (Bitfield-Mask: 0x01)                         */
36302  #define R_CTSU2_CTSUCHTRCA_CHTRC10_Pos    (10UL)         /*!< CHTRC10 (Bit 10)                                      */
36303  #define R_CTSU2_CTSUCHTRCA_CHTRC10_Msk    (0x400UL)      /*!< CHTRC10 (Bitfield-Mask: 0x01)                         */
36304  #define R_CTSU2_CTSUCHTRCA_CHTRC11_Pos    (11UL)         /*!< CHTRC11 (Bit 11)                                      */
36305  #define R_CTSU2_CTSUCHTRCA_CHTRC11_Msk    (0x800UL)      /*!< CHTRC11 (Bitfield-Mask: 0x01)                         */
36306  #define R_CTSU2_CTSUCHTRCA_CHTRC12_Pos    (12UL)         /*!< CHTRC12 (Bit 12)                                      */
36307  #define R_CTSU2_CTSUCHTRCA_CHTRC12_Msk    (0x1000UL)     /*!< CHTRC12 (Bitfield-Mask: 0x01)                         */
36308  #define R_CTSU2_CTSUCHTRCA_CHTRC13_Pos    (13UL)         /*!< CHTRC13 (Bit 13)                                      */
36309  #define R_CTSU2_CTSUCHTRCA_CHTRC13_Msk    (0x2000UL)     /*!< CHTRC13 (Bitfield-Mask: 0x01)                         */
36310  #define R_CTSU2_CTSUCHTRCA_CHTRC14_Pos    (14UL)         /*!< CHTRC14 (Bit 14)                                      */
36311  #define R_CTSU2_CTSUCHTRCA_CHTRC14_Msk    (0x4000UL)     /*!< CHTRC14 (Bitfield-Mask: 0x01)                         */
36312  #define R_CTSU2_CTSUCHTRCA_CHTRC15_Pos    (15UL)         /*!< CHTRC15 (Bit 15)                                      */
36313  #define R_CTSU2_CTSUCHTRCA_CHTRC15_Msk    (0x8000UL)     /*!< CHTRC15 (Bitfield-Mask: 0x01)                         */
36314  #define R_CTSU2_CTSUCHTRCA_CHTRC16_Pos    (16UL)         /*!< CHTRC16 (Bit 16)                                      */
36315  #define R_CTSU2_CTSUCHTRCA_CHTRC16_Msk    (0x10000UL)    /*!< CHTRC16 (Bitfield-Mask: 0x01)                         */
36316  #define R_CTSU2_CTSUCHTRCA_CHTRC17_Pos    (17UL)         /*!< CHTRC17 (Bit 17)                                      */
36317  #define R_CTSU2_CTSUCHTRCA_CHTRC17_Msk    (0x20000UL)    /*!< CHTRC17 (Bitfield-Mask: 0x01)                         */
36318  #define R_CTSU2_CTSUCHTRCA_CHTRC18_Pos    (18UL)         /*!< CHTRC18 (Bit 18)                                      */
36319  #define R_CTSU2_CTSUCHTRCA_CHTRC18_Msk    (0x40000UL)    /*!< CHTRC18 (Bitfield-Mask: 0x01)                         */
36320  #define R_CTSU2_CTSUCHTRCA_CHTRC21_Pos    (21UL)         /*!< CHTRC21 (Bit 21)                                      */
36321  #define R_CTSU2_CTSUCHTRCA_CHTRC21_Msk    (0x200000UL)   /*!< CHTRC21 (Bitfield-Mask: 0x01)                         */
36322  #define R_CTSU2_CTSUCHTRCA_CHTRC22_Pos    (22UL)         /*!< CHTRC22 (Bit 22)                                      */
36323  #define R_CTSU2_CTSUCHTRCA_CHTRC22_Msk    (0x400000UL)   /*!< CHTRC22 (Bitfield-Mask: 0x01)                         */
36324  #define R_CTSU2_CTSUCHTRCA_CHTRC23_Pos    (23UL)         /*!< CHTRC23 (Bit 23)                                      */
36325  #define R_CTSU2_CTSUCHTRCA_CHTRC23_Msk    (0x800000UL)   /*!< CHTRC23 (Bitfield-Mask: 0x01)                         */
36326  #define R_CTSU2_CTSUCHTRCA_CHTRC24_Pos    (24UL)         /*!< CHTRC24 (Bit 24)                                      */
36327  #define R_CTSU2_CTSUCHTRCA_CHTRC24_Msk    (0x1000000UL)  /*!< CHTRC24 (Bitfield-Mask: 0x01)                         */
36328  #define R_CTSU2_CTSUCHTRCA_CHTRC25_Pos    (25UL)         /*!< CHTRC25 (Bit 25)                                      */
36329  #define R_CTSU2_CTSUCHTRCA_CHTRC25_Msk    (0x2000000UL)  /*!< CHTRC25 (Bitfield-Mask: 0x01)                         */
36330  #define R_CTSU2_CTSUCHTRCA_CHTRC26_Pos    (26UL)         /*!< CHTRC26 (Bit 26)                                      */
36331  #define R_CTSU2_CTSUCHTRCA_CHTRC26_Msk    (0x4000000UL)  /*!< CHTRC26 (Bitfield-Mask: 0x01)                         */
36332  #define R_CTSU2_CTSUCHTRCA_CHTRC27_Pos    (27UL)         /*!< CHTRC27 (Bit 27)                                      */
36333  #define R_CTSU2_CTSUCHTRCA_CHTRC27_Msk    (0x8000000UL)  /*!< CHTRC27 (Bitfield-Mask: 0x01)                         */
36334  #define R_CTSU2_CTSUCHTRCA_CHTRC28_Pos    (28UL)         /*!< CHTRC28 (Bit 28)                                      */
36335  #define R_CTSU2_CTSUCHTRCA_CHTRC28_Msk    (0x10000000UL) /*!< CHTRC28 (Bitfield-Mask: 0x01)                         */
36336  #define R_CTSU2_CTSUCHTRCA_CHTRC29_Pos    (29UL)         /*!< CHTRC29 (Bit 29)                                      */
36337  #define R_CTSU2_CTSUCHTRCA_CHTRC29_Msk    (0x20000000UL) /*!< CHTRC29 (Bitfield-Mask: 0x01)                         */
36338  #define R_CTSU2_CTSUCHTRCA_CHTRC30_Pos    (30UL)         /*!< CHTRC30 (Bit 30)                                      */
36339  #define R_CTSU2_CTSUCHTRCA_CHTRC30_Msk    (0x40000000UL) /*!< CHTRC30 (Bitfield-Mask: 0x01)                         */
36340  #define R_CTSU2_CTSUCHTRCA_CHTRC31_Pos    (31UL)         /*!< CHTRC31 (Bit 31)                                      */
36341  #define R_CTSU2_CTSUCHTRCA_CHTRC31_Msk    (0x80000000UL) /*!< CHTRC31 (Bitfield-Mask: 0x01)                         */
36342 /* ======================================================  CTSUCHTRCAL  ====================================================== */
36343 /* ======================================================  CTSUCHTRC0  ======================================================= */
36344 /* ======================================================  CTSUCHTRC1  ======================================================= */
36345 /* ======================================================  CTSUCHTRCAH  ====================================================== */
36346 /* ======================================================  CTSUCHTRC2  ======================================================= */
36347 /* ======================================================  CTSUCHTRC3  ======================================================= */
36348 /* ======================================================  CTSUCHTRCB  ======================================================= */
36349  #define R_CTSU2_CTSUCHTRCB_CHTRC32_Pos    (0UL)        /*!< CHTRC32 (Bit 0)                                       */
36350  #define R_CTSU2_CTSUCHTRCB_CHTRC32_Msk    (0x1UL)      /*!< CHTRC32 (Bitfield-Mask: 0x01)                         */
36351  #define R_CTSU2_CTSUCHTRCB_CHTRC33_Pos    (1UL)        /*!< CHTRC33 (Bit 1)                                       */
36352  #define R_CTSU2_CTSUCHTRCB_CHTRC33_Msk    (0x2UL)      /*!< CHTRC33 (Bitfield-Mask: 0x01)                         */
36353  #define R_CTSU2_CTSUCHTRCB_CHTRC34_Pos    (2UL)        /*!< CHTRC34 (Bit 2)                                       */
36354  #define R_CTSU2_CTSUCHTRCB_CHTRC34_Msk    (0x4UL)      /*!< CHTRC34 (Bitfield-Mask: 0x01)                         */
36355  #define R_CTSU2_CTSUCHTRCB_CHTRC35_Pos    (3UL)        /*!< CHTRC35 (Bit 3)                                       */
36356  #define R_CTSU2_CTSUCHTRCB_CHTRC35_Msk    (0x8UL)      /*!< CHTRC35 (Bitfield-Mask: 0x01)                         */
36357 /* ======================================================  CTSUCHTRCBL  ====================================================== */
36358 /* ======================================================  CTSUCHTRC4  ======================================================= */
36359 /* ========================================================  CTSUSR  ========================================================= */
36360  #define R_CTSU2_CTSUSR_MFC_Pos            (0UL)        /*!< MFC (Bit 0)                                           */
36361  #define R_CTSU2_CTSUSR_MFC_Msk            (0x3UL)      /*!< MFC (Bitfield-Mask: 0x03)                             */
36362  #define R_CTSU2_CTSUSR_ICOMPRST_Pos       (5UL)        /*!< ICOMPRST (Bit 5)                                      */
36363  #define R_CTSU2_CTSUSR_ICOMPRST_Msk       (0x20UL)     /*!< ICOMPRST (Bitfield-Mask: 0x01)                        */
36364  #define R_CTSU2_CTSUSR_ICOMP1_Pos         (6UL)        /*!< ICOMP1 (Bit 6)                                        */
36365  #define R_CTSU2_CTSUSR_ICOMP1_Msk         (0x40UL)     /*!< ICOMP1 (Bitfield-Mask: 0x01)                          */
36366  #define R_CTSU2_CTSUSR_ICOMP0_Pos         (7UL)        /*!< ICOMP0 (Bit 7)                                        */
36367  #define R_CTSU2_CTSUSR_ICOMP0_Msk         (0x80UL)     /*!< ICOMP0 (Bitfield-Mask: 0x01)                          */
36368  #define R_CTSU2_CTSUSR_STC_Pos            (8UL)        /*!< STC (Bit 8)                                           */
36369  #define R_CTSU2_CTSUSR_STC_Msk            (0x700UL)    /*!< STC (Bitfield-Mask: 0x07)                             */
36370  #define R_CTSU2_CTSUSR_DTSR_Pos           (12UL)       /*!< DTSR (Bit 12)                                         */
36371  #define R_CTSU2_CTSUSR_DTSR_Msk           (0x1000UL)   /*!< DTSR (Bitfield-Mask: 0x01)                            */
36372  #define R_CTSU2_CTSUSR_SENSOVF_Pos        (13UL)       /*!< SENSOVF (Bit 13)                                      */
36373  #define R_CTSU2_CTSUSR_SENSOVF_Msk        (0x2000UL)   /*!< SENSOVF (Bitfield-Mask: 0x01)                         */
36374  #define R_CTSU2_CTSUSR_SUOVF_Pos          (14UL)       /*!< SUOVF (Bit 14)                                        */
36375  #define R_CTSU2_CTSUSR_SUOVF_Msk          (0x4000UL)   /*!< SUOVF (Bitfield-Mask: 0x01)                           */
36376  #define R_CTSU2_CTSUSR_PS_Pos             (15UL)       /*!< PS (Bit 15)                                           */
36377  #define R_CTSU2_CTSUSR_PS_Msk             (0x8000UL)   /*!< PS (Bitfield-Mask: 0x01)                              */
36378  #define R_CTSU2_CTSUSR_CFCRDCH_Pos        (16UL)       /*!< CFCRDCH (Bit 16)                                      */
36379  #define R_CTSU2_CTSUSR_CFCRDCH_Msk        (0x3f0000UL) /*!< CFCRDCH (Bitfield-Mask: 0x3f)                         */
36380 /* ========================================================  CTSUSRL  ======================================================== */
36381 /* ========================================================  CTSUSR0  ======================================================== */
36382 /* ========================================================  CTSUST  ========================================================= */
36383 /* ========================================================  CTSUSRH  ======================================================== */
36384 /* ========================================================  CTSUSR2  ======================================================== */
36385 /* ========================================================  CTSUSO  ========================================================= */
36386  #define R_CTSU2_CTSUSO_SO_Pos              (0UL)          /*!< SO (Bit 0)                                            */
36387  #define R_CTSU2_CTSUSO_SO_Msk              (0x3ffUL)      /*!< SO (Bitfield-Mask: 0x3ff)                             */
36388  #define R_CTSU2_CTSUSO_SNUM_Pos            (10UL)         /*!< SNUM (Bit 10)                                         */
36389  #define R_CTSU2_CTSUSO_SNUM_Msk            (0x3fc00UL)    /*!< SNUM (Bitfield-Mask: 0xff)                            */
36390  #define R_CTSU2_CTSUSO_SSDIV_Pos           (20UL)         /*!< SSDIV (Bit 20)                                        */
36391  #define R_CTSU2_CTSUSO_SSDIV_Msk           (0xf00000UL)   /*!< SSDIV (Bitfield-Mask: 0x0f)                           */
36392  #define R_CTSU2_CTSUSO_SDPA_Pos            (24UL)         /*!< SDPA (Bit 24)                                         */
36393  #define R_CTSU2_CTSUSO_SDPA_Msk            (0xff000000UL) /*!< SDPA (Bitfield-Mask: 0xff)                            */
36394 /* ========================================================  CTSUSO0  ======================================================== */
36395 /* ========================================================  CTSUSO1  ======================================================== */
36396 /* =======================================================  CTSUSCNT  ======================================================== */
36397  #define R_CTSU2_CTSUSCNT_SENSCNT_Pos       (0UL)          /*!< SENSCNT (Bit 0)                                       */
36398  #define R_CTSU2_CTSUSCNT_SENSCNT_Msk       (0xffffUL)     /*!< SENSCNT (Bitfield-Mask: 0xffff)                       */
36399  #define R_CTSU2_CTSUSCNT_SUCKCNT_Pos       (16UL)         /*!< SUCKCNT (Bit 16)                                      */
36400  #define R_CTSU2_CTSUSCNT_SUCKCNT_Msk       (0xffff0000UL) /*!< SUCKCNT (Bitfield-Mask: 0xffff)                       */
36401 /* ========================================================  CTSUSC  ========================================================= */
36402 /* =======================================================  CTSUCALIB  ======================================================= */
36403  #define R_CTSU2_CTSUCALIB_TSOD_Pos         (2UL)          /*!< TSOD (Bit 2)                                          */
36404  #define R_CTSU2_CTSUCALIB_TSOD_Msk         (0x4UL)        /*!< TSOD (Bitfield-Mask: 0x01)                            */
36405  #define R_CTSU2_CTSUCALIB_DRV_Pos          (3UL)          /*!< DRV (Bit 3)                                           */
36406  #define R_CTSU2_CTSUCALIB_DRV_Msk          (0x8UL)        /*!< DRV (Bitfield-Mask: 0x01)                             */
36407  #define R_CTSU2_CTSUCALIB_CLKSEL_Pos       (4UL)          /*!< CLKSEL (Bit 4)                                        */
36408  #define R_CTSU2_CTSUCALIB_CLKSEL_Msk       (0x30UL)       /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
36409  #define R_CTSU2_CTSUCALIB_SUCLKEN_Pos      (6UL)          /*!< SUCLKEN (Bit 6)                                       */
36410  #define R_CTSU2_CTSUCALIB_SUCLKEN_Msk      (0x40UL)       /*!< SUCLKEN (Bitfield-Mask: 0x01)                         */
36411  #define R_CTSU2_CTSUCALIB_TSOC_Pos         (7UL)          /*!< TSOC (Bit 7)                                          */
36412  #define R_CTSU2_CTSUCALIB_TSOC_Msk         (0x80UL)       /*!< TSOC (Bitfield-Mask: 0x01)                            */
36413  #define R_CTSU2_CTSUCALIB_CNTRDSEL_Pos     (8UL)          /*!< CNTRDSEL (Bit 8)                                      */
36414  #define R_CTSU2_CTSUCALIB_CNTRDSEL_Msk     (0x100UL)      /*!< CNTRDSEL (Bitfield-Mask: 0x01)                        */
36415  #define R_CTSU2_CTSUCALIB_IOC_Pos          (9UL)          /*!< IOC (Bit 9)                                           */
36416  #define R_CTSU2_CTSUCALIB_IOC_Msk          (0x200UL)      /*!< IOC (Bitfield-Mask: 0x01)                             */
36417  #define R_CTSU2_CTSUCALIB_CFCRDMD_Pos      (10UL)         /*!< CFCRDMD (Bit 10)                                      */
36418  #define R_CTSU2_CTSUCALIB_CFCRDMD_Msk      (0x400UL)      /*!< CFCRDMD (Bitfield-Mask: 0x01)                         */
36419  #define R_CTSU2_CTSUCALIB_DCOFF_Pos        (11UL)         /*!< DCOFF (Bit 11)                                        */
36420  #define R_CTSU2_CTSUCALIB_DCOFF_Msk        (0x800UL)      /*!< DCOFF (Bitfield-Mask: 0x01)                           */
36421  #define R_CTSU2_CTSUCALIB_CFCSEL_Pos       (16UL)         /*!< CFCSEL (Bit 16)                                       */
36422  #define R_CTSU2_CTSUCALIB_CFCSEL_Msk       (0x3f0000UL)   /*!< CFCSEL (Bitfield-Mask: 0x3f)                          */
36423  #define R_CTSU2_CTSUCALIB_CFCMODE_Pos      (22UL)         /*!< CFCMODE (Bit 22)                                      */
36424  #define R_CTSU2_CTSUCALIB_CFCMODE_Msk      (0x400000UL)   /*!< CFCMODE (Bitfield-Mask: 0x01)                         */
36425  #define R_CTSU2_CTSUCALIB_DACMSEL_Pos      (24UL)         /*!< DACMSEL (Bit 24)                                      */
36426  #define R_CTSU2_CTSUCALIB_DACMSEL_Msk      (0x1000000UL)  /*!< DACMSEL (Bitfield-Mask: 0x01)                         */
36427  #define R_CTSU2_CTSUCALIB_DACCARRY_Pos     (25UL)         /*!< DACCARRY (Bit 25)                                     */
36428  #define R_CTSU2_CTSUCALIB_DACCARRY_Msk     (0x2000000UL)  /*!< DACCARRY (Bitfield-Mask: 0x01)                        */
36429  #define R_CTSU2_CTSUCALIB_SUMSEL_Pos       (26UL)         /*!< SUMSEL (Bit 26)                                       */
36430  #define R_CTSU2_CTSUCALIB_SUMSEL_Msk       (0x4000000UL)  /*!< SUMSEL (Bitfield-Mask: 0x01)                          */
36431  #define R_CTSU2_CTSUCALIB_SUCARRY_Pos      (27UL)         /*!< SUCARRY (Bit 27)                                      */
36432  #define R_CTSU2_CTSUCALIB_SUCARRY_Msk      (0x8000000UL)  /*!< SUCARRY (Bitfield-Mask: 0x01)                         */
36433  #define R_CTSU2_CTSUCALIB_DACCLK_Pos       (28UL)         /*!< DACCLK (Bit 28)                                       */
36434  #define R_CTSU2_CTSUCALIB_DACCLK_Msk       (0x10000000UL) /*!< DACCLK (Bitfield-Mask: 0x01)                          */
36435  #define R_CTSU2_CTSUCALIB_CCOCLK_Pos       (29UL)         /*!< CCOCLK (Bit 29)                                       */
36436  #define R_CTSU2_CTSUCALIB_CCOCLK_Msk       (0x20000000UL) /*!< CCOCLK (Bitfield-Mask: 0x01)                          */
36437  #define R_CTSU2_CTSUCALIB_CCOCALIB_Pos     (30UL)         /*!< CCOCALIB (Bit 30)                                     */
36438  #define R_CTSU2_CTSUCALIB_CCOCALIB_Msk     (0x40000000UL) /*!< CCOCALIB (Bitfield-Mask: 0x01)                        */
36439  #define R_CTSU2_CTSUCALIB_TXREV_Pos        (31UL)         /*!< TXREV (Bit 31)                                        */
36440  #define R_CTSU2_CTSUCALIB_TXREV_Msk        (0x80000000UL) /*!< TXREV (Bitfield-Mask: 0x01)                           */
36441 /* =======================================================  CTSUDBGR0  ======================================================= */
36442 /* =======================================================  CTSUDBGR1  ======================================================= */
36443 /* ======================================================  CTSUSUCLKA  ======================================================= */
36444  #define R_CTSU2_CTSUSUCLKA_SUADJ0_Pos      (0UL)          /*!< SUADJ0 (Bit 0)                                        */
36445  #define R_CTSU2_CTSUSUCLKA_SUADJ0_Msk      (0xffUL)       /*!< SUADJ0 (Bitfield-Mask: 0xff)                          */
36446  #define R_CTSU2_CTSUSUCLKA_SUMULTI0_Pos    (8UL)          /*!< SUMULTI0 (Bit 8)                                      */
36447  #define R_CTSU2_CTSUSUCLKA_SUMULTI0_Msk    (0xff00UL)     /*!< SUMULTI0 (Bitfield-Mask: 0xff)                        */
36448  #define R_CTSU2_CTSUSUCLKA_SUADJ1_Pos      (16UL)         /*!< SUADJ1 (Bit 16)                                       */
36449  #define R_CTSU2_CTSUSUCLKA_SUADJ1_Msk      (0xff0000UL)   /*!< SUADJ1 (Bitfield-Mask: 0xff)                          */
36450  #define R_CTSU2_CTSUSUCLKA_SUMULTI1_Pos    (24UL)         /*!< SUMULTI1 (Bit 24)                                     */
36451  #define R_CTSU2_CTSUSUCLKA_SUMULTI1_Msk    (0xff000000UL) /*!< SUMULTI1 (Bitfield-Mask: 0xff)                        */
36452 /* ======================================================  CTSUSUCLK0  ======================================================= */
36453 /* ======================================================  CTSUSUCLK1  ======================================================= */
36454 /* ======================================================  CTSUSUCLKB  ======================================================= */
36455  #define R_CTSU2_CTSUSUCLKB_SUADJ2_Pos      (0UL)          /*!< SUADJ2 (Bit 0)                                        */
36456  #define R_CTSU2_CTSUSUCLKB_SUADJ2_Msk      (0xffUL)       /*!< SUADJ2 (Bitfield-Mask: 0xff)                          */
36457  #define R_CTSU2_CTSUSUCLKB_SUMULTI2_Pos    (8UL)          /*!< SUMULTI2 (Bit 8)                                      */
36458  #define R_CTSU2_CTSUSUCLKB_SUMULTI2_Msk    (0xff00UL)     /*!< SUMULTI2 (Bitfield-Mask: 0xff)                        */
36459  #define R_CTSU2_CTSUSUCLKB_SUADJ3_Pos      (16UL)         /*!< SUADJ3 (Bit 16)                                       */
36460  #define R_CTSU2_CTSUSUCLKB_SUADJ3_Msk      (0xff0000UL)   /*!< SUADJ3 (Bitfield-Mask: 0xff)                          */
36461  #define R_CTSU2_CTSUSUCLKB_SUMULTI3_Pos    (24UL)         /*!< SUMULTI3 (Bit 24)                                     */
36462  #define R_CTSU2_CTSUSUCLKB_SUMULTI3_Msk    (0xff000000UL) /*!< SUMULTI3 (Bitfield-Mask: 0xff)                        */
36463 /* ======================================================  CTSUSUCLK2  ======================================================= */
36464 /* ======================================================  CTSUSUCLK3  ======================================================= */
36465 /* ======================================================  CTSUCFCCNT  ======================================================= */
36466  #define R_CTSU2_CTSUCFCCNT_CFCCNT_Pos      (0UL)          /*!< CFCCNT (Bit 0)                                        */
36467  #define R_CTSU2_CTSUCFCCNT_CFCCNT_Msk      (0xffffUL)     /*!< CFCCNT (Bitfield-Mask: 0xffff)                        */
36468 /* ======================================================  CTSUCFCCNTL  ====================================================== */
36469 
36470 /* =========================================================================================================================== */
36471 /* ================                                           R_DAC                                           ================ */
36472 /* =========================================================================================================================== */
36473 
36474 /* =========================================================  DACR  ========================================================== */
36475  #define R_DAC_DACR_DAE_Pos            (5UL)      /*!< DAE (Bit 5)                                           */
36476  #define R_DAC_DACR_DAE_Msk            (0x20UL)   /*!< DAE (Bitfield-Mask: 0x01)                             */
36477  #define R_DAC_DACR_DAOE_Pos           (6UL)      /*!< DAOE (Bit 6)                                          */
36478  #define R_DAC_DACR_DAOE_Msk           (0x40UL)   /*!< DAOE (Bitfield-Mask: 0x01)                            */
36479 /* =========================================================  DADR  ========================================================== */
36480  #define R_DAC_DADR_DADR_Pos           (0UL)      /*!< DADR (Bit 0)                                          */
36481  #define R_DAC_DADR_DADR_Msk           (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff)                          */
36482 /* =========================================================  DADPR  ========================================================= */
36483  #define R_DAC_DADPR_DPSEL_Pos         (7UL)      /*!< DPSEL (Bit 7)                                         */
36484  #define R_DAC_DADPR_DPSEL_Msk         (0x80UL)   /*!< DPSEL (Bitfield-Mask: 0x01)                           */
36485 /* ========================================================  DAADSCR  ======================================================== */
36486  #define R_DAC_DAADSCR_DAADST_Pos      (7UL)      /*!< DAADST (Bit 7)                                        */
36487  #define R_DAC_DAADSCR_DAADST_Msk      (0x80UL)   /*!< DAADST (Bitfield-Mask: 0x01)                          */
36488 /* =======================================================  DAVREFCR  ======================================================== */
36489  #define R_DAC_DAVREFCR_REF_Pos        (0UL)      /*!< REF (Bit 0)                                           */
36490  #define R_DAC_DAVREFCR_REF_Msk        (0x7UL)    /*!< REF (Bitfield-Mask: 0x07)                             */
36491 /* =========================================================  DAPC  ========================================================== */
36492  #define R_DAC_DAPC_PUMPEN_Pos         (0UL)      /*!< PUMPEN (Bit 0)                                        */
36493  #define R_DAC_DAPC_PUMPEN_Msk         (0x1UL)    /*!< PUMPEN (Bitfield-Mask: 0x01)                          */
36494 /* ========================================================  DAAMPCR  ======================================================== */
36495  #define R_DAC_DAAMPCR_DAAMP_Pos       (6UL)      /*!< DAAMP (Bit 6)                                         */
36496  #define R_DAC_DAAMPCR_DAAMP_Msk       (0x40UL)   /*!< DAAMP (Bitfield-Mask: 0x01)                           */
36497 /* ========================================================  DAASWCR  ======================================================== */
36498  #define R_DAC_DAASWCR_DAASW1_Pos      (7UL)      /*!< DAASW1 (Bit 7)                                        */
36499  #define R_DAC_DAASWCR_DAASW1_Msk      (0x80UL)   /*!< DAASW1 (Bitfield-Mask: 0x01)                          */
36500  #define R_DAC_DAASWCR_DAASW0_Pos      (6UL)      /*!< DAASW0 (Bit 6)                                        */
36501  #define R_DAC_DAASWCR_DAASW0_Msk      (0x40UL)   /*!< DAASW0 (Bitfield-Mask: 0x01)                          */
36502 /* ========================================================  DAADUSR  ======================================================== */
36503  #define R_DAC_DAADUSR_AMADSEL1_Pos    (6UL)      /*!< AMADSEL1 (Bit 6)                                      */
36504  #define R_DAC_DAADUSR_AMADSEL1_Msk    (0x40UL)   /*!< AMADSEL1 (Bitfield-Mask: 0x01)                        */
36505 
36506 /* =========================================================================================================================== */
36507 /* ================                                          R_DAC8                                           ================ */
36508 /* =========================================================================================================================== */
36509 
36510 /* ==========================================================  DAM  ========================================================== */
36511  #define R_DAC8_DAM_DACE1_Pos           (5UL)    /*!< DACE1 (Bit 5)                                         */
36512  #define R_DAC8_DAM_DACE1_Msk           (0x20UL) /*!< DACE1 (Bitfield-Mask: 0x01)                           */
36513  #define R_DAC8_DAM_DACE0_Pos           (4UL)    /*!< DACE0 (Bit 4)                                         */
36514  #define R_DAC8_DAM_DACE0_Msk           (0x10UL) /*!< DACE0 (Bitfield-Mask: 0x01)                           */
36515  #define R_DAC8_DAM_DAMD1_Pos           (1UL)    /*!< DAMD1 (Bit 1)                                         */
36516  #define R_DAC8_DAM_DAMD1_Msk           (0x2UL)  /*!< DAMD1 (Bitfield-Mask: 0x01)                           */
36517  #define R_DAC8_DAM_DAMD0_Pos           (0UL)    /*!< DAMD0 (Bit 0)                                         */
36518  #define R_DAC8_DAM_DAMD0_Msk           (0x1UL)  /*!< DAMD0 (Bitfield-Mask: 0x01)                           */
36519 /* =========================================================  DACS  ========================================================== */
36520  #define R_DAC8_DACS_DACS_Pos           (0UL)    /*!< DACS (Bit 0)                                          */
36521  #define R_DAC8_DACS_DACS_Msk           (0xffUL) /*!< DACS (Bitfield-Mask: 0xff)                            */
36522 /* =======================================================  DACADSCR  ======================================================== */
36523  #define R_DAC8_DACADSCR_DACADST_Pos    (0UL)    /*!< DACADST (Bit 0)                                       */
36524  #define R_DAC8_DACADSCR_DACADST_Msk    (0x1UL)  /*!< DACADST (Bitfield-Mask: 0x01)                         */
36525 /* =========================================================  DACPC  ========================================================= */
36526  #define R_DAC8_DACPC_PUMPEN_Pos        (0UL)    /*!< PUMPEN (Bit 0)                                        */
36527  #define R_DAC8_DACPC_PUMPEN_Msk        (0x1UL)  /*!< PUMPEN (Bitfield-Mask: 0x01)                          */
36528 
36529 /* =========================================================================================================================== */
36530 /* ================                                          R_DALI0                                          ================ */
36531 /* =========================================================================================================================== */
36532 
36533 /* ========================================================  BTVTHR1  ======================================================== */
36534  #define R_DALI0_BTVTHR1_BTV2_Pos     (8UL)      /*!< BTV2 (Bit 8)                                          */
36535  #define R_DALI0_BTVTHR1_BTV2_Msk     (0xff00UL) /*!< BTV2 (Bitfield-Mask: 0xff)                            */
36536  #define R_DALI0_BTVTHR1_BTV1_Pos     (0UL)      /*!< BTV1 (Bit 0)                                          */
36537  #define R_DALI0_BTVTHR1_BTV1_Msk     (0x7fUL)   /*!< BTV1 (Bitfield-Mask: 0x7f)                            */
36538 /* ========================================================  BTVTHR2  ======================================================== */
36539  #define R_DALI0_BTVTHR2_BTV4_Pos     (8UL)      /*!< BTV4 (Bit 8)                                          */
36540  #define R_DALI0_BTVTHR2_BTV4_Msk     (0xff00UL) /*!< BTV4 (Bitfield-Mask: 0xff)                            */
36541  #define R_DALI0_BTVTHR2_BTV3_Pos     (0UL)      /*!< BTV3 (Bit 0)                                          */
36542  #define R_DALI0_BTVTHR2_BTV3_Msk     (0xffUL)   /*!< BTV3 (Bitfield-Mask: 0xff)                            */
36543 /* ========================================================  BTVTHR3  ======================================================== */
36544  #define R_DALI0_BTVTHR3_BTV5_Pos     (0UL)      /*!< BTV5 (Bit 0)                                          */
36545  #define R_DALI0_BTVTHR3_BTV5_Msk     (0xffUL)   /*!< BTV5 (Bitfield-Mask: 0xff)                            */
36546 /* ========================================================  BTVTHR4  ======================================================== */
36547  #define R_DALI0_BTVTHR4_BTV6_Pos     (0UL)      /*!< BTV6 (Bit 0)                                          */
36548  #define R_DALI0_BTVTHR4_BTV6_Msk     (0x1ffUL)  /*!< BTV6 (Bitfield-Mask: 0x1ff)                           */
36549 /* ========================================================  COLTHR1  ======================================================== */
36550  #define R_DALI0_COLTHR1_COL2_Pos     (8UL)      /*!< COL2 (Bit 8)                                          */
36551  #define R_DALI0_COLTHR1_COL2_Msk     (0x3f00UL) /*!< COL2 (Bitfield-Mask: 0x3f)                            */
36552  #define R_DALI0_COLTHR1_COL1_Pos     (0UL)      /*!< COL1 (Bit 0)                                          */
36553  #define R_DALI0_COLTHR1_COL1_Msk     (0x3fUL)   /*!< COL1 (Bitfield-Mask: 0x3f)                            */
36554 /* ========================================================  COLTHR2  ======================================================== */
36555  #define R_DALI0_COLTHR2_COL4_Pos     (8UL)      /*!< COL4 (Bit 8)                                          */
36556  #define R_DALI0_COLTHR2_COL4_Msk     (0x7f00UL) /*!< COL4 (Bitfield-Mask: 0x7f)                            */
36557  #define R_DALI0_COLTHR2_COL3_Pos     (0UL)      /*!< COL3 (Bit 0)                                          */
36558  #define R_DALI0_COLTHR2_COL3_Msk     (0x7fUL)   /*!< COL3 (Bitfield-Mask: 0x7f)                            */
36559 /* ========================================================  COLTHR3  ======================================================== */
36560  #define R_DALI0_COLTHR3_COL6_Pos     (8UL)      /*!< COL6 (Bit 8)                                          */
36561  #define R_DALI0_COLTHR3_COL6_Msk     (0x7f00UL) /*!< COL6 (Bitfield-Mask: 0x7f)                            */
36562  #define R_DALI0_COLTHR3_COL5_Pos     (0UL)      /*!< COL5 (Bit 0)                                          */
36563  #define R_DALI0_COLTHR3_COL5_Msk     (0x7fUL)   /*!< COL5 (Bitfield-Mask: 0x7f)                            */
36564 /* ========================================================  COLTHR4  ======================================================== */
36565  #define R_DALI0_COLTHR4_COL8_Pos     (8UL)      /*!< COL8 (Bit 8)                                          */
36566  #define R_DALI0_COLTHR4_COL8_Msk     (0xff00UL) /*!< COL8 (Bitfield-Mask: 0xff)                            */
36567  #define R_DALI0_COLTHR4_COL7_Pos     (0UL)      /*!< COL7 (Bit 0)                                          */
36568  #define R_DALI0_COLTHR4_COL7_Msk     (0xffUL)   /*!< COL7 (Bitfield-Mask: 0xff)                            */
36569 /* ========================================================  COLTHR5  ======================================================== */
36570  #define R_DALI0_COLTHR5_COL9_Pos     (0UL)      /*!< COL9 (Bit 0)                                          */
36571  #define R_DALI0_COLTHR5_COL9_Msk     (0xffUL)   /*!< COL9 (Bitfield-Mask: 0xff)                            */
36572 /* =========================================================  CNFR1  ========================================================= */
36573  #define R_DALI0_CNFR1_CHL_Pos        (12UL)     /*!< CHL (Bit 12)                                          */
36574  #define R_DALI0_CNFR1_CHL_Msk        (0x7000UL) /*!< CHL (Bitfield-Mask: 0x07)                             */
36575  #define R_DALI0_CNFR1_CKS_Pos        (8UL)      /*!< CKS (Bit 8)                                           */
36576  #define R_DALI0_CNFR1_CKS_Msk        (0x300UL)  /*!< CKS (Bitfield-Mask: 0x03)                             */
36577  #define R_DALI0_CNFR1_BR_Pos         (0UL)      /*!< BR (Bit 0)                                            */
36578  #define R_DALI0_CNFR1_BR_Msk         (0xffUL)   /*!< BR (Bitfield-Mask: 0xff)                              */
36579 /* =========================================================  CNFR2  ========================================================= */
36580  #define R_DALI0_CNFR2_CDM0_Pos       (5UL)      /*!< CDM0 (Bit 5)                                          */
36581  #define R_DALI0_CNFR2_CDM0_Msk       (0x20UL)   /*!< CDM0 (Bitfield-Mask: 0x01)                            */
36582  #define R_DALI0_CNFR2_CDE_Pos        (4UL)      /*!< CDE (Bit 4)                                           */
36583  #define R_DALI0_CNFR2_CDE_Msk        (0x10UL)   /*!< CDE (Bitfield-Mask: 0x01)                             */
36584  #define R_DALI0_CNFR2_TXWE_Pos       (3UL)      /*!< TXWE (Bit 3)                                          */
36585  #define R_DALI0_CNFR2_TXWE_Msk       (0x8UL)    /*!< TXWE (Bitfield-Mask: 0x01)                            */
36586  #define R_DALI0_CNFR2_SGA_Pos        (2UL)      /*!< SGA (Bit 2)                                           */
36587  #define R_DALI0_CNFR2_SGA_Msk        (0x4UL)    /*!< SGA (Bitfield-Mask: 0x01)                             */
36588  #define R_DALI0_CNFR2_BTVM_Pos       (1UL)      /*!< BTVM (Bit 1)                                          */
36589  #define R_DALI0_CNFR2_BTVM_Msk       (0x2UL)    /*!< BTVM (Bitfield-Mask: 0x01)                            */
36590  #define R_DALI0_CNFR2_BTVE_Pos       (0UL)      /*!< BTVE (Bit 0)                                          */
36591  #define R_DALI0_CNFR2_BTVE_Msk       (0x1UL)    /*!< BTVE (Bitfield-Mask: 0x01)                            */
36592 /* =========================================================  TXWR1  ========================================================= */
36593  #define R_DALI0_TXWR1_TXLW_Pos       (0UL)      /*!< TXLW (Bit 0)                                          */
36594  #define R_DALI0_TXWR1_TXLW_Msk       (0x7fUL)   /*!< TXLW (Bitfield-Mask: 0x7f)                            */
36595 /* =========================================================  TDR1H  ========================================================= */
36596  #define R_DALI0_TDR1H_DTDR_Pos       (0UL)      /*!< DTDR (Bit 0)                                          */
36597  #define R_DALI0_TDR1H_DTDR_Msk       (0xffffUL) /*!< DTDR (Bitfield-Mask: 0xffff)                          */
36598 /* =========================================================  TDR1L  ========================================================= */
36599  #define R_DALI0_TDR1L_DTDR_Pos       (0UL)      /*!< DTDR (Bit 0)                                          */
36600  #define R_DALI0_TDR1L_DTDR_Msk       (0xffffUL) /*!< DTDR (Bitfield-Mask: 0xffff)                          */
36601 /* ========================================================  TRSTR1  ========================================================= */
36602  #define R_DALI0_TRSTR1_TRST_Pos      (0UL)      /*!< TRST (Bit 0)                                          */
36603  #define R_DALI0_TRSTR1_TRST_Msk      (0x1UL)    /*!< TRST (Bitfield-Mask: 0x01)                            */
36604 /* =========================================================  CTR1  ========================================================== */
36605  #define R_DALI0_CTR1_FEIE_Pos        (12UL)     /*!< FEIE (Bit 12)                                         */
36606  #define R_DALI0_CTR1_FEIE_Msk        (0x1000UL) /*!< FEIE (Bitfield-Mask: 0x01)                            */
36607  #define R_DALI0_CTR1_BPIE_Pos        (11UL)     /*!< BPIE (Bit 11)                                         */
36608  #define R_DALI0_CTR1_BPIE_Msk        (0x800UL)  /*!< BPIE (Bitfield-Mask: 0x01)                            */
36609  #define R_DALI0_CTR1_CLIE_Pos        (10UL)     /*!< CLIE (Bit 10)                                         */
36610  #define R_DALI0_CTR1_CLIE_Msk        (0x400UL)  /*!< CLIE (Bitfield-Mask: 0x01)                            */
36611  #define R_DALI0_CTR1_DEIE_Pos        (9UL)      /*!< DEIE (Bit 9)                                          */
36612  #define R_DALI0_CTR1_DEIE_Msk        (0x200UL)  /*!< DEIE (Bitfield-Mask: 0x01)                            */
36613  #define R_DALI0_CTR1_SDIE_Pos        (8UL)      /*!< SDIE (Bit 8)                                          */
36614  #define R_DALI0_CTR1_SDIE_Msk        (0x100UL)  /*!< SDIE (Bitfield-Mask: 0x01)                            */
36615  #define R_DALI0_CTR1_RE_Pos          (1UL)      /*!< RE (Bit 1)                                            */
36616  #define R_DALI0_CTR1_RE_Msk          (0x2UL)    /*!< RE (Bitfield-Mask: 0x01)                              */
36617  #define R_DALI0_CTR1_TE_Pos          (0UL)      /*!< TE (Bit 0)                                            */
36618  #define R_DALI0_CTR1_TE_Msk          (0x1UL)    /*!< TE (Bitfield-Mask: 0x01)                              */
36619 /* ========================================================  TXDCTR1  ======================================================== */
36620  #define R_DALI0_TXDCTR1_TXASE_Pos    (1UL)      /*!< TXASE (Bit 1)                                         */
36621  #define R_DALI0_TXDCTR1_TXASE_Msk    (0x2UL)    /*!< TXASE (Bitfield-Mask: 0x01)                           */
36622  #define R_DALI0_TXDCTR1_TXAS_Pos     (0UL)      /*!< TXAS (Bit 0)                                          */
36623  #define R_DALI0_TXDCTR1_TXAS_Msk     (0x1UL)    /*!< TXAS (Bitfield-Mask: 0x01)                            */
36624 /* =========================================================  RDR1H  ========================================================= */
36625  #define R_DALI0_RDR1H_DRDR_Pos       (0UL)      /*!< DRDR (Bit 0)                                          */
36626  #define R_DALI0_RDR1H_DRDR_Msk       (0xffffUL) /*!< DRDR (Bitfield-Mask: 0xffff)                          */
36627 /* =========================================================  RDR1L  ========================================================= */
36628  #define R_DALI0_RDR1L_DRDR_Pos       (0UL)      /*!< DRDR (Bit 0)                                          */
36629  #define R_DALI0_RDR1L_DRDR_Msk       (0xffffUL) /*!< DRDR (Bitfield-Mask: 0xffff)                          */
36630 /* =========================================================  STR1  ========================================================== */
36631  #define R_DALI0_STR1_RDBL_Pos        (10UL)     /*!< RDBL (Bit 10)                                         */
36632  #define R_DALI0_STR1_RDBL_Msk        (0xfc00UL) /*!< RDBL (Bitfield-Mask: 0x3f)                            */
36633  #define R_DALI0_STR1_DAF_Pos         (9UL)      /*!< DAF (Bit 9)                                           */
36634  #define R_DALI0_STR1_DAF_Msk         (0x200UL)  /*!< DAF (Bitfield-Mask: 0x01)                             */
36635  #define R_DALI0_STR1_CDF_Pos         (8UL)      /*!< CDF (Bit 8)                                           */
36636  #define R_DALI0_STR1_CDF_Msk         (0x100UL)  /*!< CDF (Bitfield-Mask: 0x01)                             */
36637  #define R_DALI0_STR1_O32F_Pos        (7UL)      /*!< O32F (Bit 7)                                          */
36638  #define R_DALI0_STR1_O32F_Msk        (0x80UL)   /*!< O32F (Bitfield-Mask: 0x01)                            */
36639  #define R_DALI0_STR1_BPDF_Pos        (6UL)      /*!< BPDF (Bit 6)                                          */
36640  #define R_DALI0_STR1_BPDF_Msk        (0x40UL)   /*!< BPDF (Bitfield-Mask: 0x01)                            */
36641  #define R_DALI0_STR1_BBF_Pos         (5UL)      /*!< BBF (Bit 5)                                           */
36642  #define R_DALI0_STR1_BBF_Msk         (0x20UL)   /*!< BBF (Bitfield-Mask: 0x01)                             */
36643  #define R_DALI0_STR1_TENDF_Pos       (4UL)      /*!< TENDF (Bit 4)                                         */
36644  #define R_DALI0_STR1_TENDF_Msk       (0x10UL)   /*!< TENDF (Bitfield-Mask: 0x01)                           */
36645  #define R_DALI0_STR1_RDRF_Pos        (3UL)      /*!< RDRF (Bit 3)                                          */
36646  #define R_DALI0_STR1_RDRF_Msk        (0x8UL)    /*!< RDRF (Bitfield-Mask: 0x01)                            */
36647  #define R_DALI0_STR1_BTVF_Pos        (2UL)      /*!< BTVF (Bit 2)                                          */
36648  #define R_DALI0_STR1_BTVF_Msk        (0x4UL)    /*!< BTVF (Bitfield-Mask: 0x01)                            */
36649  #define R_DALI0_STR1_OVF_Pos         (1UL)      /*!< OVF (Bit 1)                                           */
36650  #define R_DALI0_STR1_OVF_Msk         (0x2UL)    /*!< OVF (Bitfield-Mask: 0x01)                             */
36651  #define R_DALI0_STR1_MFEF_Pos        (0UL)      /*!< MFEF (Bit 0)                                          */
36652  #define R_DALI0_STR1_MFEF_Msk        (0x1UL)    /*!< MFEF (Bitfield-Mask: 0x01)                            */
36653 /* =========================================================  COLR1  ========================================================= */
36654  #define R_DALI0_COLR1_TXDCV_Pos      (13UL)     /*!< TXDCV (Bit 13)                                        */
36655  #define R_DALI0_COLR1_TXDCV_Msk      (0x2000UL) /*!< TXDCV (Bitfield-Mask: 0x01)                           */
36656  #define R_DALI0_COLR1_RXDCEG_Pos     (12UL)     /*!< RXDCEG (Bit 12)                                       */
36657  #define R_DALI0_COLR1_RXDCEG_Msk     (0x1000UL) /*!< RXDCEG (Bitfield-Mask: 0x01)                          */
36658  #define R_DALI0_COLR1_RXDMON_Pos     (11UL)     /*!< RXDMON (Bit 11)                                       */
36659  #define R_DALI0_COLR1_RXDMON_Msk     (0x800UL)  /*!< RXDMON (Bitfield-Mask: 0x01)                          */
36660  #define R_DALI0_COLR1_CLDAF_Pos      (10UL)     /*!< CLDAF (Bit 10)                                        */
36661  #define R_DALI0_COLR1_CLDAF_Msk      (0x400UL)  /*!< CLDAF (Bitfield-Mask: 0x01)                           */
36662  #define R_DALI0_COLR1_CDTF1_Pos      (4UL)      /*!< CDTF1 (Bit 4)                                         */
36663  #define R_DALI0_COLR1_CDTF1_Msk      (0x10UL)   /*!< CDTF1 (Bitfield-Mask: 0x01)                           */
36664  #define R_DALI0_COLR1_CFTF2_Pos      (0UL)      /*!< CFTF2 (Bit 0)                                         */
36665  #define R_DALI0_COLR1_CFTF2_Msk      (0xfUL)    /*!< CFTF2 (Bitfield-Mask: 0x0f)                           */
36666 /* =========================================================  FECR1  ========================================================= */
36667  #define R_DALI0_FECR1_DAFC_Pos       (9UL)      /*!< DAFC (Bit 9)                                          */
36668  #define R_DALI0_FECR1_DAFC_Msk       (0x200UL)  /*!< DAFC (Bitfield-Mask: 0x01)                            */
36669  #define R_DALI0_FECR1_CDFC_Pos       (8UL)      /*!< CDFC (Bit 8)                                          */
36670  #define R_DALI0_FECR1_CDFC_Msk       (0x100UL)  /*!< CDFC (Bitfield-Mask: 0x01)                            */
36671  #define R_DALI0_FECR1_O32FC_Pos      (7UL)      /*!< O32FC (Bit 7)                                         */
36672  #define R_DALI0_FECR1_O32FC_Msk      (0x80UL)   /*!< O32FC (Bitfield-Mask: 0x01)                           */
36673  #define R_DALI0_FECR1_BPDFC_Pos      (6UL)      /*!< BPDFC (Bit 6)                                         */
36674  #define R_DALI0_FECR1_BPDFC_Msk      (0x40UL)   /*!< BPDFC (Bitfield-Mask: 0x01)                           */
36675  #define R_DALI0_FECR1_BBFC_Pos       (5UL)      /*!< BBFC (Bit 5)                                          */
36676  #define R_DALI0_FECR1_BBFC_Msk       (0x20UL)   /*!< BBFC (Bitfield-Mask: 0x01)                            */
36677  #define R_DALI0_FECR1_TENDFC_Pos     (4UL)      /*!< TENDFC (Bit 4)                                        */
36678  #define R_DALI0_FECR1_TENDFC_Msk     (0x10UL)   /*!< TENDFC (Bitfield-Mask: 0x01)                          */
36679  #define R_DALI0_FECR1_RDRFC_Pos      (3UL)      /*!< RDRFC (Bit 3)                                         */
36680  #define R_DALI0_FECR1_RDRFC_Msk      (0x8UL)    /*!< RDRFC (Bitfield-Mask: 0x01)                           */
36681  #define R_DALI0_FECR1_BTVFC_Pos      (2UL)      /*!< BTVFC (Bit 2)                                         */
36682  #define R_DALI0_FECR1_BTVFC_Msk      (0x4UL)    /*!< BTVFC (Bitfield-Mask: 0x01)                           */
36683  #define R_DALI0_FECR1_OVFC_Pos       (1UL)      /*!< OVFC (Bit 1)                                          */
36684  #define R_DALI0_FECR1_OVFC_Msk       (0x2UL)    /*!< OVFC (Bitfield-Mask: 0x01)                            */
36685  #define R_DALI0_FECR1_MFEFC_Pos      (0UL)      /*!< MFEFC (Bit 0)                                         */
36686  #define R_DALI0_FECR1_MFEFC_Msk      (0x1UL)    /*!< MFEFC (Bitfield-Mask: 0x01)                           */
36687 /* =========================================================  SWRR1  ========================================================= */
36688  #define R_DALI0_SWRR1_SWR_Pos        (0UL)      /*!< SWR (Bit 0)                                           */
36689  #define R_DALI0_SWRR1_SWR_Msk        (0x1UL)    /*!< SWR (Bitfield-Mask: 0x01)                             */
36690 
36691 /* =========================================================================================================================== */
36692 /* ================                                          R_DEBUG                                          ================ */
36693 /* =========================================================================================================================== */
36694 
36695 /* ========================================================  DBGSTR  ========================================================= */
36696  #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos        (28UL)         /*!< CDBGPWRUPREQ (Bit 28)                                 */
36697  #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk        (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01)                    */
36698  #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos        (29UL)         /*!< CDBGPWRUPACK (Bit 29)                                 */
36699  #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk        (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01)                    */
36700 /* =======================================================  DBGSTOPCR  ======================================================= */
36701  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos     (24UL)         /*!< DBGSTOP_RPER (Bit 24)                                 */
36702  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk     (0x1000000UL)  /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01)                    */
36703  #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos      (16UL)         /*!< DBGSTOP_LVD (Bit 16)                                  */
36704  #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk      (0x10000UL)    /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01)                     */
36705  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos    (25UL)         /*!< DBGSTOP_RECCR (Bit 25)                                */
36706  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk    (0x2000000UL)  /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01)                   */
36707  #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos     (0UL)          /*!< DBGSTOP_IWDT (Bit 0)                                  */
36708  #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk     (0x1UL)        /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01)                    */
36709  #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos      (1UL)          /*!< DBGSTOP_WDT (Bit 1)                                   */
36710  #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk      (0x2UL)        /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01)                     */
36711  #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos     (31UL)         /*!< DBGSTOP_CPER (Bit 31)                                 */
36712  #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk     (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01)                    */
36713 
36714 /* =========================================================================================================================== */
36715 /* ================                                           R_DMA                                           ================ */
36716 /* =========================================================================================================================== */
36717 
36718 /* =========================================================  DMAST  ========================================================= */
36719  #define R_DMA_DMAST_DMST_Pos         (0UL)       /*!< DMST (Bit 0)                                          */
36720  #define R_DMA_DMAST_DMST_Msk         (0x1UL)     /*!< DMST (Bitfield-Mask: 0x01)                            */
36721 /* ========================================================  DMECHR  ========================================================= */
36722  #define R_DMA_DMECHR_DMECH_Pos       (0UL)       /*!< DMECH (Bit 0)                                         */
36723  #define R_DMA_DMECHR_DMECH_Msk       (0x7UL)     /*!< DMECH (Bitfield-Mask: 0x07)                           */
36724  #define R_DMA_DMECHR_DMECHSAM_Pos    (8UL)       /*!< DMECHSAM (Bit 8)                                      */
36725  #define R_DMA_DMECHR_DMECHSAM_Msk    (0x100UL)   /*!< DMECHSAM (Bitfield-Mask: 0x01)                        */
36726  #define R_DMA_DMECHR_DMESTA_Pos      (16UL)      /*!< DMESTA (Bit 16)                                       */
36727  #define R_DMA_DMECHR_DMESTA_Msk      (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01)                          */
36728 
36729 /* =========================================================================================================================== */
36730 /* ================                                          R_DMAC0                                          ================ */
36731 /* =========================================================================================================================== */
36732 
36733 /* =========================================================  DMSAR  ========================================================= */
36734  #define R_DMAC0_DMSAR_DMSAR_Pos     (0UL)          /*!< DMSAR (Bit 0)                                         */
36735  #define R_DMAC0_DMSAR_DMSAR_Msk     (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff)                     */
36736 /* =========================================================  DMDAR  ========================================================= */
36737  #define R_DMAC0_DMDAR_DMDAR_Pos     (0UL)          /*!< DMDAR (Bit 0)                                         */
36738  #define R_DMAC0_DMDAR_DMDAR_Msk     (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff)                     */
36739 /* =========================================================  DMCRA  ========================================================= */
36740  #define R_DMAC0_DMCRA_DMCRAH_Pos    (16UL)         /*!< DMCRAH (Bit 16)                                       */
36741  #define R_DMAC0_DMCRA_DMCRAH_Msk    (0x3ff0000UL)  /*!< DMCRAH (Bitfield-Mask: 0x3ff)                         */
36742  #define R_DMAC0_DMCRA_DMCRAL_Pos    (0UL)          /*!< DMCRAL (Bit 0)                                        */
36743  #define R_DMAC0_DMCRA_DMCRAL_Msk    (0xffffUL)     /*!< DMCRAL (Bitfield-Mask: 0xffff)                        */
36744 /* =========================================================  DMCRB  ========================================================= */
36745  #define R_DMAC0_DMCRB_DMCRB_Pos     (0UL)          /*!< DMCRB (Bit 0)                                         */
36746  #define R_DMAC0_DMCRB_DMCRB_Msk     (0xffffUL)     /*!< DMCRB (Bitfield-Mask: 0xffff)                         */
36747 /* =========================================================  DMTMD  ========================================================= */
36748  #define R_DMAC0_DMTMD_MD_Pos        (14UL)         /*!< MD (Bit 14)                                           */
36749  #define R_DMAC0_DMTMD_MD_Msk        (0xc000UL)     /*!< MD (Bitfield-Mask: 0x03)                              */
36750  #define R_DMAC0_DMTMD_DTS_Pos       (12UL)         /*!< DTS (Bit 12)                                          */
36751  #define R_DMAC0_DMTMD_DTS_Msk       (0x3000UL)     /*!< DTS (Bitfield-Mask: 0x03)                             */
36752  #define R_DMAC0_DMTMD_SZ_Pos        (8UL)          /*!< SZ (Bit 8)                                            */
36753  #define R_DMAC0_DMTMD_SZ_Msk        (0x300UL)      /*!< SZ (Bitfield-Mask: 0x03)                              */
36754  #define R_DMAC0_DMTMD_DCTG_Pos      (0UL)          /*!< DCTG (Bit 0)                                          */
36755  #define R_DMAC0_DMTMD_DCTG_Msk      (0x3UL)        /*!< DCTG (Bitfield-Mask: 0x03)                            */
36756  #define R_DMAC0_DMTMD_TKP_Pos       (10UL)         /*!< TKP (Bit 10)                                          */
36757  #define R_DMAC0_DMTMD_TKP_Msk       (0x400UL)      /*!< TKP (Bitfield-Mask: 0x01)                             */
36758 /* =========================================================  DMINT  ========================================================= */
36759  #define R_DMAC0_DMINT_DTIE_Pos      (4UL)          /*!< DTIE (Bit 4)                                          */
36760  #define R_DMAC0_DMINT_DTIE_Msk      (0x10UL)       /*!< DTIE (Bitfield-Mask: 0x01)                            */
36761  #define R_DMAC0_DMINT_ESIE_Pos      (3UL)          /*!< ESIE (Bit 3)                                          */
36762  #define R_DMAC0_DMINT_ESIE_Msk      (0x8UL)        /*!< ESIE (Bitfield-Mask: 0x01)                            */
36763  #define R_DMAC0_DMINT_RPTIE_Pos     (2UL)          /*!< RPTIE (Bit 2)                                         */
36764  #define R_DMAC0_DMINT_RPTIE_Msk     (0x4UL)        /*!< RPTIE (Bitfield-Mask: 0x01)                           */
36765  #define R_DMAC0_DMINT_SARIE_Pos     (1UL)          /*!< SARIE (Bit 1)                                         */
36766  #define R_DMAC0_DMINT_SARIE_Msk     (0x2UL)        /*!< SARIE (Bitfield-Mask: 0x01)                           */
36767  #define R_DMAC0_DMINT_DARIE_Pos     (0UL)          /*!< DARIE (Bit 0)                                         */
36768  #define R_DMAC0_DMINT_DARIE_Msk     (0x1UL)        /*!< DARIE (Bitfield-Mask: 0x01)                           */
36769 /* =========================================================  DMAMD  ========================================================= */
36770  #define R_DMAC0_DMAMD_SM_Pos        (14UL)         /*!< SM (Bit 14)                                           */
36771  #define R_DMAC0_DMAMD_SM_Msk        (0xc000UL)     /*!< SM (Bitfield-Mask: 0x03)                              */
36772  #define R_DMAC0_DMAMD_SARA_Pos      (8UL)          /*!< SARA (Bit 8)                                          */
36773  #define R_DMAC0_DMAMD_SARA_Msk      (0x1f00UL)     /*!< SARA (Bitfield-Mask: 0x1f)                            */
36774  #define R_DMAC0_DMAMD_DM_Pos        (6UL)          /*!< DM (Bit 6)                                            */
36775  #define R_DMAC0_DMAMD_DM_Msk        (0xc0UL)       /*!< DM (Bitfield-Mask: 0x03)                              */
36776  #define R_DMAC0_DMAMD_DARA_Pos      (0UL)          /*!< DARA (Bit 0)                                          */
36777  #define R_DMAC0_DMAMD_DARA_Msk      (0x1fUL)       /*!< DARA (Bitfield-Mask: 0x1f)                            */
36778  #define R_DMAC0_DMAMD_DADR_Pos      (5UL)          /*!< DADR (Bit 5)                                          */
36779  #define R_DMAC0_DMAMD_DADR_Msk      (0x20UL)       /*!< DADR (Bitfield-Mask: 0x01)                            */
36780  #define R_DMAC0_DMAMD_SADR_Pos      (13UL)         /*!< SADR (Bit 13)                                         */
36781  #define R_DMAC0_DMAMD_SADR_Msk      (0x2000UL)     /*!< SADR (Bitfield-Mask: 0x01)                            */
36782 /* =========================================================  DMOFR  ========================================================= */
36783  #define R_DMAC0_DMOFR_DMOFR_Pos     (0UL)          /*!< DMOFR (Bit 0)                                         */
36784  #define R_DMAC0_DMOFR_DMOFR_Msk     (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff)                     */
36785 /* =========================================================  DMCNT  ========================================================= */
36786  #define R_DMAC0_DMCNT_DTE_Pos       (0UL)          /*!< DTE (Bit 0)                                           */
36787  #define R_DMAC0_DMCNT_DTE_Msk       (0x1UL)        /*!< DTE (Bitfield-Mask: 0x01)                             */
36788 /* =========================================================  DMREQ  ========================================================= */
36789  #define R_DMAC0_DMREQ_CLRS_Pos      (4UL)          /*!< CLRS (Bit 4)                                          */
36790  #define R_DMAC0_DMREQ_CLRS_Msk      (0x10UL)       /*!< CLRS (Bitfield-Mask: 0x01)                            */
36791  #define R_DMAC0_DMREQ_SWREQ_Pos     (0UL)          /*!< SWREQ (Bit 0)                                         */
36792  #define R_DMAC0_DMREQ_SWREQ_Msk     (0x1UL)        /*!< SWREQ (Bitfield-Mask: 0x01)                           */
36793 /* =========================================================  DMSTS  ========================================================= */
36794  #define R_DMAC0_DMSTS_ACT_Pos       (7UL)          /*!< ACT (Bit 7)                                           */
36795  #define R_DMAC0_DMSTS_ACT_Msk       (0x80UL)       /*!< ACT (Bitfield-Mask: 0x01)                             */
36796  #define R_DMAC0_DMSTS_DTIF_Pos      (4UL)          /*!< DTIF (Bit 4)                                          */
36797  #define R_DMAC0_DMSTS_DTIF_Msk      (0x10UL)       /*!< DTIF (Bitfield-Mask: 0x01)                            */
36798  #define R_DMAC0_DMSTS_ESIF_Pos      (0UL)          /*!< ESIF (Bit 0)                                          */
36799  #define R_DMAC0_DMSTS_ESIF_Msk      (0x1UL)        /*!< ESIF (Bitfield-Mask: 0x01)                            */
36800 /* =========================================================  DMSRR  ========================================================= */
36801 /* =========================================================  DMDRR  ========================================================= */
36802 /* =========================================================  DMSBS  ========================================================= */
36803  #define R_DMAC0_DMSBS_DMSBSL_Pos    (0UL)          /*!< DMSBSL (Bit 0)                                        */
36804  #define R_DMAC0_DMSBS_DMSBSL_Msk    (0xffffUL)     /*!< DMSBSL (Bitfield-Mask: 0xffff)                        */
36805  #define R_DMAC0_DMSBS_DMSBSH_Pos    (16UL)         /*!< DMSBSH (Bit 16)                                       */
36806  #define R_DMAC0_DMSBS_DMSBSH_Msk    (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff)                        */
36807 /* =========================================================  DMDBS  ========================================================= */
36808  #define R_DMAC0_DMDBS_DMDBSL_Pos    (0UL)          /*!< DMDBSL (Bit 0)                                        */
36809  #define R_DMAC0_DMDBS_DMDBSL_Msk    (0xffffUL)     /*!< DMDBSL (Bitfield-Mask: 0xffff)                        */
36810  #define R_DMAC0_DMDBS_DMDBSH_Pos    (16UL)         /*!< DMDBSH (Bit 16)                                       */
36811  #define R_DMAC0_DMDBS_DMDBSH_Msk    (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff)                        */
36812 /* =========================================================  DMBWR  ========================================================= */
36813  #define R_DMAC0_DMBWR_BWE_Pos       (0UL)          /*!< BWE (Bit 0)                                           */
36814  #define R_DMAC0_DMBWR_BWE_Msk       (0x1UL)        /*!< BWE (Bitfield-Mask: 0x01)                             */
36815 
36816 /* =========================================================================================================================== */
36817 /* ================                                           R_DOC                                           ================ */
36818 /* =========================================================================================================================== */
36819 
36820 /* =========================================================  DOCR  ========================================================== */
36821  #define R_DOC_DOCR_DOPCFCL_Pos    (6UL)      /*!< DOPCFCL (Bit 6)                                       */
36822  #define R_DOC_DOCR_DOPCFCL_Msk    (0x40UL)   /*!< DOPCFCL (Bitfield-Mask: 0x01)                         */
36823  #define R_DOC_DOCR_DOPCF_Pos      (5UL)      /*!< DOPCF (Bit 5)                                         */
36824  #define R_DOC_DOCR_DOPCF_Msk      (0x20UL)   /*!< DOPCF (Bitfield-Mask: 0x01)                           */
36825  #define R_DOC_DOCR_DCSEL_Pos      (2UL)      /*!< DCSEL (Bit 2)                                         */
36826  #define R_DOC_DOCR_DCSEL_Msk      (0x4UL)    /*!< DCSEL (Bitfield-Mask: 0x01)                           */
36827  #define R_DOC_DOCR_OMS_Pos        (0UL)      /*!< OMS (Bit 0)                                           */
36828  #define R_DOC_DOCR_OMS_Msk        (0x3UL)    /*!< OMS (Bitfield-Mask: 0x03)                             */
36829 /* =========================================================  DODIR  ========================================================= */
36830  #define R_DOC_DODIR_DODIR_Pos     (0UL)      /*!< DODIR (Bit 0)                                         */
36831  #define R_DOC_DODIR_DODIR_Msk     (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff)                         */
36832 /* =========================================================  DODSR  ========================================================= */
36833  #define R_DOC_DODSR_DODSR_Pos     (0UL)      /*!< DODSR (Bit 0)                                         */
36834  #define R_DOC_DODSR_DODSR_Msk     (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff)                         */
36835 
36836 /* =========================================================================================================================== */
36837 /* ================                                           R_DRW                                           ================ */
36838 /* =========================================================================================================================== */
36839 
36840 /* ========================================================  CONTROL  ======================================================== */
36841  #define R_DRW_CONTROL_SPANSTORE_Pos           (23UL)         /*!< SPANSTORE (Bit 23)                                    */
36842  #define R_DRW_CONTROL_SPANSTORE_Msk           (0x800000UL)   /*!< SPANSTORE (Bitfield-Mask: 0x01)                       */
36843  #define R_DRW_CONTROL_SPANABORT_Pos           (22UL)         /*!< SPANABORT (Bit 22)                                    */
36844  #define R_DRW_CONTROL_SPANABORT_Msk           (0x400000UL)   /*!< SPANABORT (Bitfield-Mask: 0x01)                       */
36845  #define R_DRW_CONTROL_UNIONCD_Pos             (21UL)         /*!< UNIONCD (Bit 21)                                      */
36846  #define R_DRW_CONTROL_UNIONCD_Msk             (0x200000UL)   /*!< UNIONCD (Bitfield-Mask: 0x01)                         */
36847  #define R_DRW_CONTROL_UNIONAB_Pos             (20UL)         /*!< UNIONAB (Bit 20)                                      */
36848  #define R_DRW_CONTROL_UNIONAB_Msk             (0x100000UL)   /*!< UNIONAB (Bitfield-Mask: 0x01)                         */
36849  #define R_DRW_CONTROL_UNION56_Pos             (19UL)         /*!< UNION56 (Bit 19)                                      */
36850  #define R_DRW_CONTROL_UNION56_Msk             (0x80000UL)    /*!< UNION56 (Bitfield-Mask: 0x01)                         */
36851  #define R_DRW_CONTROL_UNION34_Pos             (18UL)         /*!< UNION34 (Bit 18)                                      */
36852  #define R_DRW_CONTROL_UNION34_Msk             (0x40000UL)    /*!< UNION34 (Bitfield-Mask: 0x01)                         */
36853  #define R_DRW_CONTROL_UNION12_Pos             (17UL)         /*!< UNION12 (Bit 17)                                      */
36854  #define R_DRW_CONTROL_UNION12_Msk             (0x20000UL)    /*!< UNION12 (Bitfield-Mask: 0x01)                         */
36855  #define R_DRW_CONTROL_BAND2ENABLE_Pos         (16UL)         /*!< BAND2ENABLE (Bit 16)                                  */
36856  #define R_DRW_CONTROL_BAND2ENABLE_Msk         (0x10000UL)    /*!< BAND2ENABLE (Bitfield-Mask: 0x01)                     */
36857  #define R_DRW_CONTROL_BAND1ENABLE_Pos         (15UL)         /*!< BAND1ENABLE (Bit 15)                                  */
36858  #define R_DRW_CONTROL_BAND1ENABLE_Msk         (0x8000UL)     /*!< BAND1ENABLE (Bitfield-Mask: 0x01)                     */
36859  #define R_DRW_CONTROL_LIM6THRESHOLD_Pos       (14UL)         /*!< LIM6THRESHOLD (Bit 14)                                */
36860  #define R_DRW_CONTROL_LIM6THRESHOLD_Msk       (0x4000UL)     /*!< LIM6THRESHOLD (Bitfield-Mask: 0x01)                   */
36861  #define R_DRW_CONTROL_LIM5THRESHOLD_Pos       (13UL)         /*!< LIM5THRESHOLD (Bit 13)                                */
36862  #define R_DRW_CONTROL_LIM5THRESHOLD_Msk       (0x2000UL)     /*!< LIM5THRESHOLD (Bitfield-Mask: 0x01)                   */
36863  #define R_DRW_CONTROL_LIM4THRESHOLD_Pos       (12UL)         /*!< LIM4THRESHOLD (Bit 12)                                */
36864  #define R_DRW_CONTROL_LIM4THRESHOLD_Msk       (0x1000UL)     /*!< LIM4THRESHOLD (Bitfield-Mask: 0x01)                   */
36865  #define R_DRW_CONTROL_LIM3THRESHOLD_Pos       (11UL)         /*!< LIM3THRESHOLD (Bit 11)                                */
36866  #define R_DRW_CONTROL_LIM3THRESHOLD_Msk       (0x800UL)      /*!< LIM3THRESHOLD (Bitfield-Mask: 0x01)                   */
36867  #define R_DRW_CONTROL_LIM2THRESHOLD_Pos       (10UL)         /*!< LIM2THRESHOLD (Bit 10)                                */
36868  #define R_DRW_CONTROL_LIM2THRESHOLD_Msk       (0x400UL)      /*!< LIM2THRESHOLD (Bitfield-Mask: 0x01)                   */
36869  #define R_DRW_CONTROL_LIM1THRESHOLD_Pos       (9UL)          /*!< LIM1THRESHOLD (Bit 9)                                 */
36870  #define R_DRW_CONTROL_LIM1THRESHOLD_Msk       (0x200UL)      /*!< LIM1THRESHOLD (Bitfield-Mask: 0x01)                   */
36871  #define R_DRW_CONTROL_QUAD3ENABLE_Pos         (8UL)          /*!< QUAD3ENABLE (Bit 8)                                   */
36872  #define R_DRW_CONTROL_QUAD3ENABLE_Msk         (0x100UL)      /*!< QUAD3ENABLE (Bitfield-Mask: 0x01)                     */
36873  #define R_DRW_CONTROL_QUAD2ENABLE_Pos         (7UL)          /*!< QUAD2ENABLE (Bit 7)                                   */
36874  #define R_DRW_CONTROL_QUAD2ENABLE_Msk         (0x80UL)       /*!< QUAD2ENABLE (Bitfield-Mask: 0x01)                     */
36875  #define R_DRW_CONTROL_QUAD1ENABLE_Pos         (6UL)          /*!< QUAD1ENABLE (Bit 6)                                   */
36876  #define R_DRW_CONTROL_QUAD1ENABLE_Msk         (0x40UL)       /*!< QUAD1ENABLE (Bitfield-Mask: 0x01)                     */
36877  #define R_DRW_CONTROL_LIM6ENABLE_Pos          (5UL)          /*!< LIM6ENABLE (Bit 5)                                    */
36878  #define R_DRW_CONTROL_LIM6ENABLE_Msk          (0x20UL)       /*!< LIM6ENABLE (Bitfield-Mask: 0x01)                      */
36879  #define R_DRW_CONTROL_LIM5ENABLE_Pos          (4UL)          /*!< LIM5ENABLE (Bit 4)                                    */
36880  #define R_DRW_CONTROL_LIM5ENABLE_Msk          (0x10UL)       /*!< LIM5ENABLE (Bitfield-Mask: 0x01)                      */
36881  #define R_DRW_CONTROL_LIM4ENABLE_Pos          (3UL)          /*!< LIM4ENABLE (Bit 3)                                    */
36882  #define R_DRW_CONTROL_LIM4ENABLE_Msk          (0x8UL)        /*!< LIM4ENABLE (Bitfield-Mask: 0x01)                      */
36883  #define R_DRW_CONTROL_LIM3ENABLE_Pos          (2UL)          /*!< LIM3ENABLE (Bit 2)                                    */
36884  #define R_DRW_CONTROL_LIM3ENABLE_Msk          (0x4UL)        /*!< LIM3ENABLE (Bitfield-Mask: 0x01)                      */
36885  #define R_DRW_CONTROL_LIM2ENABLE_Pos          (1UL)          /*!< LIM2ENABLE (Bit 1)                                    */
36886  #define R_DRW_CONTROL_LIM2ENABLE_Msk          (0x2UL)        /*!< LIM2ENABLE (Bitfield-Mask: 0x01)                      */
36887  #define R_DRW_CONTROL_LIM1ENABLE_Pos          (0UL)          /*!< LIM1ENABLE (Bit 0)                                    */
36888  #define R_DRW_CONTROL_LIM1ENABLE_Msk          (0x1UL)        /*!< LIM1ENABLE (Bitfield-Mask: 0x01)                      */
36889 /* =======================================================  CONTROL2  ======================================================== */
36890  #define R_DRW_CONTROL2_RLEPIXELWIDTH_Pos      (30UL)         /*!< RLEPIXELWIDTH (Bit 30)                                */
36891  #define R_DRW_CONTROL2_RLEPIXELWIDTH_Msk      (0xc0000000UL) /*!< RLEPIXELWIDTH (Bitfield-Mask: 0x03)                   */
36892  #define R_DRW_CONTROL2_BDIA_Pos               (29UL)         /*!< BDIA (Bit 29)                                         */
36893  #define R_DRW_CONTROL2_BDIA_Msk               (0x20000000UL) /*!< BDIA (Bitfield-Mask: 0x01)                            */
36894  #define R_DRW_CONTROL2_BSIA_Pos               (28UL)         /*!< BSIA (Bit 28)                                         */
36895  #define R_DRW_CONTROL2_BSIA_Msk               (0x10000000UL) /*!< BSIA (Bitfield-Mask: 0x01)                            */
36896  #define R_DRW_CONTROL2_CLUTFORMAT_Pos         (27UL)         /*!< CLUTFORMAT (Bit 27)                                   */
36897  #define R_DRW_CONTROL2_CLUTFORMAT_Msk         (0x8000000UL)  /*!< CLUTFORMAT (Bitfield-Mask: 0x01)                      */
36898  #define R_DRW_CONTROL2_COLKEYENABLE_Pos       (26UL)         /*!< COLKEYENABLE (Bit 26)                                 */
36899  #define R_DRW_CONTROL2_COLKEYENABLE_Msk       (0x4000000UL)  /*!< COLKEYENABLE (Bitfield-Mask: 0x01)                    */
36900  #define R_DRW_CONTROL2_CLUTENABLE_Pos         (25UL)         /*!< CLUTENABLE (Bit 25)                                   */
36901  #define R_DRW_CONTROL2_CLUTENABLE_Msk         (0x2000000UL)  /*!< CLUTENABLE (Bitfield-Mask: 0x01)                      */
36902  #define R_DRW_CONTROL2_RLEENABLE_Pos          (24UL)         /*!< RLEENABLE (Bit 24)                                    */
36903  #define R_DRW_CONTROL2_RLEENABLE_Msk          (0x1000000UL)  /*!< RLEENABLE (Bitfield-Mask: 0x01)                       */
36904  #define R_DRW_CONTROL2_WRITEALPHA_Pos         (22UL)         /*!< WRITEALPHA (Bit 22)                                   */
36905  #define R_DRW_CONTROL2_WRITEALPHA_Msk         (0xc00000UL)   /*!< WRITEALPHA (Bitfield-Mask: 0x03)                      */
36906  #define R_DRW_CONTROL2_WRITEFORMAT10_Pos      (20UL)         /*!< WRITEFORMAT10 (Bit 20)                                */
36907  #define R_DRW_CONTROL2_WRITEFORMAT10_Msk      (0x300000UL)   /*!< WRITEFORMAT10 (Bitfield-Mask: 0x03)                   */
36908  #define R_DRW_CONTROL2_READFORMAT10_Pos       (18UL)         /*!< READFORMAT10 (Bit 18)                                 */
36909  #define R_DRW_CONTROL2_READFORMAT10_Msk       (0xc0000UL)    /*!< READFORMAT10 (Bitfield-Mask: 0x03)                    */
36910  #define R_DRW_CONTROL2_TEXTUREFILTERY_Pos     (17UL)         /*!< TEXTUREFILTERY (Bit 17)                               */
36911  #define R_DRW_CONTROL2_TEXTUREFILTERY_Msk     (0x20000UL)    /*!< TEXTUREFILTERY (Bitfield-Mask: 0x01)                  */
36912  #define R_DRW_CONTROL2_TEXTUREFILTERX_Pos     (16UL)         /*!< TEXTUREFILTERX (Bit 16)                               */
36913  #define R_DRW_CONTROL2_TEXTUREFILTERX_Msk     (0x10000UL)    /*!< TEXTUREFILTERX (Bitfield-Mask: 0x01)                  */
36914  #define R_DRW_CONTROL2_TEXTURECLAMPY_Pos      (15UL)         /*!< TEXTURECLAMPY (Bit 15)                                */
36915  #define R_DRW_CONTROL2_TEXTURECLAMPY_Msk      (0x8000UL)     /*!< TEXTURECLAMPY (Bitfield-Mask: 0x01)                   */
36916  #define R_DRW_CONTROL2_TEXTURECLAMPX_Pos      (14UL)         /*!< TEXTURECLAMPX (Bit 14)                                */
36917  #define R_DRW_CONTROL2_TEXTURECLAMPX_Msk      (0x4000UL)     /*!< TEXTURECLAMPX (Bitfield-Mask: 0x01)                   */
36918  #define R_DRW_CONTROL2_BC2_Pos                (13UL)         /*!< BC2 (Bit 13)                                          */
36919  #define R_DRW_CONTROL2_BC2_Msk                (0x2000UL)     /*!< BC2 (Bitfield-Mask: 0x01)                             */
36920  #define R_DRW_CONTROL2_BDI_Pos                (12UL)         /*!< BDI (Bit 12)                                          */
36921  #define R_DRW_CONTROL2_BDI_Msk                (0x1000UL)     /*!< BDI (Bitfield-Mask: 0x01)                             */
36922  #define R_DRW_CONTROL2_BSI_Pos                (11UL)         /*!< BSI (Bit 11)                                          */
36923  #define R_DRW_CONTROL2_BSI_Msk                (0x800UL)      /*!< BSI (Bitfield-Mask: 0x01)                             */
36924  #define R_DRW_CONTROL2_BDF_Pos                (10UL)         /*!< BDF (Bit 10)                                          */
36925  #define R_DRW_CONTROL2_BDF_Msk                (0x400UL)      /*!< BDF (Bitfield-Mask: 0x01)                             */
36926  #define R_DRW_CONTROL2_BSF_Pos                (9UL)          /*!< BSF (Bit 9)                                           */
36927  #define R_DRW_CONTROL2_BSF_Msk                (0x200UL)      /*!< BSF (Bitfield-Mask: 0x01)                             */
36928  #define R_DRW_CONTROL2_WRITEFORMAT2_Pos       (8UL)          /*!< WRITEFORMAT2 (Bit 8)                                  */
36929  #define R_DRW_CONTROL2_WRITEFORMAT2_Msk       (0x100UL)      /*!< WRITEFORMAT2 (Bitfield-Mask: 0x01)                    */
36930  #define R_DRW_CONTROL2_BDFA_Pos               (7UL)          /*!< BDFA (Bit 7)                                          */
36931  #define R_DRW_CONTROL2_BDFA_Msk               (0x80UL)       /*!< BDFA (Bitfield-Mask: 0x01)                            */
36932  #define R_DRW_CONTROL2_BSFA_Pos               (6UL)          /*!< BSFA (Bit 6)                                          */
36933  #define R_DRW_CONTROL2_BSFA_Msk               (0x40UL)       /*!< BSFA (Bitfield-Mask: 0x01)                            */
36934  #define R_DRW_CONTROL2_READFORMAT32_Pos       (4UL)          /*!< READFORMAT32 (Bit 4)                                  */
36935  #define R_DRW_CONTROL2_READFORMAT32_Msk       (0x30UL)       /*!< READFORMAT32 (Bitfield-Mask: 0x03)                    */
36936  #define R_DRW_CONTROL2_USEACB_Pos             (3UL)          /*!< USEACB (Bit 3)                                        */
36937  #define R_DRW_CONTROL2_USEACB_Msk             (0x8UL)        /*!< USEACB (Bitfield-Mask: 0x01)                          */
36938  #define R_DRW_CONTROL2_PATTERNSOURCEL5_Pos    (2UL)          /*!< PATTERNSOURCEL5 (Bit 2)                               */
36939  #define R_DRW_CONTROL2_PATTERNSOURCEL5_Msk    (0x4UL)        /*!< PATTERNSOURCEL5 (Bitfield-Mask: 0x01)                 */
36940  #define R_DRW_CONTROL2_TEXTUREENABLE_Pos      (1UL)          /*!< TEXTUREENABLE (Bit 1)                                 */
36941  #define R_DRW_CONTROL2_TEXTUREENABLE_Msk      (0x2UL)        /*!< TEXTUREENABLE (Bitfield-Mask: 0x01)                   */
36942  #define R_DRW_CONTROL2_PATTERNENABLE_Pos      (0UL)          /*!< PATTERNENABLE (Bit 0)                                 */
36943  #define R_DRW_CONTROL2_PATTERNENABLE_Msk      (0x1UL)        /*!< PATTERNENABLE (Bitfield-Mask: 0x01)                   */
36944 /* ========================================================  IRQCTL  ========================================================= */
36945  #define R_DRW_IRQCTL_BUSIRQCLR_Pos            (5UL)          /*!< BUSIRQCLR (Bit 5)                                     */
36946  #define R_DRW_IRQCTL_BUSIRQCLR_Msk            (0x20UL)       /*!< BUSIRQCLR (Bitfield-Mask: 0x01)                       */
36947  #define R_DRW_IRQCTL_BUSIRQEN_Pos             (4UL)          /*!< BUSIRQEN (Bit 4)                                      */
36948  #define R_DRW_IRQCTL_BUSIRQEN_Msk             (0x10UL)       /*!< BUSIRQEN (Bitfield-Mask: 0x01)                        */
36949  #define R_DRW_IRQCTL_DLISTIRQCLR_Pos          (3UL)          /*!< DLISTIRQCLR (Bit 3)                                   */
36950  #define R_DRW_IRQCTL_DLISTIRQCLR_Msk          (0x8UL)        /*!< DLISTIRQCLR (Bitfield-Mask: 0x01)                     */
36951  #define R_DRW_IRQCTL_ENUMIRQCLR_Pos           (2UL)          /*!< ENUMIRQCLR (Bit 2)                                    */
36952  #define R_DRW_IRQCTL_ENUMIRQCLR_Msk           (0x4UL)        /*!< ENUMIRQCLR (Bitfield-Mask: 0x01)                      */
36953  #define R_DRW_IRQCTL_DLISTIRQEN_Pos           (1UL)          /*!< DLISTIRQEN (Bit 1)                                    */
36954  #define R_DRW_IRQCTL_DLISTIRQEN_Msk           (0x2UL)        /*!< DLISTIRQEN (Bitfield-Mask: 0x01)                      */
36955  #define R_DRW_IRQCTL_ENUMIRQEN_Pos            (0UL)          /*!< ENUMIRQEN (Bit 0)                                     */
36956  #define R_DRW_IRQCTL_ENUMIRQEN_Msk            (0x1UL)        /*!< ENUMIRQEN (Bitfield-Mask: 0x01)                       */
36957 /* =======================================================  CACHECTL  ======================================================== */
36958  #define R_DRW_CACHECTL_CFLUSHTX_Pos           (3UL)          /*!< CFLUSHTX (Bit 3)                                      */
36959  #define R_DRW_CACHECTL_CFLUSHTX_Msk           (0x8UL)        /*!< CFLUSHTX (Bitfield-Mask: 0x01)                        */
36960  #define R_DRW_CACHECTL_CENABLETX_Pos          (2UL)          /*!< CENABLETX (Bit 2)                                     */
36961  #define R_DRW_CACHECTL_CENABLETX_Msk          (0x4UL)        /*!< CENABLETX (Bitfield-Mask: 0x01)                       */
36962  #define R_DRW_CACHECTL_CFLUSHFX_Pos           (1UL)          /*!< CFLUSHFX (Bit 1)                                      */
36963  #define R_DRW_CACHECTL_CFLUSHFX_Msk           (0x2UL)        /*!< CFLUSHFX (Bitfield-Mask: 0x01)                        */
36964  #define R_DRW_CACHECTL_CENABLEFX_Pos          (0UL)          /*!< CENABLEFX (Bit 0)                                     */
36965  #define R_DRW_CACHECTL_CENABLEFX_Msk          (0x1UL)        /*!< CENABLEFX (Bitfield-Mask: 0x01)                       */
36966 /* ========================================================  STATUS  ========================================================= */
36967  #define R_DRW_STATUS_BUSERRMDL_Pos            (10UL)         /*!< BUSERRMDL (Bit 10)                                    */
36968  #define R_DRW_STATUS_BUSERRMDL_Msk            (0x400UL)      /*!< BUSERRMDL (Bitfield-Mask: 0x01)                       */
36969  #define R_DRW_STATUS_BUSERRMTXMRL_Pos         (9UL)          /*!< BUSERRMTXMRL (Bit 9)                                  */
36970  #define R_DRW_STATUS_BUSERRMTXMRL_Msk         (0x200UL)      /*!< BUSERRMTXMRL (Bitfield-Mask: 0x01)                    */
36971  #define R_DRW_STATUS_BUSERRMFB_Pos            (8UL)          /*!< BUSERRMFB (Bit 8)                                     */
36972  #define R_DRW_STATUS_BUSERRMFB_Msk            (0x100UL)      /*!< BUSERRMFB (Bitfield-Mask: 0x01)                       */
36973  #define R_DRW_STATUS_BUSIRQ_Pos               (6UL)          /*!< BUSIRQ (Bit 6)                                        */
36974  #define R_DRW_STATUS_BUSIRQ_Msk               (0x40UL)       /*!< BUSIRQ (Bitfield-Mask: 0x01)                          */
36975  #define R_DRW_STATUS_DLISTIRQ_Pos             (5UL)          /*!< DLISTIRQ (Bit 5)                                      */
36976  #define R_DRW_STATUS_DLISTIRQ_Msk             (0x20UL)       /*!< DLISTIRQ (Bitfield-Mask: 0x01)                        */
36977  #define R_DRW_STATUS_ENUMIRQ_Pos              (4UL)          /*!< ENUMIRQ (Bit 4)                                       */
36978  #define R_DRW_STATUS_ENUMIRQ_Msk              (0x10UL)       /*!< ENUMIRQ (Bitfield-Mask: 0x01)                         */
36979  #define R_DRW_STATUS_DLISTACTIVE_Pos          (3UL)          /*!< DLISTACTIVE (Bit 3)                                   */
36980  #define R_DRW_STATUS_DLISTACTIVE_Msk          (0x8UL)        /*!< DLISTACTIVE (Bitfield-Mask: 0x01)                     */
36981  #define R_DRW_STATUS_CACHEDIRTY_Pos           (2UL)          /*!< CACHEDIRTY (Bit 2)                                    */
36982  #define R_DRW_STATUS_CACHEDIRTY_Msk           (0x4UL)        /*!< CACHEDIRTY (Bitfield-Mask: 0x01)                      */
36983  #define R_DRW_STATUS_BUSYWRITE_Pos            (1UL)          /*!< BUSYWRITE (Bit 1)                                     */
36984  #define R_DRW_STATUS_BUSYWRITE_Msk            (0x2UL)        /*!< BUSYWRITE (Bitfield-Mask: 0x01)                       */
36985  #define R_DRW_STATUS_BUSYENUM_Pos             (0UL)          /*!< BUSYENUM (Bit 0)                                      */
36986  #define R_DRW_STATUS_BUSYENUM_Msk             (0x1UL)        /*!< BUSYENUM (Bitfield-Mask: 0x01)                        */
36987 /* ======================================================  HWREVISION  ======================================================= */
36988  #define R_DRW_HWREVISION_ACBLEND_Pos          (27UL)         /*!< ACBLEND (Bit 27)                                      */
36989  #define R_DRW_HWREVISION_ACBLEND_Msk          (0x8000000UL)  /*!< ACBLEND (Bitfield-Mask: 0x01)                         */
36990  #define R_DRW_HWREVISION_COLORKEY_Pos         (25UL)         /*!< COLORKEY (Bit 25)                                     */
36991  #define R_DRW_HWREVISION_COLORKEY_Msk         (0x2000000UL)  /*!< COLORKEY (Bitfield-Mask: 0x01)                        */
36992  #define R_DRW_HWREVISION_TEXCLUT256_Pos       (24UL)         /*!< TEXCLUT256 (Bit 24)                                   */
36993  #define R_DRW_HWREVISION_TEXCLUT256_Msk       (0x1000000UL)  /*!< TEXCLUT256 (Bitfield-Mask: 0x01)                      */
36994  #define R_DRW_HWREVISION_RLEUNIT_Pos          (23UL)         /*!< RLEUNIT (Bit 23)                                      */
36995  #define R_DRW_HWREVISION_RLEUNIT_Msk          (0x800000UL)   /*!< RLEUNIT (Bitfield-Mask: 0x01)                         */
36996  #define R_DRW_HWREVISION_TEXCLU_Pos           (21UL)         /*!< TEXCLU (Bit 21)                                       */
36997  #define R_DRW_HWREVISION_TEXCLU_Msk           (0x200000UL)   /*!< TEXCLU (Bitfield-Mask: 0x01)                          */
36998  #define R_DRW_HWREVISION_PERFCOUNT_Pos        (20UL)         /*!< PERFCOUNT (Bit 20)                                    */
36999  #define R_DRW_HWREVISION_PERFCOUNT_Msk        (0x100000UL)   /*!< PERFCOUNT (Bitfield-Mask: 0x01)                       */
37000  #define R_DRW_HWREVISION_TXCACHE_Pos          (19UL)         /*!< TXCACHE (Bit 19)                                      */
37001  #define R_DRW_HWREVISION_TXCACHE_Msk          (0x80000UL)    /*!< TXCACHE (Bitfield-Mask: 0x01)                         */
37002  #define R_DRW_HWREVISION_FBCACHE_Pos          (18UL)         /*!< FBCACHE (Bit 18)                                      */
37003  #define R_DRW_HWREVISION_FBCACHE_Msk          (0x40000UL)    /*!< FBCACHE (Bitfield-Mask: 0x01)                         */
37004  #define R_DRW_HWREVISION_DLR_Pos              (17UL)         /*!< DLR (Bit 17)                                          */
37005  #define R_DRW_HWREVISION_DLR_Msk              (0x20000UL)    /*!< DLR (Bitfield-Mask: 0x01)                             */
37006  #define R_DRW_HWREVISION_REV_Pos              (0UL)          /*!< REV (Bit 0)                                           */
37007  #define R_DRW_HWREVISION_REV_Msk              (0xfffUL)      /*!< REV (Bitfield-Mask: 0xfff)                            */
37008 /* ========================================================  COLOR1  ========================================================= */
37009  #define R_DRW_COLOR1_COLOR1A_Pos              (24UL)         /*!< COLOR1A (Bit 24)                                      */
37010  #define R_DRW_COLOR1_COLOR1A_Msk              (0xff000000UL) /*!< COLOR1A (Bitfield-Mask: 0xff)                         */
37011  #define R_DRW_COLOR1_COLOR1R_Pos              (16UL)         /*!< COLOR1R (Bit 16)                                      */
37012  #define R_DRW_COLOR1_COLOR1R_Msk              (0xff0000UL)   /*!< COLOR1R (Bitfield-Mask: 0xff)                         */
37013  #define R_DRW_COLOR1_COLOR1G_Pos              (8UL)          /*!< COLOR1G (Bit 8)                                       */
37014  #define R_DRW_COLOR1_COLOR1G_Msk              (0xff00UL)     /*!< COLOR1G (Bitfield-Mask: 0xff)                         */
37015  #define R_DRW_COLOR1_COLOR1B_Pos              (0UL)          /*!< COLOR1B (Bit 0)                                       */
37016  #define R_DRW_COLOR1_COLOR1B_Msk              (0xffUL)       /*!< COLOR1B (Bitfield-Mask: 0xff)                         */
37017 /* ========================================================  COLOR2  ========================================================= */
37018  #define R_DRW_COLOR2_COLOR2A_Pos              (24UL)         /*!< COLOR2A (Bit 24)                                      */
37019  #define R_DRW_COLOR2_COLOR2A_Msk              (0xff000000UL) /*!< COLOR2A (Bitfield-Mask: 0xff)                         */
37020  #define R_DRW_COLOR2_COLOR2R_Pos              (16UL)         /*!< COLOR2R (Bit 16)                                      */
37021  #define R_DRW_COLOR2_COLOR2R_Msk              (0xff0000UL)   /*!< COLOR2R (Bitfield-Mask: 0xff)                         */
37022  #define R_DRW_COLOR2_COLOR2G_Pos              (8UL)          /*!< COLOR2G (Bit 8)                                       */
37023  #define R_DRW_COLOR2_COLOR2G_Msk              (0xff00UL)     /*!< COLOR2G (Bitfield-Mask: 0xff)                         */
37024  #define R_DRW_COLOR2_COLOR2B_Pos              (0UL)          /*!< COLOR2B (Bit 0)                                       */
37025  #define R_DRW_COLOR2_COLOR2B_Msk              (0xffUL)       /*!< COLOR2B (Bitfield-Mask: 0xff)                         */
37026 /* ========================================================  PATTERN  ======================================================== */
37027  #define R_DRW_PATTERN_PATTERN_Pos             (0UL)          /*!< PATTERN (Bit 0)                                       */
37028  #define R_DRW_PATTERN_PATTERN_Msk             (0xffUL)       /*!< PATTERN (Bitfield-Mask: 0xff)                         */
37029 /* ========================================================  L1START  ======================================================== */
37030  #define R_DRW_L1START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
37031  #define R_DRW_L1START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
37032 /* ========================================================  L2START  ======================================================== */
37033  #define R_DRW_L2START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
37034  #define R_DRW_L2START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
37035 /* ========================================================  L3START  ======================================================== */
37036  #define R_DRW_L3START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
37037  #define R_DRW_L3START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
37038 /* ========================================================  L4START  ======================================================== */
37039  #define R_DRW_L4START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
37040  #define R_DRW_L4START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
37041 /* ========================================================  L5START  ======================================================== */
37042  #define R_DRW_L5START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
37043  #define R_DRW_L5START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
37044 /* ========================================================  L6START  ======================================================== */
37045  #define R_DRW_L6START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
37046  #define R_DRW_L6START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
37047 /* ========================================================  L1XADD  ========================================================= */
37048  #define R_DRW_L1XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
37049  #define R_DRW_L1XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
37050 /* ========================================================  L2XADD  ========================================================= */
37051  #define R_DRW_L2XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
37052  #define R_DRW_L2XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
37053 /* ========================================================  L3XADD  ========================================================= */
37054  #define R_DRW_L3XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
37055  #define R_DRW_L3XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
37056 /* ========================================================  L4XADD  ========================================================= */
37057  #define R_DRW_L4XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
37058  #define R_DRW_L4XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
37059 /* ========================================================  L5XADD  ========================================================= */
37060  #define R_DRW_L5XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
37061  #define R_DRW_L5XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
37062 /* ========================================================  L6XADD  ========================================================= */
37063  #define R_DRW_L6XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
37064  #define R_DRW_L6XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
37065 /* ========================================================  L1YADD  ========================================================= */
37066  #define R_DRW_L1YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
37067  #define R_DRW_L1YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
37068 /* ========================================================  L2YADD  ========================================================= */
37069  #define R_DRW_L2YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
37070  #define R_DRW_L2YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
37071 /* ========================================================  L3YADD  ========================================================= */
37072  #define R_DRW_L3YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
37073  #define R_DRW_L3YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
37074 /* ========================================================  L4YADD  ========================================================= */
37075  #define R_DRW_L4YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
37076  #define R_DRW_L4YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
37077 /* ========================================================  L5YADD  ========================================================= */
37078  #define R_DRW_L5YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
37079  #define R_DRW_L5YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
37080 /* ========================================================  L6YADD  ========================================================= */
37081  #define R_DRW_L6YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
37082  #define R_DRW_L6YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
37083 /* ========================================================  L1BAND  ========================================================= */
37084  #define R_DRW_L1BAND_LBAND_Pos                (0UL)          /*!< LBAND (Bit 0)                                         */
37085  #define R_DRW_L1BAND_LBAND_Msk                (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff)                     */
37086 /* ========================================================  L2BAND  ========================================================= */
37087  #define R_DRW_L2BAND_LBAND_Pos                (0UL)          /*!< LBAND (Bit 0)                                         */
37088  #define R_DRW_L2BAND_LBAND_Msk                (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff)                     */
37089 /* =======================================================  TEXORIGIN  ======================================================= */
37090  #define R_DRW_TEXORIGIN_TEXORIGIN_Pos         (0UL)          /*!< TEXORIGIN (Bit 0)                                     */
37091  #define R_DRW_TEXORIGIN_TEXORIGIN_Msk         (0xffffffffUL) /*!< TEXORIGIN (Bitfield-Mask: 0xffffffff)                 */
37092 /* =======================================================  TEXPITCH  ======================================================== */
37093  #define R_DRW_TEXPITCH_TEXPITCH_Pos           (0UL)          /*!< TEXPITCH (Bit 0)                                      */
37094  #define R_DRW_TEXPITCH_TEXPITCH_Msk           (0xffffffffUL) /*!< TEXPITCH (Bitfield-Mask: 0xffffffff)                  */
37095 /* ========================================================  TEXMASK  ======================================================== */
37096  #define R_DRW_TEXMASK_TEXVMASK_Pos            (11UL)         /*!< TEXVMASK (Bit 11)                                     */
37097  #define R_DRW_TEXMASK_TEXVMASK_Msk            (0xfffff800UL) /*!< TEXVMASK (Bitfield-Mask: 0x1fffff)                    */
37098  #define R_DRW_TEXMASK_TEXUMASK_Pos            (0UL)          /*!< TEXUMASK (Bit 0)                                      */
37099  #define R_DRW_TEXMASK_TEXUMASK_Msk            (0x7ffUL)      /*!< TEXUMASK (Bitfield-Mask: 0x7ff)                       */
37100 /* ========================================================  LUSTART  ======================================================== */
37101  #define R_DRW_LUSTART_LUSTART_Pos             (0UL)          /*!< LUSTART (Bit 0)                                       */
37102  #define R_DRW_LUSTART_LUSTART_Msk             (0xffffffffUL) /*!< LUSTART (Bitfield-Mask: 0xffffffff)                   */
37103 /* ========================================================  LUXADD  ========================================================= */
37104  #define R_DRW_LUXADD_LUXADD_Pos               (0UL)          /*!< LUXADD (Bit 0)                                        */
37105  #define R_DRW_LUXADD_LUXADD_Msk               (0xffffffffUL) /*!< LUXADD (Bitfield-Mask: 0xffffffff)                    */
37106 /* ========================================================  LUYADD  ========================================================= */
37107  #define R_DRW_LUYADD_LUYADD_Pos               (0UL)          /*!< LUYADD (Bit 0)                                        */
37108  #define R_DRW_LUYADD_LUYADD_Msk               (0xffffffffUL) /*!< LUYADD (Bitfield-Mask: 0xffffffff)                    */
37109 /* =======================================================  LVSTARTI  ======================================================== */
37110  #define R_DRW_LVSTARTI_LVSTARTI_Pos           (0UL)          /*!< LVSTARTI (Bit 0)                                      */
37111  #define R_DRW_LVSTARTI_LVSTARTI_Msk           (0xffffffffUL) /*!< LVSTARTI (Bitfield-Mask: 0xffffffff)                  */
37112 /* =======================================================  LVSTARTF  ======================================================== */
37113  #define R_DRW_LVSTARTF_LVSTARTF_Pos           (0UL)          /*!< LVSTARTF (Bit 0)                                      */
37114  #define R_DRW_LVSTARTF_LVSTARTF_Msk           (0xffffUL)     /*!< LVSTARTF (Bitfield-Mask: 0xffff)                      */
37115 /* ========================================================  LVXADDI  ======================================================== */
37116  #define R_DRW_LVXADDI_LVXADDI_Pos             (0UL)          /*!< LVXADDI (Bit 0)                                       */
37117  #define R_DRW_LVXADDI_LVXADDI_Msk             (0xffffffffUL) /*!< LVXADDI (Bitfield-Mask: 0xffffffff)                   */
37118 /* ========================================================  LVYADDI  ======================================================== */
37119  #define R_DRW_LVYADDI_LVYADDI_Pos             (0UL)          /*!< LVYADDI (Bit 0)                                       */
37120  #define R_DRW_LVYADDI_LVYADDI_Msk             (0xffffffffUL) /*!< LVYADDI (Bitfield-Mask: 0xffffffff)                   */
37121 /* =======================================================  LVYXADDF  ======================================================== */
37122  #define R_DRW_LVYXADDF_LVYADDF_Pos            (16UL)         /*!< LVYADDF (Bit 16)                                      */
37123  #define R_DRW_LVYXADDF_LVYADDF_Msk            (0xffff0000UL) /*!< LVYADDF (Bitfield-Mask: 0xffff)                       */
37124  #define R_DRW_LVYXADDF_LVXADDF_Pos            (0UL)          /*!< LVXADDF (Bit 0)                                       */
37125  #define R_DRW_LVYXADDF_LVXADDF_Msk            (0xffffUL)     /*!< LVXADDF (Bitfield-Mask: 0xffff)                       */
37126 /* =======================================================  TEXCLADDR  ======================================================= */
37127  #define R_DRW_TEXCLADDR_CLADDR_Pos            (0UL)          /*!< CLADDR (Bit 0)                                        */
37128  #define R_DRW_TEXCLADDR_CLADDR_Msk            (0xffUL)       /*!< CLADDR (Bitfield-Mask: 0xff)                          */
37129 /* =======================================================  TEXCLDATA  ======================================================= */
37130  #define R_DRW_TEXCLDATA_CLDATA_Pos            (0UL)          /*!< CLDATA (Bit 0)                                        */
37131  #define R_DRW_TEXCLDATA_CLDATA_Msk            (0xffffffffUL) /*!< CLDATA (Bitfield-Mask: 0xffffffff)                    */
37132 /* ======================================================  TEXCLOFFSET  ====================================================== */
37133  #define R_DRW_TEXCLOFFSET_CLOFFSET_Pos        (0UL)          /*!< CLOFFSET (Bit 0)                                      */
37134  #define R_DRW_TEXCLOFFSET_CLOFFSET_Msk        (0xffUL)       /*!< CLOFFSET (Bitfield-Mask: 0xff)                        */
37135 /* ========================================================  COLKEY  ========================================================= */
37136  #define R_DRW_COLKEY_COLKEYR_Pos              (16UL)         /*!< COLKEYR (Bit 16)                                      */
37137  #define R_DRW_COLKEY_COLKEYR_Msk              (0xff0000UL)   /*!< COLKEYR (Bitfield-Mask: 0xff)                         */
37138  #define R_DRW_COLKEY_COLKEYG_Pos              (8UL)          /*!< COLKEYG (Bit 8)                                       */
37139  #define R_DRW_COLKEY_COLKEYG_Msk              (0xff00UL)     /*!< COLKEYG (Bitfield-Mask: 0xff)                         */
37140  #define R_DRW_COLKEY_COLKEYB_Pos              (0UL)          /*!< COLKEYB (Bit 0)                                       */
37141  #define R_DRW_COLKEY_COLKEYB_Msk              (0xffUL)       /*!< COLKEYB (Bitfield-Mask: 0xff)                         */
37142 /* =========================================================  SIZE  ========================================================== */
37143  #define R_DRW_SIZE_SIZEY_Pos                  (16UL)         /*!< SIZEY (Bit 16)                                        */
37144  #define R_DRW_SIZE_SIZEY_Msk                  (0xffff0000UL) /*!< SIZEY (Bitfield-Mask: 0xffff)                         */
37145  #define R_DRW_SIZE_SIZEX_Pos                  (0UL)          /*!< SIZEX (Bit 0)                                         */
37146  #define R_DRW_SIZE_SIZEX_Msk                  (0xffffUL)     /*!< SIZEX (Bitfield-Mask: 0xffff)                         */
37147 /* =========================================================  PITCH  ========================================================= */
37148  #define R_DRW_PITCH_SSD_Pos                   (16UL)         /*!< SSD (Bit 16)                                          */
37149  #define R_DRW_PITCH_SSD_Msk                   (0xffff0000UL) /*!< SSD (Bitfield-Mask: 0xffff)                           */
37150  #define R_DRW_PITCH_PITCH_Pos                 (0UL)          /*!< PITCH (Bit 0)                                         */
37151  #define R_DRW_PITCH_PITCH_Msk                 (0xffffUL)     /*!< PITCH (Bitfield-Mask: 0xffff)                         */
37152 /* ========================================================  ORIGIN  ========================================================= */
37153  #define R_DRW_ORIGIN_ORIGIN_Pos               (0UL)          /*!< ORIGIN (Bit 0)                                        */
37154  #define R_DRW_ORIGIN_ORIGIN_Msk               (0xffffffffUL) /*!< ORIGIN (Bitfield-Mask: 0xffffffff)                    */
37155 /* ======================================================  DLISTSTART  ======================================================= */
37156  #define R_DRW_DLISTSTART_DLISTSTART_Pos       (0UL)          /*!< DLISTSTART (Bit 0)                                    */
37157  #define R_DRW_DLISTSTART_DLISTSTART_Msk       (0xffffffffUL) /*!< DLISTSTART (Bitfield-Mask: 0xffffffff)                */
37158 /* ======================================================  PERFTRIGGER  ====================================================== */
37159  #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Pos    (16UL)         /*!< PERFTRIGGER2 (Bit 16)                                 */
37160  #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Msk    (0xffff0000UL) /*!< PERFTRIGGER2 (Bitfield-Mask: 0xffff)                  */
37161  #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Pos    (0UL)          /*!< PERFTRIGGER1 (Bit 0)                                  */
37162  #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Msk    (0xffffUL)     /*!< PERFTRIGGER1 (Bitfield-Mask: 0xffff)                  */
37163 /* ======================================================  PERFCOUNT1  ======================================================= */
37164  #define R_DRW_PERFCOUNT1_PERFCOUNT_Pos        (0UL)          /*!< PERFCOUNT (Bit 0)                                     */
37165  #define R_DRW_PERFCOUNT1_PERFCOUNT_Msk        (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff)                 */
37166 /* ======================================================  PERFCOUNT2  ======================================================= */
37167  #define R_DRW_PERFCOUNT2_PERFCOUNT_Pos        (0UL)          /*!< PERFCOUNT (Bit 0)                                     */
37168  #define R_DRW_PERFCOUNT2_PERFCOUNT_Msk        (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff)                 */
37169 
37170 /* =========================================================================================================================== */
37171 /* ================                                           R_DTC                                           ================ */
37172 /* =========================================================================================================================== */
37173 
37174 /* =========================================================  DTCCR  ========================================================= */
37175  #define R_DTC_DTCCR_RRS_Pos         (4UL)          /*!< RRS (Bit 4)                                           */
37176  #define R_DTC_DTCCR_RRS_Msk         (0x10UL)       /*!< RRS (Bitfield-Mask: 0x01)                             */
37177 /* ========================================================  DTCVBR  ========================================================= */
37178  #define R_DTC_DTCVBR_DTCVBR_Pos     (0UL)          /*!< DTCVBR (Bit 0)                                        */
37179  #define R_DTC_DTCVBR_DTCVBR_Msk     (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff)                    */
37180 /* =========================================================  DTCST  ========================================================= */
37181  #define R_DTC_DTCST_DTCST_Pos       (0UL)          /*!< DTCST (Bit 0)                                         */
37182  #define R_DTC_DTCST_DTCST_Msk       (0x1UL)        /*!< DTCST (Bitfield-Mask: 0x01)                           */
37183 /* ========================================================  DTCSTS  ========================================================= */
37184  #define R_DTC_DTCSTS_ACT_Pos        (15UL)         /*!< ACT (Bit 15)                                          */
37185  #define R_DTC_DTCSTS_ACT_Msk        (0x8000UL)     /*!< ACT (Bitfield-Mask: 0x01)                             */
37186  #define R_DTC_DTCSTS_VECN_Pos       (0UL)          /*!< VECN (Bit 0)                                          */
37187  #define R_DTC_DTCSTS_VECN_Msk       (0xffUL)       /*!< VECN (Bitfield-Mask: 0xff)                            */
37188 /* =======================================================  DTCCR_SEC  ======================================================= */
37189  #define R_DTC_DTCCR_SEC_RRSS_Pos    (4UL)          /*!< RRSS (Bit 4)                                          */
37190  #define R_DTC_DTCCR_SEC_RRSS_Msk    (0x10UL)       /*!< RRSS (Bitfield-Mask: 0x01)                            */
37191 /* ======================================================  DTCVBR_SEC  ======================================================= */
37192 /* =========================================================  DTEVR  ========================================================= */
37193  #define R_DTC_DTEVR_DTEV_Pos        (0UL)          /*!< DTEV (Bit 0)                                          */
37194  #define R_DTC_DTEVR_DTEV_Msk        (0xffUL)       /*!< DTEV (Bitfield-Mask: 0xff)                            */
37195  #define R_DTC_DTEVR_DTEVSAM_Pos     (8UL)          /*!< DTEVSAM (Bit 8)                                       */
37196  #define R_DTC_DTEVR_DTEVSAM_Msk     (0x100UL)      /*!< DTEVSAM (Bitfield-Mask: 0x01)                         */
37197  #define R_DTC_DTEVR_DTESTA_Pos      (16UL)         /*!< DTESTA (Bit 16)                                       */
37198  #define R_DTC_DTEVR_DTESTA_Msk      (0x10000UL)    /*!< DTESTA (Bitfield-Mask: 0x01)                          */
37199 
37200 /* =========================================================================================================================== */
37201 /* ================                                           R_ELC                                           ================ */
37202 /* =========================================================================================================================== */
37203 
37204 /* =========================================================  ELCR  ========================================================== */
37205  #define R_ELC_ELCR_ELCON_Pos         (7UL)      /*!< ELCON (Bit 7)                                         */
37206  #define R_ELC_ELCR_ELCON_Msk         (0x80UL)   /*!< ELCON (Bitfield-Mask: 0x01)                           */
37207 /* ========================================================  ELCSARA  ======================================================== */
37208  #define R_ELC_ELCSARA_ELCR_Pos       (0UL)      /*!< ELCR (Bit 0)                                          */
37209  #define R_ELC_ELCSARA_ELCR_Msk       (0x1UL)    /*!< ELCR (Bitfield-Mask: 0x01)                            */
37210  #define R_ELC_ELCSARA_ELSEGR0_Pos    (1UL)      /*!< ELSEGR0 (Bit 1)                                       */
37211  #define R_ELC_ELCSARA_ELSEGR0_Msk    (0x2UL)    /*!< ELSEGR0 (Bitfield-Mask: 0x01)                         */
37212  #define R_ELC_ELCSARA_ELSEGR1_Pos    (2UL)      /*!< ELSEGR1 (Bit 2)                                       */
37213  #define R_ELC_ELCSARA_ELSEGR1_Msk    (0x4UL)    /*!< ELSEGR1 (Bitfield-Mask: 0x01)                         */
37214 /* ========================================================  ELCSARB  ======================================================== */
37215  #define R_ELC_ELCSARB_ELSR0_Pos      (0UL)      /*!< ELSR0 (Bit 0)                                         */
37216  #define R_ELC_ELCSARB_ELSR0_Msk      (0x1UL)    /*!< ELSR0 (Bitfield-Mask: 0x01)                           */
37217  #define R_ELC_ELCSARB_ELSR1_Pos      (1UL)      /*!< ELSR1 (Bit 1)                                         */
37218  #define R_ELC_ELCSARB_ELSR1_Msk      (0x2UL)    /*!< ELSR1 (Bitfield-Mask: 0x01)                           */
37219  #define R_ELC_ELCSARB_ELSR2_Pos      (2UL)      /*!< ELSR2 (Bit 2)                                         */
37220  #define R_ELC_ELCSARB_ELSR2_Msk      (0x4UL)    /*!< ELSR2 (Bitfield-Mask: 0x01)                           */
37221  #define R_ELC_ELCSARB_ELSR3_Pos      (3UL)      /*!< ELSR3 (Bit 3)                                         */
37222  #define R_ELC_ELCSARB_ELSR3_Msk      (0x8UL)    /*!< ELSR3 (Bitfield-Mask: 0x01)                           */
37223  #define R_ELC_ELCSARB_ELSR4_Pos      (4UL)      /*!< ELSR4 (Bit 4)                                         */
37224  #define R_ELC_ELCSARB_ELSR4_Msk      (0x10UL)   /*!< ELSR4 (Bitfield-Mask: 0x01)                           */
37225  #define R_ELC_ELCSARB_ELSR5_Pos      (5UL)      /*!< ELSR5 (Bit 5)                                         */
37226  #define R_ELC_ELCSARB_ELSR5_Msk      (0x20UL)   /*!< ELSR5 (Bitfield-Mask: 0x01)                           */
37227  #define R_ELC_ELCSARB_ELSR6_Pos      (6UL)      /*!< ELSR6 (Bit 6)                                         */
37228  #define R_ELC_ELCSARB_ELSR6_Msk      (0x40UL)   /*!< ELSR6 (Bitfield-Mask: 0x01)                           */
37229  #define R_ELC_ELCSARB_ELSR7_Pos      (7UL)      /*!< ELSR7 (Bit 7)                                         */
37230  #define R_ELC_ELCSARB_ELSR7_Msk      (0x80UL)   /*!< ELSR7 (Bitfield-Mask: 0x01)                           */
37231  #define R_ELC_ELCSARB_ELSR8_Pos      (8UL)      /*!< ELSR8 (Bit 8)                                         */
37232  #define R_ELC_ELCSARB_ELSR8_Msk      (0x100UL)  /*!< ELSR8 (Bitfield-Mask: 0x01)                           */
37233  #define R_ELC_ELCSARB_ELSR9_Pos      (9UL)      /*!< ELSR9 (Bit 9)                                         */
37234  #define R_ELC_ELCSARB_ELSR9_Msk      (0x200UL)  /*!< ELSR9 (Bitfield-Mask: 0x01)                           */
37235  #define R_ELC_ELCSARB_ELSR10_Pos     (10UL)     /*!< ELSR10 (Bit 10)                                       */
37236  #define R_ELC_ELCSARB_ELSR10_Msk     (0x400UL)  /*!< ELSR10 (Bitfield-Mask: 0x01)                          */
37237  #define R_ELC_ELCSARB_ELSR11_Pos     (11UL)     /*!< ELSR11 (Bit 11)                                       */
37238  #define R_ELC_ELCSARB_ELSR11_Msk     (0x800UL)  /*!< ELSR11 (Bitfield-Mask: 0x01)                          */
37239  #define R_ELC_ELCSARB_ELSR12_Pos     (12UL)     /*!< ELSR12 (Bit 12)                                       */
37240  #define R_ELC_ELCSARB_ELSR12_Msk     (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01)                          */
37241  #define R_ELC_ELCSARB_ELSR13_Pos     (13UL)     /*!< ELSR13 (Bit 13)                                       */
37242  #define R_ELC_ELCSARB_ELSR13_Msk     (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01)                          */
37243  #define R_ELC_ELCSARB_ELSR14_Pos     (14UL)     /*!< ELSR14 (Bit 14)                                       */
37244  #define R_ELC_ELCSARB_ELSR14_Msk     (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01)                          */
37245  #define R_ELC_ELCSARB_ELSR15_Pos     (15UL)     /*!< ELSR15 (Bit 15)                                       */
37246  #define R_ELC_ELCSARB_ELSR15_Msk     (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01)                          */
37247 /* ========================================================  ELCSARC  ======================================================== */
37248  #define R_ELC_ELCSARC_ELSR16_Pos     (0UL)      /*!< ELSR16 (Bit 0)                                        */
37249  #define R_ELC_ELCSARC_ELSR16_Msk     (0x1UL)    /*!< ELSR16 (Bitfield-Mask: 0x01)                          */
37250  #define R_ELC_ELCSARC_ELSR17_Pos     (1UL)      /*!< ELSR17 (Bit 1)                                        */
37251  #define R_ELC_ELCSARC_ELSR17_Msk     (0x2UL)    /*!< ELSR17 (Bitfield-Mask: 0x01)                          */
37252  #define R_ELC_ELCSARC_ELSR18_Pos     (2UL)      /*!< ELSR18 (Bit 2)                                        */
37253  #define R_ELC_ELCSARC_ELSR18_Msk     (0x4UL)    /*!< ELSR18 (Bitfield-Mask: 0x01)                          */
37254 
37255 /* =========================================================================================================================== */
37256 /* ================                                         R_ETHERC0                                         ================ */
37257 /* =========================================================================================================================== */
37258 
37259 /* =========================================================  ECMR  ========================================================== */
37260  #define R_ETHERC0_ECMR_TPC_Pos          (20UL)         /*!< TPC (Bit 20)                                          */
37261  #define R_ETHERC0_ECMR_TPC_Msk          (0x100000UL)   /*!< TPC (Bitfield-Mask: 0x01)                             */
37262  #define R_ETHERC0_ECMR_ZPF_Pos          (19UL)         /*!< ZPF (Bit 19)                                          */
37263  #define R_ETHERC0_ECMR_ZPF_Msk          (0x80000UL)    /*!< ZPF (Bitfield-Mask: 0x01)                             */
37264  #define R_ETHERC0_ECMR_PFR_Pos          (18UL)         /*!< PFR (Bit 18)                                          */
37265  #define R_ETHERC0_ECMR_PFR_Msk          (0x40000UL)    /*!< PFR (Bitfield-Mask: 0x01)                             */
37266  #define R_ETHERC0_ECMR_RXF_Pos          (17UL)         /*!< RXF (Bit 17)                                          */
37267  #define R_ETHERC0_ECMR_RXF_Msk          (0x20000UL)    /*!< RXF (Bitfield-Mask: 0x01)                             */
37268  #define R_ETHERC0_ECMR_TXF_Pos          (16UL)         /*!< TXF (Bit 16)                                          */
37269  #define R_ETHERC0_ECMR_TXF_Msk          (0x10000UL)    /*!< TXF (Bitfield-Mask: 0x01)                             */
37270  #define R_ETHERC0_ECMR_PRCEF_Pos        (12UL)         /*!< PRCEF (Bit 12)                                        */
37271  #define R_ETHERC0_ECMR_PRCEF_Msk        (0x1000UL)     /*!< PRCEF (Bitfield-Mask: 0x01)                           */
37272  #define R_ETHERC0_ECMR_MPDE_Pos         (9UL)          /*!< MPDE (Bit 9)                                          */
37273  #define R_ETHERC0_ECMR_MPDE_Msk         (0x200UL)      /*!< MPDE (Bitfield-Mask: 0x01)                            */
37274  #define R_ETHERC0_ECMR_RE_Pos           (6UL)          /*!< RE (Bit 6)                                            */
37275  #define R_ETHERC0_ECMR_RE_Msk           (0x40UL)       /*!< RE (Bitfield-Mask: 0x01)                              */
37276  #define R_ETHERC0_ECMR_TE_Pos           (5UL)          /*!< TE (Bit 5)                                            */
37277  #define R_ETHERC0_ECMR_TE_Msk           (0x20UL)       /*!< TE (Bitfield-Mask: 0x01)                              */
37278  #define R_ETHERC0_ECMR_ILB_Pos          (3UL)          /*!< ILB (Bit 3)                                           */
37279  #define R_ETHERC0_ECMR_ILB_Msk          (0x8UL)        /*!< ILB (Bitfield-Mask: 0x01)                             */
37280  #define R_ETHERC0_ECMR_RTM_Pos          (2UL)          /*!< RTM (Bit 2)                                           */
37281  #define R_ETHERC0_ECMR_RTM_Msk          (0x4UL)        /*!< RTM (Bitfield-Mask: 0x01)                             */
37282  #define R_ETHERC0_ECMR_DM_Pos           (1UL)          /*!< DM (Bit 1)                                            */
37283  #define R_ETHERC0_ECMR_DM_Msk           (0x2UL)        /*!< DM (Bitfield-Mask: 0x01)                              */
37284  #define R_ETHERC0_ECMR_PRM_Pos          (0UL)          /*!< PRM (Bit 0)                                           */
37285  #define R_ETHERC0_ECMR_PRM_Msk          (0x1UL)        /*!< PRM (Bitfield-Mask: 0x01)                             */
37286 /* =========================================================  RFLR  ========================================================== */
37287  #define R_ETHERC0_RFLR_RFL_Pos          (0UL)          /*!< RFL (Bit 0)                                           */
37288  #define R_ETHERC0_RFLR_RFL_Msk          (0xfffUL)      /*!< RFL (Bitfield-Mask: 0xfff)                            */
37289 /* =========================================================  ECSR  ========================================================== */
37290  #define R_ETHERC0_ECSR_BFR_Pos          (5UL)          /*!< BFR (Bit 5)                                           */
37291  #define R_ETHERC0_ECSR_BFR_Msk          (0x20UL)       /*!< BFR (Bitfield-Mask: 0x01)                             */
37292  #define R_ETHERC0_ECSR_PSRTO_Pos        (4UL)          /*!< PSRTO (Bit 4)                                         */
37293  #define R_ETHERC0_ECSR_PSRTO_Msk        (0x10UL)       /*!< PSRTO (Bitfield-Mask: 0x01)                           */
37294  #define R_ETHERC0_ECSR_LCHNG_Pos        (2UL)          /*!< LCHNG (Bit 2)                                         */
37295  #define R_ETHERC0_ECSR_LCHNG_Msk        (0x4UL)        /*!< LCHNG (Bitfield-Mask: 0x01)                           */
37296  #define R_ETHERC0_ECSR_MPD_Pos          (1UL)          /*!< MPD (Bit 1)                                           */
37297  #define R_ETHERC0_ECSR_MPD_Msk          (0x2UL)        /*!< MPD (Bitfield-Mask: 0x01)                             */
37298  #define R_ETHERC0_ECSR_ICD_Pos          (0UL)          /*!< ICD (Bit 0)                                           */
37299  #define R_ETHERC0_ECSR_ICD_Msk          (0x1UL)        /*!< ICD (Bitfield-Mask: 0x01)                             */
37300 /* ========================================================  ECSIPR  ========================================================= */
37301  #define R_ETHERC0_ECSIPR_BFSIPR_Pos     (5UL)          /*!< BFSIPR (Bit 5)                                        */
37302  #define R_ETHERC0_ECSIPR_BFSIPR_Msk     (0x20UL)       /*!< BFSIPR (Bitfield-Mask: 0x01)                          */
37303  #define R_ETHERC0_ECSIPR_PSRTOIP_Pos    (4UL)          /*!< PSRTOIP (Bit 4)                                       */
37304  #define R_ETHERC0_ECSIPR_PSRTOIP_Msk    (0x10UL)       /*!< PSRTOIP (Bitfield-Mask: 0x01)                         */
37305  #define R_ETHERC0_ECSIPR_LCHNGIP_Pos    (2UL)          /*!< LCHNGIP (Bit 2)                                       */
37306  #define R_ETHERC0_ECSIPR_LCHNGIP_Msk    (0x4UL)        /*!< LCHNGIP (Bitfield-Mask: 0x01)                         */
37307  #define R_ETHERC0_ECSIPR_MPDIP_Pos      (1UL)          /*!< MPDIP (Bit 1)                                         */
37308  #define R_ETHERC0_ECSIPR_MPDIP_Msk      (0x2UL)        /*!< MPDIP (Bitfield-Mask: 0x01)                           */
37309  #define R_ETHERC0_ECSIPR_ICDIP_Pos      (0UL)          /*!< ICDIP (Bit 0)                                         */
37310  #define R_ETHERC0_ECSIPR_ICDIP_Msk      (0x1UL)        /*!< ICDIP (Bitfield-Mask: 0x01)                           */
37311 /* ==========================================================  PIR  ========================================================== */
37312  #define R_ETHERC0_PIR_MDI_Pos           (3UL)          /*!< MDI (Bit 3)                                           */
37313  #define R_ETHERC0_PIR_MDI_Msk           (0x8UL)        /*!< MDI (Bitfield-Mask: 0x01)                             */
37314  #define R_ETHERC0_PIR_MDO_Pos           (2UL)          /*!< MDO (Bit 2)                                           */
37315  #define R_ETHERC0_PIR_MDO_Msk           (0x4UL)        /*!< MDO (Bitfield-Mask: 0x01)                             */
37316  #define R_ETHERC0_PIR_MMD_Pos           (1UL)          /*!< MMD (Bit 1)                                           */
37317  #define R_ETHERC0_PIR_MMD_Msk           (0x2UL)        /*!< MMD (Bitfield-Mask: 0x01)                             */
37318  #define R_ETHERC0_PIR_MDC_Pos           (0UL)          /*!< MDC (Bit 0)                                           */
37319  #define R_ETHERC0_PIR_MDC_Msk           (0x1UL)        /*!< MDC (Bitfield-Mask: 0x01)                             */
37320 /* ==========================================================  PSR  ========================================================== */
37321  #define R_ETHERC0_PSR_LMON_Pos          (0UL)          /*!< LMON (Bit 0)                                          */
37322  #define R_ETHERC0_PSR_LMON_Msk          (0x1UL)        /*!< LMON (Bitfield-Mask: 0x01)                            */
37323 /* =========================================================  RDMLR  ========================================================= */
37324  #define R_ETHERC0_RDMLR_RMD_Pos         (0UL)          /*!< RMD (Bit 0)                                           */
37325  #define R_ETHERC0_RDMLR_RMD_Msk         (0xfffffUL)    /*!< RMD (Bitfield-Mask: 0xfffff)                          */
37326 /* =========================================================  IPGR  ========================================================== */
37327  #define R_ETHERC0_IPGR_IPG_Pos          (0UL)          /*!< IPG (Bit 0)                                           */
37328  #define R_ETHERC0_IPGR_IPG_Msk          (0x1fUL)       /*!< IPG (Bitfield-Mask: 0x1f)                             */
37329 /* ==========================================================  APR  ========================================================== */
37330  #define R_ETHERC0_APR_AP_Pos            (0UL)          /*!< AP (Bit 0)                                            */
37331  #define R_ETHERC0_APR_AP_Msk            (0xffffUL)     /*!< AP (Bitfield-Mask: 0xffff)                            */
37332 /* ==========================================================  MPR  ========================================================== */
37333  #define R_ETHERC0_MPR_MP_Pos            (0UL)          /*!< MP (Bit 0)                                            */
37334  #define R_ETHERC0_MPR_MP_Msk            (0xffffUL)     /*!< MP (Bitfield-Mask: 0xffff)                            */
37335 /* =========================================================  RFCF  ========================================================== */
37336  #define R_ETHERC0_RFCF_RPAUSE_Pos       (0UL)          /*!< RPAUSE (Bit 0)                                        */
37337  #define R_ETHERC0_RFCF_RPAUSE_Msk       (0xffUL)       /*!< RPAUSE (Bitfield-Mask: 0xff)                          */
37338 /* ========================================================  TPAUSER  ======================================================== */
37339  #define R_ETHERC0_TPAUSER_TPAUSE_Pos    (0UL)          /*!< TPAUSE (Bit 0)                                        */
37340  #define R_ETHERC0_TPAUSER_TPAUSE_Msk    (0xffffUL)     /*!< TPAUSE (Bitfield-Mask: 0xffff)                        */
37341 /* =======================================================  TPAUSECR  ======================================================== */
37342 /* =========================================================  BCFRR  ========================================================= */
37343  #define R_ETHERC0_BCFRR_BCF_Pos         (0UL)          /*!< BCF (Bit 0)                                           */
37344  #define R_ETHERC0_BCFRR_BCF_Msk         (0xffffUL)     /*!< BCF (Bitfield-Mask: 0xffff)                           */
37345 /* =========================================================  MAHR  ========================================================== */
37346  #define R_ETHERC0_MAHR_MAHR_Pos         (0UL)          /*!< MAHR (Bit 0)                                          */
37347  #define R_ETHERC0_MAHR_MAHR_Msk         (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff)                      */
37348 /* =========================================================  MALR  ========================================================== */
37349  #define R_ETHERC0_MALR_MALR_Pos         (0UL)          /*!< MALR (Bit 0)                                          */
37350  #define R_ETHERC0_MALR_MALR_Msk         (0xffffUL)     /*!< MALR (Bitfield-Mask: 0xffff)                          */
37351 /* =========================================================  TROCR  ========================================================= */
37352  #define R_ETHERC0_TROCR_TROCR_Pos       (0UL)          /*!< TROCR (Bit 0)                                         */
37353  #define R_ETHERC0_TROCR_TROCR_Msk       (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff)                     */
37354 /* =========================================================  CDCR  ========================================================== */
37355 /* =========================================================  LCCR  ========================================================== */
37356  #define R_ETHERC0_LCCR_LCCR_Pos         (0UL)          /*!< LCCR (Bit 0)                                          */
37357  #define R_ETHERC0_LCCR_LCCR_Msk         (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff)                      */
37358 /* =========================================================  CNDCR  ========================================================= */
37359  #define R_ETHERC0_CNDCR_CNDCR_Pos       (0UL)          /*!< CNDCR (Bit 0)                                         */
37360  #define R_ETHERC0_CNDCR_CNDCR_Msk       (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff)                     */
37361 /* =========================================================  CEFCR  ========================================================= */
37362  #define R_ETHERC0_CEFCR_CEFCR_Pos       (0UL)          /*!< CEFCR (Bit 0)                                         */
37363  #define R_ETHERC0_CEFCR_CEFCR_Msk       (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff)                     */
37364 /* =========================================================  FRECR  ========================================================= */
37365  #define R_ETHERC0_FRECR_FRECR_Pos       (0UL)          /*!< FRECR (Bit 0)                                         */
37366  #define R_ETHERC0_FRECR_FRECR_Msk       (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff)                     */
37367 /* ========================================================  TSFRCR  ========================================================= */
37368  #define R_ETHERC0_TSFRCR_TSFRCR_Pos     (0UL)          /*!< TSFRCR (Bit 0)                                        */
37369  #define R_ETHERC0_TSFRCR_TSFRCR_Msk     (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff)                    */
37370 /* ========================================================  TLFRCR  ========================================================= */
37371  #define R_ETHERC0_TLFRCR_TLFRCR_Pos     (0UL)          /*!< TLFRCR (Bit 0)                                        */
37372  #define R_ETHERC0_TLFRCR_TLFRCR_Msk     (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff)                    */
37373 /* =========================================================  RFCR  ========================================================== */
37374  #define R_ETHERC0_RFCR_RFCR_Pos         (0UL)          /*!< RFCR (Bit 0)                                          */
37375  #define R_ETHERC0_RFCR_RFCR_Msk         (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff)                      */
37376 /* =========================================================  MAFCR  ========================================================= */
37377  #define R_ETHERC0_MAFCR_MAFCR_Pos       (0UL)          /*!< MAFCR (Bit 0)                                         */
37378  #define R_ETHERC0_MAFCR_MAFCR_Msk       (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff)                     */
37379 
37380 /* =========================================================================================================================== */
37381 /* ================                                      R_ETHERC_EDMAC                                       ================ */
37382 /* =========================================================================================================================== */
37383 
37384 /* =========================================================  EDMR  ========================================================== */
37385  #define R_ETHERC_EDMAC_EDMR_DE_Pos           (6UL)          /*!< DE (Bit 6)                                            */
37386  #define R_ETHERC_EDMAC_EDMR_DE_Msk           (0x40UL)       /*!< DE (Bitfield-Mask: 0x01)                              */
37387  #define R_ETHERC_EDMAC_EDMR_DL_Pos           (4UL)          /*!< DL (Bit 4)                                            */
37388  #define R_ETHERC_EDMAC_EDMR_DL_Msk           (0x30UL)       /*!< DL (Bitfield-Mask: 0x03)                              */
37389  #define R_ETHERC_EDMAC_EDMR_SWR_Pos          (0UL)          /*!< SWR (Bit 0)                                           */
37390  #define R_ETHERC_EDMAC_EDMR_SWR_Msk          (0x1UL)        /*!< SWR (Bitfield-Mask: 0x01)                             */
37391 /* =========================================================  EDTRR  ========================================================= */
37392  #define R_ETHERC_EDMAC_EDTRR_TR_Pos          (0UL)          /*!< TR (Bit 0)                                            */
37393  #define R_ETHERC_EDMAC_EDTRR_TR_Msk          (0x1UL)        /*!< TR (Bitfield-Mask: 0x01)                              */
37394 /* =========================================================  EDRRR  ========================================================= */
37395  #define R_ETHERC_EDMAC_EDRRR_RR_Pos          (0UL)          /*!< RR (Bit 0)                                            */
37396  #define R_ETHERC_EDMAC_EDRRR_RR_Msk          (0x1UL)        /*!< RR (Bitfield-Mask: 0x01)                              */
37397 /* =========================================================  TDLAR  ========================================================= */
37398  #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos       (0UL)          /*!< TDLAR (Bit 0)                                         */
37399  #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk       (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff)                     */
37400 /* =========================================================  RDLAR  ========================================================= */
37401  #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos       (0UL)          /*!< RDLAR (Bit 0)                                         */
37402  #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk       (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff)                     */
37403 /* =========================================================  EESR  ========================================================== */
37404  #define R_ETHERC_EDMAC_EESR_TWB_Pos          (30UL)         /*!< TWB (Bit 30)                                          */
37405  #define R_ETHERC_EDMAC_EESR_TWB_Msk          (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01)                             */
37406  #define R_ETHERC_EDMAC_EESR_TABT_Pos         (26UL)         /*!< TABT (Bit 26)                                         */
37407  #define R_ETHERC_EDMAC_EESR_TABT_Msk         (0x4000000UL)  /*!< TABT (Bitfield-Mask: 0x01)                            */
37408  #define R_ETHERC_EDMAC_EESR_RABT_Pos         (25UL)         /*!< RABT (Bit 25)                                         */
37409  #define R_ETHERC_EDMAC_EESR_RABT_Msk         (0x2000000UL)  /*!< RABT (Bitfield-Mask: 0x01)                            */
37410  #define R_ETHERC_EDMAC_EESR_RFCOF_Pos        (24UL)         /*!< RFCOF (Bit 24)                                        */
37411  #define R_ETHERC_EDMAC_EESR_RFCOF_Msk        (0x1000000UL)  /*!< RFCOF (Bitfield-Mask: 0x01)                           */
37412  #define R_ETHERC_EDMAC_EESR_ADE_Pos          (23UL)         /*!< ADE (Bit 23)                                          */
37413  #define R_ETHERC_EDMAC_EESR_ADE_Msk          (0x800000UL)   /*!< ADE (Bitfield-Mask: 0x01)                             */
37414  #define R_ETHERC_EDMAC_EESR_ECI_Pos          (22UL)         /*!< ECI (Bit 22)                                          */
37415  #define R_ETHERC_EDMAC_EESR_ECI_Msk          (0x400000UL)   /*!< ECI (Bitfield-Mask: 0x01)                             */
37416  #define R_ETHERC_EDMAC_EESR_TC_Pos           (21UL)         /*!< TC (Bit 21)                                           */
37417  #define R_ETHERC_EDMAC_EESR_TC_Msk           (0x200000UL)   /*!< TC (Bitfield-Mask: 0x01)                              */
37418  #define R_ETHERC_EDMAC_EESR_TDE_Pos          (20UL)         /*!< TDE (Bit 20)                                          */
37419  #define R_ETHERC_EDMAC_EESR_TDE_Msk          (0x100000UL)   /*!< TDE (Bitfield-Mask: 0x01)                             */
37420  #define R_ETHERC_EDMAC_EESR_TFUF_Pos         (19UL)         /*!< TFUF (Bit 19)                                         */
37421  #define R_ETHERC_EDMAC_EESR_TFUF_Msk         (0x80000UL)    /*!< TFUF (Bitfield-Mask: 0x01)                            */
37422  #define R_ETHERC_EDMAC_EESR_FR_Pos           (18UL)         /*!< FR (Bit 18)                                           */
37423  #define R_ETHERC_EDMAC_EESR_FR_Msk           (0x40000UL)    /*!< FR (Bitfield-Mask: 0x01)                              */
37424  #define R_ETHERC_EDMAC_EESR_RDE_Pos          (17UL)         /*!< RDE (Bit 17)                                          */
37425  #define R_ETHERC_EDMAC_EESR_RDE_Msk          (0x20000UL)    /*!< RDE (Bitfield-Mask: 0x01)                             */
37426  #define R_ETHERC_EDMAC_EESR_RFOF_Pos         (16UL)         /*!< RFOF (Bit 16)                                         */
37427  #define R_ETHERC_EDMAC_EESR_RFOF_Msk         (0x10000UL)    /*!< RFOF (Bitfield-Mask: 0x01)                            */
37428  #define R_ETHERC_EDMAC_EESR_CND_Pos          (11UL)         /*!< CND (Bit 11)                                          */
37429  #define R_ETHERC_EDMAC_EESR_CND_Msk          (0x800UL)      /*!< CND (Bitfield-Mask: 0x01)                             */
37430  #define R_ETHERC_EDMAC_EESR_DLC_Pos          (10UL)         /*!< DLC (Bit 10)                                          */
37431  #define R_ETHERC_EDMAC_EESR_DLC_Msk          (0x400UL)      /*!< DLC (Bitfield-Mask: 0x01)                             */
37432  #define R_ETHERC_EDMAC_EESR_CD_Pos           (9UL)          /*!< CD (Bit 9)                                            */
37433  #define R_ETHERC_EDMAC_EESR_CD_Msk           (0x200UL)      /*!< CD (Bitfield-Mask: 0x01)                              */
37434  #define R_ETHERC_EDMAC_EESR_TRO_Pos          (8UL)          /*!< TRO (Bit 8)                                           */
37435  #define R_ETHERC_EDMAC_EESR_TRO_Msk          (0x100UL)      /*!< TRO (Bitfield-Mask: 0x01)                             */
37436  #define R_ETHERC_EDMAC_EESR_RMAF_Pos         (7UL)          /*!< RMAF (Bit 7)                                          */
37437  #define R_ETHERC_EDMAC_EESR_RMAF_Msk         (0x80UL)       /*!< RMAF (Bitfield-Mask: 0x01)                            */
37438  #define R_ETHERC_EDMAC_EESR_RRF_Pos          (4UL)          /*!< RRF (Bit 4)                                           */
37439  #define R_ETHERC_EDMAC_EESR_RRF_Msk          (0x10UL)       /*!< RRF (Bitfield-Mask: 0x01)                             */
37440  #define R_ETHERC_EDMAC_EESR_RTLF_Pos         (3UL)          /*!< RTLF (Bit 3)                                          */
37441  #define R_ETHERC_EDMAC_EESR_RTLF_Msk         (0x8UL)        /*!< RTLF (Bitfield-Mask: 0x01)                            */
37442  #define R_ETHERC_EDMAC_EESR_RTSF_Pos         (2UL)          /*!< RTSF (Bit 2)                                          */
37443  #define R_ETHERC_EDMAC_EESR_RTSF_Msk         (0x4UL)        /*!< RTSF (Bitfield-Mask: 0x01)                            */
37444  #define R_ETHERC_EDMAC_EESR_PRE_Pos          (1UL)          /*!< PRE (Bit 1)                                           */
37445  #define R_ETHERC_EDMAC_EESR_PRE_Msk          (0x2UL)        /*!< PRE (Bitfield-Mask: 0x01)                             */
37446  #define R_ETHERC_EDMAC_EESR_CERF_Pos         (0UL)          /*!< CERF (Bit 0)                                          */
37447  #define R_ETHERC_EDMAC_EESR_CERF_Msk         (0x1UL)        /*!< CERF (Bitfield-Mask: 0x01)                            */
37448 /* ========================================================  EESIPR  ========================================================= */
37449  #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos      (30UL)         /*!< TWBIP (Bit 30)                                        */
37450  #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk      (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01)                           */
37451  #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos     (26UL)         /*!< TABTIP (Bit 26)                                       */
37452  #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk     (0x4000000UL)  /*!< TABTIP (Bitfield-Mask: 0x01)                          */
37453  #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos     (25UL)         /*!< RABTIP (Bit 25)                                       */
37454  #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk     (0x2000000UL)  /*!< RABTIP (Bitfield-Mask: 0x01)                          */
37455  #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos    (24UL)         /*!< RFCOFIP (Bit 24)                                      */
37456  #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk    (0x1000000UL)  /*!< RFCOFIP (Bitfield-Mask: 0x01)                         */
37457  #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos      (23UL)         /*!< ADEIP (Bit 23)                                        */
37458  #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk      (0x800000UL)   /*!< ADEIP (Bitfield-Mask: 0x01)                           */
37459  #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos      (22UL)         /*!< ECIIP (Bit 22)                                        */
37460  #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk      (0x400000UL)   /*!< ECIIP (Bitfield-Mask: 0x01)                           */
37461  #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos       (21UL)         /*!< TCIP (Bit 21)                                         */
37462  #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk       (0x200000UL)   /*!< TCIP (Bitfield-Mask: 0x01)                            */
37463  #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos      (20UL)         /*!< TDEIP (Bit 20)                                        */
37464  #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk      (0x100000UL)   /*!< TDEIP (Bitfield-Mask: 0x01)                           */
37465  #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos     (19UL)         /*!< TFUFIP (Bit 19)                                       */
37466  #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk     (0x80000UL)    /*!< TFUFIP (Bitfield-Mask: 0x01)                          */
37467  #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos       (18UL)         /*!< FRIP (Bit 18)                                         */
37468  #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk       (0x40000UL)    /*!< FRIP (Bitfield-Mask: 0x01)                            */
37469  #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos      (17UL)         /*!< RDEIP (Bit 17)                                        */
37470  #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk      (0x20000UL)    /*!< RDEIP (Bitfield-Mask: 0x01)                           */
37471  #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos     (16UL)         /*!< RFOFIP (Bit 16)                                       */
37472  #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk     (0x10000UL)    /*!< RFOFIP (Bitfield-Mask: 0x01)                          */
37473  #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos      (11UL)         /*!< CNDIP (Bit 11)                                        */
37474  #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk      (0x800UL)      /*!< CNDIP (Bitfield-Mask: 0x01)                           */
37475  #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos      (10UL)         /*!< DLCIP (Bit 10)                                        */
37476  #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk      (0x400UL)      /*!< DLCIP (Bitfield-Mask: 0x01)                           */
37477  #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos       (9UL)          /*!< CDIP (Bit 9)                                          */
37478  #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk       (0x200UL)      /*!< CDIP (Bitfield-Mask: 0x01)                            */
37479  #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos      (8UL)          /*!< TROIP (Bit 8)                                         */
37480  #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk      (0x100UL)      /*!< TROIP (Bitfield-Mask: 0x01)                           */
37481  #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos     (7UL)          /*!< RMAFIP (Bit 7)                                        */
37482  #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk     (0x80UL)       /*!< RMAFIP (Bitfield-Mask: 0x01)                          */
37483  #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos      (4UL)          /*!< RRFIP (Bit 4)                                         */
37484  #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk      (0x10UL)       /*!< RRFIP (Bitfield-Mask: 0x01)                           */
37485  #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos     (3UL)          /*!< RTLFIP (Bit 3)                                        */
37486  #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk     (0x8UL)        /*!< RTLFIP (Bitfield-Mask: 0x01)                          */
37487  #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos     (2UL)          /*!< RTSFIP (Bit 2)                                        */
37488  #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk     (0x4UL)        /*!< RTSFIP (Bitfield-Mask: 0x01)                          */
37489  #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos      (1UL)          /*!< PREIP (Bit 1)                                         */
37490  #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk      (0x2UL)        /*!< PREIP (Bitfield-Mask: 0x01)                           */
37491  #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos     (0UL)          /*!< CERFIP (Bit 0)                                        */
37492  #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk     (0x1UL)        /*!< CERFIP (Bitfield-Mask: 0x01)                          */
37493 /* ========================================================  TRSCER  ========================================================= */
37494  #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos     (7UL)          /*!< RMAFCE (Bit 7)                                        */
37495  #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk     (0x80UL)       /*!< RMAFCE (Bitfield-Mask: 0x01)                          */
37496  #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos      (4UL)          /*!< RRFCE (Bit 4)                                         */
37497  #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk      (0x10UL)       /*!< RRFCE (Bitfield-Mask: 0x01)                           */
37498 /* =========================================================  RMFCR  ========================================================= */
37499  #define R_ETHERC_EDMAC_RMFCR_MFC_Pos         (0UL)          /*!< MFC (Bit 0)                                           */
37500  #define R_ETHERC_EDMAC_RMFCR_MFC_Msk         (0xffffUL)     /*!< MFC (Bitfield-Mask: 0xffff)                           */
37501 /* =========================================================  TFTR  ========================================================== */
37502  #define R_ETHERC_EDMAC_TFTR_TFT_Pos          (0UL)          /*!< TFT (Bit 0)                                           */
37503  #define R_ETHERC_EDMAC_TFTR_TFT_Msk          (0x7ffUL)      /*!< TFT (Bitfield-Mask: 0x7ff)                            */
37504 /* ==========================================================  FDR  ========================================================== */
37505  #define R_ETHERC_EDMAC_FDR_TFD_Pos           (8UL)          /*!< TFD (Bit 8)                                           */
37506  #define R_ETHERC_EDMAC_FDR_TFD_Msk           (0x1f00UL)     /*!< TFD (Bitfield-Mask: 0x1f)                             */
37507  #define R_ETHERC_EDMAC_FDR_RFD_Pos           (0UL)          /*!< RFD (Bit 0)                                           */
37508  #define R_ETHERC_EDMAC_FDR_RFD_Msk           (0x1fUL)       /*!< RFD (Bitfield-Mask: 0x1f)                             */
37509 /* =========================================================  RMCR  ========================================================== */
37510  #define R_ETHERC_EDMAC_RMCR_RNR_Pos          (0UL)          /*!< RNR (Bit 0)                                           */
37511  #define R_ETHERC_EDMAC_RMCR_RNR_Msk          (0x1UL)        /*!< RNR (Bitfield-Mask: 0x01)                             */
37512 /* =========================================================  TFUCR  ========================================================= */
37513  #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos       (0UL)          /*!< UNDER (Bit 0)                                         */
37514  #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk       (0xffffUL)     /*!< UNDER (Bitfield-Mask: 0xffff)                         */
37515 /* =========================================================  RFOCR  ========================================================= */
37516  #define R_ETHERC_EDMAC_RFOCR_OVER_Pos        (0UL)          /*!< OVER (Bit 0)                                          */
37517  #define R_ETHERC_EDMAC_RFOCR_OVER_Msk        (0xffffUL)     /*!< OVER (Bitfield-Mask: 0xffff)                          */
37518 /* =========================================================  IOSR  ========================================================== */
37519  #define R_ETHERC_EDMAC_IOSR_ELB_Pos          (0UL)          /*!< ELB (Bit 0)                                           */
37520  #define R_ETHERC_EDMAC_IOSR_ELB_Msk          (0x1UL)        /*!< ELB (Bitfield-Mask: 0x01)                             */
37521 /* =========================================================  FCFTR  ========================================================= */
37522  #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos        (16UL)         /*!< RFFO (Bit 16)                                         */
37523  #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk        (0x70000UL)    /*!< RFFO (Bitfield-Mask: 0x07)                            */
37524  #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos        (0UL)          /*!< RFDO (Bit 0)                                          */
37525  #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk        (0x7UL)        /*!< RFDO (Bitfield-Mask: 0x07)                            */
37526 /* ========================================================  RPADIR  ========================================================= */
37527  #define R_ETHERC_EDMAC_RPADIR_PADS_Pos       (16UL)         /*!< PADS (Bit 16)                                         */
37528  #define R_ETHERC_EDMAC_RPADIR_PADS_Msk       (0x30000UL)    /*!< PADS (Bitfield-Mask: 0x03)                            */
37529  #define R_ETHERC_EDMAC_RPADIR_PADR_Pos       (0UL)          /*!< PADR (Bit 0)                                          */
37530  #define R_ETHERC_EDMAC_RPADIR_PADR_Msk       (0x3fUL)       /*!< PADR (Bitfield-Mask: 0x3f)                            */
37531 /* =========================================================  TRIMD  ========================================================= */
37532  #define R_ETHERC_EDMAC_TRIMD_TIM_Pos         (4UL)          /*!< TIM (Bit 4)                                           */
37533  #define R_ETHERC_EDMAC_TRIMD_TIM_Msk         (0x10UL)       /*!< TIM (Bitfield-Mask: 0x01)                             */
37534  #define R_ETHERC_EDMAC_TRIMD_TIS_Pos         (0UL)          /*!< TIS (Bit 0)                                           */
37535  #define R_ETHERC_EDMAC_TRIMD_TIS_Msk         (0x1UL)        /*!< TIS (Bitfield-Mask: 0x01)                             */
37536 /* =========================================================  RBWAR  ========================================================= */
37537  #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos       (0UL)          /*!< RBWAR (Bit 0)                                         */
37538  #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk       (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff)                     */
37539 /* =========================================================  RDFAR  ========================================================= */
37540  #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos       (0UL)          /*!< RDFAR (Bit 0)                                         */
37541  #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk       (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff)                     */
37542 /* =========================================================  TBRAR  ========================================================= */
37543  #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos       (0UL)          /*!< TBRAR (Bit 0)                                         */
37544  #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk       (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff)                     */
37545 /* =========================================================  TDFAR  ========================================================= */
37546  #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos       (0UL)          /*!< TDFAR (Bit 0)                                         */
37547  #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk       (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff)                     */
37548 
37549 /* =========================================================================================================================== */
37550 /* ================                                      R_ETHERC_EPTPC                                       ================ */
37551 /* =========================================================================================================================== */
37552 
37553 /* =========================================================  SYSR  ========================================================== */
37554  #define R_ETHERC_EPTPC_SYSR_GENDN_Pos             (17UL)         /*!< GENDN (Bit 17)                                        */
37555  #define R_ETHERC_EPTPC_SYSR_GENDN_Msk             (0x20000UL)    /*!< GENDN (Bitfield-Mask: 0x01)                           */
37556  #define R_ETHERC_EPTPC_SYSR_RESDN_Pos             (16UL)         /*!< RESDN (Bit 16)                                        */
37557  #define R_ETHERC_EPTPC_SYSR_RESDN_Msk             (0x10000UL)    /*!< RESDN (Bitfield-Mask: 0x01)                           */
37558  #define R_ETHERC_EPTPC_SYSR_INFABT_Pos            (14UL)         /*!< INFABT (Bit 14)                                       */
37559  #define R_ETHERC_EPTPC_SYSR_INFABT_Msk            (0x4000UL)     /*!< INFABT (Bitfield-Mask: 0x01)                          */
37560  #define R_ETHERC_EPTPC_SYSR_RECLP_Pos             (12UL)         /*!< RECLP (Bit 12)                                        */
37561  #define R_ETHERC_EPTPC_SYSR_RECLP_Msk             (0x1000UL)     /*!< RECLP (Bitfield-Mask: 0x01)                           */
37562  #define R_ETHERC_EPTPC_SYSR_DRQOVR_Pos            (6UL)          /*!< DRQOVR (Bit 6)                                        */
37563  #define R_ETHERC_EPTPC_SYSR_DRQOVR_Msk            (0x40UL)       /*!< DRQOVR (Bitfield-Mask: 0x01)                          */
37564  #define R_ETHERC_EPTPC_SYSR_INTDEV_Pos            (5UL)          /*!< INTDEV (Bit 5)                                        */
37565  #define R_ETHERC_EPTPC_SYSR_INTDEV_Msk            (0x20UL)       /*!< INTDEV (Bitfield-Mask: 0x01)                          */
37566  #define R_ETHERC_EPTPC_SYSR_DRPTO_Pos             (4UL)          /*!< DRPTO (Bit 4)                                         */
37567  #define R_ETHERC_EPTPC_SYSR_DRPTO_Msk             (0x10UL)       /*!< DRPTO (Bitfield-Mask: 0x01)                           */
37568  #define R_ETHERC_EPTPC_SYSR_MPDUD_Pos             (2UL)          /*!< MPDUD (Bit 2)                                         */
37569  #define R_ETHERC_EPTPC_SYSR_MPDUD_Msk             (0x4UL)        /*!< MPDUD (Bitfield-Mask: 0x01)                           */
37570  #define R_ETHERC_EPTPC_SYSR_INTCHG_Pos            (1UL)          /*!< INTCHG (Bit 1)                                        */
37571  #define R_ETHERC_EPTPC_SYSR_INTCHG_Msk            (0x2UL)        /*!< INTCHG (Bitfield-Mask: 0x01)                          */
37572  #define R_ETHERC_EPTPC_SYSR_OFMUD_Pos             (0UL)          /*!< OFMUD (Bit 0)                                         */
37573  #define R_ETHERC_EPTPC_SYSR_OFMUD_Msk             (0x1UL)        /*!< OFMUD (Bitfield-Mask: 0x01)                           */
37574 /* =========================================================  SYIPR  ========================================================= */
37575  #define R_ETHERC_EPTPC_SYIPR_GENDN_Pos            (17UL)         /*!< GENDN (Bit 17)                                        */
37576  #define R_ETHERC_EPTPC_SYIPR_GENDN_Msk            (0x20000UL)    /*!< GENDN (Bitfield-Mask: 0x01)                           */
37577  #define R_ETHERC_EPTPC_SYIPR_RESDN_Pos            (16UL)         /*!< RESDN (Bit 16)                                        */
37578  #define R_ETHERC_EPTPC_SYIPR_RESDN_Msk            (0x10000UL)    /*!< RESDN (Bitfield-Mask: 0x01)                           */
37579  #define R_ETHERC_EPTPC_SYIPR_INFABT_Pos           (14UL)         /*!< INFABT (Bit 14)                                       */
37580  #define R_ETHERC_EPTPC_SYIPR_INFABT_Msk           (0x4000UL)     /*!< INFABT (Bitfield-Mask: 0x01)                          */
37581  #define R_ETHERC_EPTPC_SYIPR_RECLP_Pos            (12UL)         /*!< RECLP (Bit 12)                                        */
37582  #define R_ETHERC_EPTPC_SYIPR_RECLP_Msk            (0x1000UL)     /*!< RECLP (Bitfield-Mask: 0x01)                           */
37583  #define R_ETHERC_EPTPC_SYIPR_DRQOVR_Pos           (6UL)          /*!< DRQOVR (Bit 6)                                        */
37584  #define R_ETHERC_EPTPC_SYIPR_DRQOVR_Msk           (0x40UL)       /*!< DRQOVR (Bitfield-Mask: 0x01)                          */
37585  #define R_ETHERC_EPTPC_SYIPR_INTDEV_Pos           (5UL)          /*!< INTDEV (Bit 5)                                        */
37586  #define R_ETHERC_EPTPC_SYIPR_INTDEV_Msk           (0x20UL)       /*!< INTDEV (Bitfield-Mask: 0x01)                          */
37587  #define R_ETHERC_EPTPC_SYIPR_DRPTO_Pos            (4UL)          /*!< DRPTO (Bit 4)                                         */
37588  #define R_ETHERC_EPTPC_SYIPR_DRPTO_Msk            (0x10UL)       /*!< DRPTO (Bitfield-Mask: 0x01)                           */
37589  #define R_ETHERC_EPTPC_SYIPR_MPDUD_Pos            (2UL)          /*!< MPDUD (Bit 2)                                         */
37590  #define R_ETHERC_EPTPC_SYIPR_MPDUD_Msk            (0x4UL)        /*!< MPDUD (Bitfield-Mask: 0x01)                           */
37591  #define R_ETHERC_EPTPC_SYIPR_INTCHG_Pos           (1UL)          /*!< INTCHG (Bit 1)                                        */
37592  #define R_ETHERC_EPTPC_SYIPR_INTCHG_Msk           (0x2UL)        /*!< INTCHG (Bitfield-Mask: 0x01)                          */
37593  #define R_ETHERC_EPTPC_SYIPR_OFMUD_Pos            (0UL)          /*!< OFMUD (Bit 0)                                         */
37594  #define R_ETHERC_EPTPC_SYIPR_OFMUD_Msk            (0x1UL)        /*!< OFMUD (Bitfield-Mask: 0x01)                           */
37595 /* ========================================================  SYMACRU  ======================================================== */
37596  #define R_ETHERC_EPTPC_SYMACRU_SYMACRU_Pos        (0UL)          /*!< SYMACRU (Bit 0)                                       */
37597  #define R_ETHERC_EPTPC_SYMACRU_SYMACRU_Msk        (0xffffffUL)   /*!< SYMACRU (Bitfield-Mask: 0xffffff)                     */
37598 /* ========================================================  SYMACRL  ======================================================== */
37599  #define R_ETHERC_EPTPC_SYMACRL_SYMACRL_Pos        (0UL)          /*!< SYMACRL (Bit 0)                                       */
37600  #define R_ETHERC_EPTPC_SYMACRL_SYMACRL_Msk        (0xffffffUL)   /*!< SYMACRL (Bitfield-Mask: 0xffffff)                     */
37601 /* =======================================================  SYLLCCTLR  ======================================================= */
37602  #define R_ETHERC_EPTPC_SYLLCCTLR_CTL_Pos          (0UL)          /*!< CTL (Bit 0)                                           */
37603  #define R_ETHERC_EPTPC_SYLLCCTLR_CTL_Msk          (0xffUL)       /*!< CTL (Bitfield-Mask: 0xff)                             */
37604 /* =======================================================  SYIPADDRR  ======================================================= */
37605  #define R_ETHERC_EPTPC_SYIPADDRR_SYIPADDRR_Pos    (0UL)          /*!< SYIPADDRR (Bit 0)                                     */
37606  #define R_ETHERC_EPTPC_SYIPADDRR_SYIPADDRR_Msk    (0xffffffffUL) /*!< SYIPADDRR (Bitfield-Mask: 0xffffffff)                 */
37607 /* ========================================================  SYSPVRR  ======================================================== */
37608  #define R_ETHERC_EPTPC_SYSPVRR_TRSP_Pos           (4UL)          /*!< TRSP (Bit 4)                                          */
37609  #define R_ETHERC_EPTPC_SYSPVRR_TRSP_Msk           (0xf0UL)       /*!< TRSP (Bitfield-Mask: 0x0f)                            */
37610  #define R_ETHERC_EPTPC_SYSPVRR_VER_Pos            (0UL)          /*!< VER (Bit 0)                                           */
37611  #define R_ETHERC_EPTPC_SYSPVRR_VER_Msk            (0xfUL)        /*!< VER (Bitfield-Mask: 0x0f)                             */
37612 /* ========================================================  SYDOMR  ========================================================= */
37613  #define R_ETHERC_EPTPC_SYDOMR_DNUM_Pos            (0UL)          /*!< DNUM (Bit 0)                                          */
37614  #define R_ETHERC_EPTPC_SYDOMR_DNUM_Msk            (0xffUL)       /*!< DNUM (Bitfield-Mask: 0xff)                            */
37615 /* =========================================================  ANFR  ========================================================== */
37616  #define R_ETHERC_EPTPC_ANFR_FLAG14_Pos            (14UL)         /*!< FLAG14 (Bit 14)                                       */
37617  #define R_ETHERC_EPTPC_ANFR_FLAG14_Msk            (0x4000UL)     /*!< FLAG14 (Bitfield-Mask: 0x01)                          */
37618  #define R_ETHERC_EPTPC_ANFR_FLAG13_Pos            (13UL)         /*!< FLAG13 (Bit 13)                                       */
37619  #define R_ETHERC_EPTPC_ANFR_FLAG13_Msk            (0x2000UL)     /*!< FLAG13 (Bitfield-Mask: 0x01)                          */
37620  #define R_ETHERC_EPTPC_ANFR_FLAG10_Pos            (10UL)         /*!< FLAG10 (Bit 10)                                       */
37621  #define R_ETHERC_EPTPC_ANFR_FLAG10_Msk            (0x400UL)      /*!< FLAG10 (Bitfield-Mask: 0x01)                          */
37622  #define R_ETHERC_EPTPC_ANFR_FLAG8_Pos             (8UL)          /*!< FLAG8 (Bit 8)                                         */
37623  #define R_ETHERC_EPTPC_ANFR_FLAG8_Msk             (0x100UL)      /*!< FLAG8 (Bitfield-Mask: 0x01)                           */
37624  #define R_ETHERC_EPTPC_ANFR_FLAG5_Pos             (5UL)          /*!< FLAG5 (Bit 5)                                         */
37625  #define R_ETHERC_EPTPC_ANFR_FLAG5_Msk             (0x20UL)       /*!< FLAG5 (Bitfield-Mask: 0x01)                           */
37626  #define R_ETHERC_EPTPC_ANFR_FLAG4_Pos             (4UL)          /*!< FLAG4 (Bit 4)                                         */
37627  #define R_ETHERC_EPTPC_ANFR_FLAG4_Msk             (0x10UL)       /*!< FLAG4 (Bitfield-Mask: 0x01)                           */
37628  #define R_ETHERC_EPTPC_ANFR_FLAG3_Pos             (3UL)          /*!< FLAG3 (Bit 3)                                         */
37629  #define R_ETHERC_EPTPC_ANFR_FLAG3_Msk             (0x8UL)        /*!< FLAG3 (Bitfield-Mask: 0x01)                           */
37630  #define R_ETHERC_EPTPC_ANFR_FLAG2_Pos             (2UL)          /*!< FLAG2 (Bit 2)                                         */
37631  #define R_ETHERC_EPTPC_ANFR_FLAG2_Msk             (0x4UL)        /*!< FLAG2 (Bitfield-Mask: 0x01)                           */
37632  #define R_ETHERC_EPTPC_ANFR_FLAG1_Pos             (1UL)          /*!< FLAG1 (Bit 1)                                         */
37633  #define R_ETHERC_EPTPC_ANFR_FLAG1_Msk             (0x2UL)        /*!< FLAG1 (Bitfield-Mask: 0x01)                           */
37634  #define R_ETHERC_EPTPC_ANFR_FLAG0_Pos             (0UL)          /*!< FLAG0 (Bit 0)                                         */
37635  #define R_ETHERC_EPTPC_ANFR_FLAG0_Msk             (0x1UL)        /*!< FLAG0 (Bitfield-Mask: 0x01)                           */
37636 /* =========================================================  SYNFR  ========================================================= */
37637  #define R_ETHERC_EPTPC_SYNFR_FLAG14_Pos           (14UL)         /*!< FLAG14 (Bit 14)                                       */
37638  #define R_ETHERC_EPTPC_SYNFR_FLAG14_Msk           (0x4000UL)     /*!< FLAG14 (Bitfield-Mask: 0x01)                          */
37639  #define R_ETHERC_EPTPC_SYNFR_FLAG13_Pos           (13UL)         /*!< FLAG13 (Bit 13)                                       */
37640  #define R_ETHERC_EPTPC_SYNFR_FLAG13_Msk           (0x2000UL)     /*!< FLAG13 (Bitfield-Mask: 0x01)                          */
37641  #define R_ETHERC_EPTPC_SYNFR_FLAG10_Pos           (10UL)         /*!< FLAG10 (Bit 10)                                       */
37642  #define R_ETHERC_EPTPC_SYNFR_FLAG10_Msk           (0x400UL)      /*!< FLAG10 (Bitfield-Mask: 0x01)                          */
37643  #define R_ETHERC_EPTPC_SYNFR_FLAG9_Pos            (9UL)          /*!< FLAG9 (Bit 9)                                         */
37644  #define R_ETHERC_EPTPC_SYNFR_FLAG9_Msk            (0x200UL)      /*!< FLAG9 (Bitfield-Mask: 0x01)                           */
37645  #define R_ETHERC_EPTPC_SYNFR_FLAG8_Pos            (8UL)          /*!< FLAG8 (Bit 8)                                         */
37646  #define R_ETHERC_EPTPC_SYNFR_FLAG8_Msk            (0x100UL)      /*!< FLAG8 (Bitfield-Mask: 0x01)                           */
37647 /* ========================================================  DYRQFR  ========================================================= */
37648  #define R_ETHERC_EPTPC_DYRQFR_FLAG14_Pos          (14UL)         /*!< FLAG14 (Bit 14)                                       */
37649  #define R_ETHERC_EPTPC_DYRQFR_FLAG14_Msk          (0x4000UL)     /*!< FLAG14 (Bitfield-Mask: 0x01)                          */
37650  #define R_ETHERC_EPTPC_DYRQFR_FLAG13_Pos          (13UL)         /*!< FLAG13 (Bit 13)                                       */
37651  #define R_ETHERC_EPTPC_DYRQFR_FLAG13_Msk          (0x2000UL)     /*!< FLAG13 (Bitfield-Mask: 0x01)                          */
37652  #define R_ETHERC_EPTPC_DYRQFR_FLAG10_Pos          (10UL)         /*!< FLAG10 (Bit 10)                                       */
37653  #define R_ETHERC_EPTPC_DYRQFR_FLAG10_Msk          (0x400UL)      /*!< FLAG10 (Bitfield-Mask: 0x01)                          */
37654 /* ========================================================  DYRPFR  ========================================================= */
37655  #define R_ETHERC_EPTPC_DYRPFR_FLAG14_Pos          (14UL)         /*!< FLAG14 (Bit 14)                                       */
37656  #define R_ETHERC_EPTPC_DYRPFR_FLAG14_Msk          (0x4000UL)     /*!< FLAG14 (Bitfield-Mask: 0x01)                          */
37657  #define R_ETHERC_EPTPC_DYRPFR_FLAG13_Pos          (13UL)         /*!< FLAG13 (Bit 13)                                       */
37658  #define R_ETHERC_EPTPC_DYRPFR_FLAG13_Msk          (0x2000UL)     /*!< FLAG13 (Bitfield-Mask: 0x01)                          */
37659  #define R_ETHERC_EPTPC_DYRPFR_FLAG10_Pos          (10UL)         /*!< FLAG10 (Bit 10)                                       */
37660  #define R_ETHERC_EPTPC_DYRPFR_FLAG10_Msk          (0x400UL)      /*!< FLAG10 (Bitfield-Mask: 0x01)                          */
37661  #define R_ETHERC_EPTPC_DYRPFR_FLAG9_Pos           (9UL)          /*!< FLAG9 (Bit 9)                                         */
37662  #define R_ETHERC_EPTPC_DYRPFR_FLAG9_Msk           (0x200UL)      /*!< FLAG9 (Bitfield-Mask: 0x01)                           */
37663  #define R_ETHERC_EPTPC_DYRPFR_FLAG8_Pos           (8UL)          /*!< FLAG8 (Bit 8)                                         */
37664  #define R_ETHERC_EPTPC_DYRPFR_FLAG8_Msk           (0x100UL)      /*!< FLAG8 (Bitfield-Mask: 0x01)                           */
37665 /* ========================================================  SYCIDRU  ======================================================== */
37666  #define R_ETHERC_EPTPC_SYCIDRU_SYCIDRU_Pos        (0UL)          /*!< SYCIDRU (Bit 0)                                       */
37667  #define R_ETHERC_EPTPC_SYCIDRU_SYCIDRU_Msk        (0xffffffffUL) /*!< SYCIDRU (Bitfield-Mask: 0xffffffff)                   */
37668 /* ========================================================  SYCIDRL  ======================================================== */
37669  #define R_ETHERC_EPTPC_SYCIDRL_SYCIDRL_Pos        (0UL)          /*!< SYCIDRL (Bit 0)                                       */
37670  #define R_ETHERC_EPTPC_SYCIDRL_SYCIDRL_Msk        (0xffffffffUL) /*!< SYCIDRL (Bitfield-Mask: 0xffffffff)                   */
37671 /* ========================================================  SYPNUMR  ======================================================== */
37672  #define R_ETHERC_EPTPC_SYPNUMR_PNUM_Pos           (0UL)          /*!< PNUM (Bit 0)                                          */
37673  #define R_ETHERC_EPTPC_SYPNUMR_PNUM_Msk           (0xffffUL)     /*!< PNUM (Bitfield-Mask: 0xffff)                          */
37674 /* ========================================================  SYRVLDR  ======================================================== */
37675  #define R_ETHERC_EPTPC_SYRVLDR_ANUP_Pos           (2UL)          /*!< ANUP (Bit 2)                                          */
37676  #define R_ETHERC_EPTPC_SYRVLDR_ANUP_Msk           (0x4UL)        /*!< ANUP (Bitfield-Mask: 0x01)                            */
37677  #define R_ETHERC_EPTPC_SYRVLDR_STUP_Pos           (1UL)          /*!< STUP (Bit 1)                                          */
37678  #define R_ETHERC_EPTPC_SYRVLDR_STUP_Msk           (0x2UL)        /*!< STUP (Bitfield-Mask: 0x01)                            */
37679  #define R_ETHERC_EPTPC_SYRVLDR_BMUP_Pos           (0UL)          /*!< BMUP (Bit 0)                                          */
37680  #define R_ETHERC_EPTPC_SYRVLDR_BMUP_Msk           (0x1UL)        /*!< BMUP (Bitfield-Mask: 0x01)                            */
37681 /* ========================================================  SYRFL1R  ======================================================== */
37682  #define R_ETHERC_EPTPC_SYRFL1R_PDFUP2_Pos         (30UL)         /*!< PDFUP2 (Bit 30)                                       */
37683  #define R_ETHERC_EPTPC_SYRFL1R_PDFUP2_Msk         (0x40000000UL) /*!< PDFUP2 (Bitfield-Mask: 0x01)                          */
37684  #define R_ETHERC_EPTPC_SYRFL1R_PDFUP1_Pos         (29UL)         /*!< PDFUP1 (Bit 29)                                       */
37685  #define R_ETHERC_EPTPC_SYRFL1R_PDFUP1_Msk         (0x20000000UL) /*!< PDFUP1 (Bitfield-Mask: 0x01)                          */
37686  #define R_ETHERC_EPTPC_SYRFL1R_PDFUP0_Pos         (28UL)         /*!< PDFUP0 (Bit 28)                                       */
37687  #define R_ETHERC_EPTPC_SYRFL1R_PDFUP0_Msk         (0x10000000UL) /*!< PDFUP0 (Bitfield-Mask: 0x01)                          */
37688  #define R_ETHERC_EPTPC_SYRFL1R_PDRP2_Pos          (26UL)         /*!< PDRP2 (Bit 26)                                        */
37689  #define R_ETHERC_EPTPC_SYRFL1R_PDRP2_Msk          (0x4000000UL)  /*!< PDRP2 (Bitfield-Mask: 0x01)                           */
37690  #define R_ETHERC_EPTPC_SYRFL1R_PDRP1_Pos          (25UL)         /*!< PDRP1 (Bit 25)                                        */
37691  #define R_ETHERC_EPTPC_SYRFL1R_PDRP1_Msk          (0x2000000UL)  /*!< PDRP1 (Bitfield-Mask: 0x01)                           */
37692  #define R_ETHERC_EPTPC_SYRFL1R_PDRP0_Pos          (24UL)         /*!< PDRP0 (Bit 24)                                        */
37693  #define R_ETHERC_EPTPC_SYRFL1R_PDRP0_Msk          (0x1000000UL)  /*!< PDRP0 (Bitfield-Mask: 0x01)                           */
37694  #define R_ETHERC_EPTPC_SYRFL1R_PDRQ2_Pos          (22UL)         /*!< PDRQ2 (Bit 22)                                        */
37695  #define R_ETHERC_EPTPC_SYRFL1R_PDRQ2_Msk          (0x400000UL)   /*!< PDRQ2 (Bitfield-Mask: 0x01)                           */
37696  #define R_ETHERC_EPTPC_SYRFL1R_PDRQ1_Pos          (21UL)         /*!< PDRQ1 (Bit 21)                                        */
37697  #define R_ETHERC_EPTPC_SYRFL1R_PDRQ1_Msk          (0x200000UL)   /*!< PDRQ1 (Bitfield-Mask: 0x01)                           */
37698  #define R_ETHERC_EPTPC_SYRFL1R_PDRQ0_Pos          (20UL)         /*!< PDRQ0 (Bit 20)                                        */
37699  #define R_ETHERC_EPTPC_SYRFL1R_PDRQ0_Msk          (0x100000UL)   /*!< PDRQ0 (Bitfield-Mask: 0x01)                           */
37700  #define R_ETHERC_EPTPC_SYRFL1R_DRP2_Pos           (18UL)         /*!< DRP2 (Bit 18)                                         */
37701  #define R_ETHERC_EPTPC_SYRFL1R_DRP2_Msk           (0x40000UL)    /*!< DRP2 (Bitfield-Mask: 0x01)                            */
37702  #define R_ETHERC_EPTPC_SYRFL1R_DRP1_Pos           (17UL)         /*!< DRP1 (Bit 17)                                         */
37703  #define R_ETHERC_EPTPC_SYRFL1R_DRP1_Msk           (0x20000UL)    /*!< DRP1 (Bitfield-Mask: 0x01)                            */
37704  #define R_ETHERC_EPTPC_SYRFL1R_DRP0_Pos           (16UL)         /*!< DRP0 (Bit 16)                                         */
37705  #define R_ETHERC_EPTPC_SYRFL1R_DRP0_Msk           (0x10000UL)    /*!< DRP0 (Bitfield-Mask: 0x01)                            */
37706  #define R_ETHERC_EPTPC_SYRFL1R_DRQ2_Pos           (14UL)         /*!< DRQ2 (Bit 14)                                         */
37707  #define R_ETHERC_EPTPC_SYRFL1R_DRQ2_Msk           (0x4000UL)     /*!< DRQ2 (Bitfield-Mask: 0x01)                            */
37708  #define R_ETHERC_EPTPC_SYRFL1R_DRQ1_Pos           (13UL)         /*!< DRQ1 (Bit 13)                                         */
37709  #define R_ETHERC_EPTPC_SYRFL1R_DRQ1_Msk           (0x2000UL)     /*!< DRQ1 (Bitfield-Mask: 0x01)                            */
37710  #define R_ETHERC_EPTPC_SYRFL1R_DRQ0_Pos           (12UL)         /*!< DRQ0 (Bit 12)                                         */
37711  #define R_ETHERC_EPTPC_SYRFL1R_DRQ0_Msk           (0x1000UL)     /*!< DRQ0 (Bitfield-Mask: 0x01)                            */
37712  #define R_ETHERC_EPTPC_SYRFL1R_FUP2_Pos           (10UL)         /*!< FUP2 (Bit 10)                                         */
37713  #define R_ETHERC_EPTPC_SYRFL1R_FUP2_Msk           (0x400UL)      /*!< FUP2 (Bitfield-Mask: 0x01)                            */
37714  #define R_ETHERC_EPTPC_SYRFL1R_FUP1_Pos           (9UL)          /*!< FUP1 (Bit 9)                                          */
37715  #define R_ETHERC_EPTPC_SYRFL1R_FUP1_Msk           (0x200UL)      /*!< FUP1 (Bitfield-Mask: 0x01)                            */
37716  #define R_ETHERC_EPTPC_SYRFL1R_FUP0_Pos           (8UL)          /*!< FUP0 (Bit 8)                                          */
37717  #define R_ETHERC_EPTPC_SYRFL1R_FUP0_Msk           (0x100UL)      /*!< FUP0 (Bitfield-Mask: 0x01)                            */
37718  #define R_ETHERC_EPTPC_SYRFL1R_SYNC2_Pos          (6UL)          /*!< SYNC2 (Bit 6)                                         */
37719  #define R_ETHERC_EPTPC_SYRFL1R_SYNC2_Msk          (0x40UL)       /*!< SYNC2 (Bitfield-Mask: 0x01)                           */
37720  #define R_ETHERC_EPTPC_SYRFL1R_SYNC1_Pos          (5UL)          /*!< SYNC1 (Bit 5)                                         */
37721  #define R_ETHERC_EPTPC_SYRFL1R_SYNC1_Msk          (0x20UL)       /*!< SYNC1 (Bitfield-Mask: 0x01)                           */
37722  #define R_ETHERC_EPTPC_SYRFL1R_SYNC0_Pos          (4UL)          /*!< SYNC0 (Bit 4)                                         */
37723  #define R_ETHERC_EPTPC_SYRFL1R_SYNC0_Msk          (0x10UL)       /*!< SYNC0 (Bitfield-Mask: 0x01)                           */
37724  #define R_ETHERC_EPTPC_SYRFL1R_ANCE1_Pos          (1UL)          /*!< ANCE1 (Bit 1)                                         */
37725  #define R_ETHERC_EPTPC_SYRFL1R_ANCE1_Msk          (0x2UL)        /*!< ANCE1 (Bitfield-Mask: 0x01)                           */
37726  #define R_ETHERC_EPTPC_SYRFL1R_ANCE0_Pos          (0UL)          /*!< ANCE0 (Bit 0)                                         */
37727  #define R_ETHERC_EPTPC_SYRFL1R_ANCE0_Msk          (0x1UL)        /*!< ANCE0 (Bitfield-Mask: 0x01)                           */
37728 /* ========================================================  SYRFL2R  ======================================================== */
37729  #define R_ETHERC_EPTPC_SYRFL2R_ILL1_Pos           (29UL)         /*!< ILL1 (Bit 29)                                         */
37730  #define R_ETHERC_EPTPC_SYRFL2R_ILL1_Msk           (0x20000000UL) /*!< ILL1 (Bitfield-Mask: 0x01)                            */
37731  #define R_ETHERC_EPTPC_SYRFL2R_ILL0_Pos           (28UL)         /*!< ILL0 (Bit 28)                                         */
37732  #define R_ETHERC_EPTPC_SYRFL2R_ILL0_Msk           (0x10000000UL) /*!< ILL0 (Bitfield-Mask: 0x01)                            */
37733  #define R_ETHERC_EPTPC_SYRFL2R_SIG1_Pos           (5UL)          /*!< SIG1 (Bit 5)                                          */
37734  #define R_ETHERC_EPTPC_SYRFL2R_SIG1_Msk           (0x20UL)       /*!< SIG1 (Bitfield-Mask: 0x01)                            */
37735  #define R_ETHERC_EPTPC_SYRFL2R_SIG0_Pos           (4UL)          /*!< SIG0 (Bit 4)                                          */
37736  #define R_ETHERC_EPTPC_SYRFL2R_SIG0_Msk           (0x10UL)       /*!< SIG0 (Bitfield-Mask: 0x01)                            */
37737  #define R_ETHERC_EPTPC_SYRFL2R_MAN1_Pos           (1UL)          /*!< MAN1 (Bit 1)                                          */
37738  #define R_ETHERC_EPTPC_SYRFL2R_MAN1_Msk           (0x2UL)        /*!< MAN1 (Bitfield-Mask: 0x01)                            */
37739  #define R_ETHERC_EPTPC_SYRFL2R_MAN0_Pos           (0UL)          /*!< MAN0 (Bit 0)                                          */
37740  #define R_ETHERC_EPTPC_SYRFL2R_MAN0_Msk           (0x1UL)        /*!< MAN0 (Bitfield-Mask: 0x01)                            */
37741 /* ========================================================  SYTRENR  ======================================================== */
37742  #define R_ETHERC_EPTPC_SYTRENR_PDRQ_Pos           (12UL)         /*!< PDRQ (Bit 12)                                         */
37743  #define R_ETHERC_EPTPC_SYTRENR_PDRQ_Msk           (0x1000UL)     /*!< PDRQ (Bitfield-Mask: 0x01)                            */
37744  #define R_ETHERC_EPTPC_SYTRENR_DRQ_Pos            (8UL)          /*!< DRQ (Bit 8)                                           */
37745  #define R_ETHERC_EPTPC_SYTRENR_DRQ_Msk            (0x100UL)      /*!< DRQ (Bitfield-Mask: 0x01)                             */
37746  #define R_ETHERC_EPTPC_SYTRENR_SYNC_Pos           (4UL)          /*!< SYNC (Bit 4)                                          */
37747  #define R_ETHERC_EPTPC_SYTRENR_SYNC_Msk           (0x10UL)       /*!< SYNC (Bitfield-Mask: 0x01)                            */
37748  #define R_ETHERC_EPTPC_SYTRENR_ANCE_Pos           (0UL)          /*!< ANCE (Bit 0)                                          */
37749  #define R_ETHERC_EPTPC_SYTRENR_ANCE_Msk           (0x1UL)        /*!< ANCE (Bitfield-Mask: 0x01)                            */
37750 /* ========================================================  MTCIDU  ========================================================= */
37751  #define R_ETHERC_EPTPC_MTCIDU_MTCIDU_Pos          (0UL)          /*!< MTCIDU (Bit 0)                                        */
37752  #define R_ETHERC_EPTPC_MTCIDU_MTCIDU_Msk          (0xffffffffUL) /*!< MTCIDU (Bitfield-Mask: 0xffffffff)                    */
37753 /* ========================================================  MTCIDL  ========================================================= */
37754  #define R_ETHERC_EPTPC_MTCIDL_MTCIDL_Pos          (0UL)          /*!< MTCIDL (Bit 0)                                        */
37755  #define R_ETHERC_EPTPC_MTCIDL_MTCIDL_Msk          (0xffffffffUL) /*!< MTCIDL (Bitfield-Mask: 0xffffffff)                    */
37756 /* =========================================================  MTPID  ========================================================= */
37757  #define R_ETHERC_EPTPC_MTPID_PNUM_Pos             (0UL)          /*!< PNUM (Bit 0)                                          */
37758  #define R_ETHERC_EPTPC_MTPID_PNUM_Msk             (0xffffUL)     /*!< PNUM (Bitfield-Mask: 0xffff)                          */
37759 /* ========================================================  SYTLIR  ========================================================= */
37760  #define R_ETHERC_EPTPC_SYTLIR_DREQ_Pos            (16UL)         /*!< DREQ (Bit 16)                                         */
37761  #define R_ETHERC_EPTPC_SYTLIR_DREQ_Msk            (0xff0000UL)   /*!< DREQ (Bitfield-Mask: 0xff)                            */
37762  #define R_ETHERC_EPTPC_SYTLIR_SYNC_Pos            (8UL)          /*!< SYNC (Bit 8)                                          */
37763  #define R_ETHERC_EPTPC_SYTLIR_SYNC_Msk            (0xff00UL)     /*!< SYNC (Bitfield-Mask: 0xff)                            */
37764  #define R_ETHERC_EPTPC_SYTLIR_ANCE_Pos            (0UL)          /*!< ANCE (Bit 0)                                          */
37765  #define R_ETHERC_EPTPC_SYTLIR_ANCE_Msk            (0xffUL)       /*!< ANCE (Bitfield-Mask: 0xff)                            */
37766 /* ========================================================  SYRLIR  ========================================================= */
37767  #define R_ETHERC_EPTPC_SYRLIR_DRESP_Pos           (16UL)         /*!< DRESP (Bit 16)                                        */
37768  #define R_ETHERC_EPTPC_SYRLIR_DRESP_Msk           (0xff0000UL)   /*!< DRESP (Bitfield-Mask: 0xff)                           */
37769  #define R_ETHERC_EPTPC_SYRLIR_SYNC_Pos            (8UL)          /*!< SYNC (Bit 8)                                          */
37770  #define R_ETHERC_EPTPC_SYRLIR_SYNC_Msk            (0xff00UL)     /*!< SYNC (Bitfield-Mask: 0xff)                            */
37771  #define R_ETHERC_EPTPC_SYRLIR_ANCE_Pos            (0UL)          /*!< ANCE (Bit 0)                                          */
37772  #define R_ETHERC_EPTPC_SYRLIR_ANCE_Msk            (0xffUL)       /*!< ANCE (Bitfield-Mask: 0xff)                            */
37773 /* =========================================================  OFMRU  ========================================================= */
37774  #define R_ETHERC_EPTPC_OFMRU_OFMRU_Pos            (0UL)          /*!< OFMRU (Bit 0)                                         */
37775  #define R_ETHERC_EPTPC_OFMRU_OFMRU_Msk            (0xffffffffUL) /*!< OFMRU (Bitfield-Mask: 0xffffffff)                     */
37776 /* =========================================================  OFMRL  ========================================================= */
37777  #define R_ETHERC_EPTPC_OFMRL_OFMRL_Pos            (0UL)          /*!< OFMRL (Bit 0)                                         */
37778  #define R_ETHERC_EPTPC_OFMRL_OFMRL_Msk            (0xffffffffUL) /*!< OFMRL (Bitfield-Mask: 0xffffffff)                     */
37779 /* =========================================================  MPDRU  ========================================================= */
37780  #define R_ETHERC_EPTPC_MPDRU_MPDRU_Pos            (0UL)          /*!< MPDRU (Bit 0)                                         */
37781  #define R_ETHERC_EPTPC_MPDRU_MPDRU_Msk            (0xffffffffUL) /*!< MPDRU (Bitfield-Mask: 0xffffffff)                     */
37782 /* =========================================================  MPDRL  ========================================================= */
37783  #define R_ETHERC_EPTPC_MPDRL_MPDRL_Pos            (0UL)          /*!< MPDRL (Bit 0)                                         */
37784  #define R_ETHERC_EPTPC_MPDRL_MPDRL_Msk            (0xffffffffUL) /*!< MPDRL (Bitfield-Mask: 0xffffffff)                     */
37785 /* =========================================================  GMPR  ========================================================== */
37786  #define R_ETHERC_EPTPC_GMPR_GMPR1_Pos             (16UL)         /*!< GMPR1 (Bit 16)                                        */
37787  #define R_ETHERC_EPTPC_GMPR_GMPR1_Msk             (0xff0000UL)   /*!< GMPR1 (Bitfield-Mask: 0xff)                           */
37788  #define R_ETHERC_EPTPC_GMPR_GMPR2_Pos             (0UL)          /*!< GMPR2 (Bit 0)                                         */
37789  #define R_ETHERC_EPTPC_GMPR_GMPR2_Msk             (0xffUL)       /*!< GMPR2 (Bitfield-Mask: 0xff)                           */
37790 /* =========================================================  GMCQR  ========================================================= */
37791  #define R_ETHERC_EPTPC_GMCQR_GMCQR_Pos            (0UL)          /*!< GMCQR (Bit 0)                                         */
37792  #define R_ETHERC_EPTPC_GMCQR_GMCQR_Msk            (0xffffffffUL) /*!< GMCQR (Bitfield-Mask: 0xffffffff)                     */
37793 /* ========================================================  GMIDRU  ========================================================= */
37794  #define R_ETHERC_EPTPC_GMIDRU_GMIDRU_Pos          (0UL)          /*!< GMIDRU (Bit 0)                                        */
37795  #define R_ETHERC_EPTPC_GMIDRU_GMIDRU_Msk          (0xffffffffUL) /*!< GMIDRU (Bitfield-Mask: 0xffffffff)                    */
37796 /* ========================================================  GMIDRL  ========================================================= */
37797  #define R_ETHERC_EPTPC_GMIDRL_GMIDRL_Pos          (0UL)          /*!< GMIDRL (Bit 0)                                        */
37798  #define R_ETHERC_EPTPC_GMIDRL_GMIDRL_Msk          (0xffffffffUL) /*!< GMIDRL (Bitfield-Mask: 0xffffffff)                    */
37799 /* ========================================================  CUOTSR  ========================================================= */
37800  #define R_ETHERC_EPTPC_CUOTSR_CUTO_Pos            (16UL)         /*!< CUTO (Bit 16)                                         */
37801  #define R_ETHERC_EPTPC_CUOTSR_CUTO_Msk            (0xffff0000UL) /*!< CUTO (Bitfield-Mask: 0xffff)                          */
37802  #define R_ETHERC_EPTPC_CUOTSR_TSRC_Pos            (0UL)          /*!< TSRC (Bit 0)                                          */
37803  #define R_ETHERC_EPTPC_CUOTSR_TSRC_Msk            (0xffUL)       /*!< TSRC (Bitfield-Mask: 0xff)                            */
37804 /* ==========================================================  SRR  ========================================================== */
37805  #define R_ETHERC_EPTPC_SRR_SRMV_Pos               (0UL)          /*!< SRMV (Bit 0)                                          */
37806  #define R_ETHERC_EPTPC_SRR_SRMV_Msk               (0xffffUL)     /*!< SRMV (Bitfield-Mask: 0xffff)                          */
37807 /* ========================================================  PPMACRU  ======================================================== */
37808  #define R_ETHERC_EPTPC_PPMACRU_PPMACRU_Pos        (0UL)          /*!< PPMACRU (Bit 0)                                       */
37809  #define R_ETHERC_EPTPC_PPMACRU_PPMACRU_Msk        (0xffffffUL)   /*!< PPMACRU (Bitfield-Mask: 0xffffff)                     */
37810 /* ========================================================  PPMACRL  ======================================================== */
37811  #define R_ETHERC_EPTPC_PPMACRL_PPMACRL_Pos        (0UL)          /*!< PPMACRL (Bit 0)                                       */
37812  #define R_ETHERC_EPTPC_PPMACRL_PPMACRL_Msk        (0xffffffUL)   /*!< PPMACRL (Bitfield-Mask: 0xffffff)                     */
37813 /* ========================================================  PDMACRU  ======================================================== */
37814  #define R_ETHERC_EPTPC_PDMACRU_PDMACRU_Pos        (0UL)          /*!< PDMACRU (Bit 0)                                       */
37815  #define R_ETHERC_EPTPC_PDMACRU_PDMACRU_Msk        (0xffffffUL)   /*!< PDMACRU (Bitfield-Mask: 0xffffff)                     */
37816 /* ========================================================  PDMACRL  ======================================================== */
37817  #define R_ETHERC_EPTPC_PDMACRL_PDMACRL_Pos        (0UL)          /*!< PDMACRL (Bit 0)                                       */
37818  #define R_ETHERC_EPTPC_PDMACRL_PDMACRL_Msk        (0xffffffUL)   /*!< PDMACRL (Bitfield-Mask: 0xffffff)                     */
37819 /* ========================================================  PETYPER  ======================================================== */
37820  #define R_ETHERC_EPTPC_PETYPER_TYPE_Pos           (0UL)          /*!< TYPE (Bit 0)                                          */
37821  #define R_ETHERC_EPTPC_PETYPER_TYPE_Msk           (0xffffUL)     /*!< TYPE (Bitfield-Mask: 0xffff)                          */
37822 /* =========================================================  PPIPR  ========================================================= */
37823  #define R_ETHERC_EPTPC_PPIPR_PPIPR_Pos            (0UL)          /*!< PPIPR (Bit 0)                                         */
37824  #define R_ETHERC_EPTPC_PPIPR_PPIPR_Msk            (0xffffffffUL) /*!< PPIPR (Bitfield-Mask: 0xffffffff)                     */
37825 /* =========================================================  PDIPR  ========================================================= */
37826  #define R_ETHERC_EPTPC_PDIPR_PDIPR_Pos            (0UL)          /*!< PDIPR (Bit 0)                                         */
37827  #define R_ETHERC_EPTPC_PDIPR_PDIPR_Msk            (0xffffffffUL) /*!< PDIPR (Bitfield-Mask: 0xffffffff)                     */
37828 /* ========================================================  PETOSR  ========================================================= */
37829  #define R_ETHERC_EPTPC_PETOSR_EVTO_Pos            (0UL)          /*!< EVTO (Bit 0)                                          */
37830  #define R_ETHERC_EPTPC_PETOSR_EVTO_Msk            (0xffUL)       /*!< EVTO (Bitfield-Mask: 0xff)                            */
37831 /* ========================================================  PGTOSR  ========================================================= */
37832  #define R_ETHERC_EPTPC_PGTOSR_GETO_Pos            (0UL)          /*!< GETO (Bit 0)                                          */
37833  #define R_ETHERC_EPTPC_PGTOSR_GETO_Msk            (0xffUL)       /*!< GETO (Bitfield-Mask: 0xff)                            */
37834 /* ========================================================  PPTTLR  ========================================================= */
37835  #define R_ETHERC_EPTPC_PPTTLR_PRTL_Pos            (0UL)          /*!< PRTL (Bit 0)                                          */
37836  #define R_ETHERC_EPTPC_PPTTLR_PRTL_Msk            (0xffUL)       /*!< PRTL (Bitfield-Mask: 0xff)                            */
37837 /* ========================================================  PDTTLR  ========================================================= */
37838  #define R_ETHERC_EPTPC_PDTTLR_PDTL_Pos            (0UL)          /*!< PDTL (Bit 0)                                          */
37839  #define R_ETHERC_EPTPC_PDTTLR_PDTL_Msk            (0xffUL)       /*!< PDTL (Bitfield-Mask: 0xff)                            */
37840 /* ========================================================  PEUDPR  ========================================================= */
37841  #define R_ETHERC_EPTPC_PEUDPR_EVUPT_Pos           (0UL)          /*!< EVUPT (Bit 0)                                         */
37842  #define R_ETHERC_EPTPC_PEUDPR_EVUPT_Msk           (0xffffUL)     /*!< EVUPT (Bitfield-Mask: 0xffff)                         */
37843 /* ========================================================  PGUDPR  ========================================================= */
37844  #define R_ETHERC_EPTPC_PGUDPR_GEUPT_Pos           (0UL)          /*!< GEUPT (Bit 0)                                         */
37845  #define R_ETHERC_EPTPC_PGUDPR_GEUPT_Msk           (0xffffUL)     /*!< GEUPT (Bitfield-Mask: 0xffff)                         */
37846 /* =========================================================  FFLTR  ========================================================= */
37847  #define R_ETHERC_EPTPC_FFLTR_EXTPRM_Pos           (16UL)         /*!< EXTPRM (Bit 16)                                       */
37848  #define R_ETHERC_EPTPC_FFLTR_EXTPRM_Msk           (0x10000UL)    /*!< EXTPRM (Bitfield-Mask: 0x01)                          */
37849  #define R_ETHERC_EPTPC_FFLTR_ENB_Pos              (2UL)          /*!< ENB (Bit 2)                                           */
37850  #define R_ETHERC_EPTPC_FFLTR_ENB_Msk              (0x4UL)        /*!< ENB (Bitfield-Mask: 0x01)                             */
37851  #define R_ETHERC_EPTPC_FFLTR_PRT_Pos              (1UL)          /*!< PRT (Bit 1)                                           */
37852  #define R_ETHERC_EPTPC_FFLTR_PRT_Msk              (0x2UL)        /*!< PRT (Bitfield-Mask: 0x01)                             */
37853  #define R_ETHERC_EPTPC_FFLTR_SEL_Pos              (0UL)          /*!< SEL (Bit 0)                                           */
37854  #define R_ETHERC_EPTPC_FFLTR_SEL_Msk              (0x1UL)        /*!< SEL (Bitfield-Mask: 0x01)                             */
37855 /* ========================================================  FMAC0RU  ======================================================== */
37856  #define R_ETHERC_EPTPC_FMAC0RU_FMAC0RU_Pos        (0UL)          /*!< FMAC0RU (Bit 0)                                       */
37857  #define R_ETHERC_EPTPC_FMAC0RU_FMAC0RU_Msk        (0xffffffUL)   /*!< FMAC0RU (Bitfield-Mask: 0xffffff)                     */
37858 /* ========================================================  FMAC0RL  ======================================================== */
37859  #define R_ETHERC_EPTPC_FMAC0RL_FMAC0RL_Pos        (0UL)          /*!< FMAC0RL (Bit 0)                                       */
37860  #define R_ETHERC_EPTPC_FMAC0RL_FMAC0RL_Msk        (0xffffffUL)   /*!< FMAC0RL (Bitfield-Mask: 0xffffff)                     */
37861 /* ========================================================  FMAC1RU  ======================================================== */
37862  #define R_ETHERC_EPTPC_FMAC1RU_FMAC1RU_Pos        (0UL)          /*!< FMAC1RU (Bit 0)                                       */
37863  #define R_ETHERC_EPTPC_FMAC1RU_FMAC1RU_Msk        (0xffffffUL)   /*!< FMAC1RU (Bitfield-Mask: 0xffffff)                     */
37864 /* ========================================================  FMAC1RL  ======================================================== */
37865  #define R_ETHERC_EPTPC_FMAC1RL_FMAC1RL_Pos        (0UL)          /*!< FMAC1RL (Bit 0)                                       */
37866  #define R_ETHERC_EPTPC_FMAC1RL_FMAC1RL_Msk        (0xffffffUL)   /*!< FMAC1RL (Bitfield-Mask: 0xffffff)                     */
37867 /* ========================================================  DASYMRU  ======================================================== */
37868  #define R_ETHERC_EPTPC_DASYMRU_DASYMRU_Pos        (0UL)          /*!< DASYMRU (Bit 0)                                       */
37869  #define R_ETHERC_EPTPC_DASYMRU_DASYMRU_Msk        (0xffffUL)     /*!< DASYMRU (Bitfield-Mask: 0xffff)                       */
37870 /* ========================================================  DASYMRL  ======================================================== */
37871  #define R_ETHERC_EPTPC_DASYMRL_DASYMRL_Pos        (0UL)          /*!< DASYMRL (Bit 0)                                       */
37872  #define R_ETHERC_EPTPC_DASYMRL_DASYMRL_Msk        (0xffffffffUL) /*!< DASYMRL (Bitfield-Mask: 0xffffffff)                   */
37873 /* ========================================================  TSLATR  ========================================================= */
37874  #define R_ETHERC_EPTPC_TSLATR_INGP_Pos            (16UL)         /*!< INGP (Bit 16)                                         */
37875  #define R_ETHERC_EPTPC_TSLATR_INGP_Msk            (0xffff0000UL) /*!< INGP (Bitfield-Mask: 0xffff)                          */
37876  #define R_ETHERC_EPTPC_TSLATR_EGP_Pos             (0UL)          /*!< EGP (Bit 0)                                           */
37877  #define R_ETHERC_EPTPC_TSLATR_EGP_Msk             (0xffffUL)     /*!< EGP (Bitfield-Mask: 0xffff)                           */
37878 /* ========================================================  SYCONFR  ======================================================== */
37879  #define R_ETHERC_EPTPC_SYCONFR_TCMOD_Pos          (20UL)         /*!< TCMOD (Bit 20)                                        */
37880  #define R_ETHERC_EPTPC_SYCONFR_TCMOD_Msk          (0x100000UL)   /*!< TCMOD (Bitfield-Mask: 0x01)                           */
37881  #define R_ETHERC_EPTPC_SYCONFR_FILDIS_Pos         (16UL)         /*!< FILDIS (Bit 16)                                       */
37882  #define R_ETHERC_EPTPC_SYCONFR_FILDIS_Msk         (0x10000UL)    /*!< FILDIS (Bitfield-Mask: 0x01)                          */
37883  #define R_ETHERC_EPTPC_SYCONFR_SBDIS_Pos          (12UL)         /*!< SBDIS (Bit 12)                                        */
37884  #define R_ETHERC_EPTPC_SYCONFR_SBDIS_Msk          (0x1000UL)     /*!< SBDIS (Bitfield-Mask: 0x01)                           */
37885  #define R_ETHERC_EPTPC_SYCONFR_TCYC_Pos           (0UL)          /*!< TCYC (Bit 0)                                          */
37886  #define R_ETHERC_EPTPC_SYCONFR_TCYC_Msk           (0xffUL)       /*!< TCYC (Bitfield-Mask: 0xff)                            */
37887 /* ========================================================  SYFORMR  ======================================================== */
37888  #define R_ETHERC_EPTPC_SYFORMR_FORM1_Pos          (1UL)          /*!< FORM1 (Bit 1)                                         */
37889  #define R_ETHERC_EPTPC_SYFORMR_FORM1_Msk          (0x2UL)        /*!< FORM1 (Bitfield-Mask: 0x01)                           */
37890  #define R_ETHERC_EPTPC_SYFORMR_FORM0_Pos          (0UL)          /*!< FORM0 (Bit 0)                                         */
37891  #define R_ETHERC_EPTPC_SYFORMR_FORM0_Msk          (0x1UL)        /*!< FORM0 (Bitfield-Mask: 0x01)                           */
37892 /* ========================================================  RSTOUTR  ======================================================== */
37893  #define R_ETHERC_EPTPC_RSTOUTR_RSTOUTR_Pos        (0UL)          /*!< RSTOUTR (Bit 0)                                       */
37894  #define R_ETHERC_EPTPC_RSTOUTR_RSTOUTR_Msk        (0xffffffffUL) /*!< RSTOUTR (Bitfield-Mask: 0xffffffff)                   */
37895 
37896 /* =========================================================================================================================== */
37897 /* ================                                    R_ETHERC_EPTPC_CFG                                     ================ */
37898 /* =========================================================================================================================== */
37899 
37900 /* ========================================================  PTRSTR  ========================================================= */
37901  #define R_ETHERC_EPTPC_CFG_PTRSTR_RESET_Pos       (0UL)       /*!< RESET (Bit 0)                                         */
37902  #define R_ETHERC_EPTPC_CFG_PTRSTR_RESET_Msk       (0x1UL)     /*!< RESET (Bitfield-Mask: 0x01)                           */
37903 /* ========================================================  STCSELR  ======================================================== */
37904  #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKSEL_Pos    (8UL)       /*!< SCLKSEL (Bit 8)                                       */
37905  #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKSEL_Msk    (0x700UL)   /*!< SCLKSEL (Bitfield-Mask: 0x07)                         */
37906  #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKDIV_Pos    (0UL)       /*!< SCLKDIV (Bit 0)                                       */
37907  #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKDIV_Msk    (0x7UL)     /*!< SCLKDIV (Bitfield-Mask: 0x07)                         */
37908 /* ========================================================  BYPASS  ========================================================= */
37909  #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS1_Pos     (16UL)      /*!< BYPASS1 (Bit 16)                                      */
37910  #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS1_Msk     (0x10000UL) /*!< BYPASS1 (Bitfield-Mask: 0x01)                         */
37911  #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS0_Pos     (0UL)       /*!< BYPASS0 (Bit 0)                                       */
37912  #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS0_Msk     (0x1UL)     /*!< BYPASS0 (Bitfield-Mask: 0x01)                         */
37913 
37914 /* =========================================================================================================================== */
37915 /* ================                                   R_ETHERC_EPTPC_COMMON                                   ================ */
37916 /* =========================================================================================================================== */
37917 
37918 /* =========================================================  MIESR  ========================================================= */
37919  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC5_Pos           (21UL)         /*!< CYC5 (Bit 21)                                         */
37920  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC5_Msk           (0x200000UL)   /*!< CYC5 (Bitfield-Mask: 0x01)                            */
37921  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC4_Pos           (20UL)         /*!< CYC4 (Bit 20)                                         */
37922  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC4_Msk           (0x100000UL)   /*!< CYC4 (Bitfield-Mask: 0x01)                            */
37923  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC3_Pos           (19UL)         /*!< CYC3 (Bit 19)                                         */
37924  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC3_Msk           (0x80000UL)    /*!< CYC3 (Bitfield-Mask: 0x01)                            */
37925  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC2_Pos           (18UL)         /*!< CYC2 (Bit 18)                                         */
37926  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC2_Msk           (0x40000UL)    /*!< CYC2 (Bitfield-Mask: 0x01)                            */
37927  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC1_Pos           (17UL)         /*!< CYC1 (Bit 17)                                         */
37928  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC1_Msk           (0x20000UL)    /*!< CYC1 (Bitfield-Mask: 0x01)                            */
37929  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC0_Pos           (16UL)         /*!< CYC0 (Bit 16)                                         */
37930  #define R_ETHERC_EPTPC_COMMON_MIESR_CYC0_Msk           (0x10000UL)    /*!< CYC0 (Bitfield-Mask: 0x01)                            */
37931  #define R_ETHERC_EPTPC_COMMON_MIESR_PRC_Pos            (3UL)          /*!< PRC (Bit 3)                                           */
37932  #define R_ETHERC_EPTPC_COMMON_MIESR_PRC_Msk            (0x8UL)        /*!< PRC (Bitfield-Mask: 0x01)                             */
37933  #define R_ETHERC_EPTPC_COMMON_MIESR_SY1_Pos            (2UL)          /*!< SY1 (Bit 2)                                           */
37934  #define R_ETHERC_EPTPC_COMMON_MIESR_SY1_Msk            (0x4UL)        /*!< SY1 (Bitfield-Mask: 0x01)                             */
37935  #define R_ETHERC_EPTPC_COMMON_MIESR_SY0_Pos            (1UL)          /*!< SY0 (Bit 1)                                           */
37936  #define R_ETHERC_EPTPC_COMMON_MIESR_SY0_Msk            (0x2UL)        /*!< SY0 (Bitfield-Mask: 0x01)                             */
37937  #define R_ETHERC_EPTPC_COMMON_MIESR_ST_Pos             (0UL)          /*!< ST (Bit 0)                                            */
37938  #define R_ETHERC_EPTPC_COMMON_MIESR_ST_Msk             (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
37939 /* ========================================================  MIEIPR  ========================================================= */
37940  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC5_Pos          (21UL)         /*!< CYC5 (Bit 21)                                         */
37941  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC5_Msk          (0x200000UL)   /*!< CYC5 (Bitfield-Mask: 0x01)                            */
37942  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC4_Pos          (20UL)         /*!< CYC4 (Bit 20)                                         */
37943  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC4_Msk          (0x100000UL)   /*!< CYC4 (Bitfield-Mask: 0x01)                            */
37944  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC3_Pos          (19UL)         /*!< CYC3 (Bit 19)                                         */
37945  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC3_Msk          (0x80000UL)    /*!< CYC3 (Bitfield-Mask: 0x01)                            */
37946  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC2_Pos          (18UL)         /*!< CYC2 (Bit 18)                                         */
37947  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC2_Msk          (0x40000UL)    /*!< CYC2 (Bitfield-Mask: 0x01)                            */
37948  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC1_Pos          (17UL)         /*!< CYC1 (Bit 17)                                         */
37949  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC1_Msk          (0x20000UL)    /*!< CYC1 (Bitfield-Mask: 0x01)                            */
37950  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC0_Pos          (16UL)         /*!< CYC0 (Bit 16)                                         */
37951  #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC0_Msk          (0x10000UL)    /*!< CYC0 (Bitfield-Mask: 0x01)                            */
37952  #define R_ETHERC_EPTPC_COMMON_MIEIPR_PRC_Pos           (3UL)          /*!< PRC (Bit 3)                                           */
37953  #define R_ETHERC_EPTPC_COMMON_MIEIPR_PRC_Msk           (0x8UL)        /*!< PRC (Bitfield-Mask: 0x01)                             */
37954  #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY1_Pos           (2UL)          /*!< SY1 (Bit 2)                                           */
37955  #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY1_Msk           (0x4UL)        /*!< SY1 (Bitfield-Mask: 0x01)                             */
37956  #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY0_Pos           (1UL)          /*!< SY0 (Bit 1)                                           */
37957  #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY0_Msk           (0x2UL)        /*!< SY0 (Bitfield-Mask: 0x01)                             */
37958  #define R_ETHERC_EPTPC_COMMON_MIEIPR_ST_Pos            (0UL)          /*!< ST (Bit 0)                                            */
37959  #define R_ETHERC_EPTPC_COMMON_MIEIPR_ST_Msk            (0x1UL)        /*!< ST (Bitfield-Mask: 0x01)                              */
37960 /* ========================================================  ELIPPR  ========================================================= */
37961  #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSN_Pos          (24UL)         /*!< PLSN (Bit 24)                                         */
37962  #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSN_Msk          (0x1000000UL)  /*!< PLSN (Bitfield-Mask: 0x01)                            */
37963  #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSP_Pos          (16UL)         /*!< PLSP (Bit 16)                                         */
37964  #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSP_Msk          (0x10000UL)    /*!< PLSP (Bitfield-Mask: 0x01)                            */
37965  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN5_Pos         (13UL)         /*!< CYCN5 (Bit 13)                                        */
37966  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN5_Msk         (0x2000UL)     /*!< CYCN5 (Bitfield-Mask: 0x01)                           */
37967  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN4_Pos         (12UL)         /*!< CYCN4 (Bit 12)                                        */
37968  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN4_Msk         (0x1000UL)     /*!< CYCN4 (Bitfield-Mask: 0x01)                           */
37969  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN3_Pos         (11UL)         /*!< CYCN3 (Bit 11)                                        */
37970  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN3_Msk         (0x800UL)      /*!< CYCN3 (Bitfield-Mask: 0x01)                           */
37971  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN2_Pos         (10UL)         /*!< CYCN2 (Bit 10)                                        */
37972  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN2_Msk         (0x400UL)      /*!< CYCN2 (Bitfield-Mask: 0x01)                           */
37973  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN1_Pos         (9UL)          /*!< CYCN1 (Bit 9)                                         */
37974  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN1_Msk         (0x200UL)      /*!< CYCN1 (Bitfield-Mask: 0x01)                           */
37975  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN0_Pos         (8UL)          /*!< CYCN0 (Bit 8)                                         */
37976  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN0_Msk         (0x100UL)      /*!< CYCN0 (Bitfield-Mask: 0x01)                           */
37977  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP5_Pos         (5UL)          /*!< CYCP5 (Bit 5)                                         */
37978  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP5_Msk         (0x20UL)       /*!< CYCP5 (Bitfield-Mask: 0x01)                           */
37979  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP4_Pos         (4UL)          /*!< CYCP4 (Bit 4)                                         */
37980  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP4_Msk         (0x10UL)       /*!< CYCP4 (Bitfield-Mask: 0x01)                           */
37981  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP3_Pos         (3UL)          /*!< CYCP3 (Bit 3)                                         */
37982  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP3_Msk         (0x8UL)        /*!< CYCP3 (Bitfield-Mask: 0x01)                           */
37983  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP2_Pos         (2UL)          /*!< CYCP2 (Bit 2)                                         */
37984  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP2_Msk         (0x4UL)        /*!< CYCP2 (Bitfield-Mask: 0x01)                           */
37985  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP1_Pos         (1UL)          /*!< CYCP1 (Bit 1)                                         */
37986  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP1_Msk         (0x2UL)        /*!< CYCP1 (Bitfield-Mask: 0x01)                           */
37987  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP0_Pos         (0UL)          /*!< CYCP0 (Bit 0)                                         */
37988  #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP0_Msk         (0x1UL)        /*!< CYCP0 (Bitfield-Mask: 0x01)                           */
37989 /* ========================================================  ELIPACR  ======================================================== */
37990  #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSN_Pos         (24UL)         /*!< PLSN (Bit 24)                                         */
37991  #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSN_Msk         (0x1000000UL)  /*!< PLSN (Bitfield-Mask: 0x01)                            */
37992  #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSP_Pos         (16UL)         /*!< PLSP (Bit 16)                                         */
37993  #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSP_Msk         (0x10000UL)    /*!< PLSP (Bitfield-Mask: 0x01)                            */
37994  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN5_Pos        (13UL)         /*!< CYCN5 (Bit 13)                                        */
37995  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN5_Msk        (0x2000UL)     /*!< CYCN5 (Bitfield-Mask: 0x01)                           */
37996  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN4_Pos        (12UL)         /*!< CYCN4 (Bit 12)                                        */
37997  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN4_Msk        (0x1000UL)     /*!< CYCN4 (Bitfield-Mask: 0x01)                           */
37998  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN3_Pos        (11UL)         /*!< CYCN3 (Bit 11)                                        */
37999  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN3_Msk        (0x800UL)      /*!< CYCN3 (Bitfield-Mask: 0x01)                           */
38000  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN2_Pos        (10UL)         /*!< CYCN2 (Bit 10)                                        */
38001  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN2_Msk        (0x400UL)      /*!< CYCN2 (Bitfield-Mask: 0x01)                           */
38002  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN1_Pos        (9UL)          /*!< CYCN1 (Bit 9)                                         */
38003  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN1_Msk        (0x200UL)      /*!< CYCN1 (Bitfield-Mask: 0x01)                           */
38004  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN0_Pos        (8UL)          /*!< CYCN0 (Bit 8)                                         */
38005  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN0_Msk        (0x100UL)      /*!< CYCN0 (Bitfield-Mask: 0x01)                           */
38006  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP5_Pos        (5UL)          /*!< CYCP5 (Bit 5)                                         */
38007  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP5_Msk        (0x20UL)       /*!< CYCP5 (Bitfield-Mask: 0x01)                           */
38008  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP4_Pos        (4UL)          /*!< CYCP4 (Bit 4)                                         */
38009  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP4_Msk        (0x10UL)       /*!< CYCP4 (Bitfield-Mask: 0x01)                           */
38010  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP3_Pos        (3UL)          /*!< CYCP3 (Bit 3)                                         */
38011  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP3_Msk        (0x8UL)        /*!< CYCP3 (Bitfield-Mask: 0x01)                           */
38012  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP2_Pos        (2UL)          /*!< CYCP2 (Bit 2)                                         */
38013  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP2_Msk        (0x4UL)        /*!< CYCP2 (Bitfield-Mask: 0x01)                           */
38014  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP1_Pos        (1UL)          /*!< CYCP1 (Bit 1)                                         */
38015  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP1_Msk        (0x2UL)        /*!< CYCP1 (Bitfield-Mask: 0x01)                           */
38016  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP0_Pos        (0UL)          /*!< CYCP0 (Bit 0)                                         */
38017  #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP0_Msk        (0x1UL)        /*!< CYCP0 (Bitfield-Mask: 0x01)                           */
38018 /* =========================================================  STSR  ========================================================== */
38019  #define R_ETHERC_EPTPC_COMMON_STSR_W10D_Pos            (4UL)          /*!< W10D (Bit 4)                                          */
38020  #define R_ETHERC_EPTPC_COMMON_STSR_W10D_Msk            (0x10UL)       /*!< W10D (Bitfield-Mask: 0x01)                            */
38021  #define R_ETHERC_EPTPC_COMMON_STSR_SYNTOUT_Pos         (3UL)          /*!< SYNTOUT (Bit 3)                                       */
38022  #define R_ETHERC_EPTPC_COMMON_STSR_SYNTOUT_Msk         (0x8UL)        /*!< SYNTOUT (Bitfield-Mask: 0x01)                         */
38023  #define R_ETHERC_EPTPC_COMMON_STSR_SYNCOUT_Pos         (1UL)          /*!< SYNCOUT (Bit 1)                                       */
38024  #define R_ETHERC_EPTPC_COMMON_STSR_SYNCOUT_Msk         (0x2UL)        /*!< SYNCOUT (Bitfield-Mask: 0x01)                         */
38025  #define R_ETHERC_EPTPC_COMMON_STSR_SYNC_Pos            (0UL)          /*!< SYNC (Bit 0)                                          */
38026  #define R_ETHERC_EPTPC_COMMON_STSR_SYNC_Msk            (0x1UL)        /*!< SYNC (Bitfield-Mask: 0x01)                            */
38027 /* =========================================================  STIPR  ========================================================= */
38028  #define R_ETHERC_EPTPC_COMMON_STIPR_W10D_Pos           (4UL)          /*!< W10D (Bit 4)                                          */
38029  #define R_ETHERC_EPTPC_COMMON_STIPR_W10D_Msk           (0x10UL)       /*!< W10D (Bitfield-Mask: 0x01)                            */
38030  #define R_ETHERC_EPTPC_COMMON_STIPR_SYNTOUT_Pos        (3UL)          /*!< SYNTOUT (Bit 3)                                       */
38031  #define R_ETHERC_EPTPC_COMMON_STIPR_SYNTOUT_Msk        (0x8UL)        /*!< SYNTOUT (Bitfield-Mask: 0x01)                         */
38032  #define R_ETHERC_EPTPC_COMMON_STIPR_SYNCOUT_Pos        (1UL)          /*!< SYNCOUT (Bit 1)                                       */
38033  #define R_ETHERC_EPTPC_COMMON_STIPR_SYNCOUT_Msk        (0x2UL)        /*!< SYNCOUT (Bitfield-Mask: 0x01)                         */
38034  #define R_ETHERC_EPTPC_COMMON_STIPR_SYNC_Pos           (0UL)          /*!< SYNC (Bit 0)                                          */
38035  #define R_ETHERC_EPTPC_COMMON_STIPR_SYNC_Msk           (0x1UL)        /*!< SYNC (Bitfield-Mask: 0x01)                            */
38036 /* =========================================================  STCFR  ========================================================= */
38037  #define R_ETHERC_EPTPC_COMMON_STCFR_STCF_Pos           (0UL)          /*!< STCF (Bit 0)                                          */
38038  #define R_ETHERC_EPTPC_COMMON_STCFR_STCF_Msk           (0x3UL)        /*!< STCF (Bitfield-Mask: 0x03)                            */
38039 /* =========================================================  STMR  ========================================================== */
38040  #define R_ETHERC_EPTPC_COMMON_STMR_ALEN1_Pos           (29UL)         /*!< ALEN1 (Bit 29)                                        */
38041  #define R_ETHERC_EPTPC_COMMON_STMR_ALEN1_Msk           (0x20000000UL) /*!< ALEN1 (Bitfield-Mask: 0x01)                           */
38042  #define R_ETHERC_EPTPC_COMMON_STMR_ALEN0_Pos           (28UL)         /*!< ALEN0 (Bit 28)                                        */
38043  #define R_ETHERC_EPTPC_COMMON_STMR_ALEN0_Msk           (0x10000000UL) /*!< ALEN0 (Bitfield-Mask: 0x01)                           */
38044  #define R_ETHERC_EPTPC_COMMON_STMR_DVTH_Pos            (20UL)         /*!< DVTH (Bit 20)                                         */
38045  #define R_ETHERC_EPTPC_COMMON_STMR_DVTH_Msk            (0xf00000UL)   /*!< DVTH (Bitfield-Mask: 0x0f)                            */
38046  #define R_ETHERC_EPTPC_COMMON_STMR_SYTH_Pos            (16UL)         /*!< SYTH (Bit 16)                                         */
38047  #define R_ETHERC_EPTPC_COMMON_STMR_SYTH_Msk            (0xf0000UL)    /*!< SYTH (Bitfield-Mask: 0x0f)                            */
38048  #define R_ETHERC_EPTPC_COMMON_STMR_W10S_Pos            (15UL)         /*!< W10S (Bit 15)                                         */
38049  #define R_ETHERC_EPTPC_COMMON_STMR_W10S_Msk            (0x8000UL)     /*!< W10S (Bitfield-Mask: 0x01)                            */
38050  #define R_ETHERC_EPTPC_COMMON_STMR_CMOD_Pos            (13UL)         /*!< CMOD (Bit 13)                                         */
38051  #define R_ETHERC_EPTPC_COMMON_STMR_CMOD_Msk            (0x2000UL)     /*!< CMOD (Bitfield-Mask: 0x01)                            */
38052  #define R_ETHERC_EPTPC_COMMON_STMR_WINT_Pos            (0UL)          /*!< WINT (Bit 0)                                          */
38053  #define R_ETHERC_EPTPC_COMMON_STMR_WINT_Msk            (0xffUL)       /*!< WINT (Bitfield-Mask: 0xff)                            */
38054 /* ========================================================  SYNTOR  ========================================================= */
38055  #define R_ETHERC_EPTPC_COMMON_SYNTOR_SYNTOR_Pos        (0UL)          /*!< SYNTOR (Bit 0)                                        */
38056  #define R_ETHERC_EPTPC_COMMON_SYNTOR_SYNTOR_Msk        (0xffffffffUL) /*!< SYNTOR (Bitfield-Mask: 0xffffffff)                    */
38057 /* ========================================================  IPTSELR  ======================================================== */
38058  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL5_Pos      (5UL)          /*!< IPTSEL5 (Bit 5)                                       */
38059  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL5_Msk      (0x20UL)       /*!< IPTSEL5 (Bitfield-Mask: 0x01)                         */
38060  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL4_Pos      (4UL)          /*!< IPTSEL4 (Bit 4)                                       */
38061  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL4_Msk      (0x10UL)       /*!< IPTSEL4 (Bitfield-Mask: 0x01)                         */
38062  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL3_Pos      (3UL)          /*!< IPTSEL3 (Bit 3)                                       */
38063  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL3_Msk      (0x8UL)        /*!< IPTSEL3 (Bitfield-Mask: 0x01)                         */
38064  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL2_Pos      (2UL)          /*!< IPTSEL2 (Bit 2)                                       */
38065  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL2_Msk      (0x4UL)        /*!< IPTSEL2 (Bitfield-Mask: 0x01)                         */
38066  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL1_Pos      (1UL)          /*!< IPTSEL1 (Bit 1)                                       */
38067  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL1_Msk      (0x2UL)        /*!< IPTSEL1 (Bitfield-Mask: 0x01)                         */
38068  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL0_Pos      (0UL)          /*!< IPTSEL0 (Bit 0)                                       */
38069  #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL0_Msk      (0x1UL)        /*!< IPTSEL0 (Bitfield-Mask: 0x01)                         */
38070 /* ========================================================  MITSELR  ======================================================== */
38071  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN5_Pos      (5UL)          /*!< MINTEN5 (Bit 5)                                       */
38072  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN5_Msk      (0x20UL)       /*!< MINTEN5 (Bitfield-Mask: 0x01)                         */
38073  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN4_Pos      (4UL)          /*!< MINTEN4 (Bit 4)                                       */
38074  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN4_Msk      (0x10UL)       /*!< MINTEN4 (Bitfield-Mask: 0x01)                         */
38075  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN3_Pos      (3UL)          /*!< MINTEN3 (Bit 3)                                       */
38076  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN3_Msk      (0x8UL)        /*!< MINTEN3 (Bitfield-Mask: 0x01)                         */
38077  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN2_Pos      (2UL)          /*!< MINTEN2 (Bit 2)                                       */
38078  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN2_Msk      (0x4UL)        /*!< MINTEN2 (Bitfield-Mask: 0x01)                         */
38079  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN1_Pos      (1UL)          /*!< MINTEN1 (Bit 1)                                       */
38080  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN1_Msk      (0x2UL)        /*!< MINTEN1 (Bitfield-Mask: 0x01)                         */
38081  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN0_Pos      (0UL)          /*!< MINTEN0 (Bit 0)                                       */
38082  #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN0_Msk      (0x1UL)        /*!< MINTEN0 (Bitfield-Mask: 0x01)                         */
38083 /* ========================================================  ELTSELR  ======================================================== */
38084  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS5_Pos      (5UL)          /*!< ELTDIS5 (Bit 5)                                       */
38085  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS5_Msk      (0x20UL)       /*!< ELTDIS5 (Bitfield-Mask: 0x01)                         */
38086  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS4_Pos      (4UL)          /*!< ELTDIS4 (Bit 4)                                       */
38087  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS4_Msk      (0x10UL)       /*!< ELTDIS4 (Bitfield-Mask: 0x01)                         */
38088  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS3_Pos      (3UL)          /*!< ELTDIS3 (Bit 3)                                       */
38089  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS3_Msk      (0x8UL)        /*!< ELTDIS3 (Bitfield-Mask: 0x01)                         */
38090  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS2_Pos      (2UL)          /*!< ELTDIS2 (Bit 2)                                       */
38091  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS2_Msk      (0x4UL)        /*!< ELTDIS2 (Bitfield-Mask: 0x01)                         */
38092  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS1_Pos      (1UL)          /*!< ELTDIS1 (Bit 1)                                       */
38093  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS1_Msk      (0x2UL)        /*!< ELTDIS1 (Bitfield-Mask: 0x01)                         */
38094  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS0_Pos      (0UL)          /*!< ELTDIS0 (Bit 0)                                       */
38095  #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS0_Msk      (0x1UL)        /*!< ELTDIS0 (Bitfield-Mask: 0x01)                         */
38096 /* =======================================================  STCHSELR  ======================================================== */
38097  #define R_ETHERC_EPTPC_COMMON_STCHSELR_SYSEL_Pos       (0UL)          /*!< SYSEL (Bit 0)                                         */
38098  #define R_ETHERC_EPTPC_COMMON_STCHSELR_SYSEL_Msk       (0x1UL)        /*!< SYSEL (Bitfield-Mask: 0x01)                           */
38099 /* =======================================================  SYNSTARTR  ======================================================= */
38100  #define R_ETHERC_EPTPC_COMMON_SYNSTARTR_STR_Pos        (0UL)          /*!< STR (Bit 0)                                           */
38101  #define R_ETHERC_EPTPC_COMMON_SYNSTARTR_STR_Msk        (0x1UL)        /*!< STR (Bitfield-Mask: 0x01)                             */
38102 /* ========================================================  LCIVLDR  ======================================================== */
38103  #define R_ETHERC_EPTPC_COMMON_LCIVLDR_LOAD_Pos         (0UL)          /*!< LOAD (Bit 0)                                          */
38104  #define R_ETHERC_EPTPC_COMMON_LCIVLDR_LOAD_Msk         (0x1UL)        /*!< LOAD (Bitfield-Mask: 0x01)                            */
38105 /* =======================================================  SYNTDARU  ======================================================== */
38106  #define R_ETHERC_EPTPC_COMMON_SYNTDARU_SYNTDARU_Pos    (0UL)          /*!< SYNTDARU (Bit 0)                                      */
38107  #define R_ETHERC_EPTPC_COMMON_SYNTDARU_SYNTDARU_Msk    (0xffffffffUL) /*!< SYNTDARU (Bitfield-Mask: 0xffffffff)                  */
38108 /* =======================================================  SYNTDARL  ======================================================== */
38109  #define R_ETHERC_EPTPC_COMMON_SYNTDARL_SYNTDARL_Pos    (0UL)          /*!< SYNTDARL (Bit 0)                                      */
38110  #define R_ETHERC_EPTPC_COMMON_SYNTDARL_SYNTDARL_Msk    (0xffffffffUL) /*!< SYNTDARL (Bitfield-Mask: 0xffffffff)                  */
38111 /* =======================================================  SYNTDBRU  ======================================================== */
38112  #define R_ETHERC_EPTPC_COMMON_SYNTDBRU_SYNTDBRU_Pos    (0UL)          /*!< SYNTDBRU (Bit 0)                                      */
38113  #define R_ETHERC_EPTPC_COMMON_SYNTDBRU_SYNTDBRU_Msk    (0xffffffffUL) /*!< SYNTDBRU (Bitfield-Mask: 0xffffffff)                  */
38114 /* =======================================================  SYNTDBRL  ======================================================== */
38115  #define R_ETHERC_EPTPC_COMMON_SYNTDBRL_SYNTDBRL_Pos    (0UL)          /*!< SYNTDBRL (Bit 0)                                      */
38116  #define R_ETHERC_EPTPC_COMMON_SYNTDBRL_SYNTDBRL_Msk    (0xffffffffUL) /*!< SYNTDBRL (Bitfield-Mask: 0xffffffff)                  */
38117 /* ========================================================  LCIVRU  ========================================================= */
38118  #define R_ETHERC_EPTPC_COMMON_LCIVRU_LCIVRU_Pos        (0UL)          /*!< LCIVRU (Bit 0)                                        */
38119  #define R_ETHERC_EPTPC_COMMON_LCIVRU_LCIVRU_Msk        (0xffffUL)     /*!< LCIVRU (Bitfield-Mask: 0xffff)                        */
38120 /* ========================================================  LCIVRM  ========================================================= */
38121  #define R_ETHERC_EPTPC_COMMON_LCIVRM_LCIVRM_Pos        (0UL)          /*!< LCIVRM (Bit 0)                                        */
38122  #define R_ETHERC_EPTPC_COMMON_LCIVRM_LCIVRM_Msk        (0xffffffffUL) /*!< LCIVRM (Bitfield-Mask: 0xffffffff)                    */
38123 /* ========================================================  LCIVRL  ========================================================= */
38124  #define R_ETHERC_EPTPC_COMMON_LCIVRL_LCIVRL_Pos        (0UL)          /*!< LCIVRL (Bit 0)                                        */
38125  #define R_ETHERC_EPTPC_COMMON_LCIVRL_LCIVRL_Msk        (0xffffffffUL) /*!< LCIVRL (Bitfield-Mask: 0xffffffff)                    */
38126 /* ========================================================  GETW10R  ======================================================== */
38127  #define R_ETHERC_EPTPC_COMMON_GETW10R_GW10_Pos         (0UL)          /*!< GW10 (Bit 0)                                          */
38128  #define R_ETHERC_EPTPC_COMMON_GETW10R_GW10_Msk         (0x1UL)        /*!< GW10 (Bitfield-Mask: 0x01)                            */
38129 /* =======================================================  PLIMITRU  ======================================================== */
38130  #define R_ETHERC_EPTPC_COMMON_PLIMITRU_PLIMITRU_Pos    (0UL)          /*!< PLIMITRU (Bit 0)                                      */
38131  #define R_ETHERC_EPTPC_COMMON_PLIMITRU_PLIMITRU_Msk    (0x7fffffffUL) /*!< PLIMITRU (Bitfield-Mask: 0x7fffffff)                  */
38132 /* =======================================================  PLIMITRM  ======================================================== */
38133  #define R_ETHERC_EPTPC_COMMON_PLIMITRM_PLIMITRM_Pos    (0UL)          /*!< PLIMITRM (Bit 0)                                      */
38134  #define R_ETHERC_EPTPC_COMMON_PLIMITRM_PLIMITRM_Msk    (0xffffffffUL) /*!< PLIMITRM (Bitfield-Mask: 0xffffffff)                  */
38135 /* =======================================================  PLIMITRL  ======================================================== */
38136  #define R_ETHERC_EPTPC_COMMON_PLIMITRL_PLIMITRL_Pos    (0UL)          /*!< PLIMITRL (Bit 0)                                      */
38137  #define R_ETHERC_EPTPC_COMMON_PLIMITRL_PLIMITRL_Msk    (0xffffffffUL) /*!< PLIMITRL (Bitfield-Mask: 0xffffffff)                  */
38138 /* =======================================================  MLIMITRU  ======================================================== */
38139  #define R_ETHERC_EPTPC_COMMON_MLIMITRU_MLIMITRU_Pos    (0UL)          /*!< MLIMITRU (Bit 0)                                      */
38140  #define R_ETHERC_EPTPC_COMMON_MLIMITRU_MLIMITRU_Msk    (0x7fffffffUL) /*!< MLIMITRU (Bitfield-Mask: 0x7fffffff)                  */
38141 /* =======================================================  MLIMITRM  ======================================================== */
38142  #define R_ETHERC_EPTPC_COMMON_MLIMITRM_MLIMITRM_Pos    (0UL)          /*!< MLIMITRM (Bit 0)                                      */
38143  #define R_ETHERC_EPTPC_COMMON_MLIMITRM_MLIMITRM_Msk    (0xffffffffUL) /*!< MLIMITRM (Bitfield-Mask: 0xffffffff)                  */
38144 /* =======================================================  MLIMITRL  ======================================================== */
38145  #define R_ETHERC_EPTPC_COMMON_MLIMITRL_MLIMITRL_Pos    (0UL)          /*!< MLIMITRL (Bit 0)                                      */
38146  #define R_ETHERC_EPTPC_COMMON_MLIMITRL_MLIMITRL_Msk    (0xffffffffUL) /*!< MLIMITRL (Bitfield-Mask: 0xffffffff)                  */
38147 /* =======================================================  GETINFOR  ======================================================== */
38148  #define R_ETHERC_EPTPC_COMMON_GETINFOR_INFO_Pos        (0UL)          /*!< INFO (Bit 0)                                          */
38149  #define R_ETHERC_EPTPC_COMMON_GETINFOR_INFO_Msk        (0x1UL)        /*!< INFO (Bitfield-Mask: 0x01)                            */
38150 /* ========================================================  LCCVRU  ========================================================= */
38151  #define R_ETHERC_EPTPC_COMMON_LCCVRU_LCCVRU_Pos        (0UL)          /*!< LCCVRU (Bit 0)                                        */
38152  #define R_ETHERC_EPTPC_COMMON_LCCVRU_LCCVRU_Msk        (0xffffUL)     /*!< LCCVRU (Bitfield-Mask: 0xffff)                        */
38153 /* ========================================================  LCCVRM  ========================================================= */
38154  #define R_ETHERC_EPTPC_COMMON_LCCVRM_LCCVRM_Pos        (0UL)          /*!< LCCVRM (Bit 0)                                        */
38155  #define R_ETHERC_EPTPC_COMMON_LCCVRM_LCCVRM_Msk        (0xffffffffUL) /*!< LCCVRM (Bitfield-Mask: 0xffffffff)                    */
38156 /* ========================================================  LCCVRL  ========================================================= */
38157  #define R_ETHERC_EPTPC_COMMON_LCCVRL_LCCVRL_Pos        (0UL)          /*!< LCCVRL (Bit 0)                                        */
38158  #define R_ETHERC_EPTPC_COMMON_LCCVRL_LCCVRL_Msk        (0xffffffffUL) /*!< LCCVRL (Bitfield-Mask: 0xffffffff)                    */
38159 /* ========================================================  PW10VRU  ======================================================== */
38160  #define R_ETHERC_EPTPC_COMMON_PW10VRU_PW10VRU_Pos      (0UL)          /*!< PW10VRU (Bit 0)                                       */
38161  #define R_ETHERC_EPTPC_COMMON_PW10VRU_PW10VRU_Msk      (0xffffffffUL) /*!< PW10VRU (Bitfield-Mask: 0xffffffff)                   */
38162 /* ========================================================  PW10VRM  ======================================================== */
38163  #define R_ETHERC_EPTPC_COMMON_PW10VRM_PW10VRM_Pos      (0UL)          /*!< PW10VRM (Bit 0)                                       */
38164  #define R_ETHERC_EPTPC_COMMON_PW10VRM_PW10VRM_Msk      (0xffffffffUL) /*!< PW10VRM (Bitfield-Mask: 0xffffffff)                   */
38165 /* ========================================================  PW10VRL  ======================================================== */
38166  #define R_ETHERC_EPTPC_COMMON_PW10VRL_PW10VRL_Pos      (0UL)          /*!< PW10VRL (Bit 0)                                       */
38167  #define R_ETHERC_EPTPC_COMMON_PW10VRL_PW10VRL_Msk      (0xffffffffUL) /*!< PW10VRL (Bitfield-Mask: 0xffffffff)                   */
38168 /* ========================================================  MW10RU  ========================================================= */
38169  #define R_ETHERC_EPTPC_COMMON_MW10RU_MW10RU_Pos        (0UL)          /*!< MW10RU (Bit 0)                                        */
38170  #define R_ETHERC_EPTPC_COMMON_MW10RU_MW10RU_Msk        (0xffffffffUL) /*!< MW10RU (Bitfield-Mask: 0xffffffff)                    */
38171 /* ========================================================  MW10RM  ========================================================= */
38172  #define R_ETHERC_EPTPC_COMMON_MW10RM_MW10RM_Pos        (0UL)          /*!< MW10RM (Bit 0)                                        */
38173  #define R_ETHERC_EPTPC_COMMON_MW10RM_MW10RM_Msk        (0xffffffffUL) /*!< MW10RM (Bitfield-Mask: 0xffffffff)                    */
38174 /* ========================================================  MW10RL  ========================================================= */
38175  #define R_ETHERC_EPTPC_COMMON_MW10RL_MW10RL_Pos        (0UL)          /*!< MW10RL (Bit 0)                                        */
38176  #define R_ETHERC_EPTPC_COMMON_MW10RL_MW10RL_Msk        (0xffffffffUL) /*!< MW10RL (Bitfield-Mask: 0xffffffff)                    */
38177 /* =======================================================  TMSTARTR  ======================================================== */
38178  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN5_Pos         (5UL)          /*!< EN5 (Bit 5)                                           */
38179  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN5_Msk         (0x20UL)       /*!< EN5 (Bitfield-Mask: 0x01)                             */
38180  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN4_Pos         (4UL)          /*!< EN4 (Bit 4)                                           */
38181  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN4_Msk         (0x10UL)       /*!< EN4 (Bitfield-Mask: 0x01)                             */
38182  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN3_Pos         (3UL)          /*!< EN3 (Bit 3)                                           */
38183  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN3_Msk         (0x8UL)        /*!< EN3 (Bitfield-Mask: 0x01)                             */
38184  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN2_Pos         (2UL)          /*!< EN2 (Bit 2)                                           */
38185  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN2_Msk         (0x4UL)        /*!< EN2 (Bitfield-Mask: 0x01)                             */
38186  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN1_Pos         (1UL)          /*!< EN1 (Bit 1)                                           */
38187  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN1_Msk         (0x2UL)        /*!< EN1 (Bitfield-Mask: 0x01)                             */
38188  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN0_Pos         (0UL)          /*!< EN0 (Bit 0)                                           */
38189  #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN0_Msk         (0x1UL)        /*!< EN0 (Bitfield-Mask: 0x01)                             */
38190 /* =========================================================  PRSR  ========================================================== */
38191  #define R_ETHERC_EPTPC_COMMON_PRSR_URE1_Pos            (29UL)         /*!< URE1 (Bit 29)                                         */
38192  #define R_ETHERC_EPTPC_COMMON_PRSR_URE1_Msk            (0x20000000UL) /*!< URE1 (Bitfield-Mask: 0x01)                            */
38193  #define R_ETHERC_EPTPC_COMMON_PRSR_URE0_Pos            (28UL)         /*!< URE0 (Bit 28)                                         */
38194  #define R_ETHERC_EPTPC_COMMON_PRSR_URE0_Msk            (0x10000000UL) /*!< URE0 (Bitfield-Mask: 0x01)                            */
38195  #define R_ETHERC_EPTPC_COMMON_PRSR_MACE_Pos            (8UL)          /*!< MACE (Bit 8)                                          */
38196  #define R_ETHERC_EPTPC_COMMON_PRSR_MACE_Msk            (0x100UL)      /*!< MACE (Bitfield-Mask: 0x01)                            */
38197  #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE3_Pos           (3UL)          /*!< OVRE3 (Bit 3)                                         */
38198  #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE3_Msk           (0x8UL)        /*!< OVRE3 (Bitfield-Mask: 0x01)                           */
38199  #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE2_Pos           (2UL)          /*!< OVRE2 (Bit 2)                                         */
38200  #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE2_Msk           (0x4UL)        /*!< OVRE2 (Bitfield-Mask: 0x01)                           */
38201  #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE1_Pos           (1UL)          /*!< OVRE1 (Bit 1)                                         */
38202  #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE1_Msk           (0x2UL)        /*!< OVRE1 (Bitfield-Mask: 0x01)                           */
38203  #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE0_Pos           (0UL)          /*!< OVRE0 (Bit 0)                                         */
38204  #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE0_Msk           (0x1UL)        /*!< OVRE0 (Bitfield-Mask: 0x01)                           */
38205 /* =========================================================  PRIPR  ========================================================= */
38206  #define R_ETHERC_EPTPC_COMMON_PRIPR_URE1_Pos           (29UL)         /*!< URE1 (Bit 29)                                         */
38207  #define R_ETHERC_EPTPC_COMMON_PRIPR_URE1_Msk           (0x20000000UL) /*!< URE1 (Bitfield-Mask: 0x01)                            */
38208  #define R_ETHERC_EPTPC_COMMON_PRIPR_URE0_Pos           (28UL)         /*!< URE0 (Bit 28)                                         */
38209  #define R_ETHERC_EPTPC_COMMON_PRIPR_URE0_Msk           (0x10000000UL) /*!< URE0 (Bitfield-Mask: 0x01)                            */
38210  #define R_ETHERC_EPTPC_COMMON_PRIPR_MACE_Pos           (8UL)          /*!< MACE (Bit 8)                                          */
38211  #define R_ETHERC_EPTPC_COMMON_PRIPR_MACE_Msk           (0x100UL)      /*!< MACE (Bitfield-Mask: 0x01)                            */
38212  #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE3_Pos          (3UL)          /*!< OVRE3 (Bit 3)                                         */
38213  #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE3_Msk          (0x8UL)        /*!< OVRE3 (Bitfield-Mask: 0x01)                           */
38214  #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE2_Pos          (2UL)          /*!< OVRE2 (Bit 2)                                         */
38215  #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE2_Msk          (0x4UL)        /*!< OVRE2 (Bitfield-Mask: 0x01)                           */
38216  #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE1_Pos          (1UL)          /*!< OVRE1 (Bit 1)                                         */
38217  #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE1_Msk          (0x2UL)        /*!< OVRE1 (Bitfield-Mask: 0x01)                           */
38218  #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE0_Pos          (0UL)          /*!< OVRE0 (Bit 0)                                         */
38219  #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE0_Msk          (0x1UL)        /*!< OVRE0 (Bitfield-Mask: 0x01)                           */
38220 /* ========================================================  TRNDISR  ======================================================== */
38221  #define R_ETHERC_EPTPC_COMMON_TRNDISR_TDIS_Pos         (0UL)          /*!< TDIS (Bit 0)                                          */
38222  #define R_ETHERC_EPTPC_COMMON_TRNDISR_TDIS_Msk         (0x3UL)        /*!< TDIS (Bitfield-Mask: 0x03)                            */
38223 /* =========================================================  TRNMR  ========================================================= */
38224  #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD1_Pos           (9UL)          /*!< FWD1 (Bit 9)                                          */
38225  #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD1_Msk           (0x200UL)      /*!< FWD1 (Bitfield-Mask: 0x01)                            */
38226  #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD0_Pos           (8UL)          /*!< FWD0 (Bit 8)                                          */
38227  #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD0_Msk           (0x100UL)      /*!< FWD0 (Bitfield-Mask: 0x01)                            */
38228  #define R_ETHERC_EPTPC_COMMON_TRNMR_MOD_Pos            (0UL)          /*!< MOD (Bit 0)                                           */
38229  #define R_ETHERC_EPTPC_COMMON_TRNMR_MOD_Msk            (0x1UL)        /*!< MOD (Bitfield-Mask: 0x01)                             */
38230 /* =======================================================  TRNCTTDR  ======================================================== */
38231  #define R_ETHERC_EPTPC_COMMON_TRNCTTDR_THVAL_Pos       (0UL)          /*!< THVAL (Bit 0)                                         */
38232  #define R_ETHERC_EPTPC_COMMON_TRNCTTDR_THVAL_Msk       (0x7ffUL)      /*!< THVAL (Bitfield-Mask: 0x7ff)                          */
38233 
38234 /* =========================================================================================================================== */
38235 /* ================                                       R_FACI_HP_CMD                                       ================ */
38236 /* =========================================================================================================================== */
38237 
38238 /* ======================================================  FACI_CMD16  ======================================================= */
38239 /* =======================================================  FACI_CMD8  ======================================================= */
38240 
38241 /* =========================================================================================================================== */
38242 /* ================                                         R_FACI_HP                                         ================ */
38243 /* =========================================================================================================================== */
38244 
38245 /* ========================================================  FASTAT  ========================================================= */
38246  #define R_FACI_HP_FASTAT_CFAE_Pos         (7UL)          /*!< CFAE (Bit 7)                                          */
38247  #define R_FACI_HP_FASTAT_CFAE_Msk         (0x80UL)       /*!< CFAE (Bitfield-Mask: 0x01)                            */
38248  #define R_FACI_HP_FASTAT_CMDLK_Pos        (4UL)          /*!< CMDLK (Bit 4)                                         */
38249  #define R_FACI_HP_FASTAT_CMDLK_Msk        (0x10UL)       /*!< CMDLK (Bitfield-Mask: 0x01)                           */
38250  #define R_FACI_HP_FASTAT_DFAE_Pos         (3UL)          /*!< DFAE (Bit 3)                                          */
38251  #define R_FACI_HP_FASTAT_DFAE_Msk         (0x8UL)        /*!< DFAE (Bitfield-Mask: 0x01)                            */
38252  #define R_FACI_HP_FASTAT_ECRCT_Pos        (0UL)          /*!< ECRCT (Bit 0)                                         */
38253  #define R_FACI_HP_FASTAT_ECRCT_Msk        (0x1UL)        /*!< ECRCT (Bitfield-Mask: 0x01)                           */
38254 /* ========================================================  FAEINT  ========================================================= */
38255  #define R_FACI_HP_FAEINT_CFAEIE_Pos       (7UL)          /*!< CFAEIE (Bit 7)                                        */
38256  #define R_FACI_HP_FAEINT_CFAEIE_Msk       (0x80UL)       /*!< CFAEIE (Bitfield-Mask: 0x01)                          */
38257  #define R_FACI_HP_FAEINT_CMDLKIE_Pos      (4UL)          /*!< CMDLKIE (Bit 4)                                       */
38258  #define R_FACI_HP_FAEINT_CMDLKIE_Msk      (0x10UL)       /*!< CMDLKIE (Bitfield-Mask: 0x01)                         */
38259  #define R_FACI_HP_FAEINT_DFAEIE_Pos       (3UL)          /*!< DFAEIE (Bit 3)                                        */
38260  #define R_FACI_HP_FAEINT_DFAEIE_Msk       (0x8UL)        /*!< DFAEIE (Bitfield-Mask: 0x01)                          */
38261  #define R_FACI_HP_FAEINT_ECRCTIE_Pos      (0UL)          /*!< ECRCTIE (Bit 0)                                       */
38262  #define R_FACI_HP_FAEINT_ECRCTIE_Msk      (0x1UL)        /*!< ECRCTIE (Bitfield-Mask: 0x01)                         */
38263 /* ========================================================  FRDYIE  ========================================================= */
38264  #define R_FACI_HP_FRDYIE_FRDYIE_Pos       (0UL)          /*!< FRDYIE (Bit 0)                                        */
38265  #define R_FACI_HP_FRDYIE_FRDYIE_Msk       (0x1UL)        /*!< FRDYIE (Bitfield-Mask: 0x01)                          */
38266 /* ========================================================  FSADDR  ========================================================= */
38267  #define R_FACI_HP_FSADDR_FSA_Pos          (0UL)          /*!< FSA (Bit 0)                                           */
38268  #define R_FACI_HP_FSADDR_FSA_Msk          (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff)                       */
38269 /* ========================================================  FEADDR  ========================================================= */
38270  #define R_FACI_HP_FEADDR_FEA_Pos          (0UL)          /*!< FEA (Bit 0)                                           */
38271  #define R_FACI_HP_FEADDR_FEA_Msk          (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff)                       */
38272 /* ========================================================  FMEPROT  ======================================================== */
38273  #define R_FACI_HP_FMEPROT_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
38274  #define R_FACI_HP_FMEPROT_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
38275  #define R_FACI_HP_FMEPROT_CEPROT_Pos      (0UL)          /*!< CEPROT (Bit 0)                                        */
38276  #define R_FACI_HP_FMEPROT_CEPROT_Msk      (0x1UL)        /*!< CEPROT (Bitfield-Mask: 0x01)                          */
38277 /* ========================================================  FBPROT0  ======================================================== */
38278  #define R_FACI_HP_FBPROT0_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
38279  #define R_FACI_HP_FBPROT0_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
38280  #define R_FACI_HP_FBPROT0_BPCN0_Pos       (0UL)          /*!< BPCN0 (Bit 0)                                         */
38281  #define R_FACI_HP_FBPROT0_BPCN0_Msk       (0x1UL)        /*!< BPCN0 (Bitfield-Mask: 0x01)                           */
38282 /* ========================================================  FBPROT1  ======================================================== */
38283  #define R_FACI_HP_FBPROT1_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
38284  #define R_FACI_HP_FBPROT1_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
38285  #define R_FACI_HP_FBPROT1_BPCN1_Pos       (0UL)          /*!< BPCN1 (Bit 0)                                         */
38286  #define R_FACI_HP_FBPROT1_BPCN1_Msk       (0x1UL)        /*!< BPCN1 (Bitfield-Mask: 0x01)                           */
38287 /* ========================================================  FSTATR  ========================================================= */
38288  #define R_FACI_HP_FSTATR_ILGCOMERR_Pos    (23UL)         /*!< ILGCOMERR (Bit 23)                                    */
38289  #define R_FACI_HP_FSTATR_ILGCOMERR_Msk    (0x800000UL)   /*!< ILGCOMERR (Bitfield-Mask: 0x01)                       */
38290  #define R_FACI_HP_FSTATR_FESETERR_Pos     (22UL)         /*!< FESETERR (Bit 22)                                     */
38291  #define R_FACI_HP_FSTATR_FESETERR_Msk     (0x400000UL)   /*!< FESETERR (Bitfield-Mask: 0x01)                        */
38292  #define R_FACI_HP_FSTATR_SECERR_Pos       (21UL)         /*!< SECERR (Bit 21)                                       */
38293  #define R_FACI_HP_FSTATR_SECERR_Msk       (0x200000UL)   /*!< SECERR (Bitfield-Mask: 0x01)                          */
38294  #define R_FACI_HP_FSTATR_OTERR_Pos        (20UL)         /*!< OTERR (Bit 20)                                        */
38295  #define R_FACI_HP_FSTATR_OTERR_Msk        (0x100000UL)   /*!< OTERR (Bitfield-Mask: 0x01)                           */
38296  #define R_FACI_HP_FSTATR_FRDY_Pos         (15UL)         /*!< FRDY (Bit 15)                                         */
38297  #define R_FACI_HP_FSTATR_FRDY_Msk         (0x8000UL)     /*!< FRDY (Bitfield-Mask: 0x01)                            */
38298  #define R_FACI_HP_FSTATR_ILGLERR_Pos      (14UL)         /*!< ILGLERR (Bit 14)                                      */
38299  #define R_FACI_HP_FSTATR_ILGLERR_Msk      (0x4000UL)     /*!< ILGLERR (Bitfield-Mask: 0x01)                         */
38300  #define R_FACI_HP_FSTATR_ERSERR_Pos       (13UL)         /*!< ERSERR (Bit 13)                                       */
38301  #define R_FACI_HP_FSTATR_ERSERR_Msk       (0x2000UL)     /*!< ERSERR (Bitfield-Mask: 0x01)                          */
38302  #define R_FACI_HP_FSTATR_PRGERR_Pos       (12UL)         /*!< PRGERR (Bit 12)                                       */
38303  #define R_FACI_HP_FSTATR_PRGERR_Msk       (0x1000UL)     /*!< PRGERR (Bitfield-Mask: 0x01)                          */
38304  #define R_FACI_HP_FSTATR_SUSRDY_Pos       (11UL)         /*!< SUSRDY (Bit 11)                                       */
38305  #define R_FACI_HP_FSTATR_SUSRDY_Msk       (0x800UL)      /*!< SUSRDY (Bitfield-Mask: 0x01)                          */
38306  #define R_FACI_HP_FSTATR_DBFULL_Pos       (10UL)         /*!< DBFULL (Bit 10)                                       */
38307  #define R_FACI_HP_FSTATR_DBFULL_Msk       (0x400UL)      /*!< DBFULL (Bitfield-Mask: 0x01)                          */
38308  #define R_FACI_HP_FSTATR_ERSSPD_Pos       (9UL)          /*!< ERSSPD (Bit 9)                                        */
38309  #define R_FACI_HP_FSTATR_ERSSPD_Msk       (0x200UL)      /*!< ERSSPD (Bitfield-Mask: 0x01)                          */
38310  #define R_FACI_HP_FSTATR_PRGSPD_Pos       (8UL)          /*!< PRGSPD (Bit 8)                                        */
38311  #define R_FACI_HP_FSTATR_PRGSPD_Msk       (0x100UL)      /*!< PRGSPD (Bitfield-Mask: 0x01)                          */
38312  #define R_FACI_HP_FSTATR_FLWEERR_Pos      (6UL)          /*!< FLWEERR (Bit 6)                                       */
38313  #define R_FACI_HP_FSTATR_FLWEERR_Msk      (0x40UL)       /*!< FLWEERR (Bitfield-Mask: 0x01)                         */
38314 /* ========================================================  FENTRYR  ======================================================== */
38315  #define R_FACI_HP_FENTRYR_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
38316  #define R_FACI_HP_FENTRYR_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
38317  #define R_FACI_HP_FENTRYR_FENTRYD_Pos     (7UL)          /*!< FENTRYD (Bit 7)                                       */
38318  #define R_FACI_HP_FENTRYR_FENTRYD_Msk     (0x80UL)       /*!< FENTRYD (Bitfield-Mask: 0x01)                         */
38319  #define R_FACI_HP_FENTRYR_FENTRYC_Pos     (0UL)          /*!< FENTRYC (Bit 0)                                       */
38320  #define R_FACI_HP_FENTRYR_FENTRYC_Msk     (0x1UL)        /*!< FENTRYC (Bitfield-Mask: 0x01)                         */
38321 /* =======================================================  FSUINITR  ======================================================== */
38322  #define R_FACI_HP_FSUINITR_KEY_Pos        (8UL)          /*!< KEY (Bit 8)                                           */
38323  #define R_FACI_HP_FSUINITR_KEY_Msk        (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
38324  #define R_FACI_HP_FSUINITR_SUINIT_Pos     (0UL)          /*!< SUINIT (Bit 0)                                        */
38325  #define R_FACI_HP_FSUINITR_SUINIT_Msk     (0x1UL)        /*!< SUINIT (Bitfield-Mask: 0x01)                          */
38326 /* =========================================================  FCMDR  ========================================================= */
38327  #define R_FACI_HP_FCMDR_CMDR_Pos          (8UL)          /*!< CMDR (Bit 8)                                          */
38328  #define R_FACI_HP_FCMDR_CMDR_Msk          (0xff00UL)     /*!< CMDR (Bitfield-Mask: 0xff)                            */
38329  #define R_FACI_HP_FCMDR_PCMDR_Pos         (0UL)          /*!< PCMDR (Bit 0)                                         */
38330  #define R_FACI_HP_FCMDR_PCMDR_Msk         (0xffUL)       /*!< PCMDR (Bitfield-Mask: 0xff)                           */
38331 /* ========================================================  FPESTAT  ======================================================== */
38332  #define R_FACI_HP_FPESTAT_PEERRST_Pos     (0UL)          /*!< PEERRST (Bit 0)                                       */
38333  #define R_FACI_HP_FPESTAT_PEERRST_Msk     (0xffUL)       /*!< PEERRST (Bitfield-Mask: 0xff)                         */
38334 /* ========================================================  FBCCNT  ========================================================= */
38335  #define R_FACI_HP_FBCCNT_BCDIR_Pos        (0UL)          /*!< BCDIR (Bit 0)                                         */
38336  #define R_FACI_HP_FBCCNT_BCDIR_Msk        (0x1UL)        /*!< BCDIR (Bitfield-Mask: 0x01)                           */
38337 /* ========================================================  FBCSTAT  ======================================================== */
38338  #define R_FACI_HP_FBCSTAT_BCST_Pos        (0UL)          /*!< BCST (Bit 0)                                          */
38339  #define R_FACI_HP_FBCSTAT_BCST_Msk        (0x1UL)        /*!< BCST (Bitfield-Mask: 0x01)                            */
38340 /* ========================================================  FPSADDR  ======================================================== */
38341  #define R_FACI_HP_FPSADDR_PSADR_Pos       (0UL)          /*!< PSADR (Bit 0)                                         */
38342  #define R_FACI_HP_FPSADDR_PSADR_Msk       (0x7ffffUL)    /*!< PSADR (Bitfield-Mask: 0x7ffff)                        */
38343 /* ========================================================  FAWMON  ========================================================= */
38344  #define R_FACI_HP_FAWMON_BTFLG_Pos        (31UL)         /*!< BTFLG (Bit 31)                                        */
38345  #define R_FACI_HP_FAWMON_BTFLG_Msk        (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01)                           */
38346  #define R_FACI_HP_FAWMON_FAWE_Pos         (16UL)         /*!< FAWE (Bit 16)                                         */
38347  #define R_FACI_HP_FAWMON_FAWE_Msk         (0x7ff0000UL)  /*!< FAWE (Bitfield-Mask: 0x7ff)                           */
38348  #define R_FACI_HP_FAWMON_FSPR_Pos         (15UL)         /*!< FSPR (Bit 15)                                         */
38349  #define R_FACI_HP_FAWMON_FSPR_Msk         (0x8000UL)     /*!< FSPR (Bitfield-Mask: 0x01)                            */
38350  #define R_FACI_HP_FAWMON_FAWS_Pos         (0UL)          /*!< FAWS (Bit 0)                                          */
38351  #define R_FACI_HP_FAWMON_FAWS_Msk         (0x7ffUL)      /*!< FAWS (Bitfield-Mask: 0x7ff)                           */
38352 /* =========================================================  FCPSR  ========================================================= */
38353  #define R_FACI_HP_FCPSR_ESUSPMD_Pos       (0UL)          /*!< ESUSPMD (Bit 0)                                       */
38354  #define R_FACI_HP_FCPSR_ESUSPMD_Msk       (0x1UL)        /*!< ESUSPMD (Bitfield-Mask: 0x01)                         */
38355 /* ========================================================  FPCKAR  ========================================================= */
38356  #define R_FACI_HP_FPCKAR_KEY_Pos          (8UL)          /*!< KEY (Bit 8)                                           */
38357  #define R_FACI_HP_FPCKAR_KEY_Msk          (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
38358  #define R_FACI_HP_FPCKAR_PCKA_Pos         (0UL)          /*!< PCKA (Bit 0)                                          */
38359  #define R_FACI_HP_FPCKAR_PCKA_Msk         (0xffUL)       /*!< PCKA (Bitfield-Mask: 0xff)                            */
38360 /* ========================================================  FSUACR  ========================================================= */
38361  #define R_FACI_HP_FSUACR_KEY_Pos          (8UL)          /*!< KEY (Bit 8)                                           */
38362  #define R_FACI_HP_FSUACR_KEY_Msk          (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
38363  #define R_FACI_HP_FSUACR_SAS_Pos          (0UL)          /*!< SAS (Bit 0)                                           */
38364  #define R_FACI_HP_FSUACR_SAS_Msk          (0x3UL)        /*!< SAS (Bitfield-Mask: 0x03)                             */
38365 
38366 /* =========================================================================================================================== */
38367 /* ================                                         R_FACI_LP                                         ================ */
38368 /* =========================================================================================================================== */
38369 
38370 /* ========================================================  DFLCTL  ========================================================= */
38371 /* =========================================================  FPMCR  ========================================================= */
38372  #define R_FACI_LP_FPMCR_FMS2_Pos           (7UL)      /*!< FMS2 (Bit 7)                                          */
38373  #define R_FACI_LP_FPMCR_FMS2_Msk           (0x80UL)   /*!< FMS2 (Bitfield-Mask: 0x01)                            */
38374  #define R_FACI_LP_FPMCR_VLPE_Pos           (6UL)      /*!< VLPE (Bit 6)                                          */
38375  #define R_FACI_LP_FPMCR_VLPE_Msk           (0x40UL)   /*!< VLPE (Bitfield-Mask: 0x01)                            */
38376  #define R_FACI_LP_FPMCR_FMS1_Pos           (4UL)      /*!< FMS1 (Bit 4)                                          */
38377  #define R_FACI_LP_FPMCR_FMS1_Msk           (0x10UL)   /*!< FMS1 (Bitfield-Mask: 0x01)                            */
38378  #define R_FACI_LP_FPMCR_RPDIS_Pos          (3UL)      /*!< RPDIS (Bit 3)                                         */
38379  #define R_FACI_LP_FPMCR_RPDIS_Msk          (0x8UL)    /*!< RPDIS (Bitfield-Mask: 0x01)                           */
38380  #define R_FACI_LP_FPMCR_FMS0_Pos           (1UL)      /*!< FMS0 (Bit 1)                                          */
38381  #define R_FACI_LP_FPMCR_FMS0_Msk           (0x2UL)    /*!< FMS0 (Bitfield-Mask: 0x01)                            */
38382 /* =========================================================  FASR  ========================================================== */
38383  #define R_FACI_LP_FASR_EXS_Pos             (0UL)      /*!< EXS (Bit 0)                                           */
38384  #define R_FACI_LP_FASR_EXS_Msk             (0x1UL)    /*!< EXS (Bitfield-Mask: 0x01)                             */
38385 /* =========================================================  FSARL  ========================================================= */
38386  #define R_FACI_LP_FSARL_FSAR15_0_Pos       (0UL)      /*!< FSAR15_0 (Bit 0)                                      */
38387  #define R_FACI_LP_FSARL_FSAR15_0_Msk       (0xffffUL) /*!< FSAR15_0 (Bitfield-Mask: 0xffff)                      */
38388 /* =========================================================  FSARH  ========================================================= */
38389  #define R_FACI_LP_FSARH_FSAR31_25_Pos      (9UL)      /*!< FSAR31_25 (Bit 9)                                     */
38390  #define R_FACI_LP_FSARH_FSAR31_25_Msk      (0xfe00UL) /*!< FSAR31_25 (Bitfield-Mask: 0x7f)                       */
38391  #define R_FACI_LP_FSARH_FSAR20_16_Pos      (0UL)      /*!< FSAR20_16 (Bit 0)                                     */
38392  #define R_FACI_LP_FSARH_FSAR20_16_Msk      (0x1fUL)   /*!< FSAR20_16 (Bitfield-Mask: 0x1f)                       */
38393 /* ==========================================================  FCR  ========================================================== */
38394  #define R_FACI_LP_FCR_OPST_Pos             (7UL)      /*!< OPST (Bit 7)                                          */
38395  #define R_FACI_LP_FCR_OPST_Msk             (0x80UL)   /*!< OPST (Bitfield-Mask: 0x01)                            */
38396  #define R_FACI_LP_FCR_STOP_Pos             (6UL)      /*!< STOP (Bit 6)                                          */
38397  #define R_FACI_LP_FCR_STOP_Msk             (0x40UL)   /*!< STOP (Bitfield-Mask: 0x01)                            */
38398  #define R_FACI_LP_FCR_DRC_Pos              (4UL)      /*!< DRC (Bit 4)                                           */
38399  #define R_FACI_LP_FCR_DRC_Msk              (0x10UL)   /*!< DRC (Bitfield-Mask: 0x01)                             */
38400  #define R_FACI_LP_FCR_CMD_Pos              (0UL)      /*!< CMD (Bit 0)                                           */
38401  #define R_FACI_LP_FCR_CMD_Msk              (0xfUL)    /*!< CMD (Bitfield-Mask: 0x0f)                             */
38402 /* =========================================================  FEARL  ========================================================= */
38403  #define R_FACI_LP_FEARL_FEAR15_0_Pos       (0UL)      /*!< FEAR15_0 (Bit 0)                                      */
38404  #define R_FACI_LP_FEARL_FEAR15_0_Msk       (0xffffUL) /*!< FEAR15_0 (Bitfield-Mask: 0xffff)                      */
38405 /* =========================================================  FEARH  ========================================================= */
38406  #define R_FACI_LP_FEARH_FEAR31_25_Pos      (9UL)      /*!< FEAR31_25 (Bit 9)                                     */
38407  #define R_FACI_LP_FEARH_FEAR31_25_Msk      (0xfe00UL) /*!< FEAR31_25 (Bitfield-Mask: 0x7f)                       */
38408  #define R_FACI_LP_FEARH_FEAR20_16_Pos      (0UL)      /*!< FEAR20_16 (Bit 0)                                     */
38409  #define R_FACI_LP_FEARH_FEAR20_16_Msk      (0x1fUL)   /*!< FEAR20_16 (Bitfield-Mask: 0x1f)                       */
38410 /* ========================================================  FRESETR  ======================================================== */
38411  #define R_FACI_LP_FRESETR_FRESET_Pos       (0UL)      /*!< FRESET (Bit 0)                                        */
38412  #define R_FACI_LP_FRESETR_FRESET_Msk       (0x1UL)    /*!< FRESET (Bitfield-Mask: 0x01)                          */
38413 /* =======================================================  FSTATR00  ======================================================== */
38414  #define R_FACI_LP_FSTATR00_EILGLERR_Pos    (5UL)      /*!< EILGLERR (Bit 5)                                      */
38415  #define R_FACI_LP_FSTATR00_EILGLERR_Msk    (0x20UL)   /*!< EILGLERR (Bitfield-Mask: 0x01)                        */
38416  #define R_FACI_LP_FSTATR00_ILGLERR_Pos     (4UL)      /*!< ILGLERR (Bit 4)                                       */
38417  #define R_FACI_LP_FSTATR00_ILGLERR_Msk     (0x10UL)   /*!< ILGLERR (Bitfield-Mask: 0x01)                         */
38418  #define R_FACI_LP_FSTATR00_BCERR0_Pos      (3UL)      /*!< BCERR0 (Bit 3)                                        */
38419  #define R_FACI_LP_FSTATR00_BCERR0_Msk      (0x8UL)    /*!< BCERR0 (Bitfield-Mask: 0x01)                          */
38420  #define R_FACI_LP_FSTATR00_PRGERR01_Pos    (2UL)      /*!< PRGERR01 (Bit 2)                                      */
38421  #define R_FACI_LP_FSTATR00_PRGERR01_Msk    (0x4UL)    /*!< PRGERR01 (Bitfield-Mask: 0x01)                        */
38422  #define R_FACI_LP_FSTATR00_PRGERR0_Pos     (1UL)      /*!< PRGERR0 (Bit 1)                                       */
38423  #define R_FACI_LP_FSTATR00_PRGERR0_Msk     (0x2UL)    /*!< PRGERR0 (Bitfield-Mask: 0x01)                         */
38424  #define R_FACI_LP_FSTATR00_ERERR0_Pos      (0UL)      /*!< ERERR0 (Bit 0)                                        */
38425  #define R_FACI_LP_FSTATR00_ERERR0_Msk      (0x1UL)    /*!< ERERR0 (Bitfield-Mask: 0x01)                          */
38426 /* ========================================================  FSTATR1  ======================================================== */
38427  #define R_FACI_LP_FSTATR1_EXRDY_Pos        (7UL)      /*!< EXRDY (Bit 7)                                         */
38428  #define R_FACI_LP_FSTATR1_EXRDY_Msk        (0x80UL)   /*!< EXRDY (Bitfield-Mask: 0x01)                           */
38429  #define R_FACI_LP_FSTATR1_FRDY_Pos         (6UL)      /*!< FRDY (Bit 6)                                          */
38430  #define R_FACI_LP_FSTATR1_FRDY_Msk         (0x40UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
38431  #define R_FACI_LP_FSTATR1_DRRDY_Pos        (1UL)      /*!< DRRDY (Bit 1)                                         */
38432  #define R_FACI_LP_FSTATR1_DRRDY_Msk        (0x2UL)    /*!< DRRDY (Bitfield-Mask: 0x01)                           */
38433 /* =========================================================  FWBL0  ========================================================= */
38434  #define R_FACI_LP_FWBL0_WDATA_Pos          (0UL)      /*!< WDATA (Bit 0)                                         */
38435  #define R_FACI_LP_FWBL0_WDATA_Msk          (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff)                         */
38436 /* =========================================================  FWBH0  ========================================================= */
38437  #define R_FACI_LP_FWBH0_WDATA_Pos          (0UL)      /*!< WDATA (Bit 0)                                         */
38438  #define R_FACI_LP_FWBH0_WDATA_Msk          (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff)                         */
38439 /* =======================================================  FSTATR01  ======================================================== */
38440  #define R_FACI_LP_FSTATR01_BCERR1_Pos      (3UL)      /*!< BCERR1 (Bit 3)                                        */
38441  #define R_FACI_LP_FSTATR01_BCERR1_Msk      (0x8UL)    /*!< BCERR1 (Bitfield-Mask: 0x01)                          */
38442  #define R_FACI_LP_FSTATR01_PRGERR1_Pos     (1UL)      /*!< PRGERR1 (Bit 1)                                       */
38443  #define R_FACI_LP_FSTATR01_PRGERR1_Msk     (0x2UL)    /*!< PRGERR1 (Bitfield-Mask: 0x01)                         */
38444  #define R_FACI_LP_FSTATR01_ERERR1_Pos      (0UL)      /*!< ERERR1 (Bit 0)                                        */
38445  #define R_FACI_LP_FSTATR01_ERERR1_Msk      (0x1UL)    /*!< ERERR1 (Bitfield-Mask: 0x01)                          */
38446 /* =========================================================  FWBL1  ========================================================= */
38447  #define R_FACI_LP_FWBL1_WDATA47_32_Pos     (0UL)      /*!< WDATA47_32 (Bit 0)                                    */
38448  #define R_FACI_LP_FWBL1_WDATA47_32_Msk     (0xffffUL) /*!< WDATA47_32 (Bitfield-Mask: 0xffff)                    */
38449 /* =========================================================  FWBH1  ========================================================= */
38450  #define R_FACI_LP_FWBH1_WDATA63_48_Pos     (0UL)      /*!< WDATA63_48 (Bit 0)                                    */
38451  #define R_FACI_LP_FWBH1_WDATA63_48_Msk     (0xffffUL) /*!< WDATA63_48 (Bitfield-Mask: 0xffff)                    */
38452 /* =========================================================  FRBL1  ========================================================= */
38453  #define R_FACI_LP_FRBL1_RDATA47_32_Pos     (0UL)      /*!< RDATA47_32 (Bit 0)                                    */
38454  #define R_FACI_LP_FRBL1_RDATA47_32_Msk     (0xffffUL) /*!< RDATA47_32 (Bitfield-Mask: 0xffff)                    */
38455 /* =========================================================  FRBH1  ========================================================= */
38456  #define R_FACI_LP_FRBH1_RDATA63_48_Pos     (0UL)      /*!< RDATA63_48 (Bit 0)                                    */
38457  #define R_FACI_LP_FRBH1_RDATA63_48_Msk     (0xffffUL) /*!< RDATA63_48 (Bitfield-Mask: 0xffff)                    */
38458 /* ==========================================================  FPR  ========================================================== */
38459  #define R_FACI_LP_FPR_FPR_Pos              (0UL)      /*!< FPR (Bit 0)                                           */
38460  #define R_FACI_LP_FPR_FPR_Msk              (0xffUL)   /*!< FPR (Bitfield-Mask: 0xff)                             */
38461 /* =========================================================  FPSR  ========================================================== */
38462  #define R_FACI_LP_FPSR_PERR_Pos            (0UL)      /*!< PERR (Bit 0)                                          */
38463  #define R_FACI_LP_FPSR_PERR_Msk            (0x1UL)    /*!< PERR (Bitfield-Mask: 0x01)                            */
38464 /* =========================================================  FRBL0  ========================================================= */
38465  #define R_FACI_LP_FRBL0_RDATA_Pos          (0UL)      /*!< RDATA (Bit 0)                                         */
38466  #define R_FACI_LP_FRBL0_RDATA_Msk          (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff)                         */
38467 /* =========================================================  FRBH0  ========================================================= */
38468  #define R_FACI_LP_FRBH0_RDATA_Pos          (0UL)      /*!< RDATA (Bit 0)                                         */
38469  #define R_FACI_LP_FRBH0_RDATA_Msk          (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff)                         */
38470 /* =========================================================  FSCMR  ========================================================= */
38471  #define R_FACI_LP_FSCMR_FSPR_Pos           (14UL)     /*!< FSPR (Bit 14)                                         */
38472  #define R_FACI_LP_FSCMR_FSPR_Msk           (0x4000UL) /*!< FSPR (Bitfield-Mask: 0x01)                            */
38473  #define R_FACI_LP_FSCMR_SASMF_Pos          (8UL)      /*!< SASMF (Bit 8)                                         */
38474  #define R_FACI_LP_FSCMR_SASMF_Msk          (0x100UL)  /*!< SASMF (Bitfield-Mask: 0x01)                           */
38475 /* ========================================================  FAWSMR  ========================================================= */
38476  #define R_FACI_LP_FAWSMR_FAWS_Pos          (0UL)      /*!< FAWS (Bit 0)                                          */
38477  #define R_FACI_LP_FAWSMR_FAWS_Msk          (0xfffUL)  /*!< FAWS (Bitfield-Mask: 0xfff)                           */
38478 /* ========================================================  FAWEMR  ========================================================= */
38479  #define R_FACI_LP_FAWEMR_FAWE_Pos          (0UL)      /*!< FAWE (Bit 0)                                          */
38480  #define R_FACI_LP_FAWEMR_FAWE_Msk          (0xfffUL)  /*!< FAWE (Bitfield-Mask: 0xfff)                           */
38481 /* =========================================================  FISR  ========================================================== */
38482  #define R_FACI_LP_FISR_SAS_Pos             (6UL)      /*!< SAS (Bit 6)                                           */
38483  #define R_FACI_LP_FISR_SAS_Msk             (0xc0UL)   /*!< SAS (Bitfield-Mask: 0x03)                             */
38484  #define R_FACI_LP_FISR_PCKA_Pos            (0UL)      /*!< PCKA (Bit 0)                                          */
38485  #define R_FACI_LP_FISR_PCKA_Msk            (0x3fUL)   /*!< PCKA (Bitfield-Mask: 0x3f)                            */
38486 /* =========================================================  FEXCR  ========================================================= */
38487  #define R_FACI_LP_FEXCR_OPST_Pos           (7UL)      /*!< OPST (Bit 7)                                          */
38488  #define R_FACI_LP_FEXCR_OPST_Msk           (0x80UL)   /*!< OPST (Bitfield-Mask: 0x01)                            */
38489  #define R_FACI_LP_FEXCR_CMD_Pos            (0UL)      /*!< CMD (Bit 0)                                           */
38490  #define R_FACI_LP_FEXCR_CMD_Msk            (0x7UL)    /*!< CMD (Bitfield-Mask: 0x07)                             */
38491 /* =========================================================  FEAML  ========================================================= */
38492  #define R_FACI_LP_FEAML_FEAM_Pos           (0UL)      /*!< FEAM (Bit 0)                                          */
38493  #define R_FACI_LP_FEAML_FEAM_Msk           (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff)                          */
38494 /* =========================================================  FEAMH  ========================================================= */
38495  #define R_FACI_LP_FEAMH_FEAM_Pos           (0UL)      /*!< FEAM (Bit 0)                                          */
38496  #define R_FACI_LP_FEAMH_FEAM_Msk           (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff)                          */
38497 /* ========================================================  FSTATR2  ======================================================== */
38498  #define R_FACI_LP_FSTATR2_EILGLERR_Pos     (5UL)      /*!< EILGLERR (Bit 5)                                      */
38499  #define R_FACI_LP_FSTATR2_EILGLERR_Msk     (0x20UL)   /*!< EILGLERR (Bitfield-Mask: 0x01)                        */
38500  #define R_FACI_LP_FSTATR2_ILGLERR_Pos      (4UL)      /*!< ILGLERR (Bit 4)                                       */
38501  #define R_FACI_LP_FSTATR2_ILGLERR_Msk      (0x10UL)   /*!< ILGLERR (Bitfield-Mask: 0x01)                         */
38502  #define R_FACI_LP_FSTATR2_BCERR_Pos        (3UL)      /*!< BCERR (Bit 3)                                         */
38503  #define R_FACI_LP_FSTATR2_BCERR_Msk        (0x8UL)    /*!< BCERR (Bitfield-Mask: 0x01)                           */
38504  #define R_FACI_LP_FSTATR2_PRGERR01_Pos     (2UL)      /*!< PRGERR01 (Bit 2)                                      */
38505  #define R_FACI_LP_FSTATR2_PRGERR01_Msk     (0x4UL)    /*!< PRGERR01 (Bitfield-Mask: 0x01)                        */
38506  #define R_FACI_LP_FSTATR2_PRGERR1_Pos      (1UL)      /*!< PRGERR1 (Bit 1)                                       */
38507  #define R_FACI_LP_FSTATR2_PRGERR1_Msk      (0x2UL)    /*!< PRGERR1 (Bitfield-Mask: 0x01)                         */
38508  #define R_FACI_LP_FSTATR2_ERERR_Pos        (0UL)      /*!< ERERR (Bit 0)                                         */
38509  #define R_FACI_LP_FSTATR2_ERERR_Msk        (0x1UL)    /*!< ERERR (Bitfield-Mask: 0x01)                           */
38510 /* ======================================================  FENTRYR_MF4  ====================================================== */
38511 /* ========================================================  FENTRYR  ======================================================== */
38512 /* ========================================================  FLWAITR  ======================================================== */
38513 /* =========================================================  PFBER  ========================================================= */
38514 
38515 /* =========================================================================================================================== */
38516 /* ================                                        R_CTSUTRIM                                         ================ */
38517 /* =========================================================================================================================== */
38518 
38519 /* =======================================================  CTSUTRIMA  ======================================================= */
38520  #define R_CTSUTRIM_CTSUTRIMA_SUADJTRIM_Pos    (24UL)         /*!< SUADJTRIM (Bit 24)                                    */
38521  #define R_CTSUTRIM_CTSUTRIMA_SUADJTRIM_Msk    (0xff000000UL) /*!< SUADJTRIM (Bitfield-Mask: 0xff)                       */
38522  #define R_CTSUTRIM_CTSUTRIMA_SUADJD_Pos       (16UL)         /*!< SUADJD (Bit 16)                                       */
38523  #define R_CTSUTRIM_CTSUTRIMA_SUADJD_Msk       (0xff0000UL)   /*!< SUADJD (Bitfield-Mask: 0xff)                          */
38524  #define R_CTSUTRIM_CTSUTRIMA_DACTRIM_Pos      (8UL)          /*!< DACTRIM (Bit 8)                                       */
38525  #define R_CTSUTRIM_CTSUTRIMA_DACTRIM_Msk      (0xff00UL)     /*!< DACTRIM (Bitfield-Mask: 0xff)                         */
38526  #define R_CTSUTRIM_CTSUTRIMA_RTRIM_Pos        (0UL)          /*!< RTRIM (Bit 0)                                         */
38527  #define R_CTSUTRIM_CTSUTRIMA_RTRIM_Msk        (0xffUL)       /*!< RTRIM (Bitfield-Mask: 0xff)                           */
38528 /* =======================================================  CTSUTRIMB  ======================================================= */
38529  #define R_CTSUTRIM_CTSUTRIMB_TRESULT3_Pos     (24UL)         /*!< TRESULT3 (Bit 24)                                     */
38530  #define R_CTSUTRIM_CTSUTRIMB_TRESULT3_Msk     (0xff000000UL) /*!< TRESULT3 (Bitfield-Mask: 0xff)                        */
38531  #define R_CTSUTRIM_CTSUTRIMB_TRESULT2_Pos     (16UL)         /*!< TRESULT2 (Bit 16)                                     */
38532  #define R_CTSUTRIM_CTSUTRIMB_TRESULT2_Msk     (0xff0000UL)   /*!< TRESULT2 (Bitfield-Mask: 0xff)                        */
38533  #define R_CTSUTRIM_CTSUTRIMB_TRESULT1_Pos     (8UL)          /*!< TRESULT1 (Bit 8)                                      */
38534  #define R_CTSUTRIM_CTSUTRIMB_TRESULT1_Msk     (0xff00UL)     /*!< TRESULT1 (Bitfield-Mask: 0xff)                        */
38535  #define R_CTSUTRIM_CTSUTRIMB_TRESULT0_Pos     (0UL)          /*!< TRESULT0 (Bit 0)                                      */
38536  #define R_CTSUTRIM_CTSUTRIMB_TRESULT0_Msk     (0xffUL)       /*!< TRESULT0 (Bitfield-Mask: 0xff)                        */
38537 
38538 /* =========================================================================================================================== */
38539 /* ================                                         R_FCACHE                                          ================ */
38540 /* =========================================================================================================================== */
38541 
38542 /* ========================================================  FCACHEE  ======================================================== */
38543  #define R_FCACHE_FCACHEE_FCACHEEN_Pos     (0UL)     /*!< FCACHEEN (Bit 0)                                      */
38544  #define R_FCACHE_FCACHEE_FCACHEEN_Msk     (0x1UL)   /*!< FCACHEEN (Bitfield-Mask: 0x01)                        */
38545 /* =======================================================  FCACHEIV  ======================================================== */
38546  #define R_FCACHE_FCACHEIV_FCACHEIV_Pos    (0UL)     /*!< FCACHEIV (Bit 0)                                      */
38547  #define R_FCACHE_FCACHEIV_FCACHEIV_Msk    (0x1UL)   /*!< FCACHEIV (Bitfield-Mask: 0x01)                        */
38548 /* =========================================================  FLWT  ========================================================== */
38549  #define R_FCACHE_FLWT_FLWT_Pos            (0UL)     /*!< FLWT (Bit 0)                                          */
38550  #define R_FCACHE_FLWT_FLWT_Msk            (0x7UL)   /*!< FLWT (Bitfield-Mask: 0x07)                            */
38551 /* =========================================================  FSAR  ========================================================== */
38552  #define R_FCACHE_FSAR_FLWTSA_Pos          (0UL)     /*!< FLWTSA (Bit 0)                                        */
38553  #define R_FCACHE_FSAR_FLWTSA_Msk          (0x1UL)   /*!< FLWTSA (Bitfield-Mask: 0x01)                          */
38554  #define R_FCACHE_FSAR_FCKMHZSA_Pos        (8UL)     /*!< FCKMHZSA (Bit 8)                                      */
38555  #define R_FCACHE_FSAR_FCKMHZSA_Msk        (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01)                        */
38556 
38557 /* =========================================================================================================================== */
38558 /* ================                                          R_GLCDC                                          ================ */
38559 /* =========================================================================================================================== */
38560 
38561 /* =======================================================  GR1_CLUT0  ======================================================= */
38562  #define R_GLCDC_GR1_CLUT0_A_Pos    (24UL)         /*!< A (Bit 24)                                            */
38563  #define R_GLCDC_GR1_CLUT0_A_Msk    (0xff000000UL) /*!< A (Bitfield-Mask: 0xff)                               */
38564  #define R_GLCDC_GR1_CLUT0_R_Pos    (16UL)         /*!< R (Bit 16)                                            */
38565  #define R_GLCDC_GR1_CLUT0_R_Msk    (0xff0000UL)   /*!< R (Bitfield-Mask: 0xff)                               */
38566  #define R_GLCDC_GR1_CLUT0_G_Pos    (8UL)          /*!< G (Bit 8)                                             */
38567  #define R_GLCDC_GR1_CLUT0_G_Msk    (0xff00UL)     /*!< G (Bitfield-Mask: 0xff)                               */
38568  #define R_GLCDC_GR1_CLUT0_B_Pos    (0UL)          /*!< B (Bit 0)                                             */
38569  #define R_GLCDC_GR1_CLUT0_B_Msk    (0xffUL)       /*!< B (Bitfield-Mask: 0xff)                               */
38570 /* =======================================================  GR1_CLUT1  ======================================================= */
38571  #define R_GLCDC_GR1_CLUT1_A_Pos    (24UL)         /*!< A (Bit 24)                                            */
38572  #define R_GLCDC_GR1_CLUT1_A_Msk    (0xff000000UL) /*!< A (Bitfield-Mask: 0xff)                               */
38573  #define R_GLCDC_GR1_CLUT1_R_Pos    (16UL)         /*!< R (Bit 16)                                            */
38574  #define R_GLCDC_GR1_CLUT1_R_Msk    (0xff0000UL)   /*!< R (Bitfield-Mask: 0xff)                               */
38575  #define R_GLCDC_GR1_CLUT1_G_Pos    (8UL)          /*!< G (Bit 8)                                             */
38576  #define R_GLCDC_GR1_CLUT1_G_Msk    (0xff00UL)     /*!< G (Bitfield-Mask: 0xff)                               */
38577  #define R_GLCDC_GR1_CLUT1_B_Pos    (0UL)          /*!< B (Bit 0)                                             */
38578  #define R_GLCDC_GR1_CLUT1_B_Msk    (0xffUL)       /*!< B (Bitfield-Mask: 0xff)                               */
38579 /* =======================================================  GR2_CLUT0  ======================================================= */
38580  #define R_GLCDC_GR2_CLUT0_A_Pos    (24UL)         /*!< A (Bit 24)                                            */
38581  #define R_GLCDC_GR2_CLUT0_A_Msk    (0xff000000UL) /*!< A (Bitfield-Mask: 0xff)                               */
38582  #define R_GLCDC_GR2_CLUT0_R_Pos    (16UL)         /*!< R (Bit 16)                                            */
38583  #define R_GLCDC_GR2_CLUT0_R_Msk    (0xff0000UL)   /*!< R (Bitfield-Mask: 0xff)                               */
38584  #define R_GLCDC_GR2_CLUT0_G_Pos    (8UL)          /*!< G (Bit 8)                                             */
38585  #define R_GLCDC_GR2_CLUT0_G_Msk    (0xff00UL)     /*!< G (Bitfield-Mask: 0xff)                               */
38586  #define R_GLCDC_GR2_CLUT0_B_Pos    (0UL)          /*!< B (Bit 0)                                             */
38587  #define R_GLCDC_GR2_CLUT0_B_Msk    (0xffUL)       /*!< B (Bitfield-Mask: 0xff)                               */
38588 /* =======================================================  GR2_CLUT1  ======================================================= */
38589  #define R_GLCDC_GR2_CLUT1_A_Pos    (24UL)         /*!< A (Bit 24)                                            */
38590  #define R_GLCDC_GR2_CLUT1_A_Msk    (0xff000000UL) /*!< A (Bitfield-Mask: 0xff)                               */
38591  #define R_GLCDC_GR2_CLUT1_R_Pos    (16UL)         /*!< R (Bit 16)                                            */
38592  #define R_GLCDC_GR2_CLUT1_R_Msk    (0xff0000UL)   /*!< R (Bitfield-Mask: 0xff)                               */
38593  #define R_GLCDC_GR2_CLUT1_G_Pos    (8UL)          /*!< G (Bit 8)                                             */
38594  #define R_GLCDC_GR2_CLUT1_G_Msk    (0xff00UL)     /*!< G (Bitfield-Mask: 0xff)                               */
38595  #define R_GLCDC_GR2_CLUT1_B_Pos    (0UL)          /*!< B (Bit 0)                                             */
38596  #define R_GLCDC_GR2_CLUT1_B_Msk    (0xffUL)       /*!< B (Bitfield-Mask: 0xff)                               */
38597 
38598 /* =========================================================================================================================== */
38599 /* ================                                          R_GPT0                                           ================ */
38600 /* =========================================================================================================================== */
38601 
38602 /* =========================================================  GTWP  ========================================================== */
38603  #define R_GPT0_GTWP_PRKEY_Pos             (8UL)          /*!< PRKEY (Bit 8)                                         */
38604  #define R_GPT0_GTWP_PRKEY_Msk             (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
38605  #define R_GPT0_GTWP_WP_Pos                (0UL)          /*!< WP (Bit 0)                                            */
38606  #define R_GPT0_GTWP_WP_Msk                (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
38607  #define R_GPT0_GTWP_STRWP_Pos             (1UL)          /*!< STRWP (Bit 1)                                         */
38608  #define R_GPT0_GTWP_STRWP_Msk             (0x2UL)        /*!< STRWP (Bitfield-Mask: 0x01)                           */
38609  #define R_GPT0_GTWP_STPWP_Pos             (2UL)          /*!< STPWP (Bit 2)                                         */
38610  #define R_GPT0_GTWP_STPWP_Msk             (0x4UL)        /*!< STPWP (Bitfield-Mask: 0x01)                           */
38611  #define R_GPT0_GTWP_CLRWP_Pos             (3UL)          /*!< CLRWP (Bit 3)                                         */
38612  #define R_GPT0_GTWP_CLRWP_Msk             (0x8UL)        /*!< CLRWP (Bitfield-Mask: 0x01)                           */
38613  #define R_GPT0_GTWP_CMNWP_Pos             (4UL)          /*!< CMNWP (Bit 4)                                         */
38614  #define R_GPT0_GTWP_CMNWP_Msk             (0x10UL)       /*!< CMNWP (Bitfield-Mask: 0x01)                           */
38615 /* =========================================================  GTSTR  ========================================================= */
38616  #define R_GPT0_GTSTR_CSTRT_Pos            (0UL)          /*!< CSTRT (Bit 0)                                         */
38617  #define R_GPT0_GTSTR_CSTRT_Msk            (0x1UL)        /*!< CSTRT (Bitfield-Mask: 0x01)                           */
38618 /* =========================================================  GTSTP  ========================================================= */
38619  #define R_GPT0_GTSTP_CSTOP_Pos            (0UL)          /*!< CSTOP (Bit 0)                                         */
38620  #define R_GPT0_GTSTP_CSTOP_Msk            (0x1UL)        /*!< CSTOP (Bitfield-Mask: 0x01)                           */
38621 /* =========================================================  GTCLR  ========================================================= */
38622  #define R_GPT0_GTCLR_CCLR_Pos             (0UL)          /*!< CCLR (Bit 0)                                          */
38623  #define R_GPT0_GTCLR_CCLR_Msk             (0x1UL)        /*!< CCLR (Bitfield-Mask: 0x01)                            */
38624 /* =========================================================  GTSSR  ========================================================= */
38625  #define R_GPT0_GTSSR_CSTRT_Pos            (31UL)         /*!< CSTRT (Bit 31)                                        */
38626  #define R_GPT0_GTSSR_CSTRT_Msk            (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01)                           */
38627  #define R_GPT0_GTSSR_SSELC_Pos            (16UL)         /*!< SSELC (Bit 16)                                        */
38628  #define R_GPT0_GTSSR_SSELC_Msk            (0x10000UL)    /*!< SSELC (Bitfield-Mask: 0x01)                           */
38629  #define R_GPT0_GTSSR_SSCBFAH_Pos          (15UL)         /*!< SSCBFAH (Bit 15)                                      */
38630  #define R_GPT0_GTSSR_SSCBFAH_Msk          (0x8000UL)     /*!< SSCBFAH (Bitfield-Mask: 0x01)                         */
38631  #define R_GPT0_GTSSR_SSCBFAL_Pos          (14UL)         /*!< SSCBFAL (Bit 14)                                      */
38632  #define R_GPT0_GTSSR_SSCBFAL_Msk          (0x4000UL)     /*!< SSCBFAL (Bitfield-Mask: 0x01)                         */
38633  #define R_GPT0_GTSSR_SSCBRAH_Pos          (13UL)         /*!< SSCBRAH (Bit 13)                                      */
38634  #define R_GPT0_GTSSR_SSCBRAH_Msk          (0x2000UL)     /*!< SSCBRAH (Bitfield-Mask: 0x01)                         */
38635  #define R_GPT0_GTSSR_SSCBRAL_Pos          (12UL)         /*!< SSCBRAL (Bit 12)                                      */
38636  #define R_GPT0_GTSSR_SSCBRAL_Msk          (0x1000UL)     /*!< SSCBRAL (Bitfield-Mask: 0x01)                         */
38637  #define R_GPT0_GTSSR_SSCAFBH_Pos          (11UL)         /*!< SSCAFBH (Bit 11)                                      */
38638  #define R_GPT0_GTSSR_SSCAFBH_Msk          (0x800UL)      /*!< SSCAFBH (Bitfield-Mask: 0x01)                         */
38639  #define R_GPT0_GTSSR_SSCAFBL_Pos          (10UL)         /*!< SSCAFBL (Bit 10)                                      */
38640  #define R_GPT0_GTSSR_SSCAFBL_Msk          (0x400UL)      /*!< SSCAFBL (Bitfield-Mask: 0x01)                         */
38641  #define R_GPT0_GTSSR_SSCARBH_Pos          (9UL)          /*!< SSCARBH (Bit 9)                                       */
38642  #define R_GPT0_GTSSR_SSCARBH_Msk          (0x200UL)      /*!< SSCARBH (Bitfield-Mask: 0x01)                         */
38643  #define R_GPT0_GTSSR_SSCARBL_Pos          (8UL)          /*!< SSCARBL (Bit 8)                                       */
38644  #define R_GPT0_GTSSR_SSCARBL_Msk          (0x100UL)      /*!< SSCARBL (Bitfield-Mask: 0x01)                         */
38645  #define R_GPT0_GTSSR_SSGTRGF_Pos          (1UL)          /*!< SSGTRGF (Bit 1)                                       */
38646  #define R_GPT0_GTSSR_SSGTRGF_Msk          (0x2UL)        /*!< SSGTRGF (Bitfield-Mask: 0x01)                         */
38647  #define R_GPT0_GTSSR_SSGTRGR_Pos          (0UL)          /*!< SSGTRGR (Bit 0)                                       */
38648  #define R_GPT0_GTSSR_SSGTRGR_Msk          (0x1UL)        /*!< SSGTRGR (Bitfield-Mask: 0x01)                         */
38649 /* =========================================================  GTPSR  ========================================================= */
38650  #define R_GPT0_GTPSR_CSTOP_Pos            (31UL)         /*!< CSTOP (Bit 31)                                        */
38651  #define R_GPT0_GTPSR_CSTOP_Msk            (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01)                           */
38652  #define R_GPT0_GTPSR_PSELC_Pos            (16UL)         /*!< PSELC (Bit 16)                                        */
38653  #define R_GPT0_GTPSR_PSELC_Msk            (0x10000UL)    /*!< PSELC (Bitfield-Mask: 0x01)                           */
38654  #define R_GPT0_GTPSR_PSCBFAH_Pos          (15UL)         /*!< PSCBFAH (Bit 15)                                      */
38655  #define R_GPT0_GTPSR_PSCBFAH_Msk          (0x8000UL)     /*!< PSCBFAH (Bitfield-Mask: 0x01)                         */
38656  #define R_GPT0_GTPSR_PSCBFAL_Pos          (14UL)         /*!< PSCBFAL (Bit 14)                                      */
38657  #define R_GPT0_GTPSR_PSCBFAL_Msk          (0x4000UL)     /*!< PSCBFAL (Bitfield-Mask: 0x01)                         */
38658  #define R_GPT0_GTPSR_PSCBRAH_Pos          (13UL)         /*!< PSCBRAH (Bit 13)                                      */
38659  #define R_GPT0_GTPSR_PSCBRAH_Msk          (0x2000UL)     /*!< PSCBRAH (Bitfield-Mask: 0x01)                         */
38660  #define R_GPT0_GTPSR_PSCBRAL_Pos          (12UL)         /*!< PSCBRAL (Bit 12)                                      */
38661  #define R_GPT0_GTPSR_PSCBRAL_Msk          (0x1000UL)     /*!< PSCBRAL (Bitfield-Mask: 0x01)                         */
38662  #define R_GPT0_GTPSR_PSCAFBH_Pos          (11UL)         /*!< PSCAFBH (Bit 11)                                      */
38663  #define R_GPT0_GTPSR_PSCAFBH_Msk          (0x800UL)      /*!< PSCAFBH (Bitfield-Mask: 0x01)                         */
38664  #define R_GPT0_GTPSR_PSCAFBL_Pos          (10UL)         /*!< PSCAFBL (Bit 10)                                      */
38665  #define R_GPT0_GTPSR_PSCAFBL_Msk          (0x400UL)      /*!< PSCAFBL (Bitfield-Mask: 0x01)                         */
38666  #define R_GPT0_GTPSR_PSCARBH_Pos          (9UL)          /*!< PSCARBH (Bit 9)                                       */
38667  #define R_GPT0_GTPSR_PSCARBH_Msk          (0x200UL)      /*!< PSCARBH (Bitfield-Mask: 0x01)                         */
38668  #define R_GPT0_GTPSR_PSCARBL_Pos          (8UL)          /*!< PSCARBL (Bit 8)                                       */
38669  #define R_GPT0_GTPSR_PSCARBL_Msk          (0x100UL)      /*!< PSCARBL (Bitfield-Mask: 0x01)                         */
38670  #define R_GPT0_GTPSR_PSGTRGF_Pos          (1UL)          /*!< PSGTRGF (Bit 1)                                       */
38671  #define R_GPT0_GTPSR_PSGTRGF_Msk          (0x2UL)        /*!< PSGTRGF (Bitfield-Mask: 0x01)                         */
38672  #define R_GPT0_GTPSR_PSGTRGR_Pos          (0UL)          /*!< PSGTRGR (Bit 0)                                       */
38673  #define R_GPT0_GTPSR_PSGTRGR_Msk          (0x1UL)        /*!< PSGTRGR (Bitfield-Mask: 0x01)                         */
38674 /* =========================================================  GTCSR  ========================================================= */
38675  #define R_GPT0_GTCSR_CCLR_Pos             (31UL)         /*!< CCLR (Bit 31)                                         */
38676  #define R_GPT0_GTCSR_CCLR_Msk             (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01)                            */
38677  #define R_GPT0_GTCSR_CP1CCE_Pos           (27UL)         /*!< CP1CCE (Bit 27)                                       */
38678  #define R_GPT0_GTCSR_CP1CCE_Msk           (0x8000000UL)  /*!< CP1CCE (Bitfield-Mask: 0x01)                          */
38679  #define R_GPT0_GTCSR_CSCMSC_Pos           (24UL)         /*!< CSCMSC (Bit 24)                                       */
38680  #define R_GPT0_GTCSR_CSCMSC_Msk           (0x7000000UL)  /*!< CSCMSC (Bitfield-Mask: 0x07)                          */
38681  #define R_GPT0_GTCSR_CSELC_Pos            (16UL)         /*!< CSELC (Bit 16)                                        */
38682  #define R_GPT0_GTCSR_CSELC_Msk            (0x10000UL)    /*!< CSELC (Bitfield-Mask: 0x01)                           */
38683  #define R_GPT0_GTCSR_CSCBFAH_Pos          (15UL)         /*!< CSCBFAH (Bit 15)                                      */
38684  #define R_GPT0_GTCSR_CSCBFAH_Msk          (0x8000UL)     /*!< CSCBFAH (Bitfield-Mask: 0x01)                         */
38685  #define R_GPT0_GTCSR_CSCBFAL_Pos          (14UL)         /*!< CSCBFAL (Bit 14)                                      */
38686  #define R_GPT0_GTCSR_CSCBFAL_Msk          (0x4000UL)     /*!< CSCBFAL (Bitfield-Mask: 0x01)                         */
38687  #define R_GPT0_GTCSR_CSCBRAH_Pos          (13UL)         /*!< CSCBRAH (Bit 13)                                      */
38688  #define R_GPT0_GTCSR_CSCBRAH_Msk          (0x2000UL)     /*!< CSCBRAH (Bitfield-Mask: 0x01)                         */
38689  #define R_GPT0_GTCSR_CSCBRAL_Pos          (12UL)         /*!< CSCBRAL (Bit 12)                                      */
38690  #define R_GPT0_GTCSR_CSCBRAL_Msk          (0x1000UL)     /*!< CSCBRAL (Bitfield-Mask: 0x01)                         */
38691  #define R_GPT0_GTCSR_CSCAFBH_Pos          (11UL)         /*!< CSCAFBH (Bit 11)                                      */
38692  #define R_GPT0_GTCSR_CSCAFBH_Msk          (0x800UL)      /*!< CSCAFBH (Bitfield-Mask: 0x01)                         */
38693  #define R_GPT0_GTCSR_CSCAFBL_Pos          (10UL)         /*!< CSCAFBL (Bit 10)                                      */
38694  #define R_GPT0_GTCSR_CSCAFBL_Msk          (0x400UL)      /*!< CSCAFBL (Bitfield-Mask: 0x01)                         */
38695  #define R_GPT0_GTCSR_CSCARBH_Pos          (9UL)          /*!< CSCARBH (Bit 9)                                       */
38696  #define R_GPT0_GTCSR_CSCARBH_Msk          (0x200UL)      /*!< CSCARBH (Bitfield-Mask: 0x01)                         */
38697  #define R_GPT0_GTCSR_CSCARBL_Pos          (8UL)          /*!< CSCARBL (Bit 8)                                       */
38698  #define R_GPT0_GTCSR_CSCARBL_Msk          (0x100UL)      /*!< CSCARBL (Bitfield-Mask: 0x01)                         */
38699  #define R_GPT0_GTCSR_CSGTRGF_Pos          (1UL)          /*!< CSGTRGF (Bit 1)                                       */
38700  #define R_GPT0_GTCSR_CSGTRGF_Msk          (0x2UL)        /*!< CSGTRGF (Bitfield-Mask: 0x01)                         */
38701  #define R_GPT0_GTCSR_CSGTRGR_Pos          (0UL)          /*!< CSGTRGR (Bit 0)                                       */
38702  #define R_GPT0_GTCSR_CSGTRGR_Msk          (0x1UL)        /*!< CSGTRGR (Bitfield-Mask: 0x01)                         */
38703 /* ========================================================  GTUPSR  ========================================================= */
38704  #define R_GPT0_GTUPSR_USILVL_Pos          (24UL)         /*!< USILVL (Bit 24)                                       */
38705  #define R_GPT0_GTUPSR_USILVL_Msk          (0xf000000UL)  /*!< USILVL (Bitfield-Mask: 0x0f)                          */
38706  #define R_GPT0_GTUPSR_USELC_Pos           (16UL)         /*!< USELC (Bit 16)                                        */
38707  #define R_GPT0_GTUPSR_USELC_Msk           (0x10000UL)    /*!< USELC (Bitfield-Mask: 0x01)                           */
38708  #define R_GPT0_GTUPSR_USCBFAH_Pos         (15UL)         /*!< USCBFAH (Bit 15)                                      */
38709  #define R_GPT0_GTUPSR_USCBFAH_Msk         (0x8000UL)     /*!< USCBFAH (Bitfield-Mask: 0x01)                         */
38710  #define R_GPT0_GTUPSR_USCBFAL_Pos         (14UL)         /*!< USCBFAL (Bit 14)                                      */
38711  #define R_GPT0_GTUPSR_USCBFAL_Msk         (0x4000UL)     /*!< USCBFAL (Bitfield-Mask: 0x01)                         */
38712  #define R_GPT0_GTUPSR_USCBRAH_Pos         (13UL)         /*!< USCBRAH (Bit 13)                                      */
38713  #define R_GPT0_GTUPSR_USCBRAH_Msk         (0x2000UL)     /*!< USCBRAH (Bitfield-Mask: 0x01)                         */
38714  #define R_GPT0_GTUPSR_USCBRAL_Pos         (12UL)         /*!< USCBRAL (Bit 12)                                      */
38715  #define R_GPT0_GTUPSR_USCBRAL_Msk         (0x1000UL)     /*!< USCBRAL (Bitfield-Mask: 0x01)                         */
38716  #define R_GPT0_GTUPSR_USCAFBH_Pos         (11UL)         /*!< USCAFBH (Bit 11)                                      */
38717  #define R_GPT0_GTUPSR_USCAFBH_Msk         (0x800UL)      /*!< USCAFBH (Bitfield-Mask: 0x01)                         */
38718  #define R_GPT0_GTUPSR_USCAFBL_Pos         (10UL)         /*!< USCAFBL (Bit 10)                                      */
38719  #define R_GPT0_GTUPSR_USCAFBL_Msk         (0x400UL)      /*!< USCAFBL (Bitfield-Mask: 0x01)                         */
38720  #define R_GPT0_GTUPSR_USCARBH_Pos         (9UL)          /*!< USCARBH (Bit 9)                                       */
38721  #define R_GPT0_GTUPSR_USCARBH_Msk         (0x200UL)      /*!< USCARBH (Bitfield-Mask: 0x01)                         */
38722  #define R_GPT0_GTUPSR_USCARBL_Pos         (8UL)          /*!< USCARBL (Bit 8)                                       */
38723  #define R_GPT0_GTUPSR_USCARBL_Msk         (0x100UL)      /*!< USCARBL (Bitfield-Mask: 0x01)                         */
38724  #define R_GPT0_GTUPSR_USGTRGF_Pos         (1UL)          /*!< USGTRGF (Bit 1)                                       */
38725  #define R_GPT0_GTUPSR_USGTRGF_Msk         (0x2UL)        /*!< USGTRGF (Bitfield-Mask: 0x01)                         */
38726  #define R_GPT0_GTUPSR_USGTRGR_Pos         (0UL)          /*!< USGTRGR (Bit 0)                                       */
38727  #define R_GPT0_GTUPSR_USGTRGR_Msk         (0x1UL)        /*!< USGTRGR (Bitfield-Mask: 0x01)                         */
38728 /* ========================================================  GTDNSR  ========================================================= */
38729  #define R_GPT0_GTDNSR_DSILVL_Pos          (24UL)         /*!< DSILVL (Bit 24)                                       */
38730  #define R_GPT0_GTDNSR_DSILVL_Msk          (0xf000000UL)  /*!< DSILVL (Bitfield-Mask: 0x0f)                          */
38731  #define R_GPT0_GTDNSR_DSELC_Pos           (16UL)         /*!< DSELC (Bit 16)                                        */
38732  #define R_GPT0_GTDNSR_DSELC_Msk           (0x10000UL)    /*!< DSELC (Bitfield-Mask: 0x01)                           */
38733  #define R_GPT0_GTDNSR_DSCBFAH_Pos         (15UL)         /*!< DSCBFAH (Bit 15)                                      */
38734  #define R_GPT0_GTDNSR_DSCBFAH_Msk         (0x8000UL)     /*!< DSCBFAH (Bitfield-Mask: 0x01)                         */
38735  #define R_GPT0_GTDNSR_DSCBFAL_Pos         (14UL)         /*!< DSCBFAL (Bit 14)                                      */
38736  #define R_GPT0_GTDNSR_DSCBFAL_Msk         (0x4000UL)     /*!< DSCBFAL (Bitfield-Mask: 0x01)                         */
38737  #define R_GPT0_GTDNSR_DSCBRAH_Pos         (13UL)         /*!< DSCBRAH (Bit 13)                                      */
38738  #define R_GPT0_GTDNSR_DSCBRAH_Msk         (0x2000UL)     /*!< DSCBRAH (Bitfield-Mask: 0x01)                         */
38739  #define R_GPT0_GTDNSR_DSCBRAL_Pos         (12UL)         /*!< DSCBRAL (Bit 12)                                      */
38740  #define R_GPT0_GTDNSR_DSCBRAL_Msk         (0x1000UL)     /*!< DSCBRAL (Bitfield-Mask: 0x01)                         */
38741  #define R_GPT0_GTDNSR_DSCAFBH_Pos         (11UL)         /*!< DSCAFBH (Bit 11)                                      */
38742  #define R_GPT0_GTDNSR_DSCAFBH_Msk         (0x800UL)      /*!< DSCAFBH (Bitfield-Mask: 0x01)                         */
38743  #define R_GPT0_GTDNSR_DSCAFBL_Pos         (10UL)         /*!< DSCAFBL (Bit 10)                                      */
38744  #define R_GPT0_GTDNSR_DSCAFBL_Msk         (0x400UL)      /*!< DSCAFBL (Bitfield-Mask: 0x01)                         */
38745  #define R_GPT0_GTDNSR_DSCARBH_Pos         (9UL)          /*!< DSCARBH (Bit 9)                                       */
38746  #define R_GPT0_GTDNSR_DSCARBH_Msk         (0x200UL)      /*!< DSCARBH (Bitfield-Mask: 0x01)                         */
38747  #define R_GPT0_GTDNSR_DSCARBL_Pos         (8UL)          /*!< DSCARBL (Bit 8)                                       */
38748  #define R_GPT0_GTDNSR_DSCARBL_Msk         (0x100UL)      /*!< DSCARBL (Bitfield-Mask: 0x01)                         */
38749  #define R_GPT0_GTDNSR_DSGTRGF_Pos         (1UL)          /*!< DSGTRGF (Bit 1)                                       */
38750  #define R_GPT0_GTDNSR_DSGTRGF_Msk         (0x2UL)        /*!< DSGTRGF (Bitfield-Mask: 0x01)                         */
38751  #define R_GPT0_GTDNSR_DSGTRGR_Pos         (0UL)          /*!< DSGTRGR (Bit 0)                                       */
38752  #define R_GPT0_GTDNSR_DSGTRGR_Msk         (0x1UL)        /*!< DSGTRGR (Bitfield-Mask: 0x01)                         */
38753 /* ========================================================  GTICASR  ======================================================== */
38754  #define R_GPT0_GTICASR_ASELC_Pos          (16UL)         /*!< ASELC (Bit 16)                                        */
38755  #define R_GPT0_GTICASR_ASELC_Msk          (0x10000UL)    /*!< ASELC (Bitfield-Mask: 0x01)                           */
38756  #define R_GPT0_GTICASR_ASCBFAH_Pos        (15UL)         /*!< ASCBFAH (Bit 15)                                      */
38757  #define R_GPT0_GTICASR_ASCBFAH_Msk        (0x8000UL)     /*!< ASCBFAH (Bitfield-Mask: 0x01)                         */
38758  #define R_GPT0_GTICASR_ASCBFAL_Pos        (14UL)         /*!< ASCBFAL (Bit 14)                                      */
38759  #define R_GPT0_GTICASR_ASCBFAL_Msk        (0x4000UL)     /*!< ASCBFAL (Bitfield-Mask: 0x01)                         */
38760  #define R_GPT0_GTICASR_ASCBRAH_Pos        (13UL)         /*!< ASCBRAH (Bit 13)                                      */
38761  #define R_GPT0_GTICASR_ASCBRAH_Msk        (0x2000UL)     /*!< ASCBRAH (Bitfield-Mask: 0x01)                         */
38762  #define R_GPT0_GTICASR_ASCBRAL_Pos        (12UL)         /*!< ASCBRAL (Bit 12)                                      */
38763  #define R_GPT0_GTICASR_ASCBRAL_Msk        (0x1000UL)     /*!< ASCBRAL (Bitfield-Mask: 0x01)                         */
38764  #define R_GPT0_GTICASR_ASCAFBH_Pos        (11UL)         /*!< ASCAFBH (Bit 11)                                      */
38765  #define R_GPT0_GTICASR_ASCAFBH_Msk        (0x800UL)      /*!< ASCAFBH (Bitfield-Mask: 0x01)                         */
38766  #define R_GPT0_GTICASR_ASCAFBL_Pos        (10UL)         /*!< ASCAFBL (Bit 10)                                      */
38767  #define R_GPT0_GTICASR_ASCAFBL_Msk        (0x400UL)      /*!< ASCAFBL (Bitfield-Mask: 0x01)                         */
38768  #define R_GPT0_GTICASR_ASCARBH_Pos        (9UL)          /*!< ASCARBH (Bit 9)                                       */
38769  #define R_GPT0_GTICASR_ASCARBH_Msk        (0x200UL)      /*!< ASCARBH (Bitfield-Mask: 0x01)                         */
38770  #define R_GPT0_GTICASR_ASCARBL_Pos        (8UL)          /*!< ASCARBL (Bit 8)                                       */
38771  #define R_GPT0_GTICASR_ASCARBL_Msk        (0x100UL)      /*!< ASCARBL (Bitfield-Mask: 0x01)                         */
38772  #define R_GPT0_GTICASR_ASGTRGF_Pos        (1UL)          /*!< ASGTRGF (Bit 1)                                       */
38773  #define R_GPT0_GTICASR_ASGTRGF_Msk        (0x2UL)        /*!< ASGTRGF (Bitfield-Mask: 0x01)                         */
38774  #define R_GPT0_GTICASR_ASGTRGR_Pos        (0UL)          /*!< ASGTRGR (Bit 0)                                       */
38775  #define R_GPT0_GTICASR_ASGTRGR_Msk        (0x1UL)        /*!< ASGTRGR (Bitfield-Mask: 0x01)                         */
38776 /* ========================================================  GTICBSR  ======================================================== */
38777  #define R_GPT0_GTICBSR_BSELC_Pos          (16UL)         /*!< BSELC (Bit 16)                                        */
38778  #define R_GPT0_GTICBSR_BSELC_Msk          (0x10000UL)    /*!< BSELC (Bitfield-Mask: 0x01)                           */
38779  #define R_GPT0_GTICBSR_BSCBFAH_Pos        (15UL)         /*!< BSCBFAH (Bit 15)                                      */
38780  #define R_GPT0_GTICBSR_BSCBFAH_Msk        (0x8000UL)     /*!< BSCBFAH (Bitfield-Mask: 0x01)                         */
38781  #define R_GPT0_GTICBSR_BSCBFAL_Pos        (14UL)         /*!< BSCBFAL (Bit 14)                                      */
38782  #define R_GPT0_GTICBSR_BSCBFAL_Msk        (0x4000UL)     /*!< BSCBFAL (Bitfield-Mask: 0x01)                         */
38783  #define R_GPT0_GTICBSR_BSCBRAH_Pos        (13UL)         /*!< BSCBRAH (Bit 13)                                      */
38784  #define R_GPT0_GTICBSR_BSCBRAH_Msk        (0x2000UL)     /*!< BSCBRAH (Bitfield-Mask: 0x01)                         */
38785  #define R_GPT0_GTICBSR_BSCBRAL_Pos        (12UL)         /*!< BSCBRAL (Bit 12)                                      */
38786  #define R_GPT0_GTICBSR_BSCBRAL_Msk        (0x1000UL)     /*!< BSCBRAL (Bitfield-Mask: 0x01)                         */
38787  #define R_GPT0_GTICBSR_BSCAFBH_Pos        (11UL)         /*!< BSCAFBH (Bit 11)                                      */
38788  #define R_GPT0_GTICBSR_BSCAFBH_Msk        (0x800UL)      /*!< BSCAFBH (Bitfield-Mask: 0x01)                         */
38789  #define R_GPT0_GTICBSR_BSCAFBL_Pos        (10UL)         /*!< BSCAFBL (Bit 10)                                      */
38790  #define R_GPT0_GTICBSR_BSCAFBL_Msk        (0x400UL)      /*!< BSCAFBL (Bitfield-Mask: 0x01)                         */
38791  #define R_GPT0_GTICBSR_BSCARBH_Pos        (9UL)          /*!< BSCARBH (Bit 9)                                       */
38792  #define R_GPT0_GTICBSR_BSCARBH_Msk        (0x200UL)      /*!< BSCARBH (Bitfield-Mask: 0x01)                         */
38793  #define R_GPT0_GTICBSR_BSCARBL_Pos        (8UL)          /*!< BSCARBL (Bit 8)                                       */
38794  #define R_GPT0_GTICBSR_BSCARBL_Msk        (0x100UL)      /*!< BSCARBL (Bitfield-Mask: 0x01)                         */
38795  #define R_GPT0_GTICBSR_BSGTRGF_Pos        (1UL)          /*!< BSGTRGF (Bit 1)                                       */
38796  #define R_GPT0_GTICBSR_BSGTRGF_Msk        (0x2UL)        /*!< BSGTRGF (Bitfield-Mask: 0x01)                         */
38797  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
38798  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
38799 /* =========================================================  GTCR  ========================================================== */
38800  #define R_GPT0_GTCR_TPCS_Pos              (23UL)         /*!< TPCS (Bit 23)                                         */
38801  #define R_GPT0_GTCR_TPCS_Msk              (0x7800000UL)  /*!< TPCS (Bitfield-Mask: 0x0f)                            */
38802  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
38803  #define R_GPT0_GTCR_MD_Msk                (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
38804  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
38805  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
38806 /* =======================================================  GTUDDTYC  ======================================================== */
38807  #define R_GPT0_GTUDDTYC_OBDTYR_Pos        (27UL)         /*!< OBDTYR (Bit 27)                                       */
38808  #define R_GPT0_GTUDDTYC_OBDTYR_Msk        (0x8000000UL)  /*!< OBDTYR (Bitfield-Mask: 0x01)                          */
38809  #define R_GPT0_GTUDDTYC_OBDTYF_Pos        (26UL)         /*!< OBDTYF (Bit 26)                                       */
38810  #define R_GPT0_GTUDDTYC_OBDTYF_Msk        (0x4000000UL)  /*!< OBDTYF (Bitfield-Mask: 0x01)                          */
38811  #define R_GPT0_GTUDDTYC_OBDTY_Pos         (24UL)         /*!< OBDTY (Bit 24)                                        */
38812  #define R_GPT0_GTUDDTYC_OBDTY_Msk         (0x3000000UL)  /*!< OBDTY (Bitfield-Mask: 0x03)                           */
38813  #define R_GPT0_GTUDDTYC_OADTYR_Pos        (19UL)         /*!< OADTYR (Bit 19)                                       */
38814  #define R_GPT0_GTUDDTYC_OADTYR_Msk        (0x80000UL)    /*!< OADTYR (Bitfield-Mask: 0x01)                          */
38815  #define R_GPT0_GTUDDTYC_OADTYF_Pos        (18UL)         /*!< OADTYF (Bit 18)                                       */
38816  #define R_GPT0_GTUDDTYC_OADTYF_Msk        (0x40000UL)    /*!< OADTYF (Bitfield-Mask: 0x01)                          */
38817  #define R_GPT0_GTUDDTYC_OADTY_Pos         (16UL)         /*!< OADTY (Bit 16)                                        */
38818  #define R_GPT0_GTUDDTYC_OADTY_Msk         (0x30000UL)    /*!< OADTY (Bitfield-Mask: 0x03)                           */
38819  #define R_GPT0_GTUDDTYC_UDF_Pos           (1UL)          /*!< UDF (Bit 1)                                           */
38820  #define R_GPT0_GTUDDTYC_UDF_Msk           (0x2UL)        /*!< UDF (Bitfield-Mask: 0x01)                             */
38821  #define R_GPT0_GTUDDTYC_UD_Pos            (0UL)          /*!< UD (Bit 0)                                            */
38822  #define R_GPT0_GTUDDTYC_UD_Msk            (0x1UL)        /*!< UD (Bitfield-Mask: 0x01)                              */
38823 /* =========================================================  GTIOR  ========================================================= */
38824  #define R_GPT0_GTIOR_NFCSB_Pos            (30UL)         /*!< NFCSB (Bit 30)                                        */
38825  #define R_GPT0_GTIOR_NFCSB_Msk            (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03)                           */
38826  #define R_GPT0_GTIOR_NFBEN_Pos            (29UL)         /*!< NFBEN (Bit 29)                                        */
38827  #define R_GPT0_GTIOR_NFBEN_Msk            (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01)                           */
38828  #define R_GPT0_GTIOR_OBEOCD_Pos           (27UL)         /*!< OBEOCD (Bit 27)                                       */
38829  #define R_GPT0_GTIOR_OBEOCD_Msk           (0x8000000UL)  /*!< OBEOCD (Bitfield-Mask: 0x01)                          */
38830  #define R_GPT0_GTIOR_OBDF_Pos             (25UL)         /*!< OBDF (Bit 25)                                         */
38831  #define R_GPT0_GTIOR_OBDF_Msk             (0x6000000UL)  /*!< OBDF (Bitfield-Mask: 0x03)                            */
38832  #define R_GPT0_GTIOR_OBE_Pos              (24UL)         /*!< OBE (Bit 24)                                          */
38833  #define R_GPT0_GTIOR_OBE_Msk              (0x1000000UL)  /*!< OBE (Bitfield-Mask: 0x01)                             */
38834  #define R_GPT0_GTIOR_OBHLD_Pos            (23UL)         /*!< OBHLD (Bit 23)                                        */
38835  #define R_GPT0_GTIOR_OBHLD_Msk            (0x800000UL)   /*!< OBHLD (Bitfield-Mask: 0x01)                           */
38836  #define R_GPT0_GTIOR_OBDFLT_Pos           (22UL)         /*!< OBDFLT (Bit 22)                                       */
38837  #define R_GPT0_GTIOR_OBDFLT_Msk           (0x400000UL)   /*!< OBDFLT (Bitfield-Mask: 0x01)                          */
38838  #define R_GPT0_GTIOR_GTIOB_Pos            (16UL)         /*!< GTIOB (Bit 16)                                        */
38839  #define R_GPT0_GTIOR_GTIOB_Msk            (0x1f0000UL)   /*!< GTIOB (Bitfield-Mask: 0x1f)                           */
38840  #define R_GPT0_GTIOR_NFCSA_Pos            (14UL)         /*!< NFCSA (Bit 14)                                        */
38841  #define R_GPT0_GTIOR_NFCSA_Msk            (0xc000UL)     /*!< NFCSA (Bitfield-Mask: 0x03)                           */
38842  #define R_GPT0_GTIOR_NFAEN_Pos            (13UL)         /*!< NFAEN (Bit 13)                                        */
38843  #define R_GPT0_GTIOR_NFAEN_Msk            (0x2000UL)     /*!< NFAEN (Bitfield-Mask: 0x01)                           */
38844  #define R_GPT0_GTIOR_PSYE_Pos             (12UL)         /*!< PSYE (Bit 12)                                         */
38845  #define R_GPT0_GTIOR_PSYE_Msk             (0x1000UL)     /*!< PSYE (Bitfield-Mask: 0x01)                            */
38846  #define R_GPT0_GTIOR_OAEOCD_Pos           (11UL)         /*!< OAEOCD (Bit 11)                                       */
38847  #define R_GPT0_GTIOR_OAEOCD_Msk           (0x800UL)      /*!< OAEOCD (Bitfield-Mask: 0x01)                          */
38848  #define R_GPT0_GTIOR_OADF_Pos             (9UL)          /*!< OADF (Bit 9)                                          */
38849  #define R_GPT0_GTIOR_OADF_Msk             (0x600UL)      /*!< OADF (Bitfield-Mask: 0x03)                            */
38850  #define R_GPT0_GTIOR_OAE_Pos              (8UL)          /*!< OAE (Bit 8)                                           */
38851  #define R_GPT0_GTIOR_OAE_Msk              (0x100UL)      /*!< OAE (Bitfield-Mask: 0x01)                             */
38852  #define R_GPT0_GTIOR_OAHLD_Pos            (7UL)          /*!< OAHLD (Bit 7)                                         */
38853  #define R_GPT0_GTIOR_OAHLD_Msk            (0x80UL)       /*!< OAHLD (Bitfield-Mask: 0x01)                           */
38854  #define R_GPT0_GTIOR_OADFLT_Pos           (6UL)          /*!< OADFLT (Bit 6)                                        */
38855  #define R_GPT0_GTIOR_OADFLT_Msk           (0x40UL)       /*!< OADFLT (Bitfield-Mask: 0x01)                          */
38856  #define R_GPT0_GTIOR_CPSCIR_Pos           (5UL)          /*!< CPSCIR (Bit 5)                                        */
38857  #define R_GPT0_GTIOR_CPSCIR_Msk           (0x20UL)       /*!< CPSCIR (Bitfield-Mask: 0x01)                          */
38858  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
38859  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
38860 /* ========================================================  GTINTAD  ======================================================== */
38861  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
38862  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
38863  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
38864  #define R_GPT0_GTINTAD_GRPABH_Msk         (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01)                          */
38865  #define R_GPT0_GTINTAD_GRPDTE_Pos         (28UL)         /*!< GRPDTE (Bit 28)                                       */
38866  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
38867  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
38868  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
38869  #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
38870  #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
38871 /* =========================================================  GTST  ========================================================== */
38872  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
38873  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
38874  #define R_GPT0_GTST_OABHF_Pos             (29UL)         /*!< OABHF (Bit 29)                                        */
38875  #define R_GPT0_GTST_OABHF_Msk             (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01)                           */
38876  #define R_GPT0_GTST_DTEF_Pos              (28UL)         /*!< DTEF (Bit 28)                                         */
38877  #define R_GPT0_GTST_DTEF_Msk              (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01)                            */
38878  #define R_GPT0_GTST_ODF_Pos               (24UL)         /*!< ODF (Bit 24)                                          */
38879  #define R_GPT0_GTST_ODF_Msk               (0x1000000UL)  /*!< ODF (Bitfield-Mask: 0x01)                             */
38880  #define R_GPT0_GTST_ADTRBDF_Pos           (19UL)         /*!< ADTRBDF (Bit 19)                                      */
38881  #define R_GPT0_GTST_ADTRBDF_Msk           (0x80000UL)    /*!< ADTRBDF (Bitfield-Mask: 0x01)                         */
38882  #define R_GPT0_GTST_ADTRBUF_Pos           (18UL)         /*!< ADTRBUF (Bit 18)                                      */
38883  #define R_GPT0_GTST_ADTRBUF_Msk           (0x40000UL)    /*!< ADTRBUF (Bitfield-Mask: 0x01)                         */
38884  #define R_GPT0_GTST_ADTRADF_Pos           (17UL)         /*!< ADTRADF (Bit 17)                                      */
38885  #define R_GPT0_GTST_ADTRADF_Msk           (0x20000UL)    /*!< ADTRADF (Bitfield-Mask: 0x01)                         */
38886  #define R_GPT0_GTST_ADTRAUF_Pos           (16UL)         /*!< ADTRAUF (Bit 16)                                      */
38887  #define R_GPT0_GTST_ADTRAUF_Msk           (0x10000UL)    /*!< ADTRAUF (Bitfield-Mask: 0x01)                         */
38888  #define R_GPT0_GTST_TUCF_Pos              (15UL)         /*!< TUCF (Bit 15)                                         */
38889  #define R_GPT0_GTST_TUCF_Msk              (0x8000UL)     /*!< TUCF (Bitfield-Mask: 0x01)                            */
38890  #define R_GPT0_GTST_ITCNT_Pos             (8UL)          /*!< ITCNT (Bit 8)                                         */
38891  #define R_GPT0_GTST_ITCNT_Msk             (0x700UL)      /*!< ITCNT (Bitfield-Mask: 0x07)                           */
38892  #define R_GPT0_GTST_TCFPU_Pos             (7UL)          /*!< TCFPU (Bit 7)                                         */
38893  #define R_GPT0_GTST_TCFPU_Msk             (0x80UL)       /*!< TCFPU (Bitfield-Mask: 0x01)                           */
38894  #define R_GPT0_GTST_TCFPO_Pos             (6UL)          /*!< TCFPO (Bit 6)                                         */
38895  #define R_GPT0_GTST_TCFPO_Msk             (0x40UL)       /*!< TCFPO (Bitfield-Mask: 0x01)                           */
38896  #define R_GPT0_GTST_TCFF_Pos              (5UL)          /*!< TCFF (Bit 5)                                          */
38897  #define R_GPT0_GTST_TCFF_Msk              (0x20UL)       /*!< TCFF (Bitfield-Mask: 0x01)                            */
38898  #define R_GPT0_GTST_TCFE_Pos              (4UL)          /*!< TCFE (Bit 4)                                          */
38899  #define R_GPT0_GTST_TCFE_Msk              (0x10UL)       /*!< TCFE (Bitfield-Mask: 0x01)                            */
38900  #define R_GPT0_GTST_TCFD_Pos              (3UL)          /*!< TCFD (Bit 3)                                          */
38901  #define R_GPT0_GTST_TCFD_Msk              (0x8UL)        /*!< TCFD (Bitfield-Mask: 0x01)                            */
38902  #define R_GPT0_GTST_TCFC_Pos              (2UL)          /*!< TCFC (Bit 2)                                          */
38903  #define R_GPT0_GTST_TCFC_Msk              (0x4UL)        /*!< TCFC (Bitfield-Mask: 0x01)                            */
38904  #define R_GPT0_GTST_TCFB_Pos              (1UL)          /*!< TCFB (Bit 1)                                          */
38905  #define R_GPT0_GTST_TCFB_Msk              (0x2UL)        /*!< TCFB (Bitfield-Mask: 0x01)                            */
38906  #define R_GPT0_GTST_TCFA_Pos              (0UL)          /*!< TCFA (Bit 0)                                          */
38907  #define R_GPT0_GTST_TCFA_Msk              (0x1UL)        /*!< TCFA (Bitfield-Mask: 0x01)                            */
38908  #define R_GPT0_GTST_PCF_Pos               (31UL)         /*!< PCF (Bit 31)                                          */
38909  #define R_GPT0_GTST_PCF_Msk               (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01)                             */
38910 /* =========================================================  GTBER  ========================================================= */
38911  #define R_GPT0_GTBER_ADTDB_Pos            (30UL)         /*!< ADTDB (Bit 30)                                        */
38912  #define R_GPT0_GTBER_ADTDB_Msk            (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01)                           */
38913  #define R_GPT0_GTBER_ADTTB_Pos            (28UL)         /*!< ADTTB (Bit 28)                                        */
38914  #define R_GPT0_GTBER_ADTTB_Msk            (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03)                           */
38915  #define R_GPT0_GTBER_ADTDA_Pos            (26UL)         /*!< ADTDA (Bit 26)                                        */
38916  #define R_GPT0_GTBER_ADTDA_Msk            (0x4000000UL)  /*!< ADTDA (Bitfield-Mask: 0x01)                           */
38917  #define R_GPT0_GTBER_ADTTA_Pos            (24UL)         /*!< ADTTA (Bit 24)                                        */
38918  #define R_GPT0_GTBER_ADTTA_Msk            (0x3000000UL)  /*!< ADTTA (Bitfield-Mask: 0x03)                           */
38919  #define R_GPT0_GTBER_CCRSWT_Pos           (22UL)         /*!< CCRSWT (Bit 22)                                       */
38920  #define R_GPT0_GTBER_CCRSWT_Msk           (0x400000UL)   /*!< CCRSWT (Bitfield-Mask: 0x01)                          */
38921  #define R_GPT0_GTBER_PR_Pos               (20UL)         /*!< PR (Bit 20)                                           */
38922  #define R_GPT0_GTBER_PR_Msk               (0x300000UL)   /*!< PR (Bitfield-Mask: 0x03)                              */
38923  #define R_GPT0_GTBER_CCRB_Pos             (18UL)         /*!< CCRB (Bit 18)                                         */
38924  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
38925  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
38926  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
38927  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
38928  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
38929  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
38930  #define R_GPT0_GTBER_BD2_Msk              (0x4UL)        /*!< BD2 (Bitfield-Mask: 0x01)                             */
38931  #define R_GPT0_GTBER_BD1_Pos              (1UL)          /*!< BD1 (Bit 1)                                           */
38932  #define R_GPT0_GTBER_BD1_Msk              (0x2UL)        /*!< BD1 (Bitfield-Mask: 0x01)                             */
38933  #define R_GPT0_GTBER_BD0_Pos              (0UL)          /*!< BD0 (Bit 0)                                           */
38934  #define R_GPT0_GTBER_BD0_Msk              (0x1UL)        /*!< BD0 (Bitfield-Mask: 0x01)                             */
38935 /* =========================================================  GTITC  ========================================================= */
38936  #define R_GPT0_GTITC_ADTBL_Pos            (14UL)         /*!< ADTBL (Bit 14)                                        */
38937  #define R_GPT0_GTITC_ADTBL_Msk            (0x4000UL)     /*!< ADTBL (Bitfield-Mask: 0x01)                           */
38938  #define R_GPT0_GTITC_ADTAL_Pos            (12UL)         /*!< ADTAL (Bit 12)                                        */
38939  #define R_GPT0_GTITC_ADTAL_Msk            (0x1000UL)     /*!< ADTAL (Bitfield-Mask: 0x01)                           */
38940  #define R_GPT0_GTITC_IVTT_Pos             (8UL)          /*!< IVTT (Bit 8)                                          */
38941  #define R_GPT0_GTITC_IVTT_Msk             (0x700UL)      /*!< IVTT (Bitfield-Mask: 0x07)                            */
38942  #define R_GPT0_GTITC_IVTC_Pos             (6UL)          /*!< IVTC (Bit 6)                                          */
38943  #define R_GPT0_GTITC_IVTC_Msk             (0xc0UL)       /*!< IVTC (Bitfield-Mask: 0x03)                            */
38944  #define R_GPT0_GTITC_ITLF_Pos             (5UL)          /*!< ITLF (Bit 5)                                          */
38945  #define R_GPT0_GTITC_ITLF_Msk             (0x20UL)       /*!< ITLF (Bitfield-Mask: 0x01)                            */
38946  #define R_GPT0_GTITC_ITLE_Pos             (4UL)          /*!< ITLE (Bit 4)                                          */
38947  #define R_GPT0_GTITC_ITLE_Msk             (0x10UL)       /*!< ITLE (Bitfield-Mask: 0x01)                            */
38948  #define R_GPT0_GTITC_ITLD_Pos             (3UL)          /*!< ITLD (Bit 3)                                          */
38949  #define R_GPT0_GTITC_ITLD_Msk             (0x8UL)        /*!< ITLD (Bitfield-Mask: 0x01)                            */
38950  #define R_GPT0_GTITC_ITLC_Pos             (2UL)          /*!< ITLC (Bit 2)                                          */
38951  #define R_GPT0_GTITC_ITLC_Msk             (0x4UL)        /*!< ITLC (Bitfield-Mask: 0x01)                            */
38952  #define R_GPT0_GTITC_ITLB_Pos             (1UL)          /*!< ITLB (Bit 1)                                          */
38953  #define R_GPT0_GTITC_ITLB_Msk             (0x2UL)        /*!< ITLB (Bitfield-Mask: 0x01)                            */
38954  #define R_GPT0_GTITC_ITLA_Pos             (0UL)          /*!< ITLA (Bit 0)                                          */
38955  #define R_GPT0_GTITC_ITLA_Msk             (0x1UL)        /*!< ITLA (Bitfield-Mask: 0x01)                            */
38956 /* =========================================================  GTCNT  ========================================================= */
38957  #define R_GPT0_GTCNT_GTCNT_Pos            (0UL)          /*!< GTCNT (Bit 0)                                         */
38958  #define R_GPT0_GTCNT_GTCNT_Msk            (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff)                     */
38959 /* =========================================================  GTCCR  ========================================================= */
38960  #define R_GPT0_GTCCR_GTCCR_Pos            (0UL)          /*!< GTCCR (Bit 0)                                         */
38961  #define R_GPT0_GTCCR_GTCCR_Msk            (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff)                     */
38962 /* =========================================================  GTPR  ========================================================== */
38963  #define R_GPT0_GTPR_GTPR_Pos              (0UL)          /*!< GTPR (Bit 0)                                          */
38964  #define R_GPT0_GTPR_GTPR_Msk              (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff)                      */
38965 /* =========================================================  GTPBR  ========================================================= */
38966  #define R_GPT0_GTPBR_GTPBR_Pos            (0UL)          /*!< GTPBR (Bit 0)                                         */
38967  #define R_GPT0_GTPBR_GTPBR_Msk            (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff)                     */
38968 /* ========================================================  GTPDBR  ========================================================= */
38969  #define R_GPT0_GTPDBR_GTPDBR_Pos          (0UL)          /*!< GTPDBR (Bit 0)                                        */
38970  #define R_GPT0_GTPDBR_GTPDBR_Msk          (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff)                    */
38971 /* ========================================================  GTADTRA  ======================================================== */
38972  #define R_GPT0_GTADTRA_GTADTRA_Pos        (0UL)          /*!< GTADTRA (Bit 0)                                       */
38973  #define R_GPT0_GTADTRA_GTADTRA_Msk        (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff)                   */
38974 /* ========================================================  GTADTRB  ======================================================== */
38975  #define R_GPT0_GTADTRB_GTADTRB_Pos        (0UL)          /*!< GTADTRB (Bit 0)                                       */
38976  #define R_GPT0_GTADTRB_GTADTRB_Msk        (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff)                   */
38977 /* =======================================================  GTADTBRA  ======================================================== */
38978  #define R_GPT0_GTADTBRA_GTADTBRA_Pos      (0UL)          /*!< GTADTBRA (Bit 0)                                      */
38979  #define R_GPT0_GTADTBRA_GTADTBRA_Msk      (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff)                  */
38980 /* =======================================================  GTADTBRB  ======================================================== */
38981  #define R_GPT0_GTADTBRB_GTADTBRB_Pos      (0UL)          /*!< GTADTBRB (Bit 0)                                      */
38982  #define R_GPT0_GTADTBRB_GTADTBRB_Msk      (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff)                  */
38983 /* =======================================================  GTADTDBRA  ======================================================= */
38984  #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos    (0UL)          /*!< GTADTDBRA (Bit 0)                                     */
38985  #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk    (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff)                 */
38986 /* =======================================================  GTADTDBRB  ======================================================= */
38987  #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos    (0UL)          /*!< GTADTDBRB (Bit 0)                                     */
38988  #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk    (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff)                 */
38989 /* ========================================================  GTDTCR  ========================================================= */
38990  #define R_GPT0_GTDTCR_TDFER_Pos           (8UL)          /*!< TDFER (Bit 8)                                         */
38991  #define R_GPT0_GTDTCR_TDFER_Msk           (0x100UL)      /*!< TDFER (Bitfield-Mask: 0x01)                           */
38992  #define R_GPT0_GTDTCR_TDBDE_Pos           (5UL)          /*!< TDBDE (Bit 5)                                         */
38993  #define R_GPT0_GTDTCR_TDBDE_Msk           (0x20UL)       /*!< TDBDE (Bitfield-Mask: 0x01)                           */
38994  #define R_GPT0_GTDTCR_TDBUE_Pos           (4UL)          /*!< TDBUE (Bit 4)                                         */
38995  #define R_GPT0_GTDTCR_TDBUE_Msk           (0x10UL)       /*!< TDBUE (Bitfield-Mask: 0x01)                           */
38996  #define R_GPT0_GTDTCR_TDE_Pos             (0UL)          /*!< TDE (Bit 0)                                           */
38997  #define R_GPT0_GTDTCR_TDE_Msk             (0x1UL)        /*!< TDE (Bitfield-Mask: 0x01)                             */
38998 /* =========================================================  GTDVU  ========================================================= */
38999  #define R_GPT0_GTDVU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
39000  #define R_GPT0_GTDVU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
39001 /* =========================================================  GTDVD  ========================================================= */
39002  #define R_GPT0_GTDVD_GTDVD_Pos            (0UL)          /*!< GTDVD (Bit 0)                                         */
39003  #define R_GPT0_GTDVD_GTDVD_Msk            (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff)                     */
39004 /* =========================================================  GTDBU  ========================================================= */
39005  #define R_GPT0_GTDBU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
39006  #define R_GPT0_GTDBU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
39007 /* =========================================================  GTDBD  ========================================================= */
39008  #define R_GPT0_GTDBD_GTDBD_Pos            (0UL)          /*!< GTDBD (Bit 0)                                         */
39009  #define R_GPT0_GTDBD_GTDBD_Msk            (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff)                     */
39010 /* =========================================================  GTSOS  ========================================================= */
39011  #define R_GPT0_GTSOS_SOS_Pos              (0UL)          /*!< SOS (Bit 0)                                           */
39012  #define R_GPT0_GTSOS_SOS_Msk              (0x3UL)        /*!< SOS (Bitfield-Mask: 0x03)                             */
39013 /* ========================================================  GTSOTR  ========================================================= */
39014  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
39015  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
39016 /* ========================================================  GTICLF  ========================================================= */
39017  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
39018  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
39019  #define R_GPT0_GTICLF_ICLFSELC_Pos        (4UL)          /*!< ICLFSELC (Bit 4)                                      */
39020  #define R_GPT0_GTICLF_ICLFSELC_Msk        (0x3f0UL)      /*!< ICLFSELC (Bitfield-Mask: 0x3f)                        */
39021  #define R_GPT0_GTICLF_ICLFB_Pos           (16UL)         /*!< ICLFB (Bit 16)                                        */
39022  #define R_GPT0_GTICLF_ICLFB_Msk           (0x70000UL)    /*!< ICLFB (Bitfield-Mask: 0x07)                           */
39023  #define R_GPT0_GTICLF_ICLFSELD_Pos        (20UL)         /*!< ICLFSELD (Bit 20)                                     */
39024  #define R_GPT0_GTICLF_ICLFSELD_Msk        (0x3f00000UL)  /*!< ICLFSELD (Bitfield-Mask: 0x3f)                        */
39025 /* =========================================================  GTPC  ========================================================== */
39026  #define R_GPT0_GTPC_PCEN_Pos              (0UL)          /*!< PCEN (Bit 0)                                          */
39027  #define R_GPT0_GTPC_PCEN_Msk              (0x1UL)        /*!< PCEN (Bitfield-Mask: 0x01)                            */
39028  #define R_GPT0_GTPC_ASTP_Pos              (8UL)          /*!< ASTP (Bit 8)                                          */
39029  #define R_GPT0_GTPC_ASTP_Msk              (0x100UL)      /*!< ASTP (Bitfield-Mask: 0x01)                            */
39030  #define R_GPT0_GTPC_PCNT_Pos              (16UL)         /*!< PCNT (Bit 16)                                         */
39031  #define R_GPT0_GTPC_PCNT_Msk              (0xfff0000UL)  /*!< PCNT (Bitfield-Mask: 0xfff)                           */
39032 /* ========================================================  GTSECSR  ======================================================== */
39033  #define R_GPT0_GTSECSR_SECSEL0_Pos        (0UL)          /*!< SECSEL0 (Bit 0)                                       */
39034  #define R_GPT0_GTSECSR_SECSEL0_Msk        (0x1UL)        /*!< SECSEL0 (Bitfield-Mask: 0x01)                         */
39035  #define R_GPT0_GTSECSR_SECSEL1_Pos        (1UL)          /*!< SECSEL1 (Bit 1)                                       */
39036  #define R_GPT0_GTSECSR_SECSEL1_Msk        (0x2UL)        /*!< SECSEL1 (Bitfield-Mask: 0x01)                         */
39037  #define R_GPT0_GTSECSR_SECSEL2_Pos        (2UL)          /*!< SECSEL2 (Bit 2)                                       */
39038  #define R_GPT0_GTSECSR_SECSEL2_Msk        (0x4UL)        /*!< SECSEL2 (Bitfield-Mask: 0x01)                         */
39039  #define R_GPT0_GTSECSR_SECSEL3_Pos        (3UL)          /*!< SECSEL3 (Bit 3)                                       */
39040  #define R_GPT0_GTSECSR_SECSEL3_Msk        (0x8UL)        /*!< SECSEL3 (Bitfield-Mask: 0x01)                         */
39041  #define R_GPT0_GTSECSR_SECSEL4_Pos        (4UL)          /*!< SECSEL4 (Bit 4)                                       */
39042  #define R_GPT0_GTSECSR_SECSEL4_Msk        (0x10UL)       /*!< SECSEL4 (Bitfield-Mask: 0x01)                         */
39043  #define R_GPT0_GTSECSR_SECSEL5_Pos        (5UL)          /*!< SECSEL5 (Bit 5)                                       */
39044  #define R_GPT0_GTSECSR_SECSEL5_Msk        (0x20UL)       /*!< SECSEL5 (Bitfield-Mask: 0x01)                         */
39045  #define R_GPT0_GTSECSR_SECSEL6_Pos        (6UL)          /*!< SECSEL6 (Bit 6)                                       */
39046  #define R_GPT0_GTSECSR_SECSEL6_Msk        (0x40UL)       /*!< SECSEL6 (Bitfield-Mask: 0x01)                         */
39047  #define R_GPT0_GTSECSR_SECSEL7_Pos        (7UL)          /*!< SECSEL7 (Bit 7)                                       */
39048  #define R_GPT0_GTSECSR_SECSEL7_Msk        (0x80UL)       /*!< SECSEL7 (Bitfield-Mask: 0x01)                         */
39049  #define R_GPT0_GTSECSR_SECSEL8_Pos        (8UL)          /*!< SECSEL8 (Bit 8)                                       */
39050  #define R_GPT0_GTSECSR_SECSEL8_Msk        (0x100UL)      /*!< SECSEL8 (Bitfield-Mask: 0x01)                         */
39051  #define R_GPT0_GTSECSR_SECSEL9_Pos        (9UL)          /*!< SECSEL9 (Bit 9)                                       */
39052  #define R_GPT0_GTSECSR_SECSEL9_Msk        (0x200UL)      /*!< SECSEL9 (Bitfield-Mask: 0x01)                         */
39053 /* ========================================================  GTSECR  ========================================================= */
39054  #define R_GPT0_GTSECR_SBDCE_Pos           (0UL)          /*!< SBDCE (Bit 0)                                         */
39055  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
39056  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
39057  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
39058  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
39059  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
39060  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
39061  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
39062  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
39063  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
39064  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
39065  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
39066 
39067 /* =========================================================================================================================== */
39068 /* ================                                        R_GPT_GTCLK                                        ================ */
39069 /* =========================================================================================================================== */
39070 
39071 /* ========================================================  GTCLKCR  ======================================================== */
39072  #define R_GPT_GTCLK_GTCLKCR_BPEN_Pos    (0UL)   /*!< BPEN (Bit 0)                                          */
39073  #define R_GPT_GTCLK_GTCLKCR_BPEN_Msk    (0x1UL) /*!< BPEN (Bitfield-Mask: 0x01)                            */
39074 
39075 /* =========================================================================================================================== */
39076 /* ================                                         R_GPT_ODC                                         ================ */
39077 /* =========================================================================================================================== */
39078 
39079 /* =======================================================  GTDLYCR1  ======================================================== */
39080  #define R_GPT_ODC_GTDLYCR1_FRANGE_Pos     (8UL)      /*!< FRANGE (Bit 8)                                        */
39081  #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk     (0x100UL)  /*!< FRANGE (Bitfield-Mask: 0x01)                          */
39082  #define R_GPT_ODC_GTDLYCR1_DLYRST_Pos     (1UL)      /*!< DLYRST (Bit 1)                                        */
39083  #define R_GPT_ODC_GTDLYCR1_DLYRST_Msk     (0x2UL)    /*!< DLYRST (Bitfield-Mask: 0x01)                          */
39084  #define R_GPT_ODC_GTDLYCR1_DLLEN_Pos      (0UL)      /*!< DLLEN (Bit 0)                                         */
39085  #define R_GPT_ODC_GTDLYCR1_DLLEN_Msk      (0x1UL)    /*!< DLLEN (Bitfield-Mask: 0x01)                           */
39086 /* =======================================================  GTDLYCR2  ======================================================== */
39087  #define R_GPT_ODC_GTDLYCR2_DLYDENB_Pos    (12UL)     /*!< DLYDENB (Bit 12)                                      */
39088  #define R_GPT_ODC_GTDLYCR2_DLYDENB_Msk    (0x1000UL) /*!< DLYDENB (Bitfield-Mask: 0x01)                         */
39089  #define R_GPT_ODC_GTDLYCR2_DLYEN_Pos      (8UL)      /*!< DLYEN (Bit 8)                                         */
39090  #define R_GPT_ODC_GTDLYCR2_DLYEN_Msk      (0x100UL)  /*!< DLYEN (Bitfield-Mask: 0x01)                           */
39091  #define R_GPT_ODC_GTDLYCR2_DLYBS_Pos      (0UL)      /*!< DLYBS (Bit 0)                                         */
39092  #define R_GPT_ODC_GTDLYCR2_DLYBS_Msk      (0x1UL)    /*!< DLYBS (Bitfield-Mask: 0x01)                           */
39093 
39094 /* =========================================================================================================================== */
39095 /* ================                                         R_GPT_OPS                                         ================ */
39096 /* =========================================================================================================================== */
39097 
39098 /* =========================================================  OPSCR  ========================================================= */
39099  #define R_GPT_OPS_OPSCR_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
39100  #define R_GPT_OPS_OPSCR_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
39101  #define R_GPT_OPS_OPSCR_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
39102  #define R_GPT_OPS_OPSCR_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
39103  #define R_GPT_OPS_OPSCR_GODF_Pos     (26UL)         /*!< GODF (Bit 26)                                         */
39104  #define R_GPT_OPS_OPSCR_GODF_Msk     (0x4000000UL)  /*!< GODF (Bitfield-Mask: 0x01)                            */
39105  #define R_GPT_OPS_OPSCR_GRP_Pos      (24UL)         /*!< GRP (Bit 24)                                          */
39106  #define R_GPT_OPS_OPSCR_GRP_Msk      (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
39107  #define R_GPT_OPS_OPSCR_ALIGN_Pos    (21UL)         /*!< ALIGN (Bit 21)                                        */
39108  #define R_GPT_OPS_OPSCR_ALIGN_Msk    (0x200000UL)   /*!< ALIGN (Bitfield-Mask: 0x01)                           */
39109  #define R_GPT_OPS_OPSCR_RV_Pos       (20UL)         /*!< RV (Bit 20)                                           */
39110  #define R_GPT_OPS_OPSCR_RV_Msk       (0x100000UL)   /*!< RV (Bitfield-Mask: 0x01)                              */
39111  #define R_GPT_OPS_OPSCR_INV_Pos      (19UL)         /*!< INV (Bit 19)                                          */
39112  #define R_GPT_OPS_OPSCR_INV_Msk      (0x80000UL)    /*!< INV (Bitfield-Mask: 0x01)                             */
39113  #define R_GPT_OPS_OPSCR_N_Pos        (18UL)         /*!< N (Bit 18)                                            */
39114  #define R_GPT_OPS_OPSCR_N_Msk        (0x40000UL)    /*!< N (Bitfield-Mask: 0x01)                               */
39115  #define R_GPT_OPS_OPSCR_P_Pos        (17UL)         /*!< P (Bit 17)                                            */
39116  #define R_GPT_OPS_OPSCR_P_Msk        (0x20000UL)    /*!< P (Bitfield-Mask: 0x01)                               */
39117  #define R_GPT_OPS_OPSCR_FB_Pos       (16UL)         /*!< FB (Bit 16)                                           */
39118  #define R_GPT_OPS_OPSCR_FB_Msk       (0x10000UL)    /*!< FB (Bitfield-Mask: 0x01)                              */
39119  #define R_GPT_OPS_OPSCR_EN_Pos       (8UL)          /*!< EN (Bit 8)                                            */
39120  #define R_GPT_OPS_OPSCR_EN_Msk       (0x100UL)      /*!< EN (Bitfield-Mask: 0x01)                              */
39121  #define R_GPT_OPS_OPSCR_W_Pos        (6UL)          /*!< W (Bit 6)                                             */
39122  #define R_GPT_OPS_OPSCR_W_Msk        (0x40UL)       /*!< W (Bitfield-Mask: 0x01)                               */
39123  #define R_GPT_OPS_OPSCR_V_Pos        (5UL)          /*!< V (Bit 5)                                             */
39124  #define R_GPT_OPS_OPSCR_V_Msk        (0x20UL)       /*!< V (Bitfield-Mask: 0x01)                               */
39125  #define R_GPT_OPS_OPSCR_U_Pos        (4UL)          /*!< U (Bit 4)                                             */
39126  #define R_GPT_OPS_OPSCR_U_Msk        (0x10UL)       /*!< U (Bitfield-Mask: 0x01)                               */
39127  #define R_GPT_OPS_OPSCR_WF_Pos       (2UL)          /*!< WF (Bit 2)                                            */
39128  #define R_GPT_OPS_OPSCR_WF_Msk       (0x4UL)        /*!< WF (Bitfield-Mask: 0x01)                              */
39129  #define R_GPT_OPS_OPSCR_VF_Pos       (1UL)          /*!< VF (Bit 1)                                            */
39130  #define R_GPT_OPS_OPSCR_VF_Msk       (0x2UL)        /*!< VF (Bitfield-Mask: 0x01)                              */
39131  #define R_GPT_OPS_OPSCR_UF_Pos       (0UL)          /*!< UF (Bit 0)                                            */
39132  #define R_GPT_OPS_OPSCR_UF_Msk       (0x1UL)        /*!< UF (Bitfield-Mask: 0x01)                              */
39133 
39134 /* =========================================================================================================================== */
39135 /* ================                                        R_GPT_POEG0                                        ================ */
39136 /* =========================================================================================================================== */
39137 
39138 /* =========================================================  POEGG  ========================================================= */
39139  #define R_GPT_POEG0_POEGG_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
39140  #define R_GPT_POEG0_POEGG_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
39141  #define R_GPT_POEG0_POEGG_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
39142  #define R_GPT_POEG0_POEGG_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
39143  #define R_GPT_POEG0_POEGG_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
39144  #define R_GPT_POEG0_POEGG_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
39145  #define R_GPT_POEG0_POEGG_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
39146  #define R_GPT_POEG0_POEGG_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
39147  #define R_GPT_POEG0_POEGG_CDRE_Pos     (8UL)          /*!< CDRE (Bit 8)                                          */
39148  #define R_GPT_POEG0_POEGG_CDRE_Msk     (0x100UL)      /*!< CDRE (Bitfield-Mask: 0x01)                            */
39149  #define R_GPT_POEG0_POEGG_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
39150  #define R_GPT_POEG0_POEGG_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
39151  #define R_GPT_POEG0_POEGG_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
39152  #define R_GPT_POEG0_POEGG_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
39153  #define R_GPT_POEG0_POEGG_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
39154  #define R_GPT_POEG0_POEGG_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
39155  #define R_GPT_POEG0_POEGG_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
39156  #define R_GPT_POEG0_POEGG_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
39157  #define R_GPT_POEG0_POEGG_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
39158  #define R_GPT_POEG0_POEGG_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
39159  #define R_GPT_POEG0_POEGG_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
39160  #define R_GPT_POEG0_POEGG_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
39161  #define R_GPT_POEG0_POEGG_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
39162  #define R_GPT_POEG0_POEGG_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
39163 
39164 /* =========================================================================================================================== */
39165 /* ================                                           R_ICU                                           ================ */
39166 /* =========================================================================================================================== */
39167 
39168 /* =========================================================  IRQCR  ========================================================= */
39169  #define R_ICU_IRQCR_FLTEN_Pos           (7UL)          /*!< FLTEN (Bit 7)                                         */
39170  #define R_ICU_IRQCR_FLTEN_Msk           (0x80UL)       /*!< FLTEN (Bitfield-Mask: 0x01)                           */
39171  #define R_ICU_IRQCR_FCLKSEL_Pos         (4UL)          /*!< FCLKSEL (Bit 4)                                       */
39172  #define R_ICU_IRQCR_FCLKSEL_Msk         (0x30UL)       /*!< FCLKSEL (Bitfield-Mask: 0x03)                         */
39173  #define R_ICU_IRQCR_IRQMD_Pos           (0UL)          /*!< IRQMD (Bit 0)                                         */
39174  #define R_ICU_IRQCR_IRQMD_Msk           (0x3UL)        /*!< IRQMD (Bitfield-Mask: 0x03)                           */
39175 /* =========================================================  NMISR  ========================================================= */
39176  #define R_ICU_NMISR_SPEST_Pos           (12UL)         /*!< SPEST (Bit 12)                                        */
39177  #define R_ICU_NMISR_SPEST_Msk           (0x1000UL)     /*!< SPEST (Bitfield-Mask: 0x01)                           */
39178  #define R_ICU_NMISR_BUSMST_Pos          (11UL)         /*!< BUSMST (Bit 11)                                       */
39179  #define R_ICU_NMISR_BUSMST_Msk          (0x800UL)      /*!< BUSMST (Bitfield-Mask: 0x01)                          */
39180  #define R_ICU_NMISR_BUSSST_Pos          (10UL)         /*!< BUSSST (Bit 10)                                       */
39181  #define R_ICU_NMISR_BUSSST_Msk          (0x400UL)      /*!< BUSSST (Bitfield-Mask: 0x01)                          */
39182  #define R_ICU_NMISR_RECCST_Pos          (9UL)          /*!< RECCST (Bit 9)                                        */
39183  #define R_ICU_NMISR_RECCST_Msk          (0x200UL)      /*!< RECCST (Bitfield-Mask: 0x01)                          */
39184  #define R_ICU_NMISR_RPEST_Pos           (8UL)          /*!< RPEST (Bit 8)                                         */
39185  #define R_ICU_NMISR_RPEST_Msk           (0x100UL)      /*!< RPEST (Bitfield-Mask: 0x01)                           */
39186  #define R_ICU_NMISR_NMIST_Pos           (7UL)          /*!< NMIST (Bit 7)                                         */
39187  #define R_ICU_NMISR_NMIST_Msk           (0x80UL)       /*!< NMIST (Bitfield-Mask: 0x01)                           */
39188  #define R_ICU_NMISR_OSTST_Pos           (6UL)          /*!< OSTST (Bit 6)                                         */
39189  #define R_ICU_NMISR_OSTST_Msk           (0x40UL)       /*!< OSTST (Bitfield-Mask: 0x01)                           */
39190  #define R_ICU_NMISR_VBATTST_Pos         (4UL)          /*!< VBATTST (Bit 4)                                       */
39191  #define R_ICU_NMISR_VBATTST_Msk         (0x10UL)       /*!< VBATTST (Bitfield-Mask: 0x01)                         */
39192  #define R_ICU_NMISR_LVD2ST_Pos          (3UL)          /*!< LVD2ST (Bit 3)                                        */
39193  #define R_ICU_NMISR_LVD2ST_Msk          (0x8UL)        /*!< LVD2ST (Bitfield-Mask: 0x01)                          */
39194  #define R_ICU_NMISR_LVD1ST_Pos          (2UL)          /*!< LVD1ST (Bit 2)                                        */
39195  #define R_ICU_NMISR_LVD1ST_Msk          (0x4UL)        /*!< LVD1ST (Bitfield-Mask: 0x01)                          */
39196  #define R_ICU_NMISR_WDTST_Pos           (1UL)          /*!< WDTST (Bit 1)                                         */
39197  #define R_ICU_NMISR_WDTST_Msk           (0x2UL)        /*!< WDTST (Bitfield-Mask: 0x01)                           */
39198  #define R_ICU_NMISR_IWDTST_Pos          (0UL)          /*!< IWDTST (Bit 0)                                        */
39199  #define R_ICU_NMISR_IWDTST_Msk          (0x1UL)        /*!< IWDTST (Bitfield-Mask: 0x01)                          */
39200  #define R_ICU_NMISR_TZFST_Pos           (13UL)         /*!< TZFST (Bit 13)                                        */
39201  #define R_ICU_NMISR_TZFST_Msk           (0x2000UL)     /*!< TZFST (Bitfield-Mask: 0x01)                           */
39202  #define R_ICU_NMISR_CPEST_Pos           (15UL)         /*!< CPEST (Bit 15)                                        */
39203  #define R_ICU_NMISR_CPEST_Msk           (0x8000UL)     /*!< CPEST (Bitfield-Mask: 0x01)                           */
39204 /* =========================================================  NMIER  ========================================================= */
39205  #define R_ICU_NMIER_SPEEN_Pos           (12UL)         /*!< SPEEN (Bit 12)                                        */
39206  #define R_ICU_NMIER_SPEEN_Msk           (0x1000UL)     /*!< SPEEN (Bitfield-Mask: 0x01)                           */
39207  #define R_ICU_NMIER_BUSMEN_Pos          (11UL)         /*!< BUSMEN (Bit 11)                                       */
39208  #define R_ICU_NMIER_BUSMEN_Msk          (0x800UL)      /*!< BUSMEN (Bitfield-Mask: 0x01)                          */
39209  #define R_ICU_NMIER_BUSSEN_Pos          (10UL)         /*!< BUSSEN (Bit 10)                                       */
39210  #define R_ICU_NMIER_BUSSEN_Msk          (0x400UL)      /*!< BUSSEN (Bitfield-Mask: 0x01)                          */
39211  #define R_ICU_NMIER_RECCEN_Pos          (9UL)          /*!< RECCEN (Bit 9)                                        */
39212  #define R_ICU_NMIER_RECCEN_Msk          (0x200UL)      /*!< RECCEN (Bitfield-Mask: 0x01)                          */
39213  #define R_ICU_NMIER_RPEEN_Pos           (8UL)          /*!< RPEEN (Bit 8)                                         */
39214  #define R_ICU_NMIER_RPEEN_Msk           (0x100UL)      /*!< RPEEN (Bitfield-Mask: 0x01)                           */
39215  #define R_ICU_NMIER_NMIEN_Pos           (7UL)          /*!< NMIEN (Bit 7)                                         */
39216  #define R_ICU_NMIER_NMIEN_Msk           (0x80UL)       /*!< NMIEN (Bitfield-Mask: 0x01)                           */
39217  #define R_ICU_NMIER_OSTEN_Pos           (6UL)          /*!< OSTEN (Bit 6)                                         */
39218  #define R_ICU_NMIER_OSTEN_Msk           (0x40UL)       /*!< OSTEN (Bitfield-Mask: 0x01)                           */
39219  #define R_ICU_NMIER_VBATTEN_Pos         (4UL)          /*!< VBATTEN (Bit 4)                                       */
39220  #define R_ICU_NMIER_VBATTEN_Msk         (0x10UL)       /*!< VBATTEN (Bitfield-Mask: 0x01)                         */
39221  #define R_ICU_NMIER_LVD2EN_Pos          (3UL)          /*!< LVD2EN (Bit 3)                                        */
39222  #define R_ICU_NMIER_LVD2EN_Msk          (0x8UL)        /*!< LVD2EN (Bitfield-Mask: 0x01)                          */
39223  #define R_ICU_NMIER_LVD1EN_Pos          (2UL)          /*!< LVD1EN (Bit 2)                                        */
39224  #define R_ICU_NMIER_LVD1EN_Msk          (0x4UL)        /*!< LVD1EN (Bitfield-Mask: 0x01)                          */
39225  #define R_ICU_NMIER_WDTEN_Pos           (1UL)          /*!< WDTEN (Bit 1)                                         */
39226  #define R_ICU_NMIER_WDTEN_Msk           (0x2UL)        /*!< WDTEN (Bitfield-Mask: 0x01)                           */
39227  #define R_ICU_NMIER_IWDTEN_Pos          (0UL)          /*!< IWDTEN (Bit 0)                                        */
39228  #define R_ICU_NMIER_IWDTEN_Msk          (0x1UL)        /*!< IWDTEN (Bitfield-Mask: 0x01)                          */
39229  #define R_ICU_NMIER_TZFEN_Pos           (13UL)         /*!< TZFEN (Bit 13)                                        */
39230  #define R_ICU_NMIER_TZFEN_Msk           (0x2000UL)     /*!< TZFEN (Bitfield-Mask: 0x01)                           */
39231  #define R_ICU_NMIER_CPEEN_Pos           (15UL)         /*!< CPEEN (Bit 15)                                        */
39232  #define R_ICU_NMIER_CPEEN_Msk           (0x8000UL)     /*!< CPEEN (Bitfield-Mask: 0x01)                           */
39233 /* ========================================================  NMICLR  ========================================================= */
39234  #define R_ICU_NMICLR_SPECLR_Pos         (12UL)         /*!< SPECLR (Bit 12)                                       */
39235  #define R_ICU_NMICLR_SPECLR_Msk         (0x1000UL)     /*!< SPECLR (Bitfield-Mask: 0x01)                          */
39236  #define R_ICU_NMICLR_BUSMCLR_Pos        (11UL)         /*!< BUSMCLR (Bit 11)                                      */
39237  #define R_ICU_NMICLR_BUSMCLR_Msk        (0x800UL)      /*!< BUSMCLR (Bitfield-Mask: 0x01)                         */
39238  #define R_ICU_NMICLR_BUSSCLR_Pos        (10UL)         /*!< BUSSCLR (Bit 10)                                      */
39239  #define R_ICU_NMICLR_BUSSCLR_Msk        (0x400UL)      /*!< BUSSCLR (Bitfield-Mask: 0x01)                         */
39240  #define R_ICU_NMICLR_RECCCLR_Pos        (9UL)          /*!< RECCCLR (Bit 9)                                       */
39241  #define R_ICU_NMICLR_RECCCLR_Msk        (0x200UL)      /*!< RECCCLR (Bitfield-Mask: 0x01)                         */
39242  #define R_ICU_NMICLR_RPECLR_Pos         (8UL)          /*!< RPECLR (Bit 8)                                        */
39243  #define R_ICU_NMICLR_RPECLR_Msk         (0x100UL)      /*!< RPECLR (Bitfield-Mask: 0x01)                          */
39244  #define R_ICU_NMICLR_NMICLR_Pos         (7UL)          /*!< NMICLR (Bit 7)                                        */
39245  #define R_ICU_NMICLR_NMICLR_Msk         (0x80UL)       /*!< NMICLR (Bitfield-Mask: 0x01)                          */
39246  #define R_ICU_NMICLR_OSTCLR_Pos         (6UL)          /*!< OSTCLR (Bit 6)                                        */
39247  #define R_ICU_NMICLR_OSTCLR_Msk         (0x40UL)       /*!< OSTCLR (Bitfield-Mask: 0x01)                          */
39248  #define R_ICU_NMICLR_VBATTCLR_Pos       (4UL)          /*!< VBATTCLR (Bit 4)                                      */
39249  #define R_ICU_NMICLR_VBATTCLR_Msk       (0x10UL)       /*!< VBATTCLR (Bitfield-Mask: 0x01)                        */
39250  #define R_ICU_NMICLR_LVD2CLR_Pos        (3UL)          /*!< LVD2CLR (Bit 3)                                       */
39251  #define R_ICU_NMICLR_LVD2CLR_Msk        (0x8UL)        /*!< LVD2CLR (Bitfield-Mask: 0x01)                         */
39252  #define R_ICU_NMICLR_LVD1CLR_Pos        (2UL)          /*!< LVD1CLR (Bit 2)                                       */
39253  #define R_ICU_NMICLR_LVD1CLR_Msk        (0x4UL)        /*!< LVD1CLR (Bitfield-Mask: 0x01)                         */
39254  #define R_ICU_NMICLR_WDTCLR_Pos         (1UL)          /*!< WDTCLR (Bit 1)                                        */
39255  #define R_ICU_NMICLR_WDTCLR_Msk         (0x2UL)        /*!< WDTCLR (Bitfield-Mask: 0x01)                          */
39256  #define R_ICU_NMICLR_IWDTCLR_Pos        (0UL)          /*!< IWDTCLR (Bit 0)                                       */
39257  #define R_ICU_NMICLR_IWDTCLR_Msk        (0x1UL)        /*!< IWDTCLR (Bitfield-Mask: 0x01)                         */
39258  #define R_ICU_NMICLR_TZFCLR_Pos         (13UL)         /*!< TZFCLR (Bit 13)                                       */
39259  #define R_ICU_NMICLR_TZFCLR_Msk         (0x2000UL)     /*!< TZFCLR (Bitfield-Mask: 0x01)                          */
39260  #define R_ICU_NMICLR_CPECLR_Pos         (15UL)         /*!< CPECLR (Bit 15)                                       */
39261  #define R_ICU_NMICLR_CPECLR_Msk         (0x8000UL)     /*!< CPECLR (Bitfield-Mask: 0x01)                          */
39262 /* =========================================================  NMICR  ========================================================= */
39263  #define R_ICU_NMICR_NFLTEN_Pos          (7UL)          /*!< NFLTEN (Bit 7)                                        */
39264  #define R_ICU_NMICR_NFLTEN_Msk          (0x80UL)       /*!< NFLTEN (Bitfield-Mask: 0x01)                          */
39265  #define R_ICU_NMICR_NFCLKSEL_Pos        (4UL)          /*!< NFCLKSEL (Bit 4)                                      */
39266  #define R_ICU_NMICR_NFCLKSEL_Msk        (0x30UL)       /*!< NFCLKSEL (Bitfield-Mask: 0x03)                        */
39267  #define R_ICU_NMICR_NMIMD_Pos           (0UL)          /*!< NMIMD (Bit 0)                                         */
39268  #define R_ICU_NMICR_NMIMD_Msk           (0x1UL)        /*!< NMIMD (Bitfield-Mask: 0x01)                           */
39269 /* =========================================================  IELSR  ========================================================= */
39270  #define R_ICU_IELSR_DTCE_Pos            (24UL)         /*!< DTCE (Bit 24)                                         */
39271  #define R_ICU_IELSR_DTCE_Msk            (0x1000000UL)  /*!< DTCE (Bitfield-Mask: 0x01)                            */
39272  #define R_ICU_IELSR_IR_Pos              (16UL)         /*!< IR (Bit 16)                                           */
39273  #define R_ICU_IELSR_IR_Msk              (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
39274  #define R_ICU_IELSR_IELS_Pos            (0UL)          /*!< IELS (Bit 0)                                          */
39275  #define R_ICU_IELSR_IELS_Msk            (0x1ffUL)      /*!< IELS (Bitfield-Mask: 0x1ff)                           */
39276 /* =========================================================  DELSR  ========================================================= */
39277  #define R_ICU_DELSR_IR_Pos              (16UL)         /*!< IR (Bit 16)                                           */
39278  #define R_ICU_DELSR_IR_Msk              (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
39279  #define R_ICU_DELSR_DELS_Pos            (0UL)          /*!< DELS (Bit 0)                                          */
39280  #define R_ICU_DELSR_DELS_Msk            (0x1ffUL)      /*!< DELS (Bitfield-Mask: 0x1ff)                           */
39281 /* ========================================================  SELSR0  ========================================================= */
39282  #define R_ICU_SELSR0_SELS_Pos           (0UL)          /*!< SELS (Bit 0)                                          */
39283  #define R_ICU_SELSR0_SELS_Msk           (0x1ffUL)      /*!< SELS (Bitfield-Mask: 0x1ff)                           */
39284 /* =========================================================  WUPEN  ========================================================= */
39285  #define R_ICU_WUPEN_IIC0WUPEN_Pos       (31UL)         /*!< IIC0WUPEN (Bit 31)                                    */
39286  #define R_ICU_WUPEN_IIC0WUPEN_Msk       (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01)                       */
39287  #define R_ICU_WUPEN_AGT1CBWUPEN_Pos     (30UL)         /*!< AGT1CBWUPEN (Bit 30)                                  */
39288  #define R_ICU_WUPEN_AGT1CBWUPEN_Msk     (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01)                     */
39289  #define R_ICU_WUPEN_AGT1CAWUPEN_Pos     (29UL)         /*!< AGT1CAWUPEN (Bit 29)                                  */
39290  #define R_ICU_WUPEN_AGT1CAWUPEN_Msk     (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01)                     */
39291  #define R_ICU_WUPEN_AGT1UDWUPEN_Pos     (28UL)         /*!< AGT1UDWUPEN (Bit 28)                                  */
39292  #define R_ICU_WUPEN_AGT1UDWUPEN_Msk     (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01)                     */
39293  #define R_ICU_WUPEN_USBFSWUPEN_Pos      (27UL)         /*!< USBFSWUPEN (Bit 27)                                   */
39294  #define R_ICU_WUPEN_USBFSWUPEN_Msk      (0x8000000UL)  /*!< USBFSWUPEN (Bitfield-Mask: 0x01)                      */
39295  #define R_ICU_WUPEN_USBHSWUPEN_Pos      (26UL)         /*!< USBHSWUPEN (Bit 26)                                   */
39296  #define R_ICU_WUPEN_USBHSWUPEN_Msk      (0x4000000UL)  /*!< USBHSWUPEN (Bitfield-Mask: 0x01)                      */
39297  #define R_ICU_WUPEN_RTCPRDWUPEN_Pos     (25UL)         /*!< RTCPRDWUPEN (Bit 25)                                  */
39298  #define R_ICU_WUPEN_RTCPRDWUPEN_Msk     (0x2000000UL)  /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01)                     */
39299  #define R_ICU_WUPEN_RTCALMWUPEN_Pos     (24UL)         /*!< RTCALMWUPEN (Bit 24)                                  */
39300  #define R_ICU_WUPEN_RTCALMWUPEN_Msk     (0x1000000UL)  /*!< RTCALMWUPEN (Bitfield-Mask: 0x01)                     */
39301  #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos    (23UL)         /*!< ACMPLP0WUPEN (Bit 23)                                 */
39302  #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk    (0x800000UL)   /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01)                    */
39303  #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos    (22UL)         /*!< ACMPHS0WUPEN (Bit 22)                                 */
39304  #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk    (0x400000UL)   /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01)                    */
39305  #define R_ICU_WUPEN_VBATTWUPEN_Pos      (20UL)         /*!< VBATTWUPEN (Bit 20)                                   */
39306  #define R_ICU_WUPEN_VBATTWUPEN_Msk      (0x100000UL)   /*!< VBATTWUPEN (Bitfield-Mask: 0x01)                      */
39307  #define R_ICU_WUPEN_LVD2WUPEN_Pos       (19UL)         /*!< LVD2WUPEN (Bit 19)                                    */
39308  #define R_ICU_WUPEN_LVD2WUPEN_Msk       (0x80000UL)    /*!< LVD2WUPEN (Bitfield-Mask: 0x01)                       */
39309  #define R_ICU_WUPEN_LVD1WUPEN_Pos       (18UL)         /*!< LVD1WUPEN (Bit 18)                                    */
39310  #define R_ICU_WUPEN_LVD1WUPEN_Msk       (0x40000UL)    /*!< LVD1WUPEN (Bitfield-Mask: 0x01)                       */
39311  #define R_ICU_WUPEN_KEYWUPEN_Pos        (17UL)         /*!< KEYWUPEN (Bit 17)                                     */
39312  #define R_ICU_WUPEN_KEYWUPEN_Msk        (0x20000UL)    /*!< KEYWUPEN (Bitfield-Mask: 0x01)                        */
39313  #define R_ICU_WUPEN_IWDTWUPEN_Pos       (16UL)         /*!< IWDTWUPEN (Bit 16)                                    */
39314  #define R_ICU_WUPEN_IWDTWUPEN_Msk       (0x10000UL)    /*!< IWDTWUPEN (Bitfield-Mask: 0x01)                       */
39315  #define R_ICU_WUPEN_IRQWUPEN_Pos        (0UL)          /*!< IRQWUPEN (Bit 0)                                      */
39316  #define R_ICU_WUPEN_IRQWUPEN_Msk        (0x1UL)        /*!< IRQWUPEN (Bitfield-Mask: 0x01)                        */
39317 /* ========================================================  WUPEN1  ========================================================= */
39318  #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos    (0UL)          /*!< AGT3UDWUPEN (Bit 0)                                   */
39319  #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk    (0x1UL)        /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01)                     */
39320  #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos    (1UL)          /*!< AGT3CAWUPEN (Bit 1)                                   */
39321  #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk    (0x2UL)        /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01)                     */
39322  #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos    (2UL)          /*!< AGT3CBWUPEN (Bit 2)                                   */
39323  #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk    (0x4UL)        /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01)                     */
39324 /* =========================================================  IELEN  ========================================================= */
39325  #define R_ICU_IELEN_IELEN_Pos           (1UL)          /*!< IELEN (Bit 1)                                         */
39326  #define R_ICU_IELEN_IELEN_Msk           (0x2UL)        /*!< IELEN (Bitfield-Mask: 0x01)                           */
39327  #define R_ICU_IELEN_RTCINTEN_Pos        (0UL)          /*!< RTCINTEN (Bit 0)                                      */
39328  #define R_ICU_IELEN_RTCINTEN_Msk        (0x1UL)        /*!< RTCINTEN (Bitfield-Mask: 0x01)                        */
39329 
39330 /* =========================================================================================================================== */
39331 /* ================                                          R_IIC0                                           ================ */
39332 /* =========================================================================================================================== */
39333 
39334 /* =========================================================  ICCR1  ========================================================= */
39335  #define R_IIC0_ICCR1_ICE_Pos        (7UL)    /*!< ICE (Bit 7)                                           */
39336  #define R_IIC0_ICCR1_ICE_Msk        (0x80UL) /*!< ICE (Bitfield-Mask: 0x01)                             */
39337  #define R_IIC0_ICCR1_IICRST_Pos     (6UL)    /*!< IICRST (Bit 6)                                        */
39338  #define R_IIC0_ICCR1_IICRST_Msk     (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01)                          */
39339  #define R_IIC0_ICCR1_CLO_Pos        (5UL)    /*!< CLO (Bit 5)                                           */
39340  #define R_IIC0_ICCR1_CLO_Msk        (0x20UL) /*!< CLO (Bitfield-Mask: 0x01)                             */
39341  #define R_IIC0_ICCR1_SOWP_Pos       (4UL)    /*!< SOWP (Bit 4)                                          */
39342  #define R_IIC0_ICCR1_SOWP_Msk       (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01)                            */
39343  #define R_IIC0_ICCR1_SCLO_Pos       (3UL)    /*!< SCLO (Bit 3)                                          */
39344  #define R_IIC0_ICCR1_SCLO_Msk       (0x8UL)  /*!< SCLO (Bitfield-Mask: 0x01)                            */
39345  #define R_IIC0_ICCR1_SDAO_Pos       (2UL)    /*!< SDAO (Bit 2)                                          */
39346  #define R_IIC0_ICCR1_SDAO_Msk       (0x4UL)  /*!< SDAO (Bitfield-Mask: 0x01)                            */
39347  #define R_IIC0_ICCR1_SCLI_Pos       (1UL)    /*!< SCLI (Bit 1)                                          */
39348  #define R_IIC0_ICCR1_SCLI_Msk       (0x2UL)  /*!< SCLI (Bitfield-Mask: 0x01)                            */
39349  #define R_IIC0_ICCR1_SDAI_Pos       (0UL)    /*!< SDAI (Bit 0)                                          */
39350  #define R_IIC0_ICCR1_SDAI_Msk       (0x1UL)  /*!< SDAI (Bitfield-Mask: 0x01)                            */
39351 /* =========================================================  ICCR2  ========================================================= */
39352  #define R_IIC0_ICCR2_BBSY_Pos       (7UL)    /*!< BBSY (Bit 7)                                          */
39353  #define R_IIC0_ICCR2_BBSY_Msk       (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01)                            */
39354  #define R_IIC0_ICCR2_MST_Pos        (6UL)    /*!< MST (Bit 6)                                           */
39355  #define R_IIC0_ICCR2_MST_Msk        (0x40UL) /*!< MST (Bitfield-Mask: 0x01)                             */
39356  #define R_IIC0_ICCR2_TRS_Pos        (5UL)    /*!< TRS (Bit 5)                                           */
39357  #define R_IIC0_ICCR2_TRS_Msk        (0x20UL) /*!< TRS (Bitfield-Mask: 0x01)                             */
39358  #define R_IIC0_ICCR2_SP_Pos         (3UL)    /*!< SP (Bit 3)                                            */
39359  #define R_IIC0_ICCR2_SP_Msk         (0x8UL)  /*!< SP (Bitfield-Mask: 0x01)                              */
39360  #define R_IIC0_ICCR2_RS_Pos         (2UL)    /*!< RS (Bit 2)                                            */
39361  #define R_IIC0_ICCR2_RS_Msk         (0x4UL)  /*!< RS (Bitfield-Mask: 0x01)                              */
39362  #define R_IIC0_ICCR2_ST_Pos         (1UL)    /*!< ST (Bit 1)                                            */
39363  #define R_IIC0_ICCR2_ST_Msk         (0x2UL)  /*!< ST (Bitfield-Mask: 0x01)                              */
39364 /* =========================================================  ICMR1  ========================================================= */
39365  #define R_IIC0_ICMR1_MTWP_Pos       (7UL)    /*!< MTWP (Bit 7)                                          */
39366  #define R_IIC0_ICMR1_MTWP_Msk       (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01)                            */
39367  #define R_IIC0_ICMR1_CKS_Pos        (4UL)    /*!< CKS (Bit 4)                                           */
39368  #define R_IIC0_ICMR1_CKS_Msk        (0x70UL) /*!< CKS (Bitfield-Mask: 0x07)                             */
39369  #define R_IIC0_ICMR1_BCWP_Pos       (3UL)    /*!< BCWP (Bit 3)                                          */
39370  #define R_IIC0_ICMR1_BCWP_Msk       (0x8UL)  /*!< BCWP (Bitfield-Mask: 0x01)                            */
39371  #define R_IIC0_ICMR1_BC_Pos         (0UL)    /*!< BC (Bit 0)                                            */
39372  #define R_IIC0_ICMR1_BC_Msk         (0x7UL)  /*!< BC (Bitfield-Mask: 0x07)                              */
39373 /* =========================================================  ICMR2  ========================================================= */
39374  #define R_IIC0_ICMR2_DLCS_Pos       (7UL)    /*!< DLCS (Bit 7)                                          */
39375  #define R_IIC0_ICMR2_DLCS_Msk       (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01)                            */
39376  #define R_IIC0_ICMR2_SDDL_Pos       (4UL)    /*!< SDDL (Bit 4)                                          */
39377  #define R_IIC0_ICMR2_SDDL_Msk       (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07)                            */
39378  #define R_IIC0_ICMR2_TMOH_Pos       (2UL)    /*!< TMOH (Bit 2)                                          */
39379  #define R_IIC0_ICMR2_TMOH_Msk       (0x4UL)  /*!< TMOH (Bitfield-Mask: 0x01)                            */
39380  #define R_IIC0_ICMR2_TMOL_Pos       (1UL)    /*!< TMOL (Bit 1)                                          */
39381  #define R_IIC0_ICMR2_TMOL_Msk       (0x2UL)  /*!< TMOL (Bitfield-Mask: 0x01)                            */
39382  #define R_IIC0_ICMR2_TMOS_Pos       (0UL)    /*!< TMOS (Bit 0)                                          */
39383  #define R_IIC0_ICMR2_TMOS_Msk       (0x1UL)  /*!< TMOS (Bitfield-Mask: 0x01)                            */
39384 /* =========================================================  ICMR3  ========================================================= */
39385  #define R_IIC0_ICMR3_SMBS_Pos       (7UL)    /*!< SMBS (Bit 7)                                          */
39386  #define R_IIC0_ICMR3_SMBS_Msk       (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01)                            */
39387  #define R_IIC0_ICMR3_WAIT_Pos       (6UL)    /*!< WAIT (Bit 6)                                          */
39388  #define R_IIC0_ICMR3_WAIT_Msk       (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01)                            */
39389  #define R_IIC0_ICMR3_RDRFS_Pos      (5UL)    /*!< RDRFS (Bit 5)                                         */
39390  #define R_IIC0_ICMR3_RDRFS_Msk      (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01)                           */
39391  #define R_IIC0_ICMR3_ACKWP_Pos      (4UL)    /*!< ACKWP (Bit 4)                                         */
39392  #define R_IIC0_ICMR3_ACKWP_Msk      (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01)                           */
39393  #define R_IIC0_ICMR3_ACKBT_Pos      (3UL)    /*!< ACKBT (Bit 3)                                         */
39394  #define R_IIC0_ICMR3_ACKBT_Msk      (0x8UL)  /*!< ACKBT (Bitfield-Mask: 0x01)                           */
39395  #define R_IIC0_ICMR3_ACKBR_Pos      (2UL)    /*!< ACKBR (Bit 2)                                         */
39396  #define R_IIC0_ICMR3_ACKBR_Msk      (0x4UL)  /*!< ACKBR (Bitfield-Mask: 0x01)                           */
39397  #define R_IIC0_ICMR3_NF_Pos         (0UL)    /*!< NF (Bit 0)                                            */
39398  #define R_IIC0_ICMR3_NF_Msk         (0x3UL)  /*!< NF (Bitfield-Mask: 0x03)                              */
39399 /* =========================================================  ICFER  ========================================================= */
39400  #define R_IIC0_ICFER_FMPE_Pos       (7UL)    /*!< FMPE (Bit 7)                                          */
39401  #define R_IIC0_ICFER_FMPE_Msk       (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01)                            */
39402  #define R_IIC0_ICFER_SCLE_Pos       (6UL)    /*!< SCLE (Bit 6)                                          */
39403  #define R_IIC0_ICFER_SCLE_Msk       (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01)                            */
39404  #define R_IIC0_ICFER_NFE_Pos        (5UL)    /*!< NFE (Bit 5)                                           */
39405  #define R_IIC0_ICFER_NFE_Msk        (0x20UL) /*!< NFE (Bitfield-Mask: 0x01)                             */
39406  #define R_IIC0_ICFER_NACKE_Pos      (4UL)    /*!< NACKE (Bit 4)                                         */
39407  #define R_IIC0_ICFER_NACKE_Msk      (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01)                           */
39408  #define R_IIC0_ICFER_SALE_Pos       (3UL)    /*!< SALE (Bit 3)                                          */
39409  #define R_IIC0_ICFER_SALE_Msk       (0x8UL)  /*!< SALE (Bitfield-Mask: 0x01)                            */
39410  #define R_IIC0_ICFER_NALE_Pos       (2UL)    /*!< NALE (Bit 2)                                          */
39411  #define R_IIC0_ICFER_NALE_Msk       (0x4UL)  /*!< NALE (Bitfield-Mask: 0x01)                            */
39412  #define R_IIC0_ICFER_MALE_Pos       (1UL)    /*!< MALE (Bit 1)                                          */
39413  #define R_IIC0_ICFER_MALE_Msk       (0x2UL)  /*!< MALE (Bitfield-Mask: 0x01)                            */
39414  #define R_IIC0_ICFER_TMOE_Pos       (0UL)    /*!< TMOE (Bit 0)                                          */
39415  #define R_IIC0_ICFER_TMOE_Msk       (0x1UL)  /*!< TMOE (Bitfield-Mask: 0x01)                            */
39416 /* =========================================================  ICSER  ========================================================= */
39417  #define R_IIC0_ICSER_HOAE_Pos       (7UL)    /*!< HOAE (Bit 7)                                          */
39418  #define R_IIC0_ICSER_HOAE_Msk       (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01)                            */
39419  #define R_IIC0_ICSER_DIDE_Pos       (5UL)    /*!< DIDE (Bit 5)                                          */
39420  #define R_IIC0_ICSER_DIDE_Msk       (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01)                            */
39421  #define R_IIC0_ICSER_GCAE_Pos       (3UL)    /*!< GCAE (Bit 3)                                          */
39422  #define R_IIC0_ICSER_GCAE_Msk       (0x8UL)  /*!< GCAE (Bitfield-Mask: 0x01)                            */
39423  #define R_IIC0_ICSER_SAR2E_Pos      (2UL)    /*!< SAR2E (Bit 2)                                         */
39424  #define R_IIC0_ICSER_SAR2E_Msk      (0x4UL)  /*!< SAR2E (Bitfield-Mask: 0x01)                           */
39425  #define R_IIC0_ICSER_SAR1E_Pos      (1UL)    /*!< SAR1E (Bit 1)                                         */
39426  #define R_IIC0_ICSER_SAR1E_Msk      (0x2UL)  /*!< SAR1E (Bitfield-Mask: 0x01)                           */
39427  #define R_IIC0_ICSER_SAR0E_Pos      (0UL)    /*!< SAR0E (Bit 0)                                         */
39428  #define R_IIC0_ICSER_SAR0E_Msk      (0x1UL)  /*!< SAR0E (Bitfield-Mask: 0x01)                           */
39429 /* =========================================================  ICIER  ========================================================= */
39430  #define R_IIC0_ICIER_TIE_Pos        (7UL)    /*!< TIE (Bit 7)                                           */
39431  #define R_IIC0_ICIER_TIE_Msk        (0x80UL) /*!< TIE (Bitfield-Mask: 0x01)                             */
39432  #define R_IIC0_ICIER_TEIE_Pos       (6UL)    /*!< TEIE (Bit 6)                                          */
39433  #define R_IIC0_ICIER_TEIE_Msk       (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01)                            */
39434  #define R_IIC0_ICIER_RIE_Pos        (5UL)    /*!< RIE (Bit 5)                                           */
39435  #define R_IIC0_ICIER_RIE_Msk        (0x20UL) /*!< RIE (Bitfield-Mask: 0x01)                             */
39436  #define R_IIC0_ICIER_NAKIE_Pos      (4UL)    /*!< NAKIE (Bit 4)                                         */
39437  #define R_IIC0_ICIER_NAKIE_Msk      (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01)                           */
39438  #define R_IIC0_ICIER_SPIE_Pos       (3UL)    /*!< SPIE (Bit 3)                                          */
39439  #define R_IIC0_ICIER_SPIE_Msk       (0x8UL)  /*!< SPIE (Bitfield-Mask: 0x01)                            */
39440  #define R_IIC0_ICIER_STIE_Pos       (2UL)    /*!< STIE (Bit 2)                                          */
39441  #define R_IIC0_ICIER_STIE_Msk       (0x4UL)  /*!< STIE (Bitfield-Mask: 0x01)                            */
39442  #define R_IIC0_ICIER_ALIE_Pos       (1UL)    /*!< ALIE (Bit 1)                                          */
39443  #define R_IIC0_ICIER_ALIE_Msk       (0x2UL)  /*!< ALIE (Bitfield-Mask: 0x01)                            */
39444  #define R_IIC0_ICIER_TMOIE_Pos      (0UL)    /*!< TMOIE (Bit 0)                                         */
39445  #define R_IIC0_ICIER_TMOIE_Msk      (0x1UL)  /*!< TMOIE (Bitfield-Mask: 0x01)                           */
39446 /* =========================================================  ICSR1  ========================================================= */
39447  #define R_IIC0_ICSR1_HOA_Pos        (7UL)    /*!< HOA (Bit 7)                                           */
39448  #define R_IIC0_ICSR1_HOA_Msk        (0x80UL) /*!< HOA (Bitfield-Mask: 0x01)                             */
39449  #define R_IIC0_ICSR1_DID_Pos        (5UL)    /*!< DID (Bit 5)                                           */
39450  #define R_IIC0_ICSR1_DID_Msk        (0x20UL) /*!< DID (Bitfield-Mask: 0x01)                             */
39451  #define R_IIC0_ICSR1_GCA_Pos        (3UL)    /*!< GCA (Bit 3)                                           */
39452  #define R_IIC0_ICSR1_GCA_Msk        (0x8UL)  /*!< GCA (Bitfield-Mask: 0x01)                             */
39453  #define R_IIC0_ICSR1_AAS2_Pos       (2UL)    /*!< AAS2 (Bit 2)                                          */
39454  #define R_IIC0_ICSR1_AAS2_Msk       (0x4UL)  /*!< AAS2 (Bitfield-Mask: 0x01)                            */
39455  #define R_IIC0_ICSR1_AAS1_Pos       (1UL)    /*!< AAS1 (Bit 1)                                          */
39456  #define R_IIC0_ICSR1_AAS1_Msk       (0x2UL)  /*!< AAS1 (Bitfield-Mask: 0x01)                            */
39457  #define R_IIC0_ICSR1_AAS0_Pos       (0UL)    /*!< AAS0 (Bit 0)                                          */
39458  #define R_IIC0_ICSR1_AAS0_Msk       (0x1UL)  /*!< AAS0 (Bitfield-Mask: 0x01)                            */
39459 /* =========================================================  ICSR2  ========================================================= */
39460  #define R_IIC0_ICSR2_TDRE_Pos       (7UL)    /*!< TDRE (Bit 7)                                          */
39461  #define R_IIC0_ICSR2_TDRE_Msk       (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01)                            */
39462  #define R_IIC0_ICSR2_TEND_Pos       (6UL)    /*!< TEND (Bit 6)                                          */
39463  #define R_IIC0_ICSR2_TEND_Msk       (0x40UL) /*!< TEND (Bitfield-Mask: 0x01)                            */
39464  #define R_IIC0_ICSR2_RDRF_Pos       (5UL)    /*!< RDRF (Bit 5)                                          */
39465  #define R_IIC0_ICSR2_RDRF_Msk       (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01)                            */
39466  #define R_IIC0_ICSR2_NACKF_Pos      (4UL)    /*!< NACKF (Bit 4)                                         */
39467  #define R_IIC0_ICSR2_NACKF_Msk      (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01)                           */
39468  #define R_IIC0_ICSR2_STOP_Pos       (3UL)    /*!< STOP (Bit 3)                                          */
39469  #define R_IIC0_ICSR2_STOP_Msk       (0x8UL)  /*!< STOP (Bitfield-Mask: 0x01)                            */
39470  #define R_IIC0_ICSR2_START_Pos      (2UL)    /*!< START (Bit 2)                                         */
39471  #define R_IIC0_ICSR2_START_Msk      (0x4UL)  /*!< START (Bitfield-Mask: 0x01)                           */
39472  #define R_IIC0_ICSR2_AL_Pos         (1UL)    /*!< AL (Bit 1)                                            */
39473  #define R_IIC0_ICSR2_AL_Msk         (0x2UL)  /*!< AL (Bitfield-Mask: 0x01)                              */
39474  #define R_IIC0_ICSR2_TMOF_Pos       (0UL)    /*!< TMOF (Bit 0)                                          */
39475  #define R_IIC0_ICSR2_TMOF_Msk       (0x1UL)  /*!< TMOF (Bitfield-Mask: 0x01)                            */
39476 /* =========================================================  ICBRL  ========================================================= */
39477  #define R_IIC0_ICBRL_BRL_Pos        (0UL)    /*!< BRL (Bit 0)                                           */
39478  #define R_IIC0_ICBRL_BRL_Msk        (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f)                             */
39479 /* =========================================================  ICBRH  ========================================================= */
39480  #define R_IIC0_ICBRH_BRH_Pos        (0UL)    /*!< BRH (Bit 0)                                           */
39481  #define R_IIC0_ICBRH_BRH_Msk        (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f)                             */
39482 /* =========================================================  ICDRT  ========================================================= */
39483  #define R_IIC0_ICDRT_ICDRT_Pos      (0UL)    /*!< ICDRT (Bit 0)                                         */
39484  #define R_IIC0_ICDRT_ICDRT_Msk      (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff)                           */
39485 /* =========================================================  ICDRR  ========================================================= */
39486  #define R_IIC0_ICDRR_ICDRR_Pos      (0UL)    /*!< ICDRR (Bit 0)                                         */
39487  #define R_IIC0_ICDRR_ICDRR_Msk      (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff)                           */
39488 /* =========================================================  ICWUR  ========================================================= */
39489  #define R_IIC0_ICWUR_WUE_Pos        (7UL)    /*!< WUE (Bit 7)                                           */
39490  #define R_IIC0_ICWUR_WUE_Msk        (0x80UL) /*!< WUE (Bitfield-Mask: 0x01)                             */
39491  #define R_IIC0_ICWUR_WUIE_Pos       (6UL)    /*!< WUIE (Bit 6)                                          */
39492  #define R_IIC0_ICWUR_WUIE_Msk       (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01)                            */
39493  #define R_IIC0_ICWUR_WUF_Pos        (5UL)    /*!< WUF (Bit 5)                                           */
39494  #define R_IIC0_ICWUR_WUF_Msk        (0x20UL) /*!< WUF (Bitfield-Mask: 0x01)                             */
39495  #define R_IIC0_ICWUR_WUACK_Pos      (4UL)    /*!< WUACK (Bit 4)                                         */
39496  #define R_IIC0_ICWUR_WUACK_Msk      (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01)                           */
39497  #define R_IIC0_ICWUR_WUAFA_Pos      (0UL)    /*!< WUAFA (Bit 0)                                         */
39498  #define R_IIC0_ICWUR_WUAFA_Msk      (0x1UL)  /*!< WUAFA (Bitfield-Mask: 0x01)                           */
39499 /* ========================================================  ICWUR2  ========================================================= */
39500  #define R_IIC0_ICWUR2_WUSYF_Pos     (2UL)    /*!< WUSYF (Bit 2)                                         */
39501  #define R_IIC0_ICWUR2_WUSYF_Msk     (0x4UL)  /*!< WUSYF (Bitfield-Mask: 0x01)                           */
39502  #define R_IIC0_ICWUR2_WUASYF_Pos    (1UL)    /*!< WUASYF (Bit 1)                                        */
39503  #define R_IIC0_ICWUR2_WUASYF_Msk    (0x2UL)  /*!< WUASYF (Bitfield-Mask: 0x01)                          */
39504  #define R_IIC0_ICWUR2_WUSEN_Pos     (0UL)    /*!< WUSEN (Bit 0)                                         */
39505  #define R_IIC0_ICWUR2_WUSEN_Msk     (0x1UL)  /*!< WUSEN (Bitfield-Mask: 0x01)                           */
39506 
39507 /* =========================================================================================================================== */
39508 /* ================                                          R_IIRFA                                          ================ */
39509 /* =========================================================================================================================== */
39510 
39511 /* =======================================================  IIRCPRCS  ======================================================== */
39512  #define R_IIRFA_IIRCPRCS_CPRCS_Pos         (0UL)      /*!< CPRCS (Bit 0)                                         */
39513  #define R_IIRFA_IIRCPRCS_CPRCS_Msk         (0xffffUL) /*!< CPRCS (Bitfield-Mask: 0xffff)                         */
39514 /* =======================================================  IIRCPRCFF  ======================================================= */
39515  #define R_IIRFA_IIRCPRCFF_CPRCFF_Pos       (0UL)      /*!< CPRCFF (Bit 0)                                        */
39516  #define R_IIRFA_IIRCPRCFF_CPRCFF_Msk       (0xffffUL) /*!< CPRCFF (Bitfield-Mask: 0xffff)                        */
39517 /* =======================================================  IIRORDYF  ======================================================== */
39518  #define R_IIRFA_IIRORDYF_ORDYF_Pos         (0UL)      /*!< ORDYF (Bit 0)                                         */
39519  #define R_IIRFA_IIRORDYF_ORDYF_Msk         (0xffffUL) /*!< ORDYF (Bitfield-Mask: 0xffff)                         */
39520 /* =======================================================  IIRCERRF  ======================================================== */
39521  #define R_IIRFA_IIRCERRF_CERRF_Pos         (0UL)      /*!< CERRF (Bit 0)                                         */
39522  #define R_IIRFA_IIRCERRF_CERRF_Msk         (0xffffUL) /*!< CERRF (Bitfield-Mask: 0xffff)                         */
39523 /* =======================================================  IIROPCNT  ======================================================== */
39524  #define R_IIRFA_IIROPCNT_RND_Pos           (0UL)      /*!< RND (Bit 0)                                           */
39525  #define R_IIRFA_IIROPCNT_RND_Msk           (0x7UL)    /*!< RND (Bitfield-Mask: 0x07)                             */
39526 /* =======================================================  IIRECCCNT  ======================================================= */
39527  #define R_IIRFA_IIRECCCNT_ECCMD_Pos        (0UL)      /*!< ECCMD (Bit 0)                                         */
39528  #define R_IIRFA_IIRECCCNT_ECCMD_Msk        (0x1UL)    /*!< ECCMD (Bitfield-Mask: 0x01)                           */
39529  #define R_IIRFA_IIRECCCNT_ECCWBDIS_Pos     (1UL)      /*!< ECCWBDIS (Bit 1)                                      */
39530  #define R_IIRFA_IIRECCCNT_ECCWBDIS_Msk     (0x2UL)    /*!< ECCWBDIS (Bitfield-Mask: 0x01)                        */
39531 /* =======================================================  IIRECCINT  ======================================================= */
39532  #define R_IIRFA_IIRECCINT_ESEIE_Pos        (0UL)      /*!< ESEIE (Bit 0)                                         */
39533  #define R_IIRFA_IIRECCINT_ESEIE_Msk        (0x1UL)    /*!< ESEIE (Bitfield-Mask: 0x01)                           */
39534  #define R_IIRFA_IIRECCINT_EDEIE_Pos        (1UL)      /*!< EDEIE (Bit 1)                                         */
39535  #define R_IIRFA_IIRECCINT_EDEIE_Msk        (0x2UL)    /*!< EDEIE (Bitfield-Mask: 0x01)                           */
39536 /* =======================================================  IIRECCEF  ======================================================== */
39537  #define R_IIRFA_IIRECCEF_ESEF_Pos          (0UL)      /*!< ESEF (Bit 0)                                          */
39538  #define R_IIRFA_IIRECCEF_ESEF_Msk          (0x1UL)    /*!< ESEF (Bitfield-Mask: 0x01)                            */
39539  #define R_IIRFA_IIRECCEF_EDEF_Pos          (1UL)      /*!< EDEF (Bit 1)                                          */
39540  #define R_IIRFA_IIRECCEF_EDEF_Msk          (0x2UL)    /*!< EDEF (Bitfield-Mask: 0x01)                            */
39541 /* ======================================================  IIRECCEFCLR  ====================================================== */
39542  #define R_IIRFA_IIRECCEFCLR_ESEFCLR_Pos    (0UL)      /*!< ESEFCLR (Bit 0)                                       */
39543  #define R_IIRFA_IIRECCEFCLR_ESEFCLR_Msk    (0x1UL)    /*!< ESEFCLR (Bitfield-Mask: 0x01)                         */
39544  #define R_IIRFA_IIRECCEFCLR_EDEFCLR_Pos    (1UL)      /*!< EDEFCLR (Bit 1)                                       */
39545  #define R_IIRFA_IIRECCEFCLR_EDEFCLR_Msk    (0x2UL)    /*!< EDEFCLR (Bitfield-Mask: 0x01)                         */
39546 /* =======================================================  IIRESEADR  ======================================================= */
39547  #define R_IIRFA_IIRESEADR_SEADR_Pos        (0UL)      /*!< SEADR (Bit 0)                                         */
39548  #define R_IIRFA_IIRESEADR_SEADR_Msk        (0x7ffUL)  /*!< SEADR (Bitfield-Mask: 0x7ff)                          */
39549 /* =======================================================  IIREDEADR  ======================================================= */
39550  #define R_IIRFA_IIREDEADR_DEADR_Pos        (0UL)      /*!< DEADR (Bit 0)                                         */
39551  #define R_IIRFA_IIREDEADR_DEADR_Msk        (0x7ffUL)  /*!< DEADR (Bitfield-Mask: 0x7ff)                          */
39552 
39553 /* =========================================================================================================================== */
39554 /* ================                                          R_IRDA                                           ================ */
39555 /* =========================================================================================================================== */
39556 
39557 /* =========================================================  IRCR  ========================================================== */
39558  #define R_IRDA_IRCR_IRE_Pos        (7UL)    /*!< IRE (Bit 7)                                           */
39559  #define R_IRDA_IRCR_IRE_Msk        (0x80UL) /*!< IRE (Bitfield-Mask: 0x01)                             */
39560  #define R_IRDA_IRCR_IRTXINV_Pos    (3UL)    /*!< IRTXINV (Bit 3)                                       */
39561  #define R_IRDA_IRCR_IRTXINV_Msk    (0x8UL)  /*!< IRTXINV (Bitfield-Mask: 0x01)                         */
39562  #define R_IRDA_IRCR_IRRXINV_Pos    (2UL)    /*!< IRRXINV (Bit 2)                                       */
39563  #define R_IRDA_IRCR_IRRXINV_Msk    (0x4UL)  /*!< IRRXINV (Bitfield-Mask: 0x01)                         */
39564 
39565 /* =========================================================================================================================== */
39566 /* ================                                          R_IWDT                                           ================ */
39567 /* =========================================================================================================================== */
39568 
39569 /* ========================================================  IWDTRR  ========================================================= */
39570  #define R_IWDT_IWDTRR_IWDTRR_Pos    (0UL)      /*!< IWDTRR (Bit 0)                                        */
39571  #define R_IWDT_IWDTRR_IWDTRR_Msk    (0xffUL)   /*!< IWDTRR (Bitfield-Mask: 0xff)                          */
39572 /* ========================================================  IWDTSR  ========================================================= */
39573  #define R_IWDT_IWDTSR_REFEF_Pos     (15UL)     /*!< REFEF (Bit 15)                                        */
39574  #define R_IWDT_IWDTSR_REFEF_Msk     (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
39575  #define R_IWDT_IWDTSR_UNDFF_Pos     (14UL)     /*!< UNDFF (Bit 14)                                        */
39576  #define R_IWDT_IWDTSR_UNDFF_Msk     (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
39577  #define R_IWDT_IWDTSR_CNTVAL_Pos    (0UL)      /*!< CNTVAL (Bit 0)                                        */
39578  #define R_IWDT_IWDTSR_CNTVAL_Msk    (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
39579 
39580 /* =========================================================================================================================== */
39581 /* ================                                          R_JPEG                                           ================ */
39582 /* =========================================================================================================================== */
39583 
39584 /* =========================================================  JCMOD  ========================================================= */
39585  #define R_JPEG_JCMOD_DSP_Pos           (3UL)          /*!< DSP (Bit 3)                                           */
39586  #define R_JPEG_JCMOD_DSP_Msk           (0x8UL)        /*!< DSP (Bitfield-Mask: 0x01)                             */
39587  #define R_JPEG_JCMOD_REDU_Pos          (0UL)          /*!< REDU (Bit 0)                                          */
39588  #define R_JPEG_JCMOD_REDU_Msk          (0x7UL)        /*!< REDU (Bitfield-Mask: 0x07)                            */
39589 /* =========================================================  JCCMD  ========================================================= */
39590  #define R_JPEG_JCCMD_BRST_Pos          (7UL)          /*!< BRST (Bit 7)                                          */
39591  #define R_JPEG_JCCMD_BRST_Msk          (0x80UL)       /*!< BRST (Bitfield-Mask: 0x01)                            */
39592  #define R_JPEG_JCCMD_JEND_Pos          (2UL)          /*!< JEND (Bit 2)                                          */
39593  #define R_JPEG_JCCMD_JEND_Msk          (0x4UL)        /*!< JEND (Bitfield-Mask: 0x01)                            */
39594  #define R_JPEG_JCCMD_JRST_Pos          (1UL)          /*!< JRST (Bit 1)                                          */
39595  #define R_JPEG_JCCMD_JRST_Msk          (0x2UL)        /*!< JRST (Bitfield-Mask: 0x01)                            */
39596  #define R_JPEG_JCCMD_JSRT_Pos          (0UL)          /*!< JSRT (Bit 0)                                          */
39597  #define R_JPEG_JCCMD_JSRT_Msk          (0x1UL)        /*!< JSRT (Bitfield-Mask: 0x01)                            */
39598 /* =========================================================  JCQTN  ========================================================= */
39599  #define R_JPEG_JCQTN_QT3_Pos           (4UL)          /*!< QT3 (Bit 4)                                           */
39600  #define R_JPEG_JCQTN_QT3_Msk           (0x30UL)       /*!< QT3 (Bitfield-Mask: 0x03)                             */
39601  #define R_JPEG_JCQTN_QT2_Pos           (2UL)          /*!< QT2 (Bit 2)                                           */
39602  #define R_JPEG_JCQTN_QT2_Msk           (0xcUL)        /*!< QT2 (Bitfield-Mask: 0x03)                             */
39603  #define R_JPEG_JCQTN_QT1_Pos           (0UL)          /*!< QT1 (Bit 0)                                           */
39604  #define R_JPEG_JCQTN_QT1_Msk           (0x3UL)        /*!< QT1 (Bitfield-Mask: 0x03)                             */
39605 /* =========================================================  JCHTN  ========================================================= */
39606  #define R_JPEG_JCHTN_HTA3_Pos          (5UL)          /*!< HTA3 (Bit 5)                                          */
39607  #define R_JPEG_JCHTN_HTA3_Msk          (0x20UL)       /*!< HTA3 (Bitfield-Mask: 0x01)                            */
39608  #define R_JPEG_JCHTN_HTD3_Pos          (4UL)          /*!< HTD3 (Bit 4)                                          */
39609  #define R_JPEG_JCHTN_HTD3_Msk          (0x10UL)       /*!< HTD3 (Bitfield-Mask: 0x01)                            */
39610  #define R_JPEG_JCHTN_HTA2_Pos          (3UL)          /*!< HTA2 (Bit 3)                                          */
39611  #define R_JPEG_JCHTN_HTA2_Msk          (0x8UL)        /*!< HTA2 (Bitfield-Mask: 0x01)                            */
39612  #define R_JPEG_JCHTN_HTD2_Pos          (2UL)          /*!< HTD2 (Bit 2)                                          */
39613  #define R_JPEG_JCHTN_HTD2_Msk          (0x4UL)        /*!< HTD2 (Bitfield-Mask: 0x01)                            */
39614  #define R_JPEG_JCHTN_HTA1_Pos          (1UL)          /*!< HTA1 (Bit 1)                                          */
39615  #define R_JPEG_JCHTN_HTA1_Msk          (0x2UL)        /*!< HTA1 (Bitfield-Mask: 0x01)                            */
39616  #define R_JPEG_JCHTN_HTD1_Pos          (0UL)          /*!< HTD1 (Bit 0)                                          */
39617  #define R_JPEG_JCHTN_HTD1_Msk          (0x1UL)        /*!< HTD1 (Bitfield-Mask: 0x01)                            */
39618 /* ========================================================  JCDRIU  ========================================================= */
39619  #define R_JPEG_JCDRIU_DRIU_Pos         (0UL)          /*!< DRIU (Bit 0)                                          */
39620  #define R_JPEG_JCDRIU_DRIU_Msk         (0xffUL)       /*!< DRIU (Bitfield-Mask: 0xff)                            */
39621 /* ========================================================  JCDRID  ========================================================= */
39622  #define R_JPEG_JCDRID_DRID_Pos         (0UL)          /*!< DRID (Bit 0)                                          */
39623  #define R_JPEG_JCDRID_DRID_Msk         (0xffUL)       /*!< DRID (Bitfield-Mask: 0xff)                            */
39624 /* ========================================================  JCVSZU  ========================================================= */
39625  #define R_JPEG_JCVSZU_VSZU_Pos         (0UL)          /*!< VSZU (Bit 0)                                          */
39626  #define R_JPEG_JCVSZU_VSZU_Msk         (0xffUL)       /*!< VSZU (Bitfield-Mask: 0xff)                            */
39627 /* ========================================================  JCVSZD  ========================================================= */
39628  #define R_JPEG_JCVSZD_VSZD_Pos         (0UL)          /*!< VSZD (Bit 0)                                          */
39629  #define R_JPEG_JCVSZD_VSZD_Msk         (0xffUL)       /*!< VSZD (Bitfield-Mask: 0xff)                            */
39630 /* ========================================================  JCHSZU  ========================================================= */
39631  #define R_JPEG_JCHSZU_HSZU_Pos         (0UL)          /*!< HSZU (Bit 0)                                          */
39632  #define R_JPEG_JCHSZU_HSZU_Msk         (0xffUL)       /*!< HSZU (Bitfield-Mask: 0xff)                            */
39633 /* ========================================================  JCHSZD  ========================================================= */
39634  #define R_JPEG_JCHSZD_HSZD_Pos         (0UL)          /*!< HSZD (Bit 0)                                          */
39635  #define R_JPEG_JCHSZD_HSZD_Msk         (0xffUL)       /*!< HSZD (Bitfield-Mask: 0xff)                            */
39636 /* ========================================================  JCDTCU  ========================================================= */
39637  #define R_JPEG_JCDTCU_DCU_Pos          (0UL)          /*!< DCU (Bit 0)                                           */
39638  #define R_JPEG_JCDTCU_DCU_Msk          (0xffUL)       /*!< DCU (Bitfield-Mask: 0xff)                             */
39639 /* ========================================================  JCDTCM  ========================================================= */
39640  #define R_JPEG_JCDTCM_DCM_Pos          (0UL)          /*!< DCM (Bit 0)                                           */
39641  #define R_JPEG_JCDTCM_DCM_Msk          (0xffUL)       /*!< DCM (Bitfield-Mask: 0xff)                             */
39642 /* ========================================================  JCDTCD  ========================================================= */
39643  #define R_JPEG_JCDTCD_DCD_Pos          (0UL)          /*!< DCD (Bit 0)                                           */
39644  #define R_JPEG_JCDTCD_DCD_Msk          (0xffUL)       /*!< DCD (Bitfield-Mask: 0xff)                             */
39645 /* ========================================================  JINTE0  ========================================================= */
39646  #define R_JPEG_JINTE0_INT7_Pos         (7UL)          /*!< INT7 (Bit 7)                                          */
39647  #define R_JPEG_JINTE0_INT7_Msk         (0x80UL)       /*!< INT7 (Bitfield-Mask: 0x01)                            */
39648  #define R_JPEG_JINTE0_INT6_Pos         (6UL)          /*!< INT6 (Bit 6)                                          */
39649  #define R_JPEG_JINTE0_INT6_Msk         (0x40UL)       /*!< INT6 (Bitfield-Mask: 0x01)                            */
39650  #define R_JPEG_JINTE0_INT5_Pos         (5UL)          /*!< INT5 (Bit 5)                                          */
39651  #define R_JPEG_JINTE0_INT5_Msk         (0x20UL)       /*!< INT5 (Bitfield-Mask: 0x01)                            */
39652  #define R_JPEG_JINTE0_INT3_Pos         (3UL)          /*!< INT3 (Bit 3)                                          */
39653  #define R_JPEG_JINTE0_INT3_Msk         (0x8UL)        /*!< INT3 (Bitfield-Mask: 0x01)                            */
39654 /* ========================================================  JINTS0  ========================================================= */
39655  #define R_JPEG_JINTS0_INS6_Pos         (6UL)          /*!< INS6 (Bit 6)                                          */
39656  #define R_JPEG_JINTS0_INS6_Msk         (0x40UL)       /*!< INS6 (Bitfield-Mask: 0x01)                            */
39657  #define R_JPEG_JINTS0_INS5_Pos         (5UL)          /*!< INS5 (Bit 5)                                          */
39658  #define R_JPEG_JINTS0_INS5_Msk         (0x20UL)       /*!< INS5 (Bitfield-Mask: 0x01)                            */
39659  #define R_JPEG_JINTS0_INS3_Pos         (3UL)          /*!< INS3 (Bit 3)                                          */
39660  #define R_JPEG_JINTS0_INS3_Msk         (0x8UL)        /*!< INS3 (Bitfield-Mask: 0x01)                            */
39661 /* ========================================================  JCDERR  ========================================================= */
39662  #define R_JPEG_JCDERR_ERR_Pos          (0UL)          /*!< ERR (Bit 0)                                           */
39663  #define R_JPEG_JCDERR_ERR_Msk          (0xfUL)        /*!< ERR (Bitfield-Mask: 0x0f)                             */
39664 /* =========================================================  JCRST  ========================================================= */
39665  #define R_JPEG_JCRST_RST_Pos           (0UL)          /*!< RST (Bit 0)                                           */
39666  #define R_JPEG_JCRST_RST_Msk           (0x1UL)        /*!< RST (Bitfield-Mask: 0x01)                             */
39667 /* ========================================================  JIFECNT  ======================================================== */
39668  #define R_JPEG_JIFECNT_JOUTSWAP_Pos    (8UL)          /*!< JOUTSWAP (Bit 8)                                      */
39669  #define R_JPEG_JIFECNT_JOUTSWAP_Msk    (0x700UL)      /*!< JOUTSWAP (Bitfield-Mask: 0x07)                        */
39670  #define R_JPEG_JIFECNT_DINRINI_Pos     (6UL)          /*!< DINRINI (Bit 6)                                       */
39671  #define R_JPEG_JIFECNT_DINRINI_Msk     (0x40UL)       /*!< DINRINI (Bitfield-Mask: 0x01)                         */
39672  #define R_JPEG_JIFECNT_DINRCMD_Pos     (5UL)          /*!< DINRCMD (Bit 5)                                       */
39673  #define R_JPEG_JIFECNT_DINRCMD_Msk     (0x20UL)       /*!< DINRCMD (Bitfield-Mask: 0x01)                         */
39674  #define R_JPEG_JIFECNT_DINLC_Pos       (4UL)          /*!< DINLC (Bit 4)                                         */
39675  #define R_JPEG_JIFECNT_DINLC_Msk       (0x10UL)       /*!< DINLC (Bitfield-Mask: 0x01)                           */
39676  #define R_JPEG_JIFECNT_DINSWAP_Pos     (0UL)          /*!< DINSWAP (Bit 0)                                       */
39677  #define R_JPEG_JIFECNT_DINSWAP_Msk     (0x7UL)        /*!< DINSWAP (Bitfield-Mask: 0x07)                         */
39678 /* ========================================================  JIFESA  ========================================================= */
39679  #define R_JPEG_JIFESA_ESA_Pos          (0UL)          /*!< ESA (Bit 0)                                           */
39680  #define R_JPEG_JIFESA_ESA_Msk          (0xffffffffUL) /*!< ESA (Bitfield-Mask: 0xffffffff)                       */
39681 /* =======================================================  JIFESOFST  ======================================================= */
39682  #define R_JPEG_JIFESOFST_ESMW_Pos      (0UL)          /*!< ESMW (Bit 0)                                          */
39683  #define R_JPEG_JIFESOFST_ESMW_Msk      (0x7fffUL)     /*!< ESMW (Bitfield-Mask: 0x7fff)                          */
39684 /* ========================================================  JIFEDA  ========================================================= */
39685  #define R_JPEG_JIFEDA_EDA_Pos          (0UL)          /*!< EDA (Bit 0)                                           */
39686  #define R_JPEG_JIFEDA_EDA_Msk          (0xffffffffUL) /*!< EDA (Bitfield-Mask: 0xffffffff)                       */
39687 /* ========================================================  JIFESLC  ======================================================== */
39688  #define R_JPEG_JIFESLC_LINES_Pos       (0UL)          /*!< LINES (Bit 0)                                         */
39689  #define R_JPEG_JIFESLC_LINES_Msk       (0xffffUL)     /*!< LINES (Bitfield-Mask: 0xffff)                         */
39690 /* ========================================================  JIFDCNT  ======================================================== */
39691  #define R_JPEG_JIFDCNT_VINTER_Pos      (28UL)         /*!< VINTER (Bit 28)                                       */
39692  #define R_JPEG_JIFDCNT_VINTER_Msk      (0x30000000UL) /*!< VINTER (Bitfield-Mask: 0x03)                          */
39693  #define R_JPEG_JIFDCNT_HINTER_Pos      (26UL)         /*!< HINTER (Bit 26)                                       */
39694  #define R_JPEG_JIFDCNT_HINTER_Msk      (0xc000000UL)  /*!< HINTER (Bitfield-Mask: 0x03)                          */
39695  #define R_JPEG_JIFDCNT_OPF_Pos         (24UL)         /*!< OPF (Bit 24)                                          */
39696  #define R_JPEG_JIFDCNT_OPF_Msk         (0x3000000UL)  /*!< OPF (Bitfield-Mask: 0x03)                             */
39697  #define R_JPEG_JIFDCNT_JINRINI_Pos     (14UL)         /*!< JINRINI (Bit 14)                                      */
39698  #define R_JPEG_JIFDCNT_JINRINI_Msk     (0x4000UL)     /*!< JINRINI (Bitfield-Mask: 0x01)                         */
39699  #define R_JPEG_JIFDCNT_JINRCMD_Pos     (13UL)         /*!< JINRCMD (Bit 13)                                      */
39700  #define R_JPEG_JIFDCNT_JINRCMD_Msk     (0x2000UL)     /*!< JINRCMD (Bitfield-Mask: 0x01)                         */
39701  #define R_JPEG_JIFDCNT_JINC_Pos        (12UL)         /*!< JINC (Bit 12)                                         */
39702  #define R_JPEG_JIFDCNT_JINC_Msk        (0x1000UL)     /*!< JINC (Bitfield-Mask: 0x01)                            */
39703  #define R_JPEG_JIFDCNT_JINSWAP_Pos     (8UL)          /*!< JINSWAP (Bit 8)                                       */
39704  #define R_JPEG_JIFDCNT_JINSWAP_Msk     (0x700UL)      /*!< JINSWAP (Bitfield-Mask: 0x07)                         */
39705  #define R_JPEG_JIFDCNT_DOUTRINI_Pos    (6UL)          /*!< DOUTRINI (Bit 6)                                      */
39706  #define R_JPEG_JIFDCNT_DOUTRINI_Msk    (0x40UL)       /*!< DOUTRINI (Bitfield-Mask: 0x01)                        */
39707  #define R_JPEG_JIFDCNT_DOUTRCMD_Pos    (5UL)          /*!< DOUTRCMD (Bit 5)                                      */
39708  #define R_JPEG_JIFDCNT_DOUTRCMD_Msk    (0x20UL)       /*!< DOUTRCMD (Bitfield-Mask: 0x01)                        */
39709  #define R_JPEG_JIFDCNT_DOUTLC_Pos      (4UL)          /*!< DOUTLC (Bit 4)                                        */
39710  #define R_JPEG_JIFDCNT_DOUTLC_Msk      (0x10UL)       /*!< DOUTLC (Bitfield-Mask: 0x01)                          */
39711  #define R_JPEG_JIFDCNT_DOUTSWAP_Pos    (0UL)          /*!< DOUTSWAP (Bit 0)                                      */
39712  #define R_JPEG_JIFDCNT_DOUTSWAP_Msk    (0x7UL)        /*!< DOUTSWAP (Bitfield-Mask: 0x07)                        */
39713 /* ========================================================  JIFDSA  ========================================================= */
39714  #define R_JPEG_JIFDSA_DSA_Pos          (0UL)          /*!< DSA (Bit 0)                                           */
39715  #define R_JPEG_JIFDSA_DSA_Msk          (0xffffffffUL) /*!< DSA (Bitfield-Mask: 0xffffffff)                       */
39716 /* =======================================================  JIFDDOFST  ======================================================= */
39717  #define R_JPEG_JIFDDOFST_DDMW_Pos      (0UL)          /*!< DDMW (Bit 0)                                          */
39718  #define R_JPEG_JIFDDOFST_DDMW_Msk      (0x7fffUL)     /*!< DDMW (Bitfield-Mask: 0x7fff)                          */
39719 /* ========================================================  JIFDDA  ========================================================= */
39720  #define R_JPEG_JIFDDA_DDA_Pos          (0UL)          /*!< DDA (Bit 0)                                           */
39721  #define R_JPEG_JIFDDA_DDA_Msk          (0xffffffffUL) /*!< DDA (Bitfield-Mask: 0xffffffff)                       */
39722 /* ========================================================  JIFDSDC  ======================================================== */
39723  #define R_JPEG_JIFDSDC_JDATAS_Pos      (0UL)          /*!< JDATAS (Bit 0)                                        */
39724  #define R_JPEG_JIFDSDC_JDATAS_Msk      (0xffffUL)     /*!< JDATAS (Bitfield-Mask: 0xffff)                        */
39725 /* ========================================================  JIFDDLC  ======================================================== */
39726  #define R_JPEG_JIFDDLC_LINES_Pos       (0UL)          /*!< LINES (Bit 0)                                         */
39727  #define R_JPEG_JIFDDLC_LINES_Msk       (0xffffUL)     /*!< LINES (Bitfield-Mask: 0xffff)                         */
39728 /* ========================================================  JIFDADT  ======================================================== */
39729  #define R_JPEG_JIFDADT_ALPHA_Pos       (0UL)          /*!< ALPHA (Bit 0)                                         */
39730  #define R_JPEG_JIFDADT_ALPHA_Msk       (0xffUL)       /*!< ALPHA (Bitfield-Mask: 0xff)                           */
39731 /* ========================================================  JINTE1  ========================================================= */
39732  #define R_JPEG_JINTE1_CBTEN_Pos        (6UL)          /*!< CBTEN (Bit 6)                                         */
39733  #define R_JPEG_JINTE1_CBTEN_Msk        (0x40UL)       /*!< CBTEN (Bitfield-Mask: 0x01)                           */
39734  #define R_JPEG_JINTE1_DINLEN_Pos       (5UL)          /*!< DINLEN (Bit 5)                                        */
39735  #define R_JPEG_JINTE1_DINLEN_Msk       (0x20UL)       /*!< DINLEN (Bitfield-Mask: 0x01)                          */
39736  #define R_JPEG_JINTE1_DBTEN_Pos        (2UL)          /*!< DBTEN (Bit 2)                                         */
39737  #define R_JPEG_JINTE1_DBTEN_Msk        (0x4UL)        /*!< DBTEN (Bitfield-Mask: 0x01)                           */
39738  #define R_JPEG_JINTE1_JINEN_Pos        (1UL)          /*!< JINEN (Bit 1)                                         */
39739  #define R_JPEG_JINTE1_JINEN_Msk        (0x2UL)        /*!< JINEN (Bitfield-Mask: 0x01)                           */
39740  #define R_JPEG_JINTE1_DOUTLEN_Pos      (0UL)          /*!< DOUTLEN (Bit 0)                                       */
39741  #define R_JPEG_JINTE1_DOUTLEN_Msk      (0x1UL)        /*!< DOUTLEN (Bitfield-Mask: 0x01)                         */
39742 /* ========================================================  JINTS1  ========================================================= */
39743  #define R_JPEG_JINTS1_CBTF_Pos         (6UL)          /*!< CBTF (Bit 6)                                          */
39744  #define R_JPEG_JINTS1_CBTF_Msk         (0x40UL)       /*!< CBTF (Bitfield-Mask: 0x01)                            */
39745  #define R_JPEG_JINTS1_DINLF_Pos        (5UL)          /*!< DINLF (Bit 5)                                         */
39746  #define R_JPEG_JINTS1_DINLF_Msk        (0x20UL)       /*!< DINLF (Bitfield-Mask: 0x01)                           */
39747  #define R_JPEG_JINTS1_DBTF_Pos         (2UL)          /*!< DBTF (Bit 2)                                          */
39748  #define R_JPEG_JINTS1_DBTF_Msk         (0x4UL)        /*!< DBTF (Bitfield-Mask: 0x01)                            */
39749  #define R_JPEG_JINTS1_JINF_Pos         (1UL)          /*!< JINF (Bit 1)                                          */
39750  #define R_JPEG_JINTS1_JINF_Msk         (0x2UL)        /*!< JINF (Bitfield-Mask: 0x01)                            */
39751  #define R_JPEG_JINTS1_DOUTLF_Pos       (0UL)          /*!< DOUTLF (Bit 0)                                        */
39752  #define R_JPEG_JINTS1_DOUTLF_Msk       (0x1UL)        /*!< DOUTLF (Bitfield-Mask: 0x01)                          */
39753 /* ========================================================  JCQTBL0  ======================================================== */
39754 /* ========================================================  JCQTBL1  ======================================================== */
39755 /* ========================================================  JCQTBL2  ======================================================== */
39756 /* ========================================================  JCQTBL3  ======================================================== */
39757 /* ========================================================  JCHTBD0  ======================================================== */
39758 /* ========================================================  JCHTBD1  ======================================================== */
39759 /* ========================================================  JCHTBA0  ======================================================== */
39760 /* ========================================================  JCHTBA1  ======================================================== */
39761 
39762 /* =========================================================================================================================== */
39763 /* ================                                          R_KINT                                           ================ */
39764 /* =========================================================================================================================== */
39765 
39766 /* =========================================================  KRCTL  ========================================================= */
39767  #define R_KINT_KRCTL_KRMD_Pos    (7UL)    /*!< KRMD (Bit 7)                                          */
39768  #define R_KINT_KRCTL_KRMD_Msk    (0x80UL) /*!< KRMD (Bitfield-Mask: 0x01)                            */
39769  #define R_KINT_KRCTL_KREG_Pos    (0UL)    /*!< KREG (Bit 0)                                          */
39770  #define R_KINT_KRCTL_KREG_Msk    (0x1UL)  /*!< KREG (Bitfield-Mask: 0x01)                            */
39771 /* ==========================================================  KRF  ========================================================== */
39772  #define R_KINT_KRF_KRF7_Pos      (7UL)    /*!< KRF7 (Bit 7)                                          */
39773  #define R_KINT_KRF_KRF7_Msk      (0x80UL) /*!< KRF7 (Bitfield-Mask: 0x01)                            */
39774  #define R_KINT_KRF_KRF6_Pos      (6UL)    /*!< KRF6 (Bit 6)                                          */
39775  #define R_KINT_KRF_KRF6_Msk      (0x40UL) /*!< KRF6 (Bitfield-Mask: 0x01)                            */
39776  #define R_KINT_KRF_KRF5_Pos      (5UL)    /*!< KRF5 (Bit 5)                                          */
39777  #define R_KINT_KRF_KRF5_Msk      (0x20UL) /*!< KRF5 (Bitfield-Mask: 0x01)                            */
39778  #define R_KINT_KRF_KRF4_Pos      (4UL)    /*!< KRF4 (Bit 4)                                          */
39779  #define R_KINT_KRF_KRF4_Msk      (0x10UL) /*!< KRF4 (Bitfield-Mask: 0x01)                            */
39780  #define R_KINT_KRF_KRF3_Pos      (3UL)    /*!< KRF3 (Bit 3)                                          */
39781  #define R_KINT_KRF_KRF3_Msk      (0x8UL)  /*!< KRF3 (Bitfield-Mask: 0x01)                            */
39782  #define R_KINT_KRF_KRF2_Pos      (2UL)    /*!< KRF2 (Bit 2)                                          */
39783  #define R_KINT_KRF_KRF2_Msk      (0x4UL)  /*!< KRF2 (Bitfield-Mask: 0x01)                            */
39784  #define R_KINT_KRF_KRF1_Pos      (1UL)    /*!< KRF1 (Bit 1)                                          */
39785  #define R_KINT_KRF_KRF1_Msk      (0x2UL)  /*!< KRF1 (Bitfield-Mask: 0x01)                            */
39786  #define R_KINT_KRF_KRF0_Pos      (0UL)    /*!< KRF0 (Bit 0)                                          */
39787  #define R_KINT_KRF_KRF0_Msk      (0x1UL)  /*!< KRF0 (Bitfield-Mask: 0x01)                            */
39788 /* ==========================================================  KRM  ========================================================== */
39789  #define R_KINT_KRM_KRM7_Pos      (7UL)    /*!< KRM7 (Bit 7)                                          */
39790  #define R_KINT_KRM_KRM7_Msk      (0x80UL) /*!< KRM7 (Bitfield-Mask: 0x01)                            */
39791  #define R_KINT_KRM_KRM6_Pos      (6UL)    /*!< KRM6 (Bit 6)                                          */
39792  #define R_KINT_KRM_KRM6_Msk      (0x40UL) /*!< KRM6 (Bitfield-Mask: 0x01)                            */
39793  #define R_KINT_KRM_KRM5_Pos      (5UL)    /*!< KRM5 (Bit 5)                                          */
39794  #define R_KINT_KRM_KRM5_Msk      (0x20UL) /*!< KRM5 (Bitfield-Mask: 0x01)                            */
39795  #define R_KINT_KRM_KRM4_Pos      (4UL)    /*!< KRM4 (Bit 4)                                          */
39796  #define R_KINT_KRM_KRM4_Msk      (0x10UL) /*!< KRM4 (Bitfield-Mask: 0x01)                            */
39797  #define R_KINT_KRM_KRM3_Pos      (3UL)    /*!< KRM3 (Bit 3)                                          */
39798  #define R_KINT_KRM_KRM3_Msk      (0x8UL)  /*!< KRM3 (Bitfield-Mask: 0x01)                            */
39799  #define R_KINT_KRM_KRM2_Pos      (2UL)    /*!< KRM2 (Bit 2)                                          */
39800  #define R_KINT_KRM_KRM2_Msk      (0x4UL)  /*!< KRM2 (Bitfield-Mask: 0x01)                            */
39801  #define R_KINT_KRM_KRM1_Pos      (1UL)    /*!< KRM1 (Bit 1)                                          */
39802  #define R_KINT_KRM_KRM1_Msk      (0x2UL)  /*!< KRM1 (Bitfield-Mask: 0x01)                            */
39803  #define R_KINT_KRM_KRM0_Pos      (0UL)    /*!< KRM0 (Bit 0)                                          */
39804  #define R_KINT_KRM_KRM0_Msk      (0x1UL)  /*!< KRM0 (Bitfield-Mask: 0x01)                            */
39805 
39806 /* =========================================================================================================================== */
39807 /* ================                                          R_I3C0                                           ================ */
39808 /* =========================================================================================================================== */
39809 
39810 /* =========================================================  PRTS  ========================================================== */
39811  #define R_I3C0_PRTS_PRTMD_Pos          (0UL)          /*!< PRTMD (Bit 0)                                         */
39812  #define R_I3C0_PRTS_PRTMD_Msk          (0x1UL)        /*!< PRTMD (Bitfield-Mask: 0x01)                           */
39813 /* =========================================================  CECTL  ========================================================= */
39814  #define R_I3C0_CECTL_CLKE_Pos          (0UL)          /*!< CLKE (Bit 0)                                          */
39815  #define R_I3C0_CECTL_CLKE_Msk          (0x1UL)        /*!< CLKE (Bitfield-Mask: 0x01)                            */
39816 /* =========================================================  BCTL  ========================================================== */
39817  #define R_I3C0_BCTL_INCBA_Pos          (0UL)          /*!< INCBA (Bit 0)                                         */
39818  #define R_I3C0_BCTL_INCBA_Msk          (0x1UL)        /*!< INCBA (Bitfield-Mask: 0x01)                           */
39819  #define R_I3C0_BCTL_BMDS_Pos           (7UL)          /*!< BMDS (Bit 7)                                          */
39820  #define R_I3C0_BCTL_BMDS_Msk           (0x80UL)       /*!< BMDS (Bitfield-Mask: 0x01)                            */
39821  #define R_I3C0_BCTL_HJACKCTL_Pos       (8UL)          /*!< HJACKCTL (Bit 8)                                      */
39822  #define R_I3C0_BCTL_HJACKCTL_Msk       (0x100UL)      /*!< HJACKCTL (Bitfield-Mask: 0x01)                        */
39823  #define R_I3C0_BCTL_ABT_Pos            (29UL)         /*!< ABT (Bit 29)                                          */
39824  #define R_I3C0_BCTL_ABT_Msk            (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01)                             */
39825  #define R_I3C0_BCTL_RSM_Pos            (30UL)         /*!< RSM (Bit 30)                                          */
39826  #define R_I3C0_BCTL_RSM_Msk            (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01)                             */
39827  #define R_I3C0_BCTL_BUSE_Pos           (31UL)         /*!< BUSE (Bit 31)                                         */
39828  #define R_I3C0_BCTL_BUSE_Msk           (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01)                            */
39829 /* ========================================================  MSDVAD  ========================================================= */
39830  #define R_I3C0_MSDVAD_MDYAD_Pos        (16UL)         /*!< MDYAD (Bit 16)                                        */
39831  #define R_I3C0_MSDVAD_MDYAD_Msk        (0x7f0000UL)   /*!< MDYAD (Bitfield-Mask: 0x7f)                           */
39832  #define R_I3C0_MSDVAD_MDYADV_Pos       (31UL)         /*!< MDYADV (Bit 31)                                       */
39833  #define R_I3C0_MSDVAD_MDYADV_Msk       (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01)                          */
39834 /* ========================================================  RSTCTL  ========================================================= */
39835  #define R_I3C0_RSTCTL_RI3CRST_Pos      (0UL)          /*!< RI3CRST (Bit 0)                                       */
39836  #define R_I3C0_RSTCTL_RI3CRST_Msk      (0x1UL)        /*!< RI3CRST (Bitfield-Mask: 0x01)                         */
39837  #define R_I3C0_RSTCTL_CMDQRST_Pos      (1UL)          /*!< CMDQRST (Bit 1)                                       */
39838  #define R_I3C0_RSTCTL_CMDQRST_Msk      (0x2UL)        /*!< CMDQRST (Bitfield-Mask: 0x01)                         */
39839  #define R_I3C0_RSTCTL_RSPQRST_Pos      (2UL)          /*!< RSPQRST (Bit 2)                                       */
39840  #define R_I3C0_RSTCTL_RSPQRST_Msk      (0x4UL)        /*!< RSPQRST (Bitfield-Mask: 0x01)                         */
39841  #define R_I3C0_RSTCTL_TDBRST_Pos       (3UL)          /*!< TDBRST (Bit 3)                                        */
39842  #define R_I3C0_RSTCTL_TDBRST_Msk       (0x8UL)        /*!< TDBRST (Bitfield-Mask: 0x01)                          */
39843  #define R_I3C0_RSTCTL_RDBRST_Pos       (4UL)          /*!< RDBRST (Bit 4)                                        */
39844  #define R_I3C0_RSTCTL_RDBRST_Msk       (0x10UL)       /*!< RDBRST (Bitfield-Mask: 0x01)                          */
39845  #define R_I3C0_RSTCTL_IBIQRST_Pos      (5UL)          /*!< IBIQRST (Bit 5)                                       */
39846  #define R_I3C0_RSTCTL_IBIQRST_Msk      (0x20UL)       /*!< IBIQRST (Bitfield-Mask: 0x01)                         */
39847  #define R_I3C0_RSTCTL_RSQRST_Pos       (6UL)          /*!< RSQRST (Bit 6)                                        */
39848  #define R_I3C0_RSTCTL_RSQRST_Msk       (0x40UL)       /*!< RSQRST (Bitfield-Mask: 0x01)                          */
39849  #define R_I3C0_RSTCTL_INTLRST_Pos      (16UL)         /*!< INTLRST (Bit 16)                                      */
39850  #define R_I3C0_RSTCTL_INTLRST_Msk      (0x10000UL)    /*!< INTLRST (Bitfield-Mask: 0x01)                         */
39851 /* =========================================================  PRSST  ========================================================= */
39852  #define R_I3C0_PRSST_CRMS_Pos          (2UL)          /*!< CRMS (Bit 2)                                          */
39853  #define R_I3C0_PRSST_CRMS_Msk          (0x4UL)        /*!< CRMS (Bitfield-Mask: 0x01)                            */
39854  #define R_I3C0_PRSST_TRMD_Pos          (4UL)          /*!< TRMD (Bit 4)                                          */
39855  #define R_I3C0_PRSST_TRMD_Msk          (0x10UL)       /*!< TRMD (Bitfield-Mask: 0x01)                            */
39856  #define R_I3C0_PRSST_PRSSTWP_Pos       (7UL)          /*!< PRSSTWP (Bit 7)                                       */
39857  #define R_I3C0_PRSST_PRSSTWP_Msk       (0x80UL)       /*!< PRSSTWP (Bitfield-Mask: 0x01)                         */
39858 /* =========================================================  INST  ========================================================== */
39859  #define R_I3C0_INST_INEF_Pos           (10UL)         /*!< INEF (Bit 10)                                         */
39860  #define R_I3C0_INST_INEF_Msk           (0x400UL)      /*!< INEF (Bitfield-Mask: 0x01)                            */
39861 /* =========================================================  INSTE  ========================================================= */
39862  #define R_I3C0_INSTE_INEE_Pos          (10UL)         /*!< INEE (Bit 10)                                         */
39863  #define R_I3C0_INSTE_INEE_Msk          (0x400UL)      /*!< INEE (Bitfield-Mask: 0x01)                            */
39864 /* =========================================================  INIE  ========================================================== */
39865  #define R_I3C0_INIE_INEIE_Pos          (10UL)         /*!< INEIE (Bit 10)                                        */
39866  #define R_I3C0_INIE_INEIE_Msk          (0x400UL)      /*!< INEIE (Bitfield-Mask: 0x01)                           */
39867 /* ========================================================  INSTFC  ========================================================= */
39868  #define R_I3C0_INSTFC_INEFC_Pos        (10UL)         /*!< INEFC (Bit 10)                                        */
39869  #define R_I3C0_INSTFC_INEFC_Msk        (0x400UL)      /*!< INEFC (Bitfield-Mask: 0x01)                           */
39870 /* =========================================================  DVCT  ========================================================== */
39871  #define R_I3C0_DVCT_IDX_Pos            (19UL)         /*!< IDX (Bit 19)                                          */
39872  #define R_I3C0_DVCT_IDX_Msk            (0xf80000UL)   /*!< IDX (Bitfield-Mask: 0x1f)                             */
39873 /* ========================================================  IBINCTL  ======================================================== */
39874  #define R_I3C0_IBINCTL_NRHJCTL_Pos     (0UL)          /*!< NRHJCTL (Bit 0)                                       */
39875  #define R_I3C0_IBINCTL_NRHJCTL_Msk     (0x1UL)        /*!< NRHJCTL (Bitfield-Mask: 0x01)                         */
39876  #define R_I3C0_IBINCTL_NRMRCTL_Pos     (1UL)          /*!< NRMRCTL (Bit 1)                                       */
39877  #define R_I3C0_IBINCTL_NRMRCTL_Msk     (0x2UL)        /*!< NRMRCTL (Bitfield-Mask: 0x01)                         */
39878  #define R_I3C0_IBINCTL_NRSIRCTL_Pos    (3UL)          /*!< NRSIRCTL (Bit 3)                                      */
39879  #define R_I3C0_IBINCTL_NRSIRCTL_Msk    (0x8UL)        /*!< NRSIRCTL (Bitfield-Mask: 0x01)                        */
39880 /* =========================================================  BFCTL  ========================================================= */
39881  #define R_I3C0_BFCTL_MALE_Pos          (0UL)          /*!< MALE (Bit 0)                                          */
39882  #define R_I3C0_BFCTL_MALE_Msk          (0x1UL)        /*!< MALE (Bitfield-Mask: 0x01)                            */
39883  #define R_I3C0_BFCTL_NALE_Pos          (1UL)          /*!< NALE (Bit 1)                                          */
39884  #define R_I3C0_BFCTL_NALE_Msk          (0x2UL)        /*!< NALE (Bitfield-Mask: 0x01)                            */
39885  #define R_I3C0_BFCTL_SALE_Pos          (2UL)          /*!< SALE (Bit 2)                                          */
39886  #define R_I3C0_BFCTL_SALE_Msk          (0x4UL)        /*!< SALE (Bitfield-Mask: 0x01)                            */
39887  #define R_I3C0_BFCTL_SCSYNE_Pos        (8UL)          /*!< SCSYNE (Bit 8)                                        */
39888  #define R_I3C0_BFCTL_SCSYNE_Msk        (0x100UL)      /*!< SCSYNE (Bitfield-Mask: 0x01)                          */
39889  #define R_I3C0_BFCTL_SMBS_Pos          (12UL)         /*!< SMBS (Bit 12)                                         */
39890  #define R_I3C0_BFCTL_SMBS_Msk          (0x1000UL)     /*!< SMBS (Bitfield-Mask: 0x01)                            */
39891  #define R_I3C0_BFCTL_FMPE_Pos          (14UL)         /*!< FMPE (Bit 14)                                         */
39892  #define R_I3C0_BFCTL_FMPE_Msk          (0x4000UL)     /*!< FMPE (Bitfield-Mask: 0x01)                            */
39893  #define R_I3C0_BFCTL_HSME_Pos          (15UL)         /*!< HSME (Bit 15)                                         */
39894  #define R_I3C0_BFCTL_HSME_Msk          (0x8000UL)     /*!< HSME (Bitfield-Mask: 0x01)                            */
39895 /* =========================================================  SVCTL  ========================================================= */
39896  #define R_I3C0_SVCTL_GCAE_Pos          (0UL)          /*!< GCAE (Bit 0)                                          */
39897  #define R_I3C0_SVCTL_GCAE_Msk          (0x1UL)        /*!< GCAE (Bitfield-Mask: 0x01)                            */
39898  #define R_I3C0_SVCTL_HSMCE_Pos         (5UL)          /*!< HSMCE (Bit 5)                                         */
39899  #define R_I3C0_SVCTL_HSMCE_Msk         (0x20UL)       /*!< HSMCE (Bitfield-Mask: 0x01)                           */
39900  #define R_I3C0_SVCTL_DVIDE_Pos         (6UL)          /*!< DVIDE (Bit 6)                                         */
39901  #define R_I3C0_SVCTL_DVIDE_Msk         (0x40UL)       /*!< DVIDE (Bitfield-Mask: 0x01)                           */
39902  #define R_I3C0_SVCTL_HOAE_Pos          (15UL)         /*!< HOAE (Bit 15)                                         */
39903  #define R_I3C0_SVCTL_HOAE_Msk          (0x8000UL)     /*!< HOAE (Bitfield-Mask: 0x01)                            */
39904  #define R_I3C0_SVCTL_SVAEn_Pos         (16UL)         /*!< SVAEn (Bit 16)                                        */
39905  #define R_I3C0_SVCTL_SVAEn_Msk         (0x10000UL)    /*!< SVAEn (Bitfield-Mask: 0x01)                           */
39906 /* =======================================================  REFCKCTL  ======================================================== */
39907  #define R_I3C0_REFCKCTL_IREFCKS_Pos    (0UL)          /*!< IREFCKS (Bit 0)                                       */
39908  #define R_I3C0_REFCKCTL_IREFCKS_Msk    (0x7UL)        /*!< IREFCKS (Bitfield-Mask: 0x07)                         */
39909 /* =========================================================  STDBR  ========================================================= */
39910  #define R_I3C0_STDBR_SBRLO_Pos         (0UL)          /*!< SBRLO (Bit 0)                                         */
39911  #define R_I3C0_STDBR_SBRLO_Msk         (0xffUL)       /*!< SBRLO (Bitfield-Mask: 0xff)                           */
39912  #define R_I3C0_STDBR_SBRHO_Pos         (8UL)          /*!< SBRHO (Bit 8)                                         */
39913  #define R_I3C0_STDBR_SBRHO_Msk         (0xff00UL)     /*!< SBRHO (Bitfield-Mask: 0xff)                           */
39914  #define R_I3C0_STDBR_SBRLP_Pos         (16UL)         /*!< SBRLP (Bit 16)                                        */
39915  #define R_I3C0_STDBR_SBRLP_Msk         (0x3f0000UL)   /*!< SBRLP (Bitfield-Mask: 0x3f)                           */
39916  #define R_I3C0_STDBR_SBRHP_Pos         (24UL)         /*!< SBRHP (Bit 24)                                        */
39917  #define R_I3C0_STDBR_SBRHP_Msk         (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f)                           */
39918  #define R_I3C0_STDBR_DSBRPO_Pos        (31UL)         /*!< DSBRPO (Bit 31)                                       */
39919  #define R_I3C0_STDBR_DSBRPO_Msk        (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01)                          */
39920 /* =========================================================  EXTBR  ========================================================= */
39921  #define R_I3C0_EXTBR_EBRLO_Pos         (0UL)          /*!< EBRLO (Bit 0)                                         */
39922  #define R_I3C0_EXTBR_EBRLO_Msk         (0xffUL)       /*!< EBRLO (Bitfield-Mask: 0xff)                           */
39923  #define R_I3C0_EXTBR_EBRHO_Pos         (8UL)          /*!< EBRHO (Bit 8)                                         */
39924  #define R_I3C0_EXTBR_EBRHO_Msk         (0xff00UL)     /*!< EBRHO (Bitfield-Mask: 0xff)                           */
39925  #define R_I3C0_EXTBR_EBRLP_Pos         (16UL)         /*!< EBRLP (Bit 16)                                        */
39926  #define R_I3C0_EXTBR_EBRLP_Msk         (0x3f0000UL)   /*!< EBRLP (Bitfield-Mask: 0x3f)                           */
39927  #define R_I3C0_EXTBR_EBRHP_Pos         (24UL)         /*!< EBRHP (Bit 24)                                        */
39928  #define R_I3C0_EXTBR_EBRHP_Msk         (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f)                           */
39929 /* ========================================================  BFRECDT  ======================================================== */
39930  #define R_I3C0_BFRECDT_FRECYC_Pos      (0UL)          /*!< FRECYC (Bit 0)                                        */
39931  #define R_I3C0_BFRECDT_FRECYC_Msk      (0x1ffUL)      /*!< FRECYC (Bitfield-Mask: 0x1ff)                         */
39932 /* ========================================================  BAVLCDT  ======================================================== */
39933  #define R_I3C0_BAVLCDT_AVLCYC_Pos      (0UL)          /*!< AVLCYC (Bit 0)                                        */
39934  #define R_I3C0_BAVLCDT_AVLCYC_Msk      (0x1ffUL)      /*!< AVLCYC (Bitfield-Mask: 0x1ff)                         */
39935 /* ========================================================  BIDLCDT  ======================================================== */
39936  #define R_I3C0_BIDLCDT_IDLCYC_Pos      (0UL)          /*!< IDLCYC (Bit 0)                                        */
39937  #define R_I3C0_BIDLCDT_IDLCYC_Msk      (0x3ffffUL)    /*!< IDLCYC (Bitfield-Mask: 0x3ffff)                       */
39938 /* ========================================================  OUTCTL  ========================================================= */
39939  #define R_I3C0_OUTCTL_SDOC_Pos         (0UL)          /*!< SDOC (Bit 0)                                          */
39940  #define R_I3C0_OUTCTL_SDOC_Msk         (0x1UL)        /*!< SDOC (Bitfield-Mask: 0x01)                            */
39941  #define R_I3C0_OUTCTL_SCOC_Pos         (1UL)          /*!< SCOC (Bit 1)                                          */
39942  #define R_I3C0_OUTCTL_SCOC_Msk         (0x2UL)        /*!< SCOC (Bitfield-Mask: 0x01)                            */
39943  #define R_I3C0_OUTCTL_SOCWP_Pos        (2UL)          /*!< SOCWP (Bit 2)                                         */
39944  #define R_I3C0_OUTCTL_SOCWP_Msk        (0x4UL)        /*!< SOCWP (Bitfield-Mask: 0x01)                           */
39945  #define R_I3C0_OUTCTL_EXCYC_Pos        (4UL)          /*!< EXCYC (Bit 4)                                         */
39946  #define R_I3C0_OUTCTL_EXCYC_Msk        (0x10UL)       /*!< EXCYC (Bitfield-Mask: 0x01)                           */
39947  #define R_I3C0_OUTCTL_SDOD_Pos         (8UL)          /*!< SDOD (Bit 8)                                          */
39948  #define R_I3C0_OUTCTL_SDOD_Msk         (0x700UL)      /*!< SDOD (Bitfield-Mask: 0x07)                            */
39949  #define R_I3C0_OUTCTL_SDODCS_Pos       (15UL)         /*!< SDODCS (Bit 15)                                       */
39950  #define R_I3C0_OUTCTL_SDODCS_Msk       (0x8000UL)     /*!< SDODCS (Bitfield-Mask: 0x01)                          */
39951 /* =========================================================  INCTL  ========================================================= */
39952  #define R_I3C0_INCTL_DNFS_Pos          (0UL)          /*!< DNFS (Bit 0)                                          */
39953  #define R_I3C0_INCTL_DNFS_Msk          (0xfUL)        /*!< DNFS (Bitfield-Mask: 0x0f)                            */
39954  #define R_I3C0_INCTL_DNFE_Pos          (4UL)          /*!< DNFE (Bit 4)                                          */
39955  #define R_I3C0_INCTL_DNFE_Msk          (0x10UL)       /*!< DNFE (Bitfield-Mask: 0x01)                            */
39956 /* ========================================================  TMOCTL  ========================================================= */
39957  #define R_I3C0_TMOCTL_TODTS_Pos        (0UL)          /*!< TODTS (Bit 0)                                         */
39958  #define R_I3C0_TMOCTL_TODTS_Msk        (0x3UL)        /*!< TODTS (Bitfield-Mask: 0x03)                           */
39959  #define R_I3C0_TMOCTL_TOLCTL_Pos       (4UL)          /*!< TOLCTL (Bit 4)                                        */
39960  #define R_I3C0_TMOCTL_TOLCTL_Msk       (0x10UL)       /*!< TOLCTL (Bitfield-Mask: 0x01)                          */
39961  #define R_I3C0_TMOCTL_TOHCTL_Pos       (5UL)          /*!< TOHCTL (Bit 5)                                        */
39962  #define R_I3C0_TMOCTL_TOHCTL_Msk       (0x20UL)       /*!< TOHCTL (Bitfield-Mask: 0x01)                          */
39963  #define R_I3C0_TMOCTL_TOMDS_Pos        (6UL)          /*!< TOMDS (Bit 6)                                         */
39964  #define R_I3C0_TMOCTL_TOMDS_Msk        (0xc0UL)       /*!< TOMDS (Bitfield-Mask: 0x03)                           */
39965 /* =========================================================  WUCTL  ========================================================= */
39966  #define R_I3C0_WUCTL_WUACKS_Pos        (0UL)          /*!< WUACKS (Bit 0)                                        */
39967  #define R_I3C0_WUCTL_WUACKS_Msk        (0x1UL)        /*!< WUACKS (Bitfield-Mask: 0x01)                          */
39968  #define R_I3C0_WUCTL_WUANFS_Pos        (4UL)          /*!< WUANFS (Bit 4)                                        */
39969  #define R_I3C0_WUCTL_WUANFS_Msk        (0x10UL)       /*!< WUANFS (Bitfield-Mask: 0x01)                          */
39970  #define R_I3C0_WUCTL_WUFSYNE_Pos       (6UL)          /*!< WUFSYNE (Bit 6)                                       */
39971  #define R_I3C0_WUCTL_WUFSYNE_Msk       (0x40UL)       /*!< WUFSYNE (Bitfield-Mask: 0x01)                         */
39972  #define R_I3C0_WUCTL_WUFE_Pos          (7UL)          /*!< WUFE (Bit 7)                                          */
39973  #define R_I3C0_WUCTL_WUFE_Msk          (0x80UL)       /*!< WUFE (Bitfield-Mask: 0x01)                            */
39974 /* ========================================================  ACKCTL  ========================================================= */
39975  #define R_I3C0_ACKCTL_ACKR_Pos         (0UL)          /*!< ACKR (Bit 0)                                          */
39976  #define R_I3C0_ACKCTL_ACKR_Msk         (0x1UL)        /*!< ACKR (Bitfield-Mask: 0x01)                            */
39977  #define R_I3C0_ACKCTL_ACKT_Pos         (1UL)          /*!< ACKT (Bit 1)                                          */
39978  #define R_I3C0_ACKCTL_ACKT_Msk         (0x2UL)        /*!< ACKT (Bitfield-Mask: 0x01)                            */
39979  #define R_I3C0_ACKCTL_ACKTWP_Pos       (2UL)          /*!< ACKTWP (Bit 2)                                        */
39980  #define R_I3C0_ACKCTL_ACKTWP_Msk       (0x4UL)        /*!< ACKTWP (Bitfield-Mask: 0x01)                          */
39981 /* =======================================================  SCSTRCTL  ======================================================== */
39982  #define R_I3C0_SCSTRCTL_ACKTWE_Pos     (0UL)          /*!< ACKTWE (Bit 0)                                        */
39983  #define R_I3C0_SCSTRCTL_ACKTWE_Msk     (0x1UL)        /*!< ACKTWE (Bitfield-Mask: 0x01)                          */
39984  #define R_I3C0_SCSTRCTL_RWE_Pos        (1UL)          /*!< RWE (Bit 1)                                           */
39985  #define R_I3C0_SCSTRCTL_RWE_Msk        (0x2UL)        /*!< RWE (Bitfield-Mask: 0x01)                             */
39986 /* =======================================================  SCSTLCTL  ======================================================== */
39987  #define R_I3C0_SCSTLCTL_STLCYC_Pos     (0UL)          /*!< STLCYC (Bit 0)                                        */
39988  #define R_I3C0_SCSTLCTL_STLCYC_Msk     (0xffffUL)     /*!< STLCYC (Bitfield-Mask: 0xffff)                        */
39989  #define R_I3C0_SCSTLCTL_AAPE_Pos       (28UL)         /*!< AAPE (Bit 28)                                         */
39990  #define R_I3C0_SCSTLCTL_AAPE_Msk       (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01)                            */
39991  #define R_I3C0_SCSTLCTL_TRAPE_Pos      (29UL)         /*!< TRAPE (Bit 29)                                        */
39992  #define R_I3C0_SCSTLCTL_TRAPE_Msk      (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01)                           */
39993  #define R_I3C0_SCSTLCTL_PARPE_Pos      (30UL)         /*!< PARPE (Bit 30)                                        */
39994  #define R_I3C0_SCSTLCTL_PARPE_Msk      (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01)                           */
39995  #define R_I3C0_SCSTLCTL_ACKPE_Pos      (31UL)         /*!< ACKPE (Bit 31)                                        */
39996  #define R_I3C0_SCSTLCTL_ACKPE_Msk      (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01)                           */
39997 /* ========================================================  SVTDLG0  ======================================================== */
39998  #define R_I3C0_SVTDLG0_STDLG_Pos       (16UL)         /*!< STDLG (Bit 16)                                        */
39999  #define R_I3C0_SVTDLG0_STDLG_Msk       (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff)                         */
40000 /* ========================================================  CNDCTL  ========================================================= */
40001  #define R_I3C0_CNDCTL_STCND_Pos        (0UL)          /*!< STCND (Bit 0)                                         */
40002  #define R_I3C0_CNDCTL_STCND_Msk        (0x1UL)        /*!< STCND (Bitfield-Mask: 0x01)                           */
40003  #define R_I3C0_CNDCTL_SRCND_Pos        (1UL)          /*!< SRCND (Bit 1)                                         */
40004  #define R_I3C0_CNDCTL_SRCND_Msk        (0x2UL)        /*!< SRCND (Bitfield-Mask: 0x01)                           */
40005  #define R_I3C0_CNDCTL_SPCND_Pos        (2UL)          /*!< SPCND (Bit 2)                                         */
40006  #define R_I3C0_CNDCTL_SPCND_Msk        (0x4UL)        /*!< SPCND (Bitfield-Mask: 0x01)                           */
40007 /* ========================================================  NCMDQP  ========================================================= */
40008 /* ========================================================  NRSPQP  ========================================================= */
40009 /* ========================================================  NTDTBP0  ======================================================== */
40010 /* ========================================================  NIBIQP  ========================================================= */
40011 /* =========================================================  NRSQP  ========================================================= */
40012 /* ========================================================  NQTHCTL  ======================================================== */
40013  #define R_I3C0_NQTHCTL_CMDQTH_Pos      (0UL)          /*!< CMDQTH (Bit 0)                                        */
40014  #define R_I3C0_NQTHCTL_CMDQTH_Msk      (0xffUL)       /*!< CMDQTH (Bitfield-Mask: 0xff)                          */
40015  #define R_I3C0_NQTHCTL_RSPQTH_Pos      (8UL)          /*!< RSPQTH (Bit 8)                                        */
40016  #define R_I3C0_NQTHCTL_RSPQTH_Msk      (0xff00UL)     /*!< RSPQTH (Bitfield-Mask: 0xff)                          */
40017  #define R_I3C0_NQTHCTL_IBIDSSZ_Pos     (16UL)         /*!< IBIDSSZ (Bit 16)                                      */
40018  #define R_I3C0_NQTHCTL_IBIDSSZ_Msk     (0xff0000UL)   /*!< IBIDSSZ (Bitfield-Mask: 0xff)                         */
40019  #define R_I3C0_NQTHCTL_IBIQTH_Pos      (24UL)         /*!< IBIQTH (Bit 24)                                       */
40020  #define R_I3C0_NQTHCTL_IBIQTH_Msk      (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff)                          */
40021 /* =======================================================  NTBTHCTL0  ======================================================= */
40022  #define R_I3C0_NTBTHCTL0_TXDBTH_Pos    (0UL)          /*!< TXDBTH (Bit 0)                                        */
40023  #define R_I3C0_NTBTHCTL0_TXDBTH_Msk    (0x7UL)        /*!< TXDBTH (Bitfield-Mask: 0x07)                          */
40024  #define R_I3C0_NTBTHCTL0_RXDBTH_Pos    (8UL)          /*!< RXDBTH (Bit 8)                                        */
40025  #define R_I3C0_NTBTHCTL0_RXDBTH_Msk    (0x700UL)      /*!< RXDBTH (Bitfield-Mask: 0x07)                          */
40026  #define R_I3C0_NTBTHCTL0_TXSTTH_Pos    (16UL)         /*!< TXSTTH (Bit 16)                                       */
40027  #define R_I3C0_NTBTHCTL0_TXSTTH_Msk    (0x70000UL)    /*!< TXSTTH (Bitfield-Mask: 0x07)                          */
40028  #define R_I3C0_NTBTHCTL0_RXSTTH_Pos    (24UL)         /*!< RXSTTH (Bit 24)                                       */
40029  #define R_I3C0_NTBTHCTL0_RXSTTH_Msk    (0x7000000UL)  /*!< RXSTTH (Bitfield-Mask: 0x07)                          */
40030 /* =======================================================  NRQTHCTL  ======================================================== */
40031  #define R_I3C0_NRQTHCTL_RSQTH_Pos      (0UL)          /*!< RSQTH (Bit 0)                                         */
40032  #define R_I3C0_NRQTHCTL_RSQTH_Msk      (0xffUL)       /*!< RSQTH (Bitfield-Mask: 0xff)                           */
40033 /* ==========================================================  BST  ========================================================== */
40034  #define R_I3C0_BST_STCNDDF_Pos         (0UL)          /*!< STCNDDF (Bit 0)                                       */
40035  #define R_I3C0_BST_STCNDDF_Msk         (0x1UL)        /*!< STCNDDF (Bitfield-Mask: 0x01)                         */
40036  #define R_I3C0_BST_SPCNDDF_Pos         (1UL)          /*!< SPCNDDF (Bit 1)                                       */
40037  #define R_I3C0_BST_SPCNDDF_Msk         (0x2UL)        /*!< SPCNDDF (Bitfield-Mask: 0x01)                         */
40038  #define R_I3C0_BST_HDREXDF_Pos         (2UL)          /*!< HDREXDF (Bit 2)                                       */
40039  #define R_I3C0_BST_HDREXDF_Msk         (0x4UL)        /*!< HDREXDF (Bitfield-Mask: 0x01)                         */
40040  #define R_I3C0_BST_NACKDF_Pos          (4UL)          /*!< NACKDF (Bit 4)                                        */
40041  #define R_I3C0_BST_NACKDF_Msk          (0x10UL)       /*!< NACKDF (Bitfield-Mask: 0x01)                          */
40042  #define R_I3C0_BST_TENDF_Pos           (8UL)          /*!< TENDF (Bit 8)                                         */
40043  #define R_I3C0_BST_TENDF_Msk           (0x100UL)      /*!< TENDF (Bitfield-Mask: 0x01)                           */
40044  #define R_I3C0_BST_ALF_Pos             (16UL)         /*!< ALF (Bit 16)                                          */
40045  #define R_I3C0_BST_ALF_Msk             (0x10000UL)    /*!< ALF (Bitfield-Mask: 0x01)                             */
40046  #define R_I3C0_BST_TODF_Pos            (20UL)         /*!< TODF (Bit 20)                                         */
40047  #define R_I3C0_BST_TODF_Msk            (0x100000UL)   /*!< TODF (Bitfield-Mask: 0x01)                            */
40048 /* =========================================================  BSTE  ========================================================== */
40049  #define R_I3C0_BSTE_STCNDDE_Pos        (0UL)          /*!< STCNDDE (Bit 0)                                       */
40050  #define R_I3C0_BSTE_STCNDDE_Msk        (0x1UL)        /*!< STCNDDE (Bitfield-Mask: 0x01)                         */
40051  #define R_I3C0_BSTE_SPCNDDE_Pos        (1UL)          /*!< SPCNDDE (Bit 1)                                       */
40052  #define R_I3C0_BSTE_SPCNDDE_Msk        (0x2UL)        /*!< SPCNDDE (Bitfield-Mask: 0x01)                         */
40053  #define R_I3C0_BSTE_HDREXDE_Pos        (2UL)          /*!< HDREXDE (Bit 2)                                       */
40054  #define R_I3C0_BSTE_HDREXDE_Msk        (0x4UL)        /*!< HDREXDE (Bitfield-Mask: 0x01)                         */
40055  #define R_I3C0_BSTE_NACKDE_Pos         (4UL)          /*!< NACKDE (Bit 4)                                        */
40056  #define R_I3C0_BSTE_NACKDE_Msk         (0x10UL)       /*!< NACKDE (Bitfield-Mask: 0x01)                          */
40057  #define R_I3C0_BSTE_TENDE_Pos          (8UL)          /*!< TENDE (Bit 8)                                         */
40058  #define R_I3C0_BSTE_TENDE_Msk          (0x100UL)      /*!< TENDE (Bitfield-Mask: 0x01)                           */
40059  #define R_I3C0_BSTE_ALE_Pos            (16UL)         /*!< ALE (Bit 16)                                          */
40060  #define R_I3C0_BSTE_ALE_Msk            (0x10000UL)    /*!< ALE (Bitfield-Mask: 0x01)                             */
40061  #define R_I3C0_BSTE_TODE_Pos           (20UL)         /*!< TODE (Bit 20)                                         */
40062  #define R_I3C0_BSTE_TODE_Msk           (0x100000UL)   /*!< TODE (Bitfield-Mask: 0x01)                            */
40063 /* ==========================================================  BIE  ========================================================== */
40064  #define R_I3C0_BIE_STCNDDIE_Pos        (0UL)          /*!< STCNDDIE (Bit 0)                                      */
40065  #define R_I3C0_BIE_STCNDDIE_Msk        (0x1UL)        /*!< STCNDDIE (Bitfield-Mask: 0x01)                        */
40066  #define R_I3C0_BIE_SPCNDDIE_Pos        (1UL)          /*!< SPCNDDIE (Bit 1)                                      */
40067  #define R_I3C0_BIE_SPCNDDIE_Msk        (0x2UL)        /*!< SPCNDDIE (Bitfield-Mask: 0x01)                        */
40068  #define R_I3C0_BIE_HDREXDIE_Pos        (2UL)          /*!< HDREXDIE (Bit 2)                                      */
40069  #define R_I3C0_BIE_HDREXDIE_Msk        (0x4UL)        /*!< HDREXDIE (Bitfield-Mask: 0x01)                        */
40070  #define R_I3C0_BIE_NACKDIE_Pos         (4UL)          /*!< NACKDIE (Bit 4)                                       */
40071  #define R_I3C0_BIE_NACKDIE_Msk         (0x10UL)       /*!< NACKDIE (Bitfield-Mask: 0x01)                         */
40072  #define R_I3C0_BIE_TENDIE_Pos          (8UL)          /*!< TENDIE (Bit 8)                                        */
40073  #define R_I3C0_BIE_TENDIE_Msk          (0x100UL)      /*!< TENDIE (Bitfield-Mask: 0x01)                          */
40074  #define R_I3C0_BIE_ALIE_Pos            (16UL)         /*!< ALIE (Bit 16)                                         */
40075  #define R_I3C0_BIE_ALIE_Msk            (0x10000UL)    /*!< ALIE (Bitfield-Mask: 0x01)                            */
40076  #define R_I3C0_BIE_TODIE_Pos           (20UL)         /*!< TODIE (Bit 20)                                        */
40077  #define R_I3C0_BIE_TODIE_Msk           (0x100000UL)   /*!< TODIE (Bitfield-Mask: 0x01)                           */
40078 /* =========================================================  BSTFC  ========================================================= */
40079  #define R_I3C0_BSTFC_STCNDDFC_Pos      (0UL)          /*!< STCNDDFC (Bit 0)                                      */
40080  #define R_I3C0_BSTFC_STCNDDFC_Msk      (0x1UL)        /*!< STCNDDFC (Bitfield-Mask: 0x01)                        */
40081  #define R_I3C0_BSTFC_SPCNDDFC_Pos      (1UL)          /*!< SPCNDDFC (Bit 1)                                      */
40082  #define R_I3C0_BSTFC_SPCNDDFC_Msk      (0x2UL)        /*!< SPCNDDFC (Bitfield-Mask: 0x01)                        */
40083  #define R_I3C0_BSTFC_HDREXDFC_Pos      (2UL)          /*!< HDREXDFC (Bit 2)                                      */
40084  #define R_I3C0_BSTFC_HDREXDFC_Msk      (0x4UL)        /*!< HDREXDFC (Bitfield-Mask: 0x01)                        */
40085  #define R_I3C0_BSTFC_NACKDFC_Pos       (4UL)          /*!< NACKDFC (Bit 4)                                       */
40086  #define R_I3C0_BSTFC_NACKDFC_Msk       (0x10UL)       /*!< NACKDFC (Bitfield-Mask: 0x01)                         */
40087  #define R_I3C0_BSTFC_TENDFC_Pos        (8UL)          /*!< TENDFC (Bit 8)                                        */
40088  #define R_I3C0_BSTFC_TENDFC_Msk        (0x100UL)      /*!< TENDFC (Bitfield-Mask: 0x01)                          */
40089  #define R_I3C0_BSTFC_ALFC_Pos          (16UL)         /*!< ALFC (Bit 16)                                         */
40090  #define R_I3C0_BSTFC_ALFC_Msk          (0x10000UL)    /*!< ALFC (Bitfield-Mask: 0x01)                            */
40091  #define R_I3C0_BSTFC_TODFC_Pos         (20UL)         /*!< TODFC (Bit 20)                                        */
40092  #define R_I3C0_BSTFC_TODFC_Msk         (0x100000UL)   /*!< TODFC (Bitfield-Mask: 0x01)                           */
40093 /* =========================================================  NTST  ========================================================== */
40094  #define R_I3C0_NTST_TDBEF0_Pos         (0UL)          /*!< TDBEF0 (Bit 0)                                        */
40095  #define R_I3C0_NTST_TDBEF0_Msk         (0x1UL)        /*!< TDBEF0 (Bitfield-Mask: 0x01)                          */
40096  #define R_I3C0_NTST_RDBFF0_Pos         (1UL)          /*!< RDBFF0 (Bit 1)                                        */
40097  #define R_I3C0_NTST_RDBFF0_Msk         (0x2UL)        /*!< RDBFF0 (Bitfield-Mask: 0x01)                          */
40098  #define R_I3C0_NTST_IBIQEFF_Pos        (2UL)          /*!< IBIQEFF (Bit 2)                                       */
40099  #define R_I3C0_NTST_IBIQEFF_Msk        (0x4UL)        /*!< IBIQEFF (Bitfield-Mask: 0x01)                         */
40100  #define R_I3C0_NTST_CMDQEF_Pos         (3UL)          /*!< CMDQEF (Bit 3)                                        */
40101  #define R_I3C0_NTST_CMDQEF_Msk         (0x8UL)        /*!< CMDQEF (Bitfield-Mask: 0x01)                          */
40102  #define R_I3C0_NTST_RSPQFF_Pos         (4UL)          /*!< RSPQFF (Bit 4)                                        */
40103  #define R_I3C0_NTST_RSPQFF_Msk         (0x10UL)       /*!< RSPQFF (Bitfield-Mask: 0x01)                          */
40104  #define R_I3C0_NTST_TABTF_Pos          (5UL)          /*!< TABTF (Bit 5)                                         */
40105  #define R_I3C0_NTST_TABTF_Msk          (0x20UL)       /*!< TABTF (Bitfield-Mask: 0x01)                           */
40106  #define R_I3C0_NTST_TEF_Pos            (9UL)          /*!< TEF (Bit 9)                                           */
40107  #define R_I3C0_NTST_TEF_Msk            (0x200UL)      /*!< TEF (Bitfield-Mask: 0x01)                             */
40108  #define R_I3C0_NTST_RSQFF_Pos          (20UL)         /*!< RSQFF (Bit 20)                                        */
40109  #define R_I3C0_NTST_RSQFF_Msk          (0x100000UL)   /*!< RSQFF (Bitfield-Mask: 0x01)                           */
40110 /* =========================================================  NTSTE  ========================================================= */
40111  #define R_I3C0_NTSTE_TDBEE0_Pos        (0UL)          /*!< TDBEE0 (Bit 0)                                        */
40112  #define R_I3C0_NTSTE_TDBEE0_Msk        (0x1UL)        /*!< TDBEE0 (Bitfield-Mask: 0x01)                          */
40113  #define R_I3C0_NTSTE_RDBFE0_Pos        (1UL)          /*!< RDBFE0 (Bit 1)                                        */
40114  #define R_I3C0_NTSTE_RDBFE0_Msk        (0x2UL)        /*!< RDBFE0 (Bitfield-Mask: 0x01)                          */
40115  #define R_I3C0_NTSTE_IBIQEFE_Pos       (2UL)          /*!< IBIQEFE (Bit 2)                                       */
40116  #define R_I3C0_NTSTE_IBIQEFE_Msk       (0x4UL)        /*!< IBIQEFE (Bitfield-Mask: 0x01)                         */
40117  #define R_I3C0_NTSTE_CMDQEE_Pos        (3UL)          /*!< CMDQEE (Bit 3)                                        */
40118  #define R_I3C0_NTSTE_CMDQEE_Msk        (0x8UL)        /*!< CMDQEE (Bitfield-Mask: 0x01)                          */
40119  #define R_I3C0_NTSTE_RSPQFE_Pos        (4UL)          /*!< RSPQFE (Bit 4)                                        */
40120  #define R_I3C0_NTSTE_RSPQFE_Msk        (0x10UL)       /*!< RSPQFE (Bitfield-Mask: 0x01)                          */
40121  #define R_I3C0_NTSTE_TABTE_Pos         (5UL)          /*!< TABTE (Bit 5)                                         */
40122  #define R_I3C0_NTSTE_TABTE_Msk         (0x20UL)       /*!< TABTE (Bitfield-Mask: 0x01)                           */
40123  #define R_I3C0_NTSTE_TEE_Pos           (9UL)          /*!< TEE (Bit 9)                                           */
40124  #define R_I3C0_NTSTE_TEE_Msk           (0x200UL)      /*!< TEE (Bitfield-Mask: 0x01)                             */
40125  #define R_I3C0_NTSTE_RSQFE_Pos         (20UL)         /*!< RSQFE (Bit 20)                                        */
40126  #define R_I3C0_NTSTE_RSQFE_Msk         (0x100000UL)   /*!< RSQFE (Bitfield-Mask: 0x01)                           */
40127 /* =========================================================  NTIE  ========================================================== */
40128  #define R_I3C0_NTIE_TDBEIE0_Pos        (0UL)          /*!< TDBEIE0 (Bit 0)                                       */
40129  #define R_I3C0_NTIE_TDBEIE0_Msk        (0x1UL)        /*!< TDBEIE0 (Bitfield-Mask: 0x01)                         */
40130  #define R_I3C0_NTIE_RDBFIE0_Pos        (1UL)          /*!< RDBFIE0 (Bit 1)                                       */
40131  #define R_I3C0_NTIE_RDBFIE0_Msk        (0x2UL)        /*!< RDBFIE0 (Bitfield-Mask: 0x01)                         */
40132  #define R_I3C0_NTIE_IBIQEFIE_Pos       (2UL)          /*!< IBIQEFIE (Bit 2)                                      */
40133  #define R_I3C0_NTIE_IBIQEFIE_Msk       (0x4UL)        /*!< IBIQEFIE (Bitfield-Mask: 0x01)                        */
40134  #define R_I3C0_NTIE_CMDQEIE_Pos        (3UL)          /*!< CMDQEIE (Bit 3)                                       */
40135  #define R_I3C0_NTIE_CMDQEIE_Msk        (0x8UL)        /*!< CMDQEIE (Bitfield-Mask: 0x01)                         */
40136  #define R_I3C0_NTIE_RSPQFIE_Pos        (4UL)          /*!< RSPQFIE (Bit 4)                                       */
40137  #define R_I3C0_NTIE_RSPQFIE_Msk        (0x10UL)       /*!< RSPQFIE (Bitfield-Mask: 0x01)                         */
40138  #define R_I3C0_NTIE_TABTIE_Pos         (5UL)          /*!< TABTIE (Bit 5)                                        */
40139  #define R_I3C0_NTIE_TABTIE_Msk         (0x20UL)       /*!< TABTIE (Bitfield-Mask: 0x01)                          */
40140  #define R_I3C0_NTIE_TEIE_Pos           (9UL)          /*!< TEIE (Bit 9)                                          */
40141  #define R_I3C0_NTIE_TEIE_Msk           (0x200UL)      /*!< TEIE (Bitfield-Mask: 0x01)                            */
40142  #define R_I3C0_NTIE_RSQFIE_Pos         (20UL)         /*!< RSQFIE (Bit 20)                                       */
40143  #define R_I3C0_NTIE_RSQFIE_Msk         (0x100000UL)   /*!< RSQFIE (Bitfield-Mask: 0x01)                          */
40144 /* ========================================================  NTSTFC  ========================================================= */
40145  #define R_I3C0_NTSTFC_TDBEFC0_Pos      (0UL)          /*!< TDBEFC0 (Bit 0)                                       */
40146  #define R_I3C0_NTSTFC_TDBEFC0_Msk      (0x1UL)        /*!< TDBEFC0 (Bitfield-Mask: 0x01)                         */
40147  #define R_I3C0_NTSTFC_RDBFFC0_Pos      (1UL)          /*!< RDBFFC0 (Bit 1)                                       */
40148  #define R_I3C0_NTSTFC_RDBFFC0_Msk      (0x2UL)        /*!< RDBFFC0 (Bitfield-Mask: 0x01)                         */
40149  #define R_I3C0_NTSTFC_IBIQEFFC_Pos     (2UL)          /*!< IBIQEFFC (Bit 2)                                      */
40150  #define R_I3C0_NTSTFC_IBIQEFFC_Msk     (0x4UL)        /*!< IBIQEFFC (Bitfield-Mask: 0x01)                        */
40151  #define R_I3C0_NTSTFC_CMDQEFC_Pos      (3UL)          /*!< CMDQEFC (Bit 3)                                       */
40152  #define R_I3C0_NTSTFC_CMDQEFC_Msk      (0x8UL)        /*!< CMDQEFC (Bitfield-Mask: 0x01)                         */
40153  #define R_I3C0_NTSTFC_RSPQFFC_Pos      (4UL)          /*!< RSPQFFC (Bit 4)                                       */
40154  #define R_I3C0_NTSTFC_RSPQFFC_Msk      (0x10UL)       /*!< RSPQFFC (Bitfield-Mask: 0x01)                         */
40155  #define R_I3C0_NTSTFC_TABTFC_Pos       (5UL)          /*!< TABTFC (Bit 5)                                        */
40156  #define R_I3C0_NTSTFC_TABTFC_Msk       (0x20UL)       /*!< TABTFC (Bitfield-Mask: 0x01)                          */
40157  #define R_I3C0_NTSTFC_TEFC_Pos         (9UL)          /*!< TEFC (Bit 9)                                          */
40158  #define R_I3C0_NTSTFC_TEFC_Msk         (0x200UL)      /*!< TEFC (Bitfield-Mask: 0x01)                            */
40159  #define R_I3C0_NTSTFC_RSQFFC_Pos       (20UL)         /*!< RSQFFC (Bit 20)                                       */
40160  #define R_I3C0_NTSTFC_RSQFFC_Msk       (0x100000UL)   /*!< RSQFFC (Bitfield-Mask: 0x01)                          */
40161 /* =========================================================  BCST  ========================================================== */
40162  #define R_I3C0_BCST_BFREF_Pos          (0UL)          /*!< BFREF (Bit 0)                                         */
40163  #define R_I3C0_BCST_BFREF_Msk          (0x1UL)        /*!< BFREF (Bitfield-Mask: 0x01)                           */
40164  #define R_I3C0_BCST_BAVLF_Pos          (1UL)          /*!< BAVLF (Bit 1)                                         */
40165  #define R_I3C0_BCST_BAVLF_Msk          (0x2UL)        /*!< BAVLF (Bitfield-Mask: 0x01)                           */
40166  #define R_I3C0_BCST_BIDLF_Pos          (2UL)          /*!< BIDLF (Bit 2)                                         */
40167  #define R_I3C0_BCST_BIDLF_Msk          (0x4UL)        /*!< BIDLF (Bitfield-Mask: 0x01)                           */
40168 /* =========================================================  SVST  ========================================================== */
40169  #define R_I3C0_SVST_GCAF_Pos           (0UL)          /*!< GCAF (Bit 0)                                          */
40170  #define R_I3C0_SVST_GCAF_Msk           (0x1UL)        /*!< GCAF (Bitfield-Mask: 0x01)                            */
40171  #define R_I3C0_SVST_HSMCF_Pos          (5UL)          /*!< HSMCF (Bit 5)                                         */
40172  #define R_I3C0_SVST_HSMCF_Msk          (0x20UL)       /*!< HSMCF (Bitfield-Mask: 0x01)                           */
40173  #define R_I3C0_SVST_DVIDF_Pos          (6UL)          /*!< DVIDF (Bit 6)                                         */
40174  #define R_I3C0_SVST_DVIDF_Msk          (0x40UL)       /*!< DVIDF (Bitfield-Mask: 0x01)                           */
40175  #define R_I3C0_SVST_HOAF_Pos           (15UL)         /*!< HOAF (Bit 15)                                         */
40176  #define R_I3C0_SVST_HOAF_Msk           (0x8000UL)     /*!< HOAF (Bitfield-Mask: 0x01)                            */
40177  #define R_I3C0_SVST_SVAFn_Pos          (16UL)         /*!< SVAFn (Bit 16)                                        */
40178  #define R_I3C0_SVST_SVAFn_Msk          (0x10000UL)    /*!< SVAFn (Bitfield-Mask: 0x01)                           */
40179 /* =========================================================  WUST  ========================================================== */
40180  #define R_I3C0_WUST_WUASYNF_Pos        (0UL)          /*!< WUASYNF (Bit 0)                                       */
40181  #define R_I3C0_WUST_WUASYNF_Msk        (0x1UL)        /*!< WUASYNF (Bitfield-Mask: 0x01)                         */
40182 /* ========================================================  DATBAS0  ======================================================== */
40183  #define R_I3C0_DATBAS0_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
40184  #define R_I3C0_DATBAS0_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
40185  #define R_I3C0_DATBAS0_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
40186  #define R_I3C0_DATBAS0_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
40187  #define R_I3C0_DATBAS0_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
40188  #define R_I3C0_DATBAS0_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
40189  #define R_I3C0_DATBAS0_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
40190  #define R_I3C0_DATBAS0_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
40191  #define R_I3C0_DATBAS0_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
40192  #define R_I3C0_DATBAS0_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
40193  #define R_I3C0_DATBAS0_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
40194  #define R_I3C0_DATBAS0_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
40195  #define R_I3C0_DATBAS0_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
40196  #define R_I3C0_DATBAS0_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
40197  #define R_I3C0_DATBAS0_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
40198  #define R_I3C0_DATBAS0_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
40199 /* ========================================================  DATBAS1  ======================================================== */
40200  #define R_I3C0_DATBAS1_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
40201  #define R_I3C0_DATBAS1_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
40202  #define R_I3C0_DATBAS1_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
40203  #define R_I3C0_DATBAS1_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
40204  #define R_I3C0_DATBAS1_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
40205  #define R_I3C0_DATBAS1_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
40206  #define R_I3C0_DATBAS1_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
40207  #define R_I3C0_DATBAS1_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
40208  #define R_I3C0_DATBAS1_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
40209  #define R_I3C0_DATBAS1_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
40210  #define R_I3C0_DATBAS1_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
40211  #define R_I3C0_DATBAS1_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
40212  #define R_I3C0_DATBAS1_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
40213  #define R_I3C0_DATBAS1_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
40214  #define R_I3C0_DATBAS1_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
40215  #define R_I3C0_DATBAS1_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
40216 /* ========================================================  DATBAS2  ======================================================== */
40217  #define R_I3C0_DATBAS2_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
40218  #define R_I3C0_DATBAS2_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
40219  #define R_I3C0_DATBAS2_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
40220  #define R_I3C0_DATBAS2_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
40221  #define R_I3C0_DATBAS2_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
40222  #define R_I3C0_DATBAS2_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
40223  #define R_I3C0_DATBAS2_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
40224  #define R_I3C0_DATBAS2_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
40225  #define R_I3C0_DATBAS2_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
40226  #define R_I3C0_DATBAS2_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
40227  #define R_I3C0_DATBAS2_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
40228  #define R_I3C0_DATBAS2_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
40229  #define R_I3C0_DATBAS2_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
40230  #define R_I3C0_DATBAS2_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
40231  #define R_I3C0_DATBAS2_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
40232  #define R_I3C0_DATBAS2_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
40233 /* ========================================================  DATBAS3  ======================================================== */
40234  #define R_I3C0_DATBAS3_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
40235  #define R_I3C0_DATBAS3_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
40236  #define R_I3C0_DATBAS3_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
40237  #define R_I3C0_DATBAS3_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
40238  #define R_I3C0_DATBAS3_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
40239  #define R_I3C0_DATBAS3_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
40240  #define R_I3C0_DATBAS3_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
40241  #define R_I3C0_DATBAS3_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
40242  #define R_I3C0_DATBAS3_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
40243  #define R_I3C0_DATBAS3_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
40244  #define R_I3C0_DATBAS3_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
40245  #define R_I3C0_DATBAS3_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
40246  #define R_I3C0_DATBAS3_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
40247  #define R_I3C0_DATBAS3_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
40248  #define R_I3C0_DATBAS3_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
40249  #define R_I3C0_DATBAS3_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
40250 /* =======================================================  EXDATBAS  ======================================================== */
40251  #define R_I3C0_EXDATBAS_EDSTAD_Pos     (0UL)          /*!< EDSTAD (Bit 0)                                        */
40252  #define R_I3C0_EXDATBAS_EDSTAD_Msk     (0x7fUL)       /*!< EDSTAD (Bitfield-Mask: 0x7f)                          */
40253  #define R_I3C0_EXDATBAS_EDDYAD_Pos     (16UL)         /*!< EDDYAD (Bit 16)                                       */
40254  #define R_I3C0_EXDATBAS_EDDYAD_Msk     (0xff0000UL)   /*!< EDDYAD (Bitfield-Mask: 0xff)                          */
40255  #define R_I3C0_EXDATBAS_EDNACK_Pos     (29UL)         /*!< EDNACK (Bit 29)                                       */
40256  #define R_I3C0_EXDATBAS_EDNACK_Msk     (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03)                          */
40257  #define R_I3C0_EXDATBAS_EDTYP_Pos      (31UL)         /*!< EDTYP (Bit 31)                                        */
40258  #define R_I3C0_EXDATBAS_EDTYP_Msk      (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01)                           */
40259 /* =======================================================  SDATBAS0  ======================================================== */
40260  #define R_I3C0_SDATBAS0_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
40261  #define R_I3C0_SDATBAS0_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
40262  #define R_I3C0_SDATBAS0_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
40263  #define R_I3C0_SDATBAS0_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
40264  #define R_I3C0_SDATBAS0_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
40265  #define R_I3C0_SDATBAS0_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
40266  #define R_I3C0_SDATBAS0_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
40267  #define R_I3C0_SDATBAS0_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
40268 /* =======================================================  SDATBAS1  ======================================================== */
40269  #define R_I3C0_SDATBAS1_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
40270  #define R_I3C0_SDATBAS1_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
40271  #define R_I3C0_SDATBAS1_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
40272  #define R_I3C0_SDATBAS1_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
40273  #define R_I3C0_SDATBAS1_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
40274  #define R_I3C0_SDATBAS1_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
40275  #define R_I3C0_SDATBAS1_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
40276  #define R_I3C0_SDATBAS1_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
40277 /* =======================================================  SDATBAS2  ======================================================== */
40278  #define R_I3C0_SDATBAS2_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
40279  #define R_I3C0_SDATBAS2_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
40280  #define R_I3C0_SDATBAS2_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
40281  #define R_I3C0_SDATBAS2_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
40282  #define R_I3C0_SDATBAS2_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
40283  #define R_I3C0_SDATBAS2_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
40284  #define R_I3C0_SDATBAS2_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
40285  #define R_I3C0_SDATBAS2_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
40286 /* ========================================================  MSDCT0  ========================================================= */
40287  #define R_I3C0_MSDCT0_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
40288  #define R_I3C0_MSDCT0_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
40289  #define R_I3C0_MSDCT0_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
40290  #define R_I3C0_MSDCT0_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
40291  #define R_I3C0_MSDCT0_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
40292  #define R_I3C0_MSDCT0_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
40293  #define R_I3C0_MSDCT0_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
40294  #define R_I3C0_MSDCT0_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
40295  #define R_I3C0_MSDCT0_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
40296  #define R_I3C0_MSDCT0_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
40297 /* ========================================================  MSDCT1  ========================================================= */
40298  #define R_I3C0_MSDCT1_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
40299  #define R_I3C0_MSDCT1_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
40300  #define R_I3C0_MSDCT1_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
40301  #define R_I3C0_MSDCT1_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
40302  #define R_I3C0_MSDCT1_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
40303  #define R_I3C0_MSDCT1_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
40304  #define R_I3C0_MSDCT1_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
40305  #define R_I3C0_MSDCT1_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
40306  #define R_I3C0_MSDCT1_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
40307  #define R_I3C0_MSDCT1_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
40308 /* ========================================================  MSDCT2  ========================================================= */
40309  #define R_I3C0_MSDCT2_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
40310  #define R_I3C0_MSDCT2_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
40311  #define R_I3C0_MSDCT2_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
40312  #define R_I3C0_MSDCT2_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
40313  #define R_I3C0_MSDCT2_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
40314  #define R_I3C0_MSDCT2_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
40315  #define R_I3C0_MSDCT2_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
40316  #define R_I3C0_MSDCT2_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
40317  #define R_I3C0_MSDCT2_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
40318  #define R_I3C0_MSDCT2_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
40319 /* ========================================================  MSDCT3  ========================================================= */
40320  #define R_I3C0_MSDCT3_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
40321  #define R_I3C0_MSDCT3_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
40322  #define R_I3C0_MSDCT3_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
40323  #define R_I3C0_MSDCT3_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
40324  #define R_I3C0_MSDCT3_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
40325  #define R_I3C0_MSDCT3_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
40326  #define R_I3C0_MSDCT3_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
40327  #define R_I3C0_MSDCT3_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
40328  #define R_I3C0_MSDCT3_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
40329  #define R_I3C0_MSDCT3_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
40330 /* =========================================================  SVDCT  ========================================================= */
40331  #define R_I3C0_SVDCT_TDCR_Pos          (0UL)          /*!< TDCR (Bit 0)                                          */
40332  #define R_I3C0_SVDCT_TDCR_Msk          (0xffUL)       /*!< TDCR (Bitfield-Mask: 0xff)                            */
40333  #define R_I3C0_SVDCT_TBCR0_Pos         (8UL)          /*!< TBCR0 (Bit 8)                                         */
40334  #define R_I3C0_SVDCT_TBCR0_Msk         (0x100UL)      /*!< TBCR0 (Bitfield-Mask: 0x01)                           */
40335  #define R_I3C0_SVDCT_TBCR1_Pos         (9UL)          /*!< TBCR1 (Bit 9)                                         */
40336  #define R_I3C0_SVDCT_TBCR1_Msk         (0x200UL)      /*!< TBCR1 (Bitfield-Mask: 0x01)                           */
40337  #define R_I3C0_SVDCT_TBCR2_Pos         (10UL)         /*!< TBCR2 (Bit 10)                                        */
40338  #define R_I3C0_SVDCT_TBCR2_Msk         (0x400UL)      /*!< TBCR2 (Bitfield-Mask: 0x01)                           */
40339  #define R_I3C0_SVDCT_TBCR3_Pos         (11UL)         /*!< TBCR3 (Bit 11)                                        */
40340  #define R_I3C0_SVDCT_TBCR3_Msk         (0x800UL)      /*!< TBCR3 (Bitfield-Mask: 0x01)                           */
40341  #define R_I3C0_SVDCT_TBCR76_Pos        (14UL)         /*!< TBCR76 (Bit 14)                                       */
40342  #define R_I3C0_SVDCT_TBCR76_Msk        (0xc000UL)     /*!< TBCR76 (Bitfield-Mask: 0x03)                          */
40343 /* =======================================================  SDCTPIDL  ======================================================== */
40344 /* =======================================================  SDCTPIDH  ======================================================== */
40345 /* ========================================================  SVDVAD0  ======================================================== */
40346  #define R_I3C0_SVDVAD0_SVAD_Pos        (16UL)         /*!< SVAD (Bit 16)                                         */
40347  #define R_I3C0_SVDVAD0_SVAD_Msk        (0x3ff0000UL)  /*!< SVAD (Bitfield-Mask: 0x3ff)                           */
40348  #define R_I3C0_SVDVAD0_SADLG_Pos       (27UL)         /*!< SADLG (Bit 27)                                        */
40349  #define R_I3C0_SVDVAD0_SADLG_Msk       (0x8000000UL)  /*!< SADLG (Bitfield-Mask: 0x01)                           */
40350  #define R_I3C0_SVDVAD0_SSTADV_Pos      (30UL)         /*!< SSTADV (Bit 30)                                       */
40351  #define R_I3C0_SVDVAD0_SSTADV_Msk      (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01)                          */
40352  #define R_I3C0_SVDVAD0_SDYADV_Pos      (31UL)         /*!< SDYADV (Bit 31)                                       */
40353  #define R_I3C0_SVDVAD0_SDYADV_Msk      (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01)                          */
40354 /* ========================================================  CSECMD  ========================================================= */
40355  #define R_I3C0_CSECMD_SVIRQE_Pos       (0UL)          /*!< SVIRQE (Bit 0)                                        */
40356  #define R_I3C0_CSECMD_SVIRQE_Msk       (0x1UL)        /*!< SVIRQE (Bitfield-Mask: 0x01)                          */
40357  #define R_I3C0_CSECMD_MSRQE_Pos        (1UL)          /*!< MSRQE (Bit 1)                                         */
40358  #define R_I3C0_CSECMD_MSRQE_Msk        (0x2UL)        /*!< MSRQE (Bitfield-Mask: 0x01)                           */
40359  #define R_I3C0_CSECMD_HJEVE_Pos        (3UL)          /*!< HJEVE (Bit 3)                                         */
40360  #define R_I3C0_CSECMD_HJEVE_Msk        (0x8UL)        /*!< HJEVE (Bitfield-Mask: 0x01)                           */
40361 /* ========================================================  CEACTST  ======================================================== */
40362  #define R_I3C0_CEACTST_ACTST_Pos       (0UL)          /*!< ACTST (Bit 0)                                         */
40363  #define R_I3C0_CEACTST_ACTST_Msk       (0xfUL)        /*!< ACTST (Bitfield-Mask: 0x0f)                           */
40364 /* =========================================================  CMWLG  ========================================================= */
40365  #define R_I3C0_CMWLG_MWLG_Pos          (0UL)          /*!< MWLG (Bit 0)                                          */
40366  #define R_I3C0_CMWLG_MWLG_Msk          (0xffffUL)     /*!< MWLG (Bitfield-Mask: 0xffff)                          */
40367 /* =========================================================  CMRLG  ========================================================= */
40368  #define R_I3C0_CMRLG_MRLG_Pos          (0UL)          /*!< MRLG (Bit 0)                                          */
40369  #define R_I3C0_CMRLG_MRLG_Msk          (0xffffUL)     /*!< MRLG (Bitfield-Mask: 0xffff)                          */
40370  #define R_I3C0_CMRLG_IBIPSZ_Pos        (16UL)         /*!< IBIPSZ (Bit 16)                                       */
40371  #define R_I3C0_CMRLG_IBIPSZ_Msk        (0xff0000UL)   /*!< IBIPSZ (Bitfield-Mask: 0xff)                          */
40372 /* ========================================================  CETSTMD  ======================================================== */
40373  #define R_I3C0_CETSTMD_TSTMD_Pos       (0UL)          /*!< TSTMD (Bit 0)                                         */
40374  #define R_I3C0_CETSTMD_TSTMD_Msk       (0xffUL)       /*!< TSTMD (Bitfield-Mask: 0xff)                           */
40375 /* ========================================================  CGDVST  ========================================================= */
40376  #define R_I3C0_CGDVST_PNDINT_Pos       (0UL)          /*!< PNDINT (Bit 0)                                        */
40377  #define R_I3C0_CGDVST_PNDINT_Msk       (0xfUL)        /*!< PNDINT (Bitfield-Mask: 0x0f)                          */
40378  #define R_I3C0_CGDVST_PRTE_Pos         (5UL)          /*!< PRTE (Bit 5)                                          */
40379  #define R_I3C0_CGDVST_PRTE_Msk         (0x20UL)       /*!< PRTE (Bitfield-Mask: 0x01)                            */
40380  #define R_I3C0_CGDVST_ACTMD_Pos        (6UL)          /*!< ACTMD (Bit 6)                                         */
40381  #define R_I3C0_CGDVST_ACTMD_Msk        (0xc0UL)       /*!< ACTMD (Bitfield-Mask: 0x03)                           */
40382  #define R_I3C0_CGDVST_VDRSV_Pos        (8UL)          /*!< VDRSV (Bit 8)                                         */
40383  #define R_I3C0_CGDVST_VDRSV_Msk        (0xff00UL)     /*!< VDRSV (Bitfield-Mask: 0xff)                           */
40384 /* ========================================================  CMDSPW  ========================================================= */
40385  #define R_I3C0_CMDSPW_MSWDR_Pos        (0UL)          /*!< MSWDR (Bit 0)                                         */
40386  #define R_I3C0_CMDSPW_MSWDR_Msk        (0x7UL)        /*!< MSWDR (Bitfield-Mask: 0x07)                           */
40387 /* ========================================================  CMDSPR  ========================================================= */
40388  #define R_I3C0_CMDSPR_MSRDR_Pos        (0UL)          /*!< MSRDR (Bit 0)                                         */
40389  #define R_I3C0_CMDSPR_MSRDR_Msk        (0x7UL)        /*!< MSRDR (Bitfield-Mask: 0x07)                           */
40390  #define R_I3C0_CMDSPR_CDTTIM_Pos       (3UL)          /*!< CDTTIM (Bit 3)                                        */
40391  #define R_I3C0_CMDSPR_CDTTIM_Msk       (0x38UL)       /*!< CDTTIM (Bitfield-Mask: 0x07)                          */
40392 /* ========================================================  CMDSPT  ========================================================= */
40393  #define R_I3C0_CMDSPT_MRTTIM_Pos       (0UL)          /*!< MRTTIM (Bit 0)                                        */
40394  #define R_I3C0_CMDSPT_MRTTIM_Msk       (0xffffffUL)   /*!< MRTTIM (Bitfield-Mask: 0xffffff)                      */
40395  #define R_I3C0_CMDSPT_MRTE_Pos         (31UL)         /*!< MRTE (Bit 31)                                         */
40396  #define R_I3C0_CMDSPT_MRTE_Msk         (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01)                            */
40397 /* =========================================================  CETSM  ========================================================= */
40398  #define R_I3C0_CETSM_FREQ_Pos          (8UL)          /*!< FREQ (Bit 8)                                          */
40399  #define R_I3C0_CETSM_FREQ_Msk          (0xff00UL)     /*!< FREQ (Bitfield-Mask: 0xff)                            */
40400  #define R_I3C0_CETSM_INAC_Pos          (16UL)         /*!< INAC (Bit 16)                                         */
40401  #define R_I3C0_CETSM_INAC_Msk          (0xff0000UL)   /*!< INAC (Bitfield-Mask: 0xff)                            */
40402 /* ========================================================  BITCNT  ========================================================= */
40403  #define R_I3C0_BITCNT_BCNT_Pos         (0UL)          /*!< BCNT (Bit 0)                                          */
40404  #define R_I3C0_BITCNT_BCNT_Msk         (0x1fUL)       /*!< BCNT (Bitfield-Mask: 0x1f)                            */
40405  #define R_I3C0_BITCNT_BCNTWP_Pos       (7UL)          /*!< BCNTWP (Bit 7)                                        */
40406  #define R_I3C0_BITCNT_BCNTWP_Msk       (0x80UL)       /*!< BCNTWP (Bitfield-Mask: 0x01)                          */
40407 /* ========================================================  NQSTLV  ========================================================= */
40408  #define R_I3C0_NQSTLV_CMDQFLV_Pos      (0UL)          /*!< CMDQFLV (Bit 0)                                       */
40409  #define R_I3C0_NQSTLV_CMDQFLV_Msk      (0xffUL)       /*!< CMDQFLV (Bitfield-Mask: 0xff)                         */
40410  #define R_I3C0_NQSTLV_RSPQLV_Pos       (8UL)          /*!< RSPQLV (Bit 8)                                        */
40411  #define R_I3C0_NQSTLV_RSPQLV_Msk       (0xff00UL)     /*!< RSPQLV (Bitfield-Mask: 0xff)                          */
40412  #define R_I3C0_NQSTLV_IBIQLV_Pos       (16UL)         /*!< IBIQLV (Bit 16)                                       */
40413  #define R_I3C0_NQSTLV_IBIQLV_Msk       (0xff0000UL)   /*!< IBIQLV (Bitfield-Mask: 0xff)                          */
40414  #define R_I3C0_NQSTLV_IBISCNT_Pos      (24UL)         /*!< IBISCNT (Bit 24)                                      */
40415  #define R_I3C0_NQSTLV_IBISCNT_Msk      (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f)                         */
40416 /* =======================================================  NDBSTLV0  ======================================================== */
40417  #define R_I3C0_NDBSTLV0_TDBFLV_Pos     (0UL)          /*!< TDBFLV (Bit 0)                                        */
40418  #define R_I3C0_NDBSTLV0_TDBFLV_Msk     (0xffUL)       /*!< TDBFLV (Bitfield-Mask: 0xff)                          */
40419  #define R_I3C0_NDBSTLV0_RDBLV_Pos      (8UL)          /*!< RDBLV (Bit 8)                                         */
40420  #define R_I3C0_NDBSTLV0_RDBLV_Msk      (0xff00UL)     /*!< RDBLV (Bitfield-Mask: 0xff)                           */
40421 /* =======================================================  NRSQSTLV  ======================================================== */
40422  #define R_I3C0_NRSQSTLV_RSQLV_Pos      (0UL)          /*!< RSQLV (Bit 0)                                         */
40423  #define R_I3C0_NRSQSTLV_RSQLV_Msk      (0xffUL)       /*!< RSQLV (Bitfield-Mask: 0xff)                           */
40424 /* ========================================================  PRSTDBG  ======================================================== */
40425  #define R_I3C0_PRSTDBG_SCILV_Pos       (0UL)          /*!< SCILV (Bit 0)                                         */
40426  #define R_I3C0_PRSTDBG_SCILV_Msk       (0x1UL)        /*!< SCILV (Bitfield-Mask: 0x01)                           */
40427  #define R_I3C0_PRSTDBG_SDILV_Pos       (1UL)          /*!< SDILV (Bit 1)                                         */
40428  #define R_I3C0_PRSTDBG_SDILV_Msk       (0x2UL)        /*!< SDILV (Bitfield-Mask: 0x01)                           */
40429  #define R_I3C0_PRSTDBG_SCOLV_Pos       (2UL)          /*!< SCOLV (Bit 2)                                         */
40430  #define R_I3C0_PRSTDBG_SCOLV_Msk       (0x4UL)        /*!< SCOLV (Bitfield-Mask: 0x01)                           */
40431  #define R_I3C0_PRSTDBG_SDOLV_Pos       (3UL)          /*!< SDOLV (Bit 3)                                         */
40432  #define R_I3C0_PRSTDBG_SDOLV_Msk       (0x8UL)        /*!< SDOLV (Bitfield-Mask: 0x01)                           */
40433 /* =======================================================  MSERRCNT  ======================================================== */
40434  #define R_I3C0_MSERRCNT_M2ECNT_Pos     (0UL)          /*!< M2ECNT (Bit 0)                                        */
40435  #define R_I3C0_MSERRCNT_M2ECNT_Msk     (0xffUL)       /*!< M2ECNT (Bitfield-Mask: 0xff)                          */
40436 
40437 /* =========================================================================================================================== */
40438 /* ================                                           R_MMF                                           ================ */
40439 /* =========================================================================================================================== */
40440 
40441 /* =========================================================  MMSFR  ========================================================= */
40442  #define R_MMF_MMSFR_KEY_Pos           (24UL)         /*!< KEY (Bit 24)                                          */
40443  #define R_MMF_MMSFR_KEY_Msk           (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
40444  #define R_MMF_MMSFR_MEMMIRADDR_Pos    (7UL)          /*!< MEMMIRADDR (Bit 7)                                    */
40445  #define R_MMF_MMSFR_MEMMIRADDR_Msk    (0x7fff80UL)   /*!< MEMMIRADDR (Bitfield-Mask: 0xffff)                    */
40446 /* =========================================================  MMEN  ========================================================== */
40447  #define R_MMF_MMEN_KEY_Pos            (24UL)         /*!< KEY (Bit 24)                                          */
40448  #define R_MMF_MMEN_KEY_Msk            (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
40449  #define R_MMF_MMEN_EN_Pos             (0UL)          /*!< EN (Bit 0)                                            */
40450  #define R_MMF_MMEN_EN_Msk             (0x1UL)        /*!< EN (Bitfield-Mask: 0x01)                              */
40451 
40452 /* =========================================================================================================================== */
40453 /* ================                                        R_MPU_MMPU                                         ================ */
40454 /* =========================================================================================================================== */
40455 
40456 /* =========================================================================================================================== */
40457 /* ================                                        R_MPU_SMPU                                         ================ */
40458 /* =========================================================================================================================== */
40459 
40460 /* ========================================================  SMPUCTL  ======================================================== */
40461  #define R_MPU_SMPU_SMPUCTL_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
40462  #define R_MPU_SMPU_SMPUCTL_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
40463  #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos    (1UL)      /*!< PROTECT (Bit 1)                                       */
40464  #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk    (0x2UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
40465  #define R_MPU_SMPU_SMPUCTL_OAD_Pos        (0UL)      /*!< OAD (Bit 0)                                           */
40466  #define R_MPU_SMPU_SMPUCTL_OAD_Msk        (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
40467 
40468 /* =========================================================================================================================== */
40469 /* ================                                        R_MPU_SPMON                                        ================ */
40470 /* =========================================================================================================================== */
40471 
40472 /* =========================================================================================================================== */
40473 /* ================                                          R_MSTP                                           ================ */
40474 /* =========================================================================================================================== */
40475 
40476 /* ========================================================  MSTPCRA  ======================================================== */
40477  #define R_MSTP_MSTPCRA_MSTPA22_Pos    (22UL)         /*!< MSTPA22 (Bit 22)                                      */
40478  #define R_MSTP_MSTPCRA_MSTPA22_Msk    (0x400000UL)   /*!< MSTPA22 (Bitfield-Mask: 0x01)                         */
40479  #define R_MSTP_MSTPCRA_MSTPA7_Pos     (7UL)          /*!< MSTPA7 (Bit 7)                                        */
40480  #define R_MSTP_MSTPCRA_MSTPA7_Msk     (0x80UL)       /*!< MSTPA7 (Bitfield-Mask: 0x01)                          */
40481  #define R_MSTP_MSTPCRA_MSTPA0_Pos     (0UL)          /*!< MSTPA0 (Bit 0)                                        */
40482  #define R_MSTP_MSTPCRA_MSTPA0_Msk     (0x1UL)        /*!< MSTPA0 (Bitfield-Mask: 0x01)                          */
40483 /* ========================================================  MSTPCRB  ======================================================== */
40484  #define R_MSTP_MSTPCRB_MSTPB31_Pos    (31UL)         /*!< MSTPB31 (Bit 31)                                      */
40485  #define R_MSTP_MSTPCRB_MSTPB31_Msk    (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01)                         */
40486  #define R_MSTP_MSTPCRB_MSTPB30_Pos    (30UL)         /*!< MSTPB30 (Bit 30)                                      */
40487  #define R_MSTP_MSTPCRB_MSTPB30_Msk    (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01)                         */
40488  #define R_MSTP_MSTPCRB_MSTPB29_Pos    (29UL)         /*!< MSTPB29 (Bit 29)                                      */
40489  #define R_MSTP_MSTPCRB_MSTPB29_Msk    (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01)                         */
40490  #define R_MSTP_MSTPCRB_MSTPB28_Pos    (28UL)         /*!< MSTPB28 (Bit 28)                                      */
40491  #define R_MSTP_MSTPCRB_MSTPB28_Msk    (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01)                         */
40492  #define R_MSTP_MSTPCRB_MSTPB27_Pos    (27UL)         /*!< MSTPB27 (Bit 27)                                      */
40493  #define R_MSTP_MSTPCRB_MSTPB27_Msk    (0x8000000UL)  /*!< MSTPB27 (Bitfield-Mask: 0x01)                         */
40494  #define R_MSTP_MSTPCRB_MSTPB26_Pos    (26UL)         /*!< MSTPB26 (Bit 26)                                      */
40495  #define R_MSTP_MSTPCRB_MSTPB26_Msk    (0x4000000UL)  /*!< MSTPB26 (Bitfield-Mask: 0x01)                         */
40496  #define R_MSTP_MSTPCRB_MSTPB25_Pos    (25UL)         /*!< MSTPB25 (Bit 25)                                      */
40497  #define R_MSTP_MSTPCRB_MSTPB25_Msk    (0x2000000UL)  /*!< MSTPB25 (Bitfield-Mask: 0x01)                         */
40498  #define R_MSTP_MSTPCRB_MSTPB24_Pos    (24UL)         /*!< MSTPB24 (Bit 24)                                      */
40499  #define R_MSTP_MSTPCRB_MSTPB24_Msk    (0x1000000UL)  /*!< MSTPB24 (Bitfield-Mask: 0x01)                         */
40500  #define R_MSTP_MSTPCRB_MSTPB23_Pos    (23UL)         /*!< MSTPB23 (Bit 23)                                      */
40501  #define R_MSTP_MSTPCRB_MSTPB23_Msk    (0x800000UL)   /*!< MSTPB23 (Bitfield-Mask: 0x01)                         */
40502  #define R_MSTP_MSTPCRB_MSTPB22_Pos    (22UL)         /*!< MSTPB22 (Bit 22)                                      */
40503  #define R_MSTP_MSTPCRB_MSTPB22_Msk    (0x400000UL)   /*!< MSTPB22 (Bitfield-Mask: 0x01)                         */
40504  #define R_MSTP_MSTPCRB_MSTPB19_Pos    (19UL)         /*!< MSTPB19 (Bit 19)                                      */
40505  #define R_MSTP_MSTPCRB_MSTPB19_Msk    (0x80000UL)    /*!< MSTPB19 (Bitfield-Mask: 0x01)                         */
40506  #define R_MSTP_MSTPCRB_MSTPB18_Pos    (18UL)         /*!< MSTPB18 (Bit 18)                                      */
40507  #define R_MSTP_MSTPCRB_MSTPB18_Msk    (0x40000UL)    /*!< MSTPB18 (Bitfield-Mask: 0x01)                         */
40508  #define R_MSTP_MSTPCRB_MSTPB15_Pos    (15UL)         /*!< MSTPB15 (Bit 15)                                      */
40509  #define R_MSTP_MSTPCRB_MSTPB15_Msk    (0x8000UL)     /*!< MSTPB15 (Bitfield-Mask: 0x01)                         */
40510  #define R_MSTP_MSTPCRB_MSTPB14_Pos    (14UL)         /*!< MSTPB14 (Bit 14)                                      */
40511  #define R_MSTP_MSTPCRB_MSTPB14_Msk    (0x4000UL)     /*!< MSTPB14 (Bitfield-Mask: 0x01)                         */
40512  #define R_MSTP_MSTPCRB_MSTPB13_Pos    (13UL)         /*!< MSTPB13 (Bit 13)                                      */
40513  #define R_MSTP_MSTPCRB_MSTPB13_Msk    (0x2000UL)     /*!< MSTPB13 (Bitfield-Mask: 0x01)                         */
40514  #define R_MSTP_MSTPCRB_MSTPB12_Pos    (12UL)         /*!< MSTPB12 (Bit 12)                                      */
40515  #define R_MSTP_MSTPCRB_MSTPB12_Msk    (0x1000UL)     /*!< MSTPB12 (Bitfield-Mask: 0x01)                         */
40516  #define R_MSTP_MSTPCRB_MSTPB11_Pos    (11UL)         /*!< MSTPB11 (Bit 11)                                      */
40517  #define R_MSTP_MSTPCRB_MSTPB11_Msk    (0x800UL)      /*!< MSTPB11 (Bitfield-Mask: 0x01)                         */
40518  #define R_MSTP_MSTPCRB_MSTPB9_Pos     (9UL)          /*!< MSTPB9 (Bit 9)                                        */
40519  #define R_MSTP_MSTPCRB_MSTPB9_Msk     (0x200UL)      /*!< MSTPB9 (Bitfield-Mask: 0x01)                          */
40520  #define R_MSTP_MSTPCRB_MSTPB8_Pos     (8UL)          /*!< MSTPB8 (Bit 8)                                        */
40521  #define R_MSTP_MSTPCRB_MSTPB8_Msk     (0x100UL)      /*!< MSTPB8 (Bitfield-Mask: 0x01)                          */
40522  #define R_MSTP_MSTPCRB_MSTPB7_Pos     (7UL)          /*!< MSTPB7 (Bit 7)                                        */
40523  #define R_MSTP_MSTPCRB_MSTPB7_Msk     (0x80UL)       /*!< MSTPB7 (Bitfield-Mask: 0x01)                          */
40524  #define R_MSTP_MSTPCRB_MSTPB6_Pos     (6UL)          /*!< MSTPB6 (Bit 6)                                        */
40525  #define R_MSTP_MSTPCRB_MSTPB6_Msk     (0x40UL)       /*!< MSTPB6 (Bitfield-Mask: 0x01)                          */
40526  #define R_MSTP_MSTPCRB_MSTPB5_Pos     (5UL)          /*!< MSTPB5 (Bit 5)                                        */
40527  #define R_MSTP_MSTPCRB_MSTPB5_Msk     (0x20UL)       /*!< MSTPB5 (Bitfield-Mask: 0x01)                          */
40528  #define R_MSTP_MSTPCRB_MSTPB3_Pos     (3UL)          /*!< MSTPB3 (Bit 3)                                        */
40529  #define R_MSTP_MSTPCRB_MSTPB3_Msk     (0x8UL)        /*!< MSTPB3 (Bitfield-Mask: 0x01)                          */
40530  #define R_MSTP_MSTPCRB_MSTPB2_Pos     (2UL)          /*!< MSTPB2 (Bit 2)                                        */
40531  #define R_MSTP_MSTPCRB_MSTPB2_Msk     (0x4UL)        /*!< MSTPB2 (Bitfield-Mask: 0x01)                          */
40532  #define R_MSTP_MSTPCRB_MSTPB1_Pos     (1UL)          /*!< MSTPB1 (Bit 1)                                        */
40533  #define R_MSTP_MSTPCRB_MSTPB1_Msk     (0x2UL)        /*!< MSTPB1 (Bitfield-Mask: 0x01)                          */
40534 /* ========================================================  MSTPCRC  ======================================================== */
40535  #define R_MSTP_MSTPCRC_MSTPC31_Pos    (31UL)         /*!< MSTPC31 (Bit 31)                                      */
40536  #define R_MSTP_MSTPCRC_MSTPC31_Msk    (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01)                         */
40537  #define R_MSTP_MSTPCRC_MSTPC28_Pos    (28UL)         /*!< MSTPC28 (Bit 28)                                      */
40538  #define R_MSTP_MSTPCRC_MSTPC28_Msk    (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01)                         */
40539  #define R_MSTP_MSTPCRC_MSTPC27_Pos    (27UL)         /*!< MSTPC27 (Bit 27)                                      */
40540  #define R_MSTP_MSTPCRC_MSTPC27_Msk    (0x8000000UL)  /*!< MSTPC27 (Bitfield-Mask: 0x01)                         */
40541  #define R_MSTP_MSTPCRC_MSTPC21_Pos    (21UL)         /*!< MSTPC21 (Bit 21)                                      */
40542  #define R_MSTP_MSTPCRC_MSTPC21_Msk    (0x200000UL)   /*!< MSTPC21 (Bitfield-Mask: 0x01)                         */
40543  #define R_MSTP_MSTPCRC_MSTPC20_Pos    (20UL)         /*!< MSTPC20 (Bit 20)                                      */
40544  #define R_MSTP_MSTPCRC_MSTPC20_Msk    (0x100000UL)   /*!< MSTPC20 (Bitfield-Mask: 0x01)                         */
40545  #define R_MSTP_MSTPCRC_MSTPC14_Pos    (14UL)         /*!< MSTPC14 (Bit 14)                                      */
40546  #define R_MSTP_MSTPCRC_MSTPC14_Msk    (0x4000UL)     /*!< MSTPC14 (Bitfield-Mask: 0x01)                         */
40547  #define R_MSTP_MSTPCRC_MSTPC13_Pos    (13UL)         /*!< MSTPC13 (Bit 13)                                      */
40548  #define R_MSTP_MSTPCRC_MSTPC13_Msk    (0x2000UL)     /*!< MSTPC13 (Bitfield-Mask: 0x01)                         */
40549  #define R_MSTP_MSTPCRC_MSTPC12_Pos    (12UL)         /*!< MSTPC12 (Bit 12)                                      */
40550  #define R_MSTP_MSTPCRC_MSTPC12_Msk    (0x1000UL)     /*!< MSTPC12 (Bitfield-Mask: 0x01)                         */
40551  #define R_MSTP_MSTPCRC_MSTPC11_Pos    (11UL)         /*!< MSTPC11 (Bit 11)                                      */
40552  #define R_MSTP_MSTPCRC_MSTPC11_Msk    (0x800UL)      /*!< MSTPC11 (Bitfield-Mask: 0x01)                         */
40553  #define R_MSTP_MSTPCRC_MSTPC9_Pos     (9UL)          /*!< MSTPC9 (Bit 9)                                        */
40554  #define R_MSTP_MSTPCRC_MSTPC9_Msk     (0x200UL)      /*!< MSTPC9 (Bitfield-Mask: 0x01)                          */
40555  #define R_MSTP_MSTPCRC_MSTPC8_Pos     (8UL)          /*!< MSTPC8 (Bit 8)                                        */
40556  #define R_MSTP_MSTPCRC_MSTPC8_Msk     (0x100UL)      /*!< MSTPC8 (Bitfield-Mask: 0x01)                          */
40557  #define R_MSTP_MSTPCRC_MSTPC7_Pos     (7UL)          /*!< MSTPC7 (Bit 7)                                        */
40558  #define R_MSTP_MSTPCRC_MSTPC7_Msk     (0x80UL)       /*!< MSTPC7 (Bitfield-Mask: 0x01)                          */
40559  #define R_MSTP_MSTPCRC_MSTPC6_Pos     (6UL)          /*!< MSTPC6 (Bit 6)                                        */
40560  #define R_MSTP_MSTPCRC_MSTPC6_Msk     (0x40UL)       /*!< MSTPC6 (Bitfield-Mask: 0x01)                          */
40561  #define R_MSTP_MSTPCRC_MSTPC5_Pos     (5UL)          /*!< MSTPC5 (Bit 5)                                        */
40562  #define R_MSTP_MSTPCRC_MSTPC5_Msk     (0x20UL)       /*!< MSTPC5 (Bitfield-Mask: 0x01)                          */
40563  #define R_MSTP_MSTPCRC_MSTPC4_Pos     (4UL)          /*!< MSTPC4 (Bit 4)                                        */
40564  #define R_MSTP_MSTPCRC_MSTPC4_Msk     (0x10UL)       /*!< MSTPC4 (Bitfield-Mask: 0x01)                          */
40565  #define R_MSTP_MSTPCRC_MSTPC3_Pos     (3UL)          /*!< MSTPC3 (Bit 3)                                        */
40566  #define R_MSTP_MSTPCRC_MSTPC3_Msk     (0x8UL)        /*!< MSTPC3 (Bitfield-Mask: 0x01)                          */
40567  #define R_MSTP_MSTPCRC_MSTPC2_Pos     (2UL)          /*!< MSTPC2 (Bit 2)                                        */
40568  #define R_MSTP_MSTPCRC_MSTPC2_Msk     (0x4UL)        /*!< MSTPC2 (Bitfield-Mask: 0x01)                          */
40569  #define R_MSTP_MSTPCRC_MSTPC1_Pos     (1UL)          /*!< MSTPC1 (Bit 1)                                        */
40570  #define R_MSTP_MSTPCRC_MSTPC1_Msk     (0x2UL)        /*!< MSTPC1 (Bitfield-Mask: 0x01)                          */
40571  #define R_MSTP_MSTPCRC_MSTPC0_Pos     (0UL)          /*!< MSTPC0 (Bit 0)                                        */
40572  #define R_MSTP_MSTPCRC_MSTPC0_Msk     (0x1UL)        /*!< MSTPC0 (Bitfield-Mask: 0x01)                          */
40573 /* ========================================================  MSTPCRD  ======================================================== */
40574  #define R_MSTP_MSTPCRD_MSTPD31_Pos    (31UL)         /*!< MSTPD31 (Bit 31)                                      */
40575  #define R_MSTP_MSTPCRD_MSTPD31_Msk    (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01)                         */
40576  #define R_MSTP_MSTPCRD_MSTPD29_Pos    (29UL)         /*!< MSTPD29 (Bit 29)                                      */
40577  #define R_MSTP_MSTPCRD_MSTPD29_Msk    (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01)                         */
40578  #define R_MSTP_MSTPCRD_MSTPD28_Pos    (28UL)         /*!< MSTPD28 (Bit 28)                                      */
40579  #define R_MSTP_MSTPCRD_MSTPD28_Msk    (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01)                         */
40580  #define R_MSTP_MSTPCRD_MSTPD27_Pos    (27UL)         /*!< MSTPD27 (Bit 27)                                      */
40581  #define R_MSTP_MSTPCRD_MSTPD27_Msk    (0x8000000UL)  /*!< MSTPD27 (Bitfield-Mask: 0x01)                         */
40582  #define R_MSTP_MSTPCRD_MSTPD26_Pos    (26UL)         /*!< MSTPD26 (Bit 26)                                      */
40583  #define R_MSTP_MSTPCRD_MSTPD26_Msk    (0x4000000UL)  /*!< MSTPD26 (Bitfield-Mask: 0x01)                         */
40584  #define R_MSTP_MSTPCRD_MSTPD25_Pos    (25UL)         /*!< MSTPD25 (Bit 25)                                      */
40585  #define R_MSTP_MSTPCRD_MSTPD25_Msk    (0x2000000UL)  /*!< MSTPD25 (Bitfield-Mask: 0x01)                         */
40586  #define R_MSTP_MSTPCRD_MSTPD24_Pos    (24UL)         /*!< MSTPD24 (Bit 24)                                      */
40587  #define R_MSTP_MSTPCRD_MSTPD24_Msk    (0x1000000UL)  /*!< MSTPD24 (Bitfield-Mask: 0x01)                         */
40588  #define R_MSTP_MSTPCRD_MSTPD23_Pos    (23UL)         /*!< MSTPD23 (Bit 23)                                      */
40589  #define R_MSTP_MSTPCRD_MSTPD23_Msk    (0x800000UL)   /*!< MSTPD23 (Bitfield-Mask: 0x01)                         */
40590  #define R_MSTP_MSTPCRD_MSTPD22_Pos    (22UL)         /*!< MSTPD22 (Bit 22)                                      */
40591  #define R_MSTP_MSTPCRD_MSTPD22_Msk    (0x400000UL)   /*!< MSTPD22 (Bitfield-Mask: 0x01)                         */
40592  #define R_MSTP_MSTPCRD_MSTPD20_Pos    (20UL)         /*!< MSTPD20 (Bit 20)                                      */
40593  #define R_MSTP_MSTPCRD_MSTPD20_Msk    (0x100000UL)   /*!< MSTPD20 (Bitfield-Mask: 0x01)                         */
40594  #define R_MSTP_MSTPCRD_MSTPD19_Pos    (19UL)         /*!< MSTPD19 (Bit 19)                                      */
40595  #define R_MSTP_MSTPCRD_MSTPD19_Msk    (0x80000UL)    /*!< MSTPD19 (Bitfield-Mask: 0x01)                         */
40596  #define R_MSTP_MSTPCRD_MSTPD17_Pos    (17UL)         /*!< MSTPD17 (Bit 17)                                      */
40597  #define R_MSTP_MSTPCRD_MSTPD17_Msk    (0x20000UL)    /*!< MSTPD17 (Bitfield-Mask: 0x01)                         */
40598  #define R_MSTP_MSTPCRD_MSTPD16_Pos    (16UL)         /*!< MSTPD16 (Bit 16)                                      */
40599  #define R_MSTP_MSTPCRD_MSTPD16_Msk    (0x10000UL)    /*!< MSTPD16 (Bitfield-Mask: 0x01)                         */
40600  #define R_MSTP_MSTPCRD_MSTPD15_Pos    (15UL)         /*!< MSTPD15 (Bit 15)                                      */
40601  #define R_MSTP_MSTPCRD_MSTPD15_Msk    (0x8000UL)     /*!< MSTPD15 (Bitfield-Mask: 0x01)                         */
40602  #define R_MSTP_MSTPCRD_MSTPD14_Pos    (14UL)         /*!< MSTPD14 (Bit 14)                                      */
40603  #define R_MSTP_MSTPCRD_MSTPD14_Msk    (0x4000UL)     /*!< MSTPD14 (Bitfield-Mask: 0x01)                         */
40604  #define R_MSTP_MSTPCRD_MSTPD13_Pos    (13UL)         /*!< MSTPD13 (Bit 13)                                      */
40605  #define R_MSTP_MSTPCRD_MSTPD13_Msk    (0x2000UL)     /*!< MSTPD13 (Bitfield-Mask: 0x01)                         */
40606  #define R_MSTP_MSTPCRD_MSTPD12_Pos    (12UL)         /*!< MSTPD12 (Bit 12)                                      */
40607  #define R_MSTP_MSTPCRD_MSTPD12_Msk    (0x1000UL)     /*!< MSTPD12 (Bitfield-Mask: 0x01)                         */
40608  #define R_MSTP_MSTPCRD_MSTPD11_Pos    (11UL)         /*!< MSTPD11 (Bit 11)                                      */
40609  #define R_MSTP_MSTPCRD_MSTPD11_Msk    (0x800UL)      /*!< MSTPD11 (Bitfield-Mask: 0x01)                         */
40610  #define R_MSTP_MSTPCRD_MSTPD6_Pos     (6UL)          /*!< MSTPD6 (Bit 6)                                        */
40611  #define R_MSTP_MSTPCRD_MSTPD6_Msk     (0x40UL)       /*!< MSTPD6 (Bitfield-Mask: 0x01)                          */
40612  #define R_MSTP_MSTPCRD_MSTPD5_Pos     (5UL)          /*!< MSTPD5 (Bit 5)                                        */
40613  #define R_MSTP_MSTPCRD_MSTPD5_Msk     (0x20UL)       /*!< MSTPD5 (Bitfield-Mask: 0x01)                          */
40614  #define R_MSTP_MSTPCRD_MSTPD3_Pos     (3UL)          /*!< MSTPD3 (Bit 3)                                        */
40615  #define R_MSTP_MSTPCRD_MSTPD3_Msk     (0x8UL)        /*!< MSTPD3 (Bitfield-Mask: 0x01)                          */
40616  #define R_MSTP_MSTPCRD_MSTPD2_Pos     (2UL)          /*!< MSTPD2 (Bit 2)                                        */
40617  #define R_MSTP_MSTPCRD_MSTPD2_Msk     (0x4UL)        /*!< MSTPD2 (Bitfield-Mask: 0x01)                          */
40618  #define R_MSTP_MSTPCRD_MSTPD1_Pos     (1UL)          /*!< MSTPD1 (Bit 1)                                        */
40619  #define R_MSTP_MSTPCRD_MSTPD1_Msk     (0x2UL)        /*!< MSTPD1 (Bitfield-Mask: 0x01)                          */
40620  #define R_MSTP_MSTPCRD_MSTPD0_Pos     (0UL)          /*!< MSTPD0 (Bit 0)                                        */
40621  #define R_MSTP_MSTPCRD_MSTPD0_Msk     (0x1UL)        /*!< MSTPD0 (Bitfield-Mask: 0x01)                          */
40622 /* ========================================================  MSTPCRE  ======================================================== */
40623  #define R_MSTP_MSTPCRE_MSTPE4_Pos     (4UL)          /*!< MSTPE4 (Bit 4)                                        */
40624  #define R_MSTP_MSTPCRE_MSTPE4_Msk     (0x10UL)       /*!< MSTPE4 (Bitfield-Mask: 0x01)                          */
40625  #define R_MSTP_MSTPCRE_MSTPE14_Pos    (14UL)         /*!< MSTPE14 (Bit 14)                                      */
40626  #define R_MSTP_MSTPCRE_MSTPE14_Msk    (0x4000UL)     /*!< MSTPE14 (Bitfield-Mask: 0x01)                         */
40627  #define R_MSTP_MSTPCRE_MSTPE15_Pos    (15UL)         /*!< MSTPE15 (Bit 15)                                      */
40628  #define R_MSTP_MSTPCRE_MSTPE15_Msk    (0x8000UL)     /*!< MSTPE15 (Bitfield-Mask: 0x01)                         */
40629  #define R_MSTP_MSTPCRE_MSTPE22_Pos    (22UL)         /*!< MSTPE22 (Bit 22)                                      */
40630  #define R_MSTP_MSTPCRE_MSTPE22_Msk    (0x400000UL)   /*!< MSTPE22 (Bitfield-Mask: 0x01)                         */
40631  #define R_MSTP_MSTPCRE_MSTPE23_Pos    (23UL)         /*!< MSTPE23 (Bit 23)                                      */
40632  #define R_MSTP_MSTPCRE_MSTPE23_Msk    (0x800000UL)   /*!< MSTPE23 (Bitfield-Mask: 0x01)                         */
40633  #define R_MSTP_MSTPCRE_MSTPE24_Pos    (24UL)         /*!< MSTPE24 (Bit 24)                                      */
40634  #define R_MSTP_MSTPCRE_MSTPE24_Msk    (0x1000000UL)  /*!< MSTPE24 (Bitfield-Mask: 0x01)                         */
40635  #define R_MSTP_MSTPCRE_MSTPE25_Pos    (25UL)         /*!< MSTPE25 (Bit 25)                                      */
40636  #define R_MSTP_MSTPCRE_MSTPE25_Msk    (0x2000000UL)  /*!< MSTPE25 (Bitfield-Mask: 0x01)                         */
40637  #define R_MSTP_MSTPCRE_MSTPE26_Pos    (26UL)         /*!< MSTPE26 (Bit 26)                                      */
40638  #define R_MSTP_MSTPCRE_MSTPE26_Msk    (0x4000000UL)  /*!< MSTPE26 (Bitfield-Mask: 0x01)                         */
40639  #define R_MSTP_MSTPCRE_MSTPE27_Pos    (27UL)         /*!< MSTPE27 (Bit 27)                                      */
40640  #define R_MSTP_MSTPCRE_MSTPE27_Msk    (0x8000000UL)  /*!< MSTPE27 (Bitfield-Mask: 0x01)                         */
40641  #define R_MSTP_MSTPCRE_MSTPE28_Pos    (28UL)         /*!< MSTPE28 (Bit 28)                                      */
40642  #define R_MSTP_MSTPCRE_MSTPE28_Msk    (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01)                         */
40643  #define R_MSTP_MSTPCRE_MSTPE29_Pos    (29UL)         /*!< MSTPE29 (Bit 29)                                      */
40644  #define R_MSTP_MSTPCRE_MSTPE29_Msk    (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01)                         */
40645  #define R_MSTP_MSTPCRE_MSTPE30_Pos    (30UL)         /*!< MSTPE30 (Bit 30)                                      */
40646  #define R_MSTP_MSTPCRE_MSTPE30_Msk    (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01)                         */
40647  #define R_MSTP_MSTPCRE_MSTPE31_Pos    (31UL)         /*!< MSTPE31 (Bit 31)                                      */
40648  #define R_MSTP_MSTPCRE_MSTPE31_Msk    (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01)                         */
40649 
40650 /* =========================================================================================================================== */
40651 /* ================                                          R_OPAMP                                          ================ */
40652 /* =========================================================================================================================== */
40653 
40654 /* =========================================================  AMPMC  ========================================================= */
40655  #define R_OPAMP_AMPMC_AMPSP_Pos      (7UL)    /*!< AMPSP (Bit 7)                                         */
40656  #define R_OPAMP_AMPMC_AMPSP_Msk      (0x80UL) /*!< AMPSP (Bitfield-Mask: 0x01)                           */
40657  #define R_OPAMP_AMPMC_AMPPC_Pos      (0UL)    /*!< AMPPC (Bit 0)                                         */
40658  #define R_OPAMP_AMPMC_AMPPC_Msk      (0x1UL)  /*!< AMPPC (Bitfield-Mask: 0x01)                           */
40659 /* ========================================================  AMPTRM  ========================================================= */
40660  #define R_OPAMP_AMPTRM_AMPTRM_Pos    (0UL)    /*!< AMPTRM (Bit 0)                                        */
40661  #define R_OPAMP_AMPTRM_AMPTRM_Msk    (0x3UL)  /*!< AMPTRM (Bitfield-Mask: 0x03)                          */
40662 /* ========================================================  AMPTRS  ========================================================= */
40663  #define R_OPAMP_AMPTRS_AMPTRS_Pos    (0UL)    /*!< AMPTRS (Bit 0)                                        */
40664  #define R_OPAMP_AMPTRS_AMPTRS_Msk    (0x3UL)  /*!< AMPTRS (Bitfield-Mask: 0x03)                          */
40665 /* =========================================================  AMPC  ========================================================== */
40666  #define R_OPAMP_AMPC_IREFE_Pos       (7UL)    /*!< IREFE (Bit 7)                                         */
40667  #define R_OPAMP_AMPC_IREFE_Msk       (0x80UL) /*!< IREFE (Bitfield-Mask: 0x01)                           */
40668  #define R_OPAMP_AMPC_AMPE_Pos        (0UL)    /*!< AMPE (Bit 0)                                          */
40669  #define R_OPAMP_AMPC_AMPE_Msk        (0x1UL)  /*!< AMPE (Bitfield-Mask: 0x01)                            */
40670 /* ========================================================  AMPMON  ========================================================= */
40671  #define R_OPAMP_AMPMON_AMPMON_Pos    (0UL)    /*!< AMPMON (Bit 0)                                        */
40672  #define R_OPAMP_AMPMON_AMPMON_Msk    (0x1UL)  /*!< AMPMON (Bitfield-Mask: 0x01)                          */
40673 /* ========================================================  AMPCPC  ========================================================= */
40674  #define R_OPAMP_AMPCPC_PUMPEN_Pos    (0UL)    /*!< PUMPEN (Bit 0)                                        */
40675  #define R_OPAMP_AMPCPC_PUMPEN_Msk    (0x1UL)  /*!< PUMPEN (Bitfield-Mask: 0x01)                          */
40676 /* ========================================================  AMPUOTE  ======================================================== */
40677  #define R_OPAMP_AMPUOTE_AMPTE_Pos    (0UL)    /*!< AMPTE (Bit 0)                                         */
40678  #define R_OPAMP_AMPUOTE_AMPTE_Msk    (0x1UL)  /*!< AMPTE (Bitfield-Mask: 0x01)                           */
40679 
40680 /* =========================================================================================================================== */
40681 /* ================                                           R_PDC                                           ================ */
40682 /* =========================================================================================================================== */
40683 
40684 /* =========================================================  PCCR0  ========================================================= */
40685  #define R_PDC_PCCR0_EDS_Pos       (14UL)         /*!< EDS (Bit 14)                                          */
40686  #define R_PDC_PCCR0_EDS_Msk       (0x4000UL)     /*!< EDS (Bitfield-Mask: 0x01)                             */
40687  #define R_PDC_PCCR0_PCKDIV_Pos    (11UL)         /*!< PCKDIV (Bit 11)                                       */
40688  #define R_PDC_PCCR0_PCKDIV_Msk    (0x3800UL)     /*!< PCKDIV (Bitfield-Mask: 0x07)                          */
40689  #define R_PDC_PCCR0_PCKOE_Pos     (10UL)         /*!< PCKOE (Bit 10)                                        */
40690  #define R_PDC_PCCR0_PCKOE_Msk     (0x400UL)      /*!< PCKOE (Bitfield-Mask: 0x01)                           */
40691  #define R_PDC_PCCR0_HERIE_Pos     (9UL)          /*!< HERIE (Bit 9)                                         */
40692  #define R_PDC_PCCR0_HERIE_Msk     (0x200UL)      /*!< HERIE (Bitfield-Mask: 0x01)                           */
40693  #define R_PDC_PCCR0_VERIE_Pos     (8UL)          /*!< VERIE (Bit 8)                                         */
40694  #define R_PDC_PCCR0_VERIE_Msk     (0x100UL)      /*!< VERIE (Bitfield-Mask: 0x01)                           */
40695  #define R_PDC_PCCR0_UDRIE_Pos     (7UL)          /*!< UDRIE (Bit 7)                                         */
40696  #define R_PDC_PCCR0_UDRIE_Msk     (0x80UL)       /*!< UDRIE (Bitfield-Mask: 0x01)                           */
40697  #define R_PDC_PCCR0_OVIE_Pos      (6UL)          /*!< OVIE (Bit 6)                                          */
40698  #define R_PDC_PCCR0_OVIE_Msk      (0x40UL)       /*!< OVIE (Bitfield-Mask: 0x01)                            */
40699  #define R_PDC_PCCR0_FEIE_Pos      (5UL)          /*!< FEIE (Bit 5)                                          */
40700  #define R_PDC_PCCR0_FEIE_Msk      (0x20UL)       /*!< FEIE (Bitfield-Mask: 0x01)                            */
40701  #define R_PDC_PCCR0_DFIE_Pos      (4UL)          /*!< DFIE (Bit 4)                                          */
40702  #define R_PDC_PCCR0_DFIE_Msk      (0x10UL)       /*!< DFIE (Bitfield-Mask: 0x01)                            */
40703  #define R_PDC_PCCR0_PRST_Pos      (3UL)          /*!< PRST (Bit 3)                                          */
40704  #define R_PDC_PCCR0_PRST_Msk      (0x8UL)        /*!< PRST (Bitfield-Mask: 0x01)                            */
40705  #define R_PDC_PCCR0_HPS_Pos       (2UL)          /*!< HPS (Bit 2)                                           */
40706  #define R_PDC_PCCR0_HPS_Msk       (0x4UL)        /*!< HPS (Bitfield-Mask: 0x01)                             */
40707  #define R_PDC_PCCR0_VPS_Pos       (1UL)          /*!< VPS (Bit 1)                                           */
40708  #define R_PDC_PCCR0_VPS_Msk       (0x2UL)        /*!< VPS (Bitfield-Mask: 0x01)                             */
40709  #define R_PDC_PCCR0_PCKE_Pos      (0UL)          /*!< PCKE (Bit 0)                                          */
40710  #define R_PDC_PCCR0_PCKE_Msk      (0x1UL)        /*!< PCKE (Bitfield-Mask: 0x01)                            */
40711 /* =========================================================  PCCR1  ========================================================= */
40712  #define R_PDC_PCCR1_PCE_Pos       (0UL)          /*!< PCE (Bit 0)                                           */
40713  #define R_PDC_PCCR1_PCE_Msk       (0x1UL)        /*!< PCE (Bitfield-Mask: 0x01)                             */
40714 /* =========================================================  PCSR  ========================================================== */
40715  #define R_PDC_PCSR_HERF_Pos       (6UL)          /*!< HERF (Bit 6)                                          */
40716  #define R_PDC_PCSR_HERF_Msk       (0x40UL)       /*!< HERF (Bitfield-Mask: 0x01)                            */
40717  #define R_PDC_PCSR_VERF_Pos       (5UL)          /*!< VERF (Bit 5)                                          */
40718  #define R_PDC_PCSR_VERF_Msk       (0x20UL)       /*!< VERF (Bitfield-Mask: 0x01)                            */
40719  #define R_PDC_PCSR_UDRF_Pos       (4UL)          /*!< UDRF (Bit 4)                                          */
40720  #define R_PDC_PCSR_UDRF_Msk       (0x10UL)       /*!< UDRF (Bitfield-Mask: 0x01)                            */
40721  #define R_PDC_PCSR_OVRF_Pos       (3UL)          /*!< OVRF (Bit 3)                                          */
40722  #define R_PDC_PCSR_OVRF_Msk       (0x8UL)        /*!< OVRF (Bitfield-Mask: 0x01)                            */
40723  #define R_PDC_PCSR_FEF_Pos        (2UL)          /*!< FEF (Bit 2)                                           */
40724  #define R_PDC_PCSR_FEF_Msk        (0x4UL)        /*!< FEF (Bitfield-Mask: 0x01)                             */
40725  #define R_PDC_PCSR_FEMPF_Pos      (1UL)          /*!< FEMPF (Bit 1)                                         */
40726  #define R_PDC_PCSR_FEMPF_Msk      (0x2UL)        /*!< FEMPF (Bitfield-Mask: 0x01)                           */
40727  #define R_PDC_PCSR_FBSY_Pos       (0UL)          /*!< FBSY (Bit 0)                                          */
40728  #define R_PDC_PCSR_FBSY_Msk       (0x1UL)        /*!< FBSY (Bitfield-Mask: 0x01)                            */
40729 /* ========================================================  PCMONR  ========================================================= */
40730  #define R_PDC_PCMONR_HSYNC_Pos    (1UL)          /*!< HSYNC (Bit 1)                                         */
40731  #define R_PDC_PCMONR_HSYNC_Msk    (0x2UL)        /*!< HSYNC (Bitfield-Mask: 0x01)                           */
40732  #define R_PDC_PCMONR_VSYNC_Pos    (0UL)          /*!< VSYNC (Bit 0)                                         */
40733  #define R_PDC_PCMONR_VSYNC_Msk    (0x1UL)        /*!< VSYNC (Bitfield-Mask: 0x01)                           */
40734 /* =========================================================  PCDR  ========================================================== */
40735  #define R_PDC_PCDR_PCDR_Pos       (0UL)          /*!< PCDR (Bit 0)                                          */
40736  #define R_PDC_PCDR_PCDR_Msk       (0xffffffffUL) /*!< PCDR (Bitfield-Mask: 0xffffffff)                      */
40737 /* ==========================================================  VCR  ========================================================== */
40738  #define R_PDC_VCR_VSZ_Pos         (16UL)         /*!< VSZ (Bit 16)                                          */
40739  #define R_PDC_VCR_VSZ_Msk         (0xfff0000UL)  /*!< VSZ (Bitfield-Mask: 0xfff)                            */
40740  #define R_PDC_VCR_VST_Pos         (0UL)          /*!< VST (Bit 0)                                           */
40741  #define R_PDC_VCR_VST_Msk         (0xfffUL)      /*!< VST (Bitfield-Mask: 0xfff)                            */
40742 /* ==========================================================  HCR  ========================================================== */
40743  #define R_PDC_HCR_HSZ_Pos         (16UL)         /*!< HSZ (Bit 16)                                          */
40744  #define R_PDC_HCR_HSZ_Msk         (0xfff0000UL)  /*!< HSZ (Bitfield-Mask: 0xfff)                            */
40745  #define R_PDC_HCR_HST_Pos         (0UL)          /*!< HST (Bit 0)                                           */
40746  #define R_PDC_HCR_HST_Msk         (0xfffUL)      /*!< HST (Bitfield-Mask: 0xfff)                            */
40747 
40748 /* =========================================================================================================================== */
40749 /* ================                                          R_PORT0                                          ================ */
40750 /* =========================================================================================================================== */
40751 
40752 /* ========================================================  PCNTR1  ========================================================= */
40753  #define R_PORT0_PCNTR1_PODR_Pos    (16UL)         /*!< PODR (Bit 16)                                         */
40754  #define R_PORT0_PCNTR1_PODR_Msk    (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff)                          */
40755  #define R_PORT0_PCNTR1_PDR_Pos     (0UL)          /*!< PDR (Bit 0)                                           */
40756  #define R_PORT0_PCNTR1_PDR_Msk     (0xffffUL)     /*!< PDR (Bitfield-Mask: 0xffff)                           */
40757 /* =========================================================  PODR  ========================================================== */
40758  #define R_PORT0_PODR_PODR_Pos      (0UL)          /*!< PODR (Bit 0)                                          */
40759  #define R_PORT0_PODR_PODR_Msk      (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
40760 /* ==========================================================  PDR  ========================================================== */
40761  #define R_PORT0_PDR_PDR_Pos        (0UL)          /*!< PDR (Bit 0)                                           */
40762  #define R_PORT0_PDR_PDR_Msk        (0x1UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
40763 /* ========================================================  PCNTR2  ========================================================= */
40764  #define R_PORT0_PCNTR2_EIDR_Pos    (16UL)         /*!< EIDR (Bit 16)                                         */
40765  #define R_PORT0_PCNTR2_EIDR_Msk    (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff)                          */
40766  #define R_PORT0_PCNTR2_PIDR_Pos    (0UL)          /*!< PIDR (Bit 0)                                          */
40767  #define R_PORT0_PCNTR2_PIDR_Msk    (0xffffUL)     /*!< PIDR (Bitfield-Mask: 0xffff)                          */
40768 /* =========================================================  EIDR  ========================================================== */
40769  #define R_PORT0_EIDR_EIDR_Pos      (0UL)          /*!< EIDR (Bit 0)                                          */
40770  #define R_PORT0_EIDR_EIDR_Msk      (0x1UL)        /*!< EIDR (Bitfield-Mask: 0x01)                            */
40771 /* =========================================================  PIDR  ========================================================== */
40772  #define R_PORT0_PIDR_PIDR_Pos      (0UL)          /*!< PIDR (Bit 0)                                          */
40773  #define R_PORT0_PIDR_PIDR_Msk      (0x1UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
40774 /* ========================================================  PCNTR3  ========================================================= */
40775  #define R_PORT0_PCNTR3_PORR_Pos    (16UL)         /*!< PORR (Bit 16)                                         */
40776  #define R_PORT0_PCNTR3_PORR_Msk    (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff)                          */
40777  #define R_PORT0_PCNTR3_POSR_Pos    (0UL)          /*!< POSR (Bit 0)                                          */
40778  #define R_PORT0_PCNTR3_POSR_Msk    (0xffffUL)     /*!< POSR (Bitfield-Mask: 0xffff)                          */
40779 /* =========================================================  PORR  ========================================================== */
40780  #define R_PORT0_PORR_PORR_Pos      (0UL)          /*!< PORR (Bit 0)                                          */
40781  #define R_PORT0_PORR_PORR_Msk      (0x1UL)        /*!< PORR (Bitfield-Mask: 0x01)                            */
40782 /* =========================================================  POSR  ========================================================== */
40783  #define R_PORT0_POSR_POSR_Pos      (0UL)          /*!< POSR (Bit 0)                                          */
40784  #define R_PORT0_POSR_POSR_Msk      (0x1UL)        /*!< POSR (Bitfield-Mask: 0x01)                            */
40785 /* ========================================================  PCNTR4  ========================================================= */
40786  #define R_PORT0_PCNTR4_EORR_Pos    (16UL)         /*!< EORR (Bit 16)                                         */
40787  #define R_PORT0_PCNTR4_EORR_Msk    (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff)                          */
40788  #define R_PORT0_PCNTR4_EOSR_Pos    (0UL)          /*!< EOSR (Bit 0)                                          */
40789  #define R_PORT0_PCNTR4_EOSR_Msk    (0xffffUL)     /*!< EOSR (Bitfield-Mask: 0xffff)                          */
40790 /* =========================================================  EORR  ========================================================== */
40791  #define R_PORT0_EORR_EORR_Pos      (0UL)          /*!< EORR (Bit 0)                                          */
40792  #define R_PORT0_EORR_EORR_Msk      (0x1UL)        /*!< EORR (Bitfield-Mask: 0x01)                            */
40793 /* =========================================================  EOSR  ========================================================== */
40794  #define R_PORT0_EOSR_EOSR_Pos      (0UL)          /*!< EOSR (Bit 0)                                          */
40795  #define R_PORT0_EOSR_EOSR_Msk      (0x1UL)        /*!< EOSR (Bitfield-Mask: 0x01)                            */
40796 
40797 /* =========================================================================================================================== */
40798 /* ================                                           R_PFS                                           ================ */
40799 /* =========================================================================================================================== */
40800 
40801 /* =========================================================================================================================== */
40802 /* ================                                          R_PMISC                                          ================ */
40803 /* =========================================================================================================================== */
40804 
40805 /* ========================================================  PFENET  ========================================================= */
40806  #define R_PMISC_PFENET_PHYMODE1_Pos    (5UL)    /*!< PHYMODE1 (Bit 5)                                      */
40807  #define R_PMISC_PFENET_PHYMODE1_Msk    (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01)                        */
40808  #define R_PMISC_PFENET_PHYMODE0_Pos    (4UL)    /*!< PHYMODE0 (Bit 4)                                      */
40809  #define R_PMISC_PFENET_PHYMODE0_Msk    (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01)                        */
40810 /* =========================================================  PWPR  ========================================================== */
40811  #define R_PMISC_PWPR_PFSWE_Pos         (6UL)    /*!< PFSWE (Bit 6)                                         */
40812  #define R_PMISC_PWPR_PFSWE_Msk         (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
40813  #define R_PMISC_PWPR_B0WI_Pos          (7UL)    /*!< B0WI (Bit 7)                                          */
40814  #define R_PMISC_PWPR_B0WI_Msk          (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
40815 /* =========================================================  PWPRS  ========================================================= */
40816  #define R_PMISC_PWPRS_PFSWE_Pos        (6UL)    /*!< PFSWE (Bit 6)                                         */
40817  #define R_PMISC_PWPRS_PFSWE_Msk        (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
40818  #define R_PMISC_PWPRS_B0WI_Pos         (7UL)    /*!< B0WI (Bit 7)                                          */
40819  #define R_PMISC_PWPRS_B0WI_Msk         (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
40820 
40821 /* =========================================================================================================================== */
40822 /* ================                                          R_QSPI                                           ================ */
40823 /* =========================================================================================================================== */
40824 
40825 /* ========================================================  SFMSMD  ========================================================= */
40826  #define R_QSPI_SFMSMD_SFMCCE_Pos       (15UL)         /*!< SFMCCE (Bit 15)                                       */
40827  #define R_QSPI_SFMSMD_SFMCCE_Msk       (0x8000UL)     /*!< SFMCCE (Bitfield-Mask: 0x01)                          */
40828  #define R_QSPI_SFMSMD_SFMOSW_Pos       (11UL)         /*!< SFMOSW (Bit 11)                                       */
40829  #define R_QSPI_SFMSMD_SFMOSW_Msk       (0x800UL)      /*!< SFMOSW (Bitfield-Mask: 0x01)                          */
40830  #define R_QSPI_SFMSMD_SFMOHW_Pos       (10UL)         /*!< SFMOHW (Bit 10)                                       */
40831  #define R_QSPI_SFMSMD_SFMOHW_Msk       (0x400UL)      /*!< SFMOHW (Bitfield-Mask: 0x01)                          */
40832  #define R_QSPI_SFMSMD_SFMOEX_Pos       (9UL)          /*!< SFMOEX (Bit 9)                                        */
40833  #define R_QSPI_SFMSMD_SFMOEX_Msk       (0x200UL)      /*!< SFMOEX (Bitfield-Mask: 0x01)                          */
40834  #define R_QSPI_SFMSMD_SFMMD3_Pos       (8UL)          /*!< SFMMD3 (Bit 8)                                        */
40835  #define R_QSPI_SFMSMD_SFMMD3_Msk       (0x100UL)      /*!< SFMMD3 (Bitfield-Mask: 0x01)                          */
40836  #define R_QSPI_SFMSMD_SFMPAE_Pos       (7UL)          /*!< SFMPAE (Bit 7)                                        */
40837  #define R_QSPI_SFMSMD_SFMPAE_Msk       (0x80UL)       /*!< SFMPAE (Bitfield-Mask: 0x01)                          */
40838  #define R_QSPI_SFMSMD_SFMPFE_Pos       (6UL)          /*!< SFMPFE (Bit 6)                                        */
40839  #define R_QSPI_SFMSMD_SFMPFE_Msk       (0x40UL)       /*!< SFMPFE (Bitfield-Mask: 0x01)                          */
40840  #define R_QSPI_SFMSMD_SFMSE_Pos        (4UL)          /*!< SFMSE (Bit 4)                                         */
40841  #define R_QSPI_SFMSMD_SFMSE_Msk        (0x30UL)       /*!< SFMSE (Bitfield-Mask: 0x03)                           */
40842  #define R_QSPI_SFMSMD_SFMRM_Pos        (0UL)          /*!< SFMRM (Bit 0)                                         */
40843  #define R_QSPI_SFMSMD_SFMRM_Msk        (0x7UL)        /*!< SFMRM (Bitfield-Mask: 0x07)                           */
40844 /* ========================================================  SFMSSC  ========================================================= */
40845  #define R_QSPI_SFMSSC_SFMSLD_Pos       (5UL)          /*!< SFMSLD (Bit 5)                                        */
40846  #define R_QSPI_SFMSSC_SFMSLD_Msk       (0x20UL)       /*!< SFMSLD (Bitfield-Mask: 0x01)                          */
40847  #define R_QSPI_SFMSSC_SFMSHD_Pos       (4UL)          /*!< SFMSHD (Bit 4)                                        */
40848  #define R_QSPI_SFMSSC_SFMSHD_Msk       (0x10UL)       /*!< SFMSHD (Bitfield-Mask: 0x01)                          */
40849  #define R_QSPI_SFMSSC_SFMSW_Pos        (0UL)          /*!< SFMSW (Bit 0)                                         */
40850  #define R_QSPI_SFMSSC_SFMSW_Msk        (0xfUL)        /*!< SFMSW (Bitfield-Mask: 0x0f)                           */
40851 /* ========================================================  SFMSKC  ========================================================= */
40852  #define R_QSPI_SFMSKC_SFMDTY_Pos       (5UL)          /*!< SFMDTY (Bit 5)                                        */
40853  #define R_QSPI_SFMSKC_SFMDTY_Msk       (0x20UL)       /*!< SFMDTY (Bitfield-Mask: 0x01)                          */
40854  #define R_QSPI_SFMSKC_SFMDV_Pos        (0UL)          /*!< SFMDV (Bit 0)                                         */
40855  #define R_QSPI_SFMSKC_SFMDV_Msk        (0x1fUL)       /*!< SFMDV (Bitfield-Mask: 0x1f)                           */
40856 /* ========================================================  SFMSST  ========================================================= */
40857  #define R_QSPI_SFMSST_PFOFF_Pos        (7UL)          /*!< PFOFF (Bit 7)                                         */
40858  #define R_QSPI_SFMSST_PFOFF_Msk        (0x80UL)       /*!< PFOFF (Bitfield-Mask: 0x01)                           */
40859  #define R_QSPI_SFMSST_PFFUL_Pos        (6UL)          /*!< PFFUL (Bit 6)                                         */
40860  #define R_QSPI_SFMSST_PFFUL_Msk        (0x40UL)       /*!< PFFUL (Bitfield-Mask: 0x01)                           */
40861  #define R_QSPI_SFMSST_PFCNT_Pos        (0UL)          /*!< PFCNT (Bit 0)                                         */
40862  #define R_QSPI_SFMSST_PFCNT_Msk        (0x1fUL)       /*!< PFCNT (Bitfield-Mask: 0x1f)                           */
40863 /* ========================================================  SFMCOM  ========================================================= */
40864  #define R_QSPI_SFMCOM_SFMD_Pos         (0UL)          /*!< SFMD (Bit 0)                                          */
40865  #define R_QSPI_SFMCOM_SFMD_Msk         (0xffUL)       /*!< SFMD (Bitfield-Mask: 0xff)                            */
40866 /* ========================================================  SFMCMD  ========================================================= */
40867  #define R_QSPI_SFMCMD_DCOM_Pos         (0UL)          /*!< DCOM (Bit 0)                                          */
40868  #define R_QSPI_SFMCMD_DCOM_Msk         (0x1UL)        /*!< DCOM (Bitfield-Mask: 0x01)                            */
40869 /* ========================================================  SFMCST  ========================================================= */
40870  #define R_QSPI_SFMCST_EROMR_Pos        (7UL)          /*!< EROMR (Bit 7)                                         */
40871  #define R_QSPI_SFMCST_EROMR_Msk        (0x80UL)       /*!< EROMR (Bitfield-Mask: 0x01)                           */
40872  #define R_QSPI_SFMCST_COMBSY_Pos       (0UL)          /*!< COMBSY (Bit 0)                                        */
40873  #define R_QSPI_SFMCST_COMBSY_Msk       (0x1UL)        /*!< COMBSY (Bitfield-Mask: 0x01)                          */
40874 /* ========================================================  SFMSIC  ========================================================= */
40875  #define R_QSPI_SFMSIC_SFMCIC_Pos       (0UL)          /*!< SFMCIC (Bit 0)                                        */
40876  #define R_QSPI_SFMSIC_SFMCIC_Msk       (0xffUL)       /*!< SFMCIC (Bitfield-Mask: 0xff)                          */
40877 /* ========================================================  SFMSAC  ========================================================= */
40878  #define R_QSPI_SFMSAC_SFM4BC_Pos       (4UL)          /*!< SFM4BC (Bit 4)                                        */
40879  #define R_QSPI_SFMSAC_SFM4BC_Msk       (0x10UL)       /*!< SFM4BC (Bitfield-Mask: 0x01)                          */
40880  #define R_QSPI_SFMSAC_SFMAS_Pos        (0UL)          /*!< SFMAS (Bit 0)                                         */
40881  #define R_QSPI_SFMSAC_SFMAS_Msk        (0x3UL)        /*!< SFMAS (Bitfield-Mask: 0x03)                           */
40882 /* ========================================================  SFMSDC  ========================================================= */
40883  #define R_QSPI_SFMSDC_SFMXD_Pos        (8UL)          /*!< SFMXD (Bit 8)                                         */
40884  #define R_QSPI_SFMSDC_SFMXD_Msk        (0xff00UL)     /*!< SFMXD (Bitfield-Mask: 0xff)                           */
40885  #define R_QSPI_SFMSDC_SFMXEN_Pos       (7UL)          /*!< SFMXEN (Bit 7)                                        */
40886  #define R_QSPI_SFMSDC_SFMXEN_Msk       (0x80UL)       /*!< SFMXEN (Bitfield-Mask: 0x01)                          */
40887  #define R_QSPI_SFMSDC_SFMXST_Pos       (6UL)          /*!< SFMXST (Bit 6)                                        */
40888  #define R_QSPI_SFMSDC_SFMXST_Msk       (0x40UL)       /*!< SFMXST (Bitfield-Mask: 0x01)                          */
40889  #define R_QSPI_SFMSDC_SFMDN_Pos        (0UL)          /*!< SFMDN (Bit 0)                                         */
40890  #define R_QSPI_SFMSDC_SFMDN_Msk        (0xfUL)        /*!< SFMDN (Bitfield-Mask: 0x0f)                           */
40891 /* ========================================================  SFMSPC  ========================================================= */
40892  #define R_QSPI_SFMSPC_SFMSDE_Pos       (4UL)          /*!< SFMSDE (Bit 4)                                        */
40893  #define R_QSPI_SFMSPC_SFMSDE_Msk       (0x10UL)       /*!< SFMSDE (Bitfield-Mask: 0x01)                          */
40894  #define R_QSPI_SFMSPC_SFMSPI_Pos       (0UL)          /*!< SFMSPI (Bit 0)                                        */
40895  #define R_QSPI_SFMSPC_SFMSPI_Msk       (0x3UL)        /*!< SFMSPI (Bitfield-Mask: 0x03)                          */
40896 /* ========================================================  SFMPMD  ========================================================= */
40897  #define R_QSPI_SFMPMD_SFMWPL_Pos       (2UL)          /*!< SFMWPL (Bit 2)                                        */
40898  #define R_QSPI_SFMPMD_SFMWPL_Msk       (0x4UL)        /*!< SFMWPL (Bitfield-Mask: 0x01)                          */
40899 /* ========================================================  SFMCNT1  ======================================================== */
40900  #define R_QSPI_SFMCNT1_QSPI_EXT_Pos    (26UL)         /*!< QSPI_EXT (Bit 26)                                     */
40901  #define R_QSPI_SFMCNT1_QSPI_EXT_Msk    (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f)                        */
40902 
40903 /* =========================================================================================================================== */
40904 /* ================                                           R_RTC                                           ================ */
40905 /* =========================================================================================================================== */
40906 
40907 /* ========================================================  R64CNT  ========================================================= */
40908  #define R_RTC_R64CNT_F1HZ_Pos        (6UL)      /*!< F1HZ (Bit 6)                                          */
40909  #define R_RTC_R64CNT_F1HZ_Msk        (0x40UL)   /*!< F1HZ (Bitfield-Mask: 0x01)                            */
40910  #define R_RTC_R64CNT_F2HZ_Pos        (5UL)      /*!< F2HZ (Bit 5)                                          */
40911  #define R_RTC_R64CNT_F2HZ_Msk        (0x20UL)   /*!< F2HZ (Bitfield-Mask: 0x01)                            */
40912  #define R_RTC_R64CNT_F4HZ_Pos        (4UL)      /*!< F4HZ (Bit 4)                                          */
40913  #define R_RTC_R64CNT_F4HZ_Msk        (0x10UL)   /*!< F4HZ (Bitfield-Mask: 0x01)                            */
40914  #define R_RTC_R64CNT_F8HZ_Pos        (3UL)      /*!< F8HZ (Bit 3)                                          */
40915  #define R_RTC_R64CNT_F8HZ_Msk        (0x8UL)    /*!< F8HZ (Bitfield-Mask: 0x01)                            */
40916  #define R_RTC_R64CNT_F16HZ_Pos       (2UL)      /*!< F16HZ (Bit 2)                                         */
40917  #define R_RTC_R64CNT_F16HZ_Msk       (0x4UL)    /*!< F16HZ (Bitfield-Mask: 0x01)                           */
40918  #define R_RTC_R64CNT_F32HZ_Pos       (1UL)      /*!< F32HZ (Bit 1)                                         */
40919  #define R_RTC_R64CNT_F32HZ_Msk       (0x2UL)    /*!< F32HZ (Bitfield-Mask: 0x01)                           */
40920  #define R_RTC_R64CNT_F64HZ_Pos       (0UL)      /*!< F64HZ (Bit 0)                                         */
40921  #define R_RTC_R64CNT_F64HZ_Msk       (0x1UL)    /*!< F64HZ (Bitfield-Mask: 0x01)                           */
40922 /* ========================================================  RSECCNT  ======================================================== */
40923  #define R_RTC_RSECCNT_SEC10_Pos      (4UL)      /*!< SEC10 (Bit 4)                                         */
40924  #define R_RTC_RSECCNT_SEC10_Msk      (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
40925  #define R_RTC_RSECCNT_SEC1_Pos       (0UL)      /*!< SEC1 (Bit 0)                                          */
40926  #define R_RTC_RSECCNT_SEC1_Msk       (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
40927 /* =========================================================  BCNT0  ========================================================= */
40928  #define R_RTC_BCNT0_BCNT0_Pos        (0UL)      /*!< BCNT0 (Bit 0)                                         */
40929  #define R_RTC_BCNT0_BCNT0_Msk        (0xffUL)   /*!< BCNT0 (Bitfield-Mask: 0xff)                           */
40930 /* ========================================================  RMINCNT  ======================================================== */
40931  #define R_RTC_RMINCNT_MIN10_Pos      (4UL)      /*!< MIN10 (Bit 4)                                         */
40932  #define R_RTC_RMINCNT_MIN10_Msk      (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
40933  #define R_RTC_RMINCNT_MIN1_Pos       (0UL)      /*!< MIN1 (Bit 0)                                          */
40934  #define R_RTC_RMINCNT_MIN1_Msk       (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
40935 /* =========================================================  BCNT1  ========================================================= */
40936  #define R_RTC_BCNT1_BCNT1_Pos        (0UL)      /*!< BCNT1 (Bit 0)                                         */
40937  #define R_RTC_BCNT1_BCNT1_Msk        (0xffUL)   /*!< BCNT1 (Bitfield-Mask: 0xff)                           */
40938 /* ========================================================  RHRCNT  ========================================================= */
40939  #define R_RTC_RHRCNT_PM_Pos          (6UL)      /*!< PM (Bit 6)                                            */
40940  #define R_RTC_RHRCNT_PM_Msk          (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
40941  #define R_RTC_RHRCNT_HR10_Pos        (4UL)      /*!< HR10 (Bit 4)                                          */
40942  #define R_RTC_RHRCNT_HR10_Msk        (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
40943  #define R_RTC_RHRCNT_HR1_Pos         (0UL)      /*!< HR1 (Bit 0)                                           */
40944  #define R_RTC_RHRCNT_HR1_Msk         (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
40945 /* =========================================================  BCNT2  ========================================================= */
40946  #define R_RTC_BCNT2_BCNT2_Pos        (0UL)      /*!< BCNT2 (Bit 0)                                         */
40947  #define R_RTC_BCNT2_BCNT2_Msk        (0xffUL)   /*!< BCNT2 (Bitfield-Mask: 0xff)                           */
40948 /* ========================================================  RWKCNT  ========================================================= */
40949  #define R_RTC_RWKCNT_DAYW_Pos        (0UL)      /*!< DAYW (Bit 0)                                          */
40950  #define R_RTC_RWKCNT_DAYW_Msk        (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
40951 /* =========================================================  BCNT3  ========================================================= */
40952  #define R_RTC_BCNT3_BCNT3_Pos        (0UL)      /*!< BCNT3 (Bit 0)                                         */
40953  #define R_RTC_BCNT3_BCNT3_Msk        (0xffUL)   /*!< BCNT3 (Bitfield-Mask: 0xff)                           */
40954 /* ========================================================  RDAYCNT  ======================================================== */
40955  #define R_RTC_RDAYCNT_DATE10_Pos     (4UL)      /*!< DATE10 (Bit 4)                                        */
40956  #define R_RTC_RDAYCNT_DATE10_Msk     (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
40957  #define R_RTC_RDAYCNT_DATE1_Pos      (0UL)      /*!< DATE1 (Bit 0)                                         */
40958  #define R_RTC_RDAYCNT_DATE1_Msk      (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
40959 /* ========================================================  RMONCNT  ======================================================== */
40960  #define R_RTC_RMONCNT_MON10_Pos      (4UL)      /*!< MON10 (Bit 4)                                         */
40961  #define R_RTC_RMONCNT_MON10_Msk      (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
40962  #define R_RTC_RMONCNT_MON1_Pos       (0UL)      /*!< MON1 (Bit 0)                                          */
40963  #define R_RTC_RMONCNT_MON1_Msk       (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
40964 /* ========================================================  RYRCNT  ========================================================= */
40965  #define R_RTC_RYRCNT_YR10_Pos        (4UL)      /*!< YR10 (Bit 4)                                          */
40966  #define R_RTC_RYRCNT_YR10_Msk        (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
40967  #define R_RTC_RYRCNT_YR1_Pos         (0UL)      /*!< YR1 (Bit 0)                                           */
40968  #define R_RTC_RYRCNT_YR1_Msk         (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
40969 /* ========================================================  RSECAR  ========================================================= */
40970  #define R_RTC_RSECAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
40971  #define R_RTC_RSECAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
40972  #define R_RTC_RSECAR_SEC10_Pos       (4UL)      /*!< SEC10 (Bit 4)                                         */
40973  #define R_RTC_RSECAR_SEC10_Msk       (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
40974  #define R_RTC_RSECAR_SEC1_Pos        (0UL)      /*!< SEC1 (Bit 0)                                          */
40975  #define R_RTC_RSECAR_SEC1_Msk        (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
40976 /* ========================================================  BCNT0AR  ======================================================== */
40977  #define R_RTC_BCNT0AR_BCNT0AR_Pos    (0UL)      /*!< BCNT0AR (Bit 0)                                       */
40978  #define R_RTC_BCNT0AR_BCNT0AR_Msk    (0xffUL)   /*!< BCNT0AR (Bitfield-Mask: 0xff)                         */
40979 /* ========================================================  RMINAR  ========================================================= */
40980  #define R_RTC_RMINAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
40981  #define R_RTC_RMINAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
40982  #define R_RTC_RMINAR_MIN10_Pos       (4UL)      /*!< MIN10 (Bit 4)                                         */
40983  #define R_RTC_RMINAR_MIN10_Msk       (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
40984  #define R_RTC_RMINAR_MIN1_Pos        (0UL)      /*!< MIN1 (Bit 0)                                          */
40985  #define R_RTC_RMINAR_MIN1_Msk        (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
40986 /* ========================================================  BCNT1AR  ======================================================== */
40987  #define R_RTC_BCNT1AR_BCNT1AR_Pos    (0UL)      /*!< BCNT1AR (Bit 0)                                       */
40988  #define R_RTC_BCNT1AR_BCNT1AR_Msk    (0xffUL)   /*!< BCNT1AR (Bitfield-Mask: 0xff)                         */
40989 /* =========================================================  RHRAR  ========================================================= */
40990  #define R_RTC_RHRAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
40991  #define R_RTC_RHRAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
40992  #define R_RTC_RHRAR_PM_Pos           (6UL)      /*!< PM (Bit 6)                                            */
40993  #define R_RTC_RHRAR_PM_Msk           (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
40994  #define R_RTC_RHRAR_HR10_Pos         (4UL)      /*!< HR10 (Bit 4)                                          */
40995  #define R_RTC_RHRAR_HR10_Msk         (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
40996  #define R_RTC_RHRAR_HR1_Pos          (0UL)      /*!< HR1 (Bit 0)                                           */
40997  #define R_RTC_RHRAR_HR1_Msk          (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
40998 /* ========================================================  BCNT2AR  ======================================================== */
40999  #define R_RTC_BCNT2AR_BCNT2AR_Pos    (0UL)      /*!< BCNT2AR (Bit 0)                                       */
41000  #define R_RTC_BCNT2AR_BCNT2AR_Msk    (0xffUL)   /*!< BCNT2AR (Bitfield-Mask: 0xff)                         */
41001 /* =========================================================  RWKAR  ========================================================= */
41002  #define R_RTC_RWKAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
41003  #define R_RTC_RWKAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
41004  #define R_RTC_RWKAR_DAYW_Pos         (0UL)      /*!< DAYW (Bit 0)                                          */
41005  #define R_RTC_RWKAR_DAYW_Msk         (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
41006 /* ========================================================  BCNT3AR  ======================================================== */
41007  #define R_RTC_BCNT3AR_BCNT3AR_Pos    (0UL)      /*!< BCNT3AR (Bit 0)                                       */
41008  #define R_RTC_BCNT3AR_BCNT3AR_Msk    (0xffUL)   /*!< BCNT3AR (Bitfield-Mask: 0xff)                         */
41009 /* ========================================================  RDAYAR  ========================================================= */
41010  #define R_RTC_RDAYAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
41011  #define R_RTC_RDAYAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
41012  #define R_RTC_RDAYAR_DATE10_Pos      (4UL)      /*!< DATE10 (Bit 4)                                        */
41013  #define R_RTC_RDAYAR_DATE10_Msk      (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
41014  #define R_RTC_RDAYAR_DATE1_Pos       (0UL)      /*!< DATE1 (Bit 0)                                         */
41015  #define R_RTC_RDAYAR_DATE1_Msk       (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
41016 /* =======================================================  BCNT0AER  ======================================================== */
41017  #define R_RTC_BCNT0AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
41018  #define R_RTC_BCNT0AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
41019 /* ========================================================  RMONAR  ========================================================= */
41020  #define R_RTC_RMONAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
41021  #define R_RTC_RMONAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
41022  #define R_RTC_RMONAR_MON10_Pos       (4UL)      /*!< MON10 (Bit 4)                                         */
41023  #define R_RTC_RMONAR_MON10_Msk       (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
41024  #define R_RTC_RMONAR_MON1_Pos        (0UL)      /*!< MON1 (Bit 0)                                          */
41025  #define R_RTC_RMONAR_MON1_Msk        (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
41026 /* =======================================================  BCNT1AER  ======================================================== */
41027  #define R_RTC_BCNT1AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
41028  #define R_RTC_BCNT1AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
41029 /* =========================================================  RYRAR  ========================================================= */
41030  #define R_RTC_RYRAR_YR10_Pos         (4UL)      /*!< YR10 (Bit 4)                                          */
41031  #define R_RTC_RYRAR_YR10_Msk         (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
41032  #define R_RTC_RYRAR_YR1_Pos          (0UL)      /*!< YR1 (Bit 0)                                           */
41033  #define R_RTC_RYRAR_YR1_Msk          (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
41034 /* =======================================================  BCNT2AER  ======================================================== */
41035  #define R_RTC_BCNT2AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
41036  #define R_RTC_BCNT2AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
41037 /* ========================================================  RYRAREN  ======================================================== */
41038  #define R_RTC_RYRAREN_ENB_Pos        (7UL)      /*!< ENB (Bit 7)                                           */
41039  #define R_RTC_RYRAREN_ENB_Msk        (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
41040 /* =======================================================  BCNT3AER  ======================================================== */
41041  #define R_RTC_BCNT3AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
41042  #define R_RTC_BCNT3AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
41043 /* =========================================================  RCR1  ========================================================== */
41044  #define R_RTC_RCR1_PES_Pos           (4UL)      /*!< PES (Bit 4)                                           */
41045  #define R_RTC_RCR1_PES_Msk           (0xf0UL)   /*!< PES (Bitfield-Mask: 0x0f)                             */
41046  #define R_RTC_RCR1_RTCOS_Pos         (3UL)      /*!< RTCOS (Bit 3)                                         */
41047  #define R_RTC_RCR1_RTCOS_Msk         (0x8UL)    /*!< RTCOS (Bitfield-Mask: 0x01)                           */
41048  #define R_RTC_RCR1_PIE_Pos           (2UL)      /*!< PIE (Bit 2)                                           */
41049  #define R_RTC_RCR1_PIE_Msk           (0x4UL)    /*!< PIE (Bitfield-Mask: 0x01)                             */
41050  #define R_RTC_RCR1_CIE_Pos           (1UL)      /*!< CIE (Bit 1)                                           */
41051  #define R_RTC_RCR1_CIE_Msk           (0x2UL)    /*!< CIE (Bitfield-Mask: 0x01)                             */
41052  #define R_RTC_RCR1_AIE_Pos           (0UL)      /*!< AIE (Bit 0)                                           */
41053  #define R_RTC_RCR1_AIE_Msk           (0x1UL)    /*!< AIE (Bitfield-Mask: 0x01)                             */
41054 /* =========================================================  RCR2  ========================================================== */
41055  #define R_RTC_RCR2_CNTMD_Pos         (7UL)      /*!< CNTMD (Bit 7)                                         */
41056  #define R_RTC_RCR2_CNTMD_Msk         (0x80UL)   /*!< CNTMD (Bitfield-Mask: 0x01)                           */
41057  #define R_RTC_RCR2_HR24_Pos          (6UL)      /*!< HR24 (Bit 6)                                          */
41058  #define R_RTC_RCR2_HR24_Msk          (0x40UL)   /*!< HR24 (Bitfield-Mask: 0x01)                            */
41059  #define R_RTC_RCR2_AADJP_Pos         (5UL)      /*!< AADJP (Bit 5)                                         */
41060  #define R_RTC_RCR2_AADJP_Msk         (0x20UL)   /*!< AADJP (Bitfield-Mask: 0x01)                           */
41061  #define R_RTC_RCR2_AADJE_Pos         (4UL)      /*!< AADJE (Bit 4)                                         */
41062  #define R_RTC_RCR2_AADJE_Msk         (0x10UL)   /*!< AADJE (Bitfield-Mask: 0x01)                           */
41063  #define R_RTC_RCR2_RTCOE_Pos         (3UL)      /*!< RTCOE (Bit 3)                                         */
41064  #define R_RTC_RCR2_RTCOE_Msk         (0x8UL)    /*!< RTCOE (Bitfield-Mask: 0x01)                           */
41065  #define R_RTC_RCR2_ADJ30_Pos         (2UL)      /*!< ADJ30 (Bit 2)                                         */
41066  #define R_RTC_RCR2_ADJ30_Msk         (0x4UL)    /*!< ADJ30 (Bitfield-Mask: 0x01)                           */
41067  #define R_RTC_RCR2_RESET_Pos         (1UL)      /*!< RESET (Bit 1)                                         */
41068  #define R_RTC_RCR2_RESET_Msk         (0x2UL)    /*!< RESET (Bitfield-Mask: 0x01)                           */
41069  #define R_RTC_RCR2_START_Pos         (0UL)      /*!< START (Bit 0)                                         */
41070  #define R_RTC_RCR2_START_Msk         (0x1UL)    /*!< START (Bitfield-Mask: 0x01)                           */
41071 /* =========================================================  RCR4  ========================================================== */
41072  #define R_RTC_RCR4_RCKSEL_Pos        (0UL)      /*!< RCKSEL (Bit 0)                                        */
41073  #define R_RTC_RCR4_RCKSEL_Msk        (0x1UL)    /*!< RCKSEL (Bitfield-Mask: 0x01)                          */
41074  #define R_RTC_RCR4_ROPSEL_Pos        (7UL)      /*!< ROPSEL (Bit 7)                                        */
41075  #define R_RTC_RCR4_ROPSEL_Msk        (0x80UL)   /*!< ROPSEL (Bitfield-Mask: 0x01)                          */
41076 /* =========================================================  RFRH  ========================================================== */
41077  #define R_RTC_RFRH_RFC16_Pos         (0UL)      /*!< RFC16 (Bit 0)                                         */
41078  #define R_RTC_RFRH_RFC16_Msk         (0x1UL)    /*!< RFC16 (Bitfield-Mask: 0x01)                           */
41079 /* =========================================================  RFRL  ========================================================== */
41080  #define R_RTC_RFRL_RFC_Pos           (0UL)      /*!< RFC (Bit 0)                                           */
41081  #define R_RTC_RFRL_RFC_Msk           (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff)                           */
41082 /* =========================================================  RADJ  ========================================================== */
41083  #define R_RTC_RADJ_PMADJ_Pos         (6UL)      /*!< PMADJ (Bit 6)                                         */
41084  #define R_RTC_RADJ_PMADJ_Msk         (0xc0UL)   /*!< PMADJ (Bitfield-Mask: 0x03)                           */
41085  #define R_RTC_RADJ_ADJ_Pos           (0UL)      /*!< ADJ (Bit 0)                                           */
41086  #define R_RTC_RADJ_ADJ_Msk           (0x3fUL)   /*!< ADJ (Bitfield-Mask: 0x3f)                             */
41087 
41088 /* =========================================================================================================================== */
41089 /* ================                                          R_SCI0                                           ================ */
41090 /* =========================================================================================================================== */
41091 
41092 /* ==========================================================  SMR  ========================================================== */
41093  #define R_SCI0_SMR_CM_Pos              (7UL)      /*!< CM (Bit 7)                                            */
41094  #define R_SCI0_SMR_CM_Msk              (0x80UL)   /*!< CM (Bitfield-Mask: 0x01)                              */
41095  #define R_SCI0_SMR_CHR_Pos             (6UL)      /*!< CHR (Bit 6)                                           */
41096  #define R_SCI0_SMR_CHR_Msk             (0x40UL)   /*!< CHR (Bitfield-Mask: 0x01)                             */
41097  #define R_SCI0_SMR_PE_Pos              (5UL)      /*!< PE (Bit 5)                                            */
41098  #define R_SCI0_SMR_PE_Msk              (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
41099  #define R_SCI0_SMR_PM_Pos              (4UL)      /*!< PM (Bit 4)                                            */
41100  #define R_SCI0_SMR_PM_Msk              (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
41101  #define R_SCI0_SMR_STOP_Pos            (3UL)      /*!< STOP (Bit 3)                                          */
41102  #define R_SCI0_SMR_STOP_Msk            (0x8UL)    /*!< STOP (Bitfield-Mask: 0x01)                            */
41103  #define R_SCI0_SMR_MP_Pos              (2UL)      /*!< MP (Bit 2)                                            */
41104  #define R_SCI0_SMR_MP_Msk              (0x4UL)    /*!< MP (Bitfield-Mask: 0x01)                              */
41105  #define R_SCI0_SMR_CKS_Pos             (0UL)      /*!< CKS (Bit 0)                                           */
41106  #define R_SCI0_SMR_CKS_Msk             (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
41107 /* =======================================================  SMR_SMCI  ======================================================== */
41108  #define R_SCI0_SMR_SMCI_GM_Pos         (7UL)      /*!< GM (Bit 7)                                            */
41109  #define R_SCI0_SMR_SMCI_GM_Msk         (0x80UL)   /*!< GM (Bitfield-Mask: 0x01)                              */
41110  #define R_SCI0_SMR_SMCI_BLK_Pos        (6UL)      /*!< BLK (Bit 6)                                           */
41111  #define R_SCI0_SMR_SMCI_BLK_Msk        (0x40UL)   /*!< BLK (Bitfield-Mask: 0x01)                             */
41112  #define R_SCI0_SMR_SMCI_PE_Pos         (5UL)      /*!< PE (Bit 5)                                            */
41113  #define R_SCI0_SMR_SMCI_PE_Msk         (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
41114  #define R_SCI0_SMR_SMCI_PM_Pos         (4UL)      /*!< PM (Bit 4)                                            */
41115  #define R_SCI0_SMR_SMCI_PM_Msk         (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
41116  #define R_SCI0_SMR_SMCI_BCP_Pos        (2UL)      /*!< BCP (Bit 2)                                           */
41117  #define R_SCI0_SMR_SMCI_BCP_Msk        (0xcUL)    /*!< BCP (Bitfield-Mask: 0x03)                             */
41118  #define R_SCI0_SMR_SMCI_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
41119  #define R_SCI0_SMR_SMCI_CKS_Msk        (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
41120 /* ==========================================================  BRR  ========================================================== */
41121  #define R_SCI0_BRR_BRR_Pos             (0UL)      /*!< BRR (Bit 0)                                           */
41122  #define R_SCI0_BRR_BRR_Msk             (0xffUL)   /*!< BRR (Bitfield-Mask: 0xff)                             */
41123 /* ==========================================================  SCR  ========================================================== */
41124  #define R_SCI0_SCR_TIE_Pos             (7UL)      /*!< TIE (Bit 7)                                           */
41125  #define R_SCI0_SCR_TIE_Msk             (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
41126  #define R_SCI0_SCR_RIE_Pos             (6UL)      /*!< RIE (Bit 6)                                           */
41127  #define R_SCI0_SCR_RIE_Msk             (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
41128  #define R_SCI0_SCR_TE_Pos              (5UL)      /*!< TE (Bit 5)                                            */
41129  #define R_SCI0_SCR_TE_Msk              (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
41130  #define R_SCI0_SCR_RE_Pos              (4UL)      /*!< RE (Bit 4)                                            */
41131  #define R_SCI0_SCR_RE_Msk              (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
41132  #define R_SCI0_SCR_MPIE_Pos            (3UL)      /*!< MPIE (Bit 3)                                          */
41133  #define R_SCI0_SCR_MPIE_Msk            (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
41134  #define R_SCI0_SCR_TEIE_Pos            (2UL)      /*!< TEIE (Bit 2)                                          */
41135  #define R_SCI0_SCR_TEIE_Msk            (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
41136  #define R_SCI0_SCR_CKE_Pos             (0UL)      /*!< CKE (Bit 0)                                           */
41137  #define R_SCI0_SCR_CKE_Msk             (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
41138 /* =======================================================  SCR_SMCI  ======================================================== */
41139  #define R_SCI0_SCR_SMCI_TIE_Pos        (7UL)      /*!< TIE (Bit 7)                                           */
41140  #define R_SCI0_SCR_SMCI_TIE_Msk        (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
41141  #define R_SCI0_SCR_SMCI_RIE_Pos        (6UL)      /*!< RIE (Bit 6)                                           */
41142  #define R_SCI0_SCR_SMCI_RIE_Msk        (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
41143  #define R_SCI0_SCR_SMCI_TE_Pos         (5UL)      /*!< TE (Bit 5)                                            */
41144  #define R_SCI0_SCR_SMCI_TE_Msk         (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
41145  #define R_SCI0_SCR_SMCI_RE_Pos         (4UL)      /*!< RE (Bit 4)                                            */
41146  #define R_SCI0_SCR_SMCI_RE_Msk         (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
41147  #define R_SCI0_SCR_SMCI_MPIE_Pos       (3UL)      /*!< MPIE (Bit 3)                                          */
41148  #define R_SCI0_SCR_SMCI_MPIE_Msk       (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
41149  #define R_SCI0_SCR_SMCI_TEIE_Pos       (2UL)      /*!< TEIE (Bit 2)                                          */
41150  #define R_SCI0_SCR_SMCI_TEIE_Msk       (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
41151  #define R_SCI0_SCR_SMCI_CKE_Pos        (0UL)      /*!< CKE (Bit 0)                                           */
41152  #define R_SCI0_SCR_SMCI_CKE_Msk        (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
41153 /* ==========================================================  TDR  ========================================================== */
41154  #define R_SCI0_TDR_TDR_Pos             (0UL)      /*!< TDR (Bit 0)                                           */
41155  #define R_SCI0_TDR_TDR_Msk             (0xffUL)   /*!< TDR (Bitfield-Mask: 0xff)                             */
41156 /* ==========================================================  SSR  ========================================================== */
41157  #define R_SCI0_SSR_TDRE_Pos            (7UL)      /*!< TDRE (Bit 7)                                          */
41158  #define R_SCI0_SSR_TDRE_Msk            (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
41159  #define R_SCI0_SSR_RDRF_Pos            (6UL)      /*!< RDRF (Bit 6)                                          */
41160  #define R_SCI0_SSR_RDRF_Msk            (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
41161  #define R_SCI0_SSR_ORER_Pos            (5UL)      /*!< ORER (Bit 5)                                          */
41162  #define R_SCI0_SSR_ORER_Msk            (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
41163  #define R_SCI0_SSR_FER_Pos             (4UL)      /*!< FER (Bit 4)                                           */
41164  #define R_SCI0_SSR_FER_Msk             (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
41165  #define R_SCI0_SSR_PER_Pos             (3UL)      /*!< PER (Bit 3)                                           */
41166  #define R_SCI0_SSR_PER_Msk             (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
41167  #define R_SCI0_SSR_TEND_Pos            (2UL)      /*!< TEND (Bit 2)                                          */
41168  #define R_SCI0_SSR_TEND_Msk            (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
41169  #define R_SCI0_SSR_MPB_Pos             (1UL)      /*!< MPB (Bit 1)                                           */
41170  #define R_SCI0_SSR_MPB_Msk             (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
41171  #define R_SCI0_SSR_MPBT_Pos            (0UL)      /*!< MPBT (Bit 0)                                          */
41172  #define R_SCI0_SSR_MPBT_Msk            (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
41173 /* =======================================================  SSR_FIFO  ======================================================== */
41174  #define R_SCI0_SSR_FIFO_TDFE_Pos       (7UL)      /*!< TDFE (Bit 7)                                          */
41175  #define R_SCI0_SSR_FIFO_TDFE_Msk       (0x80UL)   /*!< TDFE (Bitfield-Mask: 0x01)                            */
41176  #define R_SCI0_SSR_FIFO_RDF_Pos        (6UL)      /*!< RDF (Bit 6)                                           */
41177  #define R_SCI0_SSR_FIFO_RDF_Msk        (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
41178  #define R_SCI0_SSR_FIFO_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
41179  #define R_SCI0_SSR_FIFO_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
41180  #define R_SCI0_SSR_FIFO_FER_Pos        (4UL)      /*!< FER (Bit 4)                                           */
41181  #define R_SCI0_SSR_FIFO_FER_Msk        (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
41182  #define R_SCI0_SSR_FIFO_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
41183  #define R_SCI0_SSR_FIFO_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
41184  #define R_SCI0_SSR_FIFO_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
41185  #define R_SCI0_SSR_FIFO_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
41186  #define R_SCI0_SSR_FIFO_DR_Pos         (0UL)      /*!< DR (Bit 0)                                            */
41187  #define R_SCI0_SSR_FIFO_DR_Msk         (0x1UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
41188 /* =======================================================  SSR_SMCI  ======================================================== */
41189  #define R_SCI0_SSR_SMCI_TDRE_Pos       (7UL)      /*!< TDRE (Bit 7)                                          */
41190  #define R_SCI0_SSR_SMCI_TDRE_Msk       (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
41191  #define R_SCI0_SSR_SMCI_RDRF_Pos       (6UL)      /*!< RDRF (Bit 6)                                          */
41192  #define R_SCI0_SSR_SMCI_RDRF_Msk       (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
41193  #define R_SCI0_SSR_SMCI_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
41194  #define R_SCI0_SSR_SMCI_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
41195  #define R_SCI0_SSR_SMCI_ERS_Pos        (4UL)      /*!< ERS (Bit 4)                                           */
41196  #define R_SCI0_SSR_SMCI_ERS_Msk        (0x10UL)   /*!< ERS (Bitfield-Mask: 0x01)                             */
41197  #define R_SCI0_SSR_SMCI_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
41198  #define R_SCI0_SSR_SMCI_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
41199  #define R_SCI0_SSR_SMCI_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
41200  #define R_SCI0_SSR_SMCI_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
41201  #define R_SCI0_SSR_SMCI_MPB_Pos        (1UL)      /*!< MPB (Bit 1)                                           */
41202  #define R_SCI0_SSR_SMCI_MPB_Msk        (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
41203  #define R_SCI0_SSR_SMCI_MPBT_Pos       (0UL)      /*!< MPBT (Bit 0)                                          */
41204  #define R_SCI0_SSR_SMCI_MPBT_Msk       (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
41205 /* ==========================================================  RDR  ========================================================== */
41206  #define R_SCI0_RDR_RDR_Pos             (0UL)      /*!< RDR (Bit 0)                                           */
41207  #define R_SCI0_RDR_RDR_Msk             (0xffUL)   /*!< RDR (Bitfield-Mask: 0xff)                             */
41208 /* =========================================================  SCMR  ========================================================== */
41209  #define R_SCI0_SCMR_BCP2_Pos           (7UL)      /*!< BCP2 (Bit 7)                                          */
41210  #define R_SCI0_SCMR_BCP2_Msk           (0x80UL)   /*!< BCP2 (Bitfield-Mask: 0x01)                            */
41211  #define R_SCI0_SCMR_CHR1_Pos           (4UL)      /*!< CHR1 (Bit 4)                                          */
41212  #define R_SCI0_SCMR_CHR1_Msk           (0x10UL)   /*!< CHR1 (Bitfield-Mask: 0x01)                            */
41213  #define R_SCI0_SCMR_SDIR_Pos           (3UL)      /*!< SDIR (Bit 3)                                          */
41214  #define R_SCI0_SCMR_SDIR_Msk           (0x8UL)    /*!< SDIR (Bitfield-Mask: 0x01)                            */
41215  #define R_SCI0_SCMR_SINV_Pos           (2UL)      /*!< SINV (Bit 2)                                          */
41216  #define R_SCI0_SCMR_SINV_Msk           (0x4UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
41217  #define R_SCI0_SCMR_SMIF_Pos           (0UL)      /*!< SMIF (Bit 0)                                          */
41218  #define R_SCI0_SCMR_SMIF_Msk           (0x1UL)    /*!< SMIF (Bitfield-Mask: 0x01)                            */
41219 /* =========================================================  SEMR  ========================================================== */
41220  #define R_SCI0_SEMR_RXDESEL_Pos        (7UL)      /*!< RXDESEL (Bit 7)                                       */
41221  #define R_SCI0_SEMR_RXDESEL_Msk        (0x80UL)   /*!< RXDESEL (Bitfield-Mask: 0x01)                         */
41222  #define R_SCI0_SEMR_BGDM_Pos           (6UL)      /*!< BGDM (Bit 6)                                          */
41223  #define R_SCI0_SEMR_BGDM_Msk           (0x40UL)   /*!< BGDM (Bitfield-Mask: 0x01)                            */
41224  #define R_SCI0_SEMR_NFEN_Pos           (5UL)      /*!< NFEN (Bit 5)                                          */
41225  #define R_SCI0_SEMR_NFEN_Msk           (0x20UL)   /*!< NFEN (Bitfield-Mask: 0x01)                            */
41226  #define R_SCI0_SEMR_ABCS_Pos           (4UL)      /*!< ABCS (Bit 4)                                          */
41227  #define R_SCI0_SEMR_ABCS_Msk           (0x10UL)   /*!< ABCS (Bitfield-Mask: 0x01)                            */
41228  #define R_SCI0_SEMR_ABCSE_Pos          (3UL)      /*!< ABCSE (Bit 3)                                         */
41229  #define R_SCI0_SEMR_ABCSE_Msk          (0x8UL)    /*!< ABCSE (Bitfield-Mask: 0x01)                           */
41230  #define R_SCI0_SEMR_BRME_Pos           (2UL)      /*!< BRME (Bit 2)                                          */
41231  #define R_SCI0_SEMR_BRME_Msk           (0x4UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
41232  #define R_SCI0_SEMR_PADIS_Pos          (1UL)      /*!< PADIS (Bit 1)                                         */
41233  #define R_SCI0_SEMR_PADIS_Msk          (0x2UL)    /*!< PADIS (Bitfield-Mask: 0x01)                           */
41234  #define R_SCI0_SEMR_ACS0_Pos           (0UL)      /*!< ACS0 (Bit 0)                                          */
41235  #define R_SCI0_SEMR_ACS0_Msk           (0x1UL)    /*!< ACS0 (Bitfield-Mask: 0x01)                            */
41236 /* =========================================================  SNFR  ========================================================== */
41237  #define R_SCI0_SNFR_NFCS_Pos           (0UL)      /*!< NFCS (Bit 0)                                          */
41238  #define R_SCI0_SNFR_NFCS_Msk           (0x7UL)    /*!< NFCS (Bitfield-Mask: 0x07)                            */
41239 /* =========================================================  SIMR1  ========================================================= */
41240  #define R_SCI0_SIMR1_IICDL_Pos         (3UL)      /*!< IICDL (Bit 3)                                         */
41241  #define R_SCI0_SIMR1_IICDL_Msk         (0xf8UL)   /*!< IICDL (Bitfield-Mask: 0x1f)                           */
41242  #define R_SCI0_SIMR1_IICM_Pos          (0UL)      /*!< IICM (Bit 0)                                          */
41243  #define R_SCI0_SIMR1_IICM_Msk          (0x1UL)    /*!< IICM (Bitfield-Mask: 0x01)                            */
41244 /* =========================================================  SIMR2  ========================================================= */
41245  #define R_SCI0_SIMR2_IICACKT_Pos       (5UL)      /*!< IICACKT (Bit 5)                                       */
41246  #define R_SCI0_SIMR2_IICACKT_Msk       (0x20UL)   /*!< IICACKT (Bitfield-Mask: 0x01)                         */
41247  #define R_SCI0_SIMR2_IICCSC_Pos        (1UL)      /*!< IICCSC (Bit 1)                                        */
41248  #define R_SCI0_SIMR2_IICCSC_Msk        (0x2UL)    /*!< IICCSC (Bitfield-Mask: 0x01)                          */
41249  #define R_SCI0_SIMR2_IICINTM_Pos       (0UL)      /*!< IICINTM (Bit 0)                                       */
41250  #define R_SCI0_SIMR2_IICINTM_Msk       (0x1UL)    /*!< IICINTM (Bitfield-Mask: 0x01)                         */
41251 /* =========================================================  SIMR3  ========================================================= */
41252  #define R_SCI0_SIMR3_IICSCLS_Pos       (6UL)      /*!< IICSCLS (Bit 6)                                       */
41253  #define R_SCI0_SIMR3_IICSCLS_Msk       (0xc0UL)   /*!< IICSCLS (Bitfield-Mask: 0x03)                         */
41254  #define R_SCI0_SIMR3_IICSDAS_Pos       (4UL)      /*!< IICSDAS (Bit 4)                                       */
41255  #define R_SCI0_SIMR3_IICSDAS_Msk       (0x30UL)   /*!< IICSDAS (Bitfield-Mask: 0x03)                         */
41256  #define R_SCI0_SIMR3_IICSTIF_Pos       (3UL)      /*!< IICSTIF (Bit 3)                                       */
41257  #define R_SCI0_SIMR3_IICSTIF_Msk       (0x8UL)    /*!< IICSTIF (Bitfield-Mask: 0x01)                         */
41258  #define R_SCI0_SIMR3_IICSTPREQ_Pos     (2UL)      /*!< IICSTPREQ (Bit 2)                                     */
41259  #define R_SCI0_SIMR3_IICSTPREQ_Msk     (0x4UL)    /*!< IICSTPREQ (Bitfield-Mask: 0x01)                       */
41260  #define R_SCI0_SIMR3_IICRSTAREQ_Pos    (1UL)      /*!< IICRSTAREQ (Bit 1)                                    */
41261  #define R_SCI0_SIMR3_IICRSTAREQ_Msk    (0x2UL)    /*!< IICRSTAREQ (Bitfield-Mask: 0x01)                      */
41262  #define R_SCI0_SIMR3_IICSTAREQ_Pos     (0UL)      /*!< IICSTAREQ (Bit 0)                                     */
41263  #define R_SCI0_SIMR3_IICSTAREQ_Msk     (0x1UL)    /*!< IICSTAREQ (Bitfield-Mask: 0x01)                       */
41264 /* =========================================================  SISR  ========================================================== */
41265  #define R_SCI0_SISR_IICACKR_Pos        (0UL)      /*!< IICACKR (Bit 0)                                       */
41266  #define R_SCI0_SISR_IICACKR_Msk        (0x1UL)    /*!< IICACKR (Bitfield-Mask: 0x01)                         */
41267 /* =========================================================  SPMR  ========================================================== */
41268  #define R_SCI0_SPMR_CKPH_Pos           (7UL)      /*!< CKPH (Bit 7)                                          */
41269  #define R_SCI0_SPMR_CKPH_Msk           (0x80UL)   /*!< CKPH (Bitfield-Mask: 0x01)                            */
41270  #define R_SCI0_SPMR_CKPOL_Pos          (6UL)      /*!< CKPOL (Bit 6)                                         */
41271  #define R_SCI0_SPMR_CKPOL_Msk          (0x40UL)   /*!< CKPOL (Bitfield-Mask: 0x01)                           */
41272  #define R_SCI0_SPMR_MFF_Pos            (4UL)      /*!< MFF (Bit 4)                                           */
41273  #define R_SCI0_SPMR_MFF_Msk            (0x10UL)   /*!< MFF (Bitfield-Mask: 0x01)                             */
41274  #define R_SCI0_SPMR_CSTPEN_Pos         (3UL)      /*!< CSTPEN (Bit 3)                                        */
41275  #define R_SCI0_SPMR_CSTPEN_Msk         (0x8UL)    /*!< CSTPEN (Bitfield-Mask: 0x01)                          */
41276  #define R_SCI0_SPMR_MSS_Pos            (2UL)      /*!< MSS (Bit 2)                                           */
41277  #define R_SCI0_SPMR_MSS_Msk            (0x4UL)    /*!< MSS (Bitfield-Mask: 0x01)                             */
41278  #define R_SCI0_SPMR_CTSE_Pos           (1UL)      /*!< CTSE (Bit 1)                                          */
41279  #define R_SCI0_SPMR_CTSE_Msk           (0x2UL)    /*!< CTSE (Bitfield-Mask: 0x01)                            */
41280  #define R_SCI0_SPMR_SSE_Pos            (0UL)      /*!< SSE (Bit 0)                                           */
41281  #define R_SCI0_SPMR_SSE_Msk            (0x1UL)    /*!< SSE (Bitfield-Mask: 0x01)                             */
41282 /* =========================================================  TDRHL  ========================================================= */
41283  #define R_SCI0_TDRHL_TDRHL_Pos         (0UL)      /*!< TDRHL (Bit 0)                                         */
41284  #define R_SCI0_TDRHL_TDRHL_Msk         (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff)                         */
41285 /* ========================================================  FTDRHL  ========================================================= */
41286  #define R_SCI0_FTDRHL_MPBT_Pos         (9UL)      /*!< MPBT (Bit 9)                                          */
41287  #define R_SCI0_FTDRHL_MPBT_Msk         (0x200UL)  /*!< MPBT (Bitfield-Mask: 0x01)                            */
41288  #define R_SCI0_FTDRHL_TDAT_Pos         (0UL)      /*!< TDAT (Bit 0)                                          */
41289  #define R_SCI0_FTDRHL_TDAT_Msk         (0x1ffUL)  /*!< TDAT (Bitfield-Mask: 0x1ff)                           */
41290 /* =========================================================  FTDRH  ========================================================= */
41291  #define R_SCI0_FTDRH_MPBT_Pos          (1UL)      /*!< MPBT (Bit 1)                                          */
41292  #define R_SCI0_FTDRH_MPBT_Msk          (0x2UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
41293  #define R_SCI0_FTDRH_TDATH_Pos         (0UL)      /*!< TDATH (Bit 0)                                         */
41294  #define R_SCI0_FTDRH_TDATH_Msk         (0x1UL)    /*!< TDATH (Bitfield-Mask: 0x01)                           */
41295 /* =========================================================  FTDRL  ========================================================= */
41296  #define R_SCI0_FTDRL_TDATL_Pos         (0UL)      /*!< TDATL (Bit 0)                                         */
41297  #define R_SCI0_FTDRL_TDATL_Msk         (0xffUL)   /*!< TDATL (Bitfield-Mask: 0xff)                           */
41298 /* =========================================================  RDRHL  ========================================================= */
41299  #define R_SCI0_RDRHL_RDRHL_Pos         (0UL)      /*!< RDRHL (Bit 0)                                         */
41300  #define R_SCI0_RDRHL_RDRHL_Msk         (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff)                         */
41301 /* ========================================================  FRDRHL  ========================================================= */
41302  #define R_SCI0_FRDRHL_RDF_Pos          (14UL)     /*!< RDF (Bit 14)                                          */
41303  #define R_SCI0_FRDRHL_RDF_Msk          (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01)                             */
41304  #define R_SCI0_FRDRHL_ORER_Pos         (13UL)     /*!< ORER (Bit 13)                                         */
41305  #define R_SCI0_FRDRHL_ORER_Msk         (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01)                            */
41306  #define R_SCI0_FRDRHL_FER_Pos          (12UL)     /*!< FER (Bit 12)                                          */
41307  #define R_SCI0_FRDRHL_FER_Msk          (0x1000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
41308  #define R_SCI0_FRDRHL_PER_Pos          (11UL)     /*!< PER (Bit 11)                                          */
41309  #define R_SCI0_FRDRHL_PER_Msk          (0x800UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
41310  #define R_SCI0_FRDRHL_DR_Pos           (10UL)     /*!< DR (Bit 10)                                           */
41311  #define R_SCI0_FRDRHL_DR_Msk           (0x400UL)  /*!< DR (Bitfield-Mask: 0x01)                              */
41312  #define R_SCI0_FRDRHL_MPB_Pos          (9UL)      /*!< MPB (Bit 9)                                           */
41313  #define R_SCI0_FRDRHL_MPB_Msk          (0x200UL)  /*!< MPB (Bitfield-Mask: 0x01)                             */
41314  #define R_SCI0_FRDRHL_RDAT_Pos         (0UL)      /*!< RDAT (Bit 0)                                          */
41315  #define R_SCI0_FRDRHL_RDAT_Msk         (0x1ffUL)  /*!< RDAT (Bitfield-Mask: 0x1ff)                           */
41316 /* =========================================================  FRDRH  ========================================================= */
41317  #define R_SCI0_FRDRH_RDF_Pos           (6UL)      /*!< RDF (Bit 6)                                           */
41318  #define R_SCI0_FRDRH_RDF_Msk           (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
41319  #define R_SCI0_FRDRH_ORER_Pos          (5UL)      /*!< ORER (Bit 5)                                          */
41320  #define R_SCI0_FRDRH_ORER_Msk          (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
41321  #define R_SCI0_FRDRH_FER_Pos           (4UL)      /*!< FER (Bit 4)                                           */
41322  #define R_SCI0_FRDRH_FER_Msk           (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
41323  #define R_SCI0_FRDRH_PER_Pos           (3UL)      /*!< PER (Bit 3)                                           */
41324  #define R_SCI0_FRDRH_PER_Msk           (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
41325  #define R_SCI0_FRDRH_DR_Pos            (2UL)      /*!< DR (Bit 2)                                            */
41326  #define R_SCI0_FRDRH_DR_Msk            (0x4UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
41327  #define R_SCI0_FRDRH_MPB_Pos           (1UL)      /*!< MPB (Bit 1)                                           */
41328  #define R_SCI0_FRDRH_MPB_Msk           (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
41329  #define R_SCI0_FRDRH_RDATH_Pos         (0UL)      /*!< RDATH (Bit 0)                                         */
41330  #define R_SCI0_FRDRH_RDATH_Msk         (0x1UL)    /*!< RDATH (Bitfield-Mask: 0x01)                           */
41331 /* =========================================================  FRDRL  ========================================================= */
41332  #define R_SCI0_FRDRL_RDATL_Pos         (0UL)      /*!< RDATL (Bit 0)                                         */
41333  #define R_SCI0_FRDRL_RDATL_Msk         (0xffUL)   /*!< RDATL (Bitfield-Mask: 0xff)                           */
41334 /* =========================================================  MDDR  ========================================================== */
41335  #define R_SCI0_MDDR_MDDR_Pos           (0UL)      /*!< MDDR (Bit 0)                                          */
41336  #define R_SCI0_MDDR_MDDR_Msk           (0xffUL)   /*!< MDDR (Bitfield-Mask: 0xff)                            */
41337 /* =========================================================  DCCR  ========================================================== */
41338  #define R_SCI0_DCCR_DCME_Pos           (7UL)      /*!< DCME (Bit 7)                                          */
41339  #define R_SCI0_DCCR_DCME_Msk           (0x80UL)   /*!< DCME (Bitfield-Mask: 0x01)                            */
41340  #define R_SCI0_DCCR_IDSEL_Pos          (6UL)      /*!< IDSEL (Bit 6)                                         */
41341  #define R_SCI0_DCCR_IDSEL_Msk          (0x40UL)   /*!< IDSEL (Bitfield-Mask: 0x01)                           */
41342  #define R_SCI0_DCCR_DFER_Pos           (4UL)      /*!< DFER (Bit 4)                                          */
41343  #define R_SCI0_DCCR_DFER_Msk           (0x10UL)   /*!< DFER (Bitfield-Mask: 0x01)                            */
41344  #define R_SCI0_DCCR_DPER_Pos           (3UL)      /*!< DPER (Bit 3)                                          */
41345  #define R_SCI0_DCCR_DPER_Msk           (0x8UL)    /*!< DPER (Bitfield-Mask: 0x01)                            */
41346  #define R_SCI0_DCCR_DCMF_Pos           (0UL)      /*!< DCMF (Bit 0)                                          */
41347  #define R_SCI0_DCCR_DCMF_Msk           (0x1UL)    /*!< DCMF (Bitfield-Mask: 0x01)                            */
41348 /* ==========================================================  FCR  ========================================================== */
41349  #define R_SCI0_FCR_RSTRG_Pos           (12UL)     /*!< RSTRG (Bit 12)                                        */
41350  #define R_SCI0_FCR_RSTRG_Msk           (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f)                           */
41351  #define R_SCI0_FCR_RTRG_Pos            (8UL)      /*!< RTRG (Bit 8)                                          */
41352  #define R_SCI0_FCR_RTRG_Msk            (0xf00UL)  /*!< RTRG (Bitfield-Mask: 0x0f)                            */
41353  #define R_SCI0_FCR_TTRG_Pos            (4UL)      /*!< TTRG (Bit 4)                                          */
41354  #define R_SCI0_FCR_TTRG_Msk            (0xf0UL)   /*!< TTRG (Bitfield-Mask: 0x0f)                            */
41355  #define R_SCI0_FCR_DRES_Pos            (3UL)      /*!< DRES (Bit 3)                                          */
41356  #define R_SCI0_FCR_DRES_Msk            (0x8UL)    /*!< DRES (Bitfield-Mask: 0x01)                            */
41357  #define R_SCI0_FCR_TFRST_Pos           (2UL)      /*!< TFRST (Bit 2)                                         */
41358  #define R_SCI0_FCR_TFRST_Msk           (0x4UL)    /*!< TFRST (Bitfield-Mask: 0x01)                           */
41359  #define R_SCI0_FCR_RFRST_Pos           (1UL)      /*!< RFRST (Bit 1)                                         */
41360  #define R_SCI0_FCR_RFRST_Msk           (0x2UL)    /*!< RFRST (Bitfield-Mask: 0x01)                           */
41361  #define R_SCI0_FCR_FM_Pos              (0UL)      /*!< FM (Bit 0)                                            */
41362  #define R_SCI0_FCR_FM_Msk              (0x1UL)    /*!< FM (Bitfield-Mask: 0x01)                              */
41363 /* ==========================================================  FDR  ========================================================== */
41364  #define R_SCI0_FDR_T_Pos               (8UL)      /*!< T (Bit 8)                                             */
41365  #define R_SCI0_FDR_T_Msk               (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f)                               */
41366  #define R_SCI0_FDR_R_Pos               (0UL)      /*!< R (Bit 0)                                             */
41367  #define R_SCI0_FDR_R_Msk               (0x1fUL)   /*!< R (Bitfield-Mask: 0x1f)                               */
41368 /* ==========================================================  LSR  ========================================================== */
41369  #define R_SCI0_LSR_PNUM_Pos            (8UL)      /*!< PNUM (Bit 8)                                          */
41370  #define R_SCI0_LSR_PNUM_Msk            (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f)                            */
41371  #define R_SCI0_LSR_FNUM_Pos            (2UL)      /*!< FNUM (Bit 2)                                          */
41372  #define R_SCI0_LSR_FNUM_Msk            (0x7cUL)   /*!< FNUM (Bitfield-Mask: 0x1f)                            */
41373  #define R_SCI0_LSR_ORER_Pos            (0UL)      /*!< ORER (Bit 0)                                          */
41374  #define R_SCI0_LSR_ORER_Msk            (0x1UL)    /*!< ORER (Bitfield-Mask: 0x01)                            */
41375 /* ==========================================================  CDR  ========================================================== */
41376  #define R_SCI0_CDR_CMPD_Pos            (0UL)      /*!< CMPD (Bit 0)                                          */
41377  #define R_SCI0_CDR_CMPD_Msk            (0x1ffUL)  /*!< CMPD (Bitfield-Mask: 0x1ff)                           */
41378 /* =========================================================  SPTR  ========================================================== */
41379  #define R_SCI0_SPTR_SPB2IO_Pos         (2UL)      /*!< SPB2IO (Bit 2)                                        */
41380  #define R_SCI0_SPTR_SPB2IO_Msk         (0x4UL)    /*!< SPB2IO (Bitfield-Mask: 0x01)                          */
41381  #define R_SCI0_SPTR_SPB2DT_Pos         (1UL)      /*!< SPB2DT (Bit 1)                                        */
41382  #define R_SCI0_SPTR_SPB2DT_Msk         (0x2UL)    /*!< SPB2DT (Bitfield-Mask: 0x01)                          */
41383  #define R_SCI0_SPTR_RXDMON_Pos         (0UL)      /*!< RXDMON (Bit 0)                                        */
41384  #define R_SCI0_SPTR_RXDMON_Msk         (0x1UL)    /*!< RXDMON (Bitfield-Mask: 0x01)                          */
41385  #define R_SCI0_SPTR_RINV_Pos           (4UL)      /*!< RINV (Bit 4)                                          */
41386  #define R_SCI0_SPTR_RINV_Msk           (0x10UL)   /*!< RINV (Bitfield-Mask: 0x01)                            */
41387  #define R_SCI0_SPTR_TINV_Pos           (5UL)      /*!< TINV (Bit 5)                                          */
41388  #define R_SCI0_SPTR_TINV_Msk           (0x20UL)   /*!< TINV (Bitfield-Mask: 0x01)                            */
41389  #define R_SCI0_SPTR_ASEN_Pos           (6UL)      /*!< ASEN (Bit 6)                                          */
41390  #define R_SCI0_SPTR_ASEN_Msk           (0x40UL)   /*!< ASEN (Bitfield-Mask: 0x01)                            */
41391  #define R_SCI0_SPTR_ATEN_Pos           (7UL)      /*!< ATEN (Bit 7)                                          */
41392  #define R_SCI0_SPTR_ATEN_Msk           (0x80UL)   /*!< ATEN (Bitfield-Mask: 0x01)                            */
41393 /* =========================================================  ACTR  ========================================================== */
41394  #define R_SCI0_ACTR_AST_Pos            (0UL)      /*!< AST (Bit 0)                                           */
41395  #define R_SCI0_ACTR_AST_Msk            (0x7UL)    /*!< AST (Bitfield-Mask: 0x07)                             */
41396  #define R_SCI0_ACTR_AJD_Pos            (3UL)      /*!< AJD (Bit 3)                                           */
41397  #define R_SCI0_ACTR_AJD_Msk            (0x8UL)    /*!< AJD (Bitfield-Mask: 0x01)                             */
41398  #define R_SCI0_ACTR_ATT_Pos            (4UL)      /*!< ATT (Bit 4)                                           */
41399  #define R_SCI0_ACTR_ATT_Msk            (0x70UL)   /*!< ATT (Bitfield-Mask: 0x07)                             */
41400  #define R_SCI0_ACTR_AET_Pos            (7UL)      /*!< AET (Bit 7)                                           */
41401  #define R_SCI0_ACTR_AET_Msk            (0x80UL)   /*!< AET (Bitfield-Mask: 0x01)                             */
41402 /* =========================================================  ESMER  ========================================================= */
41403  #define R_SCI0_ESMER_ESME_Pos          (0UL)      /*!< ESME (Bit 0)                                          */
41404  #define R_SCI0_ESMER_ESME_Msk          (0x1UL)    /*!< ESME (Bitfield-Mask: 0x01)                            */
41405 /* ==========================================================  CR0  ========================================================== */
41406  #define R_SCI0_CR0_SFSF_Pos            (1UL)      /*!< SFSF (Bit 1)                                          */
41407  #define R_SCI0_CR0_SFSF_Msk            (0x2UL)    /*!< SFSF (Bitfield-Mask: 0x01)                            */
41408  #define R_SCI0_CR0_RXDSF_Pos           (2UL)      /*!< RXDSF (Bit 2)                                         */
41409  #define R_SCI0_CR0_RXDSF_Msk           (0x4UL)    /*!< RXDSF (Bitfield-Mask: 0x01)                           */
41410  #define R_SCI0_CR0_BRME_Pos            (3UL)      /*!< BRME (Bit 3)                                          */
41411  #define R_SCI0_CR0_BRME_Msk            (0x8UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
41412 /* ==========================================================  CR1  ========================================================== */
41413  #define R_SCI0_CR1_BFE_Pos             (0UL)      /*!< BFE (Bit 0)                                           */
41414  #define R_SCI0_CR1_BFE_Msk             (0x1UL)    /*!< BFE (Bitfield-Mask: 0x01)                             */
41415  #define R_SCI0_CR1_CF0RE_Pos           (1UL)      /*!< CF0RE (Bit 1)                                         */
41416  #define R_SCI0_CR1_CF0RE_Msk           (0x2UL)    /*!< CF0RE (Bitfield-Mask: 0x01)                           */
41417  #define R_SCI0_CR1_CF1DS_Pos           (2UL)      /*!< CF1DS (Bit 2)                                         */
41418  #define R_SCI0_CR1_CF1DS_Msk           (0xcUL)    /*!< CF1DS (Bitfield-Mask: 0x03)                           */
41419  #define R_SCI0_CR1_PIBE_Pos            (4UL)      /*!< PIBE (Bit 4)                                          */
41420  #define R_SCI0_CR1_PIBE_Msk            (0x10UL)   /*!< PIBE (Bitfield-Mask: 0x01)                            */
41421  #define R_SCI0_CR1_PIBS_Pos            (5UL)      /*!< PIBS (Bit 5)                                          */
41422  #define R_SCI0_CR1_PIBS_Msk            (0xe0UL)   /*!< PIBS (Bitfield-Mask: 0x07)                            */
41423 /* ==========================================================  CR2  ========================================================== */
41424  #define R_SCI0_CR2_DFCS_Pos            (0UL)      /*!< DFCS (Bit 0)                                          */
41425  #define R_SCI0_CR2_DFCS_Msk            (0x7UL)    /*!< DFCS (Bitfield-Mask: 0x07)                            */
41426  #define R_SCI0_CR2_BCCS_Pos            (4UL)      /*!< BCCS (Bit 4)                                          */
41427  #define R_SCI0_CR2_BCCS_Msk            (0x30UL)   /*!< BCCS (Bitfield-Mask: 0x03)                            */
41428  #define R_SCI0_CR2_RTS_Pos             (6UL)      /*!< RTS (Bit 6)                                           */
41429  #define R_SCI0_CR2_RTS_Msk             (0xc0UL)   /*!< RTS (Bitfield-Mask: 0x03)                             */
41430 /* ==========================================================  CR3  ========================================================== */
41431  #define R_SCI0_CR3_SDST_Pos            (0UL)      /*!< SDST (Bit 0)                                          */
41432  #define R_SCI0_CR3_SDST_Msk            (0x1UL)    /*!< SDST (Bitfield-Mask: 0x01)                            */
41433 /* ==========================================================  PCR  ========================================================== */
41434  #define R_SCI0_PCR_TXDXPS_Pos          (0UL)      /*!< TXDXPS (Bit 0)                                        */
41435  #define R_SCI0_PCR_TXDXPS_Msk          (0x1UL)    /*!< TXDXPS (Bitfield-Mask: 0x01)                          */
41436  #define R_SCI0_PCR_RXDXPS_Pos          (1UL)      /*!< RXDXPS (Bit 1)                                        */
41437  #define R_SCI0_PCR_RXDXPS_Msk          (0x2UL)    /*!< RXDXPS (Bitfield-Mask: 0x01)                          */
41438  #define R_SCI0_PCR_SHARPS_Pos          (4UL)      /*!< SHARPS (Bit 4)                                        */
41439  #define R_SCI0_PCR_SHARPS_Msk          (0x10UL)   /*!< SHARPS (Bitfield-Mask: 0x01)                          */
41440 /* ==========================================================  ICR  ========================================================== */
41441  #define R_SCI0_ICR_BFDIE_Pos           (0UL)      /*!< BFDIE (Bit 0)                                         */
41442  #define R_SCI0_ICR_BFDIE_Msk           (0x1UL)    /*!< BFDIE (Bitfield-Mask: 0x01)                           */
41443  #define R_SCI0_ICR_CF0MIE_Pos          (1UL)      /*!< CF0MIE (Bit 1)                                        */
41444  #define R_SCI0_ICR_CF0MIE_Msk          (0x2UL)    /*!< CF0MIE (Bitfield-Mask: 0x01)                          */
41445  #define R_SCI0_ICR_CF1MIE_Pos          (2UL)      /*!< CF1MIE (Bit 2)                                        */
41446  #define R_SCI0_ICR_CF1MIE_Msk          (0x4UL)    /*!< CF1MIE (Bitfield-Mask: 0x01)                          */
41447  #define R_SCI0_ICR_PIBDIE_Pos          (3UL)      /*!< PIBDIE (Bit 3)                                        */
41448  #define R_SCI0_ICR_PIBDIE_Msk          (0x8UL)    /*!< PIBDIE (Bitfield-Mask: 0x01)                          */
41449  #define R_SCI0_ICR_BCDIE_Pos           (4UL)      /*!< BCDIE (Bit 4)                                         */
41450  #define R_SCI0_ICR_BCDIE_Msk           (0x10UL)   /*!< BCDIE (Bitfield-Mask: 0x01)                           */
41451  #define R_SCI0_ICR_AEDIE_Pos           (5UL)      /*!< AEDIE (Bit 5)                                         */
41452  #define R_SCI0_ICR_AEDIE_Msk           (0x20UL)   /*!< AEDIE (Bitfield-Mask: 0x01)                           */
41453 /* ==========================================================  STR  ========================================================== */
41454  #define R_SCI0_STR_BFDF_Pos            (0UL)      /*!< BFDF (Bit 0)                                          */
41455  #define R_SCI0_STR_BFDF_Msk            (0x1UL)    /*!< BFDF (Bitfield-Mask: 0x01)                            */
41456  #define R_SCI0_STR_CF0MF_Pos           (1UL)      /*!< CF0MF (Bit 1)                                         */
41457  #define R_SCI0_STR_CF0MF_Msk           (0x2UL)    /*!< CF0MF (Bitfield-Mask: 0x01)                           */
41458  #define R_SCI0_STR_CF1MF_Pos           (2UL)      /*!< CF1MF (Bit 2)                                         */
41459  #define R_SCI0_STR_CF1MF_Msk           (0x4UL)    /*!< CF1MF (Bitfield-Mask: 0x01)                           */
41460  #define R_SCI0_STR_PIBDF_Pos           (3UL)      /*!< PIBDF (Bit 3)                                         */
41461  #define R_SCI0_STR_PIBDF_Msk           (0x8UL)    /*!< PIBDF (Bitfield-Mask: 0x01)                           */
41462  #define R_SCI0_STR_BCDF_Pos            (4UL)      /*!< BCDF (Bit 4)                                          */
41463  #define R_SCI0_STR_BCDF_Msk            (0x10UL)   /*!< BCDF (Bitfield-Mask: 0x01)                            */
41464  #define R_SCI0_STR_AEDF_Pos            (5UL)      /*!< AEDF (Bit 5)                                          */
41465  #define R_SCI0_STR_AEDF_Msk            (0x20UL)   /*!< AEDF (Bitfield-Mask: 0x01)                            */
41466 /* =========================================================  STCR  ========================================================== */
41467  #define R_SCI0_STCR_BFDCL_Pos          (0UL)      /*!< BFDCL (Bit 0)                                         */
41468  #define R_SCI0_STCR_BFDCL_Msk          (0x1UL)    /*!< BFDCL (Bitfield-Mask: 0x01)                           */
41469  #define R_SCI0_STCR_CF0MCL_Pos         (1UL)      /*!< CF0MCL (Bit 1)                                        */
41470  #define R_SCI0_STCR_CF0MCL_Msk         (0x2UL)    /*!< CF0MCL (Bitfield-Mask: 0x01)                          */
41471  #define R_SCI0_STCR_CF1MCL_Pos         (2UL)      /*!< CF1MCL (Bit 2)                                        */
41472  #define R_SCI0_STCR_CF1MCL_Msk         (0x4UL)    /*!< CF1MCL (Bitfield-Mask: 0x01)                          */
41473  #define R_SCI0_STCR_PIBDCL_Pos         (3UL)      /*!< PIBDCL (Bit 3)                                        */
41474  #define R_SCI0_STCR_PIBDCL_Msk         (0x8UL)    /*!< PIBDCL (Bitfield-Mask: 0x01)                          */
41475  #define R_SCI0_STCR_BCDCL_Pos          (4UL)      /*!< BCDCL (Bit 4)                                         */
41476  #define R_SCI0_STCR_BCDCL_Msk          (0x10UL)   /*!< BCDCL (Bitfield-Mask: 0x01)                           */
41477  #define R_SCI0_STCR_AEDCL_Pos          (5UL)      /*!< AEDCL (Bit 5)                                         */
41478  #define R_SCI0_STCR_AEDCL_Msk          (0x20UL)   /*!< AEDCL (Bitfield-Mask: 0x01)                           */
41479 /* =========================================================  CF0DR  ========================================================= */
41480 /* =========================================================  CF0CR  ========================================================= */
41481  #define R_SCI0_CF0CR_CF0CE0_Pos        (0UL)      /*!< CF0CE0 (Bit 0)                                        */
41482  #define R_SCI0_CF0CR_CF0CE0_Msk        (0x1UL)    /*!< CF0CE0 (Bitfield-Mask: 0x01)                          */
41483  #define R_SCI0_CF0CR_CF0CE1_Pos        (1UL)      /*!< CF0CE1 (Bit 1)                                        */
41484  #define R_SCI0_CF0CR_CF0CE1_Msk        (0x2UL)    /*!< CF0CE1 (Bitfield-Mask: 0x01)                          */
41485  #define R_SCI0_CF0CR_CF0CE2_Pos        (2UL)      /*!< CF0CE2 (Bit 2)                                        */
41486  #define R_SCI0_CF0CR_CF0CE2_Msk        (0x4UL)    /*!< CF0CE2 (Bitfield-Mask: 0x01)                          */
41487  #define R_SCI0_CF0CR_CF0CE3_Pos        (3UL)      /*!< CF0CE3 (Bit 3)                                        */
41488  #define R_SCI0_CF0CR_CF0CE3_Msk        (0x8UL)    /*!< CF0CE3 (Bitfield-Mask: 0x01)                          */
41489  #define R_SCI0_CF0CR_CF0CE4_Pos        (4UL)      /*!< CF0CE4 (Bit 4)                                        */
41490  #define R_SCI0_CF0CR_CF0CE4_Msk        (0x10UL)   /*!< CF0CE4 (Bitfield-Mask: 0x01)                          */
41491  #define R_SCI0_CF0CR_CF0CE5_Pos        (5UL)      /*!< CF0CE5 (Bit 5)                                        */
41492  #define R_SCI0_CF0CR_CF0CE5_Msk        (0x20UL)   /*!< CF0CE5 (Bitfield-Mask: 0x01)                          */
41493  #define R_SCI0_CF0CR_CF0CE6_Pos        (6UL)      /*!< CF0CE6 (Bit 6)                                        */
41494  #define R_SCI0_CF0CR_CF0CE6_Msk        (0x40UL)   /*!< CF0CE6 (Bitfield-Mask: 0x01)                          */
41495  #define R_SCI0_CF0CR_CF0CE7_Pos        (7UL)      /*!< CF0CE7 (Bit 7)                                        */
41496  #define R_SCI0_CF0CR_CF0CE7_Msk        (0x80UL)   /*!< CF0CE7 (Bitfield-Mask: 0x01)                          */
41497 /* =========================================================  CF0RR  ========================================================= */
41498 /* ========================================================  PCF1DR  ========================================================= */
41499 /* ========================================================  SCF1DR  ========================================================= */
41500 /* =========================================================  CF1CR  ========================================================= */
41501  #define R_SCI0_CF1CR_CF1CE0_Pos        (0UL)    /*!< CF1CE0 (Bit 0)                                        */
41502  #define R_SCI0_CF1CR_CF1CE0_Msk        (0x1UL)  /*!< CF1CE0 (Bitfield-Mask: 0x01)                          */
41503  #define R_SCI0_CF1CR_CF1CE1_Pos        (1UL)    /*!< CF1CE1 (Bit 1)                                        */
41504  #define R_SCI0_CF1CR_CF1CE1_Msk        (0x2UL)  /*!< CF1CE1 (Bitfield-Mask: 0x01)                          */
41505  #define R_SCI0_CF1CR_CF1CE2_Pos        (2UL)    /*!< CF1CE2 (Bit 2)                                        */
41506  #define R_SCI0_CF1CR_CF1CE2_Msk        (0x4UL)  /*!< CF1CE2 (Bitfield-Mask: 0x01)                          */
41507  #define R_SCI0_CF1CR_CF1CE3_Pos        (3UL)    /*!< CF1CE3 (Bit 3)                                        */
41508  #define R_SCI0_CF1CR_CF1CE3_Msk        (0x8UL)  /*!< CF1CE3 (Bitfield-Mask: 0x01)                          */
41509  #define R_SCI0_CF1CR_CF1CE4_Pos        (4UL)    /*!< CF1CE4 (Bit 4)                                        */
41510  #define R_SCI0_CF1CR_CF1CE4_Msk        (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01)                          */
41511  #define R_SCI0_CF1CR_CF1CE5_Pos        (5UL)    /*!< CF1CE5 (Bit 5)                                        */
41512  #define R_SCI0_CF1CR_CF1CE5_Msk        (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01)                          */
41513  #define R_SCI0_CF1CR_CF1CE6_Pos        (6UL)    /*!< CF1CE6 (Bit 6)                                        */
41514  #define R_SCI0_CF1CR_CF1CE6_Msk        (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01)                          */
41515  #define R_SCI0_CF1CR_CF1CE7_Pos        (7UL)    /*!< CF1CE7 (Bit 7)                                        */
41516  #define R_SCI0_CF1CR_CF1CE7_Msk        (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01)                          */
41517 /* =========================================================  CF1RR  ========================================================= */
41518 /* ==========================================================  TCR  ========================================================== */
41519  #define R_SCI0_TCR_TCST_Pos            (0UL)    /*!< TCST (Bit 0)                                          */
41520  #define R_SCI0_TCR_TCST_Msk            (0x1UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
41521 /* ==========================================================  TMR  ========================================================== */
41522  #define R_SCI0_TMR_TOMS_Pos            (0UL)    /*!< TOMS (Bit 0)                                          */
41523  #define R_SCI0_TMR_TOMS_Msk            (0x3UL)  /*!< TOMS (Bitfield-Mask: 0x03)                            */
41524  #define R_SCI0_TMR_TWRC_Pos            (3UL)    /*!< TWRC (Bit 3)                                          */
41525  #define R_SCI0_TMR_TWRC_Msk            (0x8UL)  /*!< TWRC (Bitfield-Mask: 0x01)                            */
41526  #define R_SCI0_TMR_TCSS_Pos            (4UL)    /*!< TCSS (Bit 4)                                          */
41527  #define R_SCI0_TMR_TCSS_Msk            (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07)                            */
41528 /* =========================================================  TPRE  ========================================================== */
41529 /* =========================================================  TCNT  ========================================================== */
41530 
41531 /* =========================================================================================================================== */
41532 /* ================                                         R_SDADC0                                          ================ */
41533 /* =========================================================================================================================== */
41534 
41535 /* =========================================================  STC1  ========================================================== */
41536  #define R_SDADC0_STC1_VSBIAS_Pos     (8UL)          /*!< VSBIAS (Bit 8)                                        */
41537  #define R_SDADC0_STC1_VSBIAS_Msk     (0xf00UL)      /*!< VSBIAS (Bitfield-Mask: 0x0f)                          */
41538  #define R_SDADC0_STC1_CLKDIV_Pos     (0UL)          /*!< CLKDIV (Bit 0)                                        */
41539  #define R_SDADC0_STC1_CLKDIV_Msk     (0xfUL)        /*!< CLKDIV (Bitfield-Mask: 0x0f)                          */
41540  #define R_SDADC0_STC1_SDADLPM_Pos    (7UL)          /*!< SDADLPM (Bit 7)                                       */
41541  #define R_SDADC0_STC1_SDADLPM_Msk    (0x80UL)       /*!< SDADLPM (Bitfield-Mask: 0x01)                         */
41542  #define R_SDADC0_STC1_VREFSEL_Pos    (15UL)         /*!< VREFSEL (Bit 15)                                      */
41543  #define R_SDADC0_STC1_VREFSEL_Msk    (0x8000UL)     /*!< VREFSEL (Bitfield-Mask: 0x01)                         */
41544 /* =========================================================  STC2  ========================================================== */
41545  #define R_SDADC0_STC2_BGRPON_Pos     (0UL)          /*!< BGRPON (Bit 0)                                        */
41546  #define R_SDADC0_STC2_BGRPON_Msk     (0x1UL)        /*!< BGRPON (Bitfield-Mask: 0x01)                          */
41547  #define R_SDADC0_STC2_ADFPWDS_Pos    (2UL)          /*!< ADFPWDS (Bit 2)                                       */
41548  #define R_SDADC0_STC2_ADFPWDS_Msk    (0x4UL)        /*!< ADFPWDS (Bitfield-Mask: 0x01)                         */
41549  #define R_SDADC0_STC2_ADCPON_Pos     (1UL)          /*!< ADCPON (Bit 1)                                        */
41550  #define R_SDADC0_STC2_ADCPON_Msk     (0x2UL)        /*!< ADCPON (Bitfield-Mask: 0x01)                          */
41551 /* =========================================================  PGAC  ========================================================== */
41552  #define R_SDADC0_PGAC_PGAASN_Pos     (31UL)         /*!< PGAASN (Bit 31)                                       */
41553  #define R_SDADC0_PGAC_PGAASN_Msk     (0x80000000UL) /*!< PGAASN (Bitfield-Mask: 0x01)                          */
41554  #define R_SDADC0_PGAC_PGACVE_Pos     (30UL)         /*!< PGACVE (Bit 30)                                       */
41555  #define R_SDADC0_PGAC_PGACVE_Msk     (0x40000000UL) /*!< PGACVE (Bitfield-Mask: 0x01)                          */
41556  #define R_SDADC0_PGAC_PGAREV_Pos     (28UL)         /*!< PGAREV (Bit 28)                                       */
41557  #define R_SDADC0_PGAC_PGAREV_Msk     (0x10000000UL) /*!< PGAREV (Bitfield-Mask: 0x01)                          */
41558  #define R_SDADC0_PGAC_PGAAVE_Pos     (26UL)         /*!< PGAAVE (Bit 26)                                       */
41559  #define R_SDADC0_PGAC_PGAAVE_Msk     (0xc000000UL)  /*!< PGAAVE (Bitfield-Mask: 0x03)                          */
41560  #define R_SDADC0_PGAC_PGAAVN_Pos     (24UL)         /*!< PGAAVN (Bit 24)                                       */
41561  #define R_SDADC0_PGAC_PGAAVN_Msk     (0x3000000UL)  /*!< PGAAVN (Bitfield-Mask: 0x03)                          */
41562  #define R_SDADC0_PGAC_PGACTN_Pos     (21UL)         /*!< PGACTN (Bit 21)                                       */
41563  #define R_SDADC0_PGAC_PGACTN_Msk     (0xe00000UL)   /*!< PGACTN (Bitfield-Mask: 0x07)                          */
41564  #define R_SDADC0_PGAC_PGACTM_Pos     (16UL)         /*!< PGACTM (Bit 16)                                       */
41565  #define R_SDADC0_PGAC_PGACTM_Msk     (0x1f0000UL)   /*!< PGACTM (Bitfield-Mask: 0x1f)                          */
41566  #define R_SDADC0_PGAC_PGASEL_Pos     (15UL)         /*!< PGASEL (Bit 15)                                       */
41567  #define R_SDADC0_PGAC_PGASEL_Msk     (0x8000UL)     /*!< PGASEL (Bitfield-Mask: 0x01)                          */
41568  #define R_SDADC0_PGAC_PGAPOL_Pos     (14UL)         /*!< PGAPOL (Bit 14)                                       */
41569  #define R_SDADC0_PGAC_PGAPOL_Msk     (0x4000UL)     /*!< PGAPOL (Bitfield-Mask: 0x01)                          */
41570  #define R_SDADC0_PGAC_PGAOFS_Pos     (8UL)          /*!< PGAOFS (Bit 8)                                        */
41571  #define R_SDADC0_PGAC_PGAOFS_Msk     (0x1f00UL)     /*!< PGAOFS (Bitfield-Mask: 0x1f)                          */
41572  #define R_SDADC0_PGAC_PGAOSR_Pos     (5UL)          /*!< PGAOSR (Bit 5)                                        */
41573  #define R_SDADC0_PGAC_PGAOSR_Msk     (0xe0UL)       /*!< PGAOSR (Bitfield-Mask: 0x07)                          */
41574  #define R_SDADC0_PGAC_PGAGC_Pos      (0UL)          /*!< PGAGC (Bit 0)                                         */
41575  #define R_SDADC0_PGAC_PGAGC_Msk      (0x1fUL)       /*!< PGAGC (Bitfield-Mask: 0x1f)                           */
41576 /* =========================================================  ADC1  ========================================================== */
41577  #define R_SDADC0_ADC1_PGASLFT_Pos    (20UL)         /*!< PGASLFT (Bit 20)                                      */
41578  #define R_SDADC0_ADC1_PGASLFT_Msk    (0x100000UL)   /*!< PGASLFT (Bitfield-Mask: 0x01)                         */
41579  #define R_SDADC0_ADC1_PGADISC_Pos    (17UL)         /*!< PGADISC (Bit 17)                                      */
41580  #define R_SDADC0_ADC1_PGADISC_Msk    (0x20000UL)    /*!< PGADISC (Bitfield-Mask: 0x01)                         */
41581  #define R_SDADC0_ADC1_PGADISA_Pos    (16UL)         /*!< PGADISA (Bit 16)                                      */
41582  #define R_SDADC0_ADC1_PGADISA_Msk    (0x10000UL)    /*!< PGADISA (Bitfield-Mask: 0x01)                         */
41583  #define R_SDADC0_ADC1_SDADBMP_Pos    (8UL)          /*!< SDADBMP (Bit 8)                                       */
41584  #define R_SDADC0_ADC1_SDADBMP_Msk    (0x1f00UL)     /*!< SDADBMP (Bitfield-Mask: 0x1f)                         */
41585  #define R_SDADC0_ADC1_SDADTMD_Pos    (4UL)          /*!< SDADTMD (Bit 4)                                       */
41586  #define R_SDADC0_ADC1_SDADTMD_Msk    (0x10UL)       /*!< SDADTMD (Bitfield-Mask: 0x01)                         */
41587  #define R_SDADC0_ADC1_SDADSCM_Pos    (0UL)          /*!< SDADSCM (Bit 0)                                       */
41588  #define R_SDADC0_ADC1_SDADSCM_Msk    (0x1UL)        /*!< SDADSCM (Bitfield-Mask: 0x01)                         */
41589 /* =========================================================  ADC2  ========================================================== */
41590  #define R_SDADC0_ADC2_SDADST_Pos     (0UL)          /*!< SDADST (Bit 0)                                        */
41591  #define R_SDADC0_ADC2_SDADST_Msk     (0x1UL)        /*!< SDADST (Bitfield-Mask: 0x01)                          */
41592 /* =========================================================  ADCR  ========================================================== */
41593  #define R_SDADC0_ADCR_SDADCRC_Pos    (25UL)         /*!< SDADCRC (Bit 25)                                      */
41594  #define R_SDADC0_ADCR_SDADCRC_Msk    (0xe000000UL)  /*!< SDADCRC (Bitfield-Mask: 0x07)                         */
41595  #define R_SDADC0_ADCR_SDADCRS_Pos    (24UL)         /*!< SDADCRS (Bit 24)                                      */
41596  #define R_SDADC0_ADCR_SDADCRS_Msk    (0x1000000UL)  /*!< SDADCRS (Bitfield-Mask: 0x01)                         */
41597  #define R_SDADC0_ADCR_SDADCRD_Pos    (0UL)          /*!< SDADCRD (Bit 0)                                       */
41598  #define R_SDADC0_ADCR_SDADCRD_Msk    (0xffffffUL)   /*!< SDADCRD (Bitfield-Mask: 0xffffff)                     */
41599 /* =========================================================  ADAR  ========================================================== */
41600  #define R_SDADC0_ADAR_SDADMVC_Pos    (25UL)         /*!< SDADMVC (Bit 25)                                      */
41601  #define R_SDADC0_ADAR_SDADMVC_Msk    (0xe000000UL)  /*!< SDADMVC (Bitfield-Mask: 0x07)                         */
41602  #define R_SDADC0_ADAR_SDADMVS_Pos    (24UL)         /*!< SDADMVS (Bit 24)                                      */
41603  #define R_SDADC0_ADAR_SDADMVS_Msk    (0x1000000UL)  /*!< SDADMVS (Bitfield-Mask: 0x01)                         */
41604  #define R_SDADC0_ADAR_SDADMVD_Pos    (0UL)          /*!< SDADMVD (Bit 0)                                       */
41605  #define R_SDADC0_ADAR_SDADMVD_Msk    (0xffffffUL)   /*!< SDADMVD (Bitfield-Mask: 0xffffff)                     */
41606 /* =========================================================  CLBC  ========================================================== */
41607  #define R_SDADC0_CLBC_CLBMD_Pos      (0UL)          /*!< CLBMD (Bit 0)                                         */
41608  #define R_SDADC0_CLBC_CLBMD_Msk      (0x3UL)        /*!< CLBMD (Bitfield-Mask: 0x03)                           */
41609 /* ========================================================  CLBSTR  ========================================================= */
41610  #define R_SDADC0_CLBSTR_CLBST_Pos    (0UL)          /*!< CLBST (Bit 0)                                         */
41611  #define R_SDADC0_CLBSTR_CLBST_Msk    (0x1UL)        /*!< CLBST (Bitfield-Mask: 0x01)                           */
41612 /* ========================================================  CLBSSR  ========================================================= */
41613  #define R_SDADC0_CLBSSR_CLBSS_Pos    (0UL)          /*!< CLBSS (Bit 0)                                         */
41614  #define R_SDADC0_CLBSSR_CLBSS_Msk    (0x1UL)        /*!< CLBSS (Bitfield-Mask: 0x01)                           */
41615 
41616 /* =========================================================================================================================== */
41617 /* ================                                          R_SDHI0                                          ================ */
41618 /* =========================================================================================================================== */
41619 
41620 /* ========================================================  SD_CMD  ========================================================= */
41621  #define R_SDHI0_SD_CMD_CMD12AT_Pos              (14UL)         /*!< CMD12AT (Bit 14)                                      */
41622  #define R_SDHI0_SD_CMD_CMD12AT_Msk              (0xc000UL)     /*!< CMD12AT (Bitfield-Mask: 0x03)                         */
41623  #define R_SDHI0_SD_CMD_TRSTP_Pos                (13UL)         /*!< TRSTP (Bit 13)                                        */
41624  #define R_SDHI0_SD_CMD_TRSTP_Msk                (0x2000UL)     /*!< TRSTP (Bitfield-Mask: 0x01)                           */
41625  #define R_SDHI0_SD_CMD_CMDRW_Pos                (12UL)         /*!< CMDRW (Bit 12)                                        */
41626  #define R_SDHI0_SD_CMD_CMDRW_Msk                (0x1000UL)     /*!< CMDRW (Bitfield-Mask: 0x01)                           */
41627  #define R_SDHI0_SD_CMD_CMDTP_Pos                (11UL)         /*!< CMDTP (Bit 11)                                        */
41628  #define R_SDHI0_SD_CMD_CMDTP_Msk                (0x800UL)      /*!< CMDTP (Bitfield-Mask: 0x01)                           */
41629  #define R_SDHI0_SD_CMD_RSPTP_Pos                (8UL)          /*!< RSPTP (Bit 8)                                         */
41630  #define R_SDHI0_SD_CMD_RSPTP_Msk                (0x700UL)      /*!< RSPTP (Bitfield-Mask: 0x07)                           */
41631  #define R_SDHI0_SD_CMD_ACMD_Pos                 (6UL)          /*!< ACMD (Bit 6)                                          */
41632  #define R_SDHI0_SD_CMD_ACMD_Msk                 (0xc0UL)       /*!< ACMD (Bitfield-Mask: 0x03)                            */
41633  #define R_SDHI0_SD_CMD_CMDIDX_Pos               (0UL)          /*!< CMDIDX (Bit 0)                                        */
41634  #define R_SDHI0_SD_CMD_CMDIDX_Msk               (0x3fUL)       /*!< CMDIDX (Bitfield-Mask: 0x3f)                          */
41635 /* ========================================================  SD_ARG  ========================================================= */
41636  #define R_SDHI0_SD_ARG_SD_ARG_Pos               (0UL)          /*!< SD_ARG (Bit 0)                                        */
41637  #define R_SDHI0_SD_ARG_SD_ARG_Msk               (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff)                    */
41638 /* ========================================================  SD_ARG1  ======================================================== */
41639  #define R_SDHI0_SD_ARG1_SD_ARG1_Pos             (0UL)          /*!< SD_ARG1 (Bit 0)                                       */
41640  #define R_SDHI0_SD_ARG1_SD_ARG1_Msk             (0xffffUL)     /*!< SD_ARG1 (Bitfield-Mask: 0xffff)                       */
41641 /* ========================================================  SD_STOP  ======================================================== */
41642  #define R_SDHI0_SD_STOP_SEC_Pos                 (8UL)          /*!< SEC (Bit 8)                                           */
41643  #define R_SDHI0_SD_STOP_SEC_Msk                 (0x100UL)      /*!< SEC (Bitfield-Mask: 0x01)                             */
41644  #define R_SDHI0_SD_STOP_STP_Pos                 (0UL)          /*!< STP (Bit 0)                                           */
41645  #define R_SDHI0_SD_STOP_STP_Msk                 (0x1UL)        /*!< STP (Bitfield-Mask: 0x01)                             */
41646 /* =======================================================  SD_SECCNT  ======================================================= */
41647  #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos         (0UL)          /*!< SD_SECCNT (Bit 0)                                     */
41648  #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk         (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff)                 */
41649 /* =======================================================  SD_RSP10  ======================================================== */
41650  #define R_SDHI0_SD_RSP10_SD_RSP10_Pos           (0UL)          /*!< SD_RSP10 (Bit 0)                                      */
41651  #define R_SDHI0_SD_RSP10_SD_RSP10_Msk           (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff)                  */
41652 /* ========================================================  SD_RSP1  ======================================================== */
41653  #define R_SDHI0_SD_RSP1_SD_RSP1_Pos             (0UL)          /*!< SD_RSP1 (Bit 0)                                       */
41654  #define R_SDHI0_SD_RSP1_SD_RSP1_Msk             (0xffffUL)     /*!< SD_RSP1 (Bitfield-Mask: 0xffff)                       */
41655 /* =======================================================  SD_RSP32  ======================================================== */
41656  #define R_SDHI0_SD_RSP32_SD_RSP32_Pos           (0UL)          /*!< SD_RSP32 (Bit 0)                                      */
41657  #define R_SDHI0_SD_RSP32_SD_RSP32_Msk           (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff)                  */
41658 /* ========================================================  SD_RSP3  ======================================================== */
41659  #define R_SDHI0_SD_RSP3_SD_RSP3_Pos             (0UL)          /*!< SD_RSP3 (Bit 0)                                       */
41660  #define R_SDHI0_SD_RSP3_SD_RSP3_Msk             (0xffffUL)     /*!< SD_RSP3 (Bitfield-Mask: 0xffff)                       */
41661 /* =======================================================  SD_RSP54  ======================================================== */
41662  #define R_SDHI0_SD_RSP54_SD_RSP54_Pos           (0UL)          /*!< SD_RSP54 (Bit 0)                                      */
41663  #define R_SDHI0_SD_RSP54_SD_RSP54_Msk           (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff)                  */
41664 /* ========================================================  SD_RSP5  ======================================================== */
41665  #define R_SDHI0_SD_RSP5_SD_RSP5_Pos             (0UL)          /*!< SD_RSP5 (Bit 0)                                       */
41666  #define R_SDHI0_SD_RSP5_SD_RSP5_Msk             (0xffffUL)     /*!< SD_RSP5 (Bitfield-Mask: 0xffff)                       */
41667 /* =======================================================  SD_RSP76  ======================================================== */
41668  #define R_SDHI0_SD_RSP76_SD_RSP76_Pos           (0UL)          /*!< SD_RSP76 (Bit 0)                                      */
41669  #define R_SDHI0_SD_RSP76_SD_RSP76_Msk           (0xffffffUL)   /*!< SD_RSP76 (Bitfield-Mask: 0xffffff)                    */
41670 /* ========================================================  SD_RSP7  ======================================================== */
41671  #define R_SDHI0_SD_RSP7_SD_RSP7_Pos             (0UL)          /*!< SD_RSP7 (Bit 0)                                       */
41672  #define R_SDHI0_SD_RSP7_SD_RSP7_Msk             (0xffUL)       /*!< SD_RSP7 (Bitfield-Mask: 0xff)                         */
41673 /* =======================================================  SD_INFO1  ======================================================== */
41674  #define R_SDHI0_SD_INFO1_SDD3MON_Pos            (10UL)         /*!< SDD3MON (Bit 10)                                      */
41675  #define R_SDHI0_SD_INFO1_SDD3MON_Msk            (0x400UL)      /*!< SDD3MON (Bitfield-Mask: 0x01)                         */
41676  #define R_SDHI0_SD_INFO1_SDD3IN_Pos             (9UL)          /*!< SDD3IN (Bit 9)                                        */
41677  #define R_SDHI0_SD_INFO1_SDD3IN_Msk             (0x200UL)      /*!< SDD3IN (Bitfield-Mask: 0x01)                          */
41678  #define R_SDHI0_SD_INFO1_SDD3RM_Pos             (8UL)          /*!< SDD3RM (Bit 8)                                        */
41679  #define R_SDHI0_SD_INFO1_SDD3RM_Msk             (0x100UL)      /*!< SDD3RM (Bitfield-Mask: 0x01)                          */
41680  #define R_SDHI0_SD_INFO1_SDWPMON_Pos            (7UL)          /*!< SDWPMON (Bit 7)                                       */
41681  #define R_SDHI0_SD_INFO1_SDWPMON_Msk            (0x80UL)       /*!< SDWPMON (Bitfield-Mask: 0x01)                         */
41682  #define R_SDHI0_SD_INFO1_SDCDMON_Pos            (5UL)          /*!< SDCDMON (Bit 5)                                       */
41683  #define R_SDHI0_SD_INFO1_SDCDMON_Msk            (0x20UL)       /*!< SDCDMON (Bitfield-Mask: 0x01)                         */
41684  #define R_SDHI0_SD_INFO1_SDCDIN_Pos             (4UL)          /*!< SDCDIN (Bit 4)                                        */
41685  #define R_SDHI0_SD_INFO1_SDCDIN_Msk             (0x10UL)       /*!< SDCDIN (Bitfield-Mask: 0x01)                          */
41686  #define R_SDHI0_SD_INFO1_SDCDRM_Pos             (3UL)          /*!< SDCDRM (Bit 3)                                        */
41687  #define R_SDHI0_SD_INFO1_SDCDRM_Msk             (0x8UL)        /*!< SDCDRM (Bitfield-Mask: 0x01)                          */
41688  #define R_SDHI0_SD_INFO1_ACEND_Pos              (2UL)          /*!< ACEND (Bit 2)                                         */
41689  #define R_SDHI0_SD_INFO1_ACEND_Msk              (0x4UL)        /*!< ACEND (Bitfield-Mask: 0x01)                           */
41690  #define R_SDHI0_SD_INFO1_RSPEND_Pos             (0UL)          /*!< RSPEND (Bit 0)                                        */
41691  #define R_SDHI0_SD_INFO1_RSPEND_Msk             (0x1UL)        /*!< RSPEND (Bitfield-Mask: 0x01)                          */
41692 /* =======================================================  SD_INFO2  ======================================================== */
41693  #define R_SDHI0_SD_INFO2_ILA_Pos                (15UL)         /*!< ILA (Bit 15)                                          */
41694  #define R_SDHI0_SD_INFO2_ILA_Msk                (0x8000UL)     /*!< ILA (Bitfield-Mask: 0x01)                             */
41695  #define R_SDHI0_SD_INFO2_CBSY_Pos               (14UL)         /*!< CBSY (Bit 14)                                         */
41696  #define R_SDHI0_SD_INFO2_CBSY_Msk               (0x4000UL)     /*!< CBSY (Bitfield-Mask: 0x01)                            */
41697  #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos      (13UL)         /*!< SD_CLK_CTRLEN (Bit 13)                                */
41698  #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk      (0x2000UL)     /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01)                   */
41699  #define R_SDHI0_SD_INFO2_BWE_Pos                (9UL)          /*!< BWE (Bit 9)                                           */
41700  #define R_SDHI0_SD_INFO2_BWE_Msk                (0x200UL)      /*!< BWE (Bitfield-Mask: 0x01)                             */
41701  #define R_SDHI0_SD_INFO2_BRE_Pos                (8UL)          /*!< BRE (Bit 8)                                           */
41702  #define R_SDHI0_SD_INFO2_BRE_Msk                (0x100UL)      /*!< BRE (Bitfield-Mask: 0x01)                             */
41703  #define R_SDHI0_SD_INFO2_SDD0MON_Pos            (7UL)          /*!< SDD0MON (Bit 7)                                       */
41704  #define R_SDHI0_SD_INFO2_SDD0MON_Msk            (0x80UL)       /*!< SDD0MON (Bitfield-Mask: 0x01)                         */
41705  #define R_SDHI0_SD_INFO2_RSPTO_Pos              (6UL)          /*!< RSPTO (Bit 6)                                         */
41706  #define R_SDHI0_SD_INFO2_RSPTO_Msk              (0x40UL)       /*!< RSPTO (Bitfield-Mask: 0x01)                           */
41707  #define R_SDHI0_SD_INFO2_ILR_Pos                (5UL)          /*!< ILR (Bit 5)                                           */
41708  #define R_SDHI0_SD_INFO2_ILR_Msk                (0x20UL)       /*!< ILR (Bitfield-Mask: 0x01)                             */
41709  #define R_SDHI0_SD_INFO2_ILW_Pos                (4UL)          /*!< ILW (Bit 4)                                           */
41710  #define R_SDHI0_SD_INFO2_ILW_Msk                (0x10UL)       /*!< ILW (Bitfield-Mask: 0x01)                             */
41711  #define R_SDHI0_SD_INFO2_DTO_Pos                (3UL)          /*!< DTO (Bit 3)                                           */
41712  #define R_SDHI0_SD_INFO2_DTO_Msk                (0x8UL)        /*!< DTO (Bitfield-Mask: 0x01)                             */
41713  #define R_SDHI0_SD_INFO2_ENDE_Pos               (2UL)          /*!< ENDE (Bit 2)                                          */
41714  #define R_SDHI0_SD_INFO2_ENDE_Msk               (0x4UL)        /*!< ENDE (Bitfield-Mask: 0x01)                            */
41715  #define R_SDHI0_SD_INFO2_CRCE_Pos               (1UL)          /*!< CRCE (Bit 1)                                          */
41716  #define R_SDHI0_SD_INFO2_CRCE_Msk               (0x2UL)        /*!< CRCE (Bitfield-Mask: 0x01)                            */
41717  #define R_SDHI0_SD_INFO2_CMDE_Pos               (0UL)          /*!< CMDE (Bit 0)                                          */
41718  #define R_SDHI0_SD_INFO2_CMDE_Msk               (0x1UL)        /*!< CMDE (Bitfield-Mask: 0x01)                            */
41719 /* =====================================================  SD_INFO1_MASK  ===================================================== */
41720  #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos       (9UL)          /*!< SDD3INM (Bit 9)                                       */
41721  #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk       (0x200UL)      /*!< SDD3INM (Bitfield-Mask: 0x01)                         */
41722  #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos       (8UL)          /*!< SDD3RMM (Bit 8)                                       */
41723  #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk       (0x100UL)      /*!< SDD3RMM (Bitfield-Mask: 0x01)                         */
41724  #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos       (4UL)          /*!< SDCDINM (Bit 4)                                       */
41725  #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk       (0x10UL)       /*!< SDCDINM (Bitfield-Mask: 0x01)                         */
41726  #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos       (3UL)          /*!< SDCDRMM (Bit 3)                                       */
41727  #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk       (0x8UL)        /*!< SDCDRMM (Bitfield-Mask: 0x01)                         */
41728  #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos        (2UL)          /*!< ACENDM (Bit 2)                                        */
41729  #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk        (0x4UL)        /*!< ACENDM (Bitfield-Mask: 0x01)                          */
41730  #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos       (0UL)          /*!< RSPENDM (Bit 0)                                       */
41731  #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk       (0x1UL)        /*!< RSPENDM (Bitfield-Mask: 0x01)                         */
41732 /* =====================================================  SD_INFO2_MASK  ===================================================== */
41733  #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos          (15UL)         /*!< ILAM (Bit 15)                                         */
41734  #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk          (0x8000UL)     /*!< ILAM (Bitfield-Mask: 0x01)                            */
41735  #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos          (9UL)          /*!< BWEM (Bit 9)                                          */
41736  #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk          (0x200UL)      /*!< BWEM (Bitfield-Mask: 0x01)                            */
41737  #define R_SDHI0_SD_INFO2_MASK_BREM_Pos          (8UL)          /*!< BREM (Bit 8)                                          */
41738  #define R_SDHI0_SD_INFO2_MASK_BREM_Msk          (0x100UL)      /*!< BREM (Bitfield-Mask: 0x01)                            */
41739  #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos        (6UL)          /*!< RSPTOM (Bit 6)                                        */
41740  #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk        (0x40UL)       /*!< RSPTOM (Bitfield-Mask: 0x01)                          */
41741  #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos          (5UL)          /*!< ILRM (Bit 5)                                          */
41742  #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk          (0x20UL)       /*!< ILRM (Bitfield-Mask: 0x01)                            */
41743  #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos          (4UL)          /*!< ILWM (Bit 4)                                          */
41744  #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk          (0x10UL)       /*!< ILWM (Bitfield-Mask: 0x01)                            */
41745  #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos          (3UL)          /*!< DTOM (Bit 3)                                          */
41746  #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk          (0x8UL)        /*!< DTOM (Bitfield-Mask: 0x01)                            */
41747  #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos         (2UL)          /*!< ENDEM (Bit 2)                                         */
41748  #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk         (0x4UL)        /*!< ENDEM (Bitfield-Mask: 0x01)                           */
41749  #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos         (1UL)          /*!< CRCEM (Bit 1)                                         */
41750  #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk         (0x2UL)        /*!< CRCEM (Bitfield-Mask: 0x01)                           */
41751  #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos         (0UL)          /*!< CMDEM (Bit 0)                                         */
41752  #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk         (0x1UL)        /*!< CMDEM (Bitfield-Mask: 0x01)                           */
41753 /* ======================================================  SD_CLK_CTRL  ====================================================== */
41754  #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos       (9UL)          /*!< CLKCTRLEN (Bit 9)                                     */
41755  #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk       (0x200UL)      /*!< CLKCTRLEN (Bitfield-Mask: 0x01)                       */
41756  #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos           (8UL)          /*!< CLKEN (Bit 8)                                         */
41757  #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk           (0x100UL)      /*!< CLKEN (Bitfield-Mask: 0x01)                           */
41758  #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos          (0UL)          /*!< CLKSEL (Bit 0)                                        */
41759  #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk          (0xffUL)       /*!< CLKSEL (Bitfield-Mask: 0xff)                          */
41760 /* ========================================================  SD_SIZE  ======================================================== */
41761  #define R_SDHI0_SD_SIZE_LEN_Pos                 (0UL)          /*!< LEN (Bit 0)                                           */
41762  #define R_SDHI0_SD_SIZE_LEN_Msk                 (0x3ffUL)      /*!< LEN (Bitfield-Mask: 0x3ff)                            */
41763 /* =======================================================  SD_OPTION  ======================================================= */
41764  #define R_SDHI0_SD_OPTION_WIDTH_Pos             (15UL)         /*!< WIDTH (Bit 15)                                        */
41765  #define R_SDHI0_SD_OPTION_WIDTH_Msk             (0x8000UL)     /*!< WIDTH (Bitfield-Mask: 0x01)                           */
41766  #define R_SDHI0_SD_OPTION_WIDTH8_Pos            (13UL)         /*!< WIDTH8 (Bit 13)                                       */
41767  #define R_SDHI0_SD_OPTION_WIDTH8_Msk            (0x2000UL)     /*!< WIDTH8 (Bitfield-Mask: 0x01)                          */
41768  #define R_SDHI0_SD_OPTION_TOUTMASK_Pos          (8UL)          /*!< TOUTMASK (Bit 8)                                      */
41769  #define R_SDHI0_SD_OPTION_TOUTMASK_Msk          (0x100UL)      /*!< TOUTMASK (Bitfield-Mask: 0x01)                        */
41770  #define R_SDHI0_SD_OPTION_TOP_Pos               (4UL)          /*!< TOP (Bit 4)                                           */
41771  #define R_SDHI0_SD_OPTION_TOP_Msk               (0xf0UL)       /*!< TOP (Bitfield-Mask: 0x0f)                             */
41772  #define R_SDHI0_SD_OPTION_CTOP_Pos              (0UL)          /*!< CTOP (Bit 0)                                          */
41773  #define R_SDHI0_SD_OPTION_CTOP_Msk              (0xfUL)        /*!< CTOP (Bitfield-Mask: 0x0f)                            */
41774 /* ======================================================  SD_ERR_STS1  ====================================================== */
41775  #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos           (12UL)         /*!< CRCTK (Bit 12)                                        */
41776  #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk           (0x7000UL)     /*!< CRCTK (Bitfield-Mask: 0x07)                           */
41777  #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos          (11UL)         /*!< CRCTKE (Bit 11)                                       */
41778  #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk          (0x800UL)      /*!< CRCTKE (Bitfield-Mask: 0x01)                          */
41779  #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos          (10UL)         /*!< RDCRCE (Bit 10)                                       */
41780  #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk          (0x400UL)      /*!< RDCRCE (Bitfield-Mask: 0x01)                          */
41781  #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos        (9UL)          /*!< RSPCRCE1 (Bit 9)                                      */
41782  #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk        (0x200UL)      /*!< RSPCRCE1 (Bitfield-Mask: 0x01)                        */
41783  #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos        (8UL)          /*!< RSPCRCE0 (Bit 8)                                      */
41784  #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk        (0x100UL)      /*!< RSPCRCE0 (Bitfield-Mask: 0x01)                        */
41785  #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos         (5UL)          /*!< CRCLENE (Bit 5)                                       */
41786  #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk         (0x20UL)       /*!< CRCLENE (Bitfield-Mask: 0x01)                         */
41787  #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos          (4UL)          /*!< RDLENE (Bit 4)                                        */
41788  #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk          (0x10UL)       /*!< RDLENE (Bitfield-Mask: 0x01)                          */
41789  #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos        (3UL)          /*!< RSPLENE1 (Bit 3)                                      */
41790  #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk        (0x8UL)        /*!< RSPLENE1 (Bitfield-Mask: 0x01)                        */
41791  #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos        (2UL)          /*!< RSPLENE0 (Bit 2)                                      */
41792  #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk        (0x4UL)        /*!< RSPLENE0 (Bitfield-Mask: 0x01)                        */
41793  #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos           (1UL)          /*!< CMDE1 (Bit 1)                                         */
41794  #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk           (0x2UL)        /*!< CMDE1 (Bitfield-Mask: 0x01)                           */
41795  #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos           (0UL)          /*!< CMDE0 (Bit 0)                                         */
41796  #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk           (0x1UL)        /*!< CMDE0 (Bitfield-Mask: 0x01)                           */
41797 /* ======================================================  SD_ERR_STS2  ====================================================== */
41798  #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos        (6UL)          /*!< CRCBSYTO (Bit 6)                                      */
41799  #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk        (0x40UL)       /*!< CRCBSYTO (Bitfield-Mask: 0x01)                        */
41800  #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos           (5UL)          /*!< CRCTO (Bit 5)                                         */
41801  #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk           (0x20UL)       /*!< CRCTO (Bitfield-Mask: 0x01)                           */
41802  #define R_SDHI0_SD_ERR_STS2_RDTO_Pos            (4UL)          /*!< RDTO (Bit 4)                                          */
41803  #define R_SDHI0_SD_ERR_STS2_RDTO_Msk            (0x10UL)       /*!< RDTO (Bitfield-Mask: 0x01)                            */
41804  #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos          (3UL)          /*!< BSYTO1 (Bit 3)                                        */
41805  #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk          (0x8UL)        /*!< BSYTO1 (Bitfield-Mask: 0x01)                          */
41806  #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos          (2UL)          /*!< BSYTO0 (Bit 2)                                        */
41807  #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk          (0x4UL)        /*!< BSYTO0 (Bitfield-Mask: 0x01)                          */
41808  #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos          (1UL)          /*!< RSPTO1 (Bit 1)                                        */
41809  #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk          (0x2UL)        /*!< RSPTO1 (Bitfield-Mask: 0x01)                          */
41810  #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos          (0UL)          /*!< RSPTO0 (Bit 0)                                        */
41811  #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk          (0x1UL)        /*!< RSPTO0 (Bitfield-Mask: 0x01)                          */
41812 /* ========================================================  SD_BUF0  ======================================================== */
41813  #define R_SDHI0_SD_BUF0_SD_BUF_Pos              (0UL)          /*!< SD_BUF (Bit 0)                                        */
41814  #define R_SDHI0_SD_BUF0_SD_BUF_Msk              (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff)                    */
41815 /* =======================================================  SDIO_MODE  ======================================================= */
41816  #define R_SDHI0_SDIO_MODE_C52PUB_Pos            (9UL)          /*!< C52PUB (Bit 9)                                        */
41817  #define R_SDHI0_SDIO_MODE_C52PUB_Msk            (0x200UL)      /*!< C52PUB (Bitfield-Mask: 0x01)                          */
41818  #define R_SDHI0_SDIO_MODE_IOABT_Pos             (8UL)          /*!< IOABT (Bit 8)                                         */
41819  #define R_SDHI0_SDIO_MODE_IOABT_Msk             (0x100UL)      /*!< IOABT (Bitfield-Mask: 0x01)                           */
41820  #define R_SDHI0_SDIO_MODE_RWREQ_Pos             (2UL)          /*!< RWREQ (Bit 2)                                         */
41821  #define R_SDHI0_SDIO_MODE_RWREQ_Msk             (0x4UL)        /*!< RWREQ (Bitfield-Mask: 0x01)                           */
41822  #define R_SDHI0_SDIO_MODE_INTEN_Pos             (0UL)          /*!< INTEN (Bit 0)                                         */
41823  #define R_SDHI0_SDIO_MODE_INTEN_Msk             (0x1UL)        /*!< INTEN (Bitfield-Mask: 0x01)                           */
41824 /* ======================================================  SDIO_INFO1  ======================================================= */
41825  #define R_SDHI0_SDIO_INFO1_EXWT_Pos             (15UL)         /*!< EXWT (Bit 15)                                         */
41826  #define R_SDHI0_SDIO_INFO1_EXWT_Msk             (0x8000UL)     /*!< EXWT (Bitfield-Mask: 0x01)                            */
41827  #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos          (14UL)         /*!< EXPUB52 (Bit 14)                                      */
41828  #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk          (0x4000UL)     /*!< EXPUB52 (Bitfield-Mask: 0x01)                         */
41829  #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos            (0UL)          /*!< IOIRQ (Bit 0)                                         */
41830  #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk            (0x1UL)        /*!< IOIRQ (Bitfield-Mask: 0x01)                           */
41831 /* ====================================================  SDIO_INFO1_MASK  ==================================================== */
41832  #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos       (15UL)         /*!< EXWTM (Bit 15)                                        */
41833  #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk       (0x8000UL)     /*!< EXWTM (Bitfield-Mask: 0x01)                           */
41834  #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos    (14UL)         /*!< EXPUB52M (Bit 14)                                     */
41835  #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk    (0x4000UL)     /*!< EXPUB52M (Bitfield-Mask: 0x01)                        */
41836  #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos      (0UL)          /*!< IOIRQM (Bit 0)                                        */
41837  #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk      (0x1UL)        /*!< IOIRQM (Bitfield-Mask: 0x01)                          */
41838 /* =======================================================  SD_DMAEN  ======================================================== */
41839  #define R_SDHI0_SD_DMAEN_DMAEN_Pos              (1UL)          /*!< DMAEN (Bit 1)                                         */
41840  #define R_SDHI0_SD_DMAEN_DMAEN_Msk              (0x2UL)        /*!< DMAEN (Bitfield-Mask: 0x01)                           */
41841 /* =======================================================  SOFT_RST  ======================================================== */
41842  #define R_SDHI0_SOFT_RST_SDRST_Pos              (0UL)          /*!< SDRST (Bit 0)                                         */
41843  #define R_SDHI0_SOFT_RST_SDRST_Msk              (0x1UL)        /*!< SDRST (Bitfield-Mask: 0x01)                           */
41844 /* =======================================================  SDIF_MODE  ======================================================= */
41845  #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos           (8UL)          /*!< NOCHKCR (Bit 8)                                       */
41846  #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk           (0x100UL)      /*!< NOCHKCR (Bitfield-Mask: 0x01)                         */
41847 /* =======================================================  EXT_SWAP  ======================================================== */
41848  #define R_SDHI0_EXT_SWAP_BRSWP_Pos              (7UL)          /*!< BRSWP (Bit 7)                                         */
41849  #define R_SDHI0_EXT_SWAP_BRSWP_Msk              (0x80UL)       /*!< BRSWP (Bitfield-Mask: 0x01)                           */
41850  #define R_SDHI0_EXT_SWAP_BWSWP_Pos              (6UL)          /*!< BWSWP (Bit 6)                                         */
41851  #define R_SDHI0_EXT_SWAP_BWSWP_Msk              (0x40UL)       /*!< BWSWP (Bitfield-Mask: 0x01)                           */
41852 
41853 /* =========================================================================================================================== */
41854 /* ================                                          R_SLCDC                                          ================ */
41855 /* =========================================================================================================================== */
41856 
41857 /* =========================================================  LCDM0  ========================================================= */
41858  #define R_SLCDC_LCDM0_MDSET_Pos     (6UL)    /*!< MDSET (Bit 6)                                         */
41859  #define R_SLCDC_LCDM0_MDSET_Msk     (0xc0UL) /*!< MDSET (Bitfield-Mask: 0x03)                           */
41860  #define R_SLCDC_LCDM0_LWAVE_Pos     (5UL)    /*!< LWAVE (Bit 5)                                         */
41861  #define R_SLCDC_LCDM0_LWAVE_Msk     (0x20UL) /*!< LWAVE (Bitfield-Mask: 0x01)                           */
41862  #define R_SLCDC_LCDM0_LDTY_Pos      (2UL)    /*!< LDTY (Bit 2)                                          */
41863  #define R_SLCDC_LCDM0_LDTY_Msk      (0x1cUL) /*!< LDTY (Bitfield-Mask: 0x07)                            */
41864  #define R_SLCDC_LCDM0_LBAS_Pos      (0UL)    /*!< LBAS (Bit 0)                                          */
41865  #define R_SLCDC_LCDM0_LBAS_Msk      (0x3UL)  /*!< LBAS (Bitfield-Mask: 0x03)                            */
41866 /* =========================================================  LCDM1  ========================================================= */
41867  #define R_SLCDC_LCDM1_LCDON_Pos     (7UL)    /*!< LCDON (Bit 7)                                         */
41868  #define R_SLCDC_LCDM1_LCDON_Msk     (0x80UL) /*!< LCDON (Bitfield-Mask: 0x01)                           */
41869  #define R_SLCDC_LCDM1_SCOC_Pos      (6UL)    /*!< SCOC (Bit 6)                                          */
41870  #define R_SLCDC_LCDM1_SCOC_Msk      (0x40UL) /*!< SCOC (Bitfield-Mask: 0x01)                            */
41871  #define R_SLCDC_LCDM1_VLCON_Pos     (5UL)    /*!< VLCON (Bit 5)                                         */
41872  #define R_SLCDC_LCDM1_VLCON_Msk     (0x20UL) /*!< VLCON (Bitfield-Mask: 0x01)                           */
41873  #define R_SLCDC_LCDM1_BLON_Pos      (4UL)    /*!< BLON (Bit 4)                                          */
41874  #define R_SLCDC_LCDM1_BLON_Msk      (0x10UL) /*!< BLON (Bitfield-Mask: 0x01)                            */
41875  #define R_SLCDC_LCDM1_LCDSEL_Pos    (3UL)    /*!< LCDSEL (Bit 3)                                        */
41876  #define R_SLCDC_LCDM1_LCDSEL_Msk    (0x8UL)  /*!< LCDSEL (Bitfield-Mask: 0x01)                          */
41877  #define R_SLCDC_LCDM1_LCDVLM_Pos    (0UL)    /*!< LCDVLM (Bit 0)                                        */
41878  #define R_SLCDC_LCDM1_LCDVLM_Msk    (0x1UL)  /*!< LCDVLM (Bitfield-Mask: 0x01)                          */
41879 /* =========================================================  LCDC0  ========================================================= */
41880  #define R_SLCDC_LCDC0_LCDC_Pos      (0UL)    /*!< LCDC (Bit 0)                                          */
41881  #define R_SLCDC_LCDC0_LCDC_Msk      (0x3fUL) /*!< LCDC (Bitfield-Mask: 0x3f)                            */
41882 /* =========================================================  VLCD  ========================================================== */
41883  #define R_SLCDC_VLCD_VLCD_Pos       (0UL)    /*!< VLCD (Bit 0)                                          */
41884  #define R_SLCDC_VLCD_VLCD_Msk       (0x1fUL) /*!< VLCD (Bitfield-Mask: 0x1f)                            */
41885 /* ==========================================================  SEG  ========================================================== */
41886  #define R_SLCDC_SEG_A_Pos           (0UL)    /*!< A (Bit 0)                                             */
41887  #define R_SLCDC_SEG_A_Msk           (0xfUL)  /*!< A (Bitfield-Mask: 0x0f)                               */
41888  #define R_SLCDC_SEG_B_Pos           (4UL)    /*!< B (Bit 4)                                             */
41889  #define R_SLCDC_SEG_B_Msk           (0xf0UL) /*!< B (Bitfield-Mask: 0x0f)                               */
41890 
41891 /* =========================================================================================================================== */
41892 /* ================                                          R_SPI0                                           ================ */
41893 /* =========================================================================================================================== */
41894 
41895 /* =========================================================  SPCR  ========================================================== */
41896  #define R_SPI0_SPCR_SPRIE_Pos      (7UL)    /*!< SPRIE (Bit 7)                                         */
41897  #define R_SPI0_SPCR_SPRIE_Msk      (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01)                           */
41898  #define R_SPI0_SPCR_SPE_Pos        (6UL)    /*!< SPE (Bit 6)                                           */
41899  #define R_SPI0_SPCR_SPE_Msk        (0x40UL) /*!< SPE (Bitfield-Mask: 0x01)                             */
41900  #define R_SPI0_SPCR_SPTIE_Pos      (5UL)    /*!< SPTIE (Bit 5)                                         */
41901  #define R_SPI0_SPCR_SPTIE_Msk      (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01)                           */
41902  #define R_SPI0_SPCR_SPEIE_Pos      (4UL)    /*!< SPEIE (Bit 4)                                         */
41903  #define R_SPI0_SPCR_SPEIE_Msk      (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01)                           */
41904  #define R_SPI0_SPCR_MSTR_Pos       (3UL)    /*!< MSTR (Bit 3)                                          */
41905  #define R_SPI0_SPCR_MSTR_Msk       (0x8UL)  /*!< MSTR (Bitfield-Mask: 0x01)                            */
41906  #define R_SPI0_SPCR_MODFEN_Pos     (2UL)    /*!< MODFEN (Bit 2)                                        */
41907  #define R_SPI0_SPCR_MODFEN_Msk     (0x4UL)  /*!< MODFEN (Bitfield-Mask: 0x01)                          */
41908  #define R_SPI0_SPCR_TXMD_Pos       (1UL)    /*!< TXMD (Bit 1)                                          */
41909  #define R_SPI0_SPCR_TXMD_Msk       (0x2UL)  /*!< TXMD (Bitfield-Mask: 0x01)                            */
41910  #define R_SPI0_SPCR_SPMS_Pos       (0UL)    /*!< SPMS (Bit 0)                                          */
41911  #define R_SPI0_SPCR_SPMS_Msk       (0x1UL)  /*!< SPMS (Bitfield-Mask: 0x01)                            */
41912 /* =========================================================  SSLP  ========================================================== */
41913  #define R_SPI0_SSLP_SSL3P_Pos      (3UL)    /*!< SSL3P (Bit 3)                                         */
41914  #define R_SPI0_SSLP_SSL3P_Msk      (0x8UL)  /*!< SSL3P (Bitfield-Mask: 0x01)                           */
41915  #define R_SPI0_SSLP_SSL2P_Pos      (2UL)    /*!< SSL2P (Bit 2)                                         */
41916  #define R_SPI0_SSLP_SSL2P_Msk      (0x4UL)  /*!< SSL2P (Bitfield-Mask: 0x01)                           */
41917  #define R_SPI0_SSLP_SSL1P_Pos      (1UL)    /*!< SSL1P (Bit 1)                                         */
41918  #define R_SPI0_SSLP_SSL1P_Msk      (0x2UL)  /*!< SSL1P (Bitfield-Mask: 0x01)                           */
41919  #define R_SPI0_SSLP_SSL0P_Pos      (0UL)    /*!< SSL0P (Bit 0)                                         */
41920  #define R_SPI0_SSLP_SSL0P_Msk      (0x1UL)  /*!< SSL0P (Bitfield-Mask: 0x01)                           */
41921  #define R_SPI0_SSLP_SSL4P_Pos      (4UL)    /*!< SSL4P (Bit 4)                                         */
41922  #define R_SPI0_SSLP_SSL4P_Msk      (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01)                           */
41923  #define R_SPI0_SSLP_SSL5P_Pos      (5UL)    /*!< SSL5P (Bit 5)                                         */
41924  #define R_SPI0_SSLP_SSL5P_Msk      (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01)                           */
41925  #define R_SPI0_SSLP_SSL6P_Pos      (6UL)    /*!< SSL6P (Bit 6)                                         */
41926  #define R_SPI0_SSLP_SSL6P_Msk      (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01)                           */
41927  #define R_SPI0_SSLP_SSL7P_Pos      (7UL)    /*!< SSL7P (Bit 7)                                         */
41928  #define R_SPI0_SSLP_SSL7P_Msk      (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01)                           */
41929 /* =========================================================  SPPCR  ========================================================= */
41930  #define R_SPI0_SPPCR_MOIFE_Pos     (5UL)    /*!< MOIFE (Bit 5)                                         */
41931  #define R_SPI0_SPPCR_MOIFE_Msk     (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01)                           */
41932  #define R_SPI0_SPPCR_MOIFV_Pos     (4UL)    /*!< MOIFV (Bit 4)                                         */
41933  #define R_SPI0_SPPCR_MOIFV_Msk     (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01)                           */
41934  #define R_SPI0_SPPCR_SPLP2_Pos     (1UL)    /*!< SPLP2 (Bit 1)                                         */
41935  #define R_SPI0_SPPCR_SPLP2_Msk     (0x2UL)  /*!< SPLP2 (Bitfield-Mask: 0x01)                           */
41936  #define R_SPI0_SPPCR_SPLP_Pos      (0UL)    /*!< SPLP (Bit 0)                                          */
41937  #define R_SPI0_SPPCR_SPLP_Msk      (0x1UL)  /*!< SPLP (Bitfield-Mask: 0x01)                            */
41938 /* =========================================================  SPSR  ========================================================== */
41939  #define R_SPI0_SPSR_SPRF_Pos       (7UL)    /*!< SPRF (Bit 7)                                          */
41940  #define R_SPI0_SPSR_SPRF_Msk       (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01)                            */
41941  #define R_SPI0_SPSR_SPTEF_Pos      (5UL)    /*!< SPTEF (Bit 5)                                         */
41942  #define R_SPI0_SPSR_SPTEF_Msk      (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01)                           */
41943  #define R_SPI0_SPSR_UDRF_Pos       (4UL)    /*!< UDRF (Bit 4)                                          */
41944  #define R_SPI0_SPSR_UDRF_Msk       (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01)                            */
41945  #define R_SPI0_SPSR_PERF_Pos       (3UL)    /*!< PERF (Bit 3)                                          */
41946  #define R_SPI0_SPSR_PERF_Msk       (0x8UL)  /*!< PERF (Bitfield-Mask: 0x01)                            */
41947  #define R_SPI0_SPSR_MODF_Pos       (2UL)    /*!< MODF (Bit 2)                                          */
41948  #define R_SPI0_SPSR_MODF_Msk       (0x4UL)  /*!< MODF (Bitfield-Mask: 0x01)                            */
41949  #define R_SPI0_SPSR_IDLNF_Pos      (1UL)    /*!< IDLNF (Bit 1)                                         */
41950  #define R_SPI0_SPSR_IDLNF_Msk      (0x2UL)  /*!< IDLNF (Bitfield-Mask: 0x01)                           */
41951  #define R_SPI0_SPSR_OVRF_Pos       (0UL)    /*!< OVRF (Bit 0)                                          */
41952  #define R_SPI0_SPSR_OVRF_Msk       (0x1UL)  /*!< OVRF (Bitfield-Mask: 0x01)                            */
41953  #define R_SPI0_SPSR_CENDF_Pos      (6UL)    /*!< CENDF (Bit 6)                                         */
41954  #define R_SPI0_SPSR_CENDF_Msk      (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01)                           */
41955 /* =========================================================  SPDR  ========================================================== */
41956 /* ========================================================  SPDR_HA  ======================================================== */
41957 /* ========================================================  SPDR_BY  ======================================================== */
41958 /* =========================================================  SPSCR  ========================================================= */
41959  #define R_SPI0_SPSCR_SPSLN_Pos     (0UL)      /*!< SPSLN (Bit 0)                                         */
41960  #define R_SPI0_SPSCR_SPSLN_Msk     (0x7UL)    /*!< SPSLN (Bitfield-Mask: 0x07)                           */
41961 /* =========================================================  SPBR  ========================================================== */
41962  #define R_SPI0_SPBR_SPR_Pos        (0UL)      /*!< SPR (Bit 0)                                           */
41963  #define R_SPI0_SPBR_SPR_Msk        (0xffUL)   /*!< SPR (Bitfield-Mask: 0xff)                             */
41964 /* =========================================================  SPDCR  ========================================================= */
41965  #define R_SPI0_SPDCR_SPBYT_Pos     (6UL)      /*!< SPBYT (Bit 6)                                         */
41966  #define R_SPI0_SPDCR_SPBYT_Msk     (0x40UL)   /*!< SPBYT (Bitfield-Mask: 0x01)                           */
41967  #define R_SPI0_SPDCR_SPLW_Pos      (5UL)      /*!< SPLW (Bit 5)                                          */
41968  #define R_SPI0_SPDCR_SPLW_Msk      (0x20UL)   /*!< SPLW (Bitfield-Mask: 0x01)                            */
41969  #define R_SPI0_SPDCR_SPRDTD_Pos    (4UL)      /*!< SPRDTD (Bit 4)                                        */
41970  #define R_SPI0_SPDCR_SPRDTD_Msk    (0x10UL)   /*!< SPRDTD (Bitfield-Mask: 0x01)                          */
41971  #define R_SPI0_SPDCR_SPFC_Pos      (0UL)      /*!< SPFC (Bit 0)                                          */
41972  #define R_SPI0_SPDCR_SPFC_Msk      (0x3UL)    /*!< SPFC (Bitfield-Mask: 0x03)                            */
41973  #define R_SPI0_SPDCR_SLSEL_Pos     (2UL)      /*!< SLSEL (Bit 2)                                         */
41974  #define R_SPI0_SPDCR_SLSEL_Msk     (0xcUL)    /*!< SLSEL (Bitfield-Mask: 0x03)                           */
41975 /* =========================================================  SPCKD  ========================================================= */
41976  #define R_SPI0_SPCKD_SCKDL_Pos     (0UL)      /*!< SCKDL (Bit 0)                                         */
41977  #define R_SPI0_SPCKD_SCKDL_Msk     (0x7UL)    /*!< SCKDL (Bitfield-Mask: 0x07)                           */
41978 /* =========================================================  SSLND  ========================================================= */
41979  #define R_SPI0_SSLND_SLNDL_Pos     (0UL)      /*!< SLNDL (Bit 0)                                         */
41980  #define R_SPI0_SSLND_SLNDL_Msk     (0x7UL)    /*!< SLNDL (Bitfield-Mask: 0x07)                           */
41981 /* =========================================================  SPND  ========================================================== */
41982  #define R_SPI0_SPND_SPNDL_Pos      (0UL)      /*!< SPNDL (Bit 0)                                         */
41983  #define R_SPI0_SPND_SPNDL_Msk      (0x7UL)    /*!< SPNDL (Bitfield-Mask: 0x07)                           */
41984 /* =========================================================  SPCR2  ========================================================= */
41985  #define R_SPI0_SPCR2_SCKASE_Pos    (4UL)      /*!< SCKASE (Bit 4)                                        */
41986  #define R_SPI0_SPCR2_SCKASE_Msk    (0x10UL)   /*!< SCKASE (Bitfield-Mask: 0x01)                          */
41987  #define R_SPI0_SPCR2_PTE_Pos       (3UL)      /*!< PTE (Bit 3)                                           */
41988  #define R_SPI0_SPCR2_PTE_Msk       (0x8UL)    /*!< PTE (Bitfield-Mask: 0x01)                             */
41989  #define R_SPI0_SPCR2_SPIIE_Pos     (2UL)      /*!< SPIIE (Bit 2)                                         */
41990  #define R_SPI0_SPCR2_SPIIE_Msk     (0x4UL)    /*!< SPIIE (Bitfield-Mask: 0x01)                           */
41991  #define R_SPI0_SPCR2_SPOE_Pos      (1UL)      /*!< SPOE (Bit 1)                                          */
41992  #define R_SPI0_SPCR2_SPOE_Msk      (0x2UL)    /*!< SPOE (Bitfield-Mask: 0x01)                            */
41993  #define R_SPI0_SPCR2_SPPE_Pos      (0UL)      /*!< SPPE (Bit 0)                                          */
41994  #define R_SPI0_SPCR2_SPPE_Msk      (0x1UL)    /*!< SPPE (Bitfield-Mask: 0x01)                            */
41995  #define R_SPI0_SPCR2_SPTDDL_Pos    (5UL)      /*!< SPTDDL (Bit 5)                                        */
41996  #define R_SPI0_SPCR2_SPTDDL_Msk    (0xe0UL)   /*!< SPTDDL (Bitfield-Mask: 0x07)                          */
41997 /* =========================================================  SPCMD  ========================================================= */
41998  #define R_SPI0_SPCMD_SCKDEN_Pos    (15UL)     /*!< SCKDEN (Bit 15)                                       */
41999  #define R_SPI0_SPCMD_SCKDEN_Msk    (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
42000  #define R_SPI0_SPCMD_SLNDEN_Pos    (14UL)     /*!< SLNDEN (Bit 14)                                       */
42001  #define R_SPI0_SPCMD_SLNDEN_Msk    (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
42002  #define R_SPI0_SPCMD_SPNDEN_Pos    (13UL)     /*!< SPNDEN (Bit 13)                                       */
42003  #define R_SPI0_SPCMD_SPNDEN_Msk    (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
42004  #define R_SPI0_SPCMD_LSBF_Pos      (12UL)     /*!< LSBF (Bit 12)                                         */
42005  #define R_SPI0_SPCMD_LSBF_Msk      (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01)                            */
42006  #define R_SPI0_SPCMD_SPB_Pos       (8UL)      /*!< SPB (Bit 8)                                           */
42007  #define R_SPI0_SPCMD_SPB_Msk       (0xf00UL)  /*!< SPB (Bitfield-Mask: 0x0f)                             */
42008  #define R_SPI0_SPCMD_SSLKP_Pos     (7UL)      /*!< SSLKP (Bit 7)                                         */
42009  #define R_SPI0_SPCMD_SSLKP_Msk     (0x80UL)   /*!< SSLKP (Bitfield-Mask: 0x01)                           */
42010  #define R_SPI0_SPCMD_SSLA_Pos      (4UL)      /*!< SSLA (Bit 4)                                          */
42011  #define R_SPI0_SPCMD_SSLA_Msk      (0x70UL)   /*!< SSLA (Bitfield-Mask: 0x07)                            */
42012  #define R_SPI0_SPCMD_BRDV_Pos      (2UL)      /*!< BRDV (Bit 2)                                          */
42013  #define R_SPI0_SPCMD_BRDV_Msk      (0xcUL)    /*!< BRDV (Bitfield-Mask: 0x03)                            */
42014  #define R_SPI0_SPCMD_CPOL_Pos      (1UL)      /*!< CPOL (Bit 1)                                          */
42015  #define R_SPI0_SPCMD_CPOL_Msk      (0x2UL)    /*!< CPOL (Bitfield-Mask: 0x01)                            */
42016  #define R_SPI0_SPCMD_CPHA_Pos      (0UL)      /*!< CPHA (Bit 0)                                          */
42017  #define R_SPI0_SPCMD_CPHA_Msk      (0x1UL)    /*!< CPHA (Bitfield-Mask: 0x01)                            */
42018 /* ========================================================  SPDCR2  ========================================================= */
42019  #define R_SPI0_SPDCR2_BYSW_Pos     (0UL)      /*!< BYSW (Bit 0)                                          */
42020  #define R_SPI0_SPDCR2_BYSW_Msk     (0x1UL)    /*!< BYSW (Bitfield-Mask: 0x01)                            */
42021  #define R_SPI0_SPDCR2_SINV_Pos     (1UL)      /*!< SINV (Bit 1)                                          */
42022  #define R_SPI0_SPDCR2_SINV_Msk     (0x2UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
42023 /* =========================================================  SPSSR  ========================================================= */
42024  #define R_SPI0_SPSSR_SPCP_Pos      (0UL)      /*!< SPCP (Bit 0)                                          */
42025  #define R_SPI0_SPSSR_SPCP_Msk      (0x7UL)    /*!< SPCP (Bitfield-Mask: 0x07)                            */
42026  #define R_SPI0_SPSSR_SPECM_Pos     (4UL)      /*!< SPECM (Bit 4)                                         */
42027  #define R_SPI0_SPSSR_SPECM_Msk     (0x70UL)   /*!< SPECM (Bitfield-Mask: 0x07)                           */
42028 /* =========================================================  SPCR3  ========================================================= */
42029  #define R_SPI0_SPCR3_ETXMD_Pos     (0UL)      /*!< ETXMD (Bit 0)                                         */
42030  #define R_SPI0_SPCR3_ETXMD_Msk     (0x1UL)    /*!< ETXMD (Bitfield-Mask: 0x01)                           */
42031  #define R_SPI0_SPCR3_BFDS_Pos      (1UL)      /*!< BFDS (Bit 1)                                          */
42032  #define R_SPI0_SPCR3_BFDS_Msk      (0x2UL)    /*!< BFDS (Bitfield-Mask: 0x01)                            */
42033  #define R_SPI0_SPCR3_CENDIE_Pos    (4UL)      /*!< CENDIE (Bit 4)                                        */
42034  #define R_SPI0_SPCR3_CENDIE_Msk    (0x10UL)   /*!< CENDIE (Bitfield-Mask: 0x01)                          */
42035 /* =========================================================  SPPR  ========================================================== */
42036  #define R_SPI0_SPPR_BUFWID_Pos     (4UL)      /*!< BUFWID (Bit 4)                                        */
42037  #define R_SPI0_SPPR_BUFWID_Msk     (0x10UL)   /*!< BUFWID (Bitfield-Mask: 0x01)                          */
42038  #define R_SPI0_SPPR_BUFNUM_Pos     (8UL)      /*!< BUFNUM (Bit 8)                                        */
42039  #define R_SPI0_SPPR_BUFNUM_Msk     (0x700UL)  /*!< BUFNUM (Bitfield-Mask: 0x07)                          */
42040  #define R_SPI0_SPPR_CMDNUM_Pos     (12UL)     /*!< CMDNUM (Bit 12)                                       */
42041  #define R_SPI0_SPPR_CMDNUM_Msk     (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f)                          */
42042 
42043 /* =========================================================================================================================== */
42044 /* ================                                          R_SRAM                                           ================ */
42045 /* =========================================================================================================================== */
42046 
42047 /* ========================================================  PARIOAD  ======================================================== */
42048  #define R_SRAM_PARIOAD_OAD_Pos            (0UL)    /*!< OAD (Bit 0)                                           */
42049  #define R_SRAM_PARIOAD_OAD_Msk            (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
42050 /* =======================================================  SRAMPRCR  ======================================================== */
42051  #define R_SRAM_SRAMPRCR_KW_Pos            (1UL)    /*!< KW (Bit 1)                                            */
42052  #define R_SRAM_SRAMPRCR_KW_Msk            (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
42053  #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos      (0UL)    /*!< SRAMPRCR (Bit 0)                                      */
42054  #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk      (0x1UL)  /*!< SRAMPRCR (Bitfield-Mask: 0x01)                        */
42055 /* =======================================================  SRAMWTSC  ======================================================== */
42056 /* ========================================================  ECCMODE  ======================================================== */
42057  #define R_SRAM_ECCMODE_ECCMOD_Pos         (0UL)    /*!< ECCMOD (Bit 0)                                        */
42058  #define R_SRAM_ECCMODE_ECCMOD_Msk         (0x3UL)  /*!< ECCMOD (Bitfield-Mask: 0x03)                          */
42059 /* ========================================================  ECC2STS  ======================================================== */
42060  #define R_SRAM_ECC2STS_ECC2ERR_Pos        (0UL)    /*!< ECC2ERR (Bit 0)                                       */
42061  #define R_SRAM_ECC2STS_ECC2ERR_Msk        (0x1UL)  /*!< ECC2ERR (Bitfield-Mask: 0x01)                         */
42062 /* =======================================================  ECC1STSEN  ======================================================= */
42063  #define R_SRAM_ECC1STSEN_E1STSEN_Pos      (0UL)    /*!< E1STSEN (Bit 0)                                       */
42064  #define R_SRAM_ECC1STSEN_E1STSEN_Msk      (0x1UL)  /*!< E1STSEN (Bitfield-Mask: 0x01)                         */
42065 /* ========================================================  ECC1STS  ======================================================== */
42066  #define R_SRAM_ECC1STS_ECC1ERR_Pos        (0UL)    /*!< ECC1ERR (Bit 0)                                       */
42067  #define R_SRAM_ECC1STS_ECC1ERR_Msk        (0x1UL)  /*!< ECC1ERR (Bitfield-Mask: 0x01)                         */
42068 /* ========================================================  ECCPRCR  ======================================================== */
42069  #define R_SRAM_ECCPRCR_KW_Pos             (1UL)    /*!< KW (Bit 1)                                            */
42070  #define R_SRAM_ECCPRCR_KW_Msk             (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
42071  #define R_SRAM_ECCPRCR_ECCPRCR_Pos        (0UL)    /*!< ECCPRCR (Bit 0)                                       */
42072  #define R_SRAM_ECCPRCR_ECCPRCR_Msk        (0x1UL)  /*!< ECCPRCR (Bitfield-Mask: 0x01)                         */
42073 /* =======================================================  ECCPRCR2  ======================================================== */
42074  #define R_SRAM_ECCPRCR2_KW2_Pos           (1UL)    /*!< KW2 (Bit 1)                                           */
42075  #define R_SRAM_ECCPRCR2_KW2_Msk           (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f)                             */
42076  #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos      (0UL)    /*!< ECCPRCR2 (Bit 0)                                      */
42077  #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk      (0x1UL)  /*!< ECCPRCR2 (Bitfield-Mask: 0x01)                        */
42078 /* ========================================================  ECCETST  ======================================================== */
42079  #define R_SRAM_ECCETST_TSTBYP_Pos         (0UL)    /*!< TSTBYP (Bit 0)                                        */
42080  #define R_SRAM_ECCETST_TSTBYP_Msk         (0x1UL)  /*!< TSTBYP (Bitfield-Mask: 0x01)                          */
42081 /* ========================================================  ECCOAD  ========================================================= */
42082  #define R_SRAM_ECCOAD_OAD_Pos             (0UL)    /*!< OAD (Bit 0)                                           */
42083  #define R_SRAM_ECCOAD_OAD_Msk             (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
42084 /* =======================================================  SRAMPRCR2  ======================================================= */
42085  #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos    (0UL)    /*!< SRAMPRCR2 (Bit 0)                                     */
42086  #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk    (0x1UL)  /*!< SRAMPRCR2 (Bitfield-Mask: 0x01)                       */
42087  #define R_SRAM_SRAMPRCR2_KW_Pos           (1UL)    /*!< KW (Bit 1)                                            */
42088  #define R_SRAM_SRAMPRCR2_KW_Msk           (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
42089 
42090 /* =========================================================================================================================== */
42091 /* ================                                          R_BUS_B                                          ================ */
42092 /* =========================================================================================================================== */
42093 
42094 /* =====================================================  BUSSCNTFHBIU  ====================================================== */
42095  #define R_BUS_B_BUSSCNTFHBIU_ARBS_Pos           (0UL)     /*!< ARBS (Bit 0)                                          */
42096  #define R_BUS_B_BUSSCNTFHBIU_ARBS_Msk           (0x3UL)   /*!< ARBS (Bitfield-Mask: 0x03)                            */
42097 /* =====================================================  BUSSCNTFLBIU  ====================================================== */
42098  #define R_BUS_B_BUSSCNTFLBIU_ARBS_Pos           (0UL)     /*!< ARBS (Bit 0)                                          */
42099  #define R_BUS_B_BUSSCNTFLBIU_ARBS_Msk           (0x3UL)   /*!< ARBS (Bitfield-Mask: 0x03)                            */
42100 /* =====================================================  BUSSCNTS0BIU  ====================================================== */
42101  #define R_BUS_B_BUSSCNTS0BIU_ARBS_Pos           (0UL)     /*!< ARBS (Bit 0)                                          */
42102  #define R_BUS_B_BUSSCNTS0BIU_ARBS_Msk           (0x3UL)   /*!< ARBS (Bitfield-Mask: 0x03)                            */
42103 /* =====================================================  BUSSCNTPSBIU  ====================================================== */
42104  #define R_BUS_B_BUSSCNTPSBIU_ARBS_Pos           (0UL)     /*!< ARBS (Bit 0)                                          */
42105  #define R_BUS_B_BUSSCNTPSBIU_ARBS_Msk           (0x1UL)   /*!< ARBS (Bitfield-Mask: 0x01)                            */
42106 /* =====================================================  BUSSCNTPLBIU  ====================================================== */
42107  #define R_BUS_B_BUSSCNTPLBIU_ARBS_Pos           (0UL)     /*!< ARBS (Bit 0)                                          */
42108  #define R_BUS_B_BUSSCNTPLBIU_ARBS_Msk           (0x1UL)   /*!< ARBS (Bitfield-Mask: 0x01)                            */
42109 /* =====================================================  BUSSCNTPHBIU  ====================================================== */
42110  #define R_BUS_B_BUSSCNTPHBIU_ARBS_Pos           (0UL)     /*!< ARBS (Bit 0)                                          */
42111  #define R_BUS_B_BUSSCNTPHBIU_ARBS_Msk           (0x1UL)   /*!< ARBS (Bitfield-Mask: 0x01)                            */
42112 /* =====================================================  BUSSCNTEQBIU  ====================================================== */
42113  #define R_BUS_B_BUSSCNTEQBIU_ARBS_Pos           (0UL)     /*!< ARBS (Bit 0)                                          */
42114  #define R_BUS_B_BUSSCNTEQBIU_ARBS_Msk           (0x3UL)   /*!< ARBS (Bitfield-Mask: 0x03)                            */
42115 /* =====================================================  BUSSCNTEOBIU  ====================================================== */
42116  #define R_BUS_B_BUSSCNTEOBIU_ARBS_Pos           (0UL)     /*!< ARBS (Bit 0)                                          */
42117  #define R_BUS_B_BUSSCNTEOBIU_ARBS_Msk           (0x3UL)   /*!< ARBS (Bitfield-Mask: 0x03)                            */
42118 /* =====================================================  BUSSCNTECBIU  ====================================================== */
42119  #define R_BUS_B_BUSSCNTECBIU_ARBS_Pos           (0UL)     /*!< ARBS (Bit 0)                                          */
42120  #define R_BUS_B_BUSSCNTECBIU_ARBS_Msk           (0x3UL)   /*!< ARBS (Bitfield-Mask: 0x03)                            */
42121 /* ======================================================  BUS1ERRSTAT  ====================================================== */
42122  #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Pos       (0UL)     /*!< SLERRSTAT (Bit 0)                                     */
42123  #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Msk       (0x1UL)   /*!< SLERRSTAT (Bitfield-Mask: 0x01)                       */
42124  #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Pos       (1UL)     /*!< STERRSTAT (Bit 1)                                     */
42125  #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Msk       (0x2UL)   /*!< STERRSTAT (Bitfield-Mask: 0x01)                       */
42126  #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Pos       (3UL)     /*!< MMERRSTAT (Bit 3)                                     */
42127  #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Msk       (0x8UL)   /*!< MMERRSTAT (Bitfield-Mask: 0x01)                       */
42128  #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Pos       (4UL)     /*!< ILERRSTAT (Bit 4)                                     */
42129  #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Msk       (0x10UL)  /*!< ILERRSTAT (Bitfield-Mask: 0x01)                       */
42130 /* ======================================================  BUS2ERRSTAT  ====================================================== */
42131  #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Pos       (0UL)     /*!< SLERRSTAT (Bit 0)                                     */
42132  #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Msk       (0x1UL)   /*!< SLERRSTAT (Bitfield-Mask: 0x01)                       */
42133  #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Pos       (1UL)     /*!< STERRSTAT (Bit 1)                                     */
42134  #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Msk       (0x2UL)   /*!< STERRSTAT (Bitfield-Mask: 0x01)                       */
42135  #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Pos       (3UL)     /*!< MMERRSTAT (Bit 3)                                     */
42136  #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Msk       (0x8UL)   /*!< MMERRSTAT (Bitfield-Mask: 0x01)                       */
42137  #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Pos       (4UL)     /*!< ILERRSTAT (Bit 4)                                     */
42138  #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Msk       (0x10UL)  /*!< ILERRSTAT (Bitfield-Mask: 0x01)                       */
42139 /* ======================================================  BUS3ERRSTAT  ====================================================== */
42140  #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Pos       (0UL)     /*!< SLERRSTAT (Bit 0)                                     */
42141  #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Msk       (0x1UL)   /*!< SLERRSTAT (Bitfield-Mask: 0x01)                       */
42142  #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Pos       (1UL)     /*!< STERRSTAT (Bit 1)                                     */
42143  #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Msk       (0x2UL)   /*!< STERRSTAT (Bitfield-Mask: 0x01)                       */
42144  #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Pos       (3UL)     /*!< MMERRSTAT (Bit 3)                                     */
42145  #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Msk       (0x8UL)   /*!< MMERRSTAT (Bitfield-Mask: 0x01)                       */
42146  #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Pos       (4UL)     /*!< ILERRSTAT (Bit 4)                                     */
42147  #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Msk       (0x10UL)  /*!< ILERRSTAT (Bitfield-Mask: 0x01)                       */
42148 /* ======================================================  BUS4ERRSTAT  ====================================================== */
42149  #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Pos       (0UL)     /*!< SLERRSTAT (Bit 0)                                     */
42150  #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Msk       (0x1UL)   /*!< SLERRSTAT (Bitfield-Mask: 0x01)                       */
42151  #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Pos       (1UL)     /*!< STERRSTAT (Bit 1)                                     */
42152  #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Msk       (0x2UL)   /*!< STERRSTAT (Bitfield-Mask: 0x01)                       */
42153  #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Pos       (3UL)     /*!< MMERRSTAT (Bit 3)                                     */
42154  #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Msk       (0x8UL)   /*!< MMERRSTAT (Bitfield-Mask: 0x01)                       */
42155  #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Pos       (4UL)     /*!< ILERRSTAT (Bit 4)                                     */
42156  #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Msk       (0x10UL)  /*!< ILERRSTAT (Bitfield-Mask: 0x01)                       */
42157 /* ======================================================  BUS1ERRCLR  ======================================================= */
42158  #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Pos         (0UL)     /*!< SLERRCLR (Bit 0)                                      */
42159  #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Msk         (0x1UL)   /*!< SLERRCLR (Bitfield-Mask: 0x01)                        */
42160  #define R_BUS_B_BUS1ERRCLR_STERRCLR_Pos         (1UL)     /*!< STERRCLR (Bit 1)                                      */
42161  #define R_BUS_B_BUS1ERRCLR_STERRCLR_Msk         (0x2UL)   /*!< STERRCLR (Bitfield-Mask: 0x01)                        */
42162  #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Pos         (3UL)     /*!< MMERRCLR (Bit 3)                                      */
42163  #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Msk         (0x8UL)   /*!< MMERRCLR (Bitfield-Mask: 0x01)                        */
42164  #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Pos         (4UL)     /*!< ILERRCLR (Bit 4)                                      */
42165  #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Msk         (0x10UL)  /*!< ILERRCLR (Bitfield-Mask: 0x01)                        */
42166 /* ======================================================  BUS2ERRCLR  ======================================================= */
42167  #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Pos         (0UL)     /*!< SLERRCLR (Bit 0)                                      */
42168  #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Msk         (0x1UL)   /*!< SLERRCLR (Bitfield-Mask: 0x01)                        */
42169  #define R_BUS_B_BUS2ERRCLR_STERRCLR_Pos         (1UL)     /*!< STERRCLR (Bit 1)                                      */
42170  #define R_BUS_B_BUS2ERRCLR_STERRCLR_Msk         (0x2UL)   /*!< STERRCLR (Bitfield-Mask: 0x01)                        */
42171  #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Pos         (3UL)     /*!< MMERRCLR (Bit 3)                                      */
42172  #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Msk         (0x8UL)   /*!< MMERRCLR (Bitfield-Mask: 0x01)                        */
42173  #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Pos         (4UL)     /*!< ILERRCLR (Bit 4)                                      */
42174  #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Msk         (0x10UL)  /*!< ILERRCLR (Bitfield-Mask: 0x01)                        */
42175 /* ======================================================  BUS3ERRCLR  ======================================================= */
42176  #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Pos         (0UL)     /*!< SLERRCLR (Bit 0)                                      */
42177  #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Msk         (0x1UL)   /*!< SLERRCLR (Bitfield-Mask: 0x01)                        */
42178  #define R_BUS_B_BUS3ERRCLR_STERRCLR_Pos         (1UL)     /*!< STERRCLR (Bit 1)                                      */
42179  #define R_BUS_B_BUS3ERRCLR_STERRCLR_Msk         (0x2UL)   /*!< STERRCLR (Bitfield-Mask: 0x01)                        */
42180  #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Pos         (3UL)     /*!< MMERRCLR (Bit 3)                                      */
42181  #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Msk         (0x8UL)   /*!< MMERRCLR (Bitfield-Mask: 0x01)                        */
42182  #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Pos         (4UL)     /*!< ILERRCLR (Bit 4)                                      */
42183  #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Msk         (0x10UL)  /*!< ILERRCLR (Bitfield-Mask: 0x01)                        */
42184 /* ======================================================  BUS4ERRCLR  ======================================================= */
42185  #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Pos         (0UL)     /*!< SLERRCLR (Bit 0)                                      */
42186  #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Msk         (0x1UL)   /*!< SLERRCLR (Bitfield-Mask: 0x01)                        */
42187  #define R_BUS_B_BUS4ERRCLR_STERRCLR_Pos         (1UL)     /*!< STERRCLR (Bit 1)                                      */
42188  #define R_BUS_B_BUS4ERRCLR_STERRCLR_Msk         (0x2UL)   /*!< STERRCLR (Bitfield-Mask: 0x01)                        */
42189  #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Pos         (3UL)     /*!< MMERRCLR (Bit 3)                                      */
42190  #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Msk         (0x8UL)   /*!< MMERRCLR (Bitfield-Mask: 0x01)                        */
42191  #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Pos         (4UL)     /*!< ILERRCLR (Bit 4)                                      */
42192  #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Msk         (0x10UL)  /*!< ILERRCLR (Bitfield-Mask: 0x01)                        */
42193 /* ====================================================  DMACDTCERRSTAT  ===================================================== */
42194  #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Pos    (0UL)     /*!< MTERRSTAT (Bit 0)                                     */
42195  #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Msk    (0x1UL)   /*!< MTERRSTAT (Bitfield-Mask: 0x01)                       */
42196 /* =====================================================  DMACDTCERRCLR  ===================================================== */
42197  #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Pos      (0UL)     /*!< MTERRCLR (Bit 0)                                      */
42198  #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Msk      (0x1UL)   /*!< MTERRCLR (Bitfield-Mask: 0x01)                        */
42199 /* ========================================================  CSRECEN  ======================================================== */
42200  #define R_BUS_B_CSRECEN_RCVENM_Pos              (8UL)     /*!< RCVENM (Bit 8)                                        */
42201  #define R_BUS_B_CSRECEN_RCVENM_Msk              (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01)                          */
42202  #define R_BUS_B_CSRECEN_RCVEN_Pos               (0UL)     /*!< RCVEN (Bit 0)                                         */
42203  #define R_BUS_B_CSRECEN_RCVEN_Msk               (0x1UL)   /*!< RCVEN (Bitfield-Mask: 0x01)                           */
42204 
42205 /* =========================================================================================================================== */
42206 /* ================                                           R_SRC                                           ================ */
42207 /* =========================================================================================================================== */
42208 
42209 /* ========================================================  SRCFCTR  ======================================================== */
42210  #define R_SRC_SRCFCTR_SRCFCOE_Pos    (0UL)          /*!< SRCFCOE (Bit 0)                                       */
42211  #define R_SRC_SRCFCTR_SRCFCOE_Msk    (0x3fffffUL)   /*!< SRCFCOE (Bitfield-Mask: 0x3fffff)                     */
42212 /* =========================================================  SRCID  ========================================================= */
42213  #define R_SRC_SRCID_SRCID_Pos        (0UL)          /*!< SRCID (Bit 0)                                         */
42214  #define R_SRC_SRCID_SRCID_Msk        (0xffffffffUL) /*!< SRCID (Bitfield-Mask: 0xffffffff)                     */
42215 /* =========================================================  SRCOD  ========================================================= */
42216  #define R_SRC_SRCOD_SRCOD_Pos        (0UL)          /*!< SRCOD (Bit 0)                                         */
42217  #define R_SRC_SRCOD_SRCOD_Msk        (0xffffffffUL) /*!< SRCOD (Bitfield-Mask: 0xffffffff)                     */
42218 /* =======================================================  SRCIDCTRL  ======================================================= */
42219  #define R_SRC_SRCIDCTRL_IED_Pos      (9UL)          /*!< IED (Bit 9)                                           */
42220  #define R_SRC_SRCIDCTRL_IED_Msk      (0x200UL)      /*!< IED (Bitfield-Mask: 0x01)                             */
42221  #define R_SRC_SRCIDCTRL_IEN_Pos      (8UL)          /*!< IEN (Bit 8)                                           */
42222  #define R_SRC_SRCIDCTRL_IEN_Msk      (0x100UL)      /*!< IEN (Bitfield-Mask: 0x01)                             */
42223  #define R_SRC_SRCIDCTRL_IFTRG_Pos    (0UL)          /*!< IFTRG (Bit 0)                                         */
42224  #define R_SRC_SRCIDCTRL_IFTRG_Msk    (0x3UL)        /*!< IFTRG (Bitfield-Mask: 0x03)                           */
42225 /* ========================================================  SRCCTRL  ======================================================== */
42226  #define R_SRC_SRCCTRL_FICRAE_Pos     (15UL)         /*!< FICRAE (Bit 15)                                       */
42227  #define R_SRC_SRCCTRL_FICRAE_Msk     (0x8000UL)     /*!< FICRAE (Bitfield-Mask: 0x01)                          */
42228  #define R_SRC_SRCCTRL_CEEN_Pos       (13UL)         /*!< CEEN (Bit 13)                                         */
42229  #define R_SRC_SRCCTRL_CEEN_Msk       (0x2000UL)     /*!< CEEN (Bitfield-Mask: 0x01)                            */
42230  #define R_SRC_SRCCTRL_SRCEN_Pos      (12UL)         /*!< SRCEN (Bit 12)                                        */
42231  #define R_SRC_SRCCTRL_SRCEN_Msk      (0x1000UL)     /*!< SRCEN (Bitfield-Mask: 0x01)                           */
42232  #define R_SRC_SRCCTRL_UDEN_Pos       (11UL)         /*!< UDEN (Bit 11)                                         */
42233  #define R_SRC_SRCCTRL_UDEN_Msk       (0x800UL)      /*!< UDEN (Bitfield-Mask: 0x01)                            */
42234  #define R_SRC_SRCCTRL_OVEN_Pos       (10UL)         /*!< OVEN (Bit 10)                                         */
42235  #define R_SRC_SRCCTRL_OVEN_Msk       (0x400UL)      /*!< OVEN (Bitfield-Mask: 0x01)                            */
42236  #define R_SRC_SRCCTRL_FL_Pos         (9UL)          /*!< FL (Bit 9)                                            */
42237  #define R_SRC_SRCCTRL_FL_Msk         (0x200UL)      /*!< FL (Bitfield-Mask: 0x01)                              */
42238  #define R_SRC_SRCCTRL_CL_Pos         (8UL)          /*!< CL (Bit 8)                                            */
42239  #define R_SRC_SRCCTRL_CL_Msk         (0x100UL)      /*!< CL (Bitfield-Mask: 0x01)                              */
42240  #define R_SRC_SRCCTRL_IFS_Pos        (4UL)          /*!< IFS (Bit 4)                                           */
42241  #define R_SRC_SRCCTRL_IFS_Msk        (0xf0UL)       /*!< IFS (Bitfield-Mask: 0x0f)                             */
42242  #define R_SRC_SRCCTRL_OFS_Pos        (0UL)          /*!< OFS (Bit 0)                                           */
42243  #define R_SRC_SRCCTRL_OFS_Msk        (0x7UL)        /*!< OFS (Bitfield-Mask: 0x07)                             */
42244 /* =======================================================  SRCODCTRL  ======================================================= */
42245  #define R_SRC_SRCODCTRL_OCH_Pos      (10UL)         /*!< OCH (Bit 10)                                          */
42246  #define R_SRC_SRCODCTRL_OCH_Msk      (0x400UL)      /*!< OCH (Bitfield-Mask: 0x01)                             */
42247  #define R_SRC_SRCODCTRL_OED_Pos      (9UL)          /*!< OED (Bit 9)                                           */
42248  #define R_SRC_SRCODCTRL_OED_Msk      (0x200UL)      /*!< OED (Bitfield-Mask: 0x01)                             */
42249  #define R_SRC_SRCODCTRL_OEN_Pos      (8UL)          /*!< OEN (Bit 8)                                           */
42250  #define R_SRC_SRCODCTRL_OEN_Msk      (0x100UL)      /*!< OEN (Bitfield-Mask: 0x01)                             */
42251  #define R_SRC_SRCODCTRL_OFTRG_Pos    (0UL)          /*!< OFTRG (Bit 0)                                         */
42252  #define R_SRC_SRCODCTRL_OFTRG_Msk    (0x3UL)        /*!< OFTRG (Bitfield-Mask: 0x03)                           */
42253 /* ========================================================  SRCSTAT  ======================================================== */
42254  #define R_SRC_SRCSTAT_OFDN_Pos       (11UL)         /*!< OFDN (Bit 11)                                         */
42255  #define R_SRC_SRCSTAT_OFDN_Msk       (0xf800UL)     /*!< OFDN (Bitfield-Mask: 0x1f)                            */
42256  #define R_SRC_SRCSTAT_IFDN_Pos       (7UL)          /*!< IFDN (Bit 7)                                          */
42257  #define R_SRC_SRCSTAT_IFDN_Msk       (0x780UL)      /*!< IFDN (Bitfield-Mask: 0x0f)                            */
42258  #define R_SRC_SRCSTAT_CEF_Pos        (5UL)          /*!< CEF (Bit 5)                                           */
42259  #define R_SRC_SRCSTAT_CEF_Msk        (0x20UL)       /*!< CEF (Bitfield-Mask: 0x01)                             */
42260  #define R_SRC_SRCSTAT_FLF_Pos        (4UL)          /*!< FLF (Bit 4)                                           */
42261  #define R_SRC_SRCSTAT_FLF_Msk        (0x10UL)       /*!< FLF (Bitfield-Mask: 0x01)                             */
42262  #define R_SRC_SRCSTAT_UDF_Pos        (3UL)          /*!< UDF (Bit 3)                                           */
42263  #define R_SRC_SRCSTAT_UDF_Msk        (0x8UL)        /*!< UDF (Bitfield-Mask: 0x01)                             */
42264  #define R_SRC_SRCSTAT_OVF_Pos        (2UL)          /*!< OVF (Bit 2)                                           */
42265  #define R_SRC_SRCSTAT_OVF_Msk        (0x4UL)        /*!< OVF (Bitfield-Mask: 0x01)                             */
42266  #define R_SRC_SRCSTAT_IINT_Pos       (1UL)          /*!< IINT (Bit 1)                                          */
42267  #define R_SRC_SRCSTAT_IINT_Msk       (0x2UL)        /*!< IINT (Bitfield-Mask: 0x01)                            */
42268  #define R_SRC_SRCSTAT_OINT_Pos       (0UL)          /*!< OINT (Bit 0)                                          */
42269  #define R_SRC_SRCSTAT_OINT_Msk       (0x1UL)        /*!< OINT (Bitfield-Mask: 0x01)                            */
42270 
42271 /* =========================================================================================================================== */
42272 /* ================                                          R_SSI0                                           ================ */
42273 /* =========================================================================================================================== */
42274 
42275 /* =========================================================  SSICR  ========================================================= */
42276  #define R_SSI0_SSICR_CKS_Pos          (30UL)         /*!< CKS (Bit 30)                                          */
42277  #define R_SSI0_SSICR_CKS_Msk          (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01)                             */
42278  #define R_SSI0_SSICR_TUIEN_Pos        (29UL)         /*!< TUIEN (Bit 29)                                        */
42279  #define R_SSI0_SSICR_TUIEN_Msk        (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01)                           */
42280  #define R_SSI0_SSICR_TOIEN_Pos        (28UL)         /*!< TOIEN (Bit 28)                                        */
42281  #define R_SSI0_SSICR_TOIEN_Msk        (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01)                           */
42282  #define R_SSI0_SSICR_RUIEN_Pos        (27UL)         /*!< RUIEN (Bit 27)                                        */
42283  #define R_SSI0_SSICR_RUIEN_Msk        (0x8000000UL)  /*!< RUIEN (Bitfield-Mask: 0x01)                           */
42284  #define R_SSI0_SSICR_ROIEN_Pos        (26UL)         /*!< ROIEN (Bit 26)                                        */
42285  #define R_SSI0_SSICR_ROIEN_Msk        (0x4000000UL)  /*!< ROIEN (Bitfield-Mask: 0x01)                           */
42286  #define R_SSI0_SSICR_IIEN_Pos         (25UL)         /*!< IIEN (Bit 25)                                         */
42287  #define R_SSI0_SSICR_IIEN_Msk         (0x2000000UL)  /*!< IIEN (Bitfield-Mask: 0x01)                            */
42288  #define R_SSI0_SSICR_FRM_Pos          (22UL)         /*!< FRM (Bit 22)                                          */
42289  #define R_SSI0_SSICR_FRM_Msk          (0xc00000UL)   /*!< FRM (Bitfield-Mask: 0x03)                             */
42290  #define R_SSI0_SSICR_DWL_Pos          (19UL)         /*!< DWL (Bit 19)                                          */
42291  #define R_SSI0_SSICR_DWL_Msk          (0x380000UL)   /*!< DWL (Bitfield-Mask: 0x07)                             */
42292  #define R_SSI0_SSICR_SWL_Pos          (16UL)         /*!< SWL (Bit 16)                                          */
42293  #define R_SSI0_SSICR_SWL_Msk          (0x70000UL)    /*!< SWL (Bitfield-Mask: 0x07)                             */
42294  #define R_SSI0_SSICR_MST_Pos          (14UL)         /*!< MST (Bit 14)                                          */
42295  #define R_SSI0_SSICR_MST_Msk          (0x4000UL)     /*!< MST (Bitfield-Mask: 0x01)                             */
42296  #define R_SSI0_SSICR_BCKP_Pos         (13UL)         /*!< BCKP (Bit 13)                                         */
42297  #define R_SSI0_SSICR_BCKP_Msk         (0x2000UL)     /*!< BCKP (Bitfield-Mask: 0x01)                            */
42298  #define R_SSI0_SSICR_LRCKP_Pos        (12UL)         /*!< LRCKP (Bit 12)                                        */
42299  #define R_SSI0_SSICR_LRCKP_Msk        (0x1000UL)     /*!< LRCKP (Bitfield-Mask: 0x01)                           */
42300  #define R_SSI0_SSICR_SPDP_Pos         (11UL)         /*!< SPDP (Bit 11)                                         */
42301  #define R_SSI0_SSICR_SPDP_Msk         (0x800UL)      /*!< SPDP (Bitfield-Mask: 0x01)                            */
42302  #define R_SSI0_SSICR_SDTA_Pos         (10UL)         /*!< SDTA (Bit 10)                                         */
42303  #define R_SSI0_SSICR_SDTA_Msk         (0x400UL)      /*!< SDTA (Bitfield-Mask: 0x01)                            */
42304  #define R_SSI0_SSICR_PDTA_Pos         (9UL)          /*!< PDTA (Bit 9)                                          */
42305  #define R_SSI0_SSICR_PDTA_Msk         (0x200UL)      /*!< PDTA (Bitfield-Mask: 0x01)                            */
42306  #define R_SSI0_SSICR_DEL_Pos          (8UL)          /*!< DEL (Bit 8)                                           */
42307  #define R_SSI0_SSICR_DEL_Msk          (0x100UL)      /*!< DEL (Bitfield-Mask: 0x01)                             */
42308  #define R_SSI0_SSICR_CKDV_Pos         (4UL)          /*!< CKDV (Bit 4)                                          */
42309  #define R_SSI0_SSICR_CKDV_Msk         (0xf0UL)       /*!< CKDV (Bitfield-Mask: 0x0f)                            */
42310  #define R_SSI0_SSICR_MUEN_Pos         (3UL)          /*!< MUEN (Bit 3)                                          */
42311  #define R_SSI0_SSICR_MUEN_Msk         (0x8UL)        /*!< MUEN (Bitfield-Mask: 0x01)                            */
42312  #define R_SSI0_SSICR_TEN_Pos          (1UL)          /*!< TEN (Bit 1)                                           */
42313  #define R_SSI0_SSICR_TEN_Msk          (0x2UL)        /*!< TEN (Bitfield-Mask: 0x01)                             */
42314  #define R_SSI0_SSICR_REN_Pos          (0UL)          /*!< REN (Bit 0)                                           */
42315  #define R_SSI0_SSICR_REN_Msk          (0x1UL)        /*!< REN (Bitfield-Mask: 0x01)                             */
42316 /* =========================================================  SSISR  ========================================================= */
42317  #define R_SSI0_SSISR_TUIRQ_Pos        (29UL)         /*!< TUIRQ (Bit 29)                                        */
42318  #define R_SSI0_SSISR_TUIRQ_Msk        (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01)                           */
42319  #define R_SSI0_SSISR_TOIRQ_Pos        (28UL)         /*!< TOIRQ (Bit 28)                                        */
42320  #define R_SSI0_SSISR_TOIRQ_Msk        (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01)                           */
42321  #define R_SSI0_SSISR_RUIRQ_Pos        (27UL)         /*!< RUIRQ (Bit 27)                                        */
42322  #define R_SSI0_SSISR_RUIRQ_Msk        (0x8000000UL)  /*!< RUIRQ (Bitfield-Mask: 0x01)                           */
42323  #define R_SSI0_SSISR_ROIRQ_Pos        (26UL)         /*!< ROIRQ (Bit 26)                                        */
42324  #define R_SSI0_SSISR_ROIRQ_Msk        (0x4000000UL)  /*!< ROIRQ (Bitfield-Mask: 0x01)                           */
42325  #define R_SSI0_SSISR_IIRQ_Pos         (25UL)         /*!< IIRQ (Bit 25)                                         */
42326  #define R_SSI0_SSISR_IIRQ_Msk         (0x2000000UL)  /*!< IIRQ (Bitfield-Mask: 0x01)                            */
42327  #define R_SSI0_SSISR_TCHNO_Pos        (5UL)          /*!< TCHNO (Bit 5)                                         */
42328  #define R_SSI0_SSISR_TCHNO_Msk        (0x60UL)       /*!< TCHNO (Bitfield-Mask: 0x03)                           */
42329  #define R_SSI0_SSISR_TSWNO_Pos        (4UL)          /*!< TSWNO (Bit 4)                                         */
42330  #define R_SSI0_SSISR_TSWNO_Msk        (0x10UL)       /*!< TSWNO (Bitfield-Mask: 0x01)                           */
42331  #define R_SSI0_SSISR_RCHNO_Pos        (2UL)          /*!< RCHNO (Bit 2)                                         */
42332  #define R_SSI0_SSISR_RCHNO_Msk        (0xcUL)        /*!< RCHNO (Bitfield-Mask: 0x03)                           */
42333  #define R_SSI0_SSISR_RSWNO_Pos        (1UL)          /*!< RSWNO (Bit 1)                                         */
42334  #define R_SSI0_SSISR_RSWNO_Msk        (0x2UL)        /*!< RSWNO (Bitfield-Mask: 0x01)                           */
42335  #define R_SSI0_SSISR_IDST_Pos         (0UL)          /*!< IDST (Bit 0)                                          */
42336  #define R_SSI0_SSISR_IDST_Msk         (0x1UL)        /*!< IDST (Bitfield-Mask: 0x01)                            */
42337 /* ========================================================  SSIFCR  ========================================================= */
42338  #define R_SSI0_SSIFCR_AUCKE_Pos       (31UL)         /*!< AUCKE (Bit 31)                                        */
42339  #define R_SSI0_SSIFCR_AUCKE_Msk       (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01)                           */
42340  #define R_SSI0_SSIFCR_SSIRST_Pos      (16UL)         /*!< SSIRST (Bit 16)                                       */
42341  #define R_SSI0_SSIFCR_SSIRST_Msk      (0x10000UL)    /*!< SSIRST (Bitfield-Mask: 0x01)                          */
42342  #define R_SSI0_SSIFCR_TTRG_Pos        (6UL)          /*!< TTRG (Bit 6)                                          */
42343  #define R_SSI0_SSIFCR_TTRG_Msk        (0xc0UL)       /*!< TTRG (Bitfield-Mask: 0x03)                            */
42344  #define R_SSI0_SSIFCR_RTRG_Pos        (4UL)          /*!< RTRG (Bit 4)                                          */
42345  #define R_SSI0_SSIFCR_RTRG_Msk        (0x30UL)       /*!< RTRG (Bitfield-Mask: 0x03)                            */
42346  #define R_SSI0_SSIFCR_TIE_Pos         (3UL)          /*!< TIE (Bit 3)                                           */
42347  #define R_SSI0_SSIFCR_TIE_Msk         (0x8UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
42348  #define R_SSI0_SSIFCR_RIE_Pos         (2UL)          /*!< RIE (Bit 2)                                           */
42349  #define R_SSI0_SSIFCR_RIE_Msk         (0x4UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
42350  #define R_SSI0_SSIFCR_TFRST_Pos       (1UL)          /*!< TFRST (Bit 1)                                         */
42351  #define R_SSI0_SSIFCR_TFRST_Msk       (0x2UL)        /*!< TFRST (Bitfield-Mask: 0x01)                           */
42352  #define R_SSI0_SSIFCR_RFRST_Pos       (0UL)          /*!< RFRST (Bit 0)                                         */
42353  #define R_SSI0_SSIFCR_RFRST_Msk       (0x1UL)        /*!< RFRST (Bitfield-Mask: 0x01)                           */
42354  #define R_SSI0_SSIFCR_BSW_Pos         (11UL)         /*!< BSW (Bit 11)                                          */
42355  #define R_SSI0_SSIFCR_BSW_Msk         (0x800UL)      /*!< BSW (Bitfield-Mask: 0x01)                             */
42356 /* ========================================================  SSIFSR  ========================================================= */
42357  #define R_SSI0_SSIFSR_TDC_Pos         (24UL)         /*!< TDC (Bit 24)                                          */
42358  #define R_SSI0_SSIFSR_TDC_Msk         (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f)                             */
42359  #define R_SSI0_SSIFSR_TDE_Pos         (16UL)         /*!< TDE (Bit 16)                                          */
42360  #define R_SSI0_SSIFSR_TDE_Msk         (0x10000UL)    /*!< TDE (Bitfield-Mask: 0x01)                             */
42361  #define R_SSI0_SSIFSR_RDC_Pos         (8UL)          /*!< RDC (Bit 8)                                           */
42362  #define R_SSI0_SSIFSR_RDC_Msk         (0x3f00UL)     /*!< RDC (Bitfield-Mask: 0x3f)                             */
42363  #define R_SSI0_SSIFSR_RDF_Pos         (0UL)          /*!< RDF (Bit 0)                                           */
42364  #define R_SSI0_SSIFSR_RDF_Msk         (0x1UL)        /*!< RDF (Bitfield-Mask: 0x01)                             */
42365 /* ========================================================  SSIFTDR  ======================================================== */
42366  #define R_SSI0_SSIFTDR_SSIFTDR_Pos    (0UL)          /*!< SSIFTDR (Bit 0)                                       */
42367  #define R_SSI0_SSIFTDR_SSIFTDR_Msk    (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff)                   */
42368 /* =======================================================  SSIFTDR16  ======================================================= */
42369 /* =======================================================  SSIFTDR8  ======================================================== */
42370 /* ========================================================  SSIFRDR  ======================================================== */
42371  #define R_SSI0_SSIFRDR_SSIFRDR_Pos    (0UL)          /*!< SSIFRDR (Bit 0)                                       */
42372  #define R_SSI0_SSIFRDR_SSIFRDR_Msk    (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff)                   */
42373 /* =======================================================  SSIFRDR16  ======================================================= */
42374 /* =======================================================  SSIFRDR8  ======================================================== */
42375 /* ========================================================  SSIOFR  ========================================================= */
42376  #define R_SSI0_SSIOFR_BCKASTP_Pos     (9UL)          /*!< BCKASTP (Bit 9)                                       */
42377  #define R_SSI0_SSIOFR_BCKASTP_Msk     (0x200UL)      /*!< BCKASTP (Bitfield-Mask: 0x01)                         */
42378  #define R_SSI0_SSIOFR_LRCONT_Pos      (8UL)          /*!< LRCONT (Bit 8)                                        */
42379  #define R_SSI0_SSIOFR_LRCONT_Msk      (0x100UL)      /*!< LRCONT (Bitfield-Mask: 0x01)                          */
42380  #define R_SSI0_SSIOFR_OMOD_Pos        (0UL)          /*!< OMOD (Bit 0)                                          */
42381  #define R_SSI0_SSIOFR_OMOD_Msk        (0x3UL)        /*!< OMOD (Bitfield-Mask: 0x03)                            */
42382 /* ========================================================  SSISCR  ========================================================= */
42383  #define R_SSI0_SSISCR_TDES_Pos        (8UL)          /*!< TDES (Bit 8)                                          */
42384  #define R_SSI0_SSISCR_TDES_Msk        (0x1f00UL)     /*!< TDES (Bitfield-Mask: 0x1f)                            */
42385  #define R_SSI0_SSISCR_RDFS_Pos        (0UL)          /*!< RDFS (Bit 0)                                          */
42386  #define R_SSI0_SSISCR_RDFS_Msk        (0x1fUL)       /*!< RDFS (Bitfield-Mask: 0x1f)                            */
42387 
42388 /* =========================================================================================================================== */
42389 /* ================                                         R_SYSTEM                                          ================ */
42390 /* =========================================================================================================================== */
42391 
42392 /* =========================================================  SBYCR  ========================================================= */
42393  #define R_SYSTEM_SBYCR_SSBY_Pos                   (15UL)         /*!< SSBY (Bit 15)                                         */
42394  #define R_SYSTEM_SBYCR_SSBY_Msk                   (0x8000UL)     /*!< SSBY (Bitfield-Mask: 0x01)                            */
42395  #define R_SYSTEM_SBYCR_OPE_Pos                    (14UL)         /*!< OPE (Bit 14)                                          */
42396  #define R_SYSTEM_SBYCR_OPE_Msk                    (0x4000UL)     /*!< OPE (Bitfield-Mask: 0x01)                             */
42397 /* ========================================================  MSTPCRA  ======================================================== */
42398  #define R_SYSTEM_MSTPCRA_MSTPA22_Pos              (22UL)         /*!< MSTPA22 (Bit 22)                                      */
42399  #define R_SYSTEM_MSTPCRA_MSTPA22_Msk              (0x400000UL)   /*!< MSTPA22 (Bitfield-Mask: 0x01)                         */
42400  #define R_SYSTEM_MSTPCRA_MSTPA7_Pos               (7UL)          /*!< MSTPA7 (Bit 7)                                        */
42401  #define R_SYSTEM_MSTPCRA_MSTPA7_Msk               (0x80UL)       /*!< MSTPA7 (Bitfield-Mask: 0x01)                          */
42402  #define R_SYSTEM_MSTPCRA_MSTPA6_Pos               (6UL)          /*!< MSTPA6 (Bit 6)                                        */
42403  #define R_SYSTEM_MSTPCRA_MSTPA6_Msk               (0x40UL)       /*!< MSTPA6 (Bitfield-Mask: 0x01)                          */
42404  #define R_SYSTEM_MSTPCRA_MSTPA5_Pos               (5UL)          /*!< MSTPA5 (Bit 5)                                        */
42405  #define R_SYSTEM_MSTPCRA_MSTPA5_Msk               (0x20UL)       /*!< MSTPA5 (Bitfield-Mask: 0x01)                          */
42406  #define R_SYSTEM_MSTPCRA_MSTPA1_Pos               (1UL)          /*!< MSTPA1 (Bit 1)                                        */
42407  #define R_SYSTEM_MSTPCRA_MSTPA1_Msk               (0x2UL)        /*!< MSTPA1 (Bitfield-Mask: 0x01)                          */
42408  #define R_SYSTEM_MSTPCRA_MSTPA0_Pos               (0UL)          /*!< MSTPA0 (Bit 0)                                        */
42409  #define R_SYSTEM_MSTPCRA_MSTPA0_Msk               (0x1UL)        /*!< MSTPA0 (Bitfield-Mask: 0x01)                          */
42410 /* =======================================================  SCKDIVCR  ======================================================== */
42411  #define R_SYSTEM_SCKDIVCR_FCK_Pos                 (28UL)         /*!< FCK (Bit 28)                                          */
42412  #define R_SYSTEM_SCKDIVCR_FCK_Msk                 (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07)                             */
42413  #define R_SYSTEM_SCKDIVCR_ICK_Pos                 (24UL)         /*!< ICK (Bit 24)                                          */
42414  #define R_SYSTEM_SCKDIVCR_ICK_Msk                 (0x7000000UL)  /*!< ICK (Bitfield-Mask: 0x07)                             */
42415  #define R_SYSTEM_SCKDIVCR_BCK_Pos                 (16UL)         /*!< BCK (Bit 16)                                          */
42416  #define R_SYSTEM_SCKDIVCR_BCK_Msk                 (0x70000UL)    /*!< BCK (Bitfield-Mask: 0x07)                             */
42417  #define R_SYSTEM_SCKDIVCR_PCKA_Pos                (12UL)         /*!< PCKA (Bit 12)                                         */
42418  #define R_SYSTEM_SCKDIVCR_PCKA_Msk                (0x7000UL)     /*!< PCKA (Bitfield-Mask: 0x07)                            */
42419  #define R_SYSTEM_SCKDIVCR_PCKB_Pos                (8UL)          /*!< PCKB (Bit 8)                                          */
42420  #define R_SYSTEM_SCKDIVCR_PCKB_Msk                (0x700UL)      /*!< PCKB (Bitfield-Mask: 0x07)                            */
42421  #define R_SYSTEM_SCKDIVCR_PCKC_Pos                (4UL)          /*!< PCKC (Bit 4)                                          */
42422  #define R_SYSTEM_SCKDIVCR_PCKC_Msk                (0x70UL)       /*!< PCKC (Bitfield-Mask: 0x07)                            */
42423  #define R_SYSTEM_SCKDIVCR_PCKD_Pos                (0UL)          /*!< PCKD (Bit 0)                                          */
42424  #define R_SYSTEM_SCKDIVCR_PCKD_Msk                (0x7UL)        /*!< PCKD (Bitfield-Mask: 0x07)                            */
42425 /* =======================================================  SCKDIVCR2  ======================================================= */
42426  #define R_SYSTEM_SCKDIVCR2_UCK_Pos                (4UL)          /*!< UCK (Bit 4)                                           */
42427  #define R_SYSTEM_SCKDIVCR2_UCK_Msk                (0x70UL)       /*!< UCK (Bitfield-Mask: 0x07)                             */
42428 /* ========================================================  SCKSCR  ========================================================= */
42429  #define R_SYSTEM_SCKSCR_CKSEL_Pos                 (0UL)          /*!< CKSEL (Bit 0)                                         */
42430  #define R_SYSTEM_SCKSCR_CKSEL_Msk                 (0x7UL)        /*!< CKSEL (Bitfield-Mask: 0x07)                           */
42431 /* ========================================================  PLLCCR  ========================================================= */
42432  #define R_SYSTEM_PLLCCR_PLLMUL_Pos                (8UL)          /*!< PLLMUL (Bit 8)                                        */
42433  #define R_SYSTEM_PLLCCR_PLLMUL_Msk                (0x3f00UL)     /*!< PLLMUL (Bitfield-Mask: 0x3f)                          */
42434  #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos              (4UL)          /*!< PLSRCSEL (Bit 4)                                      */
42435  #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk              (0x10UL)       /*!< PLSRCSEL (Bitfield-Mask: 0x01)                        */
42436  #define R_SYSTEM_PLLCCR_PLIDIV_Pos                (0UL)          /*!< PLIDIV (Bit 0)                                        */
42437  #define R_SYSTEM_PLLCCR_PLIDIV_Msk                (0x3UL)        /*!< PLIDIV (Bitfield-Mask: 0x03)                          */
42438 /* =========================================================  PLLCR  ========================================================= */
42439  #define R_SYSTEM_PLLCR_PLLSTP_Pos                 (0UL)          /*!< PLLSTP (Bit 0)                                        */
42440  #define R_SYSTEM_PLLCR_PLLSTP_Msk                 (0x1UL)        /*!< PLLSTP (Bitfield-Mask: 0x01)                          */
42441 /* ========================================================  PLLCCR2  ======================================================== */
42442  #define R_SYSTEM_PLLCCR2_PLODIV_Pos               (6UL)          /*!< PLODIV (Bit 6)                                        */
42443  #define R_SYSTEM_PLLCCR2_PLODIV_Msk               (0xc0UL)       /*!< PLODIV (Bitfield-Mask: 0x03)                          */
42444  #define R_SYSTEM_PLLCCR2_PLLMUL_Pos               (0UL)          /*!< PLLMUL (Bit 0)                                        */
42445  #define R_SYSTEM_PLLCCR2_PLLMUL_Msk               (0x1fUL)       /*!< PLLMUL (Bitfield-Mask: 0x1f)                          */
42446 /* =========================================================  BCKCR  ========================================================= */
42447  #define R_SYSTEM_BCKCR_BCLKDIV_Pos                (0UL)          /*!< BCLKDIV (Bit 0)                                       */
42448  #define R_SYSTEM_BCKCR_BCLKDIV_Msk                (0x1UL)        /*!< BCLKDIV (Bitfield-Mask: 0x01)                         */
42449 /* ========================================================  MEMWAIT  ======================================================== */
42450  #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos              (0UL)          /*!< MEMWAIT (Bit 0)                                       */
42451  #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk              (0x1UL)        /*!< MEMWAIT (Bitfield-Mask: 0x01)                         */
42452 /* ========================================================  MOSCCR  ========================================================= */
42453  #define R_SYSTEM_MOSCCR_MOSTP_Pos                 (0UL)          /*!< MOSTP (Bit 0)                                         */
42454  #define R_SYSTEM_MOSCCR_MOSTP_Msk                 (0x1UL)        /*!< MOSTP (Bitfield-Mask: 0x01)                           */
42455 /* ========================================================  HOCOCR  ========================================================= */
42456  #define R_SYSTEM_HOCOCR_HCSTP_Pos                 (0UL)          /*!< HCSTP (Bit 0)                                         */
42457  #define R_SYSTEM_HOCOCR_HCSTP_Msk                 (0x1UL)        /*!< HCSTP (Bitfield-Mask: 0x01)                           */
42458 /* ========================================================  MOCOCR  ========================================================= */
42459  #define R_SYSTEM_MOCOCR_MCSTP_Pos                 (0UL)          /*!< MCSTP (Bit 0)                                         */
42460  #define R_SYSTEM_MOCOCR_MCSTP_Msk                 (0x1UL)        /*!< MCSTP (Bitfield-Mask: 0x01)                           */
42461 /* ========================================================  FLLCR1  ========================================================= */
42462  #define R_SYSTEM_FLLCR1_FLLEN_Pos                 (0UL)          /*!< FLLEN (Bit 0)                                         */
42463  #define R_SYSTEM_FLLCR1_FLLEN_Msk                 (0x1UL)        /*!< FLLEN (Bitfield-Mask: 0x01)                           */
42464 /* ========================================================  FLLCR2  ========================================================= */
42465  #define R_SYSTEM_FLLCR2_FLLCNTL_Pos               (0UL)          /*!< FLLCNTL (Bit 0)                                       */
42466  #define R_SYSTEM_FLLCR2_FLLCNTL_Msk               (0x7ffUL)      /*!< FLLCNTL (Bitfield-Mask: 0x7ff)                        */
42467 /* =========================================================  OSCSF  ========================================================= */
42468  #define R_SYSTEM_OSCSF_PLLSF_Pos                  (5UL)          /*!< PLLSF (Bit 5)                                         */
42469  #define R_SYSTEM_OSCSF_PLLSF_Msk                  (0x20UL)       /*!< PLLSF (Bitfield-Mask: 0x01)                           */
42470  #define R_SYSTEM_OSCSF_MOSCSF_Pos                 (3UL)          /*!< MOSCSF (Bit 3)                                        */
42471  #define R_SYSTEM_OSCSF_MOSCSF_Msk                 (0x8UL)        /*!< MOSCSF (Bitfield-Mask: 0x01)                          */
42472  #define R_SYSTEM_OSCSF_HOCOSF_Pos                 (0UL)          /*!< HOCOSF (Bit 0)                                        */
42473  #define R_SYSTEM_OSCSF_HOCOSF_Msk                 (0x1UL)        /*!< HOCOSF (Bitfield-Mask: 0x01)                          */
42474  #define R_SYSTEM_OSCSF_PLL2SF_Pos                 (6UL)          /*!< PLL2SF (Bit 6)                                        */
42475  #define R_SYSTEM_OSCSF_PLL2SF_Msk                 (0x40UL)       /*!< PLL2SF (Bitfield-Mask: 0x01)                          */
42476 /* =========================================================  CKOCR  ========================================================= */
42477  #define R_SYSTEM_CKOCR_CKOEN_Pos                  (7UL)          /*!< CKOEN (Bit 7)                                         */
42478  #define R_SYSTEM_CKOCR_CKOEN_Msk                  (0x80UL)       /*!< CKOEN (Bitfield-Mask: 0x01)                           */
42479  #define R_SYSTEM_CKOCR_CKODIV_Pos                 (4UL)          /*!< CKODIV (Bit 4)                                        */
42480  #define R_SYSTEM_CKOCR_CKODIV_Msk                 (0x70UL)       /*!< CKODIV (Bitfield-Mask: 0x07)                          */
42481  #define R_SYSTEM_CKOCR_CKOSEL_Pos                 (0UL)          /*!< CKOSEL (Bit 0)                                        */
42482  #define R_SYSTEM_CKOCR_CKOSEL_Msk                 (0x7UL)        /*!< CKOSEL (Bitfield-Mask: 0x07)                          */
42483 /* ========================================================  TRCKCR  ========================================================= */
42484  #define R_SYSTEM_TRCKCR_TRCKEN_Pos                (7UL)          /*!< TRCKEN (Bit 7)                                        */
42485  #define R_SYSTEM_TRCKCR_TRCKEN_Msk                (0x80UL)       /*!< TRCKEN (Bitfield-Mask: 0x01)                          */
42486  #define R_SYSTEM_TRCKCR_TRCK_Pos                  (0UL)          /*!< TRCK (Bit 0)                                          */
42487  #define R_SYSTEM_TRCKCR_TRCK_Msk                  (0xfUL)        /*!< TRCK (Bitfield-Mask: 0x0f)                            */
42488 /* ========================================================  OSTDCR  ========================================================= */
42489  #define R_SYSTEM_OSTDCR_OSTDE_Pos                 (7UL)          /*!< OSTDE (Bit 7)                                         */
42490  #define R_SYSTEM_OSTDCR_OSTDE_Msk                 (0x80UL)       /*!< OSTDE (Bitfield-Mask: 0x01)                           */
42491  #define R_SYSTEM_OSTDCR_OSTDIE_Pos                (0UL)          /*!< OSTDIE (Bit 0)                                        */
42492  #define R_SYSTEM_OSTDCR_OSTDIE_Msk                (0x1UL)        /*!< OSTDIE (Bitfield-Mask: 0x01)                          */
42493 /* ========================================================  OSTDSR  ========================================================= */
42494  #define R_SYSTEM_OSTDSR_OSTDF_Pos                 (0UL)          /*!< OSTDF (Bit 0)                                         */
42495  #define R_SYSTEM_OSTDSR_OSTDF_Msk                 (0x1UL)        /*!< OSTDF (Bitfield-Mask: 0x01)                           */
42496 /* =========================================================  LPOPT  ========================================================= */
42497  #define R_SYSTEM_LPOPT_LPOPTEN_Pos                (7UL)          /*!< LPOPTEN (Bit 7)                                       */
42498  #define R_SYSTEM_LPOPT_LPOPTEN_Msk                (0x80UL)       /*!< LPOPTEN (Bitfield-Mask: 0x01)                         */
42499  #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos              (3UL)          /*!< BPFCLKDIS (Bit 3)                                     */
42500  #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk              (0x8UL)        /*!< BPFCLKDIS (Bitfield-Mask: 0x01)                       */
42501  #define R_SYSTEM_LPOPT_DCLKDIS_Pos                (1UL)          /*!< DCLKDIS (Bit 1)                                       */
42502  #define R_SYSTEM_LPOPT_DCLKDIS_Msk                (0x6UL)        /*!< DCLKDIS (Bitfield-Mask: 0x03)                         */
42503  #define R_SYSTEM_LPOPT_MPUDIS_Pos                 (0UL)          /*!< MPUDIS (Bit 0)                                        */
42504  #define R_SYSTEM_LPOPT_MPUDIS_Msk                 (0x1UL)        /*!< MPUDIS (Bitfield-Mask: 0x01)                          */
42505 /* =======================================================  SLCDSCKCR  ======================================================= */
42506  #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos           (7UL)          /*!< LCDSCKEN (Bit 7)                                      */
42507  #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk           (0x80UL)       /*!< LCDSCKEN (Bitfield-Mask: 0x01)                        */
42508  #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos          (0UL)          /*!< LCDSCKSEL (Bit 0)                                     */
42509  #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk          (0x7UL)        /*!< LCDSCKSEL (Bitfield-Mask: 0x07)                       */
42510 /* ========================================================  EBCKOCR  ======================================================== */
42511  #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos              (0UL)          /*!< EBCKOEN (Bit 0)                                       */
42512  #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk              (0x1UL)        /*!< EBCKOEN (Bitfield-Mask: 0x01)                         */
42513 /* ========================================================  SDCKOCR  ======================================================== */
42514  #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos              (0UL)          /*!< SDCKOEN (Bit 0)                                       */
42515  #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk              (0x1UL)        /*!< SDCKOEN (Bitfield-Mask: 0x01)                         */
42516 /* =======================================================  MOCOUTCR  ======================================================== */
42517  #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos            (0UL)          /*!< MOCOUTRM (Bit 0)                                      */
42518  #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk            (0xffUL)       /*!< MOCOUTRM (Bitfield-Mask: 0xff)                        */
42519 /* =======================================================  HOCOUTCR  ======================================================== */
42520  #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos            (0UL)          /*!< HOCOUTRM (Bit 0)                                      */
42521  #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk            (0xffUL)       /*!< HOCOUTRM (Bitfield-Mask: 0xff)                        */
42522 /* =========================================================  SNZCR  ========================================================= */
42523  #define R_SYSTEM_SNZCR_SNZE_Pos                   (7UL)          /*!< SNZE (Bit 7)                                          */
42524  #define R_SYSTEM_SNZCR_SNZE_Msk                   (0x80UL)       /*!< SNZE (Bitfield-Mask: 0x01)                            */
42525  #define R_SYSTEM_SNZCR_SNZDTCEN_Pos               (1UL)          /*!< SNZDTCEN (Bit 1)                                      */
42526  #define R_SYSTEM_SNZCR_SNZDTCEN_Msk               (0x2UL)        /*!< SNZDTCEN (Bitfield-Mask: 0x01)                        */
42527  #define R_SYSTEM_SNZCR_RXDREQEN_Pos               (0UL)          /*!< RXDREQEN (Bit 0)                                      */
42528  #define R_SYSTEM_SNZCR_RXDREQEN_Msk               (0x1UL)        /*!< RXDREQEN (Bitfield-Mask: 0x01)                        */
42529 /* ========================================================  SNZEDCR  ======================================================== */
42530  #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos            (7UL)          /*!< SCI0UMTED (Bit 7)                                     */
42531  #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk            (0x80UL)       /*!< SCI0UMTED (Bitfield-Mask: 0x01)                       */
42532  #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos             (6UL)          /*!< AD1UMTED (Bit 6)                                      */
42533  #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk             (0x40UL)       /*!< AD1UMTED (Bitfield-Mask: 0x01)                        */
42534  #define R_SYSTEM_SNZEDCR_AD1MATED_Pos             (5UL)          /*!< AD1MATED (Bit 5)                                      */
42535  #define R_SYSTEM_SNZEDCR_AD1MATED_Msk             (0x20UL)       /*!< AD1MATED (Bitfield-Mask: 0x01)                        */
42536  #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos             (4UL)          /*!< AD0UMTED (Bit 4)                                      */
42537  #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk             (0x10UL)       /*!< AD0UMTED (Bitfield-Mask: 0x01)                        */
42538  #define R_SYSTEM_SNZEDCR_AD0MATED_Pos             (3UL)          /*!< AD0MATED (Bit 3)                                      */
42539  #define R_SYSTEM_SNZEDCR_AD0MATED_Msk             (0x8UL)        /*!< AD0MATED (Bitfield-Mask: 0x01)                        */
42540  #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos             (2UL)          /*!< DTCNZRED (Bit 2)                                      */
42541  #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk             (0x4UL)        /*!< DTCNZRED (Bitfield-Mask: 0x01)                        */
42542  #define R_SYSTEM_SNZEDCR_DTCZRED_Pos              (1UL)          /*!< DTCZRED (Bit 1)                                       */
42543  #define R_SYSTEM_SNZEDCR_DTCZRED_Msk              (0x2UL)        /*!< DTCZRED (Bitfield-Mask: 0x01)                         */
42544  #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos            (0UL)          /*!< AGT1UNFED (Bit 0)                                     */
42545  #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk            (0x1UL)        /*!< AGT1UNFED (Bitfield-Mask: 0x01)                       */
42546 /* =======================================================  SNZREQCR  ======================================================== */
42547  #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos          (30UL)         /*!< SNZREQEN30 (Bit 30)                                   */
42548  #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk          (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01)                      */
42549  #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos          (29UL)         /*!< SNZREQEN29 (Bit 29)                                   */
42550  #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk          (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01)                      */
42551  #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos          (28UL)         /*!< SNZREQEN28 (Bit 28)                                   */
42552  #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk          (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01)                      */
42553  #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos          (25UL)         /*!< SNZREQEN25 (Bit 25)                                   */
42554  #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk          (0x2000000UL)  /*!< SNZREQEN25 (Bitfield-Mask: 0x01)                      */
42555  #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos          (24UL)         /*!< SNZREQEN24 (Bit 24)                                   */
42556  #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk          (0x1000000UL)  /*!< SNZREQEN24 (Bitfield-Mask: 0x01)                      */
42557  #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos          (23UL)         /*!< SNZREQEN23 (Bit 23)                                   */
42558  #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk          (0x800000UL)   /*!< SNZREQEN23 (Bitfield-Mask: 0x01)                      */
42559  #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos          (22UL)         /*!< SNZREQEN22 (Bit 22)                                   */
42560  #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk          (0x400000UL)   /*!< SNZREQEN22 (Bitfield-Mask: 0x01)                      */
42561  #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos          (17UL)         /*!< SNZREQEN17 (Bit 17)                                   */
42562  #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk          (0x20000UL)    /*!< SNZREQEN17 (Bitfield-Mask: 0x01)                      */
42563  #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos            (0UL)          /*!< SNZREQEN (Bit 0)                                      */
42564  #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk            (0x1UL)        /*!< SNZREQEN (Bitfield-Mask: 0x01)                        */
42565 /* ========================================================  FLSTOP  ========================================================= */
42566  #define R_SYSTEM_FLSTOP_FLSTPF_Pos                (4UL)          /*!< FLSTPF (Bit 4)                                        */
42567  #define R_SYSTEM_FLSTOP_FLSTPF_Msk                (0x10UL)       /*!< FLSTPF (Bitfield-Mask: 0x01)                          */
42568  #define R_SYSTEM_FLSTOP_FLSTOP_Pos                (0UL)          /*!< FLSTOP (Bit 0)                                        */
42569  #define R_SYSTEM_FLSTOP_FLSTOP_Msk                (0x1UL)        /*!< FLSTOP (Bitfield-Mask: 0x01)                          */
42570 /* =========================================================  PSMCR  ========================================================= */
42571  #define R_SYSTEM_PSMCR_PSMC_Pos                   (0UL)          /*!< PSMC (Bit 0)                                          */
42572  #define R_SYSTEM_PSMCR_PSMC_Msk                   (0x3UL)        /*!< PSMC (Bitfield-Mask: 0x03)                            */
42573 /* =========================================================  OPCCR  ========================================================= */
42574  #define R_SYSTEM_OPCCR_OPCMTSF_Pos                (4UL)          /*!< OPCMTSF (Bit 4)                                       */
42575  #define R_SYSTEM_OPCCR_OPCMTSF_Msk                (0x10UL)       /*!< OPCMTSF (Bitfield-Mask: 0x01)                         */
42576  #define R_SYSTEM_OPCCR_OPCM_Pos                   (0UL)          /*!< OPCM (Bit 0)                                          */
42577  #define R_SYSTEM_OPCCR_OPCM_Msk                   (0x3UL)        /*!< OPCM (Bitfield-Mask: 0x03)                            */
42578 /* ========================================================  SOPCCR  ========================================================= */
42579  #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos              (4UL)          /*!< SOPCMTSF (Bit 4)                                      */
42580  #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk              (0x10UL)       /*!< SOPCMTSF (Bitfield-Mask: 0x01)                        */
42581  #define R_SYSTEM_SOPCCR_SOPCM_Pos                 (0UL)          /*!< SOPCM (Bit 0)                                         */
42582  #define R_SYSTEM_SOPCCR_SOPCM_Msk                 (0x1UL)        /*!< SOPCM (Bitfield-Mask: 0x01)                           */
42583 /* =======================================================  MOSCWTCR  ======================================================== */
42584  #define R_SYSTEM_MOSCWTCR_MSTS_Pos                (0UL)          /*!< MSTS (Bit 0)                                          */
42585  #define R_SYSTEM_MOSCWTCR_MSTS_Msk                (0xfUL)        /*!< MSTS (Bitfield-Mask: 0x0f)                            */
42586 /* =======================================================  HOCOWTCR  ======================================================== */
42587  #define R_SYSTEM_HOCOWTCR_HSTS_Pos                (0UL)          /*!< HSTS (Bit 0)                                          */
42588  #define R_SYSTEM_HOCOWTCR_HSTS_Msk                (0x7UL)        /*!< HSTS (Bitfield-Mask: 0x07)                            */
42589 /* ========================================================  RSTSR1  ========================================================= */
42590  #define R_SYSTEM_RSTSR1_SPERF_Pos                 (12UL)         /*!< SPERF (Bit 12)                                        */
42591  #define R_SYSTEM_RSTSR1_SPERF_Msk                 (0x1000UL)     /*!< SPERF (Bitfield-Mask: 0x01)                           */
42592  #define R_SYSTEM_RSTSR1_BUSMRF_Pos                (11UL)         /*!< BUSMRF (Bit 11)                                       */
42593  #define R_SYSTEM_RSTSR1_BUSMRF_Msk                (0x800UL)      /*!< BUSMRF (Bitfield-Mask: 0x01)                          */
42594  #define R_SYSTEM_RSTSR1_BUSSRF_Pos                (10UL)         /*!< BUSSRF (Bit 10)                                       */
42595  #define R_SYSTEM_RSTSR1_BUSSRF_Msk                (0x400UL)      /*!< BUSSRF (Bitfield-Mask: 0x01)                          */
42596  #define R_SYSTEM_RSTSR1_REERF_Pos                 (9UL)          /*!< REERF (Bit 9)                                         */
42597  #define R_SYSTEM_RSTSR1_REERF_Msk                 (0x200UL)      /*!< REERF (Bitfield-Mask: 0x01)                           */
42598  #define R_SYSTEM_RSTSR1_RPERF_Pos                 (8UL)          /*!< RPERF (Bit 8)                                         */
42599  #define R_SYSTEM_RSTSR1_RPERF_Msk                 (0x100UL)      /*!< RPERF (Bitfield-Mask: 0x01)                           */
42600  #define R_SYSTEM_RSTSR1_SWRF_Pos                  (2UL)          /*!< SWRF (Bit 2)                                          */
42601  #define R_SYSTEM_RSTSR1_SWRF_Msk                  (0x4UL)        /*!< SWRF (Bitfield-Mask: 0x01)                            */
42602  #define R_SYSTEM_RSTSR1_WDTRF_Pos                 (1UL)          /*!< WDTRF (Bit 1)                                         */
42603  #define R_SYSTEM_RSTSR1_WDTRF_Msk                 (0x2UL)        /*!< WDTRF (Bitfield-Mask: 0x01)                           */
42604  #define R_SYSTEM_RSTSR1_IWDTRF_Pos                (0UL)          /*!< IWDTRF (Bit 0)                                        */
42605  #define R_SYSTEM_RSTSR1_IWDTRF_Msk                (0x1UL)        /*!< IWDTRF (Bitfield-Mask: 0x01)                          */
42606  #define R_SYSTEM_RSTSR1_TZERF_Pos                 (13UL)         /*!< TZERF (Bit 13)                                        */
42607  #define R_SYSTEM_RSTSR1_TZERF_Msk                 (0x2000UL)     /*!< TZERF (Bitfield-Mask: 0x01)                           */
42608  #define R_SYSTEM_RSTSR1_CPERF_Pos                 (15UL)         /*!< CPERF (Bit 15)                                        */
42609  #define R_SYSTEM_RSTSR1_CPERF_Msk                 (0x8000UL)     /*!< CPERF (Bitfield-Mask: 0x01)                           */
42610 /* ========================================================  STCONR  ========================================================= */
42611  #define R_SYSTEM_STCONR_STCON_Pos                 (0UL)          /*!< STCON (Bit 0)                                         */
42612  #define R_SYSTEM_STCONR_STCON_Msk                 (0x3UL)        /*!< STCON (Bitfield-Mask: 0x03)                           */
42613 /* ========================================================  LVD1CR1  ======================================================== */
42614  #define R_SYSTEM_LVD1CR1_IRQSEL_Pos               (2UL)          /*!< IRQSEL (Bit 2)                                        */
42615  #define R_SYSTEM_LVD1CR1_IRQSEL_Msk               (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
42616  #define R_SYSTEM_LVD1CR1_IDTSEL_Pos               (0UL)          /*!< IDTSEL (Bit 0)                                        */
42617  #define R_SYSTEM_LVD1CR1_IDTSEL_Msk               (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
42618 /* ========================================================  LVD2CR1  ======================================================== */
42619  #define R_SYSTEM_LVD2CR1_IRQSEL_Pos               (2UL)          /*!< IRQSEL (Bit 2)                                        */
42620  #define R_SYSTEM_LVD2CR1_IRQSEL_Msk               (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
42621  #define R_SYSTEM_LVD2CR1_IDTSEL_Pos               (0UL)          /*!< IDTSEL (Bit 0)                                        */
42622  #define R_SYSTEM_LVD2CR1_IDTSEL_Msk               (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
42623 /* ======================================================  USBCKCR_ALT  ====================================================== */
42624  #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos        (0UL)          /*!< USBCLKSEL (Bit 0)                                     */
42625  #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk        (0x1UL)        /*!< USBCLKSEL (Bitfield-Mask: 0x01)                       */
42626 /* =======================================================  SDADCCKCR  ======================================================= */
42627  #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos         (0UL)          /*!< SDADCCKSEL (Bit 0)                                    */
42628  #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk         (0x1UL)        /*!< SDADCCKSEL (Bitfield-Mask: 0x01)                      */
42629  #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos          (7UL)          /*!< SDADCCKEN (Bit 7)                                     */
42630  #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk          (0x80UL)       /*!< SDADCCKEN (Bitfield-Mask: 0x01)                       */
42631 /* ========================================================  LVD1SR  ========================================================= */
42632  #define R_SYSTEM_LVD1SR_MON_Pos                   (1UL)          /*!< MON (Bit 1)                                           */
42633  #define R_SYSTEM_LVD1SR_MON_Msk                   (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
42634  #define R_SYSTEM_LVD1SR_DET_Pos                   (0UL)          /*!< DET (Bit 0)                                           */
42635  #define R_SYSTEM_LVD1SR_DET_Msk                   (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
42636 /* ========================================================  LVD2SR  ========================================================= */
42637  #define R_SYSTEM_LVD2SR_MON_Pos                   (1UL)          /*!< MON (Bit 1)                                           */
42638  #define R_SYSTEM_LVD2SR_MON_Msk                   (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
42639  #define R_SYSTEM_LVD2SR_DET_Pos                   (0UL)          /*!< DET (Bit 0)                                           */
42640  #define R_SYSTEM_LVD2SR_DET_Msk                   (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
42641 /* =========================================================  PRCR  ========================================================== */
42642  #define R_SYSTEM_PRCR_PRKEY_Pos                   (8UL)          /*!< PRKEY (Bit 8)                                         */
42643  #define R_SYSTEM_PRCR_PRKEY_Msk                   (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
42644  #define R_SYSTEM_PRCR_PRC3_Pos                    (3UL)          /*!< PRC3 (Bit 3)                                          */
42645  #define R_SYSTEM_PRCR_PRC3_Msk                    (0x8UL)        /*!< PRC3 (Bitfield-Mask: 0x01)                            */
42646  #define R_SYSTEM_PRCR_PRC1_Pos                    (1UL)          /*!< PRC1 (Bit 1)                                          */
42647  #define R_SYSTEM_PRCR_PRC1_Msk                    (0x2UL)        /*!< PRC1 (Bitfield-Mask: 0x01)                            */
42648  #define R_SYSTEM_PRCR_PRC0_Pos                    (0UL)          /*!< PRC0 (Bit 0)                                          */
42649  #define R_SYSTEM_PRCR_PRC0_Msk                    (0x1UL)        /*!< PRC0 (Bitfield-Mask: 0x01)                            */
42650  #define R_SYSTEM_PRCR_PRC4_Pos                    (4UL)          /*!< PRC4 (Bit 4)                                          */
42651  #define R_SYSTEM_PRCR_PRC4_Msk                    (0x10UL)       /*!< PRC4 (Bitfield-Mask: 0x01)                            */
42652 /* ========================================================  DPSIER0  ======================================================== */
42653  #define R_SYSTEM_DPSIER0_DIRQE_Pos                (0UL)          /*!< DIRQE (Bit 0)                                         */
42654  #define R_SYSTEM_DPSIER0_DIRQE_Msk                (0x1UL)        /*!< DIRQE (Bitfield-Mask: 0x01)                           */
42655 /* ========================================================  DPSIER1  ======================================================== */
42656  #define R_SYSTEM_DPSIER1_DIRQE_Pos                (0UL)          /*!< DIRQE (Bit 0)                                         */
42657  #define R_SYSTEM_DPSIER1_DIRQE_Msk                (0x1UL)        /*!< DIRQE (Bitfield-Mask: 0x01)                           */
42658 /* ========================================================  DPSIER2  ======================================================== */
42659  #define R_SYSTEM_DPSIER2_DNMIE_Pos                (4UL)          /*!< DNMIE (Bit 4)                                         */
42660  #define R_SYSTEM_DPSIER2_DNMIE_Msk                (0x10UL)       /*!< DNMIE (Bitfield-Mask: 0x01)                           */
42661  #define R_SYSTEM_DPSIER2_DRTCAIE_Pos              (3UL)          /*!< DRTCAIE (Bit 3)                                       */
42662  #define R_SYSTEM_DPSIER2_DRTCAIE_Msk              (0x8UL)        /*!< DRTCAIE (Bitfield-Mask: 0x01)                         */
42663  #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos             (2UL)          /*!< DTRTCIIE (Bit 2)                                      */
42664  #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk             (0x4UL)        /*!< DTRTCIIE (Bitfield-Mask: 0x01)                        */
42665  #define R_SYSTEM_DPSIER2_DLVD2IE_Pos              (1UL)          /*!< DLVD2IE (Bit 1)                                       */
42666  #define R_SYSTEM_DPSIER2_DLVD2IE_Msk              (0x2UL)        /*!< DLVD2IE (Bitfield-Mask: 0x01)                         */
42667  #define R_SYSTEM_DPSIER2_DLVD1IE_Pos              (0UL)          /*!< DLVD1IE (Bit 0)                                       */
42668  #define R_SYSTEM_DPSIER2_DLVD1IE_Msk              (0x1UL)        /*!< DLVD1IE (Bitfield-Mask: 0x01)                         */
42669 /* ========================================================  DPSIER3  ======================================================== */
42670  #define R_SYSTEM_DPSIER3_DAGT1IE_Pos              (2UL)          /*!< DAGT1IE (Bit 2)                                       */
42671  #define R_SYSTEM_DPSIER3_DAGT1IE_Msk              (0x4UL)        /*!< DAGT1IE (Bitfield-Mask: 0x01)                         */
42672  #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos             (1UL)          /*!< DUSBHSIE (Bit 1)                                      */
42673  #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk             (0x2UL)        /*!< DUSBHSIE (Bitfield-Mask: 0x01)                        */
42674  #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos             (0UL)          /*!< DUSBFSIE (Bit 0)                                      */
42675  #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk             (0x1UL)        /*!< DUSBFSIE (Bitfield-Mask: 0x01)                        */
42676  #define R_SYSTEM_DPSIER3_DAGT3IE_Pos              (3UL)          /*!< DAGT3IE (Bit 3)                                       */
42677  #define R_SYSTEM_DPSIER3_DAGT3IE_Msk              (0x8UL)        /*!< DAGT3IE (Bitfield-Mask: 0x01)                         */
42678 /* ========================================================  DPSIFR0  ======================================================== */
42679  #define R_SYSTEM_DPSIFR0_DIRQF_Pos                (0UL)          /*!< DIRQF (Bit 0)                                         */
42680  #define R_SYSTEM_DPSIFR0_DIRQF_Msk                (0x1UL)        /*!< DIRQF (Bitfield-Mask: 0x01)                           */
42681 /* ========================================================  DPSIFR1  ======================================================== */
42682  #define R_SYSTEM_DPSIFR1_DIRQF_Pos                (0UL)          /*!< DIRQF (Bit 0)                                         */
42683  #define R_SYSTEM_DPSIFR1_DIRQF_Msk                (0x1UL)        /*!< DIRQF (Bitfield-Mask: 0x01)                           */
42684 /* ========================================================  DPSIFR2  ======================================================== */
42685  #define R_SYSTEM_DPSIFR2_DNMIF_Pos                (4UL)          /*!< DNMIF (Bit 4)                                         */
42686  #define R_SYSTEM_DPSIFR2_DNMIF_Msk                (0x10UL)       /*!< DNMIF (Bitfield-Mask: 0x01)                           */
42687  #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos              (3UL)          /*!< DRTCAIF (Bit 3)                                       */
42688  #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk              (0x8UL)        /*!< DRTCAIF (Bitfield-Mask: 0x01)                         */
42689  #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos             (2UL)          /*!< DTRTCIIF (Bit 2)                                      */
42690  #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk             (0x4UL)        /*!< DTRTCIIF (Bitfield-Mask: 0x01)                        */
42691  #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos              (1UL)          /*!< DLVD2IF (Bit 1)                                       */
42692  #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk              (0x2UL)        /*!< DLVD2IF (Bitfield-Mask: 0x01)                         */
42693  #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos              (0UL)          /*!< DLVD1IF (Bit 0)                                       */
42694  #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk              (0x1UL)        /*!< DLVD1IF (Bitfield-Mask: 0x01)                         */
42695 /* ========================================================  DPSIFR3  ======================================================== */
42696  #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos              (2UL)          /*!< DAGT1IF (Bit 2)                                       */
42697  #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk              (0x4UL)        /*!< DAGT1IF (Bitfield-Mask: 0x01)                         */
42698  #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos             (1UL)          /*!< DUSBHSIF (Bit 1)                                      */
42699  #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk             (0x2UL)        /*!< DUSBHSIF (Bitfield-Mask: 0x01)                        */
42700  #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos             (0UL)          /*!< DUSBFSIF (Bit 0)                                      */
42701  #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk             (0x1UL)        /*!< DUSBFSIF (Bitfield-Mask: 0x01)                        */
42702  #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos              (3UL)          /*!< DAGT3IF (Bit 3)                                       */
42703  #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk              (0x8UL)        /*!< DAGT3IF (Bitfield-Mask: 0x01)                         */
42704 /* =======================================================  DPSIEGR0  ======================================================== */
42705  #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos              (0UL)          /*!< DIRQEG (Bit 0)                                        */
42706  #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk              (0x1UL)        /*!< DIRQEG (Bitfield-Mask: 0x01)                          */
42707 /* =======================================================  DPSIEGR1  ======================================================== */
42708  #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos              (0UL)          /*!< DIRQEG (Bit 0)                                        */
42709  #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk              (0x1UL)        /*!< DIRQEG (Bitfield-Mask: 0x01)                          */
42710 /* =======================================================  DPSIEGR2  ======================================================== */
42711  #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos              (4UL)          /*!< DNMIEG (Bit 4)                                        */
42712  #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk              (0x10UL)       /*!< DNMIEG (Bitfield-Mask: 0x01)                          */
42713  #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos            (1UL)          /*!< DLVD2IEG (Bit 1)                                      */
42714  #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk            (0x2UL)        /*!< DLVD2IEG (Bitfield-Mask: 0x01)                        */
42715  #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos            (0UL)          /*!< DLVD1IEG (Bit 0)                                      */
42716  #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk            (0x1UL)        /*!< DLVD1IEG (Bitfield-Mask: 0x01)                        */
42717 /* ========================================================  DPSBYCR  ======================================================== */
42718  #define R_SYSTEM_DPSBYCR_DPSBY_Pos                (7UL)          /*!< DPSBY (Bit 7)                                         */
42719  #define R_SYSTEM_DPSBYCR_DPSBY_Msk                (0x80UL)       /*!< DPSBY (Bitfield-Mask: 0x01)                           */
42720  #define R_SYSTEM_DPSBYCR_IOKEEP_Pos               (6UL)          /*!< IOKEEP (Bit 6)                                        */
42721  #define R_SYSTEM_DPSBYCR_IOKEEP_Msk               (0x40UL)       /*!< IOKEEP (Bitfield-Mask: 0x01)                          */
42722  #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos              (0UL)          /*!< DEEPCUT (Bit 0)                                       */
42723  #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk              (0x3UL)        /*!< DEEPCUT (Bitfield-Mask: 0x03)                         */
42724 /* ========================================================  SYOCDCR  ======================================================== */
42725  #define R_SYSTEM_SYOCDCR_DBGEN_Pos                (7UL)          /*!< DBGEN (Bit 7)                                         */
42726  #define R_SYSTEM_SYOCDCR_DBGEN_Msk                (0x80UL)       /*!< DBGEN (Bitfield-Mask: 0x01)                           */
42727  #define R_SYSTEM_SYOCDCR_DOCDF_Pos                (0UL)          /*!< DOCDF (Bit 0)                                         */
42728  #define R_SYSTEM_SYOCDCR_DOCDF_Msk                (0x1UL)        /*!< DOCDF (Bitfield-Mask: 0x01)                           */
42729 /* =========================================================  MOMCR  ========================================================= */
42730  #define R_SYSTEM_MOMCR_AUTODRVEN_Pos              (7UL)          /*!< AUTODRVEN (Bit 7)                                     */
42731  #define R_SYSTEM_MOMCR_AUTODRVEN_Msk              (0x80UL)       /*!< AUTODRVEN (Bitfield-Mask: 0x01)                       */
42732  #define R_SYSTEM_MOMCR_MOSEL_Pos                  (6UL)          /*!< MOSEL (Bit 6)                                         */
42733  #define R_SYSTEM_MOMCR_MOSEL_Msk                  (0x40UL)       /*!< MOSEL (Bitfield-Mask: 0x01)                           */
42734  #define R_SYSTEM_MOMCR_MODRV0_Pos                 (4UL)          /*!< MODRV0 (Bit 4)                                        */
42735  #define R_SYSTEM_MOMCR_MODRV0_Msk                 (0x30UL)       /*!< MODRV0 (Bitfield-Mask: 0x03)                          */
42736  #define R_SYSTEM_MOMCR_MODRV1_Pos                 (3UL)          /*!< MODRV1 (Bit 3)                                        */
42737  #define R_SYSTEM_MOMCR_MODRV1_Msk                 (0x8UL)        /*!< MODRV1 (Bitfield-Mask: 0x01)                          */
42738 /* ========================================================  RSTSR0  ========================================================= */
42739  #define R_SYSTEM_RSTSR0_DPSRSTF_Pos               (7UL)          /*!< DPSRSTF (Bit 7)                                       */
42740  #define R_SYSTEM_RSTSR0_DPSRSTF_Msk               (0x80UL)       /*!< DPSRSTF (Bitfield-Mask: 0x01)                         */
42741  #define R_SYSTEM_RSTSR0_LVD2RF_Pos                (3UL)          /*!< LVD2RF (Bit 3)                                        */
42742  #define R_SYSTEM_RSTSR0_LVD2RF_Msk                (0x8UL)        /*!< LVD2RF (Bitfield-Mask: 0x01)                          */
42743  #define R_SYSTEM_RSTSR0_LVD1RF_Pos                (2UL)          /*!< LVD1RF (Bit 2)                                        */
42744  #define R_SYSTEM_RSTSR0_LVD1RF_Msk                (0x4UL)        /*!< LVD1RF (Bitfield-Mask: 0x01)                          */
42745  #define R_SYSTEM_RSTSR0_LVD0RF_Pos                (1UL)          /*!< LVD0RF (Bit 1)                                        */
42746  #define R_SYSTEM_RSTSR0_LVD0RF_Msk                (0x2UL)        /*!< LVD0RF (Bitfield-Mask: 0x01)                          */
42747  #define R_SYSTEM_RSTSR0_PORF_Pos                  (0UL)          /*!< PORF (Bit 0)                                          */
42748  #define R_SYSTEM_RSTSR0_PORF_Msk                  (0x1UL)        /*!< PORF (Bitfield-Mask: 0x01)                            */
42749 /* ========================================================  RSTSR2  ========================================================= */
42750  #define R_SYSTEM_RSTSR2_CWSF_Pos                  (0UL)          /*!< CWSF (Bit 0)                                          */
42751  #define R_SYSTEM_RSTSR2_CWSF_Msk                  (0x1UL)        /*!< CWSF (Bitfield-Mask: 0x01)                            */
42752 /* ========================================================  LVCMPCR  ======================================================== */
42753  #define R_SYSTEM_LVCMPCR_LVD2E_Pos                (6UL)          /*!< LVD2E (Bit 6)                                         */
42754  #define R_SYSTEM_LVCMPCR_LVD2E_Msk                (0x40UL)       /*!< LVD2E (Bitfield-Mask: 0x01)                           */
42755  #define R_SYSTEM_LVCMPCR_LVD1E_Pos                (5UL)          /*!< LVD1E (Bit 5)                                         */
42756  #define R_SYSTEM_LVCMPCR_LVD1E_Msk                (0x20UL)       /*!< LVD1E (Bitfield-Mask: 0x01)                           */
42757 /* =======================================================  LVD1CMPCR  ======================================================= */
42758  #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos            (0UL)          /*!< LVD1LVL (Bit 0)                                       */
42759  #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk            (0x1fUL)       /*!< LVD1LVL (Bitfield-Mask: 0x1f)                         */
42760  #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos              (7UL)          /*!< LVD1E (Bit 7)                                         */
42761  #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk              (0x80UL)       /*!< LVD1E (Bitfield-Mask: 0x01)                           */
42762 /* ========================================================  LVDLVLR  ======================================================== */
42763  #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos              (5UL)          /*!< LVD2LVL (Bit 5)                                       */
42764  #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk              (0xe0UL)       /*!< LVD2LVL (Bitfield-Mask: 0x07)                         */
42765  #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos              (0UL)          /*!< LVD1LVL (Bit 0)                                       */
42766  #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk              (0x1fUL)       /*!< LVD1LVL (Bitfield-Mask: 0x1f)                         */
42767 /* =======================================================  LVD2CMPCR  ======================================================= */
42768  #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos            (0UL)          /*!< LVD2LVL (Bit 0)                                       */
42769  #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk            (0x7UL)        /*!< LVD2LVL (Bitfield-Mask: 0x07)                         */
42770  #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos              (7UL)          /*!< LVD2E (Bit 7)                                         */
42771  #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk              (0x80UL)       /*!< LVD2E (Bitfield-Mask: 0x01)                           */
42772 /* ========================================================  LVD1CR0  ======================================================== */
42773  #define R_SYSTEM_LVD1CR0_RN_Pos                   (7UL)          /*!< RN (Bit 7)                                            */
42774  #define R_SYSTEM_LVD1CR0_RN_Msk                   (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
42775  #define R_SYSTEM_LVD1CR0_RI_Pos                   (6UL)          /*!< RI (Bit 6)                                            */
42776  #define R_SYSTEM_LVD1CR0_RI_Msk                   (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
42777  #define R_SYSTEM_LVD1CR0_FSAMP_Pos                (4UL)          /*!< FSAMP (Bit 4)                                         */
42778  #define R_SYSTEM_LVD1CR0_FSAMP_Msk                (0x30UL)       /*!< FSAMP (Bitfield-Mask: 0x03)                           */
42779  #define R_SYSTEM_LVD1CR0_CMPE_Pos                 (2UL)          /*!< CMPE (Bit 2)                                          */
42780  #define R_SYSTEM_LVD1CR0_CMPE_Msk                 (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
42781  #define R_SYSTEM_LVD1CR0_DFDIS_Pos                (1UL)          /*!< DFDIS (Bit 1)                                         */
42782  #define R_SYSTEM_LVD1CR0_DFDIS_Msk                (0x2UL)        /*!< DFDIS (Bitfield-Mask: 0x01)                           */
42783  #define R_SYSTEM_LVD1CR0_RIE_Pos                  (0UL)          /*!< RIE (Bit 0)                                           */
42784  #define R_SYSTEM_LVD1CR0_RIE_Msk                  (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
42785 /* ========================================================  LVD2CR0  ======================================================== */
42786  #define R_SYSTEM_LVD2CR0_RN_Pos                   (7UL)          /*!< RN (Bit 7)                                            */
42787  #define R_SYSTEM_LVD2CR0_RN_Msk                   (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
42788  #define R_SYSTEM_LVD2CR0_RI_Pos                   (6UL)          /*!< RI (Bit 6)                                            */
42789  #define R_SYSTEM_LVD2CR0_RI_Msk                   (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
42790  #define R_SYSTEM_LVD2CR0_FSAMP_Pos                (4UL)          /*!< FSAMP (Bit 4)                                         */
42791  #define R_SYSTEM_LVD2CR0_FSAMP_Msk                (0x30UL)       /*!< FSAMP (Bitfield-Mask: 0x03)                           */
42792  #define R_SYSTEM_LVD2CR0_CMPE_Pos                 (2UL)          /*!< CMPE (Bit 2)                                          */
42793  #define R_SYSTEM_LVD2CR0_CMPE_Msk                 (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
42794  #define R_SYSTEM_LVD2CR0_DFDIS_Pos                (1UL)          /*!< DFDIS (Bit 1)                                         */
42795  #define R_SYSTEM_LVD2CR0_DFDIS_Msk                (0x2UL)        /*!< DFDIS (Bitfield-Mask: 0x01)                           */
42796  #define R_SYSTEM_LVD2CR0_RIE_Pos                  (0UL)          /*!< RIE (Bit 0)                                           */
42797  #define R_SYSTEM_LVD2CR0_RIE_Msk                  (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
42798 /* ========================================================  VBTCR1  ========================================================= */
42799  #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos              (0UL)          /*!< BPWSWSTP (Bit 0)                                      */
42800  #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk              (0x1UL)        /*!< BPWSWSTP (Bitfield-Mask: 0x01)                        */
42801 /* ========================================================  DCDCCTL  ======================================================== */
42802  #define R_SYSTEM_DCDCCTL_PD_Pos                   (7UL)          /*!< PD (Bit 7)                                            */
42803  #define R_SYSTEM_DCDCCTL_PD_Msk                   (0x80UL)       /*!< PD (Bitfield-Mask: 0x01)                              */
42804  #define R_SYSTEM_DCDCCTL_FST_Pos                  (6UL)          /*!< FST (Bit 6)                                           */
42805  #define R_SYSTEM_DCDCCTL_FST_Msk                  (0x40UL)       /*!< FST (Bitfield-Mask: 0x01)                             */
42806  #define R_SYSTEM_DCDCCTL_LCBOOST_Pos              (5UL)          /*!< LCBOOST (Bit 5)                                       */
42807  #define R_SYSTEM_DCDCCTL_LCBOOST_Msk              (0x20UL)       /*!< LCBOOST (Bitfield-Mask: 0x01)                         */
42808  #define R_SYSTEM_DCDCCTL_STOPZA_Pos               (4UL)          /*!< STOPZA (Bit 4)                                        */
42809  #define R_SYSTEM_DCDCCTL_STOPZA_Msk               (0x10UL)       /*!< STOPZA (Bitfield-Mask: 0x01)                          */
42810  #define R_SYSTEM_DCDCCTL_OCPEN_Pos                (1UL)          /*!< OCPEN (Bit 1)                                         */
42811  #define R_SYSTEM_DCDCCTL_OCPEN_Msk                (0x2UL)        /*!< OCPEN (Bitfield-Mask: 0x01)                           */
42812  #define R_SYSTEM_DCDCCTL_DCDCON_Pos               (0UL)          /*!< DCDCON (Bit 0)                                        */
42813  #define R_SYSTEM_DCDCCTL_DCDCON_Msk               (0x1UL)        /*!< DCDCON (Bitfield-Mask: 0x01)                          */
42814 /* ========================================================  VCCSEL  ========================================================= */
42815  #define R_SYSTEM_VCCSEL_VCCSEL_Pos                (0UL)          /*!< VCCSEL (Bit 0)                                        */
42816  #define R_SYSTEM_VCCSEL_VCCSEL_Msk                (0x3UL)        /*!< VCCSEL (Bitfield-Mask: 0x03)                          */
42817 /* ========================================================  SOSCCR  ========================================================= */
42818  #define R_SYSTEM_SOSCCR_SOSTP_Pos                 (0UL)          /*!< SOSTP (Bit 0)                                         */
42819  #define R_SYSTEM_SOSCCR_SOSTP_Msk                 (0x1UL)        /*!< SOSTP (Bitfield-Mask: 0x01)                           */
42820 /* =========================================================  SOMCR  ========================================================= */
42821  #define R_SYSTEM_SOMCR_SODRV_Pos                  (0UL)          /*!< SODRV (Bit 0)                                         */
42822  #define R_SYSTEM_SOMCR_SODRV_Msk                  (0x3UL)        /*!< SODRV (Bitfield-Mask: 0x03)                           */
42823 /* ========================================================  LOCOCR  ========================================================= */
42824  #define R_SYSTEM_LOCOCR_LCSTP_Pos                 (0UL)          /*!< LCSTP (Bit 0)                                         */
42825  #define R_SYSTEM_LOCOCR_LCSTP_Msk                 (0x1UL)        /*!< LCSTP (Bitfield-Mask: 0x01)                           */
42826 /* =======================================================  LOCOUTCR  ======================================================== */
42827  #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos            (0UL)          /*!< LOCOUTRM (Bit 0)                                      */
42828  #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk            (0xffUL)       /*!< LOCOUTRM (Bitfield-Mask: 0xff)                        */
42829 /* ========================================================  VBTCR2  ========================================================= */
42830  #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos             (6UL)          /*!< VBTLVDLVL (Bit 6)                                     */
42831  #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk             (0xc0UL)       /*!< VBTLVDLVL (Bitfield-Mask: 0x03)                       */
42832  #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos              (4UL)          /*!< VBTLVDEN (Bit 4)                                      */
42833  #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk              (0x10UL)       /*!< VBTLVDEN (Bitfield-Mask: 0x01)                        */
42834 /* =========================================================  VBTSR  ========================================================= */
42835  #define R_SYSTEM_VBTSR_VBTRVLD_Pos                (4UL)          /*!< VBTRVLD (Bit 4)                                       */
42836  #define R_SYSTEM_VBTSR_VBTRVLD_Msk                (0x10UL)       /*!< VBTRVLD (Bitfield-Mask: 0x01)                         */
42837  #define R_SYSTEM_VBTSR_VBTBLDF_Pos                (1UL)          /*!< VBTBLDF (Bit 1)                                       */
42838  #define R_SYSTEM_VBTSR_VBTBLDF_Msk                (0x2UL)        /*!< VBTBLDF (Bitfield-Mask: 0x01)                         */
42839  #define R_SYSTEM_VBTSR_VBTRDF_Pos                 (0UL)          /*!< VBTRDF (Bit 0)                                        */
42840  #define R_SYSTEM_VBTSR_VBTRDF_Msk                 (0x1UL)        /*!< VBTRDF (Bitfield-Mask: 0x01)                          */
42841 /* =======================================================  VBTCMPCR  ======================================================== */
42842  #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos             (0UL)          /*!< VBTCMPE (Bit 0)                                       */
42843  #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk             (0x1UL)        /*!< VBTCMPE (Bitfield-Mask: 0x01)                         */
42844 /* =======================================================  VBTLVDICR  ======================================================= */
42845  #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos         (1UL)          /*!< VBTLVDISEL (Bit 1)                                    */
42846  #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk         (0x2UL)        /*!< VBTLVDISEL (Bitfield-Mask: 0x01)                      */
42847  #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos           (0UL)          /*!< VBTLVDIE (Bit 0)                                      */
42848  #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk           (0x1UL)        /*!< VBTLVDIE (Bitfield-Mask: 0x01)                        */
42849 /* =======================================================  VBTWCTLR  ======================================================== */
42850  #define R_SYSTEM_VBTWCTLR_VWEN_Pos                (0UL)          /*!< VWEN (Bit 0)                                          */
42851  #define R_SYSTEM_VBTWCTLR_VWEN_Msk                (0x1UL)        /*!< VWEN (Bitfield-Mask: 0x01)                            */
42852 /* ======================================================  VBTWCH0OTSR  ====================================================== */
42853  #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos       (5UL)          /*!< CH0VAGTUTE (Bit 5)                                    */
42854  #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk       (0x20UL)       /*!< CH0VAGTUTE (Bitfield-Mask: 0x01)                      */
42855  #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos       (4UL)          /*!< CH0VRTCATE (Bit 4)                                    */
42856  #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk       (0x10UL)       /*!< CH0VRTCATE (Bitfield-Mask: 0x01)                      */
42857  #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos        (3UL)          /*!< CH0VRTCTE (Bit 3)                                     */
42858  #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk        (0x8UL)        /*!< CH0VRTCTE (Bitfield-Mask: 0x01)                       */
42859  #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos        (2UL)          /*!< CH0VCH2TE (Bit 2)                                     */
42860  #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk        (0x4UL)        /*!< CH0VCH2TE (Bitfield-Mask: 0x01)                       */
42861  #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos        (1UL)          /*!< CH0VCH1TE (Bit 1)                                     */
42862  #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk        (0x2UL)        /*!< CH0VCH1TE (Bitfield-Mask: 0x01)                       */
42863 /* ======================================================  VBTWCH1OTSR  ====================================================== */
42864  #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos       (5UL)          /*!< CH1VAGTUTE (Bit 5)                                    */
42865  #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk       (0x20UL)       /*!< CH1VAGTUTE (Bitfield-Mask: 0x01)                      */
42866  #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos       (4UL)          /*!< CH1VRTCATE (Bit 4)                                    */
42867  #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk       (0x10UL)       /*!< CH1VRTCATE (Bitfield-Mask: 0x01)                      */
42868  #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos        (3UL)          /*!< CH1VRTCTE (Bit 3)                                     */
42869  #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk        (0x8UL)        /*!< CH1VRTCTE (Bitfield-Mask: 0x01)                       */
42870  #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos        (2UL)          /*!< CH1VCH2TE (Bit 2)                                     */
42871  #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk        (0x4UL)        /*!< CH1VCH2TE (Bitfield-Mask: 0x01)                       */
42872  #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos        (0UL)          /*!< CH1VCH0TE (Bit 0)                                     */
42873  #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk        (0x1UL)        /*!< CH1VCH0TE (Bitfield-Mask: 0x01)                       */
42874 /* ======================================================  VBTWCH2OTSR  ====================================================== */
42875  #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos       (5UL)          /*!< CH2VAGTUTE (Bit 5)                                    */
42876  #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk       (0x20UL)       /*!< CH2VAGTUTE (Bitfield-Mask: 0x01)                      */
42877  #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos       (4UL)          /*!< CH2VRTCATE (Bit 4)                                    */
42878  #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk       (0x10UL)       /*!< CH2VRTCATE (Bitfield-Mask: 0x01)                      */
42879  #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos        (3UL)          /*!< CH2VRTCTE (Bit 3)                                     */
42880  #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk        (0x8UL)        /*!< CH2VRTCTE (Bitfield-Mask: 0x01)                       */
42881  #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos        (1UL)          /*!< CH2VCH1TE (Bit 1)                                     */
42882  #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk        (0x2UL)        /*!< CH2VCH1TE (Bitfield-Mask: 0x01)                       */
42883  #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos        (0UL)          /*!< CH2VCH0TE (Bit 0)                                     */
42884  #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk        (0x1UL)        /*!< CH2VCH0TE (Bitfield-Mask: 0x01)                       */
42885 /* =======================================================  VBTICTLR  ======================================================== */
42886  #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos            (2UL)          /*!< VCH2INEN (Bit 2)                                      */
42887  #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk            (0x4UL)        /*!< VCH2INEN (Bitfield-Mask: 0x01)                        */
42888  #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos            (1UL)          /*!< VCH1INEN (Bit 1)                                      */
42889  #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk            (0x2UL)        /*!< VCH1INEN (Bitfield-Mask: 0x01)                        */
42890  #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos            (0UL)          /*!< VCH0INEN (Bit 0)                                      */
42891  #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk            (0x1UL)        /*!< VCH0INEN (Bitfield-Mask: 0x01)                        */
42892 /* =======================================================  VBTOCTLR  ======================================================== */
42893  #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos           (5UL)          /*!< VOUT2LSEL (Bit 5)                                     */
42894  #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk           (0x20UL)       /*!< VOUT2LSEL (Bitfield-Mask: 0x01)                       */
42895  #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos           (4UL)          /*!< VCOU1LSEL (Bit 4)                                     */
42896  #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk           (0x10UL)       /*!< VCOU1LSEL (Bitfield-Mask: 0x01)                       */
42897  #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos           (3UL)          /*!< VOUT0LSEL (Bit 3)                                     */
42898  #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk           (0x8UL)        /*!< VOUT0LSEL (Bitfield-Mask: 0x01)                       */
42899  #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos             (2UL)          /*!< VCH2OEN (Bit 2)                                       */
42900  #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk             (0x4UL)        /*!< VCH2OEN (Bitfield-Mask: 0x01)                         */
42901  #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos             (1UL)          /*!< VCH1OEN (Bit 1)                                       */
42902  #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk             (0x2UL)        /*!< VCH1OEN (Bitfield-Mask: 0x01)                         */
42903  #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos             (0UL)          /*!< VCH0OEN (Bit 0)                                       */
42904  #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk             (0x1UL)        /*!< VCH0OEN (Bitfield-Mask: 0x01)                         */
42905 /* ========================================================  VBTWTER  ======================================================== */
42906  #define R_SYSTEM_VBTWTER_VAGTUE_Pos               (5UL)          /*!< VAGTUE (Bit 5)                                        */
42907  #define R_SYSTEM_VBTWTER_VAGTUE_Msk               (0x20UL)       /*!< VAGTUE (Bitfield-Mask: 0x01)                          */
42908  #define R_SYSTEM_VBTWTER_VRTCAE_Pos               (4UL)          /*!< VRTCAE (Bit 4)                                        */
42909  #define R_SYSTEM_VBTWTER_VRTCAE_Msk               (0x10UL)       /*!< VRTCAE (Bitfield-Mask: 0x01)                          */
42910  #define R_SYSTEM_VBTWTER_VRTCIE_Pos               (3UL)          /*!< VRTCIE (Bit 3)                                        */
42911  #define R_SYSTEM_VBTWTER_VRTCIE_Msk               (0x8UL)        /*!< VRTCIE (Bitfield-Mask: 0x01)                          */
42912  #define R_SYSTEM_VBTWTER_VCH2E_Pos                (2UL)          /*!< VCH2E (Bit 2)                                         */
42913  #define R_SYSTEM_VBTWTER_VCH2E_Msk                (0x4UL)        /*!< VCH2E (Bitfield-Mask: 0x01)                           */
42914  #define R_SYSTEM_VBTWTER_VCH1E_Pos                (1UL)          /*!< VCH1E (Bit 1)                                         */
42915  #define R_SYSTEM_VBTWTER_VCH1E_Msk                (0x2UL)        /*!< VCH1E (Bitfield-Mask: 0x01)                           */
42916  #define R_SYSTEM_VBTWTER_VCH0E_Pos                (0UL)          /*!< VCH0E (Bit 0)                                         */
42917  #define R_SYSTEM_VBTWTER_VCH0E_Msk                (0x1UL)        /*!< VCH0E (Bitfield-Mask: 0x01)                           */
42918 /* ========================================================  VBTWEGR  ======================================================== */
42919  #define R_SYSTEM_VBTWEGR_VCH2EG_Pos               (2UL)          /*!< VCH2EG (Bit 2)                                        */
42920  #define R_SYSTEM_VBTWEGR_VCH2EG_Msk               (0x4UL)        /*!< VCH2EG (Bitfield-Mask: 0x01)                          */
42921  #define R_SYSTEM_VBTWEGR_VCH1EG_Pos               (1UL)          /*!< VCH1EG (Bit 1)                                        */
42922  #define R_SYSTEM_VBTWEGR_VCH1EG_Msk               (0x2UL)        /*!< VCH1EG (Bitfield-Mask: 0x01)                          */
42923  #define R_SYSTEM_VBTWEGR_VCH0EG_Pos               (0UL)          /*!< VCH0EG (Bit 0)                                        */
42924  #define R_SYSTEM_VBTWEGR_VCH0EG_Msk               (0x1UL)        /*!< VCH0EG (Bitfield-Mask: 0x01)                          */
42925 /* ========================================================  VBTWFR  ========================================================= */
42926  #define R_SYSTEM_VBTWFR_VAGTUF_Pos                (5UL)          /*!< VAGTUF (Bit 5)                                        */
42927  #define R_SYSTEM_VBTWFR_VAGTUF_Msk                (0x20UL)       /*!< VAGTUF (Bitfield-Mask: 0x01)                          */
42928  #define R_SYSTEM_VBTWFR_VRTCAF_Pos                (4UL)          /*!< VRTCAF (Bit 4)                                        */
42929  #define R_SYSTEM_VBTWFR_VRTCAF_Msk                (0x10UL)       /*!< VRTCAF (Bitfield-Mask: 0x01)                          */
42930  #define R_SYSTEM_VBTWFR_VRTCIF_Pos                (3UL)          /*!< VRTCIF (Bit 3)                                        */
42931  #define R_SYSTEM_VBTWFR_VRTCIF_Msk                (0x8UL)        /*!< VRTCIF (Bitfield-Mask: 0x01)                          */
42932  #define R_SYSTEM_VBTWFR_VCH2F_Pos                 (2UL)          /*!< VCH2F (Bit 2)                                         */
42933  #define R_SYSTEM_VBTWFR_VCH2F_Msk                 (0x4UL)        /*!< VCH2F (Bitfield-Mask: 0x01)                           */
42934  #define R_SYSTEM_VBTWFR_VCH1F_Pos                 (1UL)          /*!< VCH1F (Bit 1)                                         */
42935  #define R_SYSTEM_VBTWFR_VCH1F_Msk                 (0x2UL)        /*!< VCH1F (Bitfield-Mask: 0x01)                           */
42936  #define R_SYSTEM_VBTWFR_VCH0F_Pos                 (0UL)          /*!< VCH0F (Bit 0)                                         */
42937  #define R_SYSTEM_VBTWFR_VCH0F_Msk                 (0x1UL)        /*!< VCH0F (Bitfield-Mask: 0x01)                           */
42938 /* ========================================================  VBTBKR  ========================================================= */
42939  #define R_SYSTEM_VBTBKR_VBTBKR_Pos                (0UL)          /*!< VBTBKR (Bit 0)                                        */
42940  #define R_SYSTEM_VBTBKR_VBTBKR_Msk                (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
42941 /* ========================================================  FWEPROR  ======================================================== */
42942  #define R_SYSTEM_FWEPROR_FLWE_Pos                 (0UL)          /*!< FLWE (Bit 0)                                          */
42943  #define R_SYSTEM_FWEPROR_FLWE_Msk                 (0x3UL)        /*!< FLWE (Bitfield-Mask: 0x03)                            */
42944 /* ========================================================  PLL2CCR  ======================================================== */
42945  #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos              (0UL)          /*!< PL2IDIV (Bit 0)                                       */
42946  #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk              (0x3UL)        /*!< PL2IDIV (Bitfield-Mask: 0x03)                         */
42947  #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos            (4UL)          /*!< PL2SRCSEL (Bit 4)                                     */
42948  #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk            (0x10UL)       /*!< PL2SRCSEL (Bitfield-Mask: 0x01)                       */
42949  #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos              (8UL)          /*!< PLL2MUL (Bit 8)                                       */
42950  #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk              (0x3f00UL)     /*!< PLL2MUL (Bitfield-Mask: 0x3f)                         */
42951 /* ========================================================  PLL2CR  ========================================================= */
42952  #define R_SYSTEM_PLL2CR_PLL2STP_Pos               (0UL)          /*!< PLL2STP (Bit 0)                                       */
42953  #define R_SYSTEM_PLL2CR_PLL2STP_Msk               (0x1UL)        /*!< PLL2STP (Bitfield-Mask: 0x01)                         */
42954 /* ======================================================  USBCKDIVCR  ======================================================= */
42955  #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos          (0UL)          /*!< USBCKDIV (Bit 0)                                      */
42956  #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk          (0x7UL)        /*!< USBCKDIV (Bitfield-Mask: 0x07)                        */
42957 /* ======================================================  OCTACKDIVCR  ====================================================== */
42958  #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos        (0UL)          /*!< OCTACKDIV (Bit 0)                                     */
42959  #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk        (0x7UL)        /*!< OCTACKDIV (Bitfield-Mask: 0x07)                       */
42960 /* =====================================================  SCISPICKDIVCR  ===================================================== */
42961  #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos    (0UL)          /*!< SCISPICKDIV (Bit 0)                                   */
42962  #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk    (0x7UL)        /*!< SCISPICKDIV (Bitfield-Mask: 0x07)                     */
42963 /* =====================================================  CANFDCKDIVCR  ====================================================== */
42964  #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos      (0UL)          /*!< CANFDCKDIV (Bit 0)                                    */
42965  #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk      (0x7UL)        /*!< CANFDCKDIV (Bitfield-Mask: 0x07)                      */
42966 /* ======================================================  GPTCKDIVCR  ======================================================= */
42967  #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos          (0UL)          /*!< GPTCKDIV (Bit 0)                                      */
42968  #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk          (0x7UL)        /*!< GPTCKDIV (Bitfield-Mask: 0x07)                        */
42969 /* ======================================================  IICCKDIVCR  ======================================================= */
42970  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
42971  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
42972 /* ========================================================  USBCKCR  ======================================================== */
42973  #define R_SYSTEM_USBCKCR_USBCKSEL_Pos             (0UL)          /*!< USBCKSEL (Bit 0)                                      */
42974  #define R_SYSTEM_USBCKCR_USBCKSEL_Msk             (0x7UL)        /*!< USBCKSEL (Bitfield-Mask: 0x07)                        */
42975  #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos            (6UL)          /*!< USBCKSREQ (Bit 6)                                     */
42976  #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk            (0x40UL)       /*!< USBCKSREQ (Bitfield-Mask: 0x01)                       */
42977  #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos            (7UL)          /*!< USBCKSRDY (Bit 7)                                     */
42978  #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk            (0x80UL)       /*!< USBCKSRDY (Bitfield-Mask: 0x01)                       */
42979 /* =======================================================  OCTACKCR  ======================================================== */
42980  #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos           (0UL)          /*!< OCTACKSEL (Bit 0)                                     */
42981  #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk           (0x7UL)        /*!< OCTACKSEL (Bitfield-Mask: 0x07)                       */
42982  #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos          (6UL)          /*!< OCTACKSREQ (Bit 6)                                    */
42983  #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk          (0x40UL)       /*!< OCTACKSREQ (Bitfield-Mask: 0x01)                      */
42984  #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos          (7UL)          /*!< OCTACKSRDY (Bit 7)                                    */
42985  #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk          (0x80UL)       /*!< OCTACKSRDY (Bitfield-Mask: 0x01)                      */
42986 /* ======================================================  SCISPICKCR  ======================================================= */
42987  #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos       (0UL)          /*!< SCISPICKSEL (Bit 0)                                   */
42988  #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk       (0x7UL)        /*!< SCISPICKSEL (Bitfield-Mask: 0x07)                     */
42989  #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos      (6UL)          /*!< SCISPICKSREQ (Bit 6)                                  */
42990  #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk      (0x40UL)       /*!< SCISPICKSREQ (Bitfield-Mask: 0x01)                    */
42991  #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos      (7UL)          /*!< SCISPICKSRDY (Bit 7)                                  */
42992  #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk      (0x80UL)       /*!< SCISPICKSRDY (Bitfield-Mask: 0x01)                    */
42993 /* =======================================================  CANFDCKCR  ======================================================= */
42994  #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos         (0UL)          /*!< CANFDCKSEL (Bit 0)                                    */
42995  #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk         (0x7UL)        /*!< CANFDCKSEL (Bitfield-Mask: 0x07)                      */
42996  #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos        (6UL)          /*!< CANFDCKSREQ (Bit 6)                                   */
42997  #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk        (0x40UL)       /*!< CANFDCKSREQ (Bitfield-Mask: 0x01)                     */
42998  #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos        (7UL)          /*!< CANFDCKSRDY (Bit 7)                                   */
42999  #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk        (0x80UL)       /*!< CANFDCKSRDY (Bitfield-Mask: 0x01)                     */
43000 /* ========================================================  GPTCKCR  ======================================================== */
43001  #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos             (0UL)          /*!< GPTCKSEL (Bit 0)                                      */
43002  #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk             (0x7UL)        /*!< GPTCKSEL (Bitfield-Mask: 0x07)                        */
43003  #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos            (6UL)          /*!< GPTCKSREQ (Bit 6)                                     */
43004  #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk            (0x40UL)       /*!< GPTCKSREQ (Bitfield-Mask: 0x01)                       */
43005  #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos            (7UL)          /*!< GPTCKSRDY (Bit 7)                                     */
43006  #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk            (0x80UL)       /*!< GPTCKSRDY (Bitfield-Mask: 0x01)                       */
43007 /* ========================================================  IICCKCR  ======================================================== */
43008  #define R_SYSTEM_IICCKCR_IICCKSEL_Pos             (0UL)          /*!< IICCKSEL (Bit 0)                                      */
43009  #define R_SYSTEM_IICCKCR_IICCKSEL_Msk             (0x7UL)        /*!< IICCKSEL (Bitfield-Mask: 0x07)                        */
43010  #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos            (6UL)          /*!< IICCKSREQ (Bit 6)                                     */
43011  #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk            (0x40UL)       /*!< IICCKSREQ (Bitfield-Mask: 0x01)                       */
43012  #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos            (7UL)          /*!< IICCKSRDY (Bit 7)                                     */
43013  #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk            (0x80UL)       /*!< IICCKSRDY (Bitfield-Mask: 0x01)                       */
43014 /* =======================================================  SNZREQCR1  ======================================================= */
43015  #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos          (0UL)          /*!< SNZREQEN0 (Bit 0)                                     */
43016  #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk          (0x1UL)        /*!< SNZREQEN0 (Bitfield-Mask: 0x01)                       */
43017  #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos          (1UL)          /*!< SNZREQEN1 (Bit 1)                                     */
43018  #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk          (0x2UL)        /*!< SNZREQEN1 (Bitfield-Mask: 0x01)                       */
43019  #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos          (2UL)          /*!< SNZREQEN2 (Bit 2)                                     */
43020  #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk          (0x4UL)        /*!< SNZREQEN2 (Bitfield-Mask: 0x01)                       */
43021 /* =======================================================  SNZEDCR1  ======================================================== */
43022  #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos           (0UL)          /*!< AGT3UNFED (Bit 0)                                     */
43023  #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk           (0x1UL)        /*!< AGT3UNFED (Bitfield-Mask: 0x01)                       */
43024 /* ========================================================  CGFSAR  ========================================================= */
43025  #define R_SYSTEM_CGFSAR_NONSEC00_Pos              (0UL)          /*!< NONSEC00 (Bit 0)                                      */
43026  #define R_SYSTEM_CGFSAR_NONSEC00_Msk              (0x1UL)        /*!< NONSEC00 (Bitfield-Mask: 0x01)                        */
43027  #define R_SYSTEM_CGFSAR_NONSEC02_Pos              (2UL)          /*!< NONSEC02 (Bit 2)                                      */
43028  #define R_SYSTEM_CGFSAR_NONSEC02_Msk              (0x4UL)        /*!< NONSEC02 (Bitfield-Mask: 0x01)                        */
43029  #define R_SYSTEM_CGFSAR_NONSEC03_Pos              (3UL)          /*!< NONSEC03 (Bit 3)                                      */
43030  #define R_SYSTEM_CGFSAR_NONSEC03_Msk              (0x8UL)        /*!< NONSEC03 (Bitfield-Mask: 0x01)                        */
43031  #define R_SYSTEM_CGFSAR_NONSEC04_Pos              (4UL)          /*!< NONSEC04 (Bit 4)                                      */
43032  #define R_SYSTEM_CGFSAR_NONSEC04_Msk              (0x10UL)       /*!< NONSEC04 (Bitfield-Mask: 0x01)                        */
43033  #define R_SYSTEM_CGFSAR_NONSEC05_Pos              (5UL)          /*!< NONSEC05 (Bit 5)                                      */
43034  #define R_SYSTEM_CGFSAR_NONSEC05_Msk              (0x20UL)       /*!< NONSEC05 (Bitfield-Mask: 0x01)                        */
43035  #define R_SYSTEM_CGFSAR_NONSEC06_Pos              (6UL)          /*!< NONSEC06 (Bit 6)                                      */
43036  #define R_SYSTEM_CGFSAR_NONSEC06_Msk              (0x40UL)       /*!< NONSEC06 (Bitfield-Mask: 0x01)                        */
43037  #define R_SYSTEM_CGFSAR_NONSEC07_Pos              (7UL)          /*!< NONSEC07 (Bit 7)                                      */
43038  #define R_SYSTEM_CGFSAR_NONSEC07_Msk              (0x80UL)       /*!< NONSEC07 (Bitfield-Mask: 0x01)                        */
43039  #define R_SYSTEM_CGFSAR_NONSEC08_Pos              (8UL)          /*!< NONSEC08 (Bit 8)                                      */
43040  #define R_SYSTEM_CGFSAR_NONSEC08_Msk              (0x100UL)      /*!< NONSEC08 (Bitfield-Mask: 0x01)                        */
43041  #define R_SYSTEM_CGFSAR_NONSEC09_Pos              (9UL)          /*!< NONSEC09 (Bit 9)                                      */
43042  #define R_SYSTEM_CGFSAR_NONSEC09_Msk              (0x200UL)      /*!< NONSEC09 (Bitfield-Mask: 0x01)                        */
43043  #define R_SYSTEM_CGFSAR_NONSEC11_Pos              (11UL)         /*!< NONSEC11 (Bit 11)                                     */
43044  #define R_SYSTEM_CGFSAR_NONSEC11_Msk              (0x800UL)      /*!< NONSEC11 (Bitfield-Mask: 0x01)                        */
43045  #define R_SYSTEM_CGFSAR_NONSEC12_Pos              (12UL)         /*!< NONSEC12 (Bit 12)                                     */
43046  #define R_SYSTEM_CGFSAR_NONSEC12_Msk              (0x1000UL)     /*!< NONSEC12 (Bitfield-Mask: 0x01)                        */
43047  #define R_SYSTEM_CGFSAR_NONSEC16_Pos              (16UL)         /*!< NONSEC16 (Bit 16)                                     */
43048  #define R_SYSTEM_CGFSAR_NONSEC16_Msk              (0x10000UL)    /*!< NONSEC16 (Bitfield-Mask: 0x01)                        */
43049  #define R_SYSTEM_CGFSAR_NONSEC17_Pos              (17UL)         /*!< NONSEC17 (Bit 17)                                     */
43050  #define R_SYSTEM_CGFSAR_NONSEC17_Msk              (0x20000UL)    /*!< NONSEC17 (Bitfield-Mask: 0x01)                        */
43051 /* ========================================================  LPMSAR  ========================================================= */
43052  #define R_SYSTEM_LPMSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
43053  #define R_SYSTEM_LPMSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
43054  #define R_SYSTEM_LPMSAR_NONSEC2_Pos               (2UL)          /*!< NONSEC2 (Bit 2)                                       */
43055  #define R_SYSTEM_LPMSAR_NONSEC2_Msk               (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
43056  #define R_SYSTEM_LPMSAR_NONSEC4_Pos               (4UL)          /*!< NONSEC4 (Bit 4)                                       */
43057  #define R_SYSTEM_LPMSAR_NONSEC4_Msk               (0x10UL)       /*!< NONSEC4 (Bitfield-Mask: 0x01)                         */
43058  #define R_SYSTEM_LPMSAR_NONSEC8_Pos               (8UL)          /*!< NONSEC8 (Bit 8)                                       */
43059  #define R_SYSTEM_LPMSAR_NONSEC8_Msk               (0x100UL)      /*!< NONSEC8 (Bitfield-Mask: 0x01)                         */
43060  #define R_SYSTEM_LPMSAR_NONSEC9_Pos               (9UL)          /*!< NONSEC9 (Bit 9)                                       */
43061  #define R_SYSTEM_LPMSAR_NONSEC9_Msk               (0x200UL)      /*!< NONSEC9 (Bitfield-Mask: 0x01)                         */
43062 /* ========================================================  LVDSAR  ========================================================= */
43063  #define R_SYSTEM_LVDSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
43064  #define R_SYSTEM_LVDSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
43065  #define R_SYSTEM_LVDSAR_NONSEC1_Pos               (1UL)          /*!< NONSEC1 (Bit 1)                                       */
43066  #define R_SYSTEM_LVDSAR_NONSEC1_Msk               (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
43067 /* ========================================================  RSTSAR  ========================================================= */
43068  #define R_SYSTEM_RSTSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
43069  #define R_SYSTEM_RSTSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
43070  #define R_SYSTEM_RSTSAR_NONSEC1_Pos               (1UL)          /*!< NONSEC1 (Bit 1)                                       */
43071  #define R_SYSTEM_RSTSAR_NONSEC1_Msk               (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
43072  #define R_SYSTEM_RSTSAR_NONSEC2_Pos               (2UL)          /*!< NONSEC2 (Bit 2)                                       */
43073  #define R_SYSTEM_RSTSAR_NONSEC2_Msk               (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
43074 /* ========================================================  BBFSAR  ========================================================= */
43075  #define R_SYSTEM_BBFSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
43076  #define R_SYSTEM_BBFSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
43077  #define R_SYSTEM_BBFSAR_NONSEC1_Pos               (1UL)          /*!< NONSEC1 (Bit 1)                                       */
43078  #define R_SYSTEM_BBFSAR_NONSEC1_Msk               (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
43079  #define R_SYSTEM_BBFSAR_NONSEC2_Pos               (2UL)          /*!< NONSEC2 (Bit 2)                                       */
43080  #define R_SYSTEM_BBFSAR_NONSEC2_Msk               (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
43081  #define R_SYSTEM_BBFSAR_NONSEC16_Pos              (16UL)         /*!< NONSEC16 (Bit 16)                                     */
43082  #define R_SYSTEM_BBFSAR_NONSEC16_Msk              (0x10000UL)    /*!< NONSEC16 (Bitfield-Mask: 0x01)                        */
43083  #define R_SYSTEM_BBFSAR_NONSEC17_Pos              (17UL)         /*!< NONSEC17 (Bit 17)                                     */
43084  #define R_SYSTEM_BBFSAR_NONSEC17_Msk              (0x20000UL)    /*!< NONSEC17 (Bitfield-Mask: 0x01)                        */
43085  #define R_SYSTEM_BBFSAR_NONSEC18_Pos              (18UL)         /*!< NONSEC18 (Bit 18)                                     */
43086  #define R_SYSTEM_BBFSAR_NONSEC18_Msk              (0x40000UL)    /*!< NONSEC18 (Bitfield-Mask: 0x01)                        */
43087  #define R_SYSTEM_BBFSAR_NONSEC19_Pos              (19UL)         /*!< NONSEC19 (Bit 19)                                     */
43088  #define R_SYSTEM_BBFSAR_NONSEC19_Msk              (0x80000UL)    /*!< NONSEC19 (Bitfield-Mask: 0x01)                        */
43089  #define R_SYSTEM_BBFSAR_NONSEC20_Pos              (20UL)         /*!< NONSEC20 (Bit 20)                                     */
43090  #define R_SYSTEM_BBFSAR_NONSEC20_Msk              (0x100000UL)   /*!< NONSEC20 (Bitfield-Mask: 0x01)                        */
43091  #define R_SYSTEM_BBFSAR_NONSEC21_Pos              (21UL)         /*!< NONSEC21 (Bit 21)                                     */
43092  #define R_SYSTEM_BBFSAR_NONSEC21_Msk              (0x200000UL)   /*!< NONSEC21 (Bitfield-Mask: 0x01)                        */
43093  #define R_SYSTEM_BBFSAR_NONSEC22_Pos              (22UL)         /*!< NONSEC22 (Bit 22)                                     */
43094  #define R_SYSTEM_BBFSAR_NONSEC22_Msk              (0x400000UL)   /*!< NONSEC22 (Bitfield-Mask: 0x01)                        */
43095  #define R_SYSTEM_BBFSAR_NONSEC23_Pos              (23UL)         /*!< NONSEC23 (Bit 23)                                     */
43096  #define R_SYSTEM_BBFSAR_NONSEC23_Msk              (0x800000UL)   /*!< NONSEC23 (Bitfield-Mask: 0x01)                        */
43097 /* ========================================================  DPFSAR  ========================================================= */
43098  #define R_SYSTEM_DPFSAR_DPFSA0_Pos                (0UL)          /*!< DPFSA0 (Bit 0)                                        */
43099  #define R_SYSTEM_DPFSAR_DPFSA0_Msk                (0x1UL)        /*!< DPFSA0 (Bitfield-Mask: 0x01)                          */
43100  #define R_SYSTEM_DPFSAR_DPFSA1_Pos                (1UL)          /*!< DPFSA1 (Bit 1)                                        */
43101  #define R_SYSTEM_DPFSAR_DPFSA1_Msk                (0x2UL)        /*!< DPFSA1 (Bitfield-Mask: 0x01)                          */
43102  #define R_SYSTEM_DPFSAR_DPFSA2_Pos                (2UL)          /*!< DPFSA2 (Bit 2)                                        */
43103  #define R_SYSTEM_DPFSAR_DPFSA2_Msk                (0x4UL)        /*!< DPFSA2 (Bitfield-Mask: 0x01)                          */
43104  #define R_SYSTEM_DPFSAR_DPFSA3_Pos                (3UL)          /*!< DPFSA3 (Bit 3)                                        */
43105  #define R_SYSTEM_DPFSAR_DPFSA3_Msk                (0x8UL)        /*!< DPFSA3 (Bitfield-Mask: 0x01)                          */
43106  #define R_SYSTEM_DPFSAR_DPFSA4_Pos                (4UL)          /*!< DPFSA4 (Bit 4)                                        */
43107  #define R_SYSTEM_DPFSAR_DPFSA4_Msk                (0x10UL)       /*!< DPFSA4 (Bitfield-Mask: 0x01)                          */
43108  #define R_SYSTEM_DPFSAR_DPFSA5_Pos                (5UL)          /*!< DPFSA5 (Bit 5)                                        */
43109  #define R_SYSTEM_DPFSAR_DPFSA5_Msk                (0x20UL)       /*!< DPFSA5 (Bitfield-Mask: 0x01)                          */
43110  #define R_SYSTEM_DPFSAR_DPFSA6_Pos                (6UL)          /*!< DPFSA6 (Bit 6)                                        */
43111  #define R_SYSTEM_DPFSAR_DPFSA6_Msk                (0x40UL)       /*!< DPFSA6 (Bitfield-Mask: 0x01)                          */
43112  #define R_SYSTEM_DPFSAR_DPFSA7_Pos                (7UL)          /*!< DPFSA7 (Bit 7)                                        */
43113  #define R_SYSTEM_DPFSAR_DPFSA7_Msk                (0x80UL)       /*!< DPFSA7 (Bitfield-Mask: 0x01)                          */
43114  #define R_SYSTEM_DPFSAR_DPFSA8_Pos                (8UL)          /*!< DPFSA8 (Bit 8)                                        */
43115  #define R_SYSTEM_DPFSAR_DPFSA8_Msk                (0x100UL)      /*!< DPFSA8 (Bitfield-Mask: 0x01)                          */
43116  #define R_SYSTEM_DPFSAR_DPFSA9_Pos                (9UL)          /*!< DPFSA9 (Bit 9)                                        */
43117  #define R_SYSTEM_DPFSAR_DPFSA9_Msk                (0x200UL)      /*!< DPFSA9 (Bitfield-Mask: 0x01)                          */
43118  #define R_SYSTEM_DPFSAR_DPFSA10_Pos               (10UL)         /*!< DPFSA10 (Bit 10)                                      */
43119  #define R_SYSTEM_DPFSAR_DPFSA10_Msk               (0x400UL)      /*!< DPFSA10 (Bitfield-Mask: 0x01)                         */
43120  #define R_SYSTEM_DPFSAR_DPFSA11_Pos               (11UL)         /*!< DPFSA11 (Bit 11)                                      */
43121  #define R_SYSTEM_DPFSAR_DPFSA11_Msk               (0x800UL)      /*!< DPFSA11 (Bitfield-Mask: 0x01)                         */
43122  #define R_SYSTEM_DPFSAR_DPFSA12_Pos               (12UL)         /*!< DPFSA12 (Bit 12)                                      */
43123  #define R_SYSTEM_DPFSAR_DPFSA12_Msk               (0x1000UL)     /*!< DPFSA12 (Bitfield-Mask: 0x01)                         */
43124  #define R_SYSTEM_DPFSAR_DPFSA13_Pos               (13UL)         /*!< DPFSA13 (Bit 13)                                      */
43125  #define R_SYSTEM_DPFSAR_DPFSA13_Msk               (0x2000UL)     /*!< DPFSA13 (Bitfield-Mask: 0x01)                         */
43126  #define R_SYSTEM_DPFSAR_DPFSA14_Pos               (14UL)         /*!< DPFSA14 (Bit 14)                                      */
43127  #define R_SYSTEM_DPFSAR_DPFSA14_Msk               (0x4000UL)     /*!< DPFSA14 (Bitfield-Mask: 0x01)                         */
43128  #define R_SYSTEM_DPFSAR_DPFSA15_Pos               (15UL)         /*!< DPFSA15 (Bit 15)                                      */
43129  #define R_SYSTEM_DPFSAR_DPFSA15_Msk               (0x8000UL)     /*!< DPFSA15 (Bitfield-Mask: 0x01)                         */
43130  #define R_SYSTEM_DPFSAR_DPFSA16_Pos               (16UL)         /*!< DPFSA16 (Bit 16)                                      */
43131  #define R_SYSTEM_DPFSAR_DPFSA16_Msk               (0x10000UL)    /*!< DPFSA16 (Bitfield-Mask: 0x01)                         */
43132  #define R_SYSTEM_DPFSAR_DPFSA17_Pos               (17UL)         /*!< DPFSA17 (Bit 17)                                      */
43133  #define R_SYSTEM_DPFSAR_DPFSA17_Msk               (0x20000UL)    /*!< DPFSA17 (Bitfield-Mask: 0x01)                         */
43134  #define R_SYSTEM_DPFSAR_DPFSA18_Pos               (18UL)         /*!< DPFSA18 (Bit 18)                                      */
43135  #define R_SYSTEM_DPFSAR_DPFSA18_Msk               (0x40000UL)    /*!< DPFSA18 (Bitfield-Mask: 0x01)                         */
43136  #define R_SYSTEM_DPFSAR_DPFSA19_Pos               (19UL)         /*!< DPFSA19 (Bit 19)                                      */
43137  #define R_SYSTEM_DPFSAR_DPFSA19_Msk               (0x80000UL)    /*!< DPFSA19 (Bitfield-Mask: 0x01)                         */
43138  #define R_SYSTEM_DPFSAR_DPFSA20_Pos               (20UL)         /*!< DPFSA20 (Bit 20)                                      */
43139  #define R_SYSTEM_DPFSAR_DPFSA20_Msk               (0x100000UL)   /*!< DPFSA20 (Bitfield-Mask: 0x01)                         */
43140  #define R_SYSTEM_DPFSAR_DPFSA24_Pos               (24UL)         /*!< DPFSA24 (Bit 24)                                      */
43141  #define R_SYSTEM_DPFSAR_DPFSA24_Msk               (0x1000000UL)  /*!< DPFSA24 (Bitfield-Mask: 0x01)                         */
43142  #define R_SYSTEM_DPFSAR_DPFSA26_Pos               (26UL)         /*!< DPFSA26 (Bit 26)                                      */
43143  #define R_SYSTEM_DPFSAR_DPFSA26_Msk               (0x4000000UL)  /*!< DPFSA26 (Bitfield-Mask: 0x01)                         */
43144  #define R_SYSTEM_DPFSAR_DPFSA27_Pos               (27UL)         /*!< DPFSA27 (Bit 27)                                      */
43145  #define R_SYSTEM_DPFSAR_DPFSA27_Msk               (0x8000000UL)  /*!< DPFSA27 (Bitfield-Mask: 0x01)                         */
43146 /* ========================================================  DPSWCR  ========================================================= */
43147  #define R_SYSTEM_DPSWCR_WTSTS_Pos                 (0UL)          /*!< WTSTS (Bit 0)                                         */
43148  #define R_SYSTEM_DPSWCR_WTSTS_Msk                 (0x3fUL)       /*!< WTSTS (Bitfield-Mask: 0x3f)                           */
43149 /* ======================================================  VBATTMNSELR  ====================================================== */
43150  #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos       (0UL)          /*!< VBATTMNSEL (Bit 0)                                    */
43151  #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk       (0x1UL)        /*!< VBATTMNSEL (Bitfield-Mask: 0x01)                      */
43152 /* =======================================================  VBATTMONR  ======================================================= */
43153  #define R_SYSTEM_VBATTMONR_VBATTMON_Pos           (0UL)          /*!< VBATTMON (Bit 0)                                      */
43154  #define R_SYSTEM_VBATTMONR_VBATTMON_Msk           (0x1UL)        /*!< VBATTMON (Bitfield-Mask: 0x01)                        */
43155 /* ========================================================  VBTBER  ========================================================= */
43156  #define R_SYSTEM_VBTBER_VBAE_Pos                  (3UL)          /*!< VBAE (Bit 3)                                          */
43157  #define R_SYSTEM_VBTBER_VBAE_Msk                  (0x8UL)        /*!< VBAE (Bitfield-Mask: 0x01)                            */
43158 
43159 /* =========================================================================================================================== */
43160 /* ================                                           R_TSN                                           ================ */
43161 /* =========================================================================================================================== */
43162 
43163 /* ========================================================  TSCDRH  ========================================================= */
43164  #define R_TSN_TSCDRH_TSCDRH_Pos    (0UL)    /*!< TSCDRH (Bit 0)                                        */
43165  #define R_TSN_TSCDRH_TSCDRH_Msk    (0xffUL) /*!< TSCDRH (Bitfield-Mask: 0xff)                          */
43166 /* ========================================================  TSCDRL  ========================================================= */
43167  #define R_TSN_TSCDRL_TSCDRL_Pos    (0UL)    /*!< TSCDRL (Bit 0)                                        */
43168  #define R_TSN_TSCDRL_TSCDRL_Msk    (0xffUL) /*!< TSCDRL (Bitfield-Mask: 0xff)                          */
43169 
43170 /* =========================================================================================================================== */
43171 /* ================                                         R_TSN_CAL                                         ================ */
43172 /* =========================================================================================================================== */
43173 
43174 /* =========================================================  TSCDR  ========================================================= */
43175  #define R_TSN_CAL_TSCDR_TSCDR_Pos    (0UL)          /*!< TSCDR (Bit 0)                                         */
43176  #define R_TSN_CAL_TSCDR_TSCDR_Msk    (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff)                     */
43177 
43178 /* =========================================================================================================================== */
43179 /* ================                                        R_TSN_CTRL                                         ================ */
43180 /* =========================================================================================================================== */
43181 
43182 /* =========================================================  TSCR  ========================================================== */
43183  #define R_TSN_CTRL_TSCR_TSEN_Pos    (7UL)    /*!< TSEN (Bit 7)                                          */
43184  #define R_TSN_CTRL_TSCR_TSEN_Msk    (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01)                            */
43185  #define R_TSN_CTRL_TSCR_TSOE_Pos    (4UL)    /*!< TSOE (Bit 4)                                          */
43186  #define R_TSN_CTRL_TSCR_TSOE_Msk    (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01)                            */
43187 
43188 /* =========================================================================================================================== */
43189 /* ================                                         R_USB_FS0                                         ================ */
43190 /* =========================================================================================================================== */
43191 
43192 /* ========================================================  SYSCFG  ========================================================= */
43193  #define R_USB_FS0_SYSCFG_SCKE_Pos         (10UL)     /*!< SCKE (Bit 10)                                         */
43194  #define R_USB_FS0_SYSCFG_SCKE_Msk         (0x400UL)  /*!< SCKE (Bitfield-Mask: 0x01)                            */
43195  #define R_USB_FS0_SYSCFG_CNEN_Pos         (8UL)      /*!< CNEN (Bit 8)                                          */
43196  #define R_USB_FS0_SYSCFG_CNEN_Msk         (0x100UL)  /*!< CNEN (Bitfield-Mask: 0x01)                            */
43197  #define R_USB_FS0_SYSCFG_DCFM_Pos         (6UL)      /*!< DCFM (Bit 6)                                          */
43198  #define R_USB_FS0_SYSCFG_DCFM_Msk         (0x40UL)   /*!< DCFM (Bitfield-Mask: 0x01)                            */
43199  #define R_USB_FS0_SYSCFG_DRPD_Pos         (5UL)      /*!< DRPD (Bit 5)                                          */
43200  #define R_USB_FS0_SYSCFG_DRPD_Msk         (0x20UL)   /*!< DRPD (Bitfield-Mask: 0x01)                            */
43201  #define R_USB_FS0_SYSCFG_DPRPU_Pos        (4UL)      /*!< DPRPU (Bit 4)                                         */
43202  #define R_USB_FS0_SYSCFG_DPRPU_Msk        (0x10UL)   /*!< DPRPU (Bitfield-Mask: 0x01)                           */
43203  #define R_USB_FS0_SYSCFG_DMRPU_Pos        (3UL)      /*!< DMRPU (Bit 3)                                         */
43204  #define R_USB_FS0_SYSCFG_DMRPU_Msk        (0x8UL)    /*!< DMRPU (Bitfield-Mask: 0x01)                           */
43205  #define R_USB_FS0_SYSCFG_USBE_Pos         (0UL)      /*!< USBE (Bit 0)                                          */
43206  #define R_USB_FS0_SYSCFG_USBE_Msk         (0x1UL)    /*!< USBE (Bitfield-Mask: 0x01)                            */
43207 /* ========================================================  BUSWAIT  ======================================================== */
43208  #define R_USB_FS0_BUSWAIT_BWAIT_Pos       (0UL)      /*!< BWAIT (Bit 0)                                         */
43209  #define R_USB_FS0_BUSWAIT_BWAIT_Msk       (0xfUL)    /*!< BWAIT (Bitfield-Mask: 0x0f)                           */
43210 /* ========================================================  SYSSTS0  ======================================================== */
43211  #define R_USB_FS0_SYSSTS0_OVCMON_Pos      (14UL)     /*!< OVCMON (Bit 14)                                       */
43212  #define R_USB_FS0_SYSSTS0_OVCMON_Msk      (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03)                          */
43213  #define R_USB_FS0_SYSSTS0_HTACT_Pos       (6UL)      /*!< HTACT (Bit 6)                                         */
43214  #define R_USB_FS0_SYSSTS0_HTACT_Msk       (0x40UL)   /*!< HTACT (Bitfield-Mask: 0x01)                           */
43215  #define R_USB_FS0_SYSSTS0_SOFEA_Pos       (5UL)      /*!< SOFEA (Bit 5)                                         */
43216  #define R_USB_FS0_SYSSTS0_SOFEA_Msk       (0x20UL)   /*!< SOFEA (Bitfield-Mask: 0x01)                           */
43217  #define R_USB_FS0_SYSSTS0_IDMON_Pos       (2UL)      /*!< IDMON (Bit 2)                                         */
43218  #define R_USB_FS0_SYSSTS0_IDMON_Msk       (0x4UL)    /*!< IDMON (Bitfield-Mask: 0x01)                           */
43219  #define R_USB_FS0_SYSSTS0_LNST_Pos        (0UL)      /*!< LNST (Bit 0)                                          */
43220  #define R_USB_FS0_SYSSTS0_LNST_Msk        (0x3UL)    /*!< LNST (Bitfield-Mask: 0x03)                            */
43221 /* ========================================================  PLLSTA  ========================================================= */
43222  #define R_USB_FS0_PLLSTA_PLLLOCK_Pos      (0UL)      /*!< PLLLOCK (Bit 0)                                       */
43223  #define R_USB_FS0_PLLSTA_PLLLOCK_Msk      (0x1UL)    /*!< PLLLOCK (Bitfield-Mask: 0x01)                         */
43224 /* =======================================================  DVSTCTR0  ======================================================== */
43225  #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos    (11UL)     /*!< HNPBTOA (Bit 11)                                      */
43226  #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk    (0x800UL)  /*!< HNPBTOA (Bitfield-Mask: 0x01)                         */
43227  #define R_USB_FS0_DVSTCTR0_EXICEN_Pos     (10UL)     /*!< EXICEN (Bit 10)                                       */
43228  #define R_USB_FS0_DVSTCTR0_EXICEN_Msk     (0x400UL)  /*!< EXICEN (Bitfield-Mask: 0x01)                          */
43229  #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos     (9UL)      /*!< VBUSEN (Bit 9)                                        */
43230  #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk     (0x200UL)  /*!< VBUSEN (Bitfield-Mask: 0x01)                          */
43231  #define R_USB_FS0_DVSTCTR0_WKUP_Pos       (8UL)      /*!< WKUP (Bit 8)                                          */
43232  #define R_USB_FS0_DVSTCTR0_WKUP_Msk       (0x100UL)  /*!< WKUP (Bitfield-Mask: 0x01)                            */
43233  #define R_USB_FS0_DVSTCTR0_RWUPE_Pos      (7UL)      /*!< RWUPE (Bit 7)                                         */
43234  #define R_USB_FS0_DVSTCTR0_RWUPE_Msk      (0x80UL)   /*!< RWUPE (Bitfield-Mask: 0x01)                           */
43235  #define R_USB_FS0_DVSTCTR0_USBRST_Pos     (6UL)      /*!< USBRST (Bit 6)                                        */
43236  #define R_USB_FS0_DVSTCTR0_USBRST_Msk     (0x40UL)   /*!< USBRST (Bitfield-Mask: 0x01)                          */
43237  #define R_USB_FS0_DVSTCTR0_RESUME_Pos     (5UL)      /*!< RESUME (Bit 5)                                        */
43238  #define R_USB_FS0_DVSTCTR0_RESUME_Msk     (0x20UL)   /*!< RESUME (Bitfield-Mask: 0x01)                          */
43239  #define R_USB_FS0_DVSTCTR0_UACT_Pos       (4UL)      /*!< UACT (Bit 4)                                          */
43240  #define R_USB_FS0_DVSTCTR0_UACT_Msk       (0x10UL)   /*!< UACT (Bitfield-Mask: 0x01)                            */
43241  #define R_USB_FS0_DVSTCTR0_RHST_Pos       (0UL)      /*!< RHST (Bit 0)                                          */
43242  #define R_USB_FS0_DVSTCTR0_RHST_Msk       (0x7UL)    /*!< RHST (Bitfield-Mask: 0x07)                            */
43243 /* =======================================================  TESTMODE  ======================================================== */
43244  #define R_USB_FS0_TESTMODE_UTST_Pos       (0UL)      /*!< UTST (Bit 0)                                          */
43245  #define R_USB_FS0_TESTMODE_UTST_Msk       (0xfUL)    /*!< UTST (Bitfield-Mask: 0x0f)                            */
43246 /* ========================================================  CFIFOL  ========================================================= */
43247 /* ========================================================  CFIFOLL  ======================================================== */
43248 /* =========================================================  CFIFO  ========================================================= */
43249 /* ========================================================  CFIFOH  ========================================================= */
43250 /* ========================================================  CFIFOHH  ======================================================== */
43251 /* ========================================================  D0FIFOL  ======================================================== */
43252 /* =======================================================  D0FIFOLL  ======================================================== */
43253 /* ========================================================  D0FIFO  ========================================================= */
43254 /* ========================================================  D0FIFOH  ======================================================== */
43255 /* =======================================================  D0FIFOHH  ======================================================== */
43256 /* ========================================================  D1FIFOL  ======================================================== */
43257 /* =======================================================  D1FIFOLL  ======================================================== */
43258 /* ========================================================  D1FIFO  ========================================================= */
43259 /* ========================================================  D1FIFOH  ======================================================== */
43260 /* =======================================================  D1FIFOHH  ======================================================== */
43261 /* =======================================================  CFIFOSEL  ======================================================== */
43262  #define R_USB_FS0_CFIFOSEL_RCNT_Pos            (15UL)       /*!< RCNT (Bit 15)                                         */
43263  #define R_USB_FS0_CFIFOSEL_RCNT_Msk            (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
43264  #define R_USB_FS0_CFIFOSEL_REW_Pos             (14UL)       /*!< REW (Bit 14)                                          */
43265  #define R_USB_FS0_CFIFOSEL_REW_Msk             (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
43266  #define R_USB_FS0_CFIFOSEL_MBW_Pos             (10UL)       /*!< MBW (Bit 10)                                          */
43267  #define R_USB_FS0_CFIFOSEL_MBW_Msk             (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
43268  #define R_USB_FS0_CFIFOSEL_BIGEND_Pos          (8UL)        /*!< BIGEND (Bit 8)                                        */
43269  #define R_USB_FS0_CFIFOSEL_BIGEND_Msk          (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
43270  #define R_USB_FS0_CFIFOSEL_ISEL_Pos            (5UL)        /*!< ISEL (Bit 5)                                          */
43271  #define R_USB_FS0_CFIFOSEL_ISEL_Msk            (0x20UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
43272  #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos         (0UL)        /*!< CURPIPE (Bit 0)                                       */
43273  #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk         (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
43274 /* =======================================================  CFIFOCTR  ======================================================== */
43275  #define R_USB_FS0_CFIFOCTR_BVAL_Pos            (15UL)       /*!< BVAL (Bit 15)                                         */
43276  #define R_USB_FS0_CFIFOCTR_BVAL_Msk            (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
43277  #define R_USB_FS0_CFIFOCTR_BCLR_Pos            (14UL)       /*!< BCLR (Bit 14)                                         */
43278  #define R_USB_FS0_CFIFOCTR_BCLR_Msk            (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
43279  #define R_USB_FS0_CFIFOCTR_FRDY_Pos            (13UL)       /*!< FRDY (Bit 13)                                         */
43280  #define R_USB_FS0_CFIFOCTR_FRDY_Msk            (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
43281  #define R_USB_FS0_CFIFOCTR_DTLN_Pos            (0UL)        /*!< DTLN (Bit 0)                                          */
43282  #define R_USB_FS0_CFIFOCTR_DTLN_Msk            (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
43283 /* =======================================================  D0FIFOSEL  ======================================================= */
43284  #define R_USB_FS0_D0FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
43285  #define R_USB_FS0_D0FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
43286  #define R_USB_FS0_D0FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
43287  #define R_USB_FS0_D0FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
43288  #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
43289  #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
43290  #define R_USB_FS0_D0FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
43291  #define R_USB_FS0_D0FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
43292  #define R_USB_FS0_D0FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
43293  #define R_USB_FS0_D0FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
43294  #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
43295  #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
43296  #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
43297  #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
43298 /* =======================================================  D0FIFOCTR  ======================================================= */
43299  #define R_USB_FS0_D0FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
43300  #define R_USB_FS0_D0FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
43301  #define R_USB_FS0_D0FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
43302  #define R_USB_FS0_D0FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
43303  #define R_USB_FS0_D0FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
43304  #define R_USB_FS0_D0FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
43305  #define R_USB_FS0_D0FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
43306  #define R_USB_FS0_D0FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
43307 /* =======================================================  D1FIFOSEL  ======================================================= */
43308  #define R_USB_FS0_D1FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
43309  #define R_USB_FS0_D1FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
43310  #define R_USB_FS0_D1FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
43311  #define R_USB_FS0_D1FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
43312  #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
43313  #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
43314  #define R_USB_FS0_D1FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
43315  #define R_USB_FS0_D1FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
43316  #define R_USB_FS0_D1FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
43317  #define R_USB_FS0_D1FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
43318  #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
43319  #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
43320  #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
43321  #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
43322 /* =======================================================  D1FIFOCTR  ======================================================= */
43323  #define R_USB_FS0_D1FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
43324  #define R_USB_FS0_D1FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
43325  #define R_USB_FS0_D1FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
43326  #define R_USB_FS0_D1FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
43327  #define R_USB_FS0_D1FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
43328  #define R_USB_FS0_D1FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
43329  #define R_USB_FS0_D1FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
43330  #define R_USB_FS0_D1FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
43331 /* ========================================================  INTENB0  ======================================================== */
43332  #define R_USB_FS0_INTENB0_VBSE_Pos             (15UL)       /*!< VBSE (Bit 15)                                         */
43333  #define R_USB_FS0_INTENB0_VBSE_Msk             (0x8000UL)   /*!< VBSE (Bitfield-Mask: 0x01)                            */
43334  #define R_USB_FS0_INTENB0_RSME_Pos             (14UL)       /*!< RSME (Bit 14)                                         */
43335  #define R_USB_FS0_INTENB0_RSME_Msk             (0x4000UL)   /*!< RSME (Bitfield-Mask: 0x01)                            */
43336  #define R_USB_FS0_INTENB0_SOFE_Pos             (13UL)       /*!< SOFE (Bit 13)                                         */
43337  #define R_USB_FS0_INTENB0_SOFE_Msk             (0x2000UL)   /*!< SOFE (Bitfield-Mask: 0x01)                            */
43338  #define R_USB_FS0_INTENB0_DVSE_Pos             (12UL)       /*!< DVSE (Bit 12)                                         */
43339  #define R_USB_FS0_INTENB0_DVSE_Msk             (0x1000UL)   /*!< DVSE (Bitfield-Mask: 0x01)                            */
43340  #define R_USB_FS0_INTENB0_CTRE_Pos             (11UL)       /*!< CTRE (Bit 11)                                         */
43341  #define R_USB_FS0_INTENB0_CTRE_Msk             (0x800UL)    /*!< CTRE (Bitfield-Mask: 0x01)                            */
43342  #define R_USB_FS0_INTENB0_BEMPE_Pos            (10UL)       /*!< BEMPE (Bit 10)                                        */
43343  #define R_USB_FS0_INTENB0_BEMPE_Msk            (0x400UL)    /*!< BEMPE (Bitfield-Mask: 0x01)                           */
43344  #define R_USB_FS0_INTENB0_NRDYE_Pos            (9UL)        /*!< NRDYE (Bit 9)                                         */
43345  #define R_USB_FS0_INTENB0_NRDYE_Msk            (0x200UL)    /*!< NRDYE (Bitfield-Mask: 0x01)                           */
43346  #define R_USB_FS0_INTENB0_BRDYE_Pos            (8UL)        /*!< BRDYE (Bit 8)                                         */
43347  #define R_USB_FS0_INTENB0_BRDYE_Msk            (0x100UL)    /*!< BRDYE (Bitfield-Mask: 0x01)                           */
43348 /* ========================================================  INTENB1  ======================================================== */
43349  #define R_USB_FS0_INTENB1_OVRCRE_Pos           (15UL)       /*!< OVRCRE (Bit 15)                                       */
43350  #define R_USB_FS0_INTENB1_OVRCRE_Msk           (0x8000UL)   /*!< OVRCRE (Bitfield-Mask: 0x01)                          */
43351  #define R_USB_FS0_INTENB1_BCHGE_Pos            (14UL)       /*!< BCHGE (Bit 14)                                        */
43352  #define R_USB_FS0_INTENB1_BCHGE_Msk            (0x4000UL)   /*!< BCHGE (Bitfield-Mask: 0x01)                           */
43353  #define R_USB_FS0_INTENB1_DTCHE_Pos            (12UL)       /*!< DTCHE (Bit 12)                                        */
43354  #define R_USB_FS0_INTENB1_DTCHE_Msk            (0x1000UL)   /*!< DTCHE (Bitfield-Mask: 0x01)                           */
43355  #define R_USB_FS0_INTENB1_ATTCHE_Pos           (11UL)       /*!< ATTCHE (Bit 11)                                       */
43356  #define R_USB_FS0_INTENB1_ATTCHE_Msk           (0x800UL)    /*!< ATTCHE (Bitfield-Mask: 0x01)                          */
43357  #define R_USB_FS0_INTENB1_EOFERRE_Pos          (6UL)        /*!< EOFERRE (Bit 6)                                       */
43358  #define R_USB_FS0_INTENB1_EOFERRE_Msk          (0x40UL)     /*!< EOFERRE (Bitfield-Mask: 0x01)                         */
43359  #define R_USB_FS0_INTENB1_SIGNE_Pos            (5UL)        /*!< SIGNE (Bit 5)                                         */
43360  #define R_USB_FS0_INTENB1_SIGNE_Msk            (0x20UL)     /*!< SIGNE (Bitfield-Mask: 0x01)                           */
43361  #define R_USB_FS0_INTENB1_SACKE_Pos            (4UL)        /*!< SACKE (Bit 4)                                         */
43362  #define R_USB_FS0_INTENB1_SACKE_Msk            (0x10UL)     /*!< SACKE (Bitfield-Mask: 0x01)                           */
43363  #define R_USB_FS0_INTENB1_PDDETINTE0_Pos       (0UL)        /*!< PDDETINTE0 (Bit 0)                                    */
43364  #define R_USB_FS0_INTENB1_PDDETINTE0_Msk       (0x1UL)      /*!< PDDETINTE0 (Bitfield-Mask: 0x01)                      */
43365 /* ========================================================  BRDYENB  ======================================================== */
43366  #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos        (0UL)        /*!< PIPEBRDYE (Bit 0)                                     */
43367  #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk        (0x1UL)      /*!< PIPEBRDYE (Bitfield-Mask: 0x01)                       */
43368 /* ========================================================  NRDYENB  ======================================================== */
43369  #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos        (0UL)        /*!< PIPENRDYE (Bit 0)                                     */
43370  #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk        (0x1UL)      /*!< PIPENRDYE (Bitfield-Mask: 0x01)                       */
43371 /* ========================================================  BEMPENB  ======================================================== */
43372  #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos        (0UL)        /*!< PIPEBEMPE (Bit 0)                                     */
43373  #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk        (0x1UL)      /*!< PIPEBEMPE (Bitfield-Mask: 0x01)                       */
43374 /* ========================================================  SOFCFG  ========================================================= */
43375  #define R_USB_FS0_SOFCFG_TRNENSEL_Pos          (8UL)        /*!< TRNENSEL (Bit 8)                                      */
43376  #define R_USB_FS0_SOFCFG_TRNENSEL_Msk          (0x100UL)    /*!< TRNENSEL (Bitfield-Mask: 0x01)                        */
43377  #define R_USB_FS0_SOFCFG_BRDYM_Pos             (6UL)        /*!< BRDYM (Bit 6)                                         */
43378  #define R_USB_FS0_SOFCFG_BRDYM_Msk             (0x40UL)     /*!< BRDYM (Bitfield-Mask: 0x01)                           */
43379  #define R_USB_FS0_SOFCFG_INTL_Pos              (5UL)        /*!< INTL (Bit 5)                                          */
43380  #define R_USB_FS0_SOFCFG_INTL_Msk              (0x20UL)     /*!< INTL (Bitfield-Mask: 0x01)                            */
43381  #define R_USB_FS0_SOFCFG_EDGESTS_Pos           (4UL)        /*!< EDGESTS (Bit 4)                                       */
43382  #define R_USB_FS0_SOFCFG_EDGESTS_Msk           (0x10UL)     /*!< EDGESTS (Bitfield-Mask: 0x01)                         */
43383 /* ========================================================  PHYSET  ========================================================= */
43384  #define R_USB_FS0_PHYSET_HSEB_Pos              (15UL)       /*!< HSEB (Bit 15)                                         */
43385  #define R_USB_FS0_PHYSET_HSEB_Msk              (0x8000UL)   /*!< HSEB (Bitfield-Mask: 0x01)                            */
43386  #define R_USB_FS0_PHYSET_REPSTART_Pos          (11UL)       /*!< REPSTART (Bit 11)                                     */
43387  #define R_USB_FS0_PHYSET_REPSTART_Msk          (0x800UL)    /*!< REPSTART (Bitfield-Mask: 0x01)                        */
43388  #define R_USB_FS0_PHYSET_REPSEL_Pos            (8UL)        /*!< REPSEL (Bit 8)                                        */
43389  #define R_USB_FS0_PHYSET_REPSEL_Msk            (0x300UL)    /*!< REPSEL (Bitfield-Mask: 0x03)                          */
43390  #define R_USB_FS0_PHYSET_CLKSEL_Pos            (4UL)        /*!< CLKSEL (Bit 4)                                        */
43391  #define R_USB_FS0_PHYSET_CLKSEL_Msk            (0x30UL)     /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
43392  #define R_USB_FS0_PHYSET_CDPEN_Pos             (3UL)        /*!< CDPEN (Bit 3)                                         */
43393  #define R_USB_FS0_PHYSET_CDPEN_Msk             (0x8UL)      /*!< CDPEN (Bitfield-Mask: 0x01)                           */
43394  #define R_USB_FS0_PHYSET_PLLRESET_Pos          (1UL)        /*!< PLLRESET (Bit 1)                                      */
43395  #define R_USB_FS0_PHYSET_PLLRESET_Msk          (0x2UL)      /*!< PLLRESET (Bitfield-Mask: 0x01)                        */
43396  #define R_USB_FS0_PHYSET_DIRPD_Pos             (0UL)        /*!< DIRPD (Bit 0)                                         */
43397  #define R_USB_FS0_PHYSET_DIRPD_Msk             (0x1UL)      /*!< DIRPD (Bitfield-Mask: 0x01)                           */
43398 /* ========================================================  INTSTS0  ======================================================== */
43399  #define R_USB_FS0_INTSTS0_VBINT_Pos            (15UL)       /*!< VBINT (Bit 15)                                        */
43400  #define R_USB_FS0_INTSTS0_VBINT_Msk            (0x8000UL)   /*!< VBINT (Bitfield-Mask: 0x01)                           */
43401  #define R_USB_FS0_INTSTS0_RESM_Pos             (14UL)       /*!< RESM (Bit 14)                                         */
43402  #define R_USB_FS0_INTSTS0_RESM_Msk             (0x4000UL)   /*!< RESM (Bitfield-Mask: 0x01)                            */
43403  #define R_USB_FS0_INTSTS0_SOFR_Pos             (13UL)       /*!< SOFR (Bit 13)                                         */
43404  #define R_USB_FS0_INTSTS0_SOFR_Msk             (0x2000UL)   /*!< SOFR (Bitfield-Mask: 0x01)                            */
43405  #define R_USB_FS0_INTSTS0_DVST_Pos             (12UL)       /*!< DVST (Bit 12)                                         */
43406  #define R_USB_FS0_INTSTS0_DVST_Msk             (0x1000UL)   /*!< DVST (Bitfield-Mask: 0x01)                            */
43407  #define R_USB_FS0_INTSTS0_CTRT_Pos             (11UL)       /*!< CTRT (Bit 11)                                         */
43408  #define R_USB_FS0_INTSTS0_CTRT_Msk             (0x800UL)    /*!< CTRT (Bitfield-Mask: 0x01)                            */
43409  #define R_USB_FS0_INTSTS0_BEMP_Pos             (10UL)       /*!< BEMP (Bit 10)                                         */
43410  #define R_USB_FS0_INTSTS0_BEMP_Msk             (0x400UL)    /*!< BEMP (Bitfield-Mask: 0x01)                            */
43411  #define R_USB_FS0_INTSTS0_NRDY_Pos             (9UL)        /*!< NRDY (Bit 9)                                          */
43412  #define R_USB_FS0_INTSTS0_NRDY_Msk             (0x200UL)    /*!< NRDY (Bitfield-Mask: 0x01)                            */
43413  #define R_USB_FS0_INTSTS0_BRDY_Pos             (8UL)        /*!< BRDY (Bit 8)                                          */
43414  #define R_USB_FS0_INTSTS0_BRDY_Msk             (0x100UL)    /*!< BRDY (Bitfield-Mask: 0x01)                            */
43415  #define R_USB_FS0_INTSTS0_VBSTS_Pos            (7UL)        /*!< VBSTS (Bit 7)                                         */
43416  #define R_USB_FS0_INTSTS0_VBSTS_Msk            (0x80UL)     /*!< VBSTS (Bitfield-Mask: 0x01)                           */
43417  #define R_USB_FS0_INTSTS0_DVSQ_Pos             (4UL)        /*!< DVSQ (Bit 4)                                          */
43418  #define R_USB_FS0_INTSTS0_DVSQ_Msk             (0x70UL)     /*!< DVSQ (Bitfield-Mask: 0x07)                            */
43419  #define R_USB_FS0_INTSTS0_VALID_Pos            (3UL)        /*!< VALID (Bit 3)                                         */
43420  #define R_USB_FS0_INTSTS0_VALID_Msk            (0x8UL)      /*!< VALID (Bitfield-Mask: 0x01)                           */
43421  #define R_USB_FS0_INTSTS0_CTSQ_Pos             (0UL)        /*!< CTSQ (Bit 0)                                          */
43422  #define R_USB_FS0_INTSTS0_CTSQ_Msk             (0x7UL)      /*!< CTSQ (Bitfield-Mask: 0x07)                            */
43423 /* ========================================================  INTSTS1  ======================================================== */
43424  #define R_USB_FS0_INTSTS1_OVRCR_Pos            (15UL)       /*!< OVRCR (Bit 15)                                        */
43425  #define R_USB_FS0_INTSTS1_OVRCR_Msk            (0x8000UL)   /*!< OVRCR (Bitfield-Mask: 0x01)                           */
43426  #define R_USB_FS0_INTSTS1_BCHG_Pos             (14UL)       /*!< BCHG (Bit 14)                                         */
43427  #define R_USB_FS0_INTSTS1_BCHG_Msk             (0x4000UL)   /*!< BCHG (Bitfield-Mask: 0x01)                            */
43428  #define R_USB_FS0_INTSTS1_DTCH_Pos             (12UL)       /*!< DTCH (Bit 12)                                         */
43429  #define R_USB_FS0_INTSTS1_DTCH_Msk             (0x1000UL)   /*!< DTCH (Bitfield-Mask: 0x01)                            */
43430  #define R_USB_FS0_INTSTS1_ATTCH_Pos            (11UL)       /*!< ATTCH (Bit 11)                                        */
43431  #define R_USB_FS0_INTSTS1_ATTCH_Msk            (0x800UL)    /*!< ATTCH (Bitfield-Mask: 0x01)                           */
43432  #define R_USB_FS0_INTSTS1_L1RSMEND_Pos         (9UL)        /*!< L1RSMEND (Bit 9)                                      */
43433  #define R_USB_FS0_INTSTS1_L1RSMEND_Msk         (0x200UL)    /*!< L1RSMEND (Bitfield-Mask: 0x01)                        */
43434  #define R_USB_FS0_INTSTS1_LPMEND_Pos           (8UL)        /*!< LPMEND (Bit 8)                                        */
43435  #define R_USB_FS0_INTSTS1_LPMEND_Msk           (0x100UL)    /*!< LPMEND (Bitfield-Mask: 0x01)                          */
43436  #define R_USB_FS0_INTSTS1_EOFERR_Pos           (6UL)        /*!< EOFERR (Bit 6)                                        */
43437  #define R_USB_FS0_INTSTS1_EOFERR_Msk           (0x40UL)     /*!< EOFERR (Bitfield-Mask: 0x01)                          */
43438  #define R_USB_FS0_INTSTS1_SIGN_Pos             (5UL)        /*!< SIGN (Bit 5)                                          */
43439  #define R_USB_FS0_INTSTS1_SIGN_Msk             (0x20UL)     /*!< SIGN (Bitfield-Mask: 0x01)                            */
43440  #define R_USB_FS0_INTSTS1_SACK_Pos             (4UL)        /*!< SACK (Bit 4)                                          */
43441  #define R_USB_FS0_INTSTS1_SACK_Msk             (0x10UL)     /*!< SACK (Bitfield-Mask: 0x01)                            */
43442  #define R_USB_FS0_INTSTS1_PDDETINT0_Pos        (0UL)        /*!< PDDETINT0 (Bit 0)                                     */
43443  #define R_USB_FS0_INTSTS1_PDDETINT0_Msk        (0x1UL)      /*!< PDDETINT0 (Bitfield-Mask: 0x01)                       */
43444 /* ========================================================  BRDYSTS  ======================================================== */
43445  #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos         (0UL)        /*!< PIPEBRDY (Bit 0)                                      */
43446  #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk         (0x1UL)      /*!< PIPEBRDY (Bitfield-Mask: 0x01)                        */
43447 /* ========================================================  NRDYSTS  ======================================================== */
43448  #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos         (0UL)        /*!< PIPENRDY (Bit 0)                                      */
43449  #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk         (0x1UL)      /*!< PIPENRDY (Bitfield-Mask: 0x01)                        */
43450 /* ========================================================  BEMPSTS  ======================================================== */
43451  #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos         (0UL)        /*!< PIPEBEMP (Bit 0)                                      */
43452  #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk         (0x1UL)      /*!< PIPEBEMP (Bitfield-Mask: 0x01)                        */
43453 /* ========================================================  FRMNUM  ========================================================= */
43454  #define R_USB_FS0_FRMNUM_OVRN_Pos              (15UL)       /*!< OVRN (Bit 15)                                         */
43455  #define R_USB_FS0_FRMNUM_OVRN_Msk              (0x8000UL)   /*!< OVRN (Bitfield-Mask: 0x01)                            */
43456  #define R_USB_FS0_FRMNUM_CRCE_Pos              (14UL)       /*!< CRCE (Bit 14)                                         */
43457  #define R_USB_FS0_FRMNUM_CRCE_Msk              (0x4000UL)   /*!< CRCE (Bitfield-Mask: 0x01)                            */
43458  #define R_USB_FS0_FRMNUM_FRNM_Pos              (0UL)        /*!< FRNM (Bit 0)                                          */
43459  #define R_USB_FS0_FRMNUM_FRNM_Msk              (0x7ffUL)    /*!< FRNM (Bitfield-Mask: 0x7ff)                           */
43460 /* ========================================================  UFRMNUM  ======================================================== */
43461  #define R_USB_FS0_UFRMNUM_DVCHG_Pos            (15UL)       /*!< DVCHG (Bit 15)                                        */
43462  #define R_USB_FS0_UFRMNUM_DVCHG_Msk            (0x8000UL)   /*!< DVCHG (Bitfield-Mask: 0x01)                           */
43463  #define R_USB_FS0_UFRMNUM_UFRNM_Pos            (0UL)        /*!< UFRNM (Bit 0)                                         */
43464  #define R_USB_FS0_UFRMNUM_UFRNM_Msk            (0x7UL)      /*!< UFRNM (Bitfield-Mask: 0x07)                           */
43465 /* ========================================================  USBADDR  ======================================================== */
43466  #define R_USB_FS0_USBADDR_STSRECOV0_Pos        (8UL)        /*!< STSRECOV0 (Bit 8)                                     */
43467  #define R_USB_FS0_USBADDR_STSRECOV0_Msk        (0x700UL)    /*!< STSRECOV0 (Bitfield-Mask: 0x07)                       */
43468  #define R_USB_FS0_USBADDR_USBADDR_Pos          (0UL)        /*!< USBADDR (Bit 0)                                       */
43469  #define R_USB_FS0_USBADDR_USBADDR_Msk          (0x7fUL)     /*!< USBADDR (Bitfield-Mask: 0x7f)                         */
43470 /* ========================================================  USBREQ  ========================================================= */
43471  #define R_USB_FS0_USBREQ_BREQUEST_Pos          (8UL)        /*!< BREQUEST (Bit 8)                                      */
43472  #define R_USB_FS0_USBREQ_BREQUEST_Msk          (0xff00UL)   /*!< BREQUEST (Bitfield-Mask: 0xff)                        */
43473  #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos     (0UL)        /*!< BMREQUESTTYPE (Bit 0)                                 */
43474  #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk     (0xffUL)     /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff)                   */
43475 /* ========================================================  USBVAL  ========================================================= */
43476  #define R_USB_FS0_USBVAL_WVALUE_Pos            (0UL)        /*!< WVALUE (Bit 0)                                        */
43477  #define R_USB_FS0_USBVAL_WVALUE_Msk            (0xffffUL)   /*!< WVALUE (Bitfield-Mask: 0xffff)                        */
43478 /* ========================================================  USBINDX  ======================================================== */
43479  #define R_USB_FS0_USBINDX_WINDEX_Pos           (0UL)        /*!< WINDEX (Bit 0)                                        */
43480  #define R_USB_FS0_USBINDX_WINDEX_Msk           (0xffffUL)   /*!< WINDEX (Bitfield-Mask: 0xffff)                        */
43481 /* ========================================================  USBLENG  ======================================================== */
43482  #define R_USB_FS0_USBLENG_WLENGTH_Pos          (0UL)        /*!< WLENGTH (Bit 0)                                       */
43483  #define R_USB_FS0_USBLENG_WLENGTH_Msk          (0xffffUL)   /*!< WLENGTH (Bitfield-Mask: 0xffff)                       */
43484 /* ========================================================  DCPCFG  ========================================================= */
43485  #define R_USB_FS0_DCPCFG_CNTMD_Pos             (8UL)        /*!< CNTMD (Bit 8)                                         */
43486  #define R_USB_FS0_DCPCFG_CNTMD_Msk             (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
43487  #define R_USB_FS0_DCPCFG_SHTNAK_Pos            (7UL)        /*!< SHTNAK (Bit 7)                                        */
43488  #define R_USB_FS0_DCPCFG_SHTNAK_Msk            (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
43489  #define R_USB_FS0_DCPCFG_DIR_Pos               (4UL)        /*!< DIR (Bit 4)                                           */
43490  #define R_USB_FS0_DCPCFG_DIR_Msk               (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
43491 /* ========================================================  DCPMAXP  ======================================================== */
43492  #define R_USB_FS0_DCPMAXP_DEVSEL_Pos           (12UL)       /*!< DEVSEL (Bit 12)                                       */
43493  #define R_USB_FS0_DCPMAXP_DEVSEL_Msk           (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
43494  #define R_USB_FS0_DCPMAXP_MXPS_Pos             (0UL)        /*!< MXPS (Bit 0)                                          */
43495  #define R_USB_FS0_DCPMAXP_MXPS_Msk             (0x7fUL)     /*!< MXPS (Bitfield-Mask: 0x7f)                            */
43496 /* ========================================================  DCPCTR  ========================================================= */
43497  #define R_USB_FS0_DCPCTR_BSTS_Pos              (15UL)       /*!< BSTS (Bit 15)                                         */
43498  #define R_USB_FS0_DCPCTR_BSTS_Msk              (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
43499  #define R_USB_FS0_DCPCTR_SUREQ_Pos             (14UL)       /*!< SUREQ (Bit 14)                                        */
43500  #define R_USB_FS0_DCPCTR_SUREQ_Msk             (0x4000UL)   /*!< SUREQ (Bitfield-Mask: 0x01)                           */
43501  #define R_USB_FS0_DCPCTR_SUREQCLR_Pos          (11UL)       /*!< SUREQCLR (Bit 11)                                     */
43502  #define R_USB_FS0_DCPCTR_SUREQCLR_Msk          (0x800UL)    /*!< SUREQCLR (Bitfield-Mask: 0x01)                        */
43503  #define R_USB_FS0_DCPCTR_SQCLR_Pos             (8UL)        /*!< SQCLR (Bit 8)                                         */
43504  #define R_USB_FS0_DCPCTR_SQCLR_Msk             (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
43505  #define R_USB_FS0_DCPCTR_SQSET_Pos             (7UL)        /*!< SQSET (Bit 7)                                         */
43506  #define R_USB_FS0_DCPCTR_SQSET_Msk             (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
43507  #define R_USB_FS0_DCPCTR_SQMON_Pos             (6UL)        /*!< SQMON (Bit 6)                                         */
43508  #define R_USB_FS0_DCPCTR_SQMON_Msk             (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
43509  #define R_USB_FS0_DCPCTR_PBUSY_Pos             (5UL)        /*!< PBUSY (Bit 5)                                         */
43510  #define R_USB_FS0_DCPCTR_PBUSY_Msk             (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
43511  #define R_USB_FS0_DCPCTR_CCPL_Pos              (2UL)        /*!< CCPL (Bit 2)                                          */
43512  #define R_USB_FS0_DCPCTR_CCPL_Msk              (0x4UL)      /*!< CCPL (Bitfield-Mask: 0x01)                            */
43513  #define R_USB_FS0_DCPCTR_PID_Pos               (0UL)        /*!< PID (Bit 0)                                           */
43514  #define R_USB_FS0_DCPCTR_PID_Msk               (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
43515 /* ========================================================  PIPESEL  ======================================================== */
43516  #define R_USB_FS0_PIPESEL_PIPESEL_Pos          (0UL)        /*!< PIPESEL (Bit 0)                                       */
43517  #define R_USB_FS0_PIPESEL_PIPESEL_Msk          (0xfUL)      /*!< PIPESEL (Bitfield-Mask: 0x0f)                         */
43518 /* ========================================================  PIPECFG  ======================================================== */
43519  #define R_USB_FS0_PIPECFG_TYPE_Pos             (14UL)       /*!< TYPE (Bit 14)                                         */
43520  #define R_USB_FS0_PIPECFG_TYPE_Msk             (0xc000UL)   /*!< TYPE (Bitfield-Mask: 0x03)                            */
43521  #define R_USB_FS0_PIPECFG_BFRE_Pos             (10UL)       /*!< BFRE (Bit 10)                                         */
43522  #define R_USB_FS0_PIPECFG_BFRE_Msk             (0x400UL)    /*!< BFRE (Bitfield-Mask: 0x01)                            */
43523  #define R_USB_FS0_PIPECFG_DBLB_Pos             (9UL)        /*!< DBLB (Bit 9)                                          */
43524  #define R_USB_FS0_PIPECFG_DBLB_Msk             (0x200UL)    /*!< DBLB (Bitfield-Mask: 0x01)                            */
43525  #define R_USB_FS0_PIPECFG_SHTNAK_Pos           (7UL)        /*!< SHTNAK (Bit 7)                                        */
43526  #define R_USB_FS0_PIPECFG_SHTNAK_Msk           (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
43527  #define R_USB_FS0_PIPECFG_DIR_Pos              (4UL)        /*!< DIR (Bit 4)                                           */
43528  #define R_USB_FS0_PIPECFG_DIR_Msk              (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
43529  #define R_USB_FS0_PIPECFG_EPNUM_Pos            (0UL)        /*!< EPNUM (Bit 0)                                         */
43530  #define R_USB_FS0_PIPECFG_EPNUM_Msk            (0xfUL)      /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
43531 /* =======================================================  PIPEMAXP  ======================================================== */
43532  #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos          (12UL)       /*!< DEVSEL (Bit 12)                                       */
43533  #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk          (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
43534  #define R_USB_FS0_PIPEMAXP_MXPS_Pos            (0UL)        /*!< MXPS (Bit 0)                                          */
43535  #define R_USB_FS0_PIPEMAXP_MXPS_Msk            (0x1ffUL)    /*!< MXPS (Bitfield-Mask: 0x1ff)                           */
43536 /* =======================================================  PIPEPERI  ======================================================== */
43537  #define R_USB_FS0_PIPEPERI_IFIS_Pos            (12UL)       /*!< IFIS (Bit 12)                                         */
43538  #define R_USB_FS0_PIPEPERI_IFIS_Msk            (0x1000UL)   /*!< IFIS (Bitfield-Mask: 0x01)                            */
43539  #define R_USB_FS0_PIPEPERI_IITV_Pos            (0UL)        /*!< IITV (Bit 0)                                          */
43540  #define R_USB_FS0_PIPEPERI_IITV_Msk            (0x7UL)      /*!< IITV (Bitfield-Mask: 0x07)                            */
43541 /* =======================================================  PIPE_CTR  ======================================================== */
43542  #define R_USB_FS0_PIPE_CTR_BSTS_Pos            (15UL)       /*!< BSTS (Bit 15)                                         */
43543  #define R_USB_FS0_PIPE_CTR_BSTS_Msk            (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
43544  #define R_USB_FS0_PIPE_CTR_INBUFM_Pos          (14UL)       /*!< INBUFM (Bit 14)                                       */
43545  #define R_USB_FS0_PIPE_CTR_INBUFM_Msk          (0x4000UL)   /*!< INBUFM (Bitfield-Mask: 0x01)                          */
43546  #define R_USB_FS0_PIPE_CTR_CSCLR_Pos           (13UL)       /*!< CSCLR (Bit 13)                                        */
43547  #define R_USB_FS0_PIPE_CTR_CSCLR_Msk           (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
43548  #define R_USB_FS0_PIPE_CTR_CSSTS_Pos           (12UL)       /*!< CSSTS (Bit 12)                                        */
43549  #define R_USB_FS0_PIPE_CTR_CSSTS_Msk           (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
43550  #define R_USB_FS0_PIPE_CTR_ATREPM_Pos          (10UL)       /*!< ATREPM (Bit 10)                                       */
43551  #define R_USB_FS0_PIPE_CTR_ATREPM_Msk          (0x400UL)    /*!< ATREPM (Bitfield-Mask: 0x01)                          */
43552  #define R_USB_FS0_PIPE_CTR_ACLRM_Pos           (9UL)        /*!< ACLRM (Bit 9)                                         */
43553  #define R_USB_FS0_PIPE_CTR_ACLRM_Msk           (0x200UL)    /*!< ACLRM (Bitfield-Mask: 0x01)                           */
43554  #define R_USB_FS0_PIPE_CTR_SQCLR_Pos           (8UL)        /*!< SQCLR (Bit 8)                                         */
43555  #define R_USB_FS0_PIPE_CTR_SQCLR_Msk           (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
43556  #define R_USB_FS0_PIPE_CTR_SQSET_Pos           (7UL)        /*!< SQSET (Bit 7)                                         */
43557  #define R_USB_FS0_PIPE_CTR_SQSET_Msk           (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
43558  #define R_USB_FS0_PIPE_CTR_SQMON_Pos           (6UL)        /*!< SQMON (Bit 6)                                         */
43559  #define R_USB_FS0_PIPE_CTR_SQMON_Msk           (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
43560  #define R_USB_FS0_PIPE_CTR_PBUSY_Pos           (5UL)        /*!< PBUSY (Bit 5)                                         */
43561  #define R_USB_FS0_PIPE_CTR_PBUSY_Msk           (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
43562  #define R_USB_FS0_PIPE_CTR_PID_Pos             (0UL)        /*!< PID (Bit 0)                                           */
43563  #define R_USB_FS0_PIPE_CTR_PID_Msk             (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
43564 /* ========================================================  DEVADD  ========================================================= */
43565  #define R_USB_FS0_DEVADD_UPPHUB_Pos            (11UL)       /*!< UPPHUB (Bit 11)                                       */
43566  #define R_USB_FS0_DEVADD_UPPHUB_Msk            (0x7800UL)   /*!< UPPHUB (Bitfield-Mask: 0x0f)                          */
43567  #define R_USB_FS0_DEVADD_HUBPORT_Pos           (8UL)        /*!< HUBPORT (Bit 8)                                       */
43568  #define R_USB_FS0_DEVADD_HUBPORT_Msk           (0x700UL)    /*!< HUBPORT (Bitfield-Mask: 0x07)                         */
43569  #define R_USB_FS0_DEVADD_USBSPD_Pos            (6UL)        /*!< USBSPD (Bit 6)                                        */
43570  #define R_USB_FS0_DEVADD_USBSPD_Msk            (0xc0UL)     /*!< USBSPD (Bitfield-Mask: 0x03)                          */
43571 /* ======================================================  USBBCCTRL0  ======================================================= */
43572  #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos     (9UL)        /*!< PDDETSTS0 (Bit 9)                                     */
43573  #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk     (0x200UL)    /*!< PDDETSTS0 (Bitfield-Mask: 0x01)                       */
43574  #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos    (8UL)        /*!< CHGDETSTS0 (Bit 8)                                    */
43575  #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk    (0x100UL)    /*!< CHGDETSTS0 (Bitfield-Mask: 0x01)                      */
43576  #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos      (7UL)        /*!< BATCHGE0 (Bit 7)                                      */
43577  #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk      (0x80UL)     /*!< BATCHGE0 (Bitfield-Mask: 0x01)                        */
43578  #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos      (5UL)        /*!< VDMSRCE0 (Bit 5)                                      */
43579  #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk      (0x20UL)     /*!< VDMSRCE0 (Bitfield-Mask: 0x01)                        */
43580  #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos     (4UL)        /*!< IDPSINKE0 (Bit 4)                                     */
43581  #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk     (0x10UL)     /*!< IDPSINKE0 (Bitfield-Mask: 0x01)                       */
43582  #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos      (3UL)        /*!< VDPSRCE0 (Bit 3)                                      */
43583  #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk      (0x8UL)      /*!< VDPSRCE0 (Bitfield-Mask: 0x01)                        */
43584  #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos     (2UL)        /*!< IDMSINKE0 (Bit 2)                                     */
43585  #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk     (0x4UL)      /*!< IDMSINKE0 (Bitfield-Mask: 0x01)                       */
43586  #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos      (1UL)        /*!< IDPSRCE0 (Bit 1)                                      */
43587  #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk      (0x2UL)      /*!< IDPSRCE0 (Bitfield-Mask: 0x01)                        */
43588  #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos        (0UL)        /*!< RPDME0 (Bit 0)                                        */
43589  #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk        (0x1UL)      /*!< RPDME0 (Bitfield-Mask: 0x01)                          */
43590 /* ========================================================  UCKSEL  ========================================================= */
43591  #define R_USB_FS0_UCKSEL_UCKSELC_Pos           (0UL)        /*!< UCKSELC (Bit 0)                                       */
43592  #define R_USB_FS0_UCKSEL_UCKSELC_Msk           (0x1UL)      /*!< UCKSELC (Bitfield-Mask: 0x01)                         */
43593 /* =========================================================  USBMC  ========================================================= */
43594  #define R_USB_FS0_USBMC_VDCEN_Pos              (7UL)        /*!< VDCEN (Bit 7)                                         */
43595  #define R_USB_FS0_USBMC_VDCEN_Msk              (0x80UL)     /*!< VDCEN (Bitfield-Mask: 0x01)                           */
43596  #define R_USB_FS0_USBMC_VDDUSBE_Pos            (0UL)        /*!< VDDUSBE (Bit 0)                                       */
43597  #define R_USB_FS0_USBMC_VDDUSBE_Msk            (0x1UL)      /*!< VDDUSBE (Bitfield-Mask: 0x01)                         */
43598 /* ========================================================  PHYSLEW  ======================================================== */
43599  #define R_USB_FS0_PHYSLEW_SLEWF01_Pos          (3UL)        /*!< SLEWF01 (Bit 3)                                       */
43600  #define R_USB_FS0_PHYSLEW_SLEWF01_Msk          (0x8UL)      /*!< SLEWF01 (Bitfield-Mask: 0x01)                         */
43601  #define R_USB_FS0_PHYSLEW_SLEWF00_Pos          (2UL)        /*!< SLEWF00 (Bit 2)                                       */
43602  #define R_USB_FS0_PHYSLEW_SLEWF00_Msk          (0x4UL)      /*!< SLEWF00 (Bitfield-Mask: 0x01)                         */
43603  #define R_USB_FS0_PHYSLEW_SLEWR01_Pos          (1UL)        /*!< SLEWR01 (Bit 1)                                       */
43604  #define R_USB_FS0_PHYSLEW_SLEWR01_Msk          (0x2UL)      /*!< SLEWR01 (Bitfield-Mask: 0x01)                         */
43605  #define R_USB_FS0_PHYSLEW_SLEWR00_Pos          (0UL)        /*!< SLEWR00 (Bit 0)                                       */
43606  #define R_USB_FS0_PHYSLEW_SLEWR00_Msk          (0x1UL)      /*!< SLEWR00 (Bitfield-Mask: 0x01)                         */
43607 /* ========================================================  LPCTRL  ========================================================= */
43608  #define R_USB_FS0_LPCTRL_HWUPM_Pos             (7UL)        /*!< HWUPM (Bit 7)                                         */
43609  #define R_USB_FS0_LPCTRL_HWUPM_Msk             (0x80UL)     /*!< HWUPM (Bitfield-Mask: 0x01)                           */
43610 /* =========================================================  LPSTS  ========================================================= */
43611  #define R_USB_FS0_LPSTS_SUSPENDM_Pos           (14UL)       /*!< SUSPENDM (Bit 14)                                     */
43612  #define R_USB_FS0_LPSTS_SUSPENDM_Msk           (0x4000UL)   /*!< SUSPENDM (Bitfield-Mask: 0x01)                        */
43613 /* ========================================================  BCCTRL  ========================================================= */
43614  #define R_USB_FS0_BCCTRL_PDDETSTS_Pos          (9UL)        /*!< PDDETSTS (Bit 9)                                      */
43615  #define R_USB_FS0_BCCTRL_PDDETSTS_Msk          (0x200UL)    /*!< PDDETSTS (Bitfield-Mask: 0x01)                        */
43616  #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos         (8UL)        /*!< CHGDETSTS (Bit 8)                                     */
43617  #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk         (0x100UL)    /*!< CHGDETSTS (Bitfield-Mask: 0x01)                       */
43618  #define R_USB_FS0_BCCTRL_DCPMODE_Pos           (5UL)        /*!< DCPMODE (Bit 5)                                       */
43619  #define R_USB_FS0_BCCTRL_DCPMODE_Msk           (0x20UL)     /*!< DCPMODE (Bitfield-Mask: 0x01)                         */
43620  #define R_USB_FS0_BCCTRL_VDMSRCE_Pos           (4UL)        /*!< VDMSRCE (Bit 4)                                       */
43621  #define R_USB_FS0_BCCTRL_VDMSRCE_Msk           (0x10UL)     /*!< VDMSRCE (Bitfield-Mask: 0x01)                         */
43622  #define R_USB_FS0_BCCTRL_IDPSINKE_Pos          (3UL)        /*!< IDPSINKE (Bit 3)                                      */
43623  #define R_USB_FS0_BCCTRL_IDPSINKE_Msk          (0x8UL)      /*!< IDPSINKE (Bitfield-Mask: 0x01)                        */
43624  #define R_USB_FS0_BCCTRL_VDPSRCE_Pos           (2UL)        /*!< VDPSRCE (Bit 2)                                       */
43625  #define R_USB_FS0_BCCTRL_VDPSRCE_Msk           (0x4UL)      /*!< VDPSRCE (Bitfield-Mask: 0x01)                         */
43626  #define R_USB_FS0_BCCTRL_IDMSINKE_Pos          (1UL)        /*!< IDMSINKE (Bit 1)                                      */
43627  #define R_USB_FS0_BCCTRL_IDMSINKE_Msk          (0x2UL)      /*!< IDMSINKE (Bitfield-Mask: 0x01)                        */
43628  #define R_USB_FS0_BCCTRL_IDPSRCE_Pos           (0UL)        /*!< IDPSRCE (Bit 0)                                       */
43629  #define R_USB_FS0_BCCTRL_IDPSRCE_Msk           (0x1UL)      /*!< IDPSRCE (Bitfield-Mask: 0x01)                         */
43630 /* =======================================================  PL1CTRL1  ======================================================== */
43631  #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos         (14UL)       /*!< L1EXTMD (Bit 14)                                      */
43632  #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk         (0x4000UL)   /*!< L1EXTMD (Bitfield-Mask: 0x01)                         */
43633  #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos         (8UL)        /*!< HIRDTHR (Bit 8)                                       */
43634  #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk         (0xf00UL)    /*!< HIRDTHR (Bitfield-Mask: 0x0f)                         */
43635  #define R_USB_FS0_PL1CTRL1_DVSQ_Pos            (4UL)        /*!< DVSQ (Bit 4)                                          */
43636  #define R_USB_FS0_PL1CTRL1_DVSQ_Msk            (0xf0UL)     /*!< DVSQ (Bitfield-Mask: 0x0f)                            */
43637  #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos        (3UL)        /*!< L1NEGOMD (Bit 3)                                      */
43638  #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk        (0x8UL)      /*!< L1NEGOMD (Bitfield-Mask: 0x01)                        */
43639  #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos        (1UL)        /*!< L1RESPMD (Bit 1)                                      */
43640  #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk        (0x6UL)      /*!< L1RESPMD (Bitfield-Mask: 0x03)                        */
43641  #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos        (0UL)        /*!< L1RESPEN (Bit 0)                                      */
43642  #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk        (0x1UL)      /*!< L1RESPEN (Bitfield-Mask: 0x01)                        */
43643 /* =======================================================  PL1CTRL2  ======================================================== */
43644  #define R_USB_FS0_PL1CTRL2_RWEMON_Pos          (12UL)       /*!< RWEMON (Bit 12)                                       */
43645  #define R_USB_FS0_PL1CTRL2_RWEMON_Msk          (0x1000UL)   /*!< RWEMON (Bitfield-Mask: 0x01)                          */
43646  #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos         (8UL)        /*!< HIRDMON (Bit 8)                                       */
43647  #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk         (0xf00UL)    /*!< HIRDMON (Bitfield-Mask: 0x0f)                         */
43648 /* =======================================================  HL1CTRL1  ======================================================== */
43649  #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos        (1UL)        /*!< L1STATUS (Bit 1)                                      */
43650  #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk        (0x6UL)      /*!< L1STATUS (Bitfield-Mask: 0x03)                        */
43651  #define R_USB_FS0_HL1CTRL1_L1REQ_Pos           (0UL)        /*!< L1REQ (Bit 0)                                         */
43652  #define R_USB_FS0_HL1CTRL1_L1REQ_Msk           (0x1UL)      /*!< L1REQ (Bitfield-Mask: 0x01)                           */
43653 /* =======================================================  HL1CTRL2  ======================================================== */
43654  #define R_USB_FS0_HL1CTRL2_BESL_Pos            (15UL)       /*!< BESL (Bit 15)                                         */
43655  #define R_USB_FS0_HL1CTRL2_BESL_Msk            (0x8000UL)   /*!< BESL (Bitfield-Mask: 0x01)                            */
43656  #define R_USB_FS0_HL1CTRL2_L1RWE_Pos           (12UL)       /*!< L1RWE (Bit 12)                                        */
43657  #define R_USB_FS0_HL1CTRL2_L1RWE_Msk           (0x1000UL)   /*!< L1RWE (Bitfield-Mask: 0x01)                           */
43658  #define R_USB_FS0_HL1CTRL2_HIRD_Pos            (8UL)        /*!< HIRD (Bit 8)                                          */
43659  #define R_USB_FS0_HL1CTRL2_HIRD_Msk            (0xf00UL)    /*!< HIRD (Bitfield-Mask: 0x0f)                            */
43660  #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos          (0UL)        /*!< L1ADDR (Bit 0)                                        */
43661  #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk          (0xfUL)      /*!< L1ADDR (Bitfield-Mask: 0x0f)                          */
43662 /* ========================================================  DPUSR0R  ======================================================== */
43663  #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos         (23UL)       /*!< DVBSTSHM (Bit 23)                                     */
43664  #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk         (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01)                        */
43665  #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos          (21UL)       /*!< DOVCBHM (Bit 21)                                      */
43666  #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk          (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01)                         */
43667  #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos          (20UL)       /*!< DOVCAHM (Bit 20)                                      */
43668  #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk          (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01)                         */
43669 /* ========================================================  DPUSR1R  ======================================================== */
43670  #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos          (23UL)       /*!< DVBSTSH (Bit 23)                                      */
43671  #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk          (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01)                         */
43672  #define R_USB_FS0_DPUSR1R_DOVCBH_Pos           (21UL)       /*!< DOVCBH (Bit 21)                                       */
43673  #define R_USB_FS0_DPUSR1R_DOVCBH_Msk           (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01)                          */
43674  #define R_USB_FS0_DPUSR1R_DOVCAH_Pos           (20UL)       /*!< DOVCAH (Bit 20)                                       */
43675  #define R_USB_FS0_DPUSR1R_DOVCAH_Msk           (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01)                          */
43676  #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos         (7UL)        /*!< DVBSTSHE (Bit 7)                                      */
43677  #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk         (0x80UL)     /*!< DVBSTSHE (Bitfield-Mask: 0x01)                        */
43678  #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos          (5UL)        /*!< DOVCBHE (Bit 5)                                       */
43679  #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk          (0x20UL)     /*!< DOVCBHE (Bitfield-Mask: 0x01)                         */
43680  #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos          (4UL)        /*!< DOVCAHE (Bit 4)                                       */
43681  #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk          (0x10UL)     /*!< DOVCAHE (Bitfield-Mask: 0x01)                         */
43682 /* ========================================================  DPUSR2R  ======================================================== */
43683  #define R_USB_FS0_DPUSR2R_DMINTE_Pos           (9UL)        /*!< DMINTE (Bit 9)                                        */
43684  #define R_USB_FS0_DPUSR2R_DMINTE_Msk           (0x200UL)    /*!< DMINTE (Bitfield-Mask: 0x01)                          */
43685  #define R_USB_FS0_DPUSR2R_DPINTE_Pos           (8UL)        /*!< DPINTE (Bit 8)                                        */
43686  #define R_USB_FS0_DPUSR2R_DPINTE_Msk           (0x100UL)    /*!< DPINTE (Bitfield-Mask: 0x01)                          */
43687  #define R_USB_FS0_DPUSR2R_DMVAL_Pos            (5UL)        /*!< DMVAL (Bit 5)                                         */
43688  #define R_USB_FS0_DPUSR2R_DMVAL_Msk            (0x20UL)     /*!< DMVAL (Bitfield-Mask: 0x01)                           */
43689  #define R_USB_FS0_DPUSR2R_DPVAL_Pos            (4UL)        /*!< DPVAL (Bit 4)                                         */
43690  #define R_USB_FS0_DPUSR2R_DPVAL_Msk            (0x10UL)     /*!< DPVAL (Bitfield-Mask: 0x01)                           */
43691  #define R_USB_FS0_DPUSR2R_DMINT_Pos            (1UL)        /*!< DMINT (Bit 1)                                         */
43692  #define R_USB_FS0_DPUSR2R_DMINT_Msk            (0x2UL)      /*!< DMINT (Bitfield-Mask: 0x01)                           */
43693  #define R_USB_FS0_DPUSR2R_DPINT_Pos            (0UL)        /*!< DPINT (Bit 0)                                         */
43694  #define R_USB_FS0_DPUSR2R_DPINT_Msk            (0x1UL)      /*!< DPINT (Bitfield-Mask: 0x01)                           */
43695 /* ========================================================  DPUSRCR  ======================================================== */
43696  #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos         (1UL)        /*!< FIXPHYPD (Bit 1)                                      */
43697  #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk         (0x2UL)      /*!< FIXPHYPD (Bitfield-Mask: 0x01)                        */
43698  #define R_USB_FS0_DPUSRCR_FIXPHY_Pos           (0UL)        /*!< FIXPHY (Bit 0)                                        */
43699  #define R_USB_FS0_DPUSRCR_FIXPHY_Msk           (0x1UL)      /*!< FIXPHY (Bitfield-Mask: 0x01)                          */
43700 /* ======================================================  DPUSR0R_FS  ======================================================= */
43701  #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos       (23UL)       /*!< DVBSTS0 (Bit 23)                                      */
43702  #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk       (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01)                         */
43703  #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos        (21UL)       /*!< DOVCB0 (Bit 21)                                       */
43704  #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk        (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01)                          */
43705  #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos        (20UL)       /*!< DOVCA0 (Bit 20)                                       */
43706  #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk        (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01)                          */
43707  #define R_USB_FS0_DPUSR0R_FS_DM0_Pos           (17UL)       /*!< DM0 (Bit 17)                                          */
43708  #define R_USB_FS0_DPUSR0R_FS_DM0_Msk           (0x20000UL)  /*!< DM0 (Bitfield-Mask: 0x01)                             */
43709  #define R_USB_FS0_DPUSR0R_FS_DP0_Pos           (16UL)       /*!< DP0 (Bit 16)                                          */
43710  #define R_USB_FS0_DPUSR0R_FS_DP0_Msk           (0x10000UL)  /*!< DP0 (Bitfield-Mask: 0x01)                             */
43711  #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos       (4UL)        /*!< FIXPHY0 (Bit 4)                                       */
43712  #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk       (0x10UL)     /*!< FIXPHY0 (Bitfield-Mask: 0x01)                         */
43713  #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos         (3UL)        /*!< DRPD0 (Bit 3)                                         */
43714  #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk         (0x8UL)      /*!< DRPD0 (Bitfield-Mask: 0x01)                           */
43715  #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos         (1UL)        /*!< RPUE0 (Bit 1)                                         */
43716  #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk         (0x2UL)      /*!< RPUE0 (Bitfield-Mask: 0x01)                           */
43717  #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos         (0UL)        /*!< SRPC0 (Bit 0)                                         */
43718  #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk         (0x1UL)      /*!< SRPC0 (Bitfield-Mask: 0x01)                           */
43719 /* ======================================================  DPUSR1R_FS  ======================================================= */
43720  #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos       (23UL)       /*!< DVBINT0 (Bit 23)                                      */
43721  #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk       (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01)                         */
43722  #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos      (21UL)       /*!< DOVRCRB0 (Bit 21)                                     */
43723  #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk      (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01)                        */
43724  #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos      (20UL)       /*!< DOVRCRA0 (Bit 20)                                     */
43725  #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk      (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01)                        */
43726  #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos        (17UL)       /*!< DMINT0 (Bit 17)                                       */
43727  #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk        (0x20000UL)  /*!< DMINT0 (Bitfield-Mask: 0x01)                          */
43728  #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos        (16UL)       /*!< DPINT0 (Bit 16)                                       */
43729  #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk        (0x10000UL)  /*!< DPINT0 (Bitfield-Mask: 0x01)                          */
43730  #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos        (7UL)        /*!< DVBSE0 (Bit 7)                                        */
43731  #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk        (0x80UL)     /*!< DVBSE0 (Bitfield-Mask: 0x01)                          */
43732  #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos     (5UL)        /*!< DOVRCRBE0 (Bit 5)                                     */
43733  #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk     (0x20UL)     /*!< DOVRCRBE0 (Bitfield-Mask: 0x01)                       */
43734  #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos     (4UL)        /*!< DOVRCRAE0 (Bit 4)                                     */
43735  #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk     (0x10UL)     /*!< DOVRCRAE0 (Bitfield-Mask: 0x01)                       */
43736  #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos       (1UL)        /*!< DMINTE0 (Bit 1)                                       */
43737  #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk       (0x2UL)      /*!< DMINTE0 (Bitfield-Mask: 0x01)                         */
43738  #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos       (0UL)        /*!< DPINTE0 (Bit 0)                                       */
43739  #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk       (0x1UL)      /*!< DPINTE0 (Bitfield-Mask: 0x01)                         */
43740 
43741 /* =========================================================================================================================== */
43742 /* ================                                           R_WDT                                           ================ */
43743 /* =========================================================================================================================== */
43744 
43745 /* =========================================================  WDTRR  ========================================================= */
43746  #define R_WDT_WDTRR_WDTRR_Pos        (0UL)      /*!< WDTRR (Bit 0)                                         */
43747  #define R_WDT_WDTRR_WDTRR_Msk        (0xffUL)   /*!< WDTRR (Bitfield-Mask: 0xff)                           */
43748 /* =========================================================  WDTCR  ========================================================= */
43749  #define R_WDT_WDTCR_RPSS_Pos         (12UL)     /*!< RPSS (Bit 12)                                         */
43750  #define R_WDT_WDTCR_RPSS_Msk         (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
43751  #define R_WDT_WDTCR_RPES_Pos         (8UL)      /*!< RPES (Bit 8)                                          */
43752  #define R_WDT_WDTCR_RPES_Msk         (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
43753  #define R_WDT_WDTCR_CKS_Pos          (4UL)      /*!< CKS (Bit 4)                                           */
43754  #define R_WDT_WDTCR_CKS_Msk          (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
43755  #define R_WDT_WDTCR_TOPS_Pos         (0UL)      /*!< TOPS (Bit 0)                                          */
43756  #define R_WDT_WDTCR_TOPS_Msk         (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
43757 /* =========================================================  WDTSR  ========================================================= */
43758  #define R_WDT_WDTSR_REFEF_Pos        (15UL)     /*!< REFEF (Bit 15)                                        */
43759  #define R_WDT_WDTSR_REFEF_Msk        (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
43760  #define R_WDT_WDTSR_UNDFF_Pos        (14UL)     /*!< UNDFF (Bit 14)                                        */
43761  #define R_WDT_WDTSR_UNDFF_Msk        (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
43762  #define R_WDT_WDTSR_CNTVAL_Pos       (0UL)      /*!< CNTVAL (Bit 0)                                        */
43763  #define R_WDT_WDTSR_CNTVAL_Msk       (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
43764 /* ========================================================  WDTRCR  ========================================================= */
43765  #define R_WDT_WDTRCR_RSTIRQS_Pos     (7UL)      /*!< RSTIRQS (Bit 7)                                       */
43766  #define R_WDT_WDTRCR_RSTIRQS_Msk     (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
43767 /* =======================================================  WDTCSTPR  ======================================================== */
43768  #define R_WDT_WDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
43769  #define R_WDT_WDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
43770 
43771 /* =========================================================================================================================== */
43772 /* ================                                           R_TZF                                           ================ */
43773 /* =========================================================================================================================== */
43774 
43775 /* ========================================================  TZFOAD  ========================================================= */
43776  #define R_TZF_TZFOAD_OAD_Pos       (0UL)      /*!< OAD (Bit 0)                                           */
43777  #define R_TZF_TZFOAD_OAD_Msk       (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
43778  #define R_TZF_TZFOAD_KEY_Pos       (8UL)      /*!< KEY (Bit 8)                                           */
43779  #define R_TZF_TZFOAD_KEY_Msk       (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
43780 /* =========================================================  TZFPT  ========================================================= */
43781  #define R_TZF_TZFPT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
43782  #define R_TZF_TZFPT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
43783  #define R_TZF_TZFPT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
43784  #define R_TZF_TZFPT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
43785 /* ========================================================  TZFSAR  ========================================================= */
43786  #define R_TZF_TZFSAR_TZFSA0_Pos    (0UL)      /*!< TZFSA0 (Bit 0)                                        */
43787  #define R_TZF_TZFSAR_TZFSA0_Msk    (0x1UL)    /*!< TZFSA0 (Bitfield-Mask: 0x01)                          */
43788 
43789 /* =========================================================================================================================== */
43790 /* ================                                          R_CACHE                                          ================ */
43791 /* =========================================================================================================================== */
43792 
43793 /* ========================================================  CCACTL  ========================================================= */
43794  #define R_CACHE_CCACTL_ENC_Pos     (0UL)    /*!< ENC (Bit 0)                                           */
43795  #define R_CACHE_CCACTL_ENC_Msk     (0x1UL)  /*!< ENC (Bitfield-Mask: 0x01)                             */
43796 /* ========================================================  CCAFCT  ========================================================= */
43797  #define R_CACHE_CCAFCT_FC_Pos      (0UL)    /*!< FC (Bit 0)                                            */
43798  #define R_CACHE_CCAFCT_FC_Msk      (0x1UL)  /*!< FC (Bitfield-Mask: 0x01)                              */
43799 /* ========================================================  CCALCF  ========================================================= */
43800  #define R_CACHE_CCALCF_CC_Pos      (0UL)    /*!< CC (Bit 0)                                            */
43801  #define R_CACHE_CCALCF_CC_Msk      (0x3UL)  /*!< CC (Bitfield-Mask: 0x03)                              */
43802 /* ========================================================  SCACTL  ========================================================= */
43803  #define R_CACHE_SCACTL_ENS_Pos     (0UL)    /*!< ENS (Bit 0)                                           */
43804  #define R_CACHE_SCACTL_ENS_Msk     (0x1UL)  /*!< ENS (Bitfield-Mask: 0x01)                             */
43805 /* ========================================================  SCAFCT  ========================================================= */
43806  #define R_CACHE_SCAFCT_FS_Pos      (0UL)    /*!< FS (Bit 0)                                            */
43807  #define R_CACHE_SCAFCT_FS_Msk      (0x1UL)  /*!< FS (Bitfield-Mask: 0x01)                              */
43808 /* ========================================================  SCALCF  ========================================================= */
43809  #define R_CACHE_SCALCF_CS_Pos      (0UL)    /*!< CS (Bit 0)                                            */
43810  #define R_CACHE_SCALCF_CS_Msk      (0x3UL)  /*!< CS (Bitfield-Mask: 0x03)                              */
43811 /* ========================================================  CAPOAD  ========================================================= */
43812  #define R_CACHE_CAPOAD_OAD_Pos     (0UL)    /*!< OAD (Bit 0)                                           */
43813  #define R_CACHE_CAPOAD_OAD_Msk     (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
43814 /* ========================================================  CAPRCR  ========================================================= */
43815  #define R_CACHE_CAPRCR_PRCR_Pos    (0UL)    /*!< PRCR (Bit 0)                                          */
43816  #define R_CACHE_CAPRCR_PRCR_Msk    (0x1UL)  /*!< PRCR (Bitfield-Mask: 0x01)                            */
43817  #define R_CACHE_CAPRCR_KW_Pos      (1UL)    /*!< KW (Bit 1)                                            */
43818  #define R_CACHE_CAPRCR_KW_Msk      (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
43819 
43820 /* =========================================================================================================================== */
43821 /* ================                                          R_CPSCU                                          ================ */
43822 /* =========================================================================================================================== */
43823 
43824 /* =========================================================  CSAR  ========================================================== */
43825  #define R_CPSCU_CSAR_CACHESA_Pos           (0UL)          /*!< CACHESA (Bit 0)                                       */
43826  #define R_CPSCU_CSAR_CACHESA_Msk           (0x1UL)        /*!< CACHESA (Bitfield-Mask: 0x01)                         */
43827  #define R_CPSCU_CSAR_CACHELSA_Pos          (1UL)          /*!< CACHELSA (Bit 1)                                      */
43828  #define R_CPSCU_CSAR_CACHELSA_Msk          (0x2UL)        /*!< CACHELSA (Bitfield-Mask: 0x01)                        */
43829  #define R_CPSCU_CSAR_CACHEESA_Pos          (2UL)          /*!< CACHEESA (Bit 2)                                      */
43830  #define R_CPSCU_CSAR_CACHEESA_Msk          (0x4UL)        /*!< CACHEESA (Bitfield-Mask: 0x01)                        */
43831 /* ========================================================  SRAMSAR  ======================================================== */
43832  #define R_CPSCU_SRAMSAR_SRAMSA0_Pos        (0UL)          /*!< SRAMSA0 (Bit 0)                                       */
43833  #define R_CPSCU_SRAMSAR_SRAMSA0_Msk        (0x1UL)        /*!< SRAMSA0 (Bitfield-Mask: 0x01)                         */
43834  #define R_CPSCU_SRAMSAR_SRAMSA1_Pos        (1UL)          /*!< SRAMSA1 (Bit 1)                                       */
43835  #define R_CPSCU_SRAMSAR_SRAMSA1_Msk        (0x2UL)        /*!< SRAMSA1 (Bitfield-Mask: 0x01)                         */
43836  #define R_CPSCU_SRAMSAR_SRAMSA2_Pos        (2UL)          /*!< SRAMSA2 (Bit 2)                                       */
43837  #define R_CPSCU_SRAMSAR_SRAMSA2_Msk        (0x4UL)        /*!< SRAMSA2 (Bitfield-Mask: 0x01)                         */
43838 /* =======================================================  STBRAMSAR  ======================================================= */
43839  #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos      (0UL)          /*!< NSBSTBR (Bit 0)                                       */
43840  #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk      (0xfUL)        /*!< NSBSTBR (Bitfield-Mask: 0x0f)                         */
43841 /* ========================================================  DTCSAR  ========================================================= */
43842  #define R_CPSCU_DTCSAR_DTCSTSA_Pos         (0UL)          /*!< DTCSTSA (Bit 0)                                       */
43843  #define R_CPSCU_DTCSAR_DTCSTSA_Msk         (0x1UL)        /*!< DTCSTSA (Bitfield-Mask: 0x01)                         */
43844 /* ========================================================  DMACSAR  ======================================================== */
43845  #define R_CPSCU_DMACSAR_DMASTSA_Pos        (0UL)          /*!< DMASTSA (Bit 0)                                       */
43846  #define R_CPSCU_DMACSAR_DMASTSA_Msk        (0x1UL)        /*!< DMASTSA (Bitfield-Mask: 0x01)                         */
43847 /* ========================================================  ICUSARA  ======================================================== */
43848  #define R_CPSCU_ICUSARA_SAIRQCRn_Pos       (0UL)          /*!< SAIRQCRn (Bit 0)                                      */
43849  #define R_CPSCU_ICUSARA_SAIRQCRn_Msk       (0xffffUL)     /*!< SAIRQCRn (Bitfield-Mask: 0xffff)                      */
43850 /* ========================================================  ICUSARB  ======================================================== */
43851  #define R_CPSCU_ICUSARB_SANMI_Pos          (0UL)          /*!< SANMI (Bit 0)                                         */
43852  #define R_CPSCU_ICUSARB_SANMI_Msk          (0x1UL)        /*!< SANMI (Bitfield-Mask: 0x01)                           */
43853 /* ========================================================  ICUSARC  ======================================================== */
43854  #define R_CPSCU_ICUSARC_SADMACn_Pos        (0UL)          /*!< SADMACn (Bit 0)                                       */
43855  #define R_CPSCU_ICUSARC_SADMACn_Msk        (0xffUL)       /*!< SADMACn (Bitfield-Mask: 0xff)                         */
43856 /* ========================================================  ICUSARD  ======================================================== */
43857  #define R_CPSCU_ICUSARD_SASELSR0_Pos       (0UL)          /*!< SASELSR0 (Bit 0)                                      */
43858  #define R_CPSCU_ICUSARD_SASELSR0_Msk       (0x1UL)        /*!< SASELSR0 (Bitfield-Mask: 0x01)                        */
43859 /* ========================================================  ICUSARE  ======================================================== */
43860  #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos      (16UL)         /*!< SAIWDTWUP (Bit 16)                                    */
43861  #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk      (0x10000UL)    /*!< SAIWDTWUP (Bitfield-Mask: 0x01)                       */
43862  #define R_CPSCU_ICUSARE_SALVD1WUP_Pos      (18UL)         /*!< SALVD1WUP (Bit 18)                                    */
43863  #define R_CPSCU_ICUSARE_SALVD1WUP_Msk      (0x40000UL)    /*!< SALVD1WUP (Bitfield-Mask: 0x01)                       */
43864  #define R_CPSCU_ICUSARE_SALVD2WUP_Pos      (19UL)         /*!< SALVD2WUP (Bit 19)                                    */
43865  #define R_CPSCU_ICUSARE_SALVD2WUP_Msk      (0x80000UL)    /*!< SALVD2WUP (Bitfield-Mask: 0x01)                       */
43866  #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos    (24UL)         /*!< SARTCALMWUP (Bit 24)                                  */
43867  #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk    (0x1000000UL)  /*!< SARTCALMWUP (Bitfield-Mask: 0x01)                     */
43868  #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos    (25UL)         /*!< SARTCPRDWUP (Bit 25)                                  */
43869  #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk    (0x2000000UL)  /*!< SARTCPRDWUP (Bitfield-Mask: 0x01)                     */
43870  #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos    (27UL)         /*!< SAUSBFS0WUP (Bit 27)                                  */
43871  #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk    (0x8000000UL)  /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01)                     */
43872  #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos    (28UL)         /*!< SAAGT1UDWUP (Bit 28)                                  */
43873  #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk    (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01)                     */
43874  #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos    (29UL)         /*!< SAAGT1CAWUP (Bit 29)                                  */
43875  #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk    (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01)                     */
43876  #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos    (30UL)         /*!< SAAGT1CBWUP (Bit 30)                                  */
43877  #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk    (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01)                     */
43878  #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos      (31UL)         /*!< SAIIC0WUP (Bit 31)                                    */
43879  #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk      (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01)                       */
43880 /* ========================================================  ICUSARF  ======================================================== */
43881  #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos    (0UL)          /*!< SAAGT3UDWUP (Bit 0)                                   */
43882  #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk    (0x1UL)        /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01)                     */
43883  #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos    (1UL)          /*!< SAAGT3CAWUP (Bit 1)                                   */
43884  #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk    (0x2UL)        /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01)                     */
43885  #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos    (2UL)          /*!< SAAGT3CBWUP (Bit 2)                                   */
43886  #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk    (0x4UL)        /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01)                     */
43887 /* ========================================================  ICUSARG  ======================================================== */
43888  #define R_CPSCU_ICUSARG_SAIELSRn_Pos       (0UL)          /*!< SAIELSRn (Bit 0)                                      */
43889  #define R_CPSCU_ICUSARG_SAIELSRn_Msk       (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
43890 /* ========================================================  ICUSARH  ======================================================== */
43891  #define R_CPSCU_ICUSARH_SAIELSRn_Pos       (0UL)          /*!< SAIELSRn (Bit 0)                                      */
43892  #define R_CPSCU_ICUSARH_SAIELSRn_Msk       (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
43893 /* ========================================================  ICUSARI  ======================================================== */
43894  #define R_CPSCU_ICUSARI_SAIELSRn_Pos       (0UL)          /*!< SAIELSRn (Bit 0)                                      */
43895  #define R_CPSCU_ICUSARI_SAIELSRn_Msk       (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
43896 /* ========================================================  BUSSARA  ======================================================== */
43897  #define R_CPSCU_BUSSARA_BUSSA0_Pos         (0UL)          /*!< BUSSA0 (Bit 0)                                        */
43898  #define R_CPSCU_BUSSARA_BUSSA0_Msk         (0x1UL)        /*!< BUSSA0 (Bitfield-Mask: 0x01)                          */
43899 /* ========================================================  BUSSARB  ======================================================== */
43900  #define R_CPSCU_BUSSARB_BUSSB0_Pos         (0UL)          /*!< BUSSB0 (Bit 0)                                        */
43901  #define R_CPSCU_BUSSARB_BUSSB0_Msk         (0x1UL)        /*!< BUSSB0 (Bitfield-Mask: 0x01)                          */
43902 /* =======================================================  MMPUSARA  ======================================================== */
43903  #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos      (0UL)          /*!< MMPUAnSA (Bit 0)                                      */
43904  #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk      (0xffUL)       /*!< MMPUAnSA (Bitfield-Mask: 0xff)                        */
43905 /* =======================================================  MMPUSARB  ======================================================== */
43906  #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos      (0UL)          /*!< MMPUB0SA (Bit 0)                                      */
43907  #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk      (0x1UL)        /*!< MMPUB0SA (Bitfield-Mask: 0x01)                        */
43908 /* ========================================================  CPUDSAR  ======================================================== */
43909  #define R_CPSCU_CPUDSAR_CPUDSA0_Pos        (0UL)          /*!< CPUDSA0 (Bit 0)                                       */
43910  #define R_CPSCU_CPUDSAR_CPUDSA0_Msk        (0x1UL)        /*!< CPUDSA0 (Bitfield-Mask: 0x01)                         */
43911 
43912 /* =========================================================================================================================== */
43913 /* ================                                           R_CEC                                           ================ */
43914 /* =========================================================================================================================== */
43915 
43916 /* =========================================================  CADR  ========================================================== */
43917  #define R_CEC_CADR_ADR00_Pos            (0UL)      /*!< ADR00 (Bit 0)                                         */
43918  #define R_CEC_CADR_ADR00_Msk            (0x1UL)    /*!< ADR00 (Bitfield-Mask: 0x01)                           */
43919  #define R_CEC_CADR_ADR01_Pos            (1UL)      /*!< ADR01 (Bit 1)                                         */
43920  #define R_CEC_CADR_ADR01_Msk            (0x2UL)    /*!< ADR01 (Bitfield-Mask: 0x01)                           */
43921  #define R_CEC_CADR_ADR02_Pos            (2UL)      /*!< ADR02 (Bit 2)                                         */
43922  #define R_CEC_CADR_ADR02_Msk            (0x4UL)    /*!< ADR02 (Bitfield-Mask: 0x01)                           */
43923  #define R_CEC_CADR_ADR03_Pos            (3UL)      /*!< ADR03 (Bit 3)                                         */
43924  #define R_CEC_CADR_ADR03_Msk            (0x8UL)    /*!< ADR03 (Bitfield-Mask: 0x01)                           */
43925  #define R_CEC_CADR_ADR04_Pos            (4UL)      /*!< ADR04 (Bit 4)                                         */
43926  #define R_CEC_CADR_ADR04_Msk            (0x10UL)   /*!< ADR04 (Bitfield-Mask: 0x01)                           */
43927  #define R_CEC_CADR_ADR05_Pos            (5UL)      /*!< ADR05 (Bit 5)                                         */
43928  #define R_CEC_CADR_ADR05_Msk            (0x20UL)   /*!< ADR05 (Bitfield-Mask: 0x01)                           */
43929  #define R_CEC_CADR_ADR06_Pos            (6UL)      /*!< ADR06 (Bit 6)                                         */
43930  #define R_CEC_CADR_ADR06_Msk            (0x40UL)   /*!< ADR06 (Bitfield-Mask: 0x01)                           */
43931  #define R_CEC_CADR_ADR07_Pos            (7UL)      /*!< ADR07 (Bit 7)                                         */
43932  #define R_CEC_CADR_ADR07_Msk            (0x80UL)   /*!< ADR07 (Bitfield-Mask: 0x01)                           */
43933  #define R_CEC_CADR_ADR08_Pos            (8UL)      /*!< ADR08 (Bit 8)                                         */
43934  #define R_CEC_CADR_ADR08_Msk            (0x100UL)  /*!< ADR08 (Bitfield-Mask: 0x01)                           */
43935  #define R_CEC_CADR_ADR09_Pos            (9UL)      /*!< ADR09 (Bit 9)                                         */
43936  #define R_CEC_CADR_ADR09_Msk            (0x200UL)  /*!< ADR09 (Bitfield-Mask: 0x01)                           */
43937  #define R_CEC_CADR_ADR10_Pos            (10UL)     /*!< ADR10 (Bit 10)                                        */
43938  #define R_CEC_CADR_ADR10_Msk            (0x400UL)  /*!< ADR10 (Bitfield-Mask: 0x01)                           */
43939  #define R_CEC_CADR_ADR11_Pos            (11UL)     /*!< ADR11 (Bit 11)                                        */
43940  #define R_CEC_CADR_ADR11_Msk            (0x800UL)  /*!< ADR11 (Bitfield-Mask: 0x01)                           */
43941  #define R_CEC_CADR_ADR12_Pos            (12UL)     /*!< ADR12 (Bit 12)                                        */
43942  #define R_CEC_CADR_ADR12_Msk            (0x1000UL) /*!< ADR12 (Bitfield-Mask: 0x01)                           */
43943  #define R_CEC_CADR_ADR13_Pos            (13UL)     /*!< ADR13 (Bit 13)                                        */
43944  #define R_CEC_CADR_ADR13_Msk            (0x2000UL) /*!< ADR13 (Bitfield-Mask: 0x01)                           */
43945  #define R_CEC_CADR_ADR14_Pos            (14UL)     /*!< ADR14 (Bit 14)                                        */
43946  #define R_CEC_CADR_ADR14_Msk            (0x4000UL) /*!< ADR14 (Bitfield-Mask: 0x01)                           */
43947 /* ========================================================  CECCTL1  ======================================================== */
43948  #define R_CEC_CECCTL1_SFT_Pos           (0UL)      /*!< SFT (Bit 0)                                           */
43949  #define R_CEC_CECCTL1_SFT_Msk           (0x3UL)    /*!< SFT (Bitfield-Mask: 0x03)                             */
43950  #define R_CEC_CECCTL1_CESEL_Pos         (2UL)      /*!< CESEL (Bit 2)                                         */
43951  #define R_CEC_CECCTL1_CESEL_Msk         (0xcUL)    /*!< CESEL (Bitfield-Mask: 0x03)                           */
43952  #define R_CEC_CECCTL1_STERRD_Pos        (4UL)      /*!< STERRD (Bit 4)                                        */
43953  #define R_CEC_CECCTL1_STERRD_Msk        (0x10UL)   /*!< STERRD (Bitfield-Mask: 0x01)                          */
43954  #define R_CEC_CECCTL1_BLERRD_Pos        (5UL)      /*!< BLERRD (Bit 5)                                        */
43955  #define R_CEC_CECCTL1_BLERRD_Msk        (0x20UL)   /*!< BLERRD (Bitfield-Mask: 0x01)                          */
43956  #define R_CEC_CECCTL1_CINTMK_Pos        (6UL)      /*!< CINTMK (Bit 6)                                        */
43957  #define R_CEC_CECCTL1_CINTMK_Msk        (0x40UL)   /*!< CINTMK (Bitfield-Mask: 0x01)                          */
43958  #define R_CEC_CECCTL1_CDFC_Pos          (7UL)      /*!< CDFC (Bit 7)                                          */
43959  #define R_CEC_CECCTL1_CDFC_Msk          (0x80UL)   /*!< CDFC (Bitfield-Mask: 0x01)                            */
43960 /* =========================================================  STATB  ========================================================= */
43961  #define R_CEC_STATB_STATB_Pos           (0UL)      /*!< STATB (Bit 0)                                         */
43962  #define R_CEC_STATB_STATB_Msk           (0x1ffUL)  /*!< STATB (Bitfield-Mask: 0x1ff)                          */
43963 /* =========================================================  STATL  ========================================================= */
43964  #define R_CEC_STATL_STATL_Pos           (0UL)      /*!< STATL (Bit 0)                                         */
43965  #define R_CEC_STATL_STATL_Msk           (0x1ffUL)  /*!< STATL (Bitfield-Mask: 0x1ff)                          */
43966 /* =========================================================  LGC0L  ========================================================= */
43967  #define R_CEC_LGC0L_LGC0L_Pos           (0UL)      /*!< LGC0L (Bit 0)                                         */
43968  #define R_CEC_LGC0L_LGC0L_Msk           (0x1ffUL)  /*!< LGC0L (Bitfield-Mask: 0x1ff)                          */
43969 /* =========================================================  LGC1L  ========================================================= */
43970  #define R_CEC_LGC1L_LGC1L_Pos           (0UL)      /*!< LGC1L (Bit 0)                                         */
43971  #define R_CEC_LGC1L_LGC1L_Msk           (0x1ffUL)  /*!< LGC1L (Bitfield-Mask: 0x1ff)                          */
43972 /* =========================================================  DATB  ========================================================== */
43973  #define R_CEC_DATB_DATB_Pos             (0UL)      /*!< DATB (Bit 0)                                          */
43974  #define R_CEC_DATB_DATB_Msk             (0x1ffUL)  /*!< DATB (Bitfield-Mask: 0x1ff)                           */
43975 /* =========================================================  NOMT  ========================================================== */
43976  #define R_CEC_NOMT_NOMT_Pos             (0UL)      /*!< NOMT (Bit 0)                                          */
43977  #define R_CEC_NOMT_NOMT_Msk             (0x1ffUL)  /*!< NOMT (Bitfield-Mask: 0x1ff)                           */
43978 /* ========================================================  STATLL  ========================================================= */
43979  #define R_CEC_STATLL_STATLL_Pos         (0UL)      /*!< STATLL (Bit 0)                                        */
43980  #define R_CEC_STATLL_STATLL_Msk         (0x1ffUL)  /*!< STATLL (Bitfield-Mask: 0x1ff)                         */
43981 /* ========================================================  STATLH  ========================================================= */
43982  #define R_CEC_STATLH_STATLH_Pos         (0UL)      /*!< STATLH (Bit 0)                                        */
43983  #define R_CEC_STATLH_STATLH_Msk         (0x1ffUL)  /*!< STATLH (Bitfield-Mask: 0x1ff)                         */
43984 /* ========================================================  STATBL  ========================================================= */
43985  #define R_CEC_STATBL_STATBL_Pos         (0UL)      /*!< STATBL (Bit 0)                                        */
43986  #define R_CEC_STATBL_STATBL_Msk         (0x1ffUL)  /*!< STATBL (Bitfield-Mask: 0x1ff)                         */
43987 /* ========================================================  STATBH  ========================================================= */
43988  #define R_CEC_STATBH_STATBH_Pos         (0UL)      /*!< STATBH (Bit 0)                                        */
43989  #define R_CEC_STATBH_STATBH_Msk         (0x1ffUL)  /*!< STATBH (Bitfield-Mask: 0x1ff)                         */
43990 /* ========================================================  LGC0LL  ========================================================= */
43991  #define R_CEC_LGC0LL_LGC0LL_Pos         (0UL)      /*!< LGC0LL (Bit 0)                                        */
43992  #define R_CEC_LGC0LL_LGC0LL_Msk         (0x1ffUL)  /*!< LGC0LL (Bitfield-Mask: 0x1ff)                         */
43993 /* ========================================================  LGC0LH  ========================================================= */
43994  #define R_CEC_LGC0LH_LGC0LH_Pos         (0UL)      /*!< LGC0LH (Bit 0)                                        */
43995  #define R_CEC_LGC0LH_LGC0LH_Msk         (0x1ffUL)  /*!< LGC0LH (Bitfield-Mask: 0x1ff)                         */
43996 /* ========================================================  LGC1LL  ========================================================= */
43997  #define R_CEC_LGC1LL_LGC1LL_Pos         (0UL)      /*!< LGC1LL (Bit 0)                                        */
43998  #define R_CEC_LGC1LL_LGC1LL_Msk         (0x1ffUL)  /*!< LGC1LL (Bitfield-Mask: 0x1ff)                         */
43999 /* ========================================================  LGC1LH  ========================================================= */
44000  #define R_CEC_LGC1LH_LGC1LH_Pos         (0UL)      /*!< LGC1LH (Bit 0)                                        */
44001  #define R_CEC_LGC1LH_LGC1LH_Msk         (0x1ffUL)  /*!< LGC1LH (Bitfield-Mask: 0x1ff)                         */
44002 /* =========================================================  DATBL  ========================================================= */
44003  #define R_CEC_DATBL_DATBL_Pos           (0UL)      /*!< DATBL (Bit 0)                                         */
44004  #define R_CEC_DATBL_DATBL_Msk           (0x1ffUL)  /*!< DATBL (Bitfield-Mask: 0x1ff)                          */
44005 /* =========================================================  DATBH  ========================================================= */
44006  #define R_CEC_DATBH_DATBH_Pos           (0UL)      /*!< DATBH (Bit 0)                                         */
44007  #define R_CEC_DATBH_DATBH_Msk           (0x1ffUL)  /*!< DATBH (Bitfield-Mask: 0x1ff)                          */
44008 /* =========================================================  NOMP  ========================================================== */
44009  #define R_CEC_NOMP_NOMP_Pos             (0UL)      /*!< NOMP (Bit 0)                                          */
44010  #define R_CEC_NOMP_NOMP_Msk             (0x1ffUL)  /*!< NOMP (Bitfield-Mask: 0x1ff)                           */
44011 /* ========================================================  CECEXMD  ======================================================== */
44012  #define R_CEC_CECEXMD_LERPLEN_Pos       (4UL)      /*!< LERPLEN (Bit 4)                                       */
44013  #define R_CEC_CECEXMD_LERPLEN_Msk       (0x10UL)   /*!< LERPLEN (Bitfield-Mask: 0x01)                         */
44014  #define R_CEC_CECEXMD_RERCVEN_Pos       (5UL)      /*!< RERCVEN (Bit 5)                                       */
44015  #define R_CEC_CECEXMD_RERCVEN_Msk       (0x20UL)   /*!< RERCVEN (Bitfield-Mask: 0x01)                         */
44016  #define R_CEC_CECEXMD_RCVINTDSEL_Pos    (7UL)      /*!< RCVINTDSEL (Bit 7)                                    */
44017  #define R_CEC_CECEXMD_RCVINTDSEL_Msk    (0x80UL)   /*!< RCVINTDSEL (Bitfield-Mask: 0x01)                      */
44018 /* =======================================================  CECEXMON  ======================================================== */
44019  #define R_CEC_CECEXMON_CECLNMON_Pos     (0UL)      /*!< CECLNMON (Bit 0)                                      */
44020  #define R_CEC_CECEXMON_CECLNMON_Msk     (0x1UL)    /*!< CECLNMON (Bitfield-Mask: 0x01)                        */
44021  #define R_CEC_CECEXMON_ACKF_Pos         (1UL)      /*!< ACKF (Bit 1)                                          */
44022  #define R_CEC_CECEXMON_ACKF_Msk         (0x2UL)    /*!< ACKF (Bitfield-Mask: 0x01)                            */
44023 /* =========================================================  CTXD  ========================================================== */
44024 /* =========================================================  CRXD  ========================================================== */
44025 /* =========================================================  CECES  ========================================================= */
44026  #define R_CEC_CECES_OERR_Pos            (0UL)      /*!< OERR (Bit 0)                                          */
44027  #define R_CEC_CECES_OERR_Msk            (0x1UL)    /*!< OERR (Bitfield-Mask: 0x01)                            */
44028  #define R_CEC_CECES_UERR_Pos            (1UL)      /*!< UERR (Bit 1)                                          */
44029  #define R_CEC_CECES_UERR_Msk            (0x2UL)    /*!< UERR (Bitfield-Mask: 0x01)                            */
44030  #define R_CEC_CECES_ACKERR_Pos          (2UL)      /*!< ACKERR (Bit 2)                                        */
44031  #define R_CEC_CECES_ACKERR_Msk          (0x4UL)    /*!< ACKERR (Bitfield-Mask: 0x01)                          */
44032  #define R_CEC_CECES_TERR_Pos            (3UL)      /*!< TERR (Bit 3)                                          */
44033  #define R_CEC_CECES_TERR_Msk            (0x8UL)    /*!< TERR (Bitfield-Mask: 0x01)                            */
44034  #define R_CEC_CECES_TXERR_Pos           (4UL)      /*!< TXERR (Bit 4)                                         */
44035  #define R_CEC_CECES_TXERR_Msk           (0x10UL)   /*!< TXERR (Bitfield-Mask: 0x01)                           */
44036  #define R_CEC_CECES_AERR_Pos            (5UL)      /*!< AERR (Bit 5)                                          */
44037  #define R_CEC_CECES_AERR_Msk            (0x20UL)   /*!< AERR (Bitfield-Mask: 0x01)                            */
44038  #define R_CEC_CECES_BLERR_Pos           (6UL)      /*!< BLERR (Bit 6)                                         */
44039  #define R_CEC_CECES_BLERR_Msk           (0x40UL)   /*!< BLERR (Bitfield-Mask: 0x01)                           */
44040 /* =========================================================  CECS  ========================================================== */
44041  #define R_CEC_CECS_ADRF_Pos             (0UL)      /*!< ADRF (Bit 0)                                          */
44042  #define R_CEC_CECS_ADRF_Msk             (0x1UL)    /*!< ADRF (Bitfield-Mask: 0x01)                            */
44043  #define R_CEC_CECS_BUSST_Pos            (1UL)      /*!< BUSST (Bit 1)                                         */
44044  #define R_CEC_CECS_BUSST_Msk            (0x2UL)    /*!< BUSST (Bitfield-Mask: 0x01)                           */
44045  #define R_CEC_CECS_TXST_Pos             (2UL)      /*!< TXST (Bit 2)                                          */
44046  #define R_CEC_CECS_TXST_Msk             (0x4UL)    /*!< TXST (Bitfield-Mask: 0x01)                            */
44047  #define R_CEC_CECS_EOMF_Pos             (3UL)      /*!< EOMF (Bit 3)                                          */
44048  #define R_CEC_CECS_EOMF_Msk             (0x8UL)    /*!< EOMF (Bitfield-Mask: 0x01)                            */
44049  #define R_CEC_CECS_ITCEF_Pos            (4UL)      /*!< ITCEF (Bit 4)                                         */
44050  #define R_CEC_CECS_ITCEF_Msk            (0x10UL)   /*!< ITCEF (Bitfield-Mask: 0x01)                           */
44051  #define R_CEC_CECS_SFTST_Pos            (7UL)      /*!< SFTST (Bit 7)                                         */
44052  #define R_CEC_CECS_SFTST_Msk            (0x80UL)   /*!< SFTST (Bitfield-Mask: 0x01)                           */
44053 /* =========================================================  CECFC  ========================================================= */
44054  #define R_CEC_CECFC_OCTRG_Pos           (0UL)      /*!< OCTRG (Bit 0)                                         */
44055  #define R_CEC_CECFC_OCTRG_Msk           (0x1UL)    /*!< OCTRG (Bitfield-Mask: 0x01)                           */
44056  #define R_CEC_CECFC_UCTRG_Pos           (1UL)      /*!< UCTRG (Bit 1)                                         */
44057  #define R_CEC_CECFC_UCTRG_Msk           (0x2UL)    /*!< UCTRG (Bitfield-Mask: 0x01)                           */
44058  #define R_CEC_CECFC_ACKCTRG_Pos         (2UL)      /*!< ACKCTRG (Bit 2)                                       */
44059  #define R_CEC_CECFC_ACKCTRG_Msk         (0x4UL)    /*!< ACKCTRG (Bitfield-Mask: 0x01)                         */
44060  #define R_CEC_CECFC_TCTRG_Pos           (3UL)      /*!< TCTRG (Bit 3)                                         */
44061  #define R_CEC_CECFC_TCTRG_Msk           (0x8UL)    /*!< TCTRG (Bitfield-Mask: 0x01)                           */
44062  #define R_CEC_CECFC_TXCTRG_Pos          (4UL)      /*!< TXCTRG (Bit 4)                                        */
44063  #define R_CEC_CECFC_TXCTRG_Msk          (0x10UL)   /*!< TXCTRG (Bitfield-Mask: 0x01)                          */
44064  #define R_CEC_CECFC_ACTRG_Pos           (5UL)      /*!< ACTRG (Bit 5)                                         */
44065  #define R_CEC_CECFC_ACTRG_Msk           (0x20UL)   /*!< ACTRG (Bitfield-Mask: 0x01)                           */
44066  #define R_CEC_CECFC_BLCTRG_Pos          (6UL)      /*!< BLCTRG (Bit 6)                                        */
44067  #define R_CEC_CECFC_BLCTRG_Msk          (0x40UL)   /*!< BLCTRG (Bitfield-Mask: 0x01)                          */
44068 /* ========================================================  CECCTL0  ======================================================== */
44069  #define R_CEC_CECCTL0_EOM_Pos           (0UL)      /*!< EOM (Bit 0)                                           */
44070  #define R_CEC_CECCTL0_EOM_Msk           (0x1UL)    /*!< EOM (Bitfield-Mask: 0x01)                             */
44071  #define R_CEC_CECCTL0_CECRXEN_Pos       (1UL)      /*!< CECRXEN (Bit 1)                                       */
44072  #define R_CEC_CECCTL0_CECRXEN_Msk       (0x2UL)    /*!< CECRXEN (Bitfield-Mask: 0x01)                         */
44073  #define R_CEC_CECCTL0_TXTRG_Pos         (2UL)      /*!< TXTRG (Bit 2)                                         */
44074  #define R_CEC_CECCTL0_TXTRG_Msk         (0x4UL)    /*!< TXTRG (Bitfield-Mask: 0x01)                           */
44075  #define R_CEC_CECCTL0_CCL_Pos           (3UL)      /*!< CCL (Bit 3)                                           */
44076  #define R_CEC_CECCTL0_CCL_Msk           (0x38UL)   /*!< CCL (Bitfield-Mask: 0x07)                             */
44077  #define R_CEC_CECCTL0_ACKTEN_Pos        (6UL)      /*!< ACKTEN (Bit 6)                                        */
44078  #define R_CEC_CECCTL0_ACKTEN_Msk        (0x40UL)   /*!< ACKTEN (Bitfield-Mask: 0x01)                          */
44079  #define R_CEC_CECCTL0_CECE_Pos          (7UL)      /*!< CECE (Bit 7)                                          */
44080  #define R_CEC_CECCTL0_CECE_Msk          (0x80UL)   /*!< CECE (Bitfield-Mask: 0x01)                            */
44081 
44082 /* =========================================================================================================================== */
44083 /* ================                                          R_OSPI                                           ================ */
44084 /* =========================================================================================================================== */
44085 
44086 /* ==========================================================  DCR  ========================================================== */
44087  #define R_OSPI_DCR_DVCMD0_Pos         (0UL)          /*!< DVCMD0 (Bit 0)                                        */
44088  #define R_OSPI_DCR_DVCMD0_Msk         (0xffUL)       /*!< DVCMD0 (Bitfield-Mask: 0xff)                          */
44089  #define R_OSPI_DCR_DVCMD1_Pos         (8UL)          /*!< DVCMD1 (Bit 8)                                        */
44090  #define R_OSPI_DCR_DVCMD1_Msk         (0xff00UL)     /*!< DVCMD1 (Bitfield-Mask: 0xff)                          */
44091 /* ==========================================================  DAR  ========================================================== */
44092  #define R_OSPI_DAR_DVAD0_Pos          (0UL)          /*!< DVAD0 (Bit 0)                                         */
44093  #define R_OSPI_DAR_DVAD0_Msk          (0xffUL)       /*!< DVAD0 (Bitfield-Mask: 0xff)                           */
44094  #define R_OSPI_DAR_DVAD1_Pos          (8UL)          /*!< DVAD1 (Bit 8)                                         */
44095  #define R_OSPI_DAR_DVAD1_Msk          (0xff00UL)     /*!< DVAD1 (Bitfield-Mask: 0xff)                           */
44096  #define R_OSPI_DAR_DVAD2_Pos          (16UL)         /*!< DVAD2 (Bit 16)                                        */
44097  #define R_OSPI_DAR_DVAD2_Msk          (0xff0000UL)   /*!< DVAD2 (Bitfield-Mask: 0xff)                           */
44098  #define R_OSPI_DAR_DVAD3_Pos          (24UL)         /*!< DVAD3 (Bit 24)                                        */
44099  #define R_OSPI_DAR_DVAD3_Msk          (0xff000000UL) /*!< DVAD3 (Bitfield-Mask: 0xff)                           */
44100 /* =========================================================  DCSR  ========================================================== */
44101  #define R_OSPI_DCSR_DALEN_Pos         (0UL)          /*!< DALEN (Bit 0)                                         */
44102  #define R_OSPI_DCSR_DALEN_Msk         (0xffUL)       /*!< DALEN (Bitfield-Mask: 0xff)                           */
44103  #define R_OSPI_DCSR_DMLEN_Pos         (8UL)          /*!< DMLEN (Bit 8)                                         */
44104  #define R_OSPI_DCSR_DMLEN_Msk         (0xff00UL)     /*!< DMLEN (Bitfield-Mask: 0xff)                           */
44105  #define R_OSPI_DCSR_ACDV_Pos          (19UL)         /*!< ACDV (Bit 19)                                         */
44106  #define R_OSPI_DCSR_ACDV_Msk          (0x80000UL)    /*!< ACDV (Bitfield-Mask: 0x01)                            */
44107  #define R_OSPI_DCSR_CMDLEN_Pos        (20UL)         /*!< CMDLEN (Bit 20)                                       */
44108  #define R_OSPI_DCSR_CMDLEN_Msk        (0x700000UL)   /*!< CMDLEN (Bitfield-Mask: 0x07)                          */
44109  #define R_OSPI_DCSR_DAOR_Pos          (23UL)         /*!< DAOR (Bit 23)                                         */
44110  #define R_OSPI_DCSR_DAOR_Msk          (0x800000UL)   /*!< DAOR (Bitfield-Mask: 0x01)                            */
44111  #define R_OSPI_DCSR_ADLEN_Pos         (24UL)         /*!< ADLEN (Bit 24)                                        */
44112  #define R_OSPI_DCSR_ADLEN_Msk         (0x7000000UL)  /*!< ADLEN (Bitfield-Mask: 0x07)                           */
44113  #define R_OSPI_DCSR_DOPI_Pos          (27UL)         /*!< DOPI (Bit 27)                                         */
44114  #define R_OSPI_DCSR_DOPI_Msk          (0x8000000UL)  /*!< DOPI (Bitfield-Mask: 0x01)                            */
44115  #define R_OSPI_DCSR_ACDA_Pos          (28UL)         /*!< ACDA (Bit 28)                                         */
44116  #define R_OSPI_DCSR_ACDA_Msk          (0x10000000UL) /*!< ACDA (Bitfield-Mask: 0x01)                            */
44117  #define R_OSPI_DCSR_PREN_Pos          (29UL)         /*!< PREN (Bit 29)                                         */
44118  #define R_OSPI_DCSR_PREN_Msk          (0x20000000UL) /*!< PREN (Bitfield-Mask: 0x01)                            */
44119 /* ==========================================================  DSR  ========================================================== */
44120  #define R_OSPI_DSR_DVSZ_Pos           (0UL)          /*!< DVSZ (Bit 0)                                          */
44121  #define R_OSPI_DSR_DVSZ_Msk           (0x3fffffffUL) /*!< DVSZ (Bitfield-Mask: 0x3fffffff)                      */
44122  #define R_OSPI_DSR_DVTYP_Pos          (30UL)         /*!< DVTYP (Bit 30)                                        */
44123  #define R_OSPI_DSR_DVTYP_Msk          (0xc0000000UL) /*!< DVTYP (Bitfield-Mask: 0x03)                           */
44124 /* =========================================================  MDTR  ========================================================== */
44125  #define R_OSPI_MDTR_DV0DEL_Pos        (0UL)          /*!< DV0DEL (Bit 0)                                        */
44126  #define R_OSPI_MDTR_DV0DEL_Msk        (0xffUL)       /*!< DV0DEL (Bitfield-Mask: 0xff)                          */
44127  #define R_OSPI_MDTR_DQSERAM_Pos       (8UL)          /*!< DQSERAM (Bit 8)                                       */
44128  #define R_OSPI_MDTR_DQSERAM_Msk       (0xf00UL)      /*!< DQSERAM (Bitfield-Mask: 0x0f)                         */
44129  #define R_OSPI_MDTR_DQSESOPI_Pos      (12UL)         /*!< DQSESOPI (Bit 12)                                     */
44130  #define R_OSPI_MDTR_DQSESOPI_Msk      (0xf000UL)     /*!< DQSESOPI (Bitfield-Mask: 0x0f)                        */
44131  #define R_OSPI_MDTR_DV1DEL_Pos        (16UL)         /*!< DV1DEL (Bit 16)                                       */
44132  #define R_OSPI_MDTR_DV1DEL_Msk        (0xff0000UL)   /*!< DV1DEL (Bitfield-Mask: 0xff)                          */
44133  #define R_OSPI_MDTR_DQSEDOPI_Pos      (24UL)         /*!< DQSEDOPI (Bit 24)                                     */
44134  #define R_OSPI_MDTR_DQSEDOPI_Msk      (0xf000000UL)  /*!< DQSEDOPI (Bitfield-Mask: 0x0f)                        */
44135 /* =========================================================  ACTR  ========================================================== */
44136  #define R_OSPI_ACTR_CTP_Pos           (0UL)          /*!< CTP (Bit 0)                                           */
44137  #define R_OSPI_ACTR_CTP_Msk           (0xffffffffUL) /*!< CTP (Bitfield-Mask: 0xffffffff)                       */
44138 /* =========================================================  ACAR  ========================================================== */
44139  #define R_OSPI_ACAR_CAD_Pos           (0UL)          /*!< CAD (Bit 0)                                           */
44140  #define R_OSPI_ACAR_CAD_Msk           (0xffffffffUL) /*!< CAD (Bitfield-Mask: 0xffffffff)                       */
44141 /* ========================================================  DRCSTR  ========================================================= */
44142  #define R_OSPI_DRCSTR_CTRW0_Pos       (0UL)          /*!< CTRW0 (Bit 0)                                         */
44143  #define R_OSPI_DRCSTR_CTRW0_Msk       (0x7fUL)       /*!< CTRW0 (Bitfield-Mask: 0x7f)                           */
44144  #define R_OSPI_DRCSTR_CTR0_Pos        (7UL)          /*!< CTR0 (Bit 7)                                          */
44145  #define R_OSPI_DRCSTR_CTR0_Msk        (0x80UL)       /*!< CTR0 (Bitfield-Mask: 0x01)                            */
44146  #define R_OSPI_DRCSTR_DVRDCMD0_Pos    (8UL)          /*!< DVRDCMD0 (Bit 8)                                      */
44147  #define R_OSPI_DRCSTR_DVRDCMD0_Msk    (0x700UL)      /*!< DVRDCMD0 (Bitfield-Mask: 0x07)                        */
44148  #define R_OSPI_DRCSTR_DVRDHI0_Pos     (11UL)         /*!< DVRDHI0 (Bit 11)                                      */
44149  #define R_OSPI_DRCSTR_DVRDHI0_Msk     (0x3800UL)     /*!< DVRDHI0 (Bitfield-Mask: 0x07)                         */
44150  #define R_OSPI_DRCSTR_DVRDLO0_Pos     (14UL)         /*!< DVRDLO0 (Bit 14)                                      */
44151  #define R_OSPI_DRCSTR_DVRDLO0_Msk     (0xc000UL)     /*!< DVRDLO0 (Bitfield-Mask: 0x03)                         */
44152  #define R_OSPI_DRCSTR_CTRW1_Pos       (16UL)         /*!< CTRW1 (Bit 16)                                        */
44153  #define R_OSPI_DRCSTR_CTRW1_Msk       (0x7f0000UL)   /*!< CTRW1 (Bitfield-Mask: 0x7f)                           */
44154  #define R_OSPI_DRCSTR_CTR1_Pos        (23UL)         /*!< CTR1 (Bit 23)                                         */
44155  #define R_OSPI_DRCSTR_CTR1_Msk        (0x800000UL)   /*!< CTR1 (Bitfield-Mask: 0x01)                            */
44156  #define R_OSPI_DRCSTR_DVRDCMD1_Pos    (24UL)         /*!< DVRDCMD1 (Bit 24)                                     */
44157  #define R_OSPI_DRCSTR_DVRDCMD1_Msk    (0x7000000UL)  /*!< DVRDCMD1 (Bitfield-Mask: 0x07)                        */
44158  #define R_OSPI_DRCSTR_DVRDHI1_Pos     (27UL)         /*!< DVRDHI1 (Bit 27)                                      */
44159  #define R_OSPI_DRCSTR_DVRDHI1_Msk     (0x38000000UL) /*!< DVRDHI1 (Bitfield-Mask: 0x07)                         */
44160  #define R_OSPI_DRCSTR_DVRDLO1_Pos     (30UL)         /*!< DVRDLO1 (Bit 30)                                      */
44161  #define R_OSPI_DRCSTR_DVRDLO1_Msk     (0xc0000000UL) /*!< DVRDLO1 (Bitfield-Mask: 0x03)                         */
44162 /* ========================================================  DWCSTR  ========================================================= */
44163  #define R_OSPI_DWCSTR_CTWW0_Pos       (0UL)          /*!< CTWW0 (Bit 0)                                         */
44164  #define R_OSPI_DWCSTR_CTWW0_Msk       (0x7fUL)       /*!< CTWW0 (Bitfield-Mask: 0x7f)                           */
44165  #define R_OSPI_DWCSTR_CTW0_Pos        (7UL)          /*!< CTW0 (Bit 7)                                          */
44166  #define R_OSPI_DWCSTR_CTW0_Msk        (0x80UL)       /*!< CTW0 (Bitfield-Mask: 0x01)                            */
44167  #define R_OSPI_DWCSTR_DVWCMD0_Pos     (8UL)          /*!< DVWCMD0 (Bit 8)                                       */
44168  #define R_OSPI_DWCSTR_DVWCMD0_Msk     (0x700UL)      /*!< DVWCMD0 (Bitfield-Mask: 0x07)                         */
44169  #define R_OSPI_DWCSTR_DVWHI0_Pos      (11UL)         /*!< DVWHI0 (Bit 11)                                       */
44170  #define R_OSPI_DWCSTR_DVWHI0_Msk      (0x3800UL)     /*!< DVWHI0 (Bitfield-Mask: 0x07)                          */
44171  #define R_OSPI_DWCSTR_DVWLO0_Pos      (14UL)         /*!< DVWLO0 (Bit 14)                                       */
44172  #define R_OSPI_DWCSTR_DVWLO0_Msk      (0xc000UL)     /*!< DVWLO0 (Bitfield-Mask: 0x03)                          */
44173  #define R_OSPI_DWCSTR_CTWW1_Pos       (16UL)         /*!< CTWW1 (Bit 16)                                        */
44174  #define R_OSPI_DWCSTR_CTWW1_Msk       (0x7f0000UL)   /*!< CTWW1 (Bitfield-Mask: 0x7f)                           */
44175  #define R_OSPI_DWCSTR_CTW1_Pos        (23UL)         /*!< CTW1 (Bit 23)                                         */
44176  #define R_OSPI_DWCSTR_CTW1_Msk        (0x800000UL)   /*!< CTW1 (Bitfield-Mask: 0x01)                            */
44177  #define R_OSPI_DWCSTR_DVWCMD1_Pos     (24UL)         /*!< DVWCMD1 (Bit 24)                                      */
44178  #define R_OSPI_DWCSTR_DVWCMD1_Msk     (0x7000000UL)  /*!< DVWCMD1 (Bitfield-Mask: 0x07)                         */
44179  #define R_OSPI_DWCSTR_DVWHI1_Pos      (27UL)         /*!< DVWHI1 (Bit 27)                                       */
44180  #define R_OSPI_DWCSTR_DVWHI1_Msk      (0x38000000UL) /*!< DVWHI1 (Bitfield-Mask: 0x07)                          */
44181  #define R_OSPI_DWCSTR_DVWLO1_Pos      (30UL)         /*!< DVWLO1 (Bit 30)                                       */
44182  #define R_OSPI_DWCSTR_DVWLO1_Msk      (0xc0000000UL) /*!< DVWLO1 (Bitfield-Mask: 0x03)                          */
44183 /* =========================================================  DCSTR  ========================================================= */
44184  #define R_OSPI_DCSTR_DVSELCMD_Pos     (8UL)          /*!< DVSELCMD (Bit 8)                                      */
44185  #define R_OSPI_DCSTR_DVSELCMD_Msk     (0x700UL)      /*!< DVSELCMD (Bitfield-Mask: 0x07)                        */
44186  #define R_OSPI_DCSTR_DVSELHI_Pos      (11UL)         /*!< DVSELHI (Bit 11)                                      */
44187  #define R_OSPI_DCSTR_DVSELHI_Msk      (0x3800UL)     /*!< DVSELHI (Bitfield-Mask: 0x07)                         */
44188  #define R_OSPI_DCSTR_DVSELLO_Pos      (14UL)         /*!< DVSELLO (Bit 14)                                      */
44189  #define R_OSPI_DCSTR_DVSELLO_Msk      (0xc000UL)     /*!< DVSELLO (Bitfield-Mask: 0x03)                         */
44190 /* =========================================================  CDSR  ========================================================== */
44191  #define R_OSPI_CDSR_DV0TTYP_Pos       (0UL)          /*!< DV0TTYP (Bit 0)                                       */
44192  #define R_OSPI_CDSR_DV0TTYP_Msk       (0x3UL)        /*!< DV0TTYP (Bitfield-Mask: 0x03)                         */
44193  #define R_OSPI_CDSR_DV1TTYP_Pos       (2UL)          /*!< DV1TTYP (Bit 2)                                       */
44194  #define R_OSPI_CDSR_DV1TTYP_Msk       (0xcUL)        /*!< DV1TTYP (Bitfield-Mask: 0x03)                         */
44195  #define R_OSPI_CDSR_DV0PC_Pos         (4UL)          /*!< DV0PC (Bit 4)                                         */
44196  #define R_OSPI_CDSR_DV0PC_Msk         (0x10UL)       /*!< DV0PC (Bitfield-Mask: 0x01)                           */
44197  #define R_OSPI_CDSR_DV1PC_Pos         (5UL)          /*!< DV1PC (Bit 5)                                         */
44198  #define R_OSPI_CDSR_DV1PC_Msk         (0x20UL)       /*!< DV1PC (Bitfield-Mask: 0x01)                           */
44199  #define R_OSPI_CDSR_ACMEME0_Pos       (10UL)         /*!< ACMEME0 (Bit 10)                                      */
44200  #define R_OSPI_CDSR_ACMEME0_Msk       (0x400UL)      /*!< ACMEME0 (Bitfield-Mask: 0x01)                         */
44201  #define R_OSPI_CDSR_ACMEME1_Pos       (11UL)         /*!< ACMEME1 (Bit 11)                                      */
44202  #define R_OSPI_CDSR_ACMEME1_Msk       (0x800UL)      /*!< ACMEME1 (Bitfield-Mask: 0x01)                         */
44203  #define R_OSPI_CDSR_ACMODE_Pos        (12UL)         /*!< ACMODE (Bit 12)                                       */
44204  #define R_OSPI_CDSR_ACMODE_Msk        (0x3000UL)     /*!< ACMODE (Bitfield-Mask: 0x03)                          */
44205  #define R_OSPI_CDSR_DLFT_Pos          (31UL)         /*!< DLFT (Bit 31)                                         */
44206  #define R_OSPI_CDSR_DLFT_Msk          (0x80000000UL) /*!< DLFT (Bitfield-Mask: 0x01)                            */
44207 /* =========================================================  MDLR  ========================================================== */
44208  #define R_OSPI_MDLR_DV0RDL_Pos        (0UL)          /*!< DV0RDL (Bit 0)                                        */
44209  #define R_OSPI_MDLR_DV0RDL_Msk        (0xffUL)       /*!< DV0RDL (Bitfield-Mask: 0xff)                          */
44210  #define R_OSPI_MDLR_DV0WDL_Pos        (8UL)          /*!< DV0WDL (Bit 8)                                        */
44211  #define R_OSPI_MDLR_DV0WDL_Msk        (0xff00UL)     /*!< DV0WDL (Bitfield-Mask: 0xff)                          */
44212  #define R_OSPI_MDLR_DV1RDL_Pos        (16UL)         /*!< DV1RDL (Bit 16)                                       */
44213  #define R_OSPI_MDLR_DV1RDL_Msk        (0xff0000UL)   /*!< DV1RDL (Bitfield-Mask: 0xff)                          */
44214  #define R_OSPI_MDLR_DV1WDL_Pos        (24UL)         /*!< DV1WDL (Bit 24)                                       */
44215  #define R_OSPI_MDLR_DV1WDL_Msk        (0xff000000UL) /*!< DV1WDL (Bitfield-Mask: 0xff)                          */
44216 /* =========================================================  MRWCR  ========================================================= */
44217  #define R_OSPI_MRWCR_DMRCMD0_Pos      (0UL)          /*!< DMRCMD0 (Bit 0)                                       */
44218  #define R_OSPI_MRWCR_DMRCMD0_Msk      (0xffUL)       /*!< DMRCMD0 (Bitfield-Mask: 0xff)                         */
44219  #define R_OSPI_MRWCR_DMRCMD1_Pos      (8UL)          /*!< DMRCMD1 (Bit 8)                                       */
44220  #define R_OSPI_MRWCR_DMRCMD1_Msk      (0xff00UL)     /*!< DMRCMD1 (Bitfield-Mask: 0xff)                         */
44221  #define R_OSPI_MRWCR_DMWCMD0_Pos      (16UL)         /*!< DMWCMD0 (Bit 16)                                      */
44222  #define R_OSPI_MRWCR_DMWCMD0_Msk      (0xff0000UL)   /*!< DMWCMD0 (Bitfield-Mask: 0xff)                         */
44223  #define R_OSPI_MRWCR_DMWCMD1_Pos      (24UL)         /*!< DMWCMD1 (Bit 24)                                      */
44224  #define R_OSPI_MRWCR_DMWCMD1_Msk      (0xff000000UL) /*!< DMWCMD1 (Bitfield-Mask: 0xff)                         */
44225 /* ========================================================  MRWCSR  ========================================================= */
44226  #define R_OSPI_MRWCSR_MRAL0_Pos       (0UL)          /*!< MRAL0 (Bit 0)                                         */
44227  #define R_OSPI_MRWCSR_MRAL0_Msk       (0x7UL)        /*!< MRAL0 (Bitfield-Mask: 0x07)                           */
44228  #define R_OSPI_MRWCSR_MRCL0_Pos       (3UL)          /*!< MRCL0 (Bit 3)                                         */
44229  #define R_OSPI_MRWCSR_MRCL0_Msk       (0x38UL)       /*!< MRCL0 (Bitfield-Mask: 0x07)                           */
44230  #define R_OSPI_MRWCSR_MRO0_Pos        (6UL)          /*!< MRO0 (Bit 6)                                          */
44231  #define R_OSPI_MRWCSR_MRO0_Msk        (0x40UL)       /*!< MRO0 (Bitfield-Mask: 0x01)                            */
44232  #define R_OSPI_MRWCSR_PREN0_Pos       (7UL)          /*!< PREN0 (Bit 7)                                         */
44233  #define R_OSPI_MRWCSR_PREN0_Msk       (0x80UL)       /*!< PREN0 (Bitfield-Mask: 0x01)                           */
44234  #define R_OSPI_MRWCSR_MWAL0_Pos       (8UL)          /*!< MWAL0 (Bit 8)                                         */
44235  #define R_OSPI_MRWCSR_MWAL0_Msk       (0x700UL)      /*!< MWAL0 (Bitfield-Mask: 0x07)                           */
44236  #define R_OSPI_MRWCSR_MWCL0_Pos       (11UL)         /*!< MWCL0 (Bit 11)                                        */
44237  #define R_OSPI_MRWCSR_MWCL0_Msk       (0x3800UL)     /*!< MWCL0 (Bitfield-Mask: 0x07)                           */
44238  #define R_OSPI_MRWCSR_MWO0_Pos        (14UL)         /*!< MWO0 (Bit 14)                                         */
44239  #define R_OSPI_MRWCSR_MWO0_Msk        (0x4000UL)     /*!< MWO0 (Bitfield-Mask: 0x01)                            */
44240  #define R_OSPI_MRWCSR_MRAL1_Pos       (16UL)         /*!< MRAL1 (Bit 16)                                        */
44241  #define R_OSPI_MRWCSR_MRAL1_Msk       (0x70000UL)    /*!< MRAL1 (Bitfield-Mask: 0x07)                           */
44242  #define R_OSPI_MRWCSR_MRCL1_Pos       (19UL)         /*!< MRCL1 (Bit 19)                                        */
44243  #define R_OSPI_MRWCSR_MRCL1_Msk       (0x380000UL)   /*!< MRCL1 (Bitfield-Mask: 0x07)                           */
44244  #define R_OSPI_MRWCSR_MRO1_Pos        (22UL)         /*!< MRO1 (Bit 22)                                         */
44245  #define R_OSPI_MRWCSR_MRO1_Msk        (0x400000UL)   /*!< MRO1 (Bitfield-Mask: 0x01)                            */
44246  #define R_OSPI_MRWCSR_PREN1_Pos       (23UL)         /*!< PREN1 (Bit 23)                                        */
44247  #define R_OSPI_MRWCSR_PREN1_Msk       (0x800000UL)   /*!< PREN1 (Bitfield-Mask: 0x01)                           */
44248  #define R_OSPI_MRWCSR_MWAL1_Pos       (24UL)         /*!< MWAL1 (Bit 24)                                        */
44249  #define R_OSPI_MRWCSR_MWAL1_Msk       (0x7000000UL)  /*!< MWAL1 (Bitfield-Mask: 0x07)                           */
44250  #define R_OSPI_MRWCSR_MWCL1_Pos       (27UL)         /*!< MWCL1 (Bit 27)                                        */
44251  #define R_OSPI_MRWCSR_MWCL1_Msk       (0x38000000UL) /*!< MWCL1 (Bitfield-Mask: 0x07)                           */
44252  #define R_OSPI_MRWCSR_MWO1_Pos        (30UL)         /*!< MWO1 (Bit 30)                                         */
44253  #define R_OSPI_MRWCSR_MWO1_Msk        (0x40000000UL) /*!< MWO1 (Bitfield-Mask: 0x01)                            */
44254 /* ==========================================================  ESR  ========================================================== */
44255  #define R_OSPI_ESR_MRESR_Pos          (0UL)          /*!< MRESR (Bit 0)                                         */
44256  #define R_OSPI_ESR_MRESR_Msk          (0xffUL)       /*!< MRESR (Bitfield-Mask: 0xff)                           */
44257  #define R_OSPI_ESR_MWESR_Pos          (8UL)          /*!< MWESR (Bit 8)                                         */
44258  #define R_OSPI_ESR_MWESR_Msk          (0xff00UL)     /*!< MWESR (Bitfield-Mask: 0xff)                           */
44259 /* =========================================================  CWNDR  ========================================================= */
44260  #define R_OSPI_CWNDR_WND_Pos          (0UL)          /*!< WND (Bit 0)                                           */
44261  #define R_OSPI_CWNDR_WND_Msk          (0xffffffffUL) /*!< WND (Bitfield-Mask: 0xffffffff)                       */
44262 /* =========================================================  CWDR  ========================================================== */
44263  #define R_OSPI_CWDR_WD0_Pos           (0UL)          /*!< WD0 (Bit 0)                                           */
44264  #define R_OSPI_CWDR_WD0_Msk           (0xffUL)       /*!< WD0 (Bitfield-Mask: 0xff)                             */
44265  #define R_OSPI_CWDR_WD1_Pos           (8UL)          /*!< WD1 (Bit 8)                                           */
44266  #define R_OSPI_CWDR_WD1_Msk           (0xff00UL)     /*!< WD1 (Bitfield-Mask: 0xff)                             */
44267  #define R_OSPI_CWDR_WD2_Pos           (16UL)         /*!< WD2 (Bit 16)                                          */
44268  #define R_OSPI_CWDR_WD2_Msk           (0xff0000UL)   /*!< WD2 (Bitfield-Mask: 0xff)                             */
44269  #define R_OSPI_CWDR_WD3_Pos           (24UL)         /*!< WD3 (Bit 24)                                          */
44270  #define R_OSPI_CWDR_WD3_Msk           (0xff000000UL) /*!< WD3 (Bitfield-Mask: 0xff)                             */
44271 /* ==========================================================  CRR  ========================================================== */
44272  #define R_OSPI_CRR_RD0_Pos            (0UL)          /*!< RD0 (Bit 0)                                           */
44273  #define R_OSPI_CRR_RD0_Msk            (0xffUL)       /*!< RD0 (Bitfield-Mask: 0xff)                             */
44274  #define R_OSPI_CRR_RD1_Pos            (8UL)          /*!< RD1 (Bit 8)                                           */
44275  #define R_OSPI_CRR_RD1_Msk            (0xff00UL)     /*!< RD1 (Bitfield-Mask: 0xff)                             */
44276  #define R_OSPI_CRR_RD2_Pos            (16UL)         /*!< RD2 (Bit 16)                                          */
44277  #define R_OSPI_CRR_RD2_Msk            (0xff0000UL)   /*!< RD2 (Bitfield-Mask: 0xff)                             */
44278  #define R_OSPI_CRR_RD3_Pos            (24UL)         /*!< RD3 (Bit 24)                                          */
44279  #define R_OSPI_CRR_RD3_Msk            (0xff000000UL) /*!< RD3 (Bitfield-Mask: 0xff)                             */
44280 /* =========================================================  ACSR  ========================================================== */
44281  #define R_OSPI_ACSR_ACSR0_Pos         (0UL)          /*!< ACSR0 (Bit 0)                                         */
44282  #define R_OSPI_ACSR_ACSR0_Msk         (0x7UL)        /*!< ACSR0 (Bitfield-Mask: 0x07)                           */
44283  #define R_OSPI_ACSR_ACSR1_Pos         (3UL)          /*!< ACSR1 (Bit 3)                                         */
44284  #define R_OSPI_ACSR_ACSR1_Msk         (0x38UL)       /*!< ACSR1 (Bitfield-Mask: 0x07)                           */
44285 /* ========================================================  DCSMXR  ========================================================= */
44286  #define R_OSPI_DCSMXR_CTWMX0_Pos      (0UL)          /*!< CTWMX0 (Bit 0)                                        */
44287  #define R_OSPI_DCSMXR_CTWMX0_Msk      (0x1ffUL)      /*!< CTWMX0 (Bitfield-Mask: 0x1ff)                         */
44288  #define R_OSPI_DCSMXR_CTWMX1_Pos      (16UL)         /*!< CTWMX1 (Bit 16)                                       */
44289  #define R_OSPI_DCSMXR_CTWMX1_Msk      (0x1ff0000UL)  /*!< CTWMX1 (Bitfield-Mask: 0x1ff)                         */
44290 /* ========================================================  DWSCTSR  ======================================================== */
44291  #define R_OSPI_DWSCTSR_CTSN0_Pos      (0UL)          /*!< CTSN0 (Bit 0)                                         */
44292  #define R_OSPI_DWSCTSR_CTSN0_Msk      (0x7ffUL)      /*!< CTSN0 (Bitfield-Mask: 0x7ff)                          */
44293  #define R_OSPI_DWSCTSR_CTSN1_Pos      (16UL)         /*!< CTSN1 (Bit 16)                                        */
44294  #define R_OSPI_DWSCTSR_CTSN1_Msk      (0x7ff0000UL)  /*!< CTSN1 (Bitfield-Mask: 0x7ff)                          */
44295 
44296 /* =========================================================================================================================== */
44297 /* ================                                         R_ADC_B0                                          ================ */
44298 /* =========================================================================================================================== */
44299 
44300 /* =======================================================  ADCLKENR  ======================================================== */
44301  #define R_ADC_B0_ADCLKENR_CLKEN_Pos           (0UL)          /*!< CLKEN (Bit 0)                                         */
44302  #define R_ADC_B0_ADCLKENR_CLKEN_Msk           (0x1UL)        /*!< CLKEN (Bitfield-Mask: 0x01)                           */
44303 /* ========================================================  ADCLKSR  ======================================================== */
44304  #define R_ADC_B0_ADCLKSR_CLKSR_Pos            (0UL)          /*!< CLKSR (Bit 0)                                         */
44305  #define R_ADC_B0_ADCLKSR_CLKSR_Msk            (0x1UL)        /*!< CLKSR (Bitfield-Mask: 0x01)                           */
44306 /* ========================================================  ADCLKCR  ======================================================== */
44307  #define R_ADC_B0_ADCLKCR_CLKSEL_Pos           (0UL)          /*!< CLKSEL (Bit 0)                                        */
44308  #define R_ADC_B0_ADCLKCR_CLKSEL_Msk           (0x3UL)        /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
44309  #define R_ADC_B0_ADCLKCR_DIVR_Pos             (16UL)         /*!< DIVR (Bit 16)                                         */
44310  #define R_ADC_B0_ADCLKCR_DIVR_Msk             (0x70000UL)    /*!< DIVR (Bitfield-Mask: 0x07)                            */
44311 /* ========================================================  ADSYCR  ========================================================= */
44312  #define R_ADC_B0_ADSYCR_ADSYCYC_Pos           (0UL)          /*!< ADSYCYC (Bit 0)                                       */
44313  #define R_ADC_B0_ADSYCR_ADSYCYC_Msk           (0x7ffUL)      /*!< ADSYCYC (Bitfield-Mask: 0x7ff)                        */
44314  #define R_ADC_B0_ADSYCR_ADSYDIS0_Pos          (16UL)         /*!< ADSYDIS0 (Bit 16)                                     */
44315  #define R_ADC_B0_ADSYCR_ADSYDIS0_Msk          (0x10000UL)    /*!< ADSYDIS0 (Bitfield-Mask: 0x01)                        */
44316  #define R_ADC_B0_ADSYCR_ADSYDIS1_Pos          (17UL)         /*!< ADSYDIS1 (Bit 17)                                     */
44317  #define R_ADC_B0_ADSYCR_ADSYDIS1_Msk          (0x20000UL)    /*!< ADSYDIS1 (Bitfield-Mask: 0x01)                        */
44318 /* =======================================================  ADERINTCR  ======================================================= */
44319  #define R_ADC_B0_ADERINTCR_ADEIE0_Pos         (0UL)          /*!< ADEIE0 (Bit 0)                                        */
44320  #define R_ADC_B0_ADERINTCR_ADEIE0_Msk         (0x1UL)        /*!< ADEIE0 (Bitfield-Mask: 0x01)                          */
44321  #define R_ADC_B0_ADERINTCR_ADEIE1_Pos         (1UL)          /*!< ADEIE1 (Bit 1)                                        */
44322  #define R_ADC_B0_ADERINTCR_ADEIE1_Msk         (0x2UL)        /*!< ADEIE1 (Bitfield-Mask: 0x01)                          */
44323 /* ======================================================  ADOVFINTCR  ======================================================= */
44324  #define R_ADC_B0_ADOVFINTCR_ADOVFIE0_Pos      (0UL)          /*!< ADOVFIE0 (Bit 0)                                      */
44325  #define R_ADC_B0_ADOVFINTCR_ADOVFIE0_Msk      (0x1UL)        /*!< ADOVFIE0 (Bitfield-Mask: 0x01)                        */
44326  #define R_ADC_B0_ADOVFINTCR_ADOVFIE1_Pos      (1UL)          /*!< ADOVFIE1 (Bit 1)                                      */
44327  #define R_ADC_B0_ADOVFINTCR_ADOVFIE1_Msk      (0x2UL)        /*!< ADOVFIE1 (Bitfield-Mask: 0x01)                        */
44328 /* ======================================================  ADCALINTCR  ======================================================= */
44329  #define R_ADC_B0_ADCALINTCR_CALENDIE0_Pos     (16UL)         /*!< CALENDIE0 (Bit 16)                                    */
44330  #define R_ADC_B0_ADCALINTCR_CALENDIE0_Msk     (0x10000UL)    /*!< CALENDIE0 (Bitfield-Mask: 0x01)                       */
44331  #define R_ADC_B0_ADCALINTCR_CALENDIE1_Pos     (17UL)         /*!< CALENDIE1 (Bit 17)                                    */
44332  #define R_ADC_B0_ADCALINTCR_CALENDIE1_Msk     (0x20000UL)    /*!< CALENDIE1 (Bitfield-Mask: 0x01)                       */
44333 /* =========================================================  ADMDR  ========================================================= */
44334  #define R_ADC_B0_ADMDR_ADMD0_Pos              (0UL)          /*!< ADMD0 (Bit 0)                                         */
44335  #define R_ADC_B0_ADMDR_ADMD0_Msk              (0xfUL)        /*!< ADMD0 (Bitfield-Mask: 0x0f)                           */
44336  #define R_ADC_B0_ADMDR_ADMD1_Pos              (8UL)          /*!< ADMD1 (Bit 8)                                         */
44337  #define R_ADC_B0_ADMDR_ADMD1_Msk              (0xf00UL)      /*!< ADMD1 (Bitfield-Mask: 0x0f)                           */
44338 /* ========================================================  ADGSPCR  ======================================================== */
44339  #define R_ADC_B0_ADGSPCR_PGS0_Pos             (0UL)          /*!< PGS0 (Bit 0)                                          */
44340  #define R_ADC_B0_ADGSPCR_PGS0_Msk             (0x1UL)        /*!< PGS0 (Bitfield-Mask: 0x01)                            */
44341  #define R_ADC_B0_ADGSPCR_RSCN0_Pos            (1UL)          /*!< RSCN0 (Bit 1)                                         */
44342  #define R_ADC_B0_ADGSPCR_RSCN0_Msk            (0x2UL)        /*!< RSCN0 (Bitfield-Mask: 0x01)                           */
44343  #define R_ADC_B0_ADGSPCR_LGRRS0_Pos           (2UL)          /*!< LGRRS0 (Bit 2)                                        */
44344  #define R_ADC_B0_ADGSPCR_LGRRS0_Msk           (0x4UL)        /*!< LGRRS0 (Bitfield-Mask: 0x01)                          */
44345  #define R_ADC_B0_ADGSPCR_GRP0_Pos             (3UL)          /*!< GRP0 (Bit 3)                                          */
44346  #define R_ADC_B0_ADGSPCR_GRP0_Msk             (0x8UL)        /*!< GRP0 (Bitfield-Mask: 0x01)                            */
44347  #define R_ADC_B0_ADGSPCR_PGS1_Pos             (8UL)          /*!< PGS1 (Bit 8)                                          */
44348  #define R_ADC_B0_ADGSPCR_PGS1_Msk             (0x100UL)      /*!< PGS1 (Bitfield-Mask: 0x01)                            */
44349  #define R_ADC_B0_ADGSPCR_RSCN1_Pos            (9UL)          /*!< RSCN1 (Bit 9)                                         */
44350  #define R_ADC_B0_ADGSPCR_RSCN1_Msk            (0x200UL)      /*!< RSCN1 (Bitfield-Mask: 0x01)                           */
44351  #define R_ADC_B0_ADGSPCR_LGRRS1_Pos           (10UL)         /*!< LGRRS1 (Bit 10)                                       */
44352  #define R_ADC_B0_ADGSPCR_LGRRS1_Msk           (0x400UL)      /*!< LGRRS1 (Bitfield-Mask: 0x01)                          */
44353  #define R_ADC_B0_ADGSPCR_GRP1_Pos             (11UL)         /*!< GRP1 (Bit 11)                                         */
44354  #define R_ADC_B0_ADGSPCR_GRP1_Msk             (0x800UL)      /*!< GRP1 (Bitfield-Mask: 0x01)                            */
44355 /* ========================================================  ADSGER  ========================================================= */
44356  #define R_ADC_B0_ADSGER_SGREn_Pos             (0UL)          /*!< SGREn (Bit 0)                                         */
44357  #define R_ADC_B0_ADSGER_SGREn_Msk             (0x1ffUL)      /*!< SGREn (Bitfield-Mask: 0x1ff)                          */
44358 /* ========================================================  ADSGCR0  ======================================================== */
44359  #define R_ADC_B0_ADSGCR0_SGADS0_Pos           (0UL)          /*!< SGADS0 (Bit 0)                                        */
44360  #define R_ADC_B0_ADSGCR0_SGADS0_Msk           (0x3UL)        /*!< SGADS0 (Bitfield-Mask: 0x03)                          */
44361  #define R_ADC_B0_ADSGCR0_SGADS1_Pos           (8UL)          /*!< SGADS1 (Bit 8)                                        */
44362  #define R_ADC_B0_ADSGCR0_SGADS1_Msk           (0x300UL)      /*!< SGADS1 (Bitfield-Mask: 0x03)                          */
44363  #define R_ADC_B0_ADSGCR0_SGADS2_Pos           (16UL)         /*!< SGADS2 (Bit 16)                                       */
44364  #define R_ADC_B0_ADSGCR0_SGADS2_Msk           (0x30000UL)    /*!< SGADS2 (Bitfield-Mask: 0x03)                          */
44365  #define R_ADC_B0_ADSGCR0_SGADS3_Pos           (24UL)         /*!< SGADS3 (Bit 24)                                       */
44366  #define R_ADC_B0_ADSGCR0_SGADS3_Msk           (0x3000000UL)  /*!< SGADS3 (Bitfield-Mask: 0x03)                          */
44367 /* ========================================================  ADSGCR1  ======================================================== */
44368  #define R_ADC_B0_ADSGCR1_SGADS4_Pos           (0UL)          /*!< SGADS4 (Bit 0)                                        */
44369  #define R_ADC_B0_ADSGCR1_SGADS4_Msk           (0x3UL)        /*!< SGADS4 (Bitfield-Mask: 0x03)                          */
44370  #define R_ADC_B0_ADSGCR1_SGADS5_Pos           (8UL)          /*!< SGADS5 (Bit 8)                                        */
44371  #define R_ADC_B0_ADSGCR1_SGADS5_Msk           (0x300UL)      /*!< SGADS5 (Bitfield-Mask: 0x03)                          */
44372  #define R_ADC_B0_ADSGCR1_SGADS6_Pos           (16UL)         /*!< SGADS6 (Bit 16)                                       */
44373  #define R_ADC_B0_ADSGCR1_SGADS6_Msk           (0x30000UL)    /*!< SGADS6 (Bitfield-Mask: 0x03)                          */
44374  #define R_ADC_B0_ADSGCR1_SGADS7_Pos           (24UL)         /*!< SGADS7 (Bit 24)                                       */
44375  #define R_ADC_B0_ADSGCR1_SGADS7_Msk           (0x3000000UL)  /*!< SGADS7 (Bitfield-Mask: 0x03)                          */
44376 /* ========================================================  ADSGCR2  ======================================================== */
44377  #define R_ADC_B0_ADSGCR2_SGADS8_Pos           (0UL)          /*!< SGADS8 (Bit 0)                                        */
44378  #define R_ADC_B0_ADSGCR2_SGADS8_Msk           (0x3UL)        /*!< SGADS8 (Bitfield-Mask: 0x03)                          */
44379 /* ========================================================  ADINTCR  ======================================================== */
44380  #define R_ADC_B0_ADINTCR_ADIEn_Pos            (0UL)          /*!< ADIEn (Bit 0)                                         */
44381  #define R_ADC_B0_ADINTCR_ADIEn_Msk            (0x3ffUL)      /*!< ADIEn (Bitfield-Mask: 0x3ff)                          */
44382 /* =======================================================  ADTRGEXT0  ======================================================= */
44383  #define R_ADC_B0_ADTRGEXT0_TRGEXT0_Pos        (0UL)          /*!< TRGEXT0 (Bit 0)                                       */
44384  #define R_ADC_B0_ADTRGEXT0_TRGEXT0_Msk        (0x1UL)        /*!< TRGEXT0 (Bitfield-Mask: 0x01)                         */
44385  #define R_ADC_B0_ADTRGEXT0_TRGEXT1_Pos        (1UL)          /*!< TRGEXT1 (Bit 1)                                       */
44386  #define R_ADC_B0_ADTRGEXT0_TRGEXT1_Msk        (0x2UL)        /*!< TRGEXT1 (Bitfield-Mask: 0x01)                         */
44387 /* =======================================================  ADTRGEXT1  ======================================================= */
44388  #define R_ADC_B0_ADTRGEXT1_TRGEXT0_Pos        (0UL)          /*!< TRGEXT0 (Bit 0)                                       */
44389  #define R_ADC_B0_ADTRGEXT1_TRGEXT0_Msk        (0x1UL)        /*!< TRGEXT0 (Bitfield-Mask: 0x01)                         */
44390  #define R_ADC_B0_ADTRGEXT1_TRGEXT1_Pos        (1UL)          /*!< TRGEXT1 (Bit 1)                                       */
44391  #define R_ADC_B0_ADTRGEXT1_TRGEXT1_Msk        (0x2UL)        /*!< TRGEXT1 (Bitfield-Mask: 0x01)                         */
44392 /* =======================================================  ADTRGEXT2  ======================================================= */
44393  #define R_ADC_B0_ADTRGEXT2_TRGEXT0_Pos        (0UL)          /*!< TRGEXT0 (Bit 0)                                       */
44394  #define R_ADC_B0_ADTRGEXT2_TRGEXT0_Msk        (0x1UL)        /*!< TRGEXT0 (Bitfield-Mask: 0x01)                         */
44395  #define R_ADC_B0_ADTRGEXT2_TRGEXT1_Pos        (1UL)          /*!< TRGEXT1 (Bit 1)                                       */
44396  #define R_ADC_B0_ADTRGEXT2_TRGEXT1_Msk        (0x2UL)        /*!< TRGEXT1 (Bitfield-Mask: 0x01)                         */
44397 /* =======================================================  ADTRGEXT3  ======================================================= */
44398  #define R_ADC_B0_ADTRGEXT3_TRGEXT0_Pos        (0UL)          /*!< TRGEXT0 (Bit 0)                                       */
44399  #define R_ADC_B0_ADTRGEXT3_TRGEXT0_Msk        (0x1UL)        /*!< TRGEXT0 (Bitfield-Mask: 0x01)                         */
44400  #define R_ADC_B0_ADTRGEXT3_TRGEXT1_Pos        (1UL)          /*!< TRGEXT1 (Bit 1)                                       */
44401  #define R_ADC_B0_ADTRGEXT3_TRGEXT1_Msk        (0x2UL)        /*!< TRGEXT1 (Bitfield-Mask: 0x01)                         */
44402 /* =======================================================  ADTRGEXT4  ======================================================= */
44403  #define R_ADC_B0_ADTRGEXT4_TRGEXT0_Pos        (0UL)          /*!< TRGEXT0 (Bit 0)                                       */
44404  #define R_ADC_B0_ADTRGEXT4_TRGEXT0_Msk        (0x1UL)        /*!< TRGEXT0 (Bitfield-Mask: 0x01)                         */
44405  #define R_ADC_B0_ADTRGEXT4_TRGEXT1_Pos        (1UL)          /*!< TRGEXT1 (Bit 1)                                       */
44406  #define R_ADC_B0_ADTRGEXT4_TRGEXT1_Msk        (0x2UL)        /*!< TRGEXT1 (Bitfield-Mask: 0x01)                         */
44407 /* =======================================================  ADTRGEXT5  ======================================================= */
44408  #define R_ADC_B0_ADTRGEXT5_TRGEXT0_Pos        (0UL)          /*!< TRGEXT0 (Bit 0)                                       */
44409  #define R_ADC_B0_ADTRGEXT5_TRGEXT0_Msk        (0x1UL)        /*!< TRGEXT0 (Bitfield-Mask: 0x01)                         */
44410  #define R_ADC_B0_ADTRGEXT5_TRGEXT1_Pos        (1UL)          /*!< TRGEXT1 (Bit 1)                                       */
44411  #define R_ADC_B0_ADTRGEXT5_TRGEXT1_Msk        (0x2UL)        /*!< TRGEXT1 (Bitfield-Mask: 0x01)                         */
44412 /* =======================================================  ADTRGEXT6  ======================================================= */
44413  #define R_ADC_B0_ADTRGEXT6_TRGEXT0_Pos        (0UL)          /*!< TRGEXT0 (Bit 0)                                       */
44414  #define R_ADC_B0_ADTRGEXT6_TRGEXT0_Msk        (0x1UL)        /*!< TRGEXT0 (Bitfield-Mask: 0x01)                         */
44415  #define R_ADC_B0_ADTRGEXT6_TRGEXT1_Pos        (1UL)          /*!< TRGEXT1 (Bit 1)                                       */
44416  #define R_ADC_B0_ADTRGEXT6_TRGEXT1_Msk        (0x2UL)        /*!< TRGEXT1 (Bitfield-Mask: 0x01)                         */
44417 /* =======================================================  ADTRGEXT7  ======================================================= */
44418  #define R_ADC_B0_ADTRGEXT7_TRGEXT0_Pos        (0UL)          /*!< TRGEXT0 (Bit 0)                                       */
44419  #define R_ADC_B0_ADTRGEXT7_TRGEXT0_Msk        (0x1UL)        /*!< TRGEXT0 (Bitfield-Mask: 0x01)                         */
44420  #define R_ADC_B0_ADTRGEXT7_TRGEXT1_Pos        (1UL)          /*!< TRGEXT1 (Bit 1)                                       */
44421  #define R_ADC_B0_ADTRGEXT7_TRGEXT1_Msk        (0x2UL)        /*!< TRGEXT1 (Bitfield-Mask: 0x01)                         */
44422 /* =======================================================  ADTRGEXT8  ======================================================= */
44423  #define R_ADC_B0_ADTRGEXT8_TRGEXT0_Pos        (0UL)          /*!< TRGEXT0 (Bit 0)                                       */
44424  #define R_ADC_B0_ADTRGEXT8_TRGEXT0_Msk        (0x1UL)        /*!< TRGEXT0 (Bitfield-Mask: 0x01)                         */
44425  #define R_ADC_B0_ADTRGEXT8_TRGEXT1_Pos        (1UL)          /*!< TRGEXT1 (Bit 1)                                       */
44426  #define R_ADC_B0_ADTRGEXT8_TRGEXT1_Msk        (0x2UL)        /*!< TRGEXT1 (Bitfield-Mask: 0x01)                         */
44427 /* =======================================================  ADTRGELC0  ======================================================= */
44428  #define R_ADC_B0_ADTRGELC0_TRGELCm_Pos        (0UL)          /*!< TRGELCm (Bit 0)                                       */
44429  #define R_ADC_B0_ADTRGELC0_TRGELCm_Msk        (0x3fUL)       /*!< TRGELCm (Bitfield-Mask: 0x3f)                         */
44430 /* =======================================================  ADTRGELC1  ======================================================= */
44431  #define R_ADC_B0_ADTRGELC1_TRGELCm_Pos        (0UL)          /*!< TRGELCm (Bit 0)                                       */
44432  #define R_ADC_B0_ADTRGELC1_TRGELCm_Msk        (0x3fUL)       /*!< TRGELCm (Bitfield-Mask: 0x3f)                         */
44433 /* =======================================================  ADTRGELC2  ======================================================= */
44434  #define R_ADC_B0_ADTRGELC2_TRGELCm_Pos        (0UL)          /*!< TRGELCm (Bit 0)                                       */
44435  #define R_ADC_B0_ADTRGELC2_TRGELCm_Msk        (0x3fUL)       /*!< TRGELCm (Bitfield-Mask: 0x3f)                         */
44436 /* =======================================================  ADTRGELC3  ======================================================= */
44437  #define R_ADC_B0_ADTRGELC3_TRGELCm_Pos        (0UL)          /*!< TRGELCm (Bit 0)                                       */
44438  #define R_ADC_B0_ADTRGELC3_TRGELCm_Msk        (0x3fUL)       /*!< TRGELCm (Bitfield-Mask: 0x3f)                         */
44439 /* =======================================================  ADTRGELC4  ======================================================= */
44440  #define R_ADC_B0_ADTRGELC4_TRGELCm_Pos        (0UL)          /*!< TRGELCm (Bit 0)                                       */
44441  #define R_ADC_B0_ADTRGELC4_TRGELCm_Msk        (0x3fUL)       /*!< TRGELCm (Bitfield-Mask: 0x3f)                         */
44442 /* =======================================================  ADTRGELC5  ======================================================= */
44443  #define R_ADC_B0_ADTRGELC5_TRGELCm_Pos        (0UL)          /*!< TRGELCm (Bit 0)                                       */
44444  #define R_ADC_B0_ADTRGELC5_TRGELCm_Msk        (0x3fUL)       /*!< TRGELCm (Bitfield-Mask: 0x3f)                         */
44445 /* =======================================================  ADTRGELC6  ======================================================= */
44446  #define R_ADC_B0_ADTRGELC6_TRGELCm_Pos        (0UL)          /*!< TRGELCm (Bit 0)                                       */
44447  #define R_ADC_B0_ADTRGELC6_TRGELCm_Msk        (0x3fUL)       /*!< TRGELCm (Bitfield-Mask: 0x3f)                         */
44448 /* =======================================================  ADTRGELC7  ======================================================= */
44449  #define R_ADC_B0_ADTRGELC7_TRGELCm_Pos        (0UL)          /*!< TRGELCm (Bit 0)                                       */
44450  #define R_ADC_B0_ADTRGELC7_TRGELCm_Msk        (0x3fUL)       /*!< TRGELCm (Bitfield-Mask: 0x3f)                         */
44451 /* =======================================================  ADTRGELC8  ======================================================= */
44452  #define R_ADC_B0_ADTRGELC8_TRGELCm_Pos        (0UL)          /*!< TRGELCm (Bit 0)                                       */
44453  #define R_ADC_B0_ADTRGELC8_TRGELCm_Msk        (0x3fUL)       /*!< TRGELCm (Bitfield-Mask: 0x3f)                         */
44454 /* =======================================================  ADTRGGPT0  ======================================================= */
44455  #define R_ADC_B0_ADTRGGPT0_TRGGPTAm_Pos       (0UL)          /*!< TRGGPTAm (Bit 0)                                      */
44456  #define R_ADC_B0_ADTRGGPT0_TRGGPTAm_Msk       (0x3ffUL)      /*!< TRGGPTAm (Bitfield-Mask: 0x3ff)                       */
44457  #define R_ADC_B0_ADTRGGPT0_TRGGPTBm_Pos       (16UL)         /*!< TRGGPTBm (Bit 16)                                     */
44458  #define R_ADC_B0_ADTRGGPT0_TRGGPTBm_Msk       (0x3ff0000UL)  /*!< TRGGPTBm (Bitfield-Mask: 0x3ff)                       */
44459 /* =======================================================  ADTRGGPT1  ======================================================= */
44460  #define R_ADC_B0_ADTRGGPT1_TRGGPTAm_Pos       (0UL)          /*!< TRGGPTAm (Bit 0)                                      */
44461  #define R_ADC_B0_ADTRGGPT1_TRGGPTAm_Msk       (0x3ffUL)      /*!< TRGGPTAm (Bitfield-Mask: 0x3ff)                       */
44462  #define R_ADC_B0_ADTRGGPT1_TRGGPTBm_Pos       (16UL)         /*!< TRGGPTBm (Bit 16)                                     */
44463  #define R_ADC_B0_ADTRGGPT1_TRGGPTBm_Msk       (0x3ff0000UL)  /*!< TRGGPTBm (Bitfield-Mask: 0x3ff)                       */
44464 /* =======================================================  ADTRGGPT2  ======================================================= */
44465  #define R_ADC_B0_ADTRGGPT2_TRGGPTAm_Pos       (0UL)          /*!< TRGGPTAm (Bit 0)                                      */
44466  #define R_ADC_B0_ADTRGGPT2_TRGGPTAm_Msk       (0x3ffUL)      /*!< TRGGPTAm (Bitfield-Mask: 0x3ff)                       */
44467  #define R_ADC_B0_ADTRGGPT2_TRGGPTBm_Pos       (16UL)         /*!< TRGGPTBm (Bit 16)                                     */
44468  #define R_ADC_B0_ADTRGGPT2_TRGGPTBm_Msk       (0x3ff0000UL)  /*!< TRGGPTBm (Bitfield-Mask: 0x3ff)                       */
44469 /* =======================================================  ADTRGGPT3  ======================================================= */
44470  #define R_ADC_B0_ADTRGGPT3_TRGGPTAm_Pos       (0UL)          /*!< TRGGPTAm (Bit 0)                                      */
44471  #define R_ADC_B0_ADTRGGPT3_TRGGPTAm_Msk       (0x3ffUL)      /*!< TRGGPTAm (Bitfield-Mask: 0x3ff)                       */
44472  #define R_ADC_B0_ADTRGGPT3_TRGGPTBm_Pos       (16UL)         /*!< TRGGPTBm (Bit 16)                                     */
44473  #define R_ADC_B0_ADTRGGPT3_TRGGPTBm_Msk       (0x3ff0000UL)  /*!< TRGGPTBm (Bitfield-Mask: 0x3ff)                       */
44474 /* =======================================================  ADTRGGPT4  ======================================================= */
44475  #define R_ADC_B0_ADTRGGPT4_TRGGPTAm_Pos       (0UL)          /*!< TRGGPTAm (Bit 0)                                      */
44476  #define R_ADC_B0_ADTRGGPT4_TRGGPTAm_Msk       (0x3ffUL)      /*!< TRGGPTAm (Bitfield-Mask: 0x3ff)                       */
44477  #define R_ADC_B0_ADTRGGPT4_TRGGPTBm_Pos       (16UL)         /*!< TRGGPTBm (Bit 16)                                     */
44478  #define R_ADC_B0_ADTRGGPT4_TRGGPTBm_Msk       (0x3ff0000UL)  /*!< TRGGPTBm (Bitfield-Mask: 0x3ff)                       */
44479 /* =======================================================  ADTRGGPT5  ======================================================= */
44480  #define R_ADC_B0_ADTRGGPT5_TRGGPTAm_Pos       (0UL)          /*!< TRGGPTAm (Bit 0)                                      */
44481  #define R_ADC_B0_ADTRGGPT5_TRGGPTAm_Msk       (0x3ffUL)      /*!< TRGGPTAm (Bitfield-Mask: 0x3ff)                       */
44482  #define R_ADC_B0_ADTRGGPT5_TRGGPTBm_Pos       (16UL)         /*!< TRGGPTBm (Bit 16)                                     */
44483  #define R_ADC_B0_ADTRGGPT5_TRGGPTBm_Msk       (0x3ff0000UL)  /*!< TRGGPTBm (Bitfield-Mask: 0x3ff)                       */
44484 /* =======================================================  ADTRGGPT6  ======================================================= */
44485  #define R_ADC_B0_ADTRGGPT6_TRGGPTAm_Pos       (0UL)          /*!< TRGGPTAm (Bit 0)                                      */
44486  #define R_ADC_B0_ADTRGGPT6_TRGGPTAm_Msk       (0x3ffUL)      /*!< TRGGPTAm (Bitfield-Mask: 0x3ff)                       */
44487  #define R_ADC_B0_ADTRGGPT6_TRGGPTBm_Pos       (16UL)         /*!< TRGGPTBm (Bit 16)                                     */
44488  #define R_ADC_B0_ADTRGGPT6_TRGGPTBm_Msk       (0x3ff0000UL)  /*!< TRGGPTBm (Bitfield-Mask: 0x3ff)                       */
44489 /* =======================================================  ADTRGGPT7  ======================================================= */
44490  #define R_ADC_B0_ADTRGGPT7_TRGGPTAm_Pos       (0UL)          /*!< TRGGPTAm (Bit 0)                                      */
44491  #define R_ADC_B0_ADTRGGPT7_TRGGPTAm_Msk       (0x3ffUL)      /*!< TRGGPTAm (Bitfield-Mask: 0x3ff)                       */
44492  #define R_ADC_B0_ADTRGGPT7_TRGGPTBm_Pos       (16UL)         /*!< TRGGPTBm (Bit 16)                                     */
44493  #define R_ADC_B0_ADTRGGPT7_TRGGPTBm_Msk       (0x3ff0000UL)  /*!< TRGGPTBm (Bitfield-Mask: 0x3ff)                       */
44494 /* =======================================================  ADTRGGPT8  ======================================================= */
44495  #define R_ADC_B0_ADTRGGPT8_TRGGPTAm_Pos       (0UL)          /*!< TRGGPTAm (Bit 0)                                      */
44496  #define R_ADC_B0_ADTRGGPT8_TRGGPTAm_Msk       (0x3ffUL)      /*!< TRGGPTAm (Bitfield-Mask: 0x3ff)                       */
44497  #define R_ADC_B0_ADTRGGPT8_TRGGPTBm_Pos       (16UL)         /*!< TRGGPTBm (Bit 16)                                     */
44498  #define R_ADC_B0_ADTRGGPT8_TRGGPTBm_Msk       (0x3ff0000UL)  /*!< TRGGPTBm (Bitfield-Mask: 0x3ff)                       */
44499 /* =======================================================  ADTRGDLR0  ======================================================= */
44500  #define R_ADC_B0_ADTRGDLR0_TRGDLY0_Pos        (0UL)          /*!< TRGDLY0 (Bit 0)                                       */
44501  #define R_ADC_B0_ADTRGDLR0_TRGDLY0_Msk        (0xffUL)       /*!< TRGDLY0 (Bitfield-Mask: 0xff)                         */
44502  #define R_ADC_B0_ADTRGDLR0_TRGDLY1_Pos        (16UL)         /*!< TRGDLY1 (Bit 16)                                      */
44503  #define R_ADC_B0_ADTRGDLR0_TRGDLY1_Msk        (0xff0000UL)   /*!< TRGDLY1 (Bitfield-Mask: 0xff)                         */
44504 /* =======================================================  ADTRGDLR1  ======================================================= */
44505  #define R_ADC_B0_ADTRGDLR1_TRGDLY2_Pos        (0UL)          /*!< TRGDLY2 (Bit 0)                                       */
44506  #define R_ADC_B0_ADTRGDLR1_TRGDLY2_Msk        (0xffUL)       /*!< TRGDLY2 (Bitfield-Mask: 0xff)                         */
44507  #define R_ADC_B0_ADTRGDLR1_TRGDLY3_Pos        (16UL)         /*!< TRGDLY3 (Bit 16)                                      */
44508  #define R_ADC_B0_ADTRGDLR1_TRGDLY3_Msk        (0xff0000UL)   /*!< TRGDLY3 (Bitfield-Mask: 0xff)                         */
44509 /* =======================================================  ADTRGDLR2  ======================================================= */
44510  #define R_ADC_B0_ADTRGDLR2_TRGDLY4_Pos        (0UL)          /*!< TRGDLY4 (Bit 0)                                       */
44511  #define R_ADC_B0_ADTRGDLR2_TRGDLY4_Msk        (0xffUL)       /*!< TRGDLY4 (Bitfield-Mask: 0xff)                         */
44512  #define R_ADC_B0_ADTRGDLR2_TRGDLY5_Pos        (16UL)         /*!< TRGDLY5 (Bit 16)                                      */
44513  #define R_ADC_B0_ADTRGDLR2_TRGDLY5_Msk        (0xff0000UL)   /*!< TRGDLY5 (Bitfield-Mask: 0xff)                         */
44514 /* =======================================================  ADTRGDLR3  ======================================================= */
44515  #define R_ADC_B0_ADTRGDLR3_TRGDLY6_Pos        (0UL)          /*!< TRGDLY6 (Bit 0)                                       */
44516  #define R_ADC_B0_ADTRGDLR3_TRGDLY6_Msk        (0xffUL)       /*!< TRGDLY6 (Bitfield-Mask: 0xff)                         */
44517  #define R_ADC_B0_ADTRGDLR3_TRGDLY7_Pos        (16UL)         /*!< TRGDLY7 (Bit 16)                                      */
44518  #define R_ADC_B0_ADTRGDLR3_TRGDLY7_Msk        (0xff0000UL)   /*!< TRGDLY7 (Bitfield-Mask: 0xff)                         */
44519 /* =======================================================  ADTRGDLR4  ======================================================= */
44520  #define R_ADC_B0_ADTRGDLR4_TRGDLY8_Pos        (0UL)          /*!< TRGDLY8 (Bit 0)                                       */
44521  #define R_ADC_B0_ADTRGDLR4_TRGDLY8_Msk        (0xffUL)       /*!< TRGDLY8 (Bitfield-Mask: 0xff)                         */
44522 /* =======================================================  ADSGDCR0  ======================================================== */
44523  #define R_ADC_B0_ADSGDCR0_DIAGVAL_Pos         (0UL)          /*!< DIAGVAL (Bit 0)                                       */
44524  #define R_ADC_B0_ADSGDCR0_DIAGVAL_Msk         (0x7UL)        /*!< DIAGVAL (Bitfield-Mask: 0x07)                         */
44525  #define R_ADC_B0_ADSGDCR0_ADDISEN_Pos         (16UL)         /*!< ADDISEN (Bit 16)                                      */
44526  #define R_ADC_B0_ADSGDCR0_ADDISEN_Msk         (0x10000UL)    /*!< ADDISEN (Bitfield-Mask: 0x01)                         */
44527  #define R_ADC_B0_ADSGDCR0_ADDISP_Pos          (20UL)         /*!< ADDISP (Bit 20)                                       */
44528  #define R_ADC_B0_ADSGDCR0_ADDISP_Msk          (0x100000UL)   /*!< ADDISP (Bitfield-Mask: 0x01)                          */
44529  #define R_ADC_B0_ADSGDCR0_ADDISN_Pos          (21UL)         /*!< ADDISN (Bit 21)                                       */
44530  #define R_ADC_B0_ADSGDCR0_ADDISN_Msk          (0x200000UL)   /*!< ADDISN (Bitfield-Mask: 0x01)                          */
44531  #define R_ADC_B0_ADSGDCR0_ADNDIS_Pos          (24UL)         /*!< ADNDIS (Bit 24)                                       */
44532  #define R_ADC_B0_ADSGDCR0_ADNDIS_Msk          (0xf000000UL)  /*!< ADNDIS (Bitfield-Mask: 0x0f)                          */
44533 /* =======================================================  ADSGDCR1  ======================================================== */
44534  #define R_ADC_B0_ADSGDCR1_DIAGVAL_Pos         (0UL)          /*!< DIAGVAL (Bit 0)                                       */
44535  #define R_ADC_B0_ADSGDCR1_DIAGVAL_Msk         (0x7UL)        /*!< DIAGVAL (Bitfield-Mask: 0x07)                         */
44536  #define R_ADC_B0_ADSGDCR1_ADDISEN_Pos         (16UL)         /*!< ADDISEN (Bit 16)                                      */
44537  #define R_ADC_B0_ADSGDCR1_ADDISEN_Msk         (0x10000UL)    /*!< ADDISEN (Bitfield-Mask: 0x01)                         */
44538  #define R_ADC_B0_ADSGDCR1_ADDISP_Pos          (20UL)         /*!< ADDISP (Bit 20)                                       */
44539  #define R_ADC_B0_ADSGDCR1_ADDISP_Msk          (0x100000UL)   /*!< ADDISP (Bitfield-Mask: 0x01)                          */
44540  #define R_ADC_B0_ADSGDCR1_ADDISN_Pos          (21UL)         /*!< ADDISN (Bit 21)                                       */
44541  #define R_ADC_B0_ADSGDCR1_ADDISN_Msk          (0x200000UL)   /*!< ADDISN (Bitfield-Mask: 0x01)                          */
44542  #define R_ADC_B0_ADSGDCR1_ADNDIS_Pos          (24UL)         /*!< ADNDIS (Bit 24)                                       */
44543  #define R_ADC_B0_ADSGDCR1_ADNDIS_Msk          (0xf000000UL)  /*!< ADNDIS (Bitfield-Mask: 0x0f)                          */
44544 /* =======================================================  ADSGDCR2  ======================================================== */
44545  #define R_ADC_B0_ADSGDCR2_DIAGVAL_Pos         (0UL)          /*!< DIAGVAL (Bit 0)                                       */
44546  #define R_ADC_B0_ADSGDCR2_DIAGVAL_Msk         (0x7UL)        /*!< DIAGVAL (Bitfield-Mask: 0x07)                         */
44547  #define R_ADC_B0_ADSGDCR2_ADDISEN_Pos         (16UL)         /*!< ADDISEN (Bit 16)                                      */
44548  #define R_ADC_B0_ADSGDCR2_ADDISEN_Msk         (0x10000UL)    /*!< ADDISEN (Bitfield-Mask: 0x01)                         */
44549  #define R_ADC_B0_ADSGDCR2_ADDISP_Pos          (20UL)         /*!< ADDISP (Bit 20)                                       */
44550  #define R_ADC_B0_ADSGDCR2_ADDISP_Msk          (0x100000UL)   /*!< ADDISP (Bitfield-Mask: 0x01)                          */
44551  #define R_ADC_B0_ADSGDCR2_ADDISN_Pos          (21UL)         /*!< ADDISN (Bit 21)                                       */
44552  #define R_ADC_B0_ADSGDCR2_ADDISN_Msk          (0x200000UL)   /*!< ADDISN (Bitfield-Mask: 0x01)                          */
44553  #define R_ADC_B0_ADSGDCR2_ADNDIS_Pos          (24UL)         /*!< ADNDIS (Bit 24)                                       */
44554  #define R_ADC_B0_ADSGDCR2_ADNDIS_Msk          (0xf000000UL)  /*!< ADNDIS (Bitfield-Mask: 0x0f)                          */
44555 /* =======================================================  ADSGDCR3  ======================================================== */
44556  #define R_ADC_B0_ADSGDCR3_DIAGVAL_Pos         (0UL)          /*!< DIAGVAL (Bit 0)                                       */
44557  #define R_ADC_B0_ADSGDCR3_DIAGVAL_Msk         (0x7UL)        /*!< DIAGVAL (Bitfield-Mask: 0x07)                         */
44558  #define R_ADC_B0_ADSGDCR3_ADDISEN_Pos         (16UL)         /*!< ADDISEN (Bit 16)                                      */
44559  #define R_ADC_B0_ADSGDCR3_ADDISEN_Msk         (0x10000UL)    /*!< ADDISEN (Bitfield-Mask: 0x01)                         */
44560  #define R_ADC_B0_ADSGDCR3_ADDISP_Pos          (20UL)         /*!< ADDISP (Bit 20)                                       */
44561  #define R_ADC_B0_ADSGDCR3_ADDISP_Msk          (0x100000UL)   /*!< ADDISP (Bitfield-Mask: 0x01)                          */
44562  #define R_ADC_B0_ADSGDCR3_ADDISN_Pos          (21UL)         /*!< ADDISN (Bit 21)                                       */
44563  #define R_ADC_B0_ADSGDCR3_ADDISN_Msk          (0x200000UL)   /*!< ADDISN (Bitfield-Mask: 0x01)                          */
44564  #define R_ADC_B0_ADSGDCR3_ADNDIS_Pos          (24UL)         /*!< ADNDIS (Bit 24)                                       */
44565  #define R_ADC_B0_ADSGDCR3_ADNDIS_Msk          (0xf000000UL)  /*!< ADNDIS (Bitfield-Mask: 0x0f)                          */
44566 /* =======================================================  ADSGDCR4  ======================================================== */
44567  #define R_ADC_B0_ADSGDCR4_DIAGVAL_Pos         (0UL)          /*!< DIAGVAL (Bit 0)                                       */
44568  #define R_ADC_B0_ADSGDCR4_DIAGVAL_Msk         (0x7UL)        /*!< DIAGVAL (Bitfield-Mask: 0x07)                         */
44569  #define R_ADC_B0_ADSGDCR4_ADDISEN_Pos         (16UL)         /*!< ADDISEN (Bit 16)                                      */
44570  #define R_ADC_B0_ADSGDCR4_ADDISEN_Msk         (0x10000UL)    /*!< ADDISEN (Bitfield-Mask: 0x01)                         */
44571  #define R_ADC_B0_ADSGDCR4_ADDISP_Pos          (20UL)         /*!< ADDISP (Bit 20)                                       */
44572  #define R_ADC_B0_ADSGDCR4_ADDISP_Msk          (0x100000UL)   /*!< ADDISP (Bitfield-Mask: 0x01)                          */
44573  #define R_ADC_B0_ADSGDCR4_ADDISN_Pos          (21UL)         /*!< ADDISN (Bit 21)                                       */
44574  #define R_ADC_B0_ADSGDCR4_ADDISN_Msk          (0x200000UL)   /*!< ADDISN (Bitfield-Mask: 0x01)                          */
44575  #define R_ADC_B0_ADSGDCR4_ADNDIS_Pos          (24UL)         /*!< ADNDIS (Bit 24)                                       */
44576  #define R_ADC_B0_ADSGDCR4_ADNDIS_Msk          (0xf000000UL)  /*!< ADNDIS (Bitfield-Mask: 0x0f)                          */
44577 /* =======================================================  ADSGDCR5  ======================================================== */
44578  #define R_ADC_B0_ADSGDCR5_DIAGVAL_Pos         (0UL)          /*!< DIAGVAL (Bit 0)                                       */
44579  #define R_ADC_B0_ADSGDCR5_DIAGVAL_Msk         (0x7UL)        /*!< DIAGVAL (Bitfield-Mask: 0x07)                         */
44580  #define R_ADC_B0_ADSGDCR5_ADDISEN_Pos         (16UL)         /*!< ADDISEN (Bit 16)                                      */
44581  #define R_ADC_B0_ADSGDCR5_ADDISEN_Msk         (0x10000UL)    /*!< ADDISEN (Bitfield-Mask: 0x01)                         */
44582  #define R_ADC_B0_ADSGDCR5_ADDISP_Pos          (20UL)         /*!< ADDISP (Bit 20)                                       */
44583  #define R_ADC_B0_ADSGDCR5_ADDISP_Msk          (0x100000UL)   /*!< ADDISP (Bitfield-Mask: 0x01)                          */
44584  #define R_ADC_B0_ADSGDCR5_ADDISN_Pos          (21UL)         /*!< ADDISN (Bit 21)                                       */
44585  #define R_ADC_B0_ADSGDCR5_ADDISN_Msk          (0x200000UL)   /*!< ADDISN (Bitfield-Mask: 0x01)                          */
44586  #define R_ADC_B0_ADSGDCR5_ADNDIS_Pos          (24UL)         /*!< ADNDIS (Bit 24)                                       */
44587  #define R_ADC_B0_ADSGDCR5_ADNDIS_Msk          (0xf000000UL)  /*!< ADNDIS (Bitfield-Mask: 0x0f)                          */
44588 /* =======================================================  ADSGDCR6  ======================================================== */
44589  #define R_ADC_B0_ADSGDCR6_DIAGVAL_Pos         (0UL)          /*!< DIAGVAL (Bit 0)                                       */
44590  #define R_ADC_B0_ADSGDCR6_DIAGVAL_Msk         (0x7UL)        /*!< DIAGVAL (Bitfield-Mask: 0x07)                         */
44591  #define R_ADC_B0_ADSGDCR6_ADDISEN_Pos         (16UL)         /*!< ADDISEN (Bit 16)                                      */
44592  #define R_ADC_B0_ADSGDCR6_ADDISEN_Msk         (0x10000UL)    /*!< ADDISEN (Bitfield-Mask: 0x01)                         */
44593  #define R_ADC_B0_ADSGDCR6_ADDISP_Pos          (20UL)         /*!< ADDISP (Bit 20)                                       */
44594  #define R_ADC_B0_ADSGDCR6_ADDISP_Msk          (0x100000UL)   /*!< ADDISP (Bitfield-Mask: 0x01)                          */
44595  #define R_ADC_B0_ADSGDCR6_ADDISN_Pos          (21UL)         /*!< ADDISN (Bit 21)                                       */
44596  #define R_ADC_B0_ADSGDCR6_ADDISN_Msk          (0x200000UL)   /*!< ADDISN (Bitfield-Mask: 0x01)                          */
44597  #define R_ADC_B0_ADSGDCR6_ADNDIS_Pos          (24UL)         /*!< ADNDIS (Bit 24)                                       */
44598  #define R_ADC_B0_ADSGDCR6_ADNDIS_Msk          (0xf000000UL)  /*!< ADNDIS (Bitfield-Mask: 0x0f)                          */
44599 /* =======================================================  ADSGDCR7  ======================================================== */
44600  #define R_ADC_B0_ADSGDCR7_DIAGVAL_Pos         (0UL)          /*!< DIAGVAL (Bit 0)                                       */
44601  #define R_ADC_B0_ADSGDCR7_DIAGVAL_Msk         (0x7UL)        /*!< DIAGVAL (Bitfield-Mask: 0x07)                         */
44602  #define R_ADC_B0_ADSGDCR7_ADDISEN_Pos         (16UL)         /*!< ADDISEN (Bit 16)                                      */
44603  #define R_ADC_B0_ADSGDCR7_ADDISEN_Msk         (0x10000UL)    /*!< ADDISEN (Bitfield-Mask: 0x01)                         */
44604  #define R_ADC_B0_ADSGDCR7_ADDISP_Pos          (20UL)         /*!< ADDISP (Bit 20)                                       */
44605  #define R_ADC_B0_ADSGDCR7_ADDISP_Msk          (0x100000UL)   /*!< ADDISP (Bitfield-Mask: 0x01)                          */
44606  #define R_ADC_B0_ADSGDCR7_ADDISN_Pos          (21UL)         /*!< ADDISN (Bit 21)                                       */
44607  #define R_ADC_B0_ADSGDCR7_ADDISN_Msk          (0x200000UL)   /*!< ADDISN (Bitfield-Mask: 0x01)                          */
44608  #define R_ADC_B0_ADSGDCR7_ADNDIS_Pos          (24UL)         /*!< ADNDIS (Bit 24)                                       */
44609  #define R_ADC_B0_ADSGDCR7_ADNDIS_Msk          (0xf000000UL)  /*!< ADNDIS (Bitfield-Mask: 0x0f)                          */
44610 /* =======================================================  ADSGDCR8  ======================================================== */
44611  #define R_ADC_B0_ADSGDCR8_DIAGVAL_Pos         (0UL)          /*!< DIAGVAL (Bit 0)                                       */
44612  #define R_ADC_B0_ADSGDCR8_DIAGVAL_Msk         (0x7UL)        /*!< DIAGVAL (Bitfield-Mask: 0x07)                         */
44613  #define R_ADC_B0_ADSGDCR8_ADDISEN_Pos         (16UL)         /*!< ADDISEN (Bit 16)                                      */
44614  #define R_ADC_B0_ADSGDCR8_ADDISEN_Msk         (0x10000UL)    /*!< ADDISEN (Bitfield-Mask: 0x01)                         */
44615  #define R_ADC_B0_ADSGDCR8_ADDISP_Pos          (20UL)         /*!< ADDISP (Bit 20)                                       */
44616  #define R_ADC_B0_ADSGDCR8_ADDISP_Msk          (0x100000UL)   /*!< ADDISP (Bitfield-Mask: 0x01)                          */
44617  #define R_ADC_B0_ADSGDCR8_ADDISN_Pos          (21UL)         /*!< ADDISN (Bit 21)                                       */
44618  #define R_ADC_B0_ADSGDCR8_ADDISN_Msk          (0x200000UL)   /*!< ADDISN (Bitfield-Mask: 0x01)                          */
44619  #define R_ADC_B0_ADSGDCR8_ADNDIS_Pos          (24UL)         /*!< ADNDIS (Bit 24)                                       */
44620  #define R_ADC_B0_ADSGDCR8_ADNDIS_Msk          (0xf000000UL)  /*!< ADNDIS (Bitfield-Mask: 0x0f)                          */
44621 /* ========================================================  ADSSTR0  ======================================================== */
44622  #define R_ADC_B0_ADSSTR0_SST0_Pos             (0UL)          /*!< SST0 (Bit 0)                                          */
44623  #define R_ADC_B0_ADSSTR0_SST0_Msk             (0x3ffUL)      /*!< SST0 (Bitfield-Mask: 0x3ff)                           */
44624  #define R_ADC_B0_ADSSTR0_SST1_Pos             (16UL)         /*!< SST1 (Bit 16)                                         */
44625  #define R_ADC_B0_ADSSTR0_SST1_Msk             (0x3ff0000UL)  /*!< SST1 (Bitfield-Mask: 0x3ff)                           */
44626 /* ========================================================  ADSSTR1  ======================================================== */
44627  #define R_ADC_B0_ADSSTR1_SST2_Pos             (0UL)          /*!< SST2 (Bit 0)                                          */
44628  #define R_ADC_B0_ADSSTR1_SST2_Msk             (0x3ffUL)      /*!< SST2 (Bitfield-Mask: 0x3ff)                           */
44629  #define R_ADC_B0_ADSSTR1_SST3_Pos             (16UL)         /*!< SST3 (Bit 16)                                         */
44630  #define R_ADC_B0_ADSSTR1_SST3_Msk             (0x3ff0000UL)  /*!< SST3 (Bitfield-Mask: 0x3ff)                           */
44631 /* ========================================================  ADSSTR2  ======================================================== */
44632  #define R_ADC_B0_ADSSTR2_SST4_Pos             (0UL)          /*!< SST4 (Bit 0)                                          */
44633  #define R_ADC_B0_ADSSTR2_SST4_Msk             (0x3ffUL)      /*!< SST4 (Bitfield-Mask: 0x3ff)                           */
44634  #define R_ADC_B0_ADSSTR2_SST5_Pos             (16UL)         /*!< SST5 (Bit 16)                                         */
44635  #define R_ADC_B0_ADSSTR2_SST5_Msk             (0x3ff0000UL)  /*!< SST5 (Bitfield-Mask: 0x3ff)                           */
44636 /* ========================================================  ADSSTR3  ======================================================== */
44637  #define R_ADC_B0_ADSSTR3_SST6_Pos             (0UL)          /*!< SST6 (Bit 0)                                          */
44638  #define R_ADC_B0_ADSSTR3_SST6_Msk             (0x3ffUL)      /*!< SST6 (Bitfield-Mask: 0x3ff)                           */
44639  #define R_ADC_B0_ADSSTR3_SST7_Pos             (16UL)         /*!< SST7 (Bit 16)                                         */
44640  #define R_ADC_B0_ADSSTR3_SST7_Msk             (0x3ff0000UL)  /*!< SST7 (Bitfield-Mask: 0x3ff)                           */
44641 /* ========================================================  ADSSTR4  ======================================================== */
44642  #define R_ADC_B0_ADSSTR4_SST8_Pos             (0UL)          /*!< SST8 (Bit 0)                                          */
44643  #define R_ADC_B0_ADSSTR4_SST8_Msk             (0x3ffUL)      /*!< SST8 (Bitfield-Mask: 0x3ff)                           */
44644  #define R_ADC_B0_ADSSTR4_SST9_Pos             (16UL)         /*!< SST9 (Bit 16)                                         */
44645  #define R_ADC_B0_ADSSTR4_SST9_Msk             (0x3ff0000UL)  /*!< SST9 (Bitfield-Mask: 0x3ff)                           */
44646 /* ========================================================  ADSSTR5  ======================================================== */
44647  #define R_ADC_B0_ADSSTR5_SST10_Pos            (0UL)          /*!< SST10 (Bit 0)                                         */
44648  #define R_ADC_B0_ADSSTR5_SST10_Msk            (0x3ffUL)      /*!< SST10 (Bitfield-Mask: 0x3ff)                          */
44649  #define R_ADC_B0_ADSSTR5_SST11_Pos            (16UL)         /*!< SST11 (Bit 16)                                        */
44650  #define R_ADC_B0_ADSSTR5_SST11_Msk            (0x3ff0000UL)  /*!< SST11 (Bitfield-Mask: 0x3ff)                          */
44651 /* ========================================================  ADSSTR6  ======================================================== */
44652  #define R_ADC_B0_ADSSTR6_SST12_Pos            (0UL)          /*!< SST12 (Bit 0)                                         */
44653  #define R_ADC_B0_ADSSTR6_SST12_Msk            (0x3ffUL)      /*!< SST12 (Bitfield-Mask: 0x3ff)                          */
44654  #define R_ADC_B0_ADSSTR6_SST13_Pos            (16UL)         /*!< SST13 (Bit 16)                                        */
44655  #define R_ADC_B0_ADSSTR6_SST13_Msk            (0x3ff0000UL)  /*!< SST13 (Bitfield-Mask: 0x3ff)                          */
44656 /* ========================================================  ADSSTR7  ======================================================== */
44657  #define R_ADC_B0_ADSSTR7_SST14_Pos            (0UL)          /*!< SST14 (Bit 0)                                         */
44658  #define R_ADC_B0_ADSSTR7_SST14_Msk            (0x3ffUL)      /*!< SST14 (Bitfield-Mask: 0x3ff)                          */
44659  #define R_ADC_B0_ADSSTR7_SST15_Pos            (16UL)         /*!< SST15 (Bit 16)                                        */
44660  #define R_ADC_B0_ADSSTR7_SST15_Msk            (0x3ff0000UL)  /*!< SST15 (Bitfield-Mask: 0x3ff)                          */
44661 /* =======================================================  ADCNVSTR  ======================================================== */
44662  #define R_ADC_B0_ADCNVSTR_CST0_Pos            (0UL)          /*!< CST0 (Bit 0)                                          */
44663  #define R_ADC_B0_ADCNVSTR_CST0_Msk            (0x3fUL)       /*!< CST0 (Bitfield-Mask: 0x3f)                            */
44664  #define R_ADC_B0_ADCNVSTR_CST1_Pos            (8UL)          /*!< CST1 (Bit 8)                                          */
44665  #define R_ADC_B0_ADCNVSTR_CST1_Msk            (0x3f00UL)     /*!< CST1 (Bitfield-Mask: 0x3f)                            */
44666 /* =======================================================  ADCALSTCR  ======================================================= */
44667  #define R_ADC_B0_ADCALSTCR_CALADSST_Pos       (0UL)          /*!< CALADSST (Bit 0)                                      */
44668  #define R_ADC_B0_ADCALSTCR_CALADSST_Msk       (0x3ffUL)      /*!< CALADSST (Bitfield-Mask: 0x3ff)                       */
44669  #define R_ADC_B0_ADCALSTCR_CALADCST_Pos       (16UL)         /*!< CALADCST (Bit 16)                                     */
44670  #define R_ADC_B0_ADCALSTCR_CALADCST_Msk       (0x3f0000UL)   /*!< CALADCST (Bitfield-Mask: 0x3f)                        */
44671 /* ========================================================  ADSHCR0  ======================================================== */
44672  #define R_ADC_B0_ADSHCR0_SHEN0_Pos            (0UL)          /*!< SHEN0 (Bit 0)                                         */
44673  #define R_ADC_B0_ADSHCR0_SHEN0_Msk            (0x1UL)        /*!< SHEN0 (Bitfield-Mask: 0x01)                           */
44674  #define R_ADC_B0_ADSHCR0_SHEN1_Pos            (1UL)          /*!< SHEN1 (Bit 1)                                         */
44675  #define R_ADC_B0_ADSHCR0_SHEN1_Msk            (0x2UL)        /*!< SHEN1 (Bitfield-Mask: 0x01)                           */
44676  #define R_ADC_B0_ADSHCR0_SHEN2_Pos            (2UL)          /*!< SHEN2 (Bit 2)                                         */
44677  #define R_ADC_B0_ADSHCR0_SHEN2_Msk            (0x4UL)        /*!< SHEN2 (Bitfield-Mask: 0x01)                           */
44678 /* =======================================================  ADSHSTR0  ======================================================== */
44679  #define R_ADC_B0_ADSHSTR0_SHSST_Pos           (0UL)          /*!< SHSST (Bit 0)                                         */
44680  #define R_ADC_B0_ADSHSTR0_SHSST_Msk           (0xffUL)       /*!< SHSST (Bitfield-Mask: 0xff)                           */
44681  #define R_ADC_B0_ADSHSTR0_SHHST_Pos           (16UL)         /*!< SHHST (Bit 16)                                        */
44682  #define R_ADC_B0_ADSHSTR0_SHHST_Msk           (0x70000UL)    /*!< SHHST (Bitfield-Mask: 0x07)                           */
44683 /* ========================================================  ADSHCR1  ======================================================== */
44684  #define R_ADC_B0_ADSHCR1_SHEN4_Pos            (0UL)          /*!< SHEN4 (Bit 0)                                         */
44685  #define R_ADC_B0_ADSHCR1_SHEN4_Msk            (0x1UL)        /*!< SHEN4 (Bitfield-Mask: 0x01)                           */
44686  #define R_ADC_B0_ADSHCR1_SHEN5_Pos            (1UL)          /*!< SHEN5 (Bit 1)                                         */
44687  #define R_ADC_B0_ADSHCR1_SHEN5_Msk            (0x2UL)        /*!< SHEN5 (Bitfield-Mask: 0x01)                           */
44688  #define R_ADC_B0_ADSHCR1_SHEN6_Pos            (2UL)          /*!< SHEN6 (Bit 2)                                         */
44689  #define R_ADC_B0_ADSHCR1_SHEN6_Msk            (0x4UL)        /*!< SHEN6 (Bitfield-Mask: 0x01)                           */
44690 /* =======================================================  ADSHSTR1  ======================================================== */
44691  #define R_ADC_B0_ADSHSTR1_SHSST_Pos           (0UL)          /*!< SHSST (Bit 0)                                         */
44692  #define R_ADC_B0_ADSHSTR1_SHSST_Msk           (0xffUL)       /*!< SHSST (Bitfield-Mask: 0xff)                           */
44693  #define R_ADC_B0_ADSHSTR1_SHHST_Pos           (16UL)         /*!< SHHST (Bit 16)                                        */
44694  #define R_ADC_B0_ADSHSTR1_SHHST_Msk           (0x70000UL)    /*!< SHHST (Bitfield-Mask: 0x07)                           */
44695 /* =======================================================  ADCALSHCR  ======================================================= */
44696  #define R_ADC_B0_ADCALSHCR_CALSHSST_Pos       (0UL)          /*!< CALSHSST (Bit 0)                                      */
44697  #define R_ADC_B0_ADCALSHCR_CALSHSST_Msk       (0xffUL)       /*!< CALSHSST (Bitfield-Mask: 0xff)                        */
44698  #define R_ADC_B0_ADCALSHCR_CALSHHST_Pos       (16UL)         /*!< CALSHHST (Bit 16)                                     */
44699  #define R_ADC_B0_ADCALSHCR_CALSHHST_Msk       (0x70000UL)    /*!< CALSHHST (Bitfield-Mask: 0x07)                        */
44700 /* ========================================================  ADPGACR  ======================================================== */
44701  #define R_ADC_B0_ADPGACR_PGADEN_Pos           (1UL)          /*!< PGADEN (Bit 1)                                        */
44702  #define R_ADC_B0_ADPGACR_PGADEN_Msk           (0x2UL)        /*!< PGADEN (Bitfield-Mask: 0x01)                          */
44703  #define R_ADC_B0_ADPGACR_PGASEL1_Pos          (2UL)          /*!< PGASEL1 (Bit 2)                                       */
44704  #define R_ADC_B0_ADPGACR_PGASEL1_Msk          (0x4UL)        /*!< PGASEL1 (Bitfield-Mask: 0x01)                         */
44705  #define R_ADC_B0_ADPGACR_PGAENAMP_Pos         (3UL)          /*!< PGAENAMP (Bit 3)                                      */
44706  #define R_ADC_B0_ADPGACR_PGAENAMP_Msk         (0x8UL)        /*!< PGAENAMP (Bitfield-Mask: 0x01)                        */
44707  #define R_ADC_B0_ADPGACR_PGAGEN_Pos           (16UL)         /*!< PGAGEN (Bit 16)                                       */
44708  #define R_ADC_B0_ADPGACR_PGAGEN_Msk           (0x10000UL)    /*!< PGAGEN (Bitfield-Mask: 0x01)                          */
44709  #define R_ADC_B0_ADPGACR_PGADG_Pos            (20UL)         /*!< PGADG (Bit 20)                                        */
44710  #define R_ADC_B0_ADPGACR_PGADG_Msk            (0x300000UL)   /*!< PGADG (Bitfield-Mask: 0x03)                           */
44711  #define R_ADC_B0_ADPGACR_PGAGAIN_Pos          (24UL)         /*!< PGAGAIN (Bit 24)                                      */
44712  #define R_ADC_B0_ADPGACR_PGAGAIN_Msk          (0xf000000UL)  /*!< PGAGAIN (Bitfield-Mask: 0x0f)                         */
44713 /* ======================================================  ADPGAMONCR  ======================================================= */
44714  #define R_ADC_B0_ADPGAMONCR_PGAMON_Pos        (0UL)          /*!< PGAMON (Bit 0)                                        */
44715  #define R_ADC_B0_ADPGAMONCR_PGAMON_Msk        (0x7UL)        /*!< PGAMON (Bitfield-Mask: 0x07)                          */
44716  #define R_ADC_B0_ADPGAMONCR_MONSEL0_Pos       (16UL)         /*!< MONSEL0 (Bit 16)                                      */
44717  #define R_ADC_B0_ADPGAMONCR_MONSEL0_Msk       (0x10000UL)    /*!< MONSEL0 (Bitfield-Mask: 0x01)                         */
44718  #define R_ADC_B0_ADPGAMONCR_MONSEL1_Pos       (17UL)         /*!< MONSEL1 (Bit 17)                                      */
44719  #define R_ADC_B0_ADPGAMONCR_MONSEL1_Msk       (0x20000UL)    /*!< MONSEL1 (Bitfield-Mask: 0x01)                         */
44720  #define R_ADC_B0_ADPGAMONCR_MONSEL2_Pos       (18UL)         /*!< MONSEL2 (Bit 18)                                      */
44721  #define R_ADC_B0_ADPGAMONCR_MONSEL2_Msk       (0x40000UL)    /*!< MONSEL2 (Bitfield-Mask: 0x01)                         */
44722  #define R_ADC_B0_ADPGAMONCR_MONSEL3_Pos       (19UL)         /*!< MONSEL3 (Bit 19)                                      */
44723  #define R_ADC_B0_ADPGAMONCR_MONSEL3_Msk       (0x80000UL)    /*!< MONSEL3 (Bitfield-Mask: 0x01)                         */
44724 /* ========================================================  ADREFCR  ======================================================== */
44725  #define R_ADC_B0_ADREFCR_VDE_Pos              (0UL)          /*!< VDE (Bit 0)                                           */
44726  #define R_ADC_B0_ADREFCR_VDE_Msk              (0x1UL)        /*!< VDE (Bitfield-Mask: 0x01)                             */
44727 /* =======================================================  ADUOFTR0  ======================================================== */
44728  #define R_ADC_B0_ADUOFTR0_UOFSET_Pos          (0UL)          /*!< UOFSET (Bit 0)                                        */
44729  #define R_ADC_B0_ADUOFTR0_UOFSET_Msk          (0xffffUL)     /*!< UOFSET (Bitfield-Mask: 0xffff)                        */
44730 /* =======================================================  ADUOFTR1  ======================================================== */
44731  #define R_ADC_B0_ADUOFTR1_UOFSET_Pos          (0UL)          /*!< UOFSET (Bit 0)                                        */
44732  #define R_ADC_B0_ADUOFTR1_UOFSET_Msk          (0xffffUL)     /*!< UOFSET (Bitfield-Mask: 0xffff)                        */
44733 /* =======================================================  ADUOFTR2  ======================================================== */
44734  #define R_ADC_B0_ADUOFTR2_UOFSET_Pos          (0UL)          /*!< UOFSET (Bit 0)                                        */
44735  #define R_ADC_B0_ADUOFTR2_UOFSET_Msk          (0xffffUL)     /*!< UOFSET (Bitfield-Mask: 0xffff)                        */
44736 /* =======================================================  ADUOFTR3  ======================================================== */
44737  #define R_ADC_B0_ADUOFTR3_UOFSET_Pos          (0UL)          /*!< UOFSET (Bit 0)                                        */
44738  #define R_ADC_B0_ADUOFTR3_UOFSET_Msk          (0xffffUL)     /*!< UOFSET (Bitfield-Mask: 0xffff)                        */
44739 /* =======================================================  ADUOFTR4  ======================================================== */
44740  #define R_ADC_B0_ADUOFTR4_UOFSET_Pos          (0UL)          /*!< UOFSET (Bit 0)                                        */
44741  #define R_ADC_B0_ADUOFTR4_UOFSET_Msk          (0xffffUL)     /*!< UOFSET (Bitfield-Mask: 0xffff)                        */
44742 /* =======================================================  ADUOFTR5  ======================================================== */
44743  #define R_ADC_B0_ADUOFTR5_UOFSET_Pos          (0UL)          /*!< UOFSET (Bit 0)                                        */
44744  #define R_ADC_B0_ADUOFTR5_UOFSET_Msk          (0xffffUL)     /*!< UOFSET (Bitfield-Mask: 0xffff)                        */
44745 /* =======================================================  ADUOFTR6  ======================================================== */
44746  #define R_ADC_B0_ADUOFTR6_UOFSET_Pos          (0UL)          /*!< UOFSET (Bit 0)                                        */
44747  #define R_ADC_B0_ADUOFTR6_UOFSET_Msk          (0xffffUL)     /*!< UOFSET (Bitfield-Mask: 0xffff)                        */
44748 /* =======================================================  ADUOFTR7  ======================================================== */
44749  #define R_ADC_B0_ADUOFTR7_UOFSET_Pos          (0UL)          /*!< UOFSET (Bit 0)                                        */
44750  #define R_ADC_B0_ADUOFTR7_UOFSET_Msk          (0xffffUL)     /*!< UOFSET (Bitfield-Mask: 0xffff)                        */
44751 /* ========================================================  ADUGTR0  ======================================================== */
44752  #define R_ADC_B0_ADUGTR0_UGAIN_Pos            (0UL)          /*!< UGAIN (Bit 0)                                         */
44753  #define R_ADC_B0_ADUGTR0_UGAIN_Msk            (0xffffffUL)   /*!< UGAIN (Bitfield-Mask: 0xffffff)                       */
44754 /* ========================================================  ADUGTR1  ======================================================== */
44755  #define R_ADC_B0_ADUGTR1_UGAIN_Pos            (0UL)          /*!< UGAIN (Bit 0)                                         */
44756  #define R_ADC_B0_ADUGTR1_UGAIN_Msk            (0xffffffUL)   /*!< UGAIN (Bitfield-Mask: 0xffffff)                       */
44757 /* ========================================================  ADUGTR2  ======================================================== */
44758  #define R_ADC_B0_ADUGTR2_UGAIN_Pos            (0UL)          /*!< UGAIN (Bit 0)                                         */
44759  #define R_ADC_B0_ADUGTR2_UGAIN_Msk            (0xffffffUL)   /*!< UGAIN (Bitfield-Mask: 0xffffff)                       */
44760 /* ========================================================  ADUGTR3  ======================================================== */
44761  #define R_ADC_B0_ADUGTR3_UGAIN_Pos            (0UL)          /*!< UGAIN (Bit 0)                                         */
44762  #define R_ADC_B0_ADUGTR3_UGAIN_Msk            (0xffffffUL)   /*!< UGAIN (Bitfield-Mask: 0xffffff)                       */
44763 /* ========================================================  ADUGTR4  ======================================================== */
44764  #define R_ADC_B0_ADUGTR4_UGAIN_Pos            (0UL)          /*!< UGAIN (Bit 0)                                         */
44765  #define R_ADC_B0_ADUGTR4_UGAIN_Msk            (0xffffffUL)   /*!< UGAIN (Bitfield-Mask: 0xffffff)                       */
44766 /* ========================================================  ADUGTR5  ======================================================== */
44767  #define R_ADC_B0_ADUGTR5_UGAIN_Pos            (0UL)          /*!< UGAIN (Bit 0)                                         */
44768  #define R_ADC_B0_ADUGTR5_UGAIN_Msk            (0xffffffUL)   /*!< UGAIN (Bitfield-Mask: 0xffffff)                       */
44769 /* ========================================================  ADUGTR6  ======================================================== */
44770  #define R_ADC_B0_ADUGTR6_UGAIN_Pos            (0UL)          /*!< UGAIN (Bit 0)                                         */
44771  #define R_ADC_B0_ADUGTR6_UGAIN_Msk            (0xffffffUL)   /*!< UGAIN (Bitfield-Mask: 0xffffff)                       */
44772 /* ========================================================  ADUGTR7  ======================================================== */
44773  #define R_ADC_B0_ADUGTR7_UGAIN_Pos            (0UL)          /*!< UGAIN (Bit 0)                                         */
44774  #define R_ADC_B0_ADUGTR7_UGAIN_Msk            (0xffffffUL)   /*!< UGAIN (Bitfield-Mask: 0xffffff)                       */
44775 /* ======================================================  ADLIMINTCR  ======================================================= */
44776  #define R_ADC_B0_ADLIMINTCR_LIMIEn_Pos        (0UL)          /*!< LIMIEn (Bit 0)                                        */
44777  #define R_ADC_B0_ADLIMINTCR_LIMIEn_Msk        (0x1ffUL)      /*!< LIMIEn (Bitfield-Mask: 0x1ff)                         */
44778 /* =======================================================  ADLIMTR0  ======================================================== */
44779  #define R_ADC_B0_ADLIMTR0_LIML_Pos            (0UL)          /*!< LIML (Bit 0)                                          */
44780  #define R_ADC_B0_ADLIMTR0_LIML_Msk            (0xffffUL)     /*!< LIML (Bitfield-Mask: 0xffff)                          */
44781  #define R_ADC_B0_ADLIMTR0_LIMU_Pos            (16UL)         /*!< LIMU (Bit 16)                                         */
44782  #define R_ADC_B0_ADLIMTR0_LIMU_Msk            (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff)                          */
44783 /* =======================================================  ADLIMTR1  ======================================================== */
44784  #define R_ADC_B0_ADLIMTR1_LIML_Pos            (0UL)          /*!< LIML (Bit 0)                                          */
44785  #define R_ADC_B0_ADLIMTR1_LIML_Msk            (0xffffUL)     /*!< LIML (Bitfield-Mask: 0xffff)                          */
44786  #define R_ADC_B0_ADLIMTR1_LIMU_Pos            (16UL)         /*!< LIMU (Bit 16)                                         */
44787  #define R_ADC_B0_ADLIMTR1_LIMU_Msk            (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff)                          */
44788 /* =======================================================  ADLIMTR2  ======================================================== */
44789  #define R_ADC_B0_ADLIMTR2_LIML_Pos            (0UL)          /*!< LIML (Bit 0)                                          */
44790  #define R_ADC_B0_ADLIMTR2_LIML_Msk            (0xffffUL)     /*!< LIML (Bitfield-Mask: 0xffff)                          */
44791  #define R_ADC_B0_ADLIMTR2_LIMU_Pos            (16UL)         /*!< LIMU (Bit 16)                                         */
44792  #define R_ADC_B0_ADLIMTR2_LIMU_Msk            (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff)                          */
44793 /* =======================================================  ADLIMTR3  ======================================================== */
44794  #define R_ADC_B0_ADLIMTR3_LIML_Pos            (0UL)          /*!< LIML (Bit 0)                                          */
44795  #define R_ADC_B0_ADLIMTR3_LIML_Msk            (0xffffUL)     /*!< LIML (Bitfield-Mask: 0xffff)                          */
44796  #define R_ADC_B0_ADLIMTR3_LIMU_Pos            (16UL)         /*!< LIMU (Bit 16)                                         */
44797  #define R_ADC_B0_ADLIMTR3_LIMU_Msk            (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff)                          */
44798 /* =======================================================  ADLIMTR4  ======================================================== */
44799  #define R_ADC_B0_ADLIMTR4_LIML_Pos            (0UL)          /*!< LIML (Bit 0)                                          */
44800  #define R_ADC_B0_ADLIMTR4_LIML_Msk            (0xffffUL)     /*!< LIML (Bitfield-Mask: 0xffff)                          */
44801  #define R_ADC_B0_ADLIMTR4_LIMU_Pos            (16UL)         /*!< LIMU (Bit 16)                                         */
44802  #define R_ADC_B0_ADLIMTR4_LIMU_Msk            (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff)                          */
44803 /* =======================================================  ADLIMTR5  ======================================================== */
44804  #define R_ADC_B0_ADLIMTR5_LIML_Pos            (0UL)          /*!< LIML (Bit 0)                                          */
44805  #define R_ADC_B0_ADLIMTR5_LIML_Msk            (0xffffUL)     /*!< LIML (Bitfield-Mask: 0xffff)                          */
44806  #define R_ADC_B0_ADLIMTR5_LIMU_Pos            (16UL)         /*!< LIMU (Bit 16)                                         */
44807  #define R_ADC_B0_ADLIMTR5_LIMU_Msk            (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff)                          */
44808 /* =======================================================  ADLIMTR6  ======================================================== */
44809  #define R_ADC_B0_ADLIMTR6_LIML_Pos            (0UL)          /*!< LIML (Bit 0)                                          */
44810  #define R_ADC_B0_ADLIMTR6_LIML_Msk            (0xffffUL)     /*!< LIML (Bitfield-Mask: 0xffff)                          */
44811  #define R_ADC_B0_ADLIMTR6_LIMU_Pos            (16UL)         /*!< LIMU (Bit 16)                                         */
44812  #define R_ADC_B0_ADLIMTR6_LIMU_Msk            (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff)                          */
44813 /* =======================================================  ADLIMTR7  ======================================================== */
44814  #define R_ADC_B0_ADLIMTR7_LIML_Pos            (0UL)          /*!< LIML (Bit 0)                                          */
44815  #define R_ADC_B0_ADLIMTR7_LIML_Msk            (0xffffUL)     /*!< LIML (Bitfield-Mask: 0xffff)                          */
44816  #define R_ADC_B0_ADLIMTR7_LIMU_Pos            (16UL)         /*!< LIMU (Bit 16)                                         */
44817  #define R_ADC_B0_ADLIMTR7_LIMU_Msk            (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff)                          */
44818 /* =======================================================  ADCMPENR  ======================================================== */
44819  #define R_ADC_B0_ADCMPENR_CMPENn_Pos          (0UL)          /*!< CMPENn (Bit 0)                                        */
44820  #define R_ADC_B0_ADCMPENR_CMPENn_Msk          (0xffUL)       /*!< CMPENn (Bitfield-Mask: 0xff)                          */
44821 /* ======================================================  ADCMPINTCR  ======================================================= */
44822  #define R_ADC_B0_ADCMPINTCR_CMPIEn_Pos        (0UL)          /*!< CMPIEn (Bit 0)                                        */
44823  #define R_ADC_B0_ADCMPINTCR_CMPIEn_Msk        (0xfUL)        /*!< CMPIEn (Bitfield-Mask: 0x0f)                          */
44824 /* =======================================================  ADCCMPCR0  ======================================================= */
44825  #define R_ADC_B0_ADCCMPCR0_CCMPCND_Pos        (0UL)          /*!< CCMPCND (Bit 0)                                       */
44826  #define R_ADC_B0_ADCCMPCR0_CCMPCND_Msk        (0x3UL)        /*!< CCMPCND (Bitfield-Mask: 0x03)                         */
44827  #define R_ADC_B0_ADCCMPCR0_CCMPTBLm_Pos       (16UL)         /*!< CCMPTBLm (Bit 16)                                     */
44828  #define R_ADC_B0_ADCCMPCR0_CCMPTBLm_Msk       (0xff0000UL)   /*!< CCMPTBLm (Bitfield-Mask: 0xff)                        */
44829 /* =======================================================  ADCCMPCR1  ======================================================= */
44830  #define R_ADC_B0_ADCCMPCR1_CCMPCND_Pos        (0UL)          /*!< CCMPCND (Bit 0)                                       */
44831  #define R_ADC_B0_ADCCMPCR1_CCMPCND_Msk        (0x3UL)        /*!< CCMPCND (Bitfield-Mask: 0x03)                         */
44832  #define R_ADC_B0_ADCCMPCR1_CCMPTBLm_Pos       (16UL)         /*!< CCMPTBLm (Bit 16)                                     */
44833  #define R_ADC_B0_ADCCMPCR1_CCMPTBLm_Msk       (0xff0000UL)   /*!< CCMPTBLm (Bitfield-Mask: 0xff)                        */
44834 /* =======================================================  ADCMPMDR0  ======================================================= */
44835  #define R_ADC_B0_ADCMPMDR0_CMPMD0_Pos         (0UL)          /*!< CMPMD0 (Bit 0)                                        */
44836  #define R_ADC_B0_ADCMPMDR0_CMPMD0_Msk         (0x3UL)        /*!< CMPMD0 (Bitfield-Mask: 0x03)                          */
44837  #define R_ADC_B0_ADCMPMDR0_CMPMD1_Pos         (8UL)          /*!< CMPMD1 (Bit 8)                                        */
44838  #define R_ADC_B0_ADCMPMDR0_CMPMD1_Msk         (0x300UL)      /*!< CMPMD1 (Bitfield-Mask: 0x03)                          */
44839  #define R_ADC_B0_ADCMPMDR0_CMPMD2_Pos         (16UL)         /*!< CMPMD2 (Bit 16)                                       */
44840  #define R_ADC_B0_ADCMPMDR0_CMPMD2_Msk         (0x30000UL)    /*!< CMPMD2 (Bitfield-Mask: 0x03)                          */
44841  #define R_ADC_B0_ADCMPMDR0_CMPMD3_Pos         (24UL)         /*!< CMPMD3 (Bit 24)                                       */
44842  #define R_ADC_B0_ADCMPMDR0_CMPMD3_Msk         (0x3000000UL)  /*!< CMPMD3 (Bitfield-Mask: 0x03)                          */
44843 /* =======================================================  ADCMPMDR1  ======================================================= */
44844  #define R_ADC_B0_ADCMPMDR1_CMPMD4_Pos         (0UL)          /*!< CMPMD4 (Bit 0)                                        */
44845  #define R_ADC_B0_ADCMPMDR1_CMPMD4_Msk         (0x3UL)        /*!< CMPMD4 (Bitfield-Mask: 0x03)                          */
44846  #define R_ADC_B0_ADCMPMDR1_CMPMD5_Pos         (8UL)          /*!< CMPMD5 (Bit 8)                                        */
44847  #define R_ADC_B0_ADCMPMDR1_CMPMD5_Msk         (0x300UL)      /*!< CMPMD5 (Bitfield-Mask: 0x03)                          */
44848  #define R_ADC_B0_ADCMPMDR1_CMPMD6_Pos         (16UL)         /*!< CMPMD6 (Bit 16)                                       */
44849  #define R_ADC_B0_ADCMPMDR1_CMPMD6_Msk         (0x30000UL)    /*!< CMPMD6 (Bitfield-Mask: 0x03)                          */
44850  #define R_ADC_B0_ADCMPMDR1_CMPMD7_Pos         (24UL)         /*!< CMPMD7 (Bit 24)                                       */
44851  #define R_ADC_B0_ADCMPMDR1_CMPMD7_Msk         (0x3000000UL)  /*!< CMPMD7 (Bitfield-Mask: 0x03)                          */
44852 /* =======================================================  ADCMPTBR0  ======================================================= */
44853  #define R_ADC_B0_ADCMPTBR0_CMPTBL_Pos         (0UL)          /*!< CMPTBL (Bit 0)                                        */
44854  #define R_ADC_B0_ADCMPTBR0_CMPTBL_Msk         (0xffffUL)     /*!< CMPTBL (Bitfield-Mask: 0xffff)                        */
44855  #define R_ADC_B0_ADCMPTBR0_CMPTBH_Pos         (16UL)         /*!< CMPTBH (Bit 16)                                       */
44856  #define R_ADC_B0_ADCMPTBR0_CMPTBH_Msk         (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff)                        */
44857 /* =======================================================  ADCMPTBR1  ======================================================= */
44858  #define R_ADC_B0_ADCMPTBR1_CMPTBL_Pos         (0UL)          /*!< CMPTBL (Bit 0)                                        */
44859  #define R_ADC_B0_ADCMPTBR1_CMPTBL_Msk         (0xffffUL)     /*!< CMPTBL (Bitfield-Mask: 0xffff)                        */
44860  #define R_ADC_B0_ADCMPTBR1_CMPTBH_Pos         (16UL)         /*!< CMPTBH (Bit 16)                                       */
44861  #define R_ADC_B0_ADCMPTBR1_CMPTBH_Msk         (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff)                        */
44862 /* =======================================================  ADCMPTBR2  ======================================================= */
44863  #define R_ADC_B0_ADCMPTBR2_CMPTBL_Pos         (0UL)          /*!< CMPTBL (Bit 0)                                        */
44864  #define R_ADC_B0_ADCMPTBR2_CMPTBL_Msk         (0xffffUL)     /*!< CMPTBL (Bitfield-Mask: 0xffff)                        */
44865  #define R_ADC_B0_ADCMPTBR2_CMPTBH_Pos         (16UL)         /*!< CMPTBH (Bit 16)                                       */
44866  #define R_ADC_B0_ADCMPTBR2_CMPTBH_Msk         (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff)                        */
44867 /* =======================================================  ADCMPTBR3  ======================================================= */
44868  #define R_ADC_B0_ADCMPTBR3_CMPTBL_Pos         (0UL)          /*!< CMPTBL (Bit 0)                                        */
44869  #define R_ADC_B0_ADCMPTBR3_CMPTBL_Msk         (0xffffUL)     /*!< CMPTBL (Bitfield-Mask: 0xffff)                        */
44870  #define R_ADC_B0_ADCMPTBR3_CMPTBH_Pos         (16UL)         /*!< CMPTBH (Bit 16)                                       */
44871  #define R_ADC_B0_ADCMPTBR3_CMPTBH_Msk         (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff)                        */
44872 /* =======================================================  ADCMPTBR4  ======================================================= */
44873  #define R_ADC_B0_ADCMPTBR4_CMPTBL_Pos         (0UL)          /*!< CMPTBL (Bit 0)                                        */
44874  #define R_ADC_B0_ADCMPTBR4_CMPTBL_Msk         (0xffffUL)     /*!< CMPTBL (Bitfield-Mask: 0xffff)                        */
44875  #define R_ADC_B0_ADCMPTBR4_CMPTBH_Pos         (16UL)         /*!< CMPTBH (Bit 16)                                       */
44876  #define R_ADC_B0_ADCMPTBR4_CMPTBH_Msk         (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff)                        */
44877 /* =======================================================  ADCMPTBR5  ======================================================= */
44878  #define R_ADC_B0_ADCMPTBR5_CMPTBL_Pos         (0UL)          /*!< CMPTBL (Bit 0)                                        */
44879  #define R_ADC_B0_ADCMPTBR5_CMPTBL_Msk         (0xffffUL)     /*!< CMPTBL (Bitfield-Mask: 0xffff)                        */
44880  #define R_ADC_B0_ADCMPTBR5_CMPTBH_Pos         (16UL)         /*!< CMPTBH (Bit 16)                                       */
44881  #define R_ADC_B0_ADCMPTBR5_CMPTBH_Msk         (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff)                        */
44882 /* =======================================================  ADCMPTBR6  ======================================================= */
44883  #define R_ADC_B0_ADCMPTBR6_CMPTBL_Pos         (0UL)          /*!< CMPTBL (Bit 0)                                        */
44884  #define R_ADC_B0_ADCMPTBR6_CMPTBL_Msk         (0xffffUL)     /*!< CMPTBL (Bitfield-Mask: 0xffff)                        */
44885  #define R_ADC_B0_ADCMPTBR6_CMPTBH_Pos         (16UL)         /*!< CMPTBH (Bit 16)                                       */
44886  #define R_ADC_B0_ADCMPTBR6_CMPTBH_Msk         (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff)                        */
44887 /* =======================================================  ADCMPTBR7  ======================================================= */
44888  #define R_ADC_B0_ADCMPTBR7_CMPTBL_Pos         (0UL)          /*!< CMPTBL (Bit 0)                                        */
44889  #define R_ADC_B0_ADCMPTBR7_CMPTBL_Msk         (0xffffUL)     /*!< CMPTBL (Bitfield-Mask: 0xffff)                        */
44890  #define R_ADC_B0_ADCMPTBR7_CMPTBH_Pos         (16UL)         /*!< CMPTBH (Bit 16)                                       */
44891  #define R_ADC_B0_ADCMPTBR7_CMPTBH_Msk         (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff)                        */
44892 /* =======================================================  ADFIFOCR  ======================================================== */
44893  #define R_ADC_B0_ADFIFOCR_FIFOEN0_Pos         (0UL)          /*!< FIFOEN0 (Bit 0)                                       */
44894  #define R_ADC_B0_ADFIFOCR_FIFOEN0_Msk         (0x1UL)        /*!< FIFOEN0 (Bitfield-Mask: 0x01)                         */
44895  #define R_ADC_B0_ADFIFOCR_FIFOEN1_Pos         (1UL)          /*!< FIFOEN1 (Bit 1)                                       */
44896  #define R_ADC_B0_ADFIFOCR_FIFOEN1_Msk         (0x2UL)        /*!< FIFOEN1 (Bitfield-Mask: 0x01)                         */
44897  #define R_ADC_B0_ADFIFOCR_FIFOEN2_Pos         (2UL)          /*!< FIFOEN2 (Bit 2)                                       */
44898  #define R_ADC_B0_ADFIFOCR_FIFOEN2_Msk         (0x4UL)        /*!< FIFOEN2 (Bitfield-Mask: 0x01)                         */
44899  #define R_ADC_B0_ADFIFOCR_FIFOEN3_Pos         (3UL)          /*!< FIFOEN3 (Bit 3)                                       */
44900  #define R_ADC_B0_ADFIFOCR_FIFOEN3_Msk         (0x8UL)        /*!< FIFOEN3 (Bitfield-Mask: 0x01)                         */
44901  #define R_ADC_B0_ADFIFOCR_FIFOEN4_Pos         (4UL)          /*!< FIFOEN4 (Bit 4)                                       */
44902  #define R_ADC_B0_ADFIFOCR_FIFOEN4_Msk         (0x10UL)       /*!< FIFOEN4 (Bitfield-Mask: 0x01)                         */
44903  #define R_ADC_B0_ADFIFOCR_FIFOEN5_Pos         (5UL)          /*!< FIFOEN5 (Bit 5)                                       */
44904  #define R_ADC_B0_ADFIFOCR_FIFOEN5_Msk         (0x20UL)       /*!< FIFOEN5 (Bitfield-Mask: 0x01)                         */
44905  #define R_ADC_B0_ADFIFOCR_FIFOEN6_Pos         (6UL)          /*!< FIFOEN6 (Bit 6)                                       */
44906  #define R_ADC_B0_ADFIFOCR_FIFOEN6_Msk         (0x40UL)       /*!< FIFOEN6 (Bitfield-Mask: 0x01)                         */
44907  #define R_ADC_B0_ADFIFOCR_FIFOEN7_Pos         (7UL)          /*!< FIFOEN7 (Bit 7)                                       */
44908  #define R_ADC_B0_ADFIFOCR_FIFOEN7_Msk         (0x80UL)       /*!< FIFOEN7 (Bitfield-Mask: 0x01)                         */
44909  #define R_ADC_B0_ADFIFOCR_FIFOEN8_Pos         (8UL)          /*!< FIFOEN8 (Bit 8)                                       */
44910  #define R_ADC_B0_ADFIFOCR_FIFOEN8_Msk         (0x100UL)      /*!< FIFOEN8 (Bitfield-Mask: 0x01)                         */
44911 /* ======================================================  ADFIFOINTCR  ====================================================== */
44912  #define R_ADC_B0_ADFIFOINTCR_FIFOIE0_Pos      (0UL)          /*!< FIFOIE0 (Bit 0)                                       */
44913  #define R_ADC_B0_ADFIFOINTCR_FIFOIE0_Msk      (0x1UL)        /*!< FIFOIE0 (Bitfield-Mask: 0x01)                         */
44914  #define R_ADC_B0_ADFIFOINTCR_FIFOIE1_Pos      (1UL)          /*!< FIFOIE1 (Bit 1)                                       */
44915  #define R_ADC_B0_ADFIFOINTCR_FIFOIE1_Msk      (0x2UL)        /*!< FIFOIE1 (Bitfield-Mask: 0x01)                         */
44916  #define R_ADC_B0_ADFIFOINTCR_FIFOIE2_Pos      (2UL)          /*!< FIFOIE2 (Bit 2)                                       */
44917  #define R_ADC_B0_ADFIFOINTCR_FIFOIE2_Msk      (0x4UL)        /*!< FIFOIE2 (Bitfield-Mask: 0x01)                         */
44918  #define R_ADC_B0_ADFIFOINTCR_FIFOIE3_Pos      (3UL)          /*!< FIFOIE3 (Bit 3)                                       */
44919  #define R_ADC_B0_ADFIFOINTCR_FIFOIE3_Msk      (0x8UL)        /*!< FIFOIE3 (Bitfield-Mask: 0x01)                         */
44920  #define R_ADC_B0_ADFIFOINTCR_FIFOIE4_Pos      (4UL)          /*!< FIFOIE4 (Bit 4)                                       */
44921  #define R_ADC_B0_ADFIFOINTCR_FIFOIE4_Msk      (0x10UL)       /*!< FIFOIE4 (Bitfield-Mask: 0x01)                         */
44922  #define R_ADC_B0_ADFIFOINTCR_FIFOIE5_Pos      (5UL)          /*!< FIFOIE5 (Bit 5)                                       */
44923  #define R_ADC_B0_ADFIFOINTCR_FIFOIE5_Msk      (0x20UL)       /*!< FIFOIE5 (Bitfield-Mask: 0x01)                         */
44924  #define R_ADC_B0_ADFIFOINTCR_FIFOIE6_Pos      (6UL)          /*!< FIFOIE6 (Bit 6)                                       */
44925  #define R_ADC_B0_ADFIFOINTCR_FIFOIE6_Msk      (0x40UL)       /*!< FIFOIE6 (Bitfield-Mask: 0x01)                         */
44926  #define R_ADC_B0_ADFIFOINTCR_FIFOIE7_Pos      (7UL)          /*!< FIFOIE7 (Bit 7)                                       */
44927  #define R_ADC_B0_ADFIFOINTCR_FIFOIE7_Msk      (0x80UL)       /*!< FIFOIE7 (Bitfield-Mask: 0x01)                         */
44928  #define R_ADC_B0_ADFIFOINTCR_FIFOIE8_Pos      (8UL)          /*!< FIFOIE8 (Bit 8)                                       */
44929  #define R_ADC_B0_ADFIFOINTCR_FIFOIE8_Msk      (0x100UL)      /*!< FIFOIE8 (Bitfield-Mask: 0x01)                         */
44930 /* =====================================================  ADFIFOINTLR0  ====================================================== */
44931  #define R_ADC_B0_ADFIFOINTLR0_FIFOILV0_Pos    (0UL)          /*!< FIFOILV0 (Bit 0)                                      */
44932  #define R_ADC_B0_ADFIFOINTLR0_FIFOILV0_Msk    (0xfUL)        /*!< FIFOILV0 (Bitfield-Mask: 0x0f)                        */
44933  #define R_ADC_B0_ADFIFOINTLR0_FIFOILV1_Pos    (16UL)         /*!< FIFOILV1 (Bit 16)                                     */
44934  #define R_ADC_B0_ADFIFOINTLR0_FIFOILV1_Msk    (0xf0000UL)    /*!< FIFOILV1 (Bitfield-Mask: 0x0f)                        */
44935 /* =====================================================  ADFIFOINTLR1  ====================================================== */
44936  #define R_ADC_B0_ADFIFOINTLR1_FIFOILV2_Pos    (0UL)          /*!< FIFOILV2 (Bit 0)                                      */
44937  #define R_ADC_B0_ADFIFOINTLR1_FIFOILV2_Msk    (0xfUL)        /*!< FIFOILV2 (Bitfield-Mask: 0x0f)                        */
44938  #define R_ADC_B0_ADFIFOINTLR1_FIFOILV3_Pos    (16UL)         /*!< FIFOILV3 (Bit 16)                                     */
44939  #define R_ADC_B0_ADFIFOINTLR1_FIFOILV3_Msk    (0xf0000UL)    /*!< FIFOILV3 (Bitfield-Mask: 0x0f)                        */
44940 /* =====================================================  ADFIFOINTLR2  ====================================================== */
44941  #define R_ADC_B0_ADFIFOINTLR2_FIFOILV4_Pos    (0UL)          /*!< FIFOILV4 (Bit 0)                                      */
44942  #define R_ADC_B0_ADFIFOINTLR2_FIFOILV4_Msk    (0xfUL)        /*!< FIFOILV4 (Bitfield-Mask: 0x0f)                        */
44943  #define R_ADC_B0_ADFIFOINTLR2_FIFOILV5_Pos    (16UL)         /*!< FIFOILV5 (Bit 16)                                     */
44944  #define R_ADC_B0_ADFIFOINTLR2_FIFOILV5_Msk    (0xf0000UL)    /*!< FIFOILV5 (Bitfield-Mask: 0x0f)                        */
44945 /* =====================================================  ADFIFOINTLR3  ====================================================== */
44946  #define R_ADC_B0_ADFIFOINTLR3_FIFOILV6_Pos    (0UL)          /*!< FIFOILV6 (Bit 0)                                      */
44947  #define R_ADC_B0_ADFIFOINTLR3_FIFOILV6_Msk    (0xfUL)        /*!< FIFOILV6 (Bitfield-Mask: 0x0f)                        */
44948  #define R_ADC_B0_ADFIFOINTLR3_FIFOILV7_Pos    (16UL)         /*!< FIFOILV7 (Bit 16)                                     */
44949  #define R_ADC_B0_ADFIFOINTLR3_FIFOILV7_Msk    (0xf0000UL)    /*!< FIFOILV7 (Bitfield-Mask: 0x0f)                        */
44950 /* =====================================================  ADFIFOINTLR4  ====================================================== */
44951  #define R_ADC_B0_ADFIFOINTLR4_FIFOILV8_Pos    (0UL)          /*!< FIFOILV8 (Bit 0)                                      */
44952  #define R_ADC_B0_ADFIFOINTLR4_FIFOILV8_Msk    (0xfUL)        /*!< FIFOILV8 (Bitfield-Mask: 0x0f)                        */
44953 /* ========================================================  ADCHCR0  ======================================================== */
44954  #define R_ADC_B0_ADCHCR0_SGSEL_Pos            (0UL)          /*!< SGSEL (Bit 0)                                         */
44955  #define R_ADC_B0_ADCHCR0_SGSEL_Msk            (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
44956  #define R_ADC_B0_ADCHCR0_CNVCS_Pos            (8UL)          /*!< CNVCS (Bit 8)                                         */
44957  #define R_ADC_B0_ADCHCR0_CNVCS_Msk            (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
44958  #define R_ADC_B0_ADCHCR0_AINMD_Pos            (15UL)         /*!< AINMD (Bit 15)                                        */
44959  #define R_ADC_B0_ADCHCR0_AINMD_Msk            (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
44960  #define R_ADC_B0_ADCHCR0_SSTSEL_Pos           (16UL)         /*!< SSTSEL (Bit 16)                                       */
44961  #define R_ADC_B0_ADCHCR0_SSTSEL_Msk           (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
44962 /* ========================================================  ADCHCR1  ======================================================== */
44963  #define R_ADC_B0_ADCHCR1_SGSEL_Pos            (0UL)          /*!< SGSEL (Bit 0)                                         */
44964  #define R_ADC_B0_ADCHCR1_SGSEL_Msk            (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
44965  #define R_ADC_B0_ADCHCR1_CNVCS_Pos            (8UL)          /*!< CNVCS (Bit 8)                                         */
44966  #define R_ADC_B0_ADCHCR1_CNVCS_Msk            (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
44967  #define R_ADC_B0_ADCHCR1_AINMD_Pos            (15UL)         /*!< AINMD (Bit 15)                                        */
44968  #define R_ADC_B0_ADCHCR1_AINMD_Msk            (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
44969  #define R_ADC_B0_ADCHCR1_SSTSEL_Pos           (16UL)         /*!< SSTSEL (Bit 16)                                       */
44970  #define R_ADC_B0_ADCHCR1_SSTSEL_Msk           (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
44971 /* ========================================================  ADCHCR2  ======================================================== */
44972  #define R_ADC_B0_ADCHCR2_SGSEL_Pos            (0UL)          /*!< SGSEL (Bit 0)                                         */
44973  #define R_ADC_B0_ADCHCR2_SGSEL_Msk            (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
44974  #define R_ADC_B0_ADCHCR2_CNVCS_Pos            (8UL)          /*!< CNVCS (Bit 8)                                         */
44975  #define R_ADC_B0_ADCHCR2_CNVCS_Msk            (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
44976  #define R_ADC_B0_ADCHCR2_AINMD_Pos            (15UL)         /*!< AINMD (Bit 15)                                        */
44977  #define R_ADC_B0_ADCHCR2_AINMD_Msk            (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
44978  #define R_ADC_B0_ADCHCR2_SSTSEL_Pos           (16UL)         /*!< SSTSEL (Bit 16)                                       */
44979  #define R_ADC_B0_ADCHCR2_SSTSEL_Msk           (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
44980 /* ========================================================  ADCHCR3  ======================================================== */
44981  #define R_ADC_B0_ADCHCR3_SGSEL_Pos            (0UL)          /*!< SGSEL (Bit 0)                                         */
44982  #define R_ADC_B0_ADCHCR3_SGSEL_Msk            (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
44983  #define R_ADC_B0_ADCHCR3_CNVCS_Pos            (8UL)          /*!< CNVCS (Bit 8)                                         */
44984  #define R_ADC_B0_ADCHCR3_CNVCS_Msk            (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
44985  #define R_ADC_B0_ADCHCR3_AINMD_Pos            (15UL)         /*!< AINMD (Bit 15)                                        */
44986  #define R_ADC_B0_ADCHCR3_AINMD_Msk            (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
44987  #define R_ADC_B0_ADCHCR3_SSTSEL_Pos           (16UL)         /*!< SSTSEL (Bit 16)                                       */
44988  #define R_ADC_B0_ADCHCR3_SSTSEL_Msk           (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
44989 /* ========================================================  ADCHCR4  ======================================================== */
44990  #define R_ADC_B0_ADCHCR4_SGSEL_Pos            (0UL)          /*!< SGSEL (Bit 0)                                         */
44991  #define R_ADC_B0_ADCHCR4_SGSEL_Msk            (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
44992  #define R_ADC_B0_ADCHCR4_CNVCS_Pos            (8UL)          /*!< CNVCS (Bit 8)                                         */
44993  #define R_ADC_B0_ADCHCR4_CNVCS_Msk            (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
44994  #define R_ADC_B0_ADCHCR4_AINMD_Pos            (15UL)         /*!< AINMD (Bit 15)                                        */
44995  #define R_ADC_B0_ADCHCR4_AINMD_Msk            (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
44996  #define R_ADC_B0_ADCHCR4_SSTSEL_Pos           (16UL)         /*!< SSTSEL (Bit 16)                                       */
44997  #define R_ADC_B0_ADCHCR4_SSTSEL_Msk           (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
44998 /* ========================================================  ADCHCR5  ======================================================== */
44999  #define R_ADC_B0_ADCHCR5_SGSEL_Pos            (0UL)          /*!< SGSEL (Bit 0)                                         */
45000  #define R_ADC_B0_ADCHCR5_SGSEL_Msk            (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45001  #define R_ADC_B0_ADCHCR5_CNVCS_Pos            (8UL)          /*!< CNVCS (Bit 8)                                         */
45002  #define R_ADC_B0_ADCHCR5_CNVCS_Msk            (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45003  #define R_ADC_B0_ADCHCR5_AINMD_Pos            (15UL)         /*!< AINMD (Bit 15)                                        */
45004  #define R_ADC_B0_ADCHCR5_AINMD_Msk            (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45005  #define R_ADC_B0_ADCHCR5_SSTSEL_Pos           (16UL)         /*!< SSTSEL (Bit 16)                                       */
45006  #define R_ADC_B0_ADCHCR5_SSTSEL_Msk           (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45007 /* ========================================================  ADCHCR6  ======================================================== */
45008  #define R_ADC_B0_ADCHCR6_SGSEL_Pos            (0UL)          /*!< SGSEL (Bit 0)                                         */
45009  #define R_ADC_B0_ADCHCR6_SGSEL_Msk            (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45010  #define R_ADC_B0_ADCHCR6_CNVCS_Pos            (8UL)          /*!< CNVCS (Bit 8)                                         */
45011  #define R_ADC_B0_ADCHCR6_CNVCS_Msk            (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45012  #define R_ADC_B0_ADCHCR6_AINMD_Pos            (15UL)         /*!< AINMD (Bit 15)                                        */
45013  #define R_ADC_B0_ADCHCR6_AINMD_Msk            (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45014  #define R_ADC_B0_ADCHCR6_SSTSEL_Pos           (16UL)         /*!< SSTSEL (Bit 16)                                       */
45015  #define R_ADC_B0_ADCHCR6_SSTSEL_Msk           (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45016 /* ========================================================  ADCHCR7  ======================================================== */
45017  #define R_ADC_B0_ADCHCR7_SGSEL_Pos            (0UL)          /*!< SGSEL (Bit 0)                                         */
45018  #define R_ADC_B0_ADCHCR7_SGSEL_Msk            (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45019  #define R_ADC_B0_ADCHCR7_CNVCS_Pos            (8UL)          /*!< CNVCS (Bit 8)                                         */
45020  #define R_ADC_B0_ADCHCR7_CNVCS_Msk            (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45021  #define R_ADC_B0_ADCHCR7_AINMD_Pos            (15UL)         /*!< AINMD (Bit 15)                                        */
45022  #define R_ADC_B0_ADCHCR7_AINMD_Msk            (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45023  #define R_ADC_B0_ADCHCR7_SSTSEL_Pos           (16UL)         /*!< SSTSEL (Bit 16)                                       */
45024  #define R_ADC_B0_ADCHCR7_SSTSEL_Msk           (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45025 /* ========================================================  ADCHCR8  ======================================================== */
45026  #define R_ADC_B0_ADCHCR8_SGSEL_Pos            (0UL)          /*!< SGSEL (Bit 0)                                         */
45027  #define R_ADC_B0_ADCHCR8_SGSEL_Msk            (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45028  #define R_ADC_B0_ADCHCR8_CNVCS_Pos            (8UL)          /*!< CNVCS (Bit 8)                                         */
45029  #define R_ADC_B0_ADCHCR8_CNVCS_Msk            (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45030  #define R_ADC_B0_ADCHCR8_AINMD_Pos            (15UL)         /*!< AINMD (Bit 15)                                        */
45031  #define R_ADC_B0_ADCHCR8_AINMD_Msk            (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45032  #define R_ADC_B0_ADCHCR8_SSTSEL_Pos           (16UL)         /*!< SSTSEL (Bit 16)                                       */
45033  #define R_ADC_B0_ADCHCR8_SSTSEL_Msk           (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45034 /* ========================================================  ADCHCR9  ======================================================== */
45035  #define R_ADC_B0_ADCHCR9_SGSEL_Pos            (0UL)          /*!< SGSEL (Bit 0)                                         */
45036  #define R_ADC_B0_ADCHCR9_SGSEL_Msk            (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45037  #define R_ADC_B0_ADCHCR9_CNVCS_Pos            (8UL)          /*!< CNVCS (Bit 8)                                         */
45038  #define R_ADC_B0_ADCHCR9_CNVCS_Msk            (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45039  #define R_ADC_B0_ADCHCR9_AINMD_Pos            (15UL)         /*!< AINMD (Bit 15)                                        */
45040  #define R_ADC_B0_ADCHCR9_AINMD_Msk            (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45041  #define R_ADC_B0_ADCHCR9_SSTSEL_Pos           (16UL)         /*!< SSTSEL (Bit 16)                                       */
45042  #define R_ADC_B0_ADCHCR9_SSTSEL_Msk           (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45043 /* =======================================================  ADCHCR10  ======================================================== */
45044  #define R_ADC_B0_ADCHCR10_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45045  #define R_ADC_B0_ADCHCR10_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45046  #define R_ADC_B0_ADCHCR10_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45047  #define R_ADC_B0_ADCHCR10_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45048  #define R_ADC_B0_ADCHCR10_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45049  #define R_ADC_B0_ADCHCR10_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45050  #define R_ADC_B0_ADCHCR10_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45051  #define R_ADC_B0_ADCHCR10_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45052 /* =======================================================  ADCHCR11  ======================================================== */
45053  #define R_ADC_B0_ADCHCR11_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45054  #define R_ADC_B0_ADCHCR11_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45055  #define R_ADC_B0_ADCHCR11_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45056  #define R_ADC_B0_ADCHCR11_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45057  #define R_ADC_B0_ADCHCR11_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45058  #define R_ADC_B0_ADCHCR11_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45059  #define R_ADC_B0_ADCHCR11_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45060  #define R_ADC_B0_ADCHCR11_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45061 /* =======================================================  ADCHCR12  ======================================================== */
45062  #define R_ADC_B0_ADCHCR12_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45063  #define R_ADC_B0_ADCHCR12_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45064  #define R_ADC_B0_ADCHCR12_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45065  #define R_ADC_B0_ADCHCR12_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45066  #define R_ADC_B0_ADCHCR12_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45067  #define R_ADC_B0_ADCHCR12_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45068  #define R_ADC_B0_ADCHCR12_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45069  #define R_ADC_B0_ADCHCR12_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45070 /* =======================================================  ADCHCR13  ======================================================== */
45071  #define R_ADC_B0_ADCHCR13_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45072  #define R_ADC_B0_ADCHCR13_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45073  #define R_ADC_B0_ADCHCR13_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45074  #define R_ADC_B0_ADCHCR13_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45075  #define R_ADC_B0_ADCHCR13_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45076  #define R_ADC_B0_ADCHCR13_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45077  #define R_ADC_B0_ADCHCR13_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45078  #define R_ADC_B0_ADCHCR13_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45079 /* =======================================================  ADCHCR14  ======================================================== */
45080  #define R_ADC_B0_ADCHCR14_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45081  #define R_ADC_B0_ADCHCR14_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45082  #define R_ADC_B0_ADCHCR14_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45083  #define R_ADC_B0_ADCHCR14_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45084  #define R_ADC_B0_ADCHCR14_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45085  #define R_ADC_B0_ADCHCR14_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45086  #define R_ADC_B0_ADCHCR14_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45087  #define R_ADC_B0_ADCHCR14_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45088 /* =======================================================  ADCHCR15  ======================================================== */
45089  #define R_ADC_B0_ADCHCR15_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45090  #define R_ADC_B0_ADCHCR15_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45091  #define R_ADC_B0_ADCHCR15_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45092  #define R_ADC_B0_ADCHCR15_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45093  #define R_ADC_B0_ADCHCR15_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45094  #define R_ADC_B0_ADCHCR15_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45095  #define R_ADC_B0_ADCHCR15_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45096  #define R_ADC_B0_ADCHCR15_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45097 /* =======================================================  ADCHCR16  ======================================================== */
45098  #define R_ADC_B0_ADCHCR16_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45099  #define R_ADC_B0_ADCHCR16_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45100  #define R_ADC_B0_ADCHCR16_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45101  #define R_ADC_B0_ADCHCR16_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45102  #define R_ADC_B0_ADCHCR16_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45103  #define R_ADC_B0_ADCHCR16_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45104  #define R_ADC_B0_ADCHCR16_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45105  #define R_ADC_B0_ADCHCR16_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45106 /* =======================================================  ADCHCR17  ======================================================== */
45107  #define R_ADC_B0_ADCHCR17_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45108  #define R_ADC_B0_ADCHCR17_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45109  #define R_ADC_B0_ADCHCR17_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45110  #define R_ADC_B0_ADCHCR17_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45111  #define R_ADC_B0_ADCHCR17_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45112  #define R_ADC_B0_ADCHCR17_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45113  #define R_ADC_B0_ADCHCR17_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45114  #define R_ADC_B0_ADCHCR17_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45115 /* =======================================================  ADCHCR18  ======================================================== */
45116  #define R_ADC_B0_ADCHCR18_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45117  #define R_ADC_B0_ADCHCR18_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45118  #define R_ADC_B0_ADCHCR18_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45119  #define R_ADC_B0_ADCHCR18_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45120  #define R_ADC_B0_ADCHCR18_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45121  #define R_ADC_B0_ADCHCR18_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45122  #define R_ADC_B0_ADCHCR18_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45123  #define R_ADC_B0_ADCHCR18_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45124 /* =======================================================  ADCHCR19  ======================================================== */
45125  #define R_ADC_B0_ADCHCR19_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45126  #define R_ADC_B0_ADCHCR19_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45127  #define R_ADC_B0_ADCHCR19_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45128  #define R_ADC_B0_ADCHCR19_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45129  #define R_ADC_B0_ADCHCR19_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45130  #define R_ADC_B0_ADCHCR19_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45131  #define R_ADC_B0_ADCHCR19_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45132  #define R_ADC_B0_ADCHCR19_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45133 /* =======================================================  ADCHCR20  ======================================================== */
45134  #define R_ADC_B0_ADCHCR20_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45135  #define R_ADC_B0_ADCHCR20_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45136  #define R_ADC_B0_ADCHCR20_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45137  #define R_ADC_B0_ADCHCR20_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45138  #define R_ADC_B0_ADCHCR20_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45139  #define R_ADC_B0_ADCHCR20_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45140  #define R_ADC_B0_ADCHCR20_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45141  #define R_ADC_B0_ADCHCR20_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45142 /* =======================================================  ADCHCR21  ======================================================== */
45143  #define R_ADC_B0_ADCHCR21_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45144  #define R_ADC_B0_ADCHCR21_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45145  #define R_ADC_B0_ADCHCR21_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45146  #define R_ADC_B0_ADCHCR21_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45147  #define R_ADC_B0_ADCHCR21_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45148  #define R_ADC_B0_ADCHCR21_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45149  #define R_ADC_B0_ADCHCR21_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45150  #define R_ADC_B0_ADCHCR21_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45151 /* =======================================================  ADCHCR22  ======================================================== */
45152  #define R_ADC_B0_ADCHCR22_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45153  #define R_ADC_B0_ADCHCR22_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45154  #define R_ADC_B0_ADCHCR22_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45155  #define R_ADC_B0_ADCHCR22_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45156  #define R_ADC_B0_ADCHCR22_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45157  #define R_ADC_B0_ADCHCR22_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45158  #define R_ADC_B0_ADCHCR22_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45159  #define R_ADC_B0_ADCHCR22_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45160 /* =======================================================  ADCHCR23  ======================================================== */
45161  #define R_ADC_B0_ADCHCR23_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45162  #define R_ADC_B0_ADCHCR23_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45163  #define R_ADC_B0_ADCHCR23_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45164  #define R_ADC_B0_ADCHCR23_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45165  #define R_ADC_B0_ADCHCR23_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45166  #define R_ADC_B0_ADCHCR23_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45167  #define R_ADC_B0_ADCHCR23_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45168  #define R_ADC_B0_ADCHCR23_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45169 /* =======================================================  ADCHCR24  ======================================================== */
45170  #define R_ADC_B0_ADCHCR24_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45171  #define R_ADC_B0_ADCHCR24_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45172  #define R_ADC_B0_ADCHCR24_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45173  #define R_ADC_B0_ADCHCR24_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45174  #define R_ADC_B0_ADCHCR24_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45175  #define R_ADC_B0_ADCHCR24_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45176  #define R_ADC_B0_ADCHCR24_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45177  #define R_ADC_B0_ADCHCR24_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45178 /* =======================================================  ADCHCR25  ======================================================== */
45179  #define R_ADC_B0_ADCHCR25_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45180  #define R_ADC_B0_ADCHCR25_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45181  #define R_ADC_B0_ADCHCR25_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45182  #define R_ADC_B0_ADCHCR25_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45183  #define R_ADC_B0_ADCHCR25_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45184  #define R_ADC_B0_ADCHCR25_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45185  #define R_ADC_B0_ADCHCR25_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45186  #define R_ADC_B0_ADCHCR25_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45187 /* =======================================================  ADCHCR26  ======================================================== */
45188  #define R_ADC_B0_ADCHCR26_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45189  #define R_ADC_B0_ADCHCR26_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45190  #define R_ADC_B0_ADCHCR26_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45191  #define R_ADC_B0_ADCHCR26_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45192  #define R_ADC_B0_ADCHCR26_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45193  #define R_ADC_B0_ADCHCR26_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45194  #define R_ADC_B0_ADCHCR26_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45195  #define R_ADC_B0_ADCHCR26_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45196 /* =======================================================  ADCHCR27  ======================================================== */
45197  #define R_ADC_B0_ADCHCR27_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45198  #define R_ADC_B0_ADCHCR27_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45199  #define R_ADC_B0_ADCHCR27_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45200  #define R_ADC_B0_ADCHCR27_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45201  #define R_ADC_B0_ADCHCR27_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45202  #define R_ADC_B0_ADCHCR27_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45203  #define R_ADC_B0_ADCHCR27_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45204  #define R_ADC_B0_ADCHCR27_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45205 /* =======================================================  ADCHCR28  ======================================================== */
45206  #define R_ADC_B0_ADCHCR28_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45207  #define R_ADC_B0_ADCHCR28_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45208  #define R_ADC_B0_ADCHCR28_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45209  #define R_ADC_B0_ADCHCR28_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45210  #define R_ADC_B0_ADCHCR28_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45211  #define R_ADC_B0_ADCHCR28_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45212  #define R_ADC_B0_ADCHCR28_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45213  #define R_ADC_B0_ADCHCR28_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45214 /* =======================================================  ADCHCR29  ======================================================== */
45215  #define R_ADC_B0_ADCHCR29_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45216  #define R_ADC_B0_ADCHCR29_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45217  #define R_ADC_B0_ADCHCR29_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45218  #define R_ADC_B0_ADCHCR29_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45219  #define R_ADC_B0_ADCHCR29_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45220  #define R_ADC_B0_ADCHCR29_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45221  #define R_ADC_B0_ADCHCR29_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45222  #define R_ADC_B0_ADCHCR29_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45223 /* =======================================================  ADCHCR30  ======================================================== */
45224  #define R_ADC_B0_ADCHCR30_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45225  #define R_ADC_B0_ADCHCR30_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45226  #define R_ADC_B0_ADCHCR30_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45227  #define R_ADC_B0_ADCHCR30_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45228  #define R_ADC_B0_ADCHCR30_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45229  #define R_ADC_B0_ADCHCR30_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45230  #define R_ADC_B0_ADCHCR30_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45231  #define R_ADC_B0_ADCHCR30_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45232 /* =======================================================  ADCHCR31  ======================================================== */
45233  #define R_ADC_B0_ADCHCR31_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45234  #define R_ADC_B0_ADCHCR31_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45235  #define R_ADC_B0_ADCHCR31_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45236  #define R_ADC_B0_ADCHCR31_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45237  #define R_ADC_B0_ADCHCR31_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45238  #define R_ADC_B0_ADCHCR31_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45239  #define R_ADC_B0_ADCHCR31_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45240  #define R_ADC_B0_ADCHCR31_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45241 /* =======================================================  ADCHCR32  ======================================================== */
45242  #define R_ADC_B0_ADCHCR32_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45243  #define R_ADC_B0_ADCHCR32_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45244  #define R_ADC_B0_ADCHCR32_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45245  #define R_ADC_B0_ADCHCR32_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45246  #define R_ADC_B0_ADCHCR32_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45247  #define R_ADC_B0_ADCHCR32_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45248  #define R_ADC_B0_ADCHCR32_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45249  #define R_ADC_B0_ADCHCR32_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45250 /* =======================================================  ADCHCR33  ======================================================== */
45251  #define R_ADC_B0_ADCHCR33_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45252  #define R_ADC_B0_ADCHCR33_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45253  #define R_ADC_B0_ADCHCR33_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45254  #define R_ADC_B0_ADCHCR33_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45255  #define R_ADC_B0_ADCHCR33_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45256  #define R_ADC_B0_ADCHCR33_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45257  #define R_ADC_B0_ADCHCR33_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45258  #define R_ADC_B0_ADCHCR33_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45259 /* =======================================================  ADCHCR34  ======================================================== */
45260  #define R_ADC_B0_ADCHCR34_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45261  #define R_ADC_B0_ADCHCR34_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45262  #define R_ADC_B0_ADCHCR34_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45263  #define R_ADC_B0_ADCHCR34_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45264  #define R_ADC_B0_ADCHCR34_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45265  #define R_ADC_B0_ADCHCR34_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45266  #define R_ADC_B0_ADCHCR34_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45267  #define R_ADC_B0_ADCHCR34_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45268 /* =======================================================  ADCHCR35  ======================================================== */
45269  #define R_ADC_B0_ADCHCR35_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45270  #define R_ADC_B0_ADCHCR35_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45271  #define R_ADC_B0_ADCHCR35_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45272  #define R_ADC_B0_ADCHCR35_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45273  #define R_ADC_B0_ADCHCR35_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45274  #define R_ADC_B0_ADCHCR35_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45275  #define R_ADC_B0_ADCHCR35_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45276  #define R_ADC_B0_ADCHCR35_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45277 /* =======================================================  ADCHCR36  ======================================================== */
45278  #define R_ADC_B0_ADCHCR36_SGSEL_Pos           (0UL)          /*!< SGSEL (Bit 0)                                         */
45279  #define R_ADC_B0_ADCHCR36_SGSEL_Msk           (0x1fUL)       /*!< SGSEL (Bitfield-Mask: 0x1f)                           */
45280  #define R_ADC_B0_ADCHCR36_CNVCS_Pos           (8UL)          /*!< CNVCS (Bit 8)                                         */
45281  #define R_ADC_B0_ADCHCR36_CNVCS_Msk           (0x7f00UL)     /*!< CNVCS (Bitfield-Mask: 0x7f)                           */
45282  #define R_ADC_B0_ADCHCR36_AINMD_Pos           (15UL)         /*!< AINMD (Bit 15)                                        */
45283  #define R_ADC_B0_ADCHCR36_AINMD_Msk           (0x8000UL)     /*!< AINMD (Bitfield-Mask: 0x01)                           */
45284  #define R_ADC_B0_ADCHCR36_SSTSEL_Pos          (16UL)         /*!< SSTSEL (Bit 16)                                       */
45285  #define R_ADC_B0_ADCHCR36_SSTSEL_Msk          (0xf0000UL)    /*!< SSTSEL (Bitfield-Mask: 0x0f)                          */
45286 /* =======================================================  ADDOPCRA0  ======================================================= */
45287  #define R_ADC_B0_ADDOPCRA0_GAINSEL_Pos        (16UL)         /*!< GAINSEL (Bit 16)                                      */
45288  #define R_ADC_B0_ADDOPCRA0_GAINSEL_Msk        (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45289  #define R_ADC_B0_ADDOPCRA0_OFSETSEL_Pos       (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45290  #define R_ADC_B0_ADDOPCRA0_OFSETSEL_Msk       (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45291 /* =======================================================  ADDOPCRA1  ======================================================= */
45292  #define R_ADC_B0_ADDOPCRA1_GAINSEL_Pos        (16UL)         /*!< GAINSEL (Bit 16)                                      */
45293  #define R_ADC_B0_ADDOPCRA1_GAINSEL_Msk        (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45294  #define R_ADC_B0_ADDOPCRA1_OFSETSEL_Pos       (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45295  #define R_ADC_B0_ADDOPCRA1_OFSETSEL_Msk       (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45296 /* =======================================================  ADDOPCRA2  ======================================================= */
45297  #define R_ADC_B0_ADDOPCRA2_GAINSEL_Pos        (16UL)         /*!< GAINSEL (Bit 16)                                      */
45298  #define R_ADC_B0_ADDOPCRA2_GAINSEL_Msk        (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45299  #define R_ADC_B0_ADDOPCRA2_OFSETSEL_Pos       (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45300  #define R_ADC_B0_ADDOPCRA2_OFSETSEL_Msk       (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45301 /* =======================================================  ADDOPCRA3  ======================================================= */
45302  #define R_ADC_B0_ADDOPCRA3_GAINSEL_Pos        (16UL)         /*!< GAINSEL (Bit 16)                                      */
45303  #define R_ADC_B0_ADDOPCRA3_GAINSEL_Msk        (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45304  #define R_ADC_B0_ADDOPCRA3_OFSETSEL_Pos       (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45305  #define R_ADC_B0_ADDOPCRA3_OFSETSEL_Msk       (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45306 /* =======================================================  ADDOPCRA4  ======================================================= */
45307  #define R_ADC_B0_ADDOPCRA4_GAINSEL_Pos        (16UL)         /*!< GAINSEL (Bit 16)                                      */
45308  #define R_ADC_B0_ADDOPCRA4_GAINSEL_Msk        (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45309  #define R_ADC_B0_ADDOPCRA4_OFSETSEL_Pos       (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45310  #define R_ADC_B0_ADDOPCRA4_OFSETSEL_Msk       (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45311 /* =======================================================  ADDOPCRA5  ======================================================= */
45312  #define R_ADC_B0_ADDOPCRA5_GAINSEL_Pos        (16UL)         /*!< GAINSEL (Bit 16)                                      */
45313  #define R_ADC_B0_ADDOPCRA5_GAINSEL_Msk        (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45314  #define R_ADC_B0_ADDOPCRA5_OFSETSEL_Pos       (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45315  #define R_ADC_B0_ADDOPCRA5_OFSETSEL_Msk       (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45316 /* =======================================================  ADDOPCRA6  ======================================================= */
45317  #define R_ADC_B0_ADDOPCRA6_GAINSEL_Pos        (16UL)         /*!< GAINSEL (Bit 16)                                      */
45318  #define R_ADC_B0_ADDOPCRA6_GAINSEL_Msk        (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45319  #define R_ADC_B0_ADDOPCRA6_OFSETSEL_Pos       (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45320  #define R_ADC_B0_ADDOPCRA6_OFSETSEL_Msk       (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45321 /* =======================================================  ADDOPCRA7  ======================================================= */
45322  #define R_ADC_B0_ADDOPCRA7_GAINSEL_Pos        (16UL)         /*!< GAINSEL (Bit 16)                                      */
45323  #define R_ADC_B0_ADDOPCRA7_GAINSEL_Msk        (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45324  #define R_ADC_B0_ADDOPCRA7_OFSETSEL_Pos       (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45325  #define R_ADC_B0_ADDOPCRA7_OFSETSEL_Msk       (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45326 /* =======================================================  ADDOPCRA8  ======================================================= */
45327  #define R_ADC_B0_ADDOPCRA8_GAINSEL_Pos        (16UL)         /*!< GAINSEL (Bit 16)                                      */
45328  #define R_ADC_B0_ADDOPCRA8_GAINSEL_Msk        (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45329  #define R_ADC_B0_ADDOPCRA8_OFSETSEL_Pos       (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45330  #define R_ADC_B0_ADDOPCRA8_OFSETSEL_Msk       (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45331 /* =======================================================  ADDOPCRA9  ======================================================= */
45332  #define R_ADC_B0_ADDOPCRA9_GAINSEL_Pos        (16UL)         /*!< GAINSEL (Bit 16)                                      */
45333  #define R_ADC_B0_ADDOPCRA9_GAINSEL_Msk        (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45334  #define R_ADC_B0_ADDOPCRA9_OFSETSEL_Pos       (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45335  #define R_ADC_B0_ADDOPCRA9_OFSETSEL_Msk       (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45336 /* ======================================================  ADDOPCRA10  ======================================================= */
45337  #define R_ADC_B0_ADDOPCRA10_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45338  #define R_ADC_B0_ADDOPCRA10_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45339  #define R_ADC_B0_ADDOPCRA10_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45340  #define R_ADC_B0_ADDOPCRA10_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45341 /* ======================================================  ADDOPCRA11  ======================================================= */
45342  #define R_ADC_B0_ADDOPCRA11_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45343  #define R_ADC_B0_ADDOPCRA11_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45344  #define R_ADC_B0_ADDOPCRA11_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45345  #define R_ADC_B0_ADDOPCRA11_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45346 /* ======================================================  ADDOPCRA12  ======================================================= */
45347  #define R_ADC_B0_ADDOPCRA12_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45348  #define R_ADC_B0_ADDOPCRA12_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45349  #define R_ADC_B0_ADDOPCRA12_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45350  #define R_ADC_B0_ADDOPCRA12_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45351 /* ======================================================  ADDOPCRA13  ======================================================= */
45352  #define R_ADC_B0_ADDOPCRA13_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45353  #define R_ADC_B0_ADDOPCRA13_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45354  #define R_ADC_B0_ADDOPCRA13_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45355  #define R_ADC_B0_ADDOPCRA13_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45356 /* ======================================================  ADDOPCRA14  ======================================================= */
45357  #define R_ADC_B0_ADDOPCRA14_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45358  #define R_ADC_B0_ADDOPCRA14_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45359  #define R_ADC_B0_ADDOPCRA14_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45360  #define R_ADC_B0_ADDOPCRA14_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45361 /* ======================================================  ADDOPCRA15  ======================================================= */
45362  #define R_ADC_B0_ADDOPCRA15_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45363  #define R_ADC_B0_ADDOPCRA15_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45364  #define R_ADC_B0_ADDOPCRA15_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45365  #define R_ADC_B0_ADDOPCRA15_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45366 /* ======================================================  ADDOPCRA16  ======================================================= */
45367  #define R_ADC_B0_ADDOPCRA16_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45368  #define R_ADC_B0_ADDOPCRA16_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45369  #define R_ADC_B0_ADDOPCRA16_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45370  #define R_ADC_B0_ADDOPCRA16_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45371 /* ======================================================  ADDOPCRA17  ======================================================= */
45372  #define R_ADC_B0_ADDOPCRA17_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45373  #define R_ADC_B0_ADDOPCRA17_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45374  #define R_ADC_B0_ADDOPCRA17_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45375  #define R_ADC_B0_ADDOPCRA17_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45376 /* ======================================================  ADDOPCRA18  ======================================================= */
45377  #define R_ADC_B0_ADDOPCRA18_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45378  #define R_ADC_B0_ADDOPCRA18_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45379  #define R_ADC_B0_ADDOPCRA18_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45380  #define R_ADC_B0_ADDOPCRA18_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45381 /* ======================================================  ADDOPCRA19  ======================================================= */
45382  #define R_ADC_B0_ADDOPCRA19_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45383  #define R_ADC_B0_ADDOPCRA19_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45384  #define R_ADC_B0_ADDOPCRA19_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45385  #define R_ADC_B0_ADDOPCRA19_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45386 /* ======================================================  ADDOPCRA20  ======================================================= */
45387  #define R_ADC_B0_ADDOPCRA20_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45388  #define R_ADC_B0_ADDOPCRA20_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45389  #define R_ADC_B0_ADDOPCRA20_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45390  #define R_ADC_B0_ADDOPCRA20_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45391 /* ======================================================  ADDOPCRA21  ======================================================= */
45392  #define R_ADC_B0_ADDOPCRA21_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45393  #define R_ADC_B0_ADDOPCRA21_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45394  #define R_ADC_B0_ADDOPCRA21_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45395  #define R_ADC_B0_ADDOPCRA21_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45396 /* ======================================================  ADDOPCRA22  ======================================================= */
45397  #define R_ADC_B0_ADDOPCRA22_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45398  #define R_ADC_B0_ADDOPCRA22_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45399  #define R_ADC_B0_ADDOPCRA22_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45400  #define R_ADC_B0_ADDOPCRA22_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45401 /* ======================================================  ADDOPCRA23  ======================================================= */
45402  #define R_ADC_B0_ADDOPCRA23_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45403  #define R_ADC_B0_ADDOPCRA23_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45404  #define R_ADC_B0_ADDOPCRA23_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45405  #define R_ADC_B0_ADDOPCRA23_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45406 /* ======================================================  ADDOPCRA24  ======================================================= */
45407  #define R_ADC_B0_ADDOPCRA24_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45408  #define R_ADC_B0_ADDOPCRA24_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45409  #define R_ADC_B0_ADDOPCRA24_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45410  #define R_ADC_B0_ADDOPCRA24_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45411 /* ======================================================  ADDOPCRA25  ======================================================= */
45412  #define R_ADC_B0_ADDOPCRA25_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45413  #define R_ADC_B0_ADDOPCRA25_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45414  #define R_ADC_B0_ADDOPCRA25_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45415  #define R_ADC_B0_ADDOPCRA25_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45416 /* ======================================================  ADDOPCRA26  ======================================================= */
45417  #define R_ADC_B0_ADDOPCRA26_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45418  #define R_ADC_B0_ADDOPCRA26_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45419  #define R_ADC_B0_ADDOPCRA26_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45420  #define R_ADC_B0_ADDOPCRA26_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45421 /* ======================================================  ADDOPCRA27  ======================================================= */
45422  #define R_ADC_B0_ADDOPCRA27_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45423  #define R_ADC_B0_ADDOPCRA27_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45424  #define R_ADC_B0_ADDOPCRA27_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45425  #define R_ADC_B0_ADDOPCRA27_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45426 /* ======================================================  ADDOPCRA28  ======================================================= */
45427  #define R_ADC_B0_ADDOPCRA28_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45428  #define R_ADC_B0_ADDOPCRA28_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45429  #define R_ADC_B0_ADDOPCRA28_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45430  #define R_ADC_B0_ADDOPCRA28_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45431 /* ======================================================  ADDOPCRA29  ======================================================= */
45432  #define R_ADC_B0_ADDOPCRA29_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45433  #define R_ADC_B0_ADDOPCRA29_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45434  #define R_ADC_B0_ADDOPCRA29_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45435  #define R_ADC_B0_ADDOPCRA29_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45436 /* ======================================================  ADDOPCRA30  ======================================================= */
45437  #define R_ADC_B0_ADDOPCRA30_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45438  #define R_ADC_B0_ADDOPCRA30_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45439  #define R_ADC_B0_ADDOPCRA30_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45440  #define R_ADC_B0_ADDOPCRA30_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45441 /* ======================================================  ADDOPCRA31  ======================================================= */
45442  #define R_ADC_B0_ADDOPCRA31_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45443  #define R_ADC_B0_ADDOPCRA31_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45444  #define R_ADC_B0_ADDOPCRA31_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45445  #define R_ADC_B0_ADDOPCRA31_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45446 /* ======================================================  ADDOPCRA32  ======================================================= */
45447  #define R_ADC_B0_ADDOPCRA32_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45448  #define R_ADC_B0_ADDOPCRA32_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45449  #define R_ADC_B0_ADDOPCRA32_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45450  #define R_ADC_B0_ADDOPCRA32_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45451 /* ======================================================  ADDOPCRA33  ======================================================= */
45452  #define R_ADC_B0_ADDOPCRA33_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45453  #define R_ADC_B0_ADDOPCRA33_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45454  #define R_ADC_B0_ADDOPCRA33_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45455  #define R_ADC_B0_ADDOPCRA33_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45456 /* ======================================================  ADDOPCRA34  ======================================================= */
45457  #define R_ADC_B0_ADDOPCRA34_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45458  #define R_ADC_B0_ADDOPCRA34_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45459  #define R_ADC_B0_ADDOPCRA34_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45460  #define R_ADC_B0_ADDOPCRA34_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45461 /* ======================================================  ADDOPCRA35  ======================================================= */
45462  #define R_ADC_B0_ADDOPCRA35_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45463  #define R_ADC_B0_ADDOPCRA35_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45464  #define R_ADC_B0_ADDOPCRA35_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45465  #define R_ADC_B0_ADDOPCRA35_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45466 /* ======================================================  ADDOPCRA36  ======================================================= */
45467  #define R_ADC_B0_ADDOPCRA36_GAINSEL_Pos       (16UL)         /*!< GAINSEL (Bit 16)                                      */
45468  #define R_ADC_B0_ADDOPCRA36_GAINSEL_Msk       (0xf0000UL)    /*!< GAINSEL (Bitfield-Mask: 0x0f)                         */
45469  #define R_ADC_B0_ADDOPCRA36_OFSETSEL_Pos      (24UL)         /*!< OFSETSEL (Bit 24)                                     */
45470  #define R_ADC_B0_ADDOPCRA36_OFSETSEL_Msk      (0xf000000UL)  /*!< OFSETSEL (Bitfield-Mask: 0x0f)                        */
45471 /* =======================================================  ADDOPCRB0  ======================================================= */
45472  #define R_ADC_B0_ADDOPCRB0_AVEMD_Pos          (0UL)          /*!< AVEMD (Bit 0)                                         */
45473  #define R_ADC_B0_ADDOPCRB0_AVEMD_Msk          (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45474  #define R_ADC_B0_ADDOPCRB0_ADC_Pos            (8UL)          /*!< ADC (Bit 8)                                           */
45475  #define R_ADC_B0_ADDOPCRB0_ADC_Msk            (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45476  #define R_ADC_B0_ADDOPCRB0_CMPTBLEm_Pos       (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45477  #define R_ADC_B0_ADDOPCRB0_CMPTBLEm_Msk       (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45478 /* =======================================================  ADDOPCRB1  ======================================================= */
45479  #define R_ADC_B0_ADDOPCRB1_AVEMD_Pos          (0UL)          /*!< AVEMD (Bit 0)                                         */
45480  #define R_ADC_B0_ADDOPCRB1_AVEMD_Msk          (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45481  #define R_ADC_B0_ADDOPCRB1_ADC_Pos            (8UL)          /*!< ADC (Bit 8)                                           */
45482  #define R_ADC_B0_ADDOPCRB1_ADC_Msk            (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45483  #define R_ADC_B0_ADDOPCRB1_CMPTBLEm_Pos       (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45484  #define R_ADC_B0_ADDOPCRB1_CMPTBLEm_Msk       (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45485 /* =======================================================  ADDOPCRB2  ======================================================= */
45486  #define R_ADC_B0_ADDOPCRB2_AVEMD_Pos          (0UL)          /*!< AVEMD (Bit 0)                                         */
45487  #define R_ADC_B0_ADDOPCRB2_AVEMD_Msk          (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45488  #define R_ADC_B0_ADDOPCRB2_ADC_Pos            (8UL)          /*!< ADC (Bit 8)                                           */
45489  #define R_ADC_B0_ADDOPCRB2_ADC_Msk            (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45490  #define R_ADC_B0_ADDOPCRB2_CMPTBLEm_Pos       (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45491  #define R_ADC_B0_ADDOPCRB2_CMPTBLEm_Msk       (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45492 /* =======================================================  ADDOPCRB3  ======================================================= */
45493  #define R_ADC_B0_ADDOPCRB3_AVEMD_Pos          (0UL)          /*!< AVEMD (Bit 0)                                         */
45494  #define R_ADC_B0_ADDOPCRB3_AVEMD_Msk          (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45495  #define R_ADC_B0_ADDOPCRB3_ADC_Pos            (8UL)          /*!< ADC (Bit 8)                                           */
45496  #define R_ADC_B0_ADDOPCRB3_ADC_Msk            (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45497  #define R_ADC_B0_ADDOPCRB3_CMPTBLEm_Pos       (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45498  #define R_ADC_B0_ADDOPCRB3_CMPTBLEm_Msk       (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45499 /* =======================================================  ADDOPCRB4  ======================================================= */
45500  #define R_ADC_B0_ADDOPCRB4_AVEMD_Pos          (0UL)          /*!< AVEMD (Bit 0)                                         */
45501  #define R_ADC_B0_ADDOPCRB4_AVEMD_Msk          (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45502  #define R_ADC_B0_ADDOPCRB4_ADC_Pos            (8UL)          /*!< ADC (Bit 8)                                           */
45503  #define R_ADC_B0_ADDOPCRB4_ADC_Msk            (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45504  #define R_ADC_B0_ADDOPCRB4_CMPTBLEm_Pos       (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45505  #define R_ADC_B0_ADDOPCRB4_CMPTBLEm_Msk       (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45506 /* =======================================================  ADDOPCRB5  ======================================================= */
45507  #define R_ADC_B0_ADDOPCRB5_AVEMD_Pos          (0UL)          /*!< AVEMD (Bit 0)                                         */
45508  #define R_ADC_B0_ADDOPCRB5_AVEMD_Msk          (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45509  #define R_ADC_B0_ADDOPCRB5_ADC_Pos            (8UL)          /*!< ADC (Bit 8)                                           */
45510  #define R_ADC_B0_ADDOPCRB5_ADC_Msk            (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45511  #define R_ADC_B0_ADDOPCRB5_CMPTBLEm_Pos       (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45512  #define R_ADC_B0_ADDOPCRB5_CMPTBLEm_Msk       (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45513 /* =======================================================  ADDOPCRB6  ======================================================= */
45514  #define R_ADC_B0_ADDOPCRB6_AVEMD_Pos          (0UL)          /*!< AVEMD (Bit 0)                                         */
45515  #define R_ADC_B0_ADDOPCRB6_AVEMD_Msk          (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45516  #define R_ADC_B0_ADDOPCRB6_ADC_Pos            (8UL)          /*!< ADC (Bit 8)                                           */
45517  #define R_ADC_B0_ADDOPCRB6_ADC_Msk            (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45518  #define R_ADC_B0_ADDOPCRB6_CMPTBLEm_Pos       (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45519  #define R_ADC_B0_ADDOPCRB6_CMPTBLEm_Msk       (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45520 /* =======================================================  ADDOPCRB7  ======================================================= */
45521  #define R_ADC_B0_ADDOPCRB7_AVEMD_Pos          (0UL)          /*!< AVEMD (Bit 0)                                         */
45522  #define R_ADC_B0_ADDOPCRB7_AVEMD_Msk          (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45523  #define R_ADC_B0_ADDOPCRB7_ADC_Pos            (8UL)          /*!< ADC (Bit 8)                                           */
45524  #define R_ADC_B0_ADDOPCRB7_ADC_Msk            (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45525  #define R_ADC_B0_ADDOPCRB7_CMPTBLEm_Pos       (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45526  #define R_ADC_B0_ADDOPCRB7_CMPTBLEm_Msk       (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45527 /* =======================================================  ADDOPCRB8  ======================================================= */
45528  #define R_ADC_B0_ADDOPCRB8_AVEMD_Pos          (0UL)          /*!< AVEMD (Bit 0)                                         */
45529  #define R_ADC_B0_ADDOPCRB8_AVEMD_Msk          (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45530  #define R_ADC_B0_ADDOPCRB8_ADC_Pos            (8UL)          /*!< ADC (Bit 8)                                           */
45531  #define R_ADC_B0_ADDOPCRB8_ADC_Msk            (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45532  #define R_ADC_B0_ADDOPCRB8_CMPTBLEm_Pos       (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45533  #define R_ADC_B0_ADDOPCRB8_CMPTBLEm_Msk       (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45534 /* =======================================================  ADDOPCRB9  ======================================================= */
45535  #define R_ADC_B0_ADDOPCRB9_AVEMD_Pos          (0UL)          /*!< AVEMD (Bit 0)                                         */
45536  #define R_ADC_B0_ADDOPCRB9_AVEMD_Msk          (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45537  #define R_ADC_B0_ADDOPCRB9_ADC_Pos            (8UL)          /*!< ADC (Bit 8)                                           */
45538  #define R_ADC_B0_ADDOPCRB9_ADC_Msk            (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45539  #define R_ADC_B0_ADDOPCRB9_CMPTBLEm_Pos       (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45540  #define R_ADC_B0_ADDOPCRB9_CMPTBLEm_Msk       (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45541 /* ======================================================  ADDOPCRB10  ======================================================= */
45542  #define R_ADC_B0_ADDOPCRB10_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45543  #define R_ADC_B0_ADDOPCRB10_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45544  #define R_ADC_B0_ADDOPCRB10_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45545  #define R_ADC_B0_ADDOPCRB10_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45546  #define R_ADC_B0_ADDOPCRB10_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45547  #define R_ADC_B0_ADDOPCRB10_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45548 /* ======================================================  ADDOPCRB11  ======================================================= */
45549  #define R_ADC_B0_ADDOPCRB11_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45550  #define R_ADC_B0_ADDOPCRB11_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45551  #define R_ADC_B0_ADDOPCRB11_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45552  #define R_ADC_B0_ADDOPCRB11_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45553  #define R_ADC_B0_ADDOPCRB11_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45554  #define R_ADC_B0_ADDOPCRB11_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45555 /* ======================================================  ADDOPCRB12  ======================================================= */
45556  #define R_ADC_B0_ADDOPCRB12_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45557  #define R_ADC_B0_ADDOPCRB12_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45558  #define R_ADC_B0_ADDOPCRB12_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45559  #define R_ADC_B0_ADDOPCRB12_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45560  #define R_ADC_B0_ADDOPCRB12_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45561  #define R_ADC_B0_ADDOPCRB12_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45562 /* ======================================================  ADDOPCRB13  ======================================================= */
45563  #define R_ADC_B0_ADDOPCRB13_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45564  #define R_ADC_B0_ADDOPCRB13_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45565  #define R_ADC_B0_ADDOPCRB13_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45566  #define R_ADC_B0_ADDOPCRB13_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45567  #define R_ADC_B0_ADDOPCRB13_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45568  #define R_ADC_B0_ADDOPCRB13_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45569 /* ======================================================  ADDOPCRB14  ======================================================= */
45570  #define R_ADC_B0_ADDOPCRB14_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45571  #define R_ADC_B0_ADDOPCRB14_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45572  #define R_ADC_B0_ADDOPCRB14_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45573  #define R_ADC_B0_ADDOPCRB14_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45574  #define R_ADC_B0_ADDOPCRB14_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45575  #define R_ADC_B0_ADDOPCRB14_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45576 /* ======================================================  ADDOPCRB15  ======================================================= */
45577  #define R_ADC_B0_ADDOPCRB15_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45578  #define R_ADC_B0_ADDOPCRB15_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45579  #define R_ADC_B0_ADDOPCRB15_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45580  #define R_ADC_B0_ADDOPCRB15_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45581  #define R_ADC_B0_ADDOPCRB15_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45582  #define R_ADC_B0_ADDOPCRB15_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45583 /* ======================================================  ADDOPCRB16  ======================================================= */
45584  #define R_ADC_B0_ADDOPCRB16_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45585  #define R_ADC_B0_ADDOPCRB16_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45586  #define R_ADC_B0_ADDOPCRB16_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45587  #define R_ADC_B0_ADDOPCRB16_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45588  #define R_ADC_B0_ADDOPCRB16_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45589  #define R_ADC_B0_ADDOPCRB16_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45590 /* ======================================================  ADDOPCRB17  ======================================================= */
45591  #define R_ADC_B0_ADDOPCRB17_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45592  #define R_ADC_B0_ADDOPCRB17_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45593  #define R_ADC_B0_ADDOPCRB17_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45594  #define R_ADC_B0_ADDOPCRB17_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45595  #define R_ADC_B0_ADDOPCRB17_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45596  #define R_ADC_B0_ADDOPCRB17_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45597 /* ======================================================  ADDOPCRB18  ======================================================= */
45598  #define R_ADC_B0_ADDOPCRB18_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45599  #define R_ADC_B0_ADDOPCRB18_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45600  #define R_ADC_B0_ADDOPCRB18_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45601  #define R_ADC_B0_ADDOPCRB18_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45602  #define R_ADC_B0_ADDOPCRB18_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45603  #define R_ADC_B0_ADDOPCRB18_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45604 /* ======================================================  ADDOPCRB19  ======================================================= */
45605  #define R_ADC_B0_ADDOPCRB19_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45606  #define R_ADC_B0_ADDOPCRB19_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45607  #define R_ADC_B0_ADDOPCRB19_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45608  #define R_ADC_B0_ADDOPCRB19_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45609  #define R_ADC_B0_ADDOPCRB19_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45610  #define R_ADC_B0_ADDOPCRB19_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45611 /* ======================================================  ADDOPCRB20  ======================================================= */
45612  #define R_ADC_B0_ADDOPCRB20_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45613  #define R_ADC_B0_ADDOPCRB20_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45614  #define R_ADC_B0_ADDOPCRB20_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45615  #define R_ADC_B0_ADDOPCRB20_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45616  #define R_ADC_B0_ADDOPCRB20_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45617  #define R_ADC_B0_ADDOPCRB20_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45618 /* ======================================================  ADDOPCRB21  ======================================================= */
45619  #define R_ADC_B0_ADDOPCRB21_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45620  #define R_ADC_B0_ADDOPCRB21_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45621  #define R_ADC_B0_ADDOPCRB21_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45622  #define R_ADC_B0_ADDOPCRB21_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45623  #define R_ADC_B0_ADDOPCRB21_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45624  #define R_ADC_B0_ADDOPCRB21_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45625 /* ======================================================  ADDOPCRB22  ======================================================= */
45626  #define R_ADC_B0_ADDOPCRB22_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45627  #define R_ADC_B0_ADDOPCRB22_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45628  #define R_ADC_B0_ADDOPCRB22_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45629  #define R_ADC_B0_ADDOPCRB22_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45630  #define R_ADC_B0_ADDOPCRB22_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45631  #define R_ADC_B0_ADDOPCRB22_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45632 /* ======================================================  ADDOPCRB23  ======================================================= */
45633  #define R_ADC_B0_ADDOPCRB23_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45634  #define R_ADC_B0_ADDOPCRB23_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45635  #define R_ADC_B0_ADDOPCRB23_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45636  #define R_ADC_B0_ADDOPCRB23_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45637  #define R_ADC_B0_ADDOPCRB23_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45638  #define R_ADC_B0_ADDOPCRB23_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45639 /* ======================================================  ADDOPCRB24  ======================================================= */
45640  #define R_ADC_B0_ADDOPCRB24_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45641  #define R_ADC_B0_ADDOPCRB24_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45642  #define R_ADC_B0_ADDOPCRB24_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45643  #define R_ADC_B0_ADDOPCRB24_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45644  #define R_ADC_B0_ADDOPCRB24_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45645  #define R_ADC_B0_ADDOPCRB24_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45646 /* ======================================================  ADDOPCRB25  ======================================================= */
45647  #define R_ADC_B0_ADDOPCRB25_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45648  #define R_ADC_B0_ADDOPCRB25_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45649  #define R_ADC_B0_ADDOPCRB25_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45650  #define R_ADC_B0_ADDOPCRB25_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45651  #define R_ADC_B0_ADDOPCRB25_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45652  #define R_ADC_B0_ADDOPCRB25_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45653 /* ======================================================  ADDOPCRB26  ======================================================= */
45654  #define R_ADC_B0_ADDOPCRB26_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45655  #define R_ADC_B0_ADDOPCRB26_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45656  #define R_ADC_B0_ADDOPCRB26_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45657  #define R_ADC_B0_ADDOPCRB26_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45658  #define R_ADC_B0_ADDOPCRB26_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45659  #define R_ADC_B0_ADDOPCRB26_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45660 /* ======================================================  ADDOPCRB27  ======================================================= */
45661  #define R_ADC_B0_ADDOPCRB27_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45662  #define R_ADC_B0_ADDOPCRB27_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45663  #define R_ADC_B0_ADDOPCRB27_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45664  #define R_ADC_B0_ADDOPCRB27_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45665  #define R_ADC_B0_ADDOPCRB27_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45666  #define R_ADC_B0_ADDOPCRB27_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45667 /* ======================================================  ADDOPCRB28  ======================================================= */
45668  #define R_ADC_B0_ADDOPCRB28_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45669  #define R_ADC_B0_ADDOPCRB28_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45670  #define R_ADC_B0_ADDOPCRB28_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45671  #define R_ADC_B0_ADDOPCRB28_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45672  #define R_ADC_B0_ADDOPCRB28_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45673  #define R_ADC_B0_ADDOPCRB28_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45674 /* ======================================================  ADDOPCRB29  ======================================================= */
45675  #define R_ADC_B0_ADDOPCRB29_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45676  #define R_ADC_B0_ADDOPCRB29_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45677  #define R_ADC_B0_ADDOPCRB29_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45678  #define R_ADC_B0_ADDOPCRB29_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45679  #define R_ADC_B0_ADDOPCRB29_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45680  #define R_ADC_B0_ADDOPCRB29_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45681 /* ======================================================  ADDOPCRB30  ======================================================= */
45682  #define R_ADC_B0_ADDOPCRB30_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45683  #define R_ADC_B0_ADDOPCRB30_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45684  #define R_ADC_B0_ADDOPCRB30_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45685  #define R_ADC_B0_ADDOPCRB30_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45686  #define R_ADC_B0_ADDOPCRB30_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45687  #define R_ADC_B0_ADDOPCRB30_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45688 /* ======================================================  ADDOPCRB31  ======================================================= */
45689  #define R_ADC_B0_ADDOPCRB31_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45690  #define R_ADC_B0_ADDOPCRB31_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45691  #define R_ADC_B0_ADDOPCRB31_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45692  #define R_ADC_B0_ADDOPCRB31_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45693  #define R_ADC_B0_ADDOPCRB31_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45694  #define R_ADC_B0_ADDOPCRB31_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45695 /* ======================================================  ADDOPCRB32  ======================================================= */
45696  #define R_ADC_B0_ADDOPCRB32_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45697  #define R_ADC_B0_ADDOPCRB32_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45698  #define R_ADC_B0_ADDOPCRB32_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45699  #define R_ADC_B0_ADDOPCRB32_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45700  #define R_ADC_B0_ADDOPCRB32_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45701  #define R_ADC_B0_ADDOPCRB32_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45702 /* ======================================================  ADDOPCRB33  ======================================================= */
45703  #define R_ADC_B0_ADDOPCRB33_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45704  #define R_ADC_B0_ADDOPCRB33_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45705  #define R_ADC_B0_ADDOPCRB33_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45706  #define R_ADC_B0_ADDOPCRB33_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45707  #define R_ADC_B0_ADDOPCRB33_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45708  #define R_ADC_B0_ADDOPCRB33_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45709 /* ======================================================  ADDOPCRB34  ======================================================= */
45710  #define R_ADC_B0_ADDOPCRB34_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45711  #define R_ADC_B0_ADDOPCRB34_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45712  #define R_ADC_B0_ADDOPCRB34_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45713  #define R_ADC_B0_ADDOPCRB34_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45714  #define R_ADC_B0_ADDOPCRB34_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45715  #define R_ADC_B0_ADDOPCRB34_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45716 /* ======================================================  ADDOPCRB35  ======================================================= */
45717  #define R_ADC_B0_ADDOPCRB35_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45718  #define R_ADC_B0_ADDOPCRB35_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45719  #define R_ADC_B0_ADDOPCRB35_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45720  #define R_ADC_B0_ADDOPCRB35_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45721  #define R_ADC_B0_ADDOPCRB35_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45722  #define R_ADC_B0_ADDOPCRB35_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45723 /* ======================================================  ADDOPCRB36  ======================================================= */
45724  #define R_ADC_B0_ADDOPCRB36_AVEMD_Pos         (0UL)          /*!< AVEMD (Bit 0)                                         */
45725  #define R_ADC_B0_ADDOPCRB36_AVEMD_Msk         (0x3UL)        /*!< AVEMD (Bitfield-Mask: 0x03)                           */
45726  #define R_ADC_B0_ADDOPCRB36_ADC_Pos           (8UL)          /*!< ADC (Bit 8)                                           */
45727  #define R_ADC_B0_ADDOPCRB36_ADC_Msk           (0xf00UL)      /*!< ADC (Bitfield-Mask: 0x0f)                             */
45728  #define R_ADC_B0_ADDOPCRB36_CMPTBLEm_Pos      (16UL)         /*!< CMPTBLEm (Bit 16)                                     */
45729  #define R_ADC_B0_ADDOPCRB36_CMPTBLEm_Msk      (0xff0000UL)   /*!< CMPTBLEm (Bitfield-Mask: 0xff)                        */
45730 /* =======================================================  ADDOPCRC0  ======================================================= */
45731  #define R_ADC_B0_ADDOPCRC0_LIMTBLS_Pos        (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45732  #define R_ADC_B0_ADDOPCRC0_LIMTBLS_Msk        (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45733  #define R_ADC_B0_ADDOPCRC0_ADPRC_Pos          (16UL)         /*!< ADPRC (Bit 16)                                        */
45734  #define R_ADC_B0_ADDOPCRC0_ADPRC_Msk          (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45735  #define R_ADC_B0_ADDOPCRC0_SIGNSEL_Pos        (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45736  #define R_ADC_B0_ADDOPCRC0_SIGNSEL_Msk        (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45737 /* =======================================================  ADDOPCRC1  ======================================================= */
45738  #define R_ADC_B0_ADDOPCRC1_LIMTBLS_Pos        (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45739  #define R_ADC_B0_ADDOPCRC1_LIMTBLS_Msk        (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45740  #define R_ADC_B0_ADDOPCRC1_ADPRC_Pos          (16UL)         /*!< ADPRC (Bit 16)                                        */
45741  #define R_ADC_B0_ADDOPCRC1_ADPRC_Msk          (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45742  #define R_ADC_B0_ADDOPCRC1_SIGNSEL_Pos        (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45743  #define R_ADC_B0_ADDOPCRC1_SIGNSEL_Msk        (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45744 /* =======================================================  ADDOPCRC2  ======================================================= */
45745  #define R_ADC_B0_ADDOPCRC2_LIMTBLS_Pos        (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45746  #define R_ADC_B0_ADDOPCRC2_LIMTBLS_Msk        (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45747  #define R_ADC_B0_ADDOPCRC2_ADPRC_Pos          (16UL)         /*!< ADPRC (Bit 16)                                        */
45748  #define R_ADC_B0_ADDOPCRC2_ADPRC_Msk          (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45749  #define R_ADC_B0_ADDOPCRC2_SIGNSEL_Pos        (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45750  #define R_ADC_B0_ADDOPCRC2_SIGNSEL_Msk        (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45751 /* =======================================================  ADDOPCRC3  ======================================================= */
45752  #define R_ADC_B0_ADDOPCRC3_LIMTBLS_Pos        (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45753  #define R_ADC_B0_ADDOPCRC3_LIMTBLS_Msk        (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45754  #define R_ADC_B0_ADDOPCRC3_ADPRC_Pos          (16UL)         /*!< ADPRC (Bit 16)                                        */
45755  #define R_ADC_B0_ADDOPCRC3_ADPRC_Msk          (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45756  #define R_ADC_B0_ADDOPCRC3_SIGNSEL_Pos        (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45757  #define R_ADC_B0_ADDOPCRC3_SIGNSEL_Msk        (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45758 /* =======================================================  ADDOPCRC4  ======================================================= */
45759  #define R_ADC_B0_ADDOPCRC4_LIMTBLS_Pos        (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45760  #define R_ADC_B0_ADDOPCRC4_LIMTBLS_Msk        (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45761  #define R_ADC_B0_ADDOPCRC4_ADPRC_Pos          (16UL)         /*!< ADPRC (Bit 16)                                        */
45762  #define R_ADC_B0_ADDOPCRC4_ADPRC_Msk          (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45763  #define R_ADC_B0_ADDOPCRC4_SIGNSEL_Pos        (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45764  #define R_ADC_B0_ADDOPCRC4_SIGNSEL_Msk        (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45765 /* =======================================================  ADDOPCRC5  ======================================================= */
45766  #define R_ADC_B0_ADDOPCRC5_LIMTBLS_Pos        (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45767  #define R_ADC_B0_ADDOPCRC5_LIMTBLS_Msk        (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45768  #define R_ADC_B0_ADDOPCRC5_ADPRC_Pos          (16UL)         /*!< ADPRC (Bit 16)                                        */
45769  #define R_ADC_B0_ADDOPCRC5_ADPRC_Msk          (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45770  #define R_ADC_B0_ADDOPCRC5_SIGNSEL_Pos        (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45771  #define R_ADC_B0_ADDOPCRC5_SIGNSEL_Msk        (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45772 /* =======================================================  ADDOPCRC6  ======================================================= */
45773  #define R_ADC_B0_ADDOPCRC6_LIMTBLS_Pos        (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45774  #define R_ADC_B0_ADDOPCRC6_LIMTBLS_Msk        (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45775  #define R_ADC_B0_ADDOPCRC6_ADPRC_Pos          (16UL)         /*!< ADPRC (Bit 16)                                        */
45776  #define R_ADC_B0_ADDOPCRC6_ADPRC_Msk          (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45777  #define R_ADC_B0_ADDOPCRC6_SIGNSEL_Pos        (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45778  #define R_ADC_B0_ADDOPCRC6_SIGNSEL_Msk        (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45779 /* =======================================================  ADDOPCRC7  ======================================================= */
45780  #define R_ADC_B0_ADDOPCRC7_LIMTBLS_Pos        (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45781  #define R_ADC_B0_ADDOPCRC7_LIMTBLS_Msk        (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45782  #define R_ADC_B0_ADDOPCRC7_ADPRC_Pos          (16UL)         /*!< ADPRC (Bit 16)                                        */
45783  #define R_ADC_B0_ADDOPCRC7_ADPRC_Msk          (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45784  #define R_ADC_B0_ADDOPCRC7_SIGNSEL_Pos        (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45785  #define R_ADC_B0_ADDOPCRC7_SIGNSEL_Msk        (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45786 /* =======================================================  ADDOPCRC8  ======================================================= */
45787  #define R_ADC_B0_ADDOPCRC8_LIMTBLS_Pos        (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45788  #define R_ADC_B0_ADDOPCRC8_LIMTBLS_Msk        (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45789  #define R_ADC_B0_ADDOPCRC8_ADPRC_Pos          (16UL)         /*!< ADPRC (Bit 16)                                        */
45790  #define R_ADC_B0_ADDOPCRC8_ADPRC_Msk          (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45791  #define R_ADC_B0_ADDOPCRC8_SIGNSEL_Pos        (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45792  #define R_ADC_B0_ADDOPCRC8_SIGNSEL_Msk        (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45793 /* =======================================================  ADDOPCRC9  ======================================================= */
45794  #define R_ADC_B0_ADDOPCRC9_LIMTBLS_Pos        (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45795  #define R_ADC_B0_ADDOPCRC9_LIMTBLS_Msk        (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45796  #define R_ADC_B0_ADDOPCRC9_ADPRC_Pos          (16UL)         /*!< ADPRC (Bit 16)                                        */
45797  #define R_ADC_B0_ADDOPCRC9_ADPRC_Msk          (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45798  #define R_ADC_B0_ADDOPCRC9_SIGNSEL_Pos        (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45799  #define R_ADC_B0_ADDOPCRC9_SIGNSEL_Msk        (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45800 /* ======================================================  ADDOPCRC10  ======================================================= */
45801  #define R_ADC_B0_ADDOPCRC10_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45802  #define R_ADC_B0_ADDOPCRC10_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45803  #define R_ADC_B0_ADDOPCRC10_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45804  #define R_ADC_B0_ADDOPCRC10_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45805  #define R_ADC_B0_ADDOPCRC10_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45806  #define R_ADC_B0_ADDOPCRC10_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45807 /* ======================================================  ADDOPCRC11  ======================================================= */
45808  #define R_ADC_B0_ADDOPCRC11_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45809  #define R_ADC_B0_ADDOPCRC11_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45810  #define R_ADC_B0_ADDOPCRC11_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45811  #define R_ADC_B0_ADDOPCRC11_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45812  #define R_ADC_B0_ADDOPCRC11_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45813  #define R_ADC_B0_ADDOPCRC11_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45814 /* ======================================================  ADDOPCRC12  ======================================================= */
45815  #define R_ADC_B0_ADDOPCRC12_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45816  #define R_ADC_B0_ADDOPCRC12_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45817  #define R_ADC_B0_ADDOPCRC12_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45818  #define R_ADC_B0_ADDOPCRC12_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45819  #define R_ADC_B0_ADDOPCRC12_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45820  #define R_ADC_B0_ADDOPCRC12_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45821 /* ======================================================  ADDOPCRC13  ======================================================= */
45822  #define R_ADC_B0_ADDOPCRC13_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45823  #define R_ADC_B0_ADDOPCRC13_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45824  #define R_ADC_B0_ADDOPCRC13_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45825  #define R_ADC_B0_ADDOPCRC13_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45826  #define R_ADC_B0_ADDOPCRC13_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45827  #define R_ADC_B0_ADDOPCRC13_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45828 /* ======================================================  ADDOPCRC14  ======================================================= */
45829  #define R_ADC_B0_ADDOPCRC14_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45830  #define R_ADC_B0_ADDOPCRC14_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45831  #define R_ADC_B0_ADDOPCRC14_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45832  #define R_ADC_B0_ADDOPCRC14_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45833  #define R_ADC_B0_ADDOPCRC14_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45834  #define R_ADC_B0_ADDOPCRC14_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45835 /* ======================================================  ADDOPCRC15  ======================================================= */
45836  #define R_ADC_B0_ADDOPCRC15_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45837  #define R_ADC_B0_ADDOPCRC15_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45838  #define R_ADC_B0_ADDOPCRC15_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45839  #define R_ADC_B0_ADDOPCRC15_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45840  #define R_ADC_B0_ADDOPCRC15_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45841  #define R_ADC_B0_ADDOPCRC15_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45842 /* ======================================================  ADDOPCRC16  ======================================================= */
45843  #define R_ADC_B0_ADDOPCRC16_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45844  #define R_ADC_B0_ADDOPCRC16_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45845  #define R_ADC_B0_ADDOPCRC16_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45846  #define R_ADC_B0_ADDOPCRC16_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45847  #define R_ADC_B0_ADDOPCRC16_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45848  #define R_ADC_B0_ADDOPCRC16_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45849 /* ======================================================  ADDOPCRC17  ======================================================= */
45850  #define R_ADC_B0_ADDOPCRC17_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45851  #define R_ADC_B0_ADDOPCRC17_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45852  #define R_ADC_B0_ADDOPCRC17_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45853  #define R_ADC_B0_ADDOPCRC17_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45854  #define R_ADC_B0_ADDOPCRC17_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45855  #define R_ADC_B0_ADDOPCRC17_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45856 /* ======================================================  ADDOPCRC18  ======================================================= */
45857  #define R_ADC_B0_ADDOPCRC18_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45858  #define R_ADC_B0_ADDOPCRC18_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45859  #define R_ADC_B0_ADDOPCRC18_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45860  #define R_ADC_B0_ADDOPCRC18_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45861  #define R_ADC_B0_ADDOPCRC18_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45862  #define R_ADC_B0_ADDOPCRC18_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45863 /* ======================================================  ADDOPCRC19  ======================================================= */
45864  #define R_ADC_B0_ADDOPCRC19_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45865  #define R_ADC_B0_ADDOPCRC19_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45866  #define R_ADC_B0_ADDOPCRC19_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45867  #define R_ADC_B0_ADDOPCRC19_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45868  #define R_ADC_B0_ADDOPCRC19_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45869  #define R_ADC_B0_ADDOPCRC19_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45870 /* ======================================================  ADDOPCRC20  ======================================================= */
45871  #define R_ADC_B0_ADDOPCRC20_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45872  #define R_ADC_B0_ADDOPCRC20_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45873  #define R_ADC_B0_ADDOPCRC20_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45874  #define R_ADC_B0_ADDOPCRC20_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45875  #define R_ADC_B0_ADDOPCRC20_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45876  #define R_ADC_B0_ADDOPCRC20_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45877 /* ======================================================  ADDOPCRC21  ======================================================= */
45878  #define R_ADC_B0_ADDOPCRC21_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45879  #define R_ADC_B0_ADDOPCRC21_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45880  #define R_ADC_B0_ADDOPCRC21_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45881  #define R_ADC_B0_ADDOPCRC21_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45882  #define R_ADC_B0_ADDOPCRC21_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45883  #define R_ADC_B0_ADDOPCRC21_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45884 /* ======================================================  ADDOPCRC22  ======================================================= */
45885  #define R_ADC_B0_ADDOPCRC22_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45886  #define R_ADC_B0_ADDOPCRC22_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45887  #define R_ADC_B0_ADDOPCRC22_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45888  #define R_ADC_B0_ADDOPCRC22_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45889  #define R_ADC_B0_ADDOPCRC22_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45890  #define R_ADC_B0_ADDOPCRC22_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45891 /* ======================================================  ADDOPCRC23  ======================================================= */
45892  #define R_ADC_B0_ADDOPCRC23_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45893  #define R_ADC_B0_ADDOPCRC23_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45894  #define R_ADC_B0_ADDOPCRC23_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45895  #define R_ADC_B0_ADDOPCRC23_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45896  #define R_ADC_B0_ADDOPCRC23_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45897  #define R_ADC_B0_ADDOPCRC23_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45898 /* ======================================================  ADDOPCRC24  ======================================================= */
45899  #define R_ADC_B0_ADDOPCRC24_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45900  #define R_ADC_B0_ADDOPCRC24_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45901  #define R_ADC_B0_ADDOPCRC24_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45902  #define R_ADC_B0_ADDOPCRC24_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45903  #define R_ADC_B0_ADDOPCRC24_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45904  #define R_ADC_B0_ADDOPCRC24_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45905 /* ======================================================  ADDOPCRC25  ======================================================= */
45906  #define R_ADC_B0_ADDOPCRC25_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45907  #define R_ADC_B0_ADDOPCRC25_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45908  #define R_ADC_B0_ADDOPCRC25_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45909  #define R_ADC_B0_ADDOPCRC25_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45910  #define R_ADC_B0_ADDOPCRC25_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45911  #define R_ADC_B0_ADDOPCRC25_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45912 /* ======================================================  ADDOPCRC26  ======================================================= */
45913  #define R_ADC_B0_ADDOPCRC26_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45914  #define R_ADC_B0_ADDOPCRC26_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45915  #define R_ADC_B0_ADDOPCRC26_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45916  #define R_ADC_B0_ADDOPCRC26_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45917  #define R_ADC_B0_ADDOPCRC26_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45918  #define R_ADC_B0_ADDOPCRC26_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45919 /* ======================================================  ADDOPCRC27  ======================================================= */
45920  #define R_ADC_B0_ADDOPCRC27_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45921  #define R_ADC_B0_ADDOPCRC27_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45922  #define R_ADC_B0_ADDOPCRC27_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45923  #define R_ADC_B0_ADDOPCRC27_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45924  #define R_ADC_B0_ADDOPCRC27_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45925  #define R_ADC_B0_ADDOPCRC27_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45926 /* ======================================================  ADDOPCRC28  ======================================================= */
45927  #define R_ADC_B0_ADDOPCRC28_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45928  #define R_ADC_B0_ADDOPCRC28_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45929  #define R_ADC_B0_ADDOPCRC28_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45930  #define R_ADC_B0_ADDOPCRC28_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45931  #define R_ADC_B0_ADDOPCRC28_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45932  #define R_ADC_B0_ADDOPCRC28_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45933 /* ======================================================  ADDOPCRC29  ======================================================= */
45934  #define R_ADC_B0_ADDOPCRC29_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45935  #define R_ADC_B0_ADDOPCRC29_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45936  #define R_ADC_B0_ADDOPCRC29_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45937  #define R_ADC_B0_ADDOPCRC29_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45938  #define R_ADC_B0_ADDOPCRC29_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45939  #define R_ADC_B0_ADDOPCRC29_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45940 /* ======================================================  ADDOPCRC30  ======================================================= */
45941  #define R_ADC_B0_ADDOPCRC30_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45942  #define R_ADC_B0_ADDOPCRC30_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45943  #define R_ADC_B0_ADDOPCRC30_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45944  #define R_ADC_B0_ADDOPCRC30_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45945  #define R_ADC_B0_ADDOPCRC30_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45946  #define R_ADC_B0_ADDOPCRC30_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45947 /* ======================================================  ADDOPCRC31  ======================================================= */
45948  #define R_ADC_B0_ADDOPCRC31_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45949  #define R_ADC_B0_ADDOPCRC31_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45950  #define R_ADC_B0_ADDOPCRC31_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45951  #define R_ADC_B0_ADDOPCRC31_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45952  #define R_ADC_B0_ADDOPCRC31_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45953  #define R_ADC_B0_ADDOPCRC31_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45954 /* ======================================================  ADDOPCRC32  ======================================================= */
45955  #define R_ADC_B0_ADDOPCRC32_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45956  #define R_ADC_B0_ADDOPCRC32_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45957  #define R_ADC_B0_ADDOPCRC32_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45958  #define R_ADC_B0_ADDOPCRC32_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45959  #define R_ADC_B0_ADDOPCRC32_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45960  #define R_ADC_B0_ADDOPCRC32_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45961 /* ======================================================  ADDOPCRC33  ======================================================= */
45962  #define R_ADC_B0_ADDOPCRC33_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45963  #define R_ADC_B0_ADDOPCRC33_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45964  #define R_ADC_B0_ADDOPCRC33_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45965  #define R_ADC_B0_ADDOPCRC33_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45966  #define R_ADC_B0_ADDOPCRC33_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45967  #define R_ADC_B0_ADDOPCRC33_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45968 /* ======================================================  ADDOPCRC34  ======================================================= */
45969  #define R_ADC_B0_ADDOPCRC34_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45970  #define R_ADC_B0_ADDOPCRC34_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45971  #define R_ADC_B0_ADDOPCRC34_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45972  #define R_ADC_B0_ADDOPCRC34_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45973  #define R_ADC_B0_ADDOPCRC34_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45974  #define R_ADC_B0_ADDOPCRC34_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45975 /* ======================================================  ADDOPCRC35  ======================================================= */
45976  #define R_ADC_B0_ADDOPCRC35_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45977  #define R_ADC_B0_ADDOPCRC35_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45978  #define R_ADC_B0_ADDOPCRC35_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45979  #define R_ADC_B0_ADDOPCRC35_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45980  #define R_ADC_B0_ADDOPCRC35_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45981  #define R_ADC_B0_ADDOPCRC35_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45982 /* ======================================================  ADDOPCRC36  ======================================================= */
45983  #define R_ADC_B0_ADDOPCRC36_LIMTBLS_Pos       (0UL)          /*!< LIMTBLS (Bit 0)                                       */
45984  #define R_ADC_B0_ADDOPCRC36_LIMTBLS_Msk       (0xfUL)        /*!< LIMTBLS (Bitfield-Mask: 0x0f)                         */
45985  #define R_ADC_B0_ADDOPCRC36_ADPRC_Pos         (16UL)         /*!< ADPRC (Bit 16)                                        */
45986  #define R_ADC_B0_ADDOPCRC36_ADPRC_Msk         (0x30000UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
45987  #define R_ADC_B0_ADDOPCRC36_SIGNSEL_Pos       (20UL)         /*!< SIGNSEL (Bit 20)                                      */
45988  #define R_ADC_B0_ADDOPCRC36_SIGNSEL_Msk       (0x100000UL)   /*!< SIGNSEL (Bitfield-Mask: 0x01)                         */
45989 /* =======================================================  ADCALSTR  ======================================================== */
45990  #define R_ADC_B0_ADCALSTR_ADCALST0_Pos        (0UL)          /*!< ADCALST0 (Bit 0)                                      */
45991  #define R_ADC_B0_ADCALSTR_ADCALST0_Msk        (0x7UL)        /*!< ADCALST0 (Bitfield-Mask: 0x07)                        */
45992  #define R_ADC_B0_ADCALSTR_ADCALST1_Pos        (8UL)          /*!< ADCALST1 (Bit 8)                                      */
45993  #define R_ADC_B0_ADCALSTR_ADCALST1_Msk        (0x700UL)      /*!< ADCALST1 (Bitfield-Mask: 0x07)                        */
45994 /* =======================================================  ADTRGENR  ======================================================== */
45995  #define R_ADC_B0_ADTRGENR_STTRGENn_Pos        (0UL)          /*!< STTRGENn (Bit 0)                                      */
45996  #define R_ADC_B0_ADTRGENR_STTRGENn_Msk        (0x1ffUL)      /*!< STTRGENn (Bitfield-Mask: 0x1ff)                       */
45997 /* ========================================================  ADSYSTR  ======================================================== */
45998  #define R_ADC_B0_ADSYSTR_ADSYSTn_Pos          (0UL)          /*!< ADSYSTn (Bit 0)                                       */
45999  #define R_ADC_B0_ADSYSTR_ADSYSTn_Msk          (0x1ffUL)      /*!< ADSYSTn (Bitfield-Mask: 0x1ff)                        */
46000 /* =========================================================  ADSTR  ========================================================= */
46001  #define R_ADC_B0_ADSTR_ADST_Pos               (0UL)          /*!< ADST (Bit 0)                                          */
46002  #define R_ADC_B0_ADSTR_ADST_Msk               (0x1UL)        /*!< ADST (Bitfield-Mask: 0x01)                            */
46003 /* ========================================================  ADSTOPR  ======================================================== */
46004  #define R_ADC_B0_ADSTOPR_ADSTOP0_Pos          (0UL)          /*!< ADSTOP0 (Bit 0)                                       */
46005  #define R_ADC_B0_ADSTOPR_ADSTOP0_Msk          (0x1UL)        /*!< ADSTOP0 (Bitfield-Mask: 0x01)                         */
46006  #define R_ADC_B0_ADSTOPR_ADSTOP1_Pos          (8UL)          /*!< ADSTOP1 (Bit 8)                                       */
46007  #define R_ADC_B0_ADSTOPR_ADSTOP1_Msk          (0x100UL)      /*!< ADSTOP1 (Bitfield-Mask: 0x01)                         */
46008 /* =========================================================  ADSR  ========================================================== */
46009  #define R_ADC_B0_ADSR_ADACT0_Pos              (0UL)          /*!< ADACT0 (Bit 0)                                        */
46010  #define R_ADC_B0_ADSR_ADACT0_Msk              (0x1UL)        /*!< ADACT0 (Bitfield-Mask: 0x01)                          */
46011  #define R_ADC_B0_ADSR_ADACT1_Pos              (1UL)          /*!< ADACT1 (Bit 1)                                        */
46012  #define R_ADC_B0_ADSR_ADACT1_Msk              (0x2UL)        /*!< ADACT1 (Bitfield-Mask: 0x01)                          */
46013  #define R_ADC_B0_ADSR_CALACT0_Pos             (16UL)         /*!< CALACT0 (Bit 16)                                      */
46014  #define R_ADC_B0_ADSR_CALACT0_Msk             (0x10000UL)    /*!< CALACT0 (Bitfield-Mask: 0x01)                         */
46015  #define R_ADC_B0_ADSR_CALACT1_Pos             (17UL)         /*!< CALACT1 (Bit 17)                                      */
46016  #define R_ADC_B0_ADSR_CALACT1_Msk             (0x20000UL)    /*!< CALACT1 (Bitfield-Mask: 0x01)                         */
46017 /* ========================================================  ADGRSR  ========================================================= */
46018  #define R_ADC_B0_ADGRSR_ACTGRn_Pos            (0UL)          /*!< ACTGRn (Bit 0)                                        */
46019  #define R_ADC_B0_ADGRSR_ACTGRn_Msk            (0x1ffUL)      /*!< ACTGRn (Bitfield-Mask: 0x1ff)                         */
46020 /* ========================================================  ADERSR  ========================================================= */
46021  #define R_ADC_B0_ADERSR_ADERF0_Pos            (0UL)          /*!< ADERF0 (Bit 0)                                        */
46022  #define R_ADC_B0_ADERSR_ADERF0_Msk            (0x1UL)        /*!< ADERF0 (Bitfield-Mask: 0x01)                          */
46023  #define R_ADC_B0_ADERSR_ADERF1_Pos            (1UL)          /*!< ADERF1 (Bit 1)                                        */
46024  #define R_ADC_B0_ADERSR_ADERF1_Msk            (0x2UL)        /*!< ADERF1 (Bitfield-Mask: 0x01)                          */
46025 /* ========================================================  ADERSCR  ======================================================== */
46026  #define R_ADC_B0_ADERSCR_ADERCLR0_Pos         (0UL)          /*!< ADERCLR0 (Bit 0)                                      */
46027  #define R_ADC_B0_ADERSCR_ADERCLR0_Msk         (0x1UL)        /*!< ADERCLR0 (Bitfield-Mask: 0x01)                        */
46028  #define R_ADC_B0_ADERSCR_ADERCLR1_Pos         (1UL)          /*!< ADERCLR1 (Bit 1)                                      */
46029  #define R_ADC_B0_ADERSCR_ADERCLR1_Msk         (0x2UL)        /*!< ADERCLR1 (Bitfield-Mask: 0x01)                        */
46030 /* ======================================================  ADCALENDSR  ======================================================= */
46031  #define R_ADC_B0_ADCALENDSR_CALENDF0_Pos      (0UL)          /*!< CALENDF0 (Bit 0)                                      */
46032  #define R_ADC_B0_ADCALENDSR_CALENDF0_Msk      (0x1UL)        /*!< CALENDF0 (Bitfield-Mask: 0x01)                        */
46033  #define R_ADC_B0_ADCALENDSR_CALENDF1_Pos      (1UL)          /*!< CALENDF1 (Bit 1)                                      */
46034  #define R_ADC_B0_ADCALENDSR_CALENDF1_Msk      (0x2UL)        /*!< CALENDF1 (Bitfield-Mask: 0x01)                        */
46035 /* ======================================================  ADCALENDSCR  ====================================================== */
46036  #define R_ADC_B0_ADCALENDSCR_CALENDC0_Pos     (0UL)          /*!< CALENDC0 (Bit 0)                                      */
46037  #define R_ADC_B0_ADCALENDSCR_CALENDC0_Msk     (0x1UL)        /*!< CALENDC0 (Bitfield-Mask: 0x01)                        */
46038  #define R_ADC_B0_ADCALENDSCR_CALENDC1_Pos     (1UL)          /*!< CALENDC1 (Bit 1)                                      */
46039  #define R_ADC_B0_ADCALENDSCR_CALENDC1_Msk     (0x2UL)        /*!< CALENDC1 (Bitfield-Mask: 0x01)                        */
46040 /* =======================================================  ADOVFERSR  ======================================================= */
46041  #define R_ADC_B0_ADOVFERSR_ADOVFEF0_Pos       (0UL)          /*!< ADOVFEF0 (Bit 0)                                      */
46042  #define R_ADC_B0_ADOVFERSR_ADOVFEF0_Msk       (0x1UL)        /*!< ADOVFEF0 (Bitfield-Mask: 0x01)                        */
46043  #define R_ADC_B0_ADOVFERSR_ADOVFEF1_Pos       (1UL)          /*!< ADOVFEF1 (Bit 1)                                      */
46044  #define R_ADC_B0_ADOVFERSR_ADOVFEF1_Msk       (0x2UL)        /*!< ADOVFEF1 (Bitfield-Mask: 0x01)                        */
46045 /* ======================================================  ADOVFCHSR0  ======================================================= */
46046  #define R_ADC_B0_ADOVFCHSR0_OFVCHFn_Pos       (0UL)          /*!< OFVCHFn (Bit 0)                                       */
46047  #define R_ADC_B0_ADOVFCHSR0_OFVCHFn_Msk       (0x1fffffffUL) /*!< OFVCHFn (Bitfield-Mask: 0x1fffffff)                   */
46048 /* =======================================================  ADOVFEXSR  ======================================================= */
46049  #define R_ADC_B0_ADOVFEXSR_OVFEXF0_Pos        (0UL)          /*!< OVFEXF0 (Bit 0)                                       */
46050  #define R_ADC_B0_ADOVFEXSR_OVFEXF0_Msk        (0x1UL)        /*!< OVFEXF0 (Bitfield-Mask: 0x01)                         */
46051  #define R_ADC_B0_ADOVFEXSR_OVFEXF1_Pos        (1UL)          /*!< OVFEXF1 (Bit 1)                                       */
46052  #define R_ADC_B0_ADOVFEXSR_OVFEXF1_Msk        (0x2UL)        /*!< OVFEXF1 (Bitfield-Mask: 0x01)                         */
46053  #define R_ADC_B0_ADOVFEXSR_OVFEXF2_Pos        (2UL)          /*!< OVFEXF2 (Bit 2)                                       */
46054  #define R_ADC_B0_ADOVFEXSR_OVFEXF2_Msk        (0x4UL)        /*!< OVFEXF2 (Bitfield-Mask: 0x01)                         */
46055  #define R_ADC_B0_ADOVFEXSR_OVFEXF5_Pos        (5UL)          /*!< OVFEXF5 (Bit 5)                                       */
46056  #define R_ADC_B0_ADOVFEXSR_OVFEXF5_Msk        (0x20UL)       /*!< OVFEXF5 (Bitfield-Mask: 0x01)                         */
46057  #define R_ADC_B0_ADOVFEXSR_OVFEXF6_Pos        (6UL)          /*!< OVFEXF6 (Bit 6)                                       */
46058  #define R_ADC_B0_ADOVFEXSR_OVFEXF6_Msk        (0x40UL)       /*!< OVFEXF6 (Bitfield-Mask: 0x01)                         */
46059  #define R_ADC_B0_ADOVFEXSR_OVFEXF7_Pos        (7UL)          /*!< OVFEXF7 (Bit 7)                                       */
46060  #define R_ADC_B0_ADOVFEXSR_OVFEXF7_Msk        (0x80UL)       /*!< OVFEXF7 (Bitfield-Mask: 0x01)                         */
46061  #define R_ADC_B0_ADOVFEXSR_OVFEXF8_Pos        (8UL)          /*!< OVFEXF8 (Bit 8)                                       */
46062  #define R_ADC_B0_ADOVFEXSR_OVFEXF8_Msk        (0x100UL)      /*!< OVFEXF8 (Bitfield-Mask: 0x01)                         */
46063 /* ======================================================  ADOVFERSCR  ======================================================= */
46064  #define R_ADC_B0_ADOVFERSCR_ADOVFEC0_Pos      (0UL)          /*!< ADOVFEC0 (Bit 0)                                      */
46065  #define R_ADC_B0_ADOVFERSCR_ADOVFEC0_Msk      (0x1UL)        /*!< ADOVFEC0 (Bitfield-Mask: 0x01)                        */
46066  #define R_ADC_B0_ADOVFERSCR_ADOVFEC1_Pos      (1UL)          /*!< ADOVFEC1 (Bit 1)                                      */
46067  #define R_ADC_B0_ADOVFERSCR_ADOVFEC1_Msk      (0x2UL)        /*!< ADOVFEC1 (Bitfield-Mask: 0x01)                        */
46068 /* ======================================================  ADOVFCHSCR0  ====================================================== */
46069  #define R_ADC_B0_ADOVFCHSCR0_OVFCHCn_Pos      (0UL)          /*!< OVFCHCn (Bit 0)                                       */
46070  #define R_ADC_B0_ADOVFCHSCR0_OVFCHCn_Msk      (0x1fffffffUL) /*!< OVFCHCn (Bitfield-Mask: 0x1fffffff)                   */
46071 /* ======================================================  ADOVFEXSCR  ======================================================= */
46072  #define R_ADC_B0_ADOVFEXSCR_OVFEXC0_Pos       (0UL)          /*!< OVFEXC0 (Bit 0)                                       */
46073  #define R_ADC_B0_ADOVFEXSCR_OVFEXC0_Msk       (0x1UL)        /*!< OVFEXC0 (Bitfield-Mask: 0x01)                         */
46074  #define R_ADC_B0_ADOVFEXSCR_OVFEXC1_Pos       (1UL)          /*!< OVFEXC1 (Bit 1)                                       */
46075  #define R_ADC_B0_ADOVFEXSCR_OVFEXC1_Msk       (0x2UL)        /*!< OVFEXC1 (Bitfield-Mask: 0x01)                         */
46076  #define R_ADC_B0_ADOVFEXSCR_OVFEXC2_Pos       (2UL)          /*!< OVFEXC2 (Bit 2)                                       */
46077  #define R_ADC_B0_ADOVFEXSCR_OVFEXC2_Msk       (0x4UL)        /*!< OVFEXC2 (Bitfield-Mask: 0x01)                         */
46078  #define R_ADC_B0_ADOVFEXSCR_OVFEXC5_Pos       (5UL)          /*!< OVFEXC5 (Bit 5)                                       */
46079  #define R_ADC_B0_ADOVFEXSCR_OVFEXC5_Msk       (0x20UL)       /*!< OVFEXC5 (Bitfield-Mask: 0x01)                         */
46080  #define R_ADC_B0_ADOVFEXSCR_OVFEXC6_Pos       (6UL)          /*!< OVFEXC6 (Bit 6)                                       */
46081  #define R_ADC_B0_ADOVFEXSCR_OVFEXC6_Msk       (0x40UL)       /*!< OVFEXC6 (Bitfield-Mask: 0x01)                         */
46082  #define R_ADC_B0_ADOVFEXSCR_OVFEXC7_Pos       (7UL)          /*!< OVFEXC7 (Bit 7)                                       */
46083  #define R_ADC_B0_ADOVFEXSCR_OVFEXC7_Msk       (0x80UL)       /*!< OVFEXC7 (Bitfield-Mask: 0x01)                         */
46084  #define R_ADC_B0_ADOVFEXSCR_OVFEXC8_Pos       (8UL)          /*!< OVFEXC8 (Bit 8)                                       */
46085  #define R_ADC_B0_ADOVFEXSCR_OVFEXC8_Msk       (0x100UL)      /*!< OVFEXC8 (Bitfield-Mask: 0x01)                         */
46086 /* =======================================================  ADFIFOSR0  ======================================================= */
46087  #define R_ADC_B0_ADFIFOSR0_FIFOST0_Pos        (0UL)          /*!< FIFOST0 (Bit 0)                                       */
46088  #define R_ADC_B0_ADFIFOSR0_FIFOST0_Msk        (0xfUL)        /*!< FIFOST0 (Bitfield-Mask: 0x0f)                         */
46089  #define R_ADC_B0_ADFIFOSR0_FIFOST1_Pos        (16UL)         /*!< FIFOST1 (Bit 16)                                      */
46090  #define R_ADC_B0_ADFIFOSR0_FIFOST1_Msk        (0xf0000UL)    /*!< FIFOST1 (Bitfield-Mask: 0x0f)                         */
46091 /* =======================================================  ADFIFOSR1  ======================================================= */
46092  #define R_ADC_B0_ADFIFOSR1_FIFOST2_Pos        (0UL)          /*!< FIFOST2 (Bit 0)                                       */
46093  #define R_ADC_B0_ADFIFOSR1_FIFOST2_Msk        (0xfUL)        /*!< FIFOST2 (Bitfield-Mask: 0x0f)                         */
46094  #define R_ADC_B0_ADFIFOSR1_FIFOST3_Pos        (16UL)         /*!< FIFOST3 (Bit 16)                                      */
46095  #define R_ADC_B0_ADFIFOSR1_FIFOST3_Msk        (0xf0000UL)    /*!< FIFOST3 (Bitfield-Mask: 0x0f)                         */
46096 /* =======================================================  ADFIFOSR2  ======================================================= */
46097  #define R_ADC_B0_ADFIFOSR2_FIFOST4_Pos        (0UL)          /*!< FIFOST4 (Bit 0)                                       */
46098  #define R_ADC_B0_ADFIFOSR2_FIFOST4_Msk        (0xfUL)        /*!< FIFOST4 (Bitfield-Mask: 0x0f)                         */
46099  #define R_ADC_B0_ADFIFOSR2_FIFOST5_Pos        (16UL)         /*!< FIFOST5 (Bit 16)                                      */
46100  #define R_ADC_B0_ADFIFOSR2_FIFOST5_Msk        (0xf0000UL)    /*!< FIFOST5 (Bitfield-Mask: 0x0f)                         */
46101 /* =======================================================  ADFIFOSR3  ======================================================= */
46102  #define R_ADC_B0_ADFIFOSR3_FIFOST6_Pos        (0UL)          /*!< FIFOST6 (Bit 0)                                       */
46103  #define R_ADC_B0_ADFIFOSR3_FIFOST6_Msk        (0xfUL)        /*!< FIFOST6 (Bitfield-Mask: 0x0f)                         */
46104  #define R_ADC_B0_ADFIFOSR3_FIFOST7_Pos        (16UL)         /*!< FIFOST7 (Bit 16)                                      */
46105  #define R_ADC_B0_ADFIFOSR3_FIFOST7_Msk        (0xf0000UL)    /*!< FIFOST7 (Bitfield-Mask: 0x0f)                         */
46106 /* =======================================================  ADFIFOSR4  ======================================================= */
46107  #define R_ADC_B0_ADFIFOSR4_FIFOST8_Pos        (0UL)          /*!< FIFOST8 (Bit 0)                                       */
46108  #define R_ADC_B0_ADFIFOSR4_FIFOST8_Msk        (0xfUL)        /*!< FIFOST8 (Bitfield-Mask: 0x0f)                         */
46109 /* =======================================================  ADFIFODCR  ======================================================= */
46110  #define R_ADC_B0_ADFIFODCR_FIFODCn_Pos        (0UL)          /*!< FIFODCn (Bit 0)                                       */
46111  #define R_ADC_B0_ADFIFODCR_FIFODCn_Msk        (0x1ffUL)      /*!< FIFODCn (Bitfield-Mask: 0x1ff)                        */
46112 /* ======================================================  ADFIFOERSR  ======================================================= */
46113  #define R_ADC_B0_ADFIFOERSR_FIFOOVFn_Pos      (0UL)          /*!< FIFOOVFn (Bit 0)                                      */
46114  #define R_ADC_B0_ADFIFOERSR_FIFOOVFn_Msk      (0x1ffUL)      /*!< FIFOOVFn (Bitfield-Mask: 0x1ff)                       */
46115  #define R_ADC_B0_ADFIFOERSR_FIFOFLFn_Pos      (16UL)         /*!< FIFOFLFn (Bit 16)                                     */
46116  #define R_ADC_B0_ADFIFOERSR_FIFOFLFn_Msk      (0x1ff0000UL)  /*!< FIFOFLFn (Bitfield-Mask: 0x1ff)                       */
46117 /* ======================================================  ADFIFOERSCR  ====================================================== */
46118  #define R_ADC_B0_ADFIFOERSCR_FIFOOVFCn_Pos    (0UL)          /*!< FIFOOVFCn (Bit 0)                                     */
46119  #define R_ADC_B0_ADFIFOERSCR_FIFOOVFCn_Msk    (0x1ffUL)      /*!< FIFOOVFCn (Bitfield-Mask: 0x1ff)                      */
46120  #define R_ADC_B0_ADFIFOERSCR_FIFOFLCn_Pos     (16UL)         /*!< FIFOFLCn (Bit 16)                                     */
46121  #define R_ADC_B0_ADFIFOERSCR_FIFOFLCn_Msk     (0x1ff0000UL)  /*!< FIFOFLCn (Bitfield-Mask: 0x1ff)                       */
46122 /* =======================================================  ADCMPTBSR  ======================================================= */
46123  #define R_ADC_B0_ADCMPTBSR_CMPTBFn_Pos        (0UL)          /*!< CMPTBFn (Bit 0)                                       */
46124  #define R_ADC_B0_ADCMPTBSR_CMPTBFn_Msk        (0xffUL)       /*!< CMPTBFn (Bitfield-Mask: 0xff)                         */
46125 /* ======================================================  ADCMPTBSCR  ======================================================= */
46126  #define R_ADC_B0_ADCMPTBSCR_CMPTBCn_Pos       (0UL)          /*!< CMPTBCn (Bit 0)                                       */
46127  #define R_ADC_B0_ADCMPTBSCR_CMPTBCn_Msk       (0xffUL)       /*!< CMPTBCn (Bitfield-Mask: 0xff)                         */
46128 /* ======================================================  ADCMPCHSR0  ======================================================= */
46129  #define R_ADC_B0_ADCMPCHSR0_CMPCHFn_Pos       (0UL)          /*!< CMPCHFn (Bit 0)                                       */
46130  #define R_ADC_B0_ADCMPCHSR0_CMPCHFn_Msk       (0x1fffffffUL) /*!< CMPCHFn (Bitfield-Mask: 0x1fffffff)                   */
46131 /* =======================================================  ADCMPEXSR  ======================================================= */
46132  #define R_ADC_B0_ADCMPEXSR_CMPEXF0_Pos        (0UL)          /*!< CMPEXF0 (Bit 0)                                       */
46133  #define R_ADC_B0_ADCMPEXSR_CMPEXF0_Msk        (0x1UL)        /*!< CMPEXF0 (Bitfield-Mask: 0x01)                         */
46134  #define R_ADC_B0_ADCMPEXSR_CMPEXF1_Pos        (1UL)          /*!< CMPEXF1 (Bit 1)                                       */
46135  #define R_ADC_B0_ADCMPEXSR_CMPEXF1_Msk        (0x2UL)        /*!< CMPEXF1 (Bitfield-Mask: 0x01)                         */
46136  #define R_ADC_B0_ADCMPEXSR_CMPEXF2_Pos        (2UL)          /*!< CMPEXF2 (Bit 2)                                       */
46137  #define R_ADC_B0_ADCMPEXSR_CMPEXF2_Msk        (0x4UL)        /*!< CMPEXF2 (Bitfield-Mask: 0x01)                         */
46138  #define R_ADC_B0_ADCMPEXSR_CMPEXF5_Pos        (5UL)          /*!< CMPEXF5 (Bit 5)                                       */
46139  #define R_ADC_B0_ADCMPEXSR_CMPEXF5_Msk        (0x20UL)       /*!< CMPEXF5 (Bitfield-Mask: 0x01)                         */
46140  #define R_ADC_B0_ADCMPEXSR_CMPEXF6_Pos        (6UL)          /*!< CMPEXF6 (Bit 6)                                       */
46141  #define R_ADC_B0_ADCMPEXSR_CMPEXF6_Msk        (0x40UL)       /*!< CMPEXF6 (Bitfield-Mask: 0x01)                         */
46142  #define R_ADC_B0_ADCMPEXSR_CMPEXF7_Pos        (7UL)          /*!< CMPEXF7 (Bit 7)                                       */
46143  #define R_ADC_B0_ADCMPEXSR_CMPEXF7_Msk        (0x80UL)       /*!< CMPEXF7 (Bitfield-Mask: 0x01)                         */
46144  #define R_ADC_B0_ADCMPEXSR_CMPEXF8_Pos        (8UL)          /*!< CMPEXF8 (Bit 8)                                       */
46145  #define R_ADC_B0_ADCMPEXSR_CMPEXF8_Msk        (0x100UL)      /*!< CMPEXF8 (Bitfield-Mask: 0x01)                         */
46146 /* ======================================================  ADCMPCHSCR0  ====================================================== */
46147  #define R_ADC_B0_ADCMPCHSCR0_CMPCHCn_Pos      (0UL)          /*!< CMPCHCn (Bit 0)                                       */
46148  #define R_ADC_B0_ADCMPCHSCR0_CMPCHCn_Msk      (0x1fffffffUL) /*!< CMPCHCn (Bitfield-Mask: 0x1fffffff)                   */
46149 /* ======================================================  ADCMPEXSCR  ======================================================= */
46150  #define R_ADC_B0_ADCMPEXSCR_CMPEXC0_Pos       (0UL)          /*!< CMPEXC0 (Bit 0)                                       */
46151  #define R_ADC_B0_ADCMPEXSCR_CMPEXC0_Msk       (0x1UL)        /*!< CMPEXC0 (Bitfield-Mask: 0x01)                         */
46152  #define R_ADC_B0_ADCMPEXSCR_CMPEXC1_Pos       (1UL)          /*!< CMPEXC1 (Bit 1)                                       */
46153  #define R_ADC_B0_ADCMPEXSCR_CMPEXC1_Msk       (0x2UL)        /*!< CMPEXC1 (Bitfield-Mask: 0x01)                         */
46154  #define R_ADC_B0_ADCMPEXSCR_CMPEXC2_Pos       (2UL)          /*!< CMPEXC2 (Bit 2)                                       */
46155  #define R_ADC_B0_ADCMPEXSCR_CMPEXC2_Msk       (0x4UL)        /*!< CMPEXC2 (Bitfield-Mask: 0x01)                         */
46156  #define R_ADC_B0_ADCMPEXSCR_CMPEXC5_Pos       (5UL)          /*!< CMPEXC5 (Bit 5)                                       */
46157  #define R_ADC_B0_ADCMPEXSCR_CMPEXC5_Msk       (0x20UL)       /*!< CMPEXC5 (Bitfield-Mask: 0x01)                         */
46158  #define R_ADC_B0_ADCMPEXSCR_CMPEXC6_Pos       (6UL)          /*!< CMPEXC6 (Bit 6)                                       */
46159  #define R_ADC_B0_ADCMPEXSCR_CMPEXC6_Msk       (0x40UL)       /*!< CMPEXC6 (Bitfield-Mask: 0x01)                         */
46160  #define R_ADC_B0_ADCMPEXSCR_CMPEXC7_Pos       (7UL)          /*!< CMPEXC7 (Bit 7)                                       */
46161  #define R_ADC_B0_ADCMPEXSCR_CMPEXC7_Msk       (0x80UL)       /*!< CMPEXC7 (Bitfield-Mask: 0x01)                         */
46162  #define R_ADC_B0_ADCMPEXSCR_CMPEXC8_Pos       (8UL)          /*!< CMPEXC8 (Bit 8)                                       */
46163  #define R_ADC_B0_ADCMPEXSCR_CMPEXC8_Msk       (0x100UL)      /*!< CMPEXC8 (Bitfield-Mask: 0x01)                         */
46164 /* =======================================================  ADLIMGRSR  ======================================================= */
46165  #define R_ADC_B0_ADLIMGRSR_LIMGRFn_Pos        (0UL)          /*!< LIMGRFn (Bit 0)                                       */
46166  #define R_ADC_B0_ADLIMGRSR_LIMGRFn_Msk        (0x1ffUL)      /*!< LIMGRFn (Bitfield-Mask: 0x1ff)                        */
46167 /* ======================================================  ADLIMCHSR0  ======================================================= */
46168  #define R_ADC_B0_ADLIMCHSR0_LIMCHFn_Pos       (0UL)          /*!< LIMCHFn (Bit 0)                                       */
46169  #define R_ADC_B0_ADLIMCHSR0_LIMCHFn_Msk       (0x1fffffffUL) /*!< LIMCHFn (Bitfield-Mask: 0x1fffffff)                   */
46170 /* =======================================================  ADLIMEXSR  ======================================================= */
46171  #define R_ADC_B0_ADLIMEXSR_LIMEXF0_Pos        (0UL)          /*!< LIMEXF0 (Bit 0)                                       */
46172  #define R_ADC_B0_ADLIMEXSR_LIMEXF0_Msk        (0x1UL)        /*!< LIMEXF0 (Bitfield-Mask: 0x01)                         */
46173  #define R_ADC_B0_ADLIMEXSR_LIMEXF1_Pos        (1UL)          /*!< LIMEXF1 (Bit 1)                                       */
46174  #define R_ADC_B0_ADLIMEXSR_LIMEXF1_Msk        (0x2UL)        /*!< LIMEXF1 (Bitfield-Mask: 0x01)                         */
46175  #define R_ADC_B0_ADLIMEXSR_LIMEXF2_Pos        (2UL)          /*!< LIMEXF2 (Bit 2)                                       */
46176  #define R_ADC_B0_ADLIMEXSR_LIMEXF2_Msk        (0x4UL)        /*!< LIMEXF2 (Bitfield-Mask: 0x01)                         */
46177  #define R_ADC_B0_ADLIMEXSR_LIMEXF5_Pos        (5UL)          /*!< LIMEXF5 (Bit 5)                                       */
46178  #define R_ADC_B0_ADLIMEXSR_LIMEXF5_Msk        (0x20UL)       /*!< LIMEXF5 (Bitfield-Mask: 0x01)                         */
46179  #define R_ADC_B0_ADLIMEXSR_LIMEXF6_Pos        (6UL)          /*!< LIMEXF6 (Bit 6)                                       */
46180  #define R_ADC_B0_ADLIMEXSR_LIMEXF6_Msk        (0x40UL)       /*!< LIMEXF6 (Bitfield-Mask: 0x01)                         */
46181  #define R_ADC_B0_ADLIMEXSR_LIMEXF7_Pos        (7UL)          /*!< LIMEXF7 (Bit 7)                                       */
46182  #define R_ADC_B0_ADLIMEXSR_LIMEXF7_Msk        (0x80UL)       /*!< LIMEXF7 (Bitfield-Mask: 0x01)                         */
46183  #define R_ADC_B0_ADLIMEXSR_LIMEXF8_Pos        (8UL)          /*!< LIMEXF8 (Bit 8)                                       */
46184  #define R_ADC_B0_ADLIMEXSR_LIMEXF8_Msk        (0x100UL)      /*!< LIMEXF8 (Bitfield-Mask: 0x01)                         */
46185 /* ======================================================  ADLIMGRSCR  ======================================================= */
46186  #define R_ADC_B0_ADLIMGRSCR_LIMGRCn_Pos       (0UL)          /*!< LIMGRCn (Bit 0)                                       */
46187  #define R_ADC_B0_ADLIMGRSCR_LIMGRCn_Msk       (0x1ffUL)      /*!< LIMGRCn (Bitfield-Mask: 0x1ff)                        */
46188 /* ======================================================  ADLIMCHSCR0  ====================================================== */
46189  #define R_ADC_B0_ADLIMCHSCR0_LIMCHCn_Pos      (0UL)          /*!< LIMCHCn (Bit 0)                                       */
46190  #define R_ADC_B0_ADLIMCHSCR0_LIMCHCn_Msk      (0x1fffffffUL) /*!< LIMCHCn (Bitfield-Mask: 0x1fffffff)                   */
46191 /* ======================================================  ADLIMEXSCR  ======================================================= */
46192  #define R_ADC_B0_ADLIMEXSCR_LIMEXF0_Pos       (0UL)          /*!< LIMEXF0 (Bit 0)                                       */
46193  #define R_ADC_B0_ADLIMEXSCR_LIMEXF0_Msk       (0x1UL)        /*!< LIMEXF0 (Bitfield-Mask: 0x01)                         */
46194  #define R_ADC_B0_ADLIMEXSCR_LIMEXF1_Pos       (1UL)          /*!< LIMEXF1 (Bit 1)                                       */
46195  #define R_ADC_B0_ADLIMEXSCR_LIMEXF1_Msk       (0x2UL)        /*!< LIMEXF1 (Bitfield-Mask: 0x01)                         */
46196  #define R_ADC_B0_ADLIMEXSCR_LIMEXF2_Pos       (2UL)          /*!< LIMEXF2 (Bit 2)                                       */
46197  #define R_ADC_B0_ADLIMEXSCR_LIMEXF2_Msk       (0x4UL)        /*!< LIMEXF2 (Bitfield-Mask: 0x01)                         */
46198  #define R_ADC_B0_ADLIMEXSCR_LIMEXF5_Pos       (5UL)          /*!< LIMEXF5 (Bit 5)                                       */
46199  #define R_ADC_B0_ADLIMEXSCR_LIMEXF5_Msk       (0x20UL)       /*!< LIMEXF5 (Bitfield-Mask: 0x01)                         */
46200  #define R_ADC_B0_ADLIMEXSCR_LIMEXF6_Pos       (6UL)          /*!< LIMEXF6 (Bit 6)                                       */
46201  #define R_ADC_B0_ADLIMEXSCR_LIMEXF6_Msk       (0x40UL)       /*!< LIMEXF6 (Bitfield-Mask: 0x01)                         */
46202  #define R_ADC_B0_ADLIMEXSCR_LIMEXF7_Pos       (7UL)          /*!< LIMEXF7 (Bit 7)                                       */
46203  #define R_ADC_B0_ADLIMEXSCR_LIMEXF7_Msk       (0x80UL)       /*!< LIMEXF7 (Bitfield-Mask: 0x01)                         */
46204  #define R_ADC_B0_ADLIMEXSCR_LIMEXF8_Pos       (8UL)          /*!< LIMEXF8 (Bit 8)                                       */
46205  #define R_ADC_B0_ADLIMEXSCR_LIMEXF8_Msk       (0x100UL)      /*!< LIMEXF8 (Bitfield-Mask: 0x01)                         */
46206 /* ======================================================  ADSCANENDSR  ====================================================== */
46207  #define R_ADC_B0_ADSCANENDSR_SCENDFn_Pos      (0UL)          /*!< SCENDFn (Bit 0)                                       */
46208  #define R_ADC_B0_ADSCANENDSR_SCENDFn_Msk      (0x1ffUL)      /*!< SCENDFn (Bitfield-Mask: 0x1ff)                        */
46209 /* =====================================================  ADSCANENDSCR  ====================================================== */
46210  #define R_ADC_B0_ADSCANENDSCR_SCENDCn_Pos     (0UL)          /*!< SCENDCn (Bit 0)                                       */
46211  #define R_ADC_B0_ADSCANENDSCR_SCENDCn_Msk     (0x1ffUL)      /*!< SCENDCn (Bitfield-Mask: 0x1ff)                        */
46212 /* =========================================================  ADDR  ========================================================== */
46213  #define R_ADC_B0_ADDR_DATA_Pos                (0UL)          /*!< DATA (Bit 0)                                          */
46214  #define R_ADC_B0_ADDR_DATA_Msk                (0xffffUL)     /*!< DATA (Bitfield-Mask: 0xffff)                          */
46215  #define R_ADC_B0_ADDR_ERR_Pos                 (31UL)         /*!< ERR (Bit 31)                                          */
46216  #define R_ADC_B0_ADDR_ERR_Msk                 (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01)                             */
46217 /* ========================================================  ADEXDR  ========================================================= */
46218  #define R_ADC_B0_ADEXDR_DATA_Pos              (0UL)          /*!< DATA (Bit 0)                                          */
46219  #define R_ADC_B0_ADEXDR_DATA_Msk              (0xffffUL)     /*!< DATA (Bitfield-Mask: 0xffff)                          */
46220  #define R_ADC_B0_ADEXDR_DIAGSR_Pos            (24UL)         /*!< DIAGSR (Bit 24)                                       */
46221  #define R_ADC_B0_ADEXDR_DIAGSR_Msk            (0x7000000UL)  /*!< DIAGSR (Bitfield-Mask: 0x07)                          */
46222  #define R_ADC_B0_ADEXDR_ERR_Pos               (31UL)         /*!< ERR (Bit 31)                                          */
46223  #define R_ADC_B0_ADEXDR_ERR_Msk               (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01)                             */
46224 /* =======================================================  ADFIFODR0  ======================================================= */
46225  #define R_ADC_B0_ADFIFODR0_DATA_Pos           (0UL)          /*!< DATA (Bit 0)                                          */
46226  #define R_ADC_B0_ADFIFODR0_DATA_Msk           (0xffffUL)     /*!< DATA (Bitfield-Mask: 0xffff)                          */
46227  #define R_ADC_B0_ADFIFODR0_CH_Pos             (24UL)         /*!< CH (Bit 24)                                           */
46228  #define R_ADC_B0_ADFIFODR0_CH_Msk             (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f)                              */
46229  #define R_ADC_B0_ADFIFODR0_ERR_Pos            (31UL)         /*!< ERR (Bit 31)                                          */
46230  #define R_ADC_B0_ADFIFODR0_ERR_Msk            (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01)                             */
46231 /* =======================================================  ADFIFODR1  ======================================================= */
46232  #define R_ADC_B0_ADFIFODR1_DATA_Pos           (0UL)          /*!< DATA (Bit 0)                                          */
46233  #define R_ADC_B0_ADFIFODR1_DATA_Msk           (0xffffUL)     /*!< DATA (Bitfield-Mask: 0xffff)                          */
46234  #define R_ADC_B0_ADFIFODR1_CH_Pos             (24UL)         /*!< CH (Bit 24)                                           */
46235  #define R_ADC_B0_ADFIFODR1_CH_Msk             (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f)                              */
46236  #define R_ADC_B0_ADFIFODR1_ERR_Pos            (31UL)         /*!< ERR (Bit 31)                                          */
46237  #define R_ADC_B0_ADFIFODR1_ERR_Msk            (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01)                             */
46238 /* =======================================================  ADFIFODR2  ======================================================= */
46239  #define R_ADC_B0_ADFIFODR2_DATA_Pos           (0UL)          /*!< DATA (Bit 0)                                          */
46240  #define R_ADC_B0_ADFIFODR2_DATA_Msk           (0xffffUL)     /*!< DATA (Bitfield-Mask: 0xffff)                          */
46241  #define R_ADC_B0_ADFIFODR2_CH_Pos             (24UL)         /*!< CH (Bit 24)                                           */
46242  #define R_ADC_B0_ADFIFODR2_CH_Msk             (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f)                              */
46243  #define R_ADC_B0_ADFIFODR2_ERR_Pos            (31UL)         /*!< ERR (Bit 31)                                          */
46244  #define R_ADC_B0_ADFIFODR2_ERR_Msk            (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01)                             */
46245 /* =======================================================  ADFIFODR3  ======================================================= */
46246  #define R_ADC_B0_ADFIFODR3_DATA_Pos           (0UL)          /*!< DATA (Bit 0)                                          */
46247  #define R_ADC_B0_ADFIFODR3_DATA_Msk           (0xffffUL)     /*!< DATA (Bitfield-Mask: 0xffff)                          */
46248  #define R_ADC_B0_ADFIFODR3_CH_Pos             (24UL)         /*!< CH (Bit 24)                                           */
46249  #define R_ADC_B0_ADFIFODR3_CH_Msk             (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f)                              */
46250  #define R_ADC_B0_ADFIFODR3_ERR_Pos            (31UL)         /*!< ERR (Bit 31)                                          */
46251  #define R_ADC_B0_ADFIFODR3_ERR_Msk            (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01)                             */
46252 /* =======================================================  ADFIFODR4  ======================================================= */
46253  #define R_ADC_B0_ADFIFODR4_DATA_Pos           (0UL)          /*!< DATA (Bit 0)                                          */
46254  #define R_ADC_B0_ADFIFODR4_DATA_Msk           (0xffffUL)     /*!< DATA (Bitfield-Mask: 0xffff)                          */
46255  #define R_ADC_B0_ADFIFODR4_CH_Pos             (24UL)         /*!< CH (Bit 24)                                           */
46256  #define R_ADC_B0_ADFIFODR4_CH_Msk             (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f)                              */
46257  #define R_ADC_B0_ADFIFODR4_ERR_Pos            (31UL)         /*!< ERR (Bit 31)                                          */
46258  #define R_ADC_B0_ADFIFODR4_ERR_Msk            (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01)                             */
46259 /* =======================================================  ADFIFODR5  ======================================================= */
46260  #define R_ADC_B0_ADFIFODR5_DATA_Pos           (0UL)          /*!< DATA (Bit 0)                                          */
46261  #define R_ADC_B0_ADFIFODR5_DATA_Msk           (0xffffUL)     /*!< DATA (Bitfield-Mask: 0xffff)                          */
46262  #define R_ADC_B0_ADFIFODR5_CH_Pos             (24UL)         /*!< CH (Bit 24)                                           */
46263  #define R_ADC_B0_ADFIFODR5_CH_Msk             (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f)                              */
46264  #define R_ADC_B0_ADFIFODR5_ERR_Pos            (31UL)         /*!< ERR (Bit 31)                                          */
46265  #define R_ADC_B0_ADFIFODR5_ERR_Msk            (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01)                             */
46266 /* =======================================================  ADFIFODR6  ======================================================= */
46267  #define R_ADC_B0_ADFIFODR6_DATA_Pos           (0UL)          /*!< DATA (Bit 0)                                          */
46268  #define R_ADC_B0_ADFIFODR6_DATA_Msk           (0xffffUL)     /*!< DATA (Bitfield-Mask: 0xffff)                          */
46269  #define R_ADC_B0_ADFIFODR6_CH_Pos             (24UL)         /*!< CH (Bit 24)                                           */
46270  #define R_ADC_B0_ADFIFODR6_CH_Msk             (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f)                              */
46271  #define R_ADC_B0_ADFIFODR6_ERR_Pos            (31UL)         /*!< ERR (Bit 31)                                          */
46272  #define R_ADC_B0_ADFIFODR6_ERR_Msk            (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01)                             */
46273 /* =======================================================  ADFIFODR7  ======================================================= */
46274  #define R_ADC_B0_ADFIFODR7_DATA_Pos           (0UL)          /*!< DATA (Bit 0)                                          */
46275  #define R_ADC_B0_ADFIFODR7_DATA_Msk           (0xffffUL)     /*!< DATA (Bitfield-Mask: 0xffff)                          */
46276  #define R_ADC_B0_ADFIFODR7_CH_Pos             (24UL)         /*!< CH (Bit 24)                                           */
46277  #define R_ADC_B0_ADFIFODR7_CH_Msk             (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f)                              */
46278  #define R_ADC_B0_ADFIFODR7_ERR_Pos            (31UL)         /*!< ERR (Bit 31)                                          */
46279  #define R_ADC_B0_ADFIFODR7_ERR_Msk            (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01)                             */
46280 /* =======================================================  ADFIFODR8  ======================================================= */
46281  #define R_ADC_B0_ADFIFODR8_DATA_Pos           (0UL)          /*!< DATA (Bit 0)                                          */
46282  #define R_ADC_B0_ADFIFODR8_DATA_Msk           (0xffffUL)     /*!< DATA (Bitfield-Mask: 0xffff)                          */
46283  #define R_ADC_B0_ADFIFODR8_CH_Pos             (24UL)         /*!< CH (Bit 24)                                           */
46284  #define R_ADC_B0_ADFIFODR8_CH_Msk             (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f)                              */
46285  #define R_ADC_B0_ADFIFODR8_ERR_Pos            (31UL)         /*!< ERR (Bit 31)                                          */
46286  #define R_ADC_B0_ADFIFODR8_ERR_Msk            (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01)                             */
46287 
46288 /* =========================================================================================================================== */
46289 /* ================                                          R_DOC_B                                          ================ */
46290 /* =========================================================================================================================== */
46291 
46292 /* =========================================================  DOCR  ========================================================== */
46293  #define R_DOC_B_DOCR_OMS_Pos         (0UL)    /*!< OMS (Bit 0)                                           */
46294  #define R_DOC_B_DOCR_OMS_Msk         (0x3UL)  /*!< OMS (Bitfield-Mask: 0x03)                             */
46295  #define R_DOC_B_DOCR_DOBW_Pos        (3UL)    /*!< DOBW (Bit 3)                                          */
46296  #define R_DOC_B_DOCR_DOBW_Msk        (0x8UL)  /*!< DOBW (Bitfield-Mask: 0x01)                            */
46297  #define R_DOC_B_DOCR_DCSEL_Pos       (4UL)    /*!< DCSEL (Bit 4)                                         */
46298  #define R_DOC_B_DOCR_DCSEL_Msk       (0x70UL) /*!< DCSEL (Bitfield-Mask: 0x07)                           */
46299  #define R_DOC_B_DOCR_DOPCIE_Pos      (7UL)    /*!< DOPCIE (Bit 7)                                        */
46300  #define R_DOC_B_DOCR_DOPCIE_Msk      (0x80UL) /*!< DOPCIE (Bitfield-Mask: 0x01)                          */
46301 /* =========================================================  DOSR  ========================================================== */
46302  #define R_DOC_B_DOSR_DOPCF_Pos       (0UL)    /*!< DOPCF (Bit 0)                                         */
46303  #define R_DOC_B_DOSR_DOPCF_Msk       (0x1UL)  /*!< DOPCF (Bitfield-Mask: 0x01)                           */
46304 /* =========================================================  DOSCR  ========================================================= */
46305  #define R_DOC_B_DOSCR_DOPCFCL_Pos    (0UL)    /*!< DOPCFCL (Bit 0)                                       */
46306  #define R_DOC_B_DOSCR_DOPCFCL_Msk    (0x1UL)  /*!< DOPCFCL (Bitfield-Mask: 0x01)                         */
46307 /* =========================================================  DODIR  ========================================================= */
46308 /* ========================================================  DODSR0  ========================================================= */
46309 /* ========================================================  DODSR1  ========================================================= */
46310 
46311 /* =========================================================================================================================== */
46312 /* ================                                         R_SCI_B0                                          ================ */
46313 /* =========================================================================================================================== */
46314 
46315 /* ==========================================================  RDR  ========================================================== */
46316  #define R_SCI_B0_RDR_RDAT_Pos           (0UL)          /*!< RDAT (Bit 0)                                          */
46317  #define R_SCI_B0_RDR_RDAT_Msk           (0x1ffUL)      /*!< RDAT (Bitfield-Mask: 0x1ff)                           */
46318  #define R_SCI_B0_RDR_MPB_Pos            (9UL)          /*!< MPB (Bit 9)                                           */
46319  #define R_SCI_B0_RDR_MPB_Msk            (0x200UL)      /*!< MPB (Bitfield-Mask: 0x01)                             */
46320  #define R_SCI_B0_RDR_DR_Pos             (10UL)         /*!< DR (Bit 10)                                           */
46321  #define R_SCI_B0_RDR_DR_Msk             (0x400UL)      /*!< DR (Bitfield-Mask: 0x01)                              */
46322  #define R_SCI_B0_RDR_FPER_Pos           (11UL)         /*!< FPER (Bit 11)                                         */
46323  #define R_SCI_B0_RDR_FPER_Msk           (0x800UL)      /*!< FPER (Bitfield-Mask: 0x01)                            */
46324  #define R_SCI_B0_RDR_FFER_Pos           (12UL)         /*!< FFER (Bit 12)                                         */
46325  #define R_SCI_B0_RDR_FFER_Msk           (0x1000UL)     /*!< FFER (Bitfield-Mask: 0x01)                            */
46326  #define R_SCI_B0_RDR_ORER_Pos           (24UL)         /*!< ORER (Bit 24)                                         */
46327  #define R_SCI_B0_RDR_ORER_Msk           (0x1000000UL)  /*!< ORER (Bitfield-Mask: 0x01)                            */
46328  #define R_SCI_B0_RDR_PER_Pos            (27UL)         /*!< PER (Bit 27)                                          */
46329  #define R_SCI_B0_RDR_PER_Msk            (0x8000000UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
46330  #define R_SCI_B0_RDR_FER_Pos            (28UL)         /*!< FER (Bit 28)                                          */
46331  #define R_SCI_B0_RDR_FER_Msk            (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
46332 /* ==========================================================  TDR  ========================================================== */
46333  #define R_SCI_B0_TDR_TDAT_Pos           (0UL)          /*!< TDAT (Bit 0)                                          */
46334  #define R_SCI_B0_TDR_TDAT_Msk           (0x1ffUL)      /*!< TDAT (Bitfield-Mask: 0x1ff)                           */
46335  #define R_SCI_B0_TDR_MPBT_Pos           (9UL)          /*!< MPBT (Bit 9)                                          */
46336  #define R_SCI_B0_TDR_MPBT_Msk           (0x200UL)      /*!< MPBT (Bitfield-Mask: 0x01)                            */
46337  #define R_SCI_B0_TDR_TSYNC_Pos          (12UL)         /*!< TSYNC (Bit 12)                                        */
46338  #define R_SCI_B0_TDR_TSYNC_Msk          (0x1000UL)     /*!< TSYNC (Bitfield-Mask: 0x01)                           */
46339 /* =========================================================  CCR0  ========================================================== */
46340  #define R_SCI_B0_CCR0_RE_Pos            (0UL)          /*!< RE (Bit 0)                                            */
46341  #define R_SCI_B0_CCR0_RE_Msk            (0x1UL)        /*!< RE (Bitfield-Mask: 0x01)                              */
46342  #define R_SCI_B0_CCR0_TE_Pos            (4UL)          /*!< TE (Bit 4)                                            */
46343  #define R_SCI_B0_CCR0_TE_Msk            (0x10UL)       /*!< TE (Bitfield-Mask: 0x01)                              */
46344  #define R_SCI_B0_CCR0_MPIE_Pos          (8UL)          /*!< MPIE (Bit 8)                                          */
46345  #define R_SCI_B0_CCR0_MPIE_Msk          (0x100UL)      /*!< MPIE (Bitfield-Mask: 0x01)                            */
46346  #define R_SCI_B0_CCR0_DCME_Pos          (9UL)          /*!< DCME (Bit 9)                                          */
46347  #define R_SCI_B0_CCR0_DCME_Msk          (0x200UL)      /*!< DCME (Bitfield-Mask: 0x01)                            */
46348  #define R_SCI_B0_CCR0_IDSEL_Pos         (10UL)         /*!< IDSEL (Bit 10)                                        */
46349  #define R_SCI_B0_CCR0_IDSEL_Msk         (0x400UL)      /*!< IDSEL (Bitfield-Mask: 0x01)                           */
46350  #define R_SCI_B0_CCR0_RIE_Pos           (16UL)         /*!< RIE (Bit 16)                                          */
46351  #define R_SCI_B0_CCR0_RIE_Msk           (0x10000UL)    /*!< RIE (Bitfield-Mask: 0x01)                             */
46352  #define R_SCI_B0_CCR0_TIE_Pos           (20UL)         /*!< TIE (Bit 20)                                          */
46353  #define R_SCI_B0_CCR0_TIE_Msk           (0x100000UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
46354  #define R_SCI_B0_CCR0_TEIE_Pos          (21UL)         /*!< TEIE (Bit 21)                                         */
46355  #define R_SCI_B0_CCR0_TEIE_Msk          (0x200000UL)   /*!< TEIE (Bitfield-Mask: 0x01)                            */
46356  #define R_SCI_B0_CCR0_SSE_Pos           (24UL)         /*!< SSE (Bit 24)                                          */
46357  #define R_SCI_B0_CCR0_SSE_Msk           (0x1000000UL)  /*!< SSE (Bitfield-Mask: 0x01)                             */
46358 /* =========================================================  CCR1  ========================================================== */
46359  #define R_SCI_B0_CCR1_CTSE_Pos          (0UL)          /*!< CTSE (Bit 0)                                          */
46360  #define R_SCI_B0_CCR1_CTSE_Msk          (0x1UL)        /*!< CTSE (Bitfield-Mask: 0x01)                            */
46361  #define R_SCI_B0_CCR1_CTSPEN_Pos        (1UL)          /*!< CTSPEN (Bit 1)                                        */
46362  #define R_SCI_B0_CCR1_CTSPEN_Msk        (0x2UL)        /*!< CTSPEN (Bitfield-Mask: 0x01)                          */
46363  #define R_SCI_B0_CCR1_SPB2DT_Pos        (4UL)          /*!< SPB2DT (Bit 4)                                        */
46364  #define R_SCI_B0_CCR1_SPB2DT_Msk        (0x10UL)       /*!< SPB2DT (Bitfield-Mask: 0x01)                          */
46365  #define R_SCI_B0_CCR1_SPB2IO_Pos        (5UL)          /*!< SPB2IO (Bit 5)                                        */
46366  #define R_SCI_B0_CCR1_SPB2IO_Msk        (0x20UL)       /*!< SPB2IO (Bitfield-Mask: 0x01)                          */
46367  #define R_SCI_B0_CCR1_PE_Pos            (8UL)          /*!< PE (Bit 8)                                            */
46368  #define R_SCI_B0_CCR1_PE_Msk            (0x100UL)      /*!< PE (Bitfield-Mask: 0x01)                              */
46369  #define R_SCI_B0_CCR1_PM_Pos            (9UL)          /*!< PM (Bit 9)                                            */
46370  #define R_SCI_B0_CCR1_PM_Msk            (0x200UL)      /*!< PM (Bitfield-Mask: 0x01)                              */
46371  #define R_SCI_B0_CCR1_TINV_Pos          (12UL)         /*!< TINV (Bit 12)                                         */
46372  #define R_SCI_B0_CCR1_TINV_Msk          (0x1000UL)     /*!< TINV (Bitfield-Mask: 0x01)                            */
46373  #define R_SCI_B0_CCR1_RINV_Pos          (13UL)         /*!< RINV (Bit 13)                                         */
46374  #define R_SCI_B0_CCR1_RINV_Msk          (0x2000UL)     /*!< RINV (Bitfield-Mask: 0x01)                            */
46375  #define R_SCI_B0_CCR1_SPLP_Pos          (16UL)         /*!< SPLP (Bit 16)                                         */
46376  #define R_SCI_B0_CCR1_SPLP_Msk          (0x10000UL)    /*!< SPLP (Bitfield-Mask: 0x01)                            */
46377  #define R_SCI_B0_CCR1_SHARPS_Pos        (20UL)         /*!< SHARPS (Bit 20)                                       */
46378  #define R_SCI_B0_CCR1_SHARPS_Msk        (0x100000UL)   /*!< SHARPS (Bitfield-Mask: 0x01)                          */
46379  #define R_SCI_B0_CCR1_NFCS_Pos          (24UL)         /*!< NFCS (Bit 24)                                         */
46380  #define R_SCI_B0_CCR1_NFCS_Msk          (0x7000000UL)  /*!< NFCS (Bitfield-Mask: 0x07)                            */
46381  #define R_SCI_B0_CCR1_NFEN_Pos          (28UL)         /*!< NFEN (Bit 28)                                         */
46382  #define R_SCI_B0_CCR1_NFEN_Msk          (0x10000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
46383 /* =========================================================  CCR2  ========================================================== */
46384  #define R_SCI_B0_CCR2_BCP_Pos           (0UL)          /*!< BCP (Bit 0)                                           */
46385  #define R_SCI_B0_CCR2_BCP_Msk           (0x7UL)        /*!< BCP (Bitfield-Mask: 0x07)                             */
46386  #define R_SCI_B0_CCR2_BGDM_Pos          (4UL)          /*!< BGDM (Bit 4)                                          */
46387  #define R_SCI_B0_CCR2_BGDM_Msk          (0x10UL)       /*!< BGDM (Bitfield-Mask: 0x01)                            */
46388  #define R_SCI_B0_CCR2_ABCS_Pos          (5UL)          /*!< ABCS (Bit 5)                                          */
46389  #define R_SCI_B0_CCR2_ABCS_Msk          (0x20UL)       /*!< ABCS (Bitfield-Mask: 0x01)                            */
46390  #define R_SCI_B0_CCR2_ABCSE_Pos         (6UL)          /*!< ABCSE (Bit 6)                                         */
46391  #define R_SCI_B0_CCR2_ABCSE_Msk         (0x40UL)       /*!< ABCSE (Bitfield-Mask: 0x01)                           */
46392  #define R_SCI_B0_CCR2_BRR_Pos           (8UL)          /*!< BRR (Bit 8)                                           */
46393  #define R_SCI_B0_CCR2_BRR_Msk           (0xff00UL)     /*!< BRR (Bitfield-Mask: 0xff)                             */
46394  #define R_SCI_B0_CCR2_BRME_Pos          (16UL)         /*!< BRME (Bit 16)                                         */
46395  #define R_SCI_B0_CCR2_BRME_Msk          (0x10000UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
46396  #define R_SCI_B0_CCR2_CKS_Pos           (20UL)         /*!< CKS (Bit 20)                                          */
46397  #define R_SCI_B0_CCR2_CKS_Msk           (0x300000UL)   /*!< CKS (Bitfield-Mask: 0x03)                             */
46398  #define R_SCI_B0_CCR2_MDDR_Pos          (24UL)         /*!< MDDR (Bit 24)                                         */
46399  #define R_SCI_B0_CCR2_MDDR_Msk          (0xff000000UL) /*!< MDDR (Bitfield-Mask: 0xff)                            */
46400 /* =========================================================  CCR3  ========================================================== */
46401  #define R_SCI_B0_CCR3_CPHA_Pos          (0UL)          /*!< CPHA (Bit 0)                                          */
46402  #define R_SCI_B0_CCR3_CPHA_Msk          (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
46403  #define R_SCI_B0_CCR3_CPOL_Pos          (1UL)          /*!< CPOL (Bit 1)                                          */
46404  #define R_SCI_B0_CCR3_CPOL_Msk          (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
46405  #define R_SCI_B0_CCR3_BPEN_Pos          (7UL)          /*!< BPEN (Bit 7)                                          */
46406  #define R_SCI_B0_CCR3_BPEN_Msk          (0x80UL)       /*!< BPEN (Bitfield-Mask: 0x01)                            */
46407  #define R_SCI_B0_CCR3_CHR_Pos           (8UL)          /*!< CHR (Bit 8)                                           */
46408  #define R_SCI_B0_CCR3_CHR_Msk           (0x300UL)      /*!< CHR (Bitfield-Mask: 0x03)                             */
46409  #define R_SCI_B0_CCR3_LSBF_Pos          (12UL)         /*!< LSBF (Bit 12)                                         */
46410  #define R_SCI_B0_CCR3_LSBF_Msk          (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
46411  #define R_SCI_B0_CCR3_SINV_Pos          (13UL)         /*!< SINV (Bit 13)                                         */
46412  #define R_SCI_B0_CCR3_SINV_Msk          (0x2000UL)     /*!< SINV (Bitfield-Mask: 0x01)                            */
46413  #define R_SCI_B0_CCR3_STP_Pos           (14UL)         /*!< STP (Bit 14)                                          */
46414  #define R_SCI_B0_CCR3_STP_Msk           (0x4000UL)     /*!< STP (Bitfield-Mask: 0x01)                             */
46415  #define R_SCI_B0_CCR3_RXDESEL_Pos       (15UL)         /*!< RXDESEL (Bit 15)                                      */
46416  #define R_SCI_B0_CCR3_RXDESEL_Msk       (0x8000UL)     /*!< RXDESEL (Bitfield-Mask: 0x01)                         */
46417  #define R_SCI_B0_CCR3_MOD_Pos           (16UL)         /*!< MOD (Bit 16)                                          */
46418  #define R_SCI_B0_CCR3_MOD_Msk           (0x70000UL)    /*!< MOD (Bitfield-Mask: 0x07)                             */
46419  #define R_SCI_B0_CCR3_MP_Pos            (19UL)         /*!< MP (Bit 19)                                           */
46420  #define R_SCI_B0_CCR3_MP_Msk            (0x80000UL)    /*!< MP (Bitfield-Mask: 0x01)                              */
46421  #define R_SCI_B0_CCR3_FM_Pos            (20UL)         /*!< FM (Bit 20)                                           */
46422  #define R_SCI_B0_CCR3_FM_Msk            (0x100000UL)   /*!< FM (Bitfield-Mask: 0x01)                              */
46423  #define R_SCI_B0_CCR3_DEN_Pos           (21UL)         /*!< DEN (Bit 21)                                          */
46424  #define R_SCI_B0_CCR3_DEN_Msk           (0x200000UL)   /*!< DEN (Bitfield-Mask: 0x01)                             */
46425  #define R_SCI_B0_CCR3_CKE_Pos           (24UL)         /*!< CKE (Bit 24)                                          */
46426  #define R_SCI_B0_CCR3_CKE_Msk           (0x3000000UL)  /*!< CKE (Bitfield-Mask: 0x03)                             */
46427  #define R_SCI_B0_CCR3_GM_Pos            (28UL)         /*!< GM (Bit 28)                                           */
46428  #define R_SCI_B0_CCR3_GM_Msk            (0x10000000UL) /*!< GM (Bitfield-Mask: 0x01)                              */
46429  #define R_SCI_B0_CCR3_BLK_Pos           (29UL)         /*!< BLK (Bit 29)                                          */
46430  #define R_SCI_B0_CCR3_BLK_Msk           (0x20000000UL) /*!< BLK (Bitfield-Mask: 0x01)                             */
46431 /* =========================================================  CCR4  ========================================================== */
46432  #define R_SCI_B0_CCR4_CMPD_Pos          (0UL)          /*!< CMPD (Bit 0)                                          */
46433  #define R_SCI_B0_CCR4_CMPD_Msk          (0x1ffUL)      /*!< CMPD (Bitfield-Mask: 0x1ff)                           */
46434  #define R_SCI_B0_CCR4_ASEN_Pos          (16UL)         /*!< ASEN (Bit 16)                                         */
46435  #define R_SCI_B0_CCR4_ASEN_Msk          (0x10000UL)    /*!< ASEN (Bitfield-Mask: 0x01)                            */
46436  #define R_SCI_B0_CCR4_ATEN_Pos          (17UL)         /*!< ATEN (Bit 17)                                         */
46437  #define R_SCI_B0_CCR4_ATEN_Msk          (0x20000UL)    /*!< ATEN (Bitfield-Mask: 0x01)                            */
46438  #define R_SCI_B0_CCR4_AST_Pos           (24UL)         /*!< AST (Bit 24)                                          */
46439  #define R_SCI_B0_CCR4_AST_Msk           (0x7000000UL)  /*!< AST (Bitfield-Mask: 0x07)                             */
46440  #define R_SCI_B0_CCR4_AJD_Pos           (27UL)         /*!< AJD (Bit 27)                                          */
46441  #define R_SCI_B0_CCR4_AJD_Msk           (0x8000000UL)  /*!< AJD (Bitfield-Mask: 0x01)                             */
46442  #define R_SCI_B0_CCR4_ATT_Pos           (28UL)         /*!< ATT (Bit 28)                                          */
46443  #define R_SCI_B0_CCR4_ATT_Msk           (0x70000000UL) /*!< ATT (Bitfield-Mask: 0x07)                             */
46444  #define R_SCI_B0_CCR4_AET_Pos           (31UL)         /*!< AET (Bit 31)                                          */
46445  #define R_SCI_B0_CCR4_AET_Msk           (0x80000000UL) /*!< AET (Bitfield-Mask: 0x01)                             */
46446 /* =========================================================  CESR  ========================================================== */
46447  #define R_SCI_B0_CESR_RIST_Pos          (0UL)          /*!< RIST (Bit 0)                                          */
46448  #define R_SCI_B0_CESR_RIST_Msk          (0x1UL)        /*!< RIST (Bitfield-Mask: 0x01)                            */
46449  #define R_SCI_B0_CESR_TIST_Pos          (4UL)          /*!< TIST (Bit 4)                                          */
46450  #define R_SCI_B0_CESR_TIST_Msk          (0x10UL)       /*!< TIST (Bitfield-Mask: 0x01)                            */
46451 /* ==========================================================  ICR  ========================================================== */
46452  #define R_SCI_B0_ICR_IICDL_Pos          (0UL)          /*!< IICDL (Bit 0)                                         */
46453  #define R_SCI_B0_ICR_IICDL_Msk          (0x1fUL)       /*!< IICDL (Bitfield-Mask: 0x1f)                           */
46454  #define R_SCI_B0_ICR_IICINTM_Pos        (8UL)          /*!< IICINTM (Bit 8)                                       */
46455  #define R_SCI_B0_ICR_IICINTM_Msk        (0x100UL)      /*!< IICINTM (Bitfield-Mask: 0x01)                         */
46456  #define R_SCI_B0_ICR_IICCSC_Pos         (9UL)          /*!< IICCSC (Bit 9)                                        */
46457  #define R_SCI_B0_ICR_IICCSC_Msk         (0x200UL)      /*!< IICCSC (Bitfield-Mask: 0x01)                          */
46458  #define R_SCI_B0_ICR_IICACKT_Pos        (13UL)         /*!< IICACKT (Bit 13)                                      */
46459  #define R_SCI_B0_ICR_IICACKT_Msk        (0x2000UL)     /*!< IICACKT (Bitfield-Mask: 0x01)                         */
46460  #define R_SCI_B0_ICR_IICSTAREQ_Pos      (16UL)         /*!< IICSTAREQ (Bit 16)                                    */
46461  #define R_SCI_B0_ICR_IICSTAREQ_Msk      (0x10000UL)    /*!< IICSTAREQ (Bitfield-Mask: 0x01)                       */
46462  #define R_SCI_B0_ICR_IICRSTAREQ_Pos     (17UL)         /*!< IICRSTAREQ (Bit 17)                                   */
46463  #define R_SCI_B0_ICR_IICRSTAREQ_Msk     (0x20000UL)    /*!< IICRSTAREQ (Bitfield-Mask: 0x01)                      */
46464  #define R_SCI_B0_ICR_IICSTPREQ_Pos      (18UL)         /*!< IICSTPREQ (Bit 18)                                    */
46465  #define R_SCI_B0_ICR_IICSTPREQ_Msk      (0x40000UL)    /*!< IICSTPREQ (Bitfield-Mask: 0x01)                       */
46466  #define R_SCI_B0_ICR_IICSDAS_Pos        (20UL)         /*!< IICSDAS (Bit 20)                                      */
46467  #define R_SCI_B0_ICR_IICSDAS_Msk        (0x300000UL)   /*!< IICSDAS (Bitfield-Mask: 0x03)                         */
46468  #define R_SCI_B0_ICR_IICSCLS_Pos        (22UL)         /*!< IICSCLS (Bit 22)                                      */
46469  #define R_SCI_B0_ICR_IICSCLS_Msk        (0xc00000UL)   /*!< IICSCLS (Bitfield-Mask: 0x03)                         */
46470 /* ==========================================================  FCR  ========================================================== */
46471  #define R_SCI_B0_FCR_DRES_Pos           (0UL)          /*!< DRES (Bit 0)                                          */
46472  #define R_SCI_B0_FCR_DRES_Msk           (0x1UL)        /*!< DRES (Bitfield-Mask: 0x01)                            */
46473  #define R_SCI_B0_FCR_TTRG_Pos           (8UL)          /*!< TTRG (Bit 8)                                          */
46474  #define R_SCI_B0_FCR_TTRG_Msk           (0x1f00UL)     /*!< TTRG (Bitfield-Mask: 0x1f)                            */
46475  #define R_SCI_B0_FCR_TFRST_Pos          (15UL)         /*!< TFRST (Bit 15)                                        */
46476  #define R_SCI_B0_FCR_TFRST_Msk          (0x8000UL)     /*!< TFRST (Bitfield-Mask: 0x01)                           */
46477  #define R_SCI_B0_FCR_RTRG_Pos           (16UL)         /*!< RTRG (Bit 16)                                         */
46478  #define R_SCI_B0_FCR_RTRG_Msk           (0x1f0000UL)   /*!< RTRG (Bitfield-Mask: 0x1f)                            */
46479  #define R_SCI_B0_FCR_RFRST_Pos          (23UL)         /*!< RFRST (Bit 23)                                        */
46480  #define R_SCI_B0_FCR_RFRST_Msk          (0x800000UL)   /*!< RFRST (Bitfield-Mask: 0x01)                           */
46481  #define R_SCI_B0_FCR_RSTRG_Pos          (24UL)         /*!< RSTRG (Bit 24)                                        */
46482  #define R_SCI_B0_FCR_RSTRG_Msk          (0x1f000000UL) /*!< RSTRG (Bitfield-Mask: 0x1f)                           */
46483 /* ==========================================================  MCR  ========================================================== */
46484  #define R_SCI_B0_MCR_RMPOL_Pos          (0UL)          /*!< RMPOL (Bit 0)                                         */
46485  #define R_SCI_B0_MCR_RMPOL_Msk          (0x1UL)        /*!< RMPOL (Bitfield-Mask: 0x01)                           */
46486  #define R_SCI_B0_MCR_TMPOL_Pos          (1UL)          /*!< TMPOL (Bit 1)                                         */
46487  #define R_SCI_B0_MCR_TMPOL_Msk          (0x2UL)        /*!< TMPOL (Bitfield-Mask: 0x01)                           */
46488  #define R_SCI_B0_MCR_ERTEN_Pos          (2UL)          /*!< ERTEN (Bit 2)                                         */
46489  #define R_SCI_B0_MCR_ERTEN_Msk          (0x4UL)        /*!< ERTEN (Bitfield-Mask: 0x01)                           */
46490  #define R_SCI_B0_MCR_SYNVAL_Pos         (4UL)          /*!< SYNVAL (Bit 4)                                        */
46491  #define R_SCI_B0_MCR_SYNVAL_Msk         (0x10UL)       /*!< SYNVAL (Bitfield-Mask: 0x01)                          */
46492  #define R_SCI_B0_MCR_SYNSEL_Pos         (5UL)          /*!< SYNSEL (Bit 5)                                        */
46493  #define R_SCI_B0_MCR_SYNSEL_Msk         (0x20UL)       /*!< SYNSEL (Bitfield-Mask: 0x01)                          */
46494  #define R_SCI_B0_MCR_SBSEL_Pos          (6UL)          /*!< SBSEL (Bit 6)                                         */
46495  #define R_SCI_B0_MCR_SBSEL_Msk          (0x40UL)       /*!< SBSEL (Bitfield-Mask: 0x01)                           */
46496  #define R_SCI_B0_MCR_TPLEN_Pos          (8UL)          /*!< TPLEN (Bit 8)                                         */
46497  #define R_SCI_B0_MCR_TPLEN_Msk          (0xf00UL)      /*!< TPLEN (Bitfield-Mask: 0x0f)                           */
46498  #define R_SCI_B0_MCR_TPPAT_Pos          (12UL)         /*!< TPPAT (Bit 12)                                        */
46499  #define R_SCI_B0_MCR_TPPAT_Msk          (0x3000UL)     /*!< TPPAT (Bitfield-Mask: 0x03)                           */
46500  #define R_SCI_B0_MCR_RPLEN_Pos          (16UL)         /*!< RPLEN (Bit 16)                                        */
46501  #define R_SCI_B0_MCR_RPLEN_Msk          (0xf0000UL)    /*!< RPLEN (Bitfield-Mask: 0x0f)                           */
46502  #define R_SCI_B0_MCR_RPPAT_Pos          (20UL)         /*!< RPPAT (Bit 20)                                        */
46503  #define R_SCI_B0_MCR_RPPAT_Msk          (0x300000UL)   /*!< RPPAT (Bitfield-Mask: 0x03)                           */
46504  #define R_SCI_B0_MCR_PFEREN_Pos         (24UL)         /*!< PFEREN (Bit 24)                                       */
46505  #define R_SCI_B0_MCR_PFEREN_Msk         (0x1000000UL)  /*!< PFEREN (Bitfield-Mask: 0x01)                          */
46506  #define R_SCI_B0_MCR_SYEREN_Pos         (25UL)         /*!< SYEREN (Bit 25)                                       */
46507  #define R_SCI_B0_MCR_SYEREN_Msk         (0x2000000UL)  /*!< SYEREN (Bitfield-Mask: 0x01)                          */
46508  #define R_SCI_B0_MCR_SBEREN_Pos         (26UL)         /*!< SBEREN (Bit 26)                                       */
46509  #define R_SCI_B0_MCR_SBEREN_Msk         (0x4000000UL)  /*!< SBEREN (Bitfield-Mask: 0x01)                          */
46510 /* ==========================================================  DCR  ========================================================== */
46511  #define R_SCI_B0_DCR_DEPOL_Pos          (0UL)          /*!< DEPOL (Bit 0)                                         */
46512  #define R_SCI_B0_DCR_DEPOL_Msk          (0x1UL)        /*!< DEPOL (Bitfield-Mask: 0x01)                           */
46513  #define R_SCI_B0_DCR_DEAST_Pos          (8UL)          /*!< DEAST (Bit 8)                                         */
46514  #define R_SCI_B0_DCR_DEAST_Msk          (0x1f00UL)     /*!< DEAST (Bitfield-Mask: 0x1f)                           */
46515  #define R_SCI_B0_DCR_DENGT_Pos          (16UL)         /*!< DENGT (Bit 16)                                        */
46516  #define R_SCI_B0_DCR_DENGT_Msk          (0x1f0000UL)   /*!< DENGT (Bitfield-Mask: 0x1f)                           */
46517 /* =========================================================  XCR0  ========================================================== */
46518  #define R_SCI_B0_XCR0_TCSS_Pos          (0UL)          /*!< TCSS (Bit 0)                                          */
46519  #define R_SCI_B0_XCR0_TCSS_Msk          (0x3UL)        /*!< TCSS (Bitfield-Mask: 0x03)                            */
46520  #define R_SCI_B0_XCR0_BFE_Pos           (8UL)          /*!< BFE (Bit 8)                                           */
46521  #define R_SCI_B0_XCR0_BFE_Msk           (0x100UL)      /*!< BFE (Bitfield-Mask: 0x01)                             */
46522  #define R_SCI_B0_XCR0_CF0RE_Pos         (9UL)          /*!< CF0RE (Bit 9)                                         */
46523  #define R_SCI_B0_XCR0_CF0RE_Msk         (0x200UL)      /*!< CF0RE (Bitfield-Mask: 0x01)                           */
46524  #define R_SCI_B0_XCR0_CF1DS_Pos         (10UL)         /*!< CF1DS (Bit 10)                                        */
46525  #define R_SCI_B0_XCR0_CF1DS_Msk         (0xc00UL)      /*!< CF1DS (Bitfield-Mask: 0x03)                           */
46526  #define R_SCI_B0_XCR0_PIBE_Pos          (12UL)         /*!< PIBE (Bit 12)                                         */
46527  #define R_SCI_B0_XCR0_PIBE_Msk          (0x1000UL)     /*!< PIBE (Bitfield-Mask: 0x01)                            */
46528  #define R_SCI_B0_XCR0_PIBS_Pos          (13UL)         /*!< PIBS (Bit 13)                                         */
46529  #define R_SCI_B0_XCR0_PIBS_Msk          (0xe000UL)     /*!< PIBS (Bitfield-Mask: 0x07)                            */
46530  #define R_SCI_B0_XCR0_BFOIE_Pos         (16UL)         /*!< BFOIE (Bit 16)                                        */
46531  #define R_SCI_B0_XCR0_BFOIE_Msk         (0x10000UL)    /*!< BFOIE (Bitfield-Mask: 0x01)                           */
46532  #define R_SCI_B0_XCR0_BCDIE_Pos         (17UL)         /*!< BCDIE (Bit 17)                                        */
46533  #define R_SCI_B0_XCR0_BCDIE_Msk         (0x20000UL)    /*!< BCDIE (Bitfield-Mask: 0x01)                           */
46534  #define R_SCI_B0_XCR0_BFDIE_Pos         (20UL)         /*!< BFDIE (Bit 20)                                        */
46535  #define R_SCI_B0_XCR0_BFDIE_Msk         (0x100000UL)   /*!< BFDIE (Bitfield-Mask: 0x01)                           */
46536  #define R_SCI_B0_XCR0_COFIE_Pos         (21UL)         /*!< COFIE (Bit 21)                                        */
46537  #define R_SCI_B0_XCR0_COFIE_Msk         (0x200000UL)   /*!< COFIE (Bitfield-Mask: 0x01)                           */
46538  #define R_SCI_B0_XCR0_AEDIE_Pos         (22UL)         /*!< AEDIE (Bit 22)                                        */
46539  #define R_SCI_B0_XCR0_AEDIE_Msk         (0x400000UL)   /*!< AEDIE (Bitfield-Mask: 0x01)                           */
46540  #define R_SCI_B0_XCR0_BCCS_Pos          (24UL)         /*!< BCCS (Bit 24)                                         */
46541  #define R_SCI_B0_XCR0_BCCS_Msk          (0x3000000UL)  /*!< BCCS (Bitfield-Mask: 0x03)                            */
46542 /* =========================================================  XCR1  ========================================================== */
46543  #define R_SCI_B0_XCR1_TCST_Pos          (0UL)          /*!< TCST (Bit 0)                                          */
46544  #define R_SCI_B0_XCR1_TCST_Msk          (0x1UL)        /*!< TCST (Bitfield-Mask: 0x01)                            */
46545  #define R_SCI_B0_XCR1_SDST_Pos          (4UL)          /*!< SDST (Bit 4)                                          */
46546  #define R_SCI_B0_XCR1_SDST_Msk          (0x10UL)       /*!< SDST (Bitfield-Mask: 0x01)                            */
46547  #define R_SCI_B0_XCR1_BMEN_Pos          (5UL)          /*!< BMEN (Bit 5)                                          */
46548  #define R_SCI_B0_XCR1_BMEN_Msk          (0x20UL)       /*!< BMEN (Bitfield-Mask: 0x01)                            */
46549  #define R_SCI_B0_XCR1_PCF1D_Pos         (8UL)          /*!< PCF1D (Bit 8)                                         */
46550  #define R_SCI_B0_XCR1_PCF1D_Msk         (0xff00UL)     /*!< PCF1D (Bitfield-Mask: 0xff)                           */
46551  #define R_SCI_B0_XCR1_SCF1D_Pos         (16UL)         /*!< SCF1D (Bit 16)                                        */
46552  #define R_SCI_B0_XCR1_SCF1D_Msk         (0xff0000UL)   /*!< SCF1D (Bitfield-Mask: 0xff)                           */
46553  #define R_SCI_B0_XCR1_CF1CE_Pos         (24UL)         /*!< CF1CE (Bit 24)                                        */
46554  #define R_SCI_B0_XCR1_CF1CE_Msk         (0xff000000UL) /*!< CF1CE (Bitfield-Mask: 0xff)                           */
46555 /* =========================================================  XCR2  ========================================================== */
46556  #define R_SCI_B0_XCR2_CF0D_Pos          (0UL)          /*!< CF0D (Bit 0)                                          */
46557  #define R_SCI_B0_XCR2_CF0D_Msk          (0xffUL)       /*!< CF0D (Bitfield-Mask: 0xff)                            */
46558  #define R_SCI_B0_XCR2_CF0CE_Pos         (8UL)          /*!< CF0CE (Bit 8)                                         */
46559  #define R_SCI_B0_XCR2_CF0CE_Msk         (0xff00UL)     /*!< CF0CE (Bitfield-Mask: 0xff)                           */
46560  #define R_SCI_B0_XCR2_BFLW_Pos          (16UL)         /*!< BFLW (Bit 16)                                         */
46561  #define R_SCI_B0_XCR2_BFLW_Msk          (0xffff0000UL) /*!< BFLW (Bitfield-Mask: 0xffff)                          */
46562 /* ==========================================================  CSR  ========================================================== */
46563  #define R_SCI_B0_CSR_ERS_Pos            (4UL)          /*!< ERS (Bit 4)                                           */
46564  #define R_SCI_B0_CSR_ERS_Msk            (0x10UL)       /*!< ERS (Bitfield-Mask: 0x01)                             */
46565  #define R_SCI_B0_CSR_RXDMON_Pos         (15UL)         /*!< RXDMON (Bit 15)                                       */
46566  #define R_SCI_B0_CSR_RXDMON_Msk         (0x8000UL)     /*!< RXDMON (Bitfield-Mask: 0x01)                          */
46567  #define R_SCI_B0_CSR_DCMF_Pos           (16UL)         /*!< DCMF (Bit 16)                                         */
46568  #define R_SCI_B0_CSR_DCMF_Msk           (0x10000UL)    /*!< DCMF (Bitfield-Mask: 0x01)                            */
46569  #define R_SCI_B0_CSR_DPER_Pos           (17UL)         /*!< DPER (Bit 17)                                         */
46570  #define R_SCI_B0_CSR_DPER_Msk           (0x20000UL)    /*!< DPER (Bitfield-Mask: 0x01)                            */
46571  #define R_SCI_B0_CSR_DFER_Pos           (18UL)         /*!< DFER (Bit 18)                                         */
46572  #define R_SCI_B0_CSR_DFER_Msk           (0x40000UL)    /*!< DFER (Bitfield-Mask: 0x01)                            */
46573  #define R_SCI_B0_CSR_ORER_Pos           (24UL)         /*!< ORER (Bit 24)                                         */
46574  #define R_SCI_B0_CSR_ORER_Msk           (0x1000000UL)  /*!< ORER (Bitfield-Mask: 0x01)                            */
46575  #define R_SCI_B0_CSR_MFF_Pos            (26UL)         /*!< MFF (Bit 26)                                          */
46576  #define R_SCI_B0_CSR_MFF_Msk            (0x4000000UL)  /*!< MFF (Bitfield-Mask: 0x01)                             */
46577  #define R_SCI_B0_CSR_PER_Pos            (27UL)         /*!< PER (Bit 27)                                          */
46578  #define R_SCI_B0_CSR_PER_Msk            (0x8000000UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
46579  #define R_SCI_B0_CSR_FER_Pos            (28UL)         /*!< FER (Bit 28)                                          */
46580  #define R_SCI_B0_CSR_FER_Msk            (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
46581  #define R_SCI_B0_CSR_TDRE_Pos           (29UL)         /*!< TDRE (Bit 29)                                         */
46582  #define R_SCI_B0_CSR_TDRE_Msk           (0x20000000UL) /*!< TDRE (Bitfield-Mask: 0x01)                            */
46583  #define R_SCI_B0_CSR_TEND_Pos           (30UL)         /*!< TEND (Bit 30)                                         */
46584  #define R_SCI_B0_CSR_TEND_Msk           (0x40000000UL) /*!< TEND (Bitfield-Mask: 0x01)                            */
46585  #define R_SCI_B0_CSR_RDRF_Pos           (31UL)         /*!< RDRF (Bit 31)                                         */
46586  #define R_SCI_B0_CSR_RDRF_Msk           (0x80000000UL) /*!< RDRF (Bitfield-Mask: 0x01)                            */
46587 /* ==========================================================  ISR  ========================================================== */
46588  #define R_SCI_B0_ISR_IICACKR_Pos        (0UL)          /*!< IICACKR (Bit 0)                                       */
46589  #define R_SCI_B0_ISR_IICACKR_Msk        (0x1UL)        /*!< IICACKR (Bitfield-Mask: 0x01)                         */
46590  #define R_SCI_B0_ISR_IICSTIF_Pos        (3UL)          /*!< IICSTIF (Bit 3)                                       */
46591  #define R_SCI_B0_ISR_IICSTIF_Msk        (0x8UL)        /*!< IICSTIF (Bitfield-Mask: 0x01)                         */
46592 /* =========================================================  FRSR  ========================================================== */
46593  #define R_SCI_B0_FRSR_DR_Pos            (0UL)          /*!< DR (Bit 0)                                            */
46594  #define R_SCI_B0_FRSR_DR_Msk            (0x1UL)        /*!< DR (Bitfield-Mask: 0x01)                              */
46595  #define R_SCI_B0_FRSR_R_Pos             (8UL)          /*!< R (Bit 8)                                             */
46596  #define R_SCI_B0_FRSR_R_Msk             (0x3f00UL)     /*!< R (Bitfield-Mask: 0x3f)                               */
46597  #define R_SCI_B0_FRSR_PNUM_Pos          (16UL)         /*!< PNUM (Bit 16)                                         */
46598  #define R_SCI_B0_FRSR_PNUM_Msk          (0x3f0000UL)   /*!< PNUM (Bitfield-Mask: 0x3f)                            */
46599  #define R_SCI_B0_FRSR_FNUM_Pos          (24UL)         /*!< FNUM (Bit 24)                                         */
46600  #define R_SCI_B0_FRSR_FNUM_Msk          (0x3f000000UL) /*!< FNUM (Bitfield-Mask: 0x3f)                            */
46601 /* =========================================================  FTSR  ========================================================== */
46602  #define R_SCI_B0_FTSR_T_Pos             (0UL)          /*!< T (Bit 0)                                             */
46603  #define R_SCI_B0_FTSR_T_Msk             (0x3fUL)       /*!< T (Bitfield-Mask: 0x3f)                               */
46604 /* ==========================================================  MSR  ========================================================== */
46605  #define R_SCI_B0_MSR_PFER_Pos           (0UL)          /*!< PFER (Bit 0)                                          */
46606  #define R_SCI_B0_MSR_PFER_Msk           (0x1UL)        /*!< PFER (Bitfield-Mask: 0x01)                            */
46607  #define R_SCI_B0_MSR_SYER_Pos           (1UL)          /*!< SYER (Bit 1)                                          */
46608  #define R_SCI_B0_MSR_SYER_Msk           (0x2UL)        /*!< SYER (Bitfield-Mask: 0x01)                            */
46609  #define R_SCI_B0_MSR_SBER_Pos           (2UL)          /*!< SBER (Bit 2)                                          */
46610  #define R_SCI_B0_MSR_SBER_Msk           (0x4UL)        /*!< SBER (Bitfield-Mask: 0x01)                            */
46611  #define R_SCI_B0_MSR_MER_Pos            (4UL)          /*!< MER (Bit 4)                                           */
46612  #define R_SCI_B0_MSR_MER_Msk            (0x10UL)       /*!< MER (Bitfield-Mask: 0x01)                             */
46613  #define R_SCI_B0_MSR_RSYNC_Pos          (6UL)          /*!< RSYNC (Bit 6)                                         */
46614  #define R_SCI_B0_MSR_RSYNC_Msk          (0x40UL)       /*!< RSYNC (Bitfield-Mask: 0x01)                           */
46615 /* =========================================================  XSR0  ========================================================== */
46616  #define R_SCI_B0_XSR0_SFSF_Pos          (0UL)          /*!< SFSF (Bit 0)                                          */
46617  #define R_SCI_B0_XSR0_SFSF_Msk          (0x1UL)        /*!< SFSF (Bitfield-Mask: 0x01)                            */
46618  #define R_SCI_B0_XSR0_RXDSF_Pos         (1UL)          /*!< RXDSF (Bit 1)                                         */
46619  #define R_SCI_B0_XSR0_RXDSF_Msk         (0x2UL)        /*!< RXDSF (Bitfield-Mask: 0x01)                           */
46620  #define R_SCI_B0_XSR0_BFOF_Pos          (8UL)          /*!< BFOF (Bit 8)                                          */
46621  #define R_SCI_B0_XSR0_BFOF_Msk          (0x100UL)      /*!< BFOF (Bitfield-Mask: 0x01)                            */
46622  #define R_SCI_B0_XSR0_BCDF_Pos          (9UL)          /*!< BCDF (Bit 9)                                          */
46623  #define R_SCI_B0_XSR0_BCDF_Msk          (0x200UL)      /*!< BCDF (Bitfield-Mask: 0x01)                            */
46624  #define R_SCI_B0_XSR0_BFDF_Pos          (10UL)         /*!< BFDF (Bit 10)                                         */
46625  #define R_SCI_B0_XSR0_BFDF_Msk          (0x400UL)      /*!< BFDF (Bitfield-Mask: 0x01)                            */
46626  #define R_SCI_B0_XSR0_CF0MF_Pos         (11UL)         /*!< CF0MF (Bit 11)                                        */
46627  #define R_SCI_B0_XSR0_CF0MF_Msk         (0x800UL)      /*!< CF0MF (Bitfield-Mask: 0x01)                           */
46628  #define R_SCI_B0_XSR0_CF1MF_Pos         (12UL)         /*!< CF1MF (Bit 12)                                        */
46629  #define R_SCI_B0_XSR0_CF1MF_Msk         (0x1000UL)     /*!< CF1MF (Bitfield-Mask: 0x01)                           */
46630  #define R_SCI_B0_XSR0_PIBDF_Pos         (13UL)         /*!< PIBDF (Bit 13)                                        */
46631  #define R_SCI_B0_XSR0_PIBDF_Msk         (0x2000UL)     /*!< PIBDF (Bitfield-Mask: 0x01)                           */
46632  #define R_SCI_B0_XSR0_COF_Pos           (14UL)         /*!< COF (Bit 14)                                          */
46633  #define R_SCI_B0_XSR0_COF_Msk           (0x4000UL)     /*!< COF (Bitfield-Mask: 0x01)                             */
46634  #define R_SCI_B0_XSR0_AEDF_Pos          (15UL)         /*!< AEDF (Bit 15)                                         */
46635  #define R_SCI_B0_XSR0_AEDF_Msk          (0x8000UL)     /*!< AEDF (Bitfield-Mask: 0x01)                            */
46636  #define R_SCI_B0_XSR0_CF0RD_Pos         (16UL)         /*!< CF0RD (Bit 16)                                        */
46637  #define R_SCI_B0_XSR0_CF0RD_Msk         (0xff0000UL)   /*!< CF0RD (Bitfield-Mask: 0xff)                           */
46638  #define R_SCI_B0_XSR0_CF1RD_Pos         (24UL)         /*!< CF1RD (Bit 24)                                        */
46639  #define R_SCI_B0_XSR0_CF1RD_Msk         (0xff000000UL) /*!< CF1RD (Bitfield-Mask: 0xff)                           */
46640 /* =========================================================  XSR1  ========================================================== */
46641  #define R_SCI_B0_XSR1_TCNT_Pos          (0UL)          /*!< TCNT (Bit 0)                                          */
46642  #define R_SCI_B0_XSR1_TCNT_Msk          (0xffffUL)     /*!< TCNT (Bitfield-Mask: 0xffff)                          */
46643 /* =========================================================  CFCLR  ========================================================= */
46644  #define R_SCI_B0_CFCLR_ERSC_Pos         (4UL)          /*!< ERSC (Bit 4)                                          */
46645  #define R_SCI_B0_CFCLR_ERSC_Msk         (0x10UL)       /*!< ERSC (Bitfield-Mask: 0x01)                            */
46646  #define R_SCI_B0_CFCLR_DCMFC_Pos        (16UL)         /*!< DCMFC (Bit 16)                                        */
46647  #define R_SCI_B0_CFCLR_DCMFC_Msk        (0x10000UL)    /*!< DCMFC (Bitfield-Mask: 0x01)                           */
46648  #define R_SCI_B0_CFCLR_DPERC_Pos        (17UL)         /*!< DPERC (Bit 17)                                        */
46649  #define R_SCI_B0_CFCLR_DPERC_Msk        (0x20000UL)    /*!< DPERC (Bitfield-Mask: 0x01)                           */
46650  #define R_SCI_B0_CFCLR_DFERC_Pos        (18UL)         /*!< DFERC (Bit 18)                                        */
46651  #define R_SCI_B0_CFCLR_DFERC_Msk        (0x40000UL)    /*!< DFERC (Bitfield-Mask: 0x01)                           */
46652  #define R_SCI_B0_CFCLR_ORERC_Pos        (24UL)         /*!< ORERC (Bit 24)                                        */
46653  #define R_SCI_B0_CFCLR_ORERC_Msk        (0x1000000UL)  /*!< ORERC (Bitfield-Mask: 0x01)                           */
46654  #define R_SCI_B0_CFCLR_MFFC_Pos         (26UL)         /*!< MFFC (Bit 26)                                         */
46655  #define R_SCI_B0_CFCLR_MFFC_Msk         (0x4000000UL)  /*!< MFFC (Bitfield-Mask: 0x01)                            */
46656  #define R_SCI_B0_CFCLR_PERC_Pos         (27UL)         /*!< PERC (Bit 27)                                         */
46657  #define R_SCI_B0_CFCLR_PERC_Msk         (0x8000000UL)  /*!< PERC (Bitfield-Mask: 0x01)                            */
46658  #define R_SCI_B0_CFCLR_FERC_Pos         (28UL)         /*!< FERC (Bit 28)                                         */
46659  #define R_SCI_B0_CFCLR_FERC_Msk         (0x10000000UL) /*!< FERC (Bitfield-Mask: 0x01)                            */
46660  #define R_SCI_B0_CFCLR_TDREC_Pos        (29UL)         /*!< TDREC (Bit 29)                                        */
46661  #define R_SCI_B0_CFCLR_TDREC_Msk        (0x20000000UL) /*!< TDREC (Bitfield-Mask: 0x01)                           */
46662  #define R_SCI_B0_CFCLR_RDRFC_Pos        (31UL)         /*!< RDRFC (Bit 31)                                        */
46663  #define R_SCI_B0_CFCLR_RDRFC_Msk        (0x80000000UL) /*!< RDRFC (Bitfield-Mask: 0x01)                           */
46664 /* ========================================================  ICFCLR  ========================================================= */
46665  #define R_SCI_B0_ICFCLR_IICSTIFC_Pos    (3UL)          /*!< IICSTIFC (Bit 3)                                      */
46666  #define R_SCI_B0_ICFCLR_IICSTIFC_Msk    (0x8UL)        /*!< IICSTIFC (Bitfield-Mask: 0x01)                        */
46667 /* =========================================================  FFCLR  ========================================================= */
46668  #define R_SCI_B0_FFCLR_DRC_Pos          (0UL)          /*!< DRC (Bit 0)                                           */
46669  #define R_SCI_B0_FFCLR_DRC_Msk          (0x1UL)        /*!< DRC (Bitfield-Mask: 0x01)                             */
46670 /* =========================================================  MFCLR  ========================================================= */
46671  #define R_SCI_B0_MFCLR_PFERC_Pos        (0UL)          /*!< PFERC (Bit 0)                                         */
46672  #define R_SCI_B0_MFCLR_PFERC_Msk        (0x1UL)        /*!< PFERC (Bitfield-Mask: 0x01)                           */
46673  #define R_SCI_B0_MFCLR_SYERC_Pos        (1UL)          /*!< SYERC (Bit 1)                                         */
46674  #define R_SCI_B0_MFCLR_SYERC_Msk        (0x2UL)        /*!< SYERC (Bitfield-Mask: 0x01)                           */
46675  #define R_SCI_B0_MFCLR_SBERC_Pos        (2UL)          /*!< SBERC (Bit 2)                                         */
46676  #define R_SCI_B0_MFCLR_SBERC_Msk        (0x4UL)        /*!< SBERC (Bitfield-Mask: 0x01)                           */
46677  #define R_SCI_B0_MFCLR_MERC_Pos         (4UL)          /*!< MERC (Bit 4)                                          */
46678  #define R_SCI_B0_MFCLR_MERC_Msk         (0x10UL)       /*!< MERC (Bitfield-Mask: 0x01)                            */
46679 /* =========================================================  XFCLR  ========================================================= */
46680  #define R_SCI_B0_XFCLR_BFOC_Pos         (8UL)          /*!< BFOC (Bit 8)                                          */
46681  #define R_SCI_B0_XFCLR_BFOC_Msk         (0x100UL)      /*!< BFOC (Bitfield-Mask: 0x01)                            */
46682  #define R_SCI_B0_XFCLR_BCDC_Pos         (9UL)          /*!< BCDC (Bit 9)                                          */
46683  #define R_SCI_B0_XFCLR_BCDC_Msk         (0x200UL)      /*!< BCDC (Bitfield-Mask: 0x01)                            */
46684  #define R_SCI_B0_XFCLR_BFDC_Pos         (10UL)         /*!< BFDC (Bit 10)                                         */
46685  #define R_SCI_B0_XFCLR_BFDC_Msk         (0x400UL)      /*!< BFDC (Bitfield-Mask: 0x01)                            */
46686  #define R_SCI_B0_XFCLR_CF0MC_Pos        (11UL)         /*!< CF0MC (Bit 11)                                        */
46687  #define R_SCI_B0_XFCLR_CF0MC_Msk        (0x800UL)      /*!< CF0MC (Bitfield-Mask: 0x01)                           */
46688  #define R_SCI_B0_XFCLR_CF1MC_Pos        (12UL)         /*!< CF1MC (Bit 12)                                        */
46689  #define R_SCI_B0_XFCLR_CF1MC_Msk        (0x1000UL)     /*!< CF1MC (Bitfield-Mask: 0x01)                           */
46690  #define R_SCI_B0_XFCLR_PIBDC_Pos        (13UL)         /*!< PIBDC (Bit 13)                                        */
46691  #define R_SCI_B0_XFCLR_PIBDC_Msk        (0x2000UL)     /*!< PIBDC (Bitfield-Mask: 0x01)                           */
46692  #define R_SCI_B0_XFCLR_COFC_Pos         (14UL)         /*!< COFC (Bit 14)                                         */
46693  #define R_SCI_B0_XFCLR_COFC_Msk         (0x4000UL)     /*!< COFC (Bitfield-Mask: 0x01)                            */
46694  #define R_SCI_B0_XFCLR_AEDC_Pos         (15UL)         /*!< AEDC (Bit 15)                                         */
46695  #define R_SCI_B0_XFCLR_AEDC_Msk         (0x8000UL)     /*!< AEDC (Bitfield-Mask: 0x01)                            */
46696 
46697 /* =========================================================================================================================== */
46698 /* ================                                         R_SPI_B0                                          ================ */
46699 /* =========================================================================================================================== */
46700 
46701 /* =========================================================  SPDR  ========================================================== */
46702 /* ========================================================  SPDECR  ========================================================= */
46703  #define R_SPI_B0_SPDECR_SCKDL_Pos     (0UL)          /*!< SCKDL (Bit 0)                                         */
46704  #define R_SPI_B0_SPDECR_SCKDL_Msk     (0x7UL)        /*!< SCKDL (Bitfield-Mask: 0x07)                           */
46705  #define R_SPI_B0_SPDECR_SLNDL_Pos     (8UL)          /*!< SLNDL (Bit 8)                                         */
46706  #define R_SPI_B0_SPDECR_SLNDL_Msk     (0x700UL)      /*!< SLNDL (Bitfield-Mask: 0x07)                           */
46707  #define R_SPI_B0_SPDECR_SPNDL_Pos     (16UL)         /*!< SPNDL (Bit 16)                                        */
46708  #define R_SPI_B0_SPDECR_SPNDL_Msk     (0x70000UL)    /*!< SPNDL (Bitfield-Mask: 0x07)                           */
46709  #define R_SPI_B0_SPDECR_ARST_Pos      (24UL)         /*!< ARST (Bit 24)                                         */
46710  #define R_SPI_B0_SPDECR_ARST_Msk      (0x7000000UL)  /*!< ARST (Bitfield-Mask: 0x07)                            */
46711 /* =========================================================  SPCR  ========================================================== */
46712  #define R_SPI_B0_SPCR_SPE_Pos         (0UL)          /*!< SPE (Bit 0)                                           */
46713  #define R_SPI_B0_SPCR_SPE_Msk         (0x1UL)        /*!< SPE (Bitfield-Mask: 0x01)                             */
46714  #define R_SPI_B0_SPCR_SPSCKSEL_Pos    (7UL)          /*!< SPSCKSEL (Bit 7)                                      */
46715  #define R_SPI_B0_SPCR_SPSCKSEL_Msk    (0x80UL)       /*!< SPSCKSEL (Bitfield-Mask: 0x01)                        */
46716  #define R_SPI_B0_SPCR_SPPE_Pos        (8UL)          /*!< SPPE (Bit 8)                                          */
46717  #define R_SPI_B0_SPCR_SPPE_Msk        (0x100UL)      /*!< SPPE (Bitfield-Mask: 0x01)                            */
46718  #define R_SPI_B0_SPCR_SPOE_Pos        (9UL)          /*!< SPOE (Bit 9)                                          */
46719  #define R_SPI_B0_SPCR_SPOE_Msk        (0x200UL)      /*!< SPOE (Bitfield-Mask: 0x01)                            */
46720  #define R_SPI_B0_SPCR_PTE_Pos         (11UL)         /*!< PTE (Bit 11)                                          */
46721  #define R_SPI_B0_SPCR_PTE_Msk         (0x800UL)      /*!< PTE (Bitfield-Mask: 0x01)                             */
46722  #define R_SPI_B0_SPCR_SCKASE_Pos      (12UL)         /*!< SCKASE (Bit 12)                                       */
46723  #define R_SPI_B0_SPCR_SCKASE_Msk      (0x1000UL)     /*!< SCKASE (Bitfield-Mask: 0x01)                          */
46724  #define R_SPI_B0_SPCR_BFDS_Pos        (13UL)         /*!< BFDS (Bit 13)                                         */
46725  #define R_SPI_B0_SPCR_BFDS_Msk        (0x2000UL)     /*!< BFDS (Bitfield-Mask: 0x01)                            */
46726  #define R_SPI_B0_SPCR_MODFEN_Pos      (14UL)         /*!< MODFEN (Bit 14)                                       */
46727  #define R_SPI_B0_SPCR_MODFEN_Msk      (0x4000UL)     /*!< MODFEN (Bitfield-Mask: 0x01)                          */
46728  #define R_SPI_B0_SPCR_SPEIE_Pos       (16UL)         /*!< SPEIE (Bit 16)                                        */
46729  #define R_SPI_B0_SPCR_SPEIE_Msk       (0x10000UL)    /*!< SPEIE (Bitfield-Mask: 0x01)                           */
46730  #define R_SPI_B0_SPCR_SPRIE_Pos       (17UL)         /*!< SPRIE (Bit 17)                                        */
46731  #define R_SPI_B0_SPCR_SPRIE_Msk       (0x20000UL)    /*!< SPRIE (Bitfield-Mask: 0x01)                           */
46732  #define R_SPI_B0_SPCR_SPIIE_Pos       (18UL)         /*!< SPIIE (Bit 18)                                        */
46733  #define R_SPI_B0_SPCR_SPIIE_Msk       (0x40000UL)    /*!< SPIIE (Bitfield-Mask: 0x01)                           */
46734  #define R_SPI_B0_SPCR_SPDRES_Pos      (19UL)         /*!< SPDRES (Bit 19)                                       */
46735  #define R_SPI_B0_SPCR_SPDRES_Msk      (0x80000UL)    /*!< SPDRES (Bitfield-Mask: 0x01)                          */
46736  #define R_SPI_B0_SPCR_SPTIE_Pos       (20UL)         /*!< SPTIE (Bit 20)                                        */
46737  #define R_SPI_B0_SPCR_SPTIE_Msk       (0x100000UL)   /*!< SPTIE (Bitfield-Mask: 0x01)                           */
46738  #define R_SPI_B0_SPCR_CENDIE_Pos      (21UL)         /*!< CENDIE (Bit 21)                                       */
46739  #define R_SPI_B0_SPCR_CENDIE_Msk      (0x200000UL)   /*!< CENDIE (Bitfield-Mask: 0x01)                          */
46740  #define R_SPI_B0_SPCR_SPMS_Pos        (24UL)         /*!< SPMS (Bit 24)                                         */
46741  #define R_SPI_B0_SPCR_SPMS_Msk        (0x1000000UL)  /*!< SPMS (Bitfield-Mask: 0x01)                            */
46742  #define R_SPI_B0_SPCR_SPFRF_Pos       (25UL)         /*!< SPFRF (Bit 25)                                        */
46743  #define R_SPI_B0_SPCR_SPFRF_Msk       (0x2000000UL)  /*!< SPFRF (Bitfield-Mask: 0x01)                           */
46744  #define R_SPI_B0_SPCR_TXMD_Pos        (28UL)         /*!< TXMD (Bit 28)                                         */
46745  #define R_SPI_B0_SPCR_TXMD_Msk        (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03)                            */
46746  #define R_SPI_B0_SPCR_MSTR_Pos        (30UL)         /*!< MSTR (Bit 30)                                         */
46747  #define R_SPI_B0_SPCR_MSTR_Msk        (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01)                            */
46748  #define R_SPI_B0_SPCR_BPEN_Pos        (31UL)         /*!< BPEN (Bit 31)                                         */
46749  #define R_SPI_B0_SPCR_BPEN_Msk        (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01)                            */
46750 /* =========================================================  SPCR2  ========================================================= */
46751  #define R_SPI_B0_SPCR2_RMFM_Pos       (0UL)          /*!< RMFM (Bit 0)                                          */
46752  #define R_SPI_B0_SPCR2_RMFM_Msk       (0x1fUL)       /*!< RMFM (Bitfield-Mask: 0x1f)                            */
46753  #define R_SPI_B0_SPCR2_RMEDTG_Pos     (6UL)          /*!< RMEDTG (Bit 6)                                        */
46754  #define R_SPI_B0_SPCR2_RMEDTG_Msk     (0x40UL)       /*!< RMEDTG (Bitfield-Mask: 0x01)                          */
46755  #define R_SPI_B0_SPCR2_RMSTTG_Pos     (7UL)          /*!< RMSTTG (Bit 7)                                        */
46756  #define R_SPI_B0_SPCR2_RMSTTG_Msk     (0x80UL)       /*!< RMSTTG (Bitfield-Mask: 0x01)                          */
46757  #define R_SPI_B0_SPCR2_SPDRC_Pos      (8UL)          /*!< SPDRC (Bit 8)                                         */
46758  #define R_SPI_B0_SPCR2_SPDRC_Msk      (0xff00UL)     /*!< SPDRC (Bitfield-Mask: 0xff)                           */
46759  #define R_SPI_B0_SPCR2_SPLP_Pos       (16UL)         /*!< SPLP (Bit 16)                                         */
46760  #define R_SPI_B0_SPCR2_SPLP_Msk       (0x10000UL)    /*!< SPLP (Bitfield-Mask: 0x01)                            */
46761  #define R_SPI_B0_SPCR2_SPLP2_Pos      (17UL)         /*!< SPLP2 (Bit 17)                                        */
46762  #define R_SPI_B0_SPCR2_SPLP2_Msk      (0x20000UL)    /*!< SPLP2 (Bitfield-Mask: 0x01)                           */
46763  #define R_SPI_B0_SPCR2_MOIFV_Pos      (20UL)         /*!< MOIFV (Bit 20)                                        */
46764  #define R_SPI_B0_SPCR2_MOIFV_Msk      (0x100000UL)   /*!< MOIFV (Bitfield-Mask: 0x01)                           */
46765  #define R_SPI_B0_SPCR2_MOIFE_Pos      (21UL)         /*!< MOIFE (Bit 21)                                        */
46766  #define R_SPI_B0_SPCR2_MOIFE_Msk      (0x200000UL)   /*!< MOIFE (Bitfield-Mask: 0x01)                           */
46767 /* =========================================================  SPCR3  ========================================================= */
46768  #define R_SPI_B0_SPCR3_SSL0P_Pos      (0UL)          /*!< SSL0P (Bit 0)                                         */
46769  #define R_SPI_B0_SPCR3_SSL0P_Msk      (0x1UL)        /*!< SSL0P (Bitfield-Mask: 0x01)                           */
46770  #define R_SPI_B0_SPCR3_SSL1P_Pos      (1UL)          /*!< SSL1P (Bit 1)                                         */
46771  #define R_SPI_B0_SPCR3_SSL1P_Msk      (0x2UL)        /*!< SSL1P (Bitfield-Mask: 0x01)                           */
46772  #define R_SPI_B0_SPCR3_SSL2P_Pos      (2UL)          /*!< SSL2P (Bit 2)                                         */
46773  #define R_SPI_B0_SPCR3_SSL2P_Msk      (0x4UL)        /*!< SSL2P (Bitfield-Mask: 0x01)                           */
46774  #define R_SPI_B0_SPCR3_SSL3P_Pos      (3UL)          /*!< SSL3P (Bit 3)                                         */
46775  #define R_SPI_B0_SPCR3_SSL3P_Msk      (0x8UL)        /*!< SSL3P (Bitfield-Mask: 0x01)                           */
46776  #define R_SPI_B0_SPCR3_SPBR_Pos       (8UL)          /*!< SPBR (Bit 8)                                          */
46777  #define R_SPI_B0_SPCR3_SPBR_Msk       (0xff00UL)     /*!< SPBR (Bitfield-Mask: 0xff)                            */
46778  #define R_SPI_B0_SPCR3_SPSLN_Pos      (24UL)         /*!< SPSLN (Bit 24)                                        */
46779  #define R_SPI_B0_SPCR3_SPSLN_Msk      (0x7000000UL)  /*!< SPSLN (Bitfield-Mask: 0x07)                           */
46780 /* ========================================================  SPCMD0  ========================================================= */
46781  #define R_SPI_B0_SPCMD0_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
46782  #define R_SPI_B0_SPCMD0_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
46783  #define R_SPI_B0_SPCMD0_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
46784  #define R_SPI_B0_SPCMD0_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
46785  #define R_SPI_B0_SPCMD0_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
46786  #define R_SPI_B0_SPCMD0_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
46787  #define R_SPI_B0_SPCMD0_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
46788  #define R_SPI_B0_SPCMD0_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
46789  #define R_SPI_B0_SPCMD0_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
46790  #define R_SPI_B0_SPCMD0_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
46791  #define R_SPI_B0_SPCMD0_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
46792  #define R_SPI_B0_SPCMD0_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
46793  #define R_SPI_B0_SPCMD0_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
46794  #define R_SPI_B0_SPCMD0_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
46795  #define R_SPI_B0_SPCMD0_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
46796  #define R_SPI_B0_SPCMD0_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
46797  #define R_SPI_B0_SPCMD0_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
46798  #define R_SPI_B0_SPCMD0_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
46799  #define R_SPI_B0_SPCMD0_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
46800  #define R_SPI_B0_SPCMD0_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
46801 /* ========================================================  SPCMD1  ========================================================= */
46802  #define R_SPI_B0_SPCMD1_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
46803  #define R_SPI_B0_SPCMD1_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
46804  #define R_SPI_B0_SPCMD1_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
46805  #define R_SPI_B0_SPCMD1_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
46806  #define R_SPI_B0_SPCMD1_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
46807  #define R_SPI_B0_SPCMD1_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
46808  #define R_SPI_B0_SPCMD1_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
46809  #define R_SPI_B0_SPCMD1_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
46810  #define R_SPI_B0_SPCMD1_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
46811  #define R_SPI_B0_SPCMD1_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
46812  #define R_SPI_B0_SPCMD1_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
46813  #define R_SPI_B0_SPCMD1_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
46814  #define R_SPI_B0_SPCMD1_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
46815  #define R_SPI_B0_SPCMD1_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
46816  #define R_SPI_B0_SPCMD1_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
46817  #define R_SPI_B0_SPCMD1_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
46818  #define R_SPI_B0_SPCMD1_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
46819  #define R_SPI_B0_SPCMD1_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
46820  #define R_SPI_B0_SPCMD1_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
46821  #define R_SPI_B0_SPCMD1_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
46822 /* ========================================================  SPCMD2  ========================================================= */
46823  #define R_SPI_B0_SPCMD2_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
46824  #define R_SPI_B0_SPCMD2_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
46825  #define R_SPI_B0_SPCMD2_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
46826  #define R_SPI_B0_SPCMD2_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
46827  #define R_SPI_B0_SPCMD2_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
46828  #define R_SPI_B0_SPCMD2_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
46829  #define R_SPI_B0_SPCMD2_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
46830  #define R_SPI_B0_SPCMD2_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
46831  #define R_SPI_B0_SPCMD2_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
46832  #define R_SPI_B0_SPCMD2_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
46833  #define R_SPI_B0_SPCMD2_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
46834  #define R_SPI_B0_SPCMD2_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
46835  #define R_SPI_B0_SPCMD2_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
46836  #define R_SPI_B0_SPCMD2_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
46837  #define R_SPI_B0_SPCMD2_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
46838  #define R_SPI_B0_SPCMD2_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
46839  #define R_SPI_B0_SPCMD2_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
46840  #define R_SPI_B0_SPCMD2_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
46841  #define R_SPI_B0_SPCMD2_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
46842  #define R_SPI_B0_SPCMD2_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
46843 /* ========================================================  SPCMD3  ========================================================= */
46844  #define R_SPI_B0_SPCMD3_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
46845  #define R_SPI_B0_SPCMD3_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
46846  #define R_SPI_B0_SPCMD3_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
46847  #define R_SPI_B0_SPCMD3_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
46848  #define R_SPI_B0_SPCMD3_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
46849  #define R_SPI_B0_SPCMD3_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
46850  #define R_SPI_B0_SPCMD3_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
46851  #define R_SPI_B0_SPCMD3_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
46852  #define R_SPI_B0_SPCMD3_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
46853  #define R_SPI_B0_SPCMD3_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
46854  #define R_SPI_B0_SPCMD3_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
46855  #define R_SPI_B0_SPCMD3_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
46856  #define R_SPI_B0_SPCMD3_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
46857  #define R_SPI_B0_SPCMD3_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
46858  #define R_SPI_B0_SPCMD3_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
46859  #define R_SPI_B0_SPCMD3_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
46860  #define R_SPI_B0_SPCMD3_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
46861  #define R_SPI_B0_SPCMD3_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
46862  #define R_SPI_B0_SPCMD3_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
46863  #define R_SPI_B0_SPCMD3_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
46864 /* ========================================================  SPCMD4  ========================================================= */
46865  #define R_SPI_B0_SPCMD4_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
46866  #define R_SPI_B0_SPCMD4_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
46867  #define R_SPI_B0_SPCMD4_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
46868  #define R_SPI_B0_SPCMD4_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
46869  #define R_SPI_B0_SPCMD4_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
46870  #define R_SPI_B0_SPCMD4_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
46871  #define R_SPI_B0_SPCMD4_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
46872  #define R_SPI_B0_SPCMD4_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
46873  #define R_SPI_B0_SPCMD4_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
46874  #define R_SPI_B0_SPCMD4_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
46875  #define R_SPI_B0_SPCMD4_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
46876  #define R_SPI_B0_SPCMD4_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
46877  #define R_SPI_B0_SPCMD4_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
46878  #define R_SPI_B0_SPCMD4_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
46879  #define R_SPI_B0_SPCMD4_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
46880  #define R_SPI_B0_SPCMD4_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
46881  #define R_SPI_B0_SPCMD4_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
46882  #define R_SPI_B0_SPCMD4_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
46883  #define R_SPI_B0_SPCMD4_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
46884  #define R_SPI_B0_SPCMD4_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
46885 /* ========================================================  SPCMD5  ========================================================= */
46886  #define R_SPI_B0_SPCMD5_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
46887  #define R_SPI_B0_SPCMD5_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
46888  #define R_SPI_B0_SPCMD5_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
46889  #define R_SPI_B0_SPCMD5_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
46890  #define R_SPI_B0_SPCMD5_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
46891  #define R_SPI_B0_SPCMD5_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
46892  #define R_SPI_B0_SPCMD5_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
46893  #define R_SPI_B0_SPCMD5_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
46894  #define R_SPI_B0_SPCMD5_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
46895  #define R_SPI_B0_SPCMD5_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
46896  #define R_SPI_B0_SPCMD5_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
46897  #define R_SPI_B0_SPCMD5_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
46898  #define R_SPI_B0_SPCMD5_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
46899  #define R_SPI_B0_SPCMD5_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
46900  #define R_SPI_B0_SPCMD5_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
46901  #define R_SPI_B0_SPCMD5_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
46902  #define R_SPI_B0_SPCMD5_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
46903  #define R_SPI_B0_SPCMD5_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
46904  #define R_SPI_B0_SPCMD5_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
46905  #define R_SPI_B0_SPCMD5_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
46906 /* ========================================================  SPCMD6  ========================================================= */
46907  #define R_SPI_B0_SPCMD6_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
46908  #define R_SPI_B0_SPCMD6_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
46909  #define R_SPI_B0_SPCMD6_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
46910  #define R_SPI_B0_SPCMD6_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
46911  #define R_SPI_B0_SPCMD6_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
46912  #define R_SPI_B0_SPCMD6_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
46913  #define R_SPI_B0_SPCMD6_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
46914  #define R_SPI_B0_SPCMD6_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
46915  #define R_SPI_B0_SPCMD6_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
46916  #define R_SPI_B0_SPCMD6_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
46917  #define R_SPI_B0_SPCMD6_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
46918  #define R_SPI_B0_SPCMD6_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
46919  #define R_SPI_B0_SPCMD6_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
46920  #define R_SPI_B0_SPCMD6_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
46921  #define R_SPI_B0_SPCMD6_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
46922  #define R_SPI_B0_SPCMD6_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
46923  #define R_SPI_B0_SPCMD6_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
46924  #define R_SPI_B0_SPCMD6_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
46925  #define R_SPI_B0_SPCMD6_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
46926  #define R_SPI_B0_SPCMD6_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
46927 /* ========================================================  SPCMD7  ========================================================= */
46928  #define R_SPI_B0_SPCMD7_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
46929  #define R_SPI_B0_SPCMD7_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
46930  #define R_SPI_B0_SPCMD7_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
46931  #define R_SPI_B0_SPCMD7_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
46932  #define R_SPI_B0_SPCMD7_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
46933  #define R_SPI_B0_SPCMD7_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
46934  #define R_SPI_B0_SPCMD7_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
46935  #define R_SPI_B0_SPCMD7_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
46936  #define R_SPI_B0_SPCMD7_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
46937  #define R_SPI_B0_SPCMD7_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
46938  #define R_SPI_B0_SPCMD7_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
46939  #define R_SPI_B0_SPCMD7_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
46940  #define R_SPI_B0_SPCMD7_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
46941  #define R_SPI_B0_SPCMD7_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
46942  #define R_SPI_B0_SPCMD7_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
46943  #define R_SPI_B0_SPCMD7_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
46944  #define R_SPI_B0_SPCMD7_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
46945  #define R_SPI_B0_SPCMD7_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
46946  #define R_SPI_B0_SPCMD7_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
46947  #define R_SPI_B0_SPCMD7_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
46948 /* =========================================================  SPDCR  ========================================================= */
46949  #define R_SPI_B0_SPDCR_BYSW_Pos       (0UL)          /*!< BYSW (Bit 0)                                          */
46950  #define R_SPI_B0_SPDCR_BYSW_Msk       (0x1UL)        /*!< BYSW (Bitfield-Mask: 0x01)                            */
46951  #define R_SPI_B0_SPDCR_SPRDTD_Pos     (3UL)          /*!< SPRDTD (Bit 3)                                        */
46952  #define R_SPI_B0_SPDCR_SPRDTD_Msk     (0x8UL)        /*!< SPRDTD (Bitfield-Mask: 0x01)                          */
46953  #define R_SPI_B0_SPDCR_SINV_Pos       (4UL)          /*!< SINV (Bit 4)                                          */
46954  #define R_SPI_B0_SPDCR_SINV_Msk       (0x10UL)       /*!< SINV (Bitfield-Mask: 0x01)                            */
46955  #define R_SPI_B0_SPDCR_SPFC_Pos       (8UL)          /*!< SPFC (Bit 8)                                          */
46956  #define R_SPI_B0_SPDCR_SPFC_Msk       (0x300UL)      /*!< SPFC (Bitfield-Mask: 0x03)                            */
46957 /* ========================================================  SPDCR2  ========================================================= */
46958  #define R_SPI_B0_SPDCR2_RTRG_Pos      (0UL)          /*!< RTRG (Bit 0)                                          */
46959  #define R_SPI_B0_SPDCR2_RTRG_Msk      (0x3UL)        /*!< RTRG (Bitfield-Mask: 0x03)                            */
46960  #define R_SPI_B0_SPDCR2_TTRG_Pos      (8UL)          /*!< TTRG (Bit 8)                                          */
46961  #define R_SPI_B0_SPDCR2_TTRG_Msk      (0x300UL)      /*!< TTRG (Bitfield-Mask: 0x03)                            */
46962 /* =========================================================  SPSR  ========================================================== */
46963  #define R_SPI_B0_SPSR_SPCP_Pos        (8UL)          /*!< SPCP (Bit 8)                                          */
46964  #define R_SPI_B0_SPSR_SPCP_Msk        (0x700UL)      /*!< SPCP (Bitfield-Mask: 0x07)                            */
46965  #define R_SPI_B0_SPSR_SPECM_Pos       (12UL)         /*!< SPECM (Bit 12)                                        */
46966  #define R_SPI_B0_SPSR_SPECM_Msk       (0x7000UL)     /*!< SPECM (Bitfield-Mask: 0x07)                           */
46967  #define R_SPI_B0_SPSR_SPDRF_Pos       (23UL)         /*!< SPDRF (Bit 23)                                        */
46968  #define R_SPI_B0_SPSR_SPDRF_Msk       (0x800000UL)   /*!< SPDRF (Bitfield-Mask: 0x01)                           */
46969  #define R_SPI_B0_SPSR_OVRF_Pos        (24UL)         /*!< OVRF (Bit 24)                                         */
46970  #define R_SPI_B0_SPSR_OVRF_Msk        (0x1000000UL)  /*!< OVRF (Bitfield-Mask: 0x01)                            */
46971  #define R_SPI_B0_SPSR_IDLNF_Pos       (25UL)         /*!< IDLNF (Bit 25)                                        */
46972  #define R_SPI_B0_SPSR_IDLNF_Msk       (0x2000000UL)  /*!< IDLNF (Bitfield-Mask: 0x01)                           */
46973  #define R_SPI_B0_SPSR_MODF_Pos        (26UL)         /*!< MODF (Bit 26)                                         */
46974  #define R_SPI_B0_SPSR_MODF_Msk        (0x4000000UL)  /*!< MODF (Bitfield-Mask: 0x01)                            */
46975  #define R_SPI_B0_SPSR_PERF_Pos        (27UL)         /*!< PERF (Bit 27)                                         */
46976  #define R_SPI_B0_SPSR_PERF_Msk        (0x8000000UL)  /*!< PERF (Bitfield-Mask: 0x01)                            */
46977  #define R_SPI_B0_SPSR_UDRF_Pos        (28UL)         /*!< UDRF (Bit 28)                                         */
46978  #define R_SPI_B0_SPSR_UDRF_Msk        (0x10000000UL) /*!< UDRF (Bitfield-Mask: 0x01)                            */
46979  #define R_SPI_B0_SPSR_SPTEF_Pos       (29UL)         /*!< SPTEF (Bit 29)                                        */
46980  #define R_SPI_B0_SPSR_SPTEF_Msk       (0x20000000UL) /*!< SPTEF (Bitfield-Mask: 0x01)                           */
46981  #define R_SPI_B0_SPSR_CENDF_Pos       (30UL)         /*!< CENDF (Bit 30)                                        */
46982  #define R_SPI_B0_SPSR_CENDF_Msk       (0x40000000UL) /*!< CENDF (Bitfield-Mask: 0x01)                           */
46983  #define R_SPI_B0_SPSR_SPRF_Pos        (31UL)         /*!< SPRF (Bit 31)                                         */
46984  #define R_SPI_B0_SPSR_SPRF_Msk        (0x80000000UL) /*!< SPRF (Bitfield-Mask: 0x01)                            */
46985 /* ========================================================  SPTFSR  ========================================================= */
46986  #define R_SPI_B0_SPTFSR_TFDN_Pos      (0UL)          /*!< TFDN (Bit 0)                                          */
46987  #define R_SPI_B0_SPTFSR_TFDN_Msk      (0x7UL)        /*!< TFDN (Bitfield-Mask: 0x07)                            */
46988 /* ========================================================  SPRFSR  ========================================================= */
46989  #define R_SPI_B0_SPRFSR_RFDN_Pos      (0UL)          /*!< RFDN (Bit 0)                                          */
46990  #define R_SPI_B0_SPRFSR_RFDN_Msk      (0x7UL)        /*!< RFDN (Bitfield-Mask: 0x07)                            */
46991 /* =========================================================  SPPSR  ========================================================= */
46992  #define R_SPI_B0_SPPSR_SPEPS_Pos      (0UL)          /*!< SPEPS (Bit 0)                                         */
46993  #define R_SPI_B0_SPPSR_SPEPS_Msk      (0x1UL)        /*!< SPEPS (Bitfield-Mask: 0x01)                           */
46994 /* =========================================================  SPSRC  ========================================================= */
46995  #define R_SPI_B0_SPSRC_SPDRFC_Pos     (23UL)         /*!< SPDRFC (Bit 23)                                       */
46996  #define R_SPI_B0_SPSRC_SPDRFC_Msk     (0x800000UL)   /*!< SPDRFC (Bitfield-Mask: 0x01)                          */
46997  #define R_SPI_B0_SPSRC_OVRFC_Pos      (24UL)         /*!< OVRFC (Bit 24)                                        */
46998  #define R_SPI_B0_SPSRC_OVRFC_Msk      (0x1000000UL)  /*!< OVRFC (Bitfield-Mask: 0x01)                           */
46999  #define R_SPI_B0_SPSRC_MODFC_Pos      (26UL)         /*!< MODFC (Bit 26)                                        */
47000  #define R_SPI_B0_SPSRC_MODFC_Msk      (0x4000000UL)  /*!< MODFC (Bitfield-Mask: 0x01)                           */
47001  #define R_SPI_B0_SPSRC_PERFC_Pos      (27UL)         /*!< PERFC (Bit 27)                                        */
47002  #define R_SPI_B0_SPSRC_PERFC_Msk      (0x8000000UL)  /*!< PERFC (Bitfield-Mask: 0x01)                           */
47003  #define R_SPI_B0_SPSRC_UDRFC_Pos      (28UL)         /*!< UDRFC (Bit 28)                                        */
47004  #define R_SPI_B0_SPSRC_UDRFC_Msk      (0x10000000UL) /*!< UDRFC (Bitfield-Mask: 0x01)                           */
47005  #define R_SPI_B0_SPSRC_SPTEFC_Pos     (29UL)         /*!< SPTEFC (Bit 29)                                       */
47006  #define R_SPI_B0_SPSRC_SPTEFC_Msk     (0x20000000UL) /*!< SPTEFC (Bitfield-Mask: 0x01)                          */
47007  #define R_SPI_B0_SPSRC_CENDFC_Pos     (30UL)         /*!< CENDFC (Bit 30)                                       */
47008  #define R_SPI_B0_SPSRC_CENDFC_Msk     (0x40000000UL) /*!< CENDFC (Bitfield-Mask: 0x01)                          */
47009  #define R_SPI_B0_SPSRC_SPRFC_Pos      (31UL)         /*!< SPRFC (Bit 31)                                        */
47010  #define R_SPI_B0_SPSRC_SPRFC_Msk      (0x80000000UL) /*!< SPRFC (Bitfield-Mask: 0x01)                           */
47011 /* =========================================================  SPFCR  ========================================================= */
47012  #define R_SPI_B0_SPFCR_SPFRST_Pos     (0UL)          /*!< SPFRST (Bit 0)                                        */
47013  #define R_SPI_B0_SPFCR_SPFRST_Msk     (0x1UL)        /*!< SPFRST (Bitfield-Mask: 0x01)                          */
47014 
47015 /* =========================================================================================================================== */
47016 /* ================                                           R_TFU                                           ================ */
47017 /* =========================================================================================================================== */
47018 
47019 /* =========================================================  SCDT0  ========================================================= */
47020  #define R_TFU_SCDT0_SCDT0_Pos    (0UL)          /*!< SCDT0 (Bit 0)                                         */
47021  #define R_TFU_SCDT0_SCDT0_Msk    (0xffffffffUL) /*!< SCDT0 (Bitfield-Mask: 0xffffffff)                     */
47022 /* =========================================================  SCDT1  ========================================================= */
47023  #define R_TFU_SCDT1_SCDT1_Pos    (0UL)          /*!< SCDT1 (Bit 0)                                         */
47024  #define R_TFU_SCDT1_SCDT1_Msk    (0xffffffffUL) /*!< SCDT1 (Bitfield-Mask: 0xffffffff)                     */
47025 /* =========================================================  ATDT0  ========================================================= */
47026  #define R_TFU_ATDT0_ATDT0_Pos    (0UL)          /*!< ATDT0 (Bit 0)                                         */
47027  #define R_TFU_ATDT0_ATDT0_Msk    (0xffffffffUL) /*!< ATDT0 (Bitfield-Mask: 0xffffffff)                     */
47028 /* =========================================================  ATDT1  ========================================================= */
47029  #define R_TFU_ATDT1_ATDT1_Pos    (0UL)          /*!< ATDT1 (Bit 0)                                         */
47030  #define R_TFU_ATDT1_ATDT1_Msk    (0xffffffffUL) /*!< ATDT1 (Bitfield-Mask: 0xffffffff)                     */
47031 
47032 /** @} */ /* End of group PosMask_peripherals */
47033 
47034  #ifdef __cplusplus
47035 }
47036  #endif
47037 
47038 #endif                                 /* RA_H */
47039 
47040 /** @} */ /* End of group RA */
47041 
47042 /** @} */ /* End of group Renesas */
47043