1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_MEDIATEK_RTC_REG_COMMON_H 4 #define SOC_MEDIATEK_RTC_REG_COMMON_H 5 6 /* RTC registers */ 7 enum { 8 RTC_BBPU = 0x0588, 9 RTC_IRQ_STA = 0x058A, 10 RTC_IRQ_EN = 0x058C, 11 RTC_CII_EN = 0x058E, 12 }; 13 14 enum { 15 RTC_TC_SEC = 0x0592, 16 RTC_TC_MIN = 0x0594, 17 RTC_TC_HOU = 0x0596, 18 RTC_TC_DOM = 0x0598, 19 RTC_TC_DOW = 0x059A, 20 RTC_TC_MTH = 0x059C, 21 RTC_TC_YEA = 0x059E, 22 }; 23 24 enum { 25 RTC_AL_SEC = 0x05A0, 26 RTC_AL_MIN = 0x05A2, 27 RTC_AL_HOU = 0x05A4, 28 RTC_AL_DOM = 0x05A6, 29 RTC_AL_DOW = 0x05A8, 30 RTC_AL_MTH = 0x05AA, 31 RTC_AL_YEA = 0x05AC, 32 RTC_AL_MASK = 0x0590, 33 }; 34 35 enum { 36 RTC_OSC32CON = 0x05AE, 37 RTC_CON = 0x05C4, 38 RTC_WRTGR = 0x05C2, 39 }; 40 41 enum { 42 RTC_POWERKEY1 = 0x05B0, 43 RTC_POWERKEY2 = 0x05B2, 44 }; 45 46 enum { 47 RTC_PDN1 = 0x05B4, 48 RTC_PDN2 = 0x05B6, 49 RTC_SPAR0 = 0x05B8, 50 RTC_SPAR1 = 0x05BA, 51 RTC_PROT = 0x05BC, 52 RTC_DIFF = 0x05BE, 53 RTC_CALI = 0x05C0, 54 }; 55 56 enum { 57 RTC_CON_VBAT_LPSTA_RAW = 1U << 0, 58 RTC_CON_EOSC32_LPEN = 1U << 1, 59 RTC_CON_XOSC32_LPEN = 1U << 2, 60 RTC_CON_LPRST = 1U << 3, 61 RTC_CON_CDBO = 1U << 4, 62 RTC_CON_F32KOB = 1U << 5, 63 RTC_CON_GPO = 1U << 6, 64 RTC_CON_GOE = 1U << 7, 65 RTC_CON_GSR = 1U << 8, 66 RTC_CON_GSMT = 1U << 9, 67 RTC_CON_GPEN = 1U << 10, 68 RTC_CON_GPU = 1U << 11, 69 RTC_CON_GE4 = 1U << 12, 70 RTC_CON_GE8 = 1U << 13, 71 RTC_CON_GPI = 1U << 14, 72 RTC_CON_LPSTA_RAW = 1U << 15, 73 }; 74 75 enum { 76 RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13, 77 RTC_LPD_OPT_EOSC_LPD = 1U << 13, 78 RTC_LPD_OPT_XOSC_LPD = 2U << 13, 79 RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13, 80 RTC_LPD_OPT_MASK = 3U << 13, 81 }; 82 83 /* PMIC TOP Register Definition */ 84 enum { 85 PMIC_RG_SCK_TOP_CON0 = 0x050C, 86 }; 87 88 /* PMIC TOP Register Definition */ 89 enum { 90 PMIC_RG_TOP_CKPDN_CON0 = 0x010C, 91 PMIC_RG_TOP_CKPDN_CON0_SET = 0x010E, 92 PMIC_RG_TOP_CKPDN_CON0_CLR = 0x0110, 93 PMIC_RG_TOP_CKPDN_CON1 = 0x0112, 94 PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114, 95 PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116, 96 PMIC_RG_TOP_CKSEL_CON0 = 0x0118, 97 PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A, 98 PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C, 99 }; 100 101 enum { 102 PMIC_RG_FQMTR_32K_CK_PDN_SHIFT = 10, 103 PMIC_RG_FQMTR_CK_PDN_SHIFT = 11, 104 }; 105 106 enum { 107 PMIC_FQMTR_RST_SHIFT = 8, 108 }; 109 110 enum { 111 PMIC_FQMTR_CON0_XOSC32_CK = 0U << 0, 112 PMIC_FQMTR_CON0_DCXO_F32K_CK = 1U << 0, 113 PMIC_FQMTR_CON0_EOSC32_CK = 2U << 0, 114 PMIC_FQMTR_CON0_XOSC32_CK_DETECTON = 3U << 0, 115 PMIC_FQMTR_CON0_FQM26M_CK = 4U << 0, 116 PMIC_FQMTR_CON0_FQM32k_CK = 5U << 0, 117 PMIC_FQMTR_CON0_TEST_CK = 6U << 0, 118 PMIC_FQMTR_CON0_TCKSEL_MASK = 7U << 0, 119 PMIC_FQMTR_CON0_BUSY = 1U << 3, 120 PMIC_FQMTR_CON0_DCXO26M_EN = 1U << 4, 121 PMIC_FQMTR_CON0_FQMTR_EN = 1U << 15, 122 }; 123 124 enum { 125 RTC_FQMTR_LOW_BASE = 794 - 2, 126 RTC_FQMTR_HIGH_BASE = 794 + 2, 127 }; 128 129 enum { 130 RTC_XOSCCALI_START = 0x00, 131 RTC_XOSCCALI_END = 0x1f, 132 }; 133 134 #endif /* SOC_MEDIATEK_RTC_REG_COMMON_H */ 135