1 /* 2 * Copyright (c) 2015-2018, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_mmio_g9.h 24 //! \brief Define the MMIO registers access of Gen9 25 //! \details 26 //! 27 28 #ifndef __MHW_MMIO_G9_H__ 29 #define __MHW_MMIO_G9_H__ 30 31 32 // CS register offsets 33 #define CS_GENERAL_PURPOSE_REGISTER0_LO_OFFSET_G9 0x2600 34 #define CS_GENERAL_PURPOSE_REGISTER0_HI_OFFSET_G9 0x2604 35 #define CS_GENERAL_PURPOSE_REGISTER4_LO_OFFSET_G9 0x2620 36 #define CS_GENERAL_PURPOSE_REGISTER4_HI_OFFSET_G9 0x2624 37 #define CS_GENERAL_PURPOSE_REGISTER11_LO_OFFSET_G9 0x2658 38 #define CS_GENERAL_PURPOSE_REGISTER11_HI_OFFSET_G9 0x265C 39 #define CS_GENERAL_PURPOSE_REGISTER12_LO_OFFSET_G9 0x2660 40 #define CS_GENERAL_PURPOSE_REGISTER12_HI_OFFSET_G9 0x2664 41 42 // Vebox register offsets 43 // Used in Commen MI 44 #define GP_REGISTER0_LO_OFFSET_G9 0x1A600 45 #define GP_REGISTER0_HI_OFFSET_G9 0x1A604 46 #define GP_REGISTER4_LO_OFFSET_G9 0x1A620 47 #define GP_REGISTER4_HI_OFFSET_G9 0x1A624 48 #define GP_REGISTER11_LO_OFFSET_G9 0x1A658 49 #define GP_REGISTER11_HI_OFFSET_G9 0x1A65C 50 #define GP_REGISTER12_LO_OFFSET_G9 0x1A660 51 #define GP_REGISTER12_HI_OFFSET_G9 0x1A664 52 53 //VDBOX HCP register offsets 54 #define HCP_ENC_IMAGE_STATUS_MASK_REG_OFFSET_INIT_G9 0x1E9B8 55 #define HCP_ENC_IMAGE_STATUS_CTRL_REG_OFFSET_INIT_G9 0x1E9BC 56 #define HCP_ENC_BIT_STREAM_BYTE_COUNT_FRAME_REG_OFFSET_INIT_G9 0x1E9A0 57 #define HCP_ENC_BIT_STREAM_SE_BIT_COUNT_FRAME_REG_OFFSET_INIT_G9 0x1E9A8 58 #define HCP_ENC_BIT_STREAM_BYTE_COUNT_FRAME_NO_HEADER_REG_OFFSET_INIT_G9 0x1E9A4 59 #define HCP_ENC_QP_STATUS_COUNT_REG_OFFSET_INIT_G9 0x1E9C0 60 #define HCP_VP9_ENC_BITSTREAM_BYTE_COUNT_FRAME_REG_OFFSET_INIT_G9 0x1E9E0 61 #define HCP_VP9_ENC_BITSTREAM_BYTE_COUNT_FRAME_NO_HEADER_REG_OFFSET_INIT_G9 0x1E9E4 62 #define HCP_VP9_ENC_IMAGE_STATUS_MASK_REG_OFFSET_INIT_G9 0x1E9F0 63 #define HCP_VP9_ENC_IMAGE_STATUS_CTRL_REG_OFFSET_INIT_G9 0x1E9F4 64 #define HCP_DEC_STATUS_REG_OFFSET_INIT_G9 0x1E900 65 #define HCP_CABAC_STATUS_REG_OFFSET_INIT_G9 0x1E904 66 67 //VDBOX HCP register initial values 68 #define HCP_ENC_SLICE_COUNT_REG_OFFSET_INIT_G9 0 69 #define HCP_ENC_VDENC_MODE_TIMER_REG_OFFSET_INIT_G9 0 70 #define CS_ENGINE_ID_OFFSET_INIT_G9 0 71 72 73 74 //VDBOX HUC 75 #define HUC_UKERNEL_HDR_INFO_REG_OFFSET_NODE_1_INIT_G9 0x0D014 76 #define HUC_STATUS_REG_OFFSET_NODE_1_INIT_G9 0x0D000 77 #define HUC_STATUS2_REG_OFFSET_NODE_1_INIT_G9 0x0D3B0 78 79 80 //VDBOX MFX register offsets 81 #define GENERAL_PURPOSE_REGISTER0_LO_OFFSET_NODE_1_INIT_G9 0x12600 82 #define GENERAL_PURPOSE_REGISTER0_HI_OFFSET_NODE_1_INIT_G9 0x12604 83 #define GENERAL_PURPOSE_REGISTER4_LO_OFFSET_NODE_1_INIT_G9 0x12620 84 #define GENERAL_PURPOSE_REGISTER4_HI_OFFSET_NODE_1_INIT_G9 0x12624 85 #define GENERAL_PURPOSE_REGISTER11_LO_OFFSET_NODE_1_INIT_G9 0x12658 86 #define GENERAL_PURPOSE_REGISTER11_HI_OFFSET_NODE_1_INIT_G9 0x1265C 87 #define GENERAL_PURPOSE_REGISTER12_LO_OFFSET_NODE_1_INIT_G9 0x12660 88 #define GENERAL_PURPOSE_REGISTER12_HI_OFFSET_NODE_1_INIT_G9 0x12664 89 #define MFC_IMAGE_STATUS_MASK_REG_OFFSET_NODE_1_INIT_G9 0x128B4 90 #define MFC_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_1_INIT_G9 0x128B8 91 #define MFC_AVC_NUM_SLICES_REG_OFFSET_NODE_1_INIT_G9 0x12954 92 #define MFC_QP_STATUS_COUNT_OFFSET_NODE_1_INIT_G9 0x128BC 93 #define MFX_ERROR_FLAG_REG_OFFSET_NODE_1_INIT_G9 0x12800 94 #define MFX_FRAME_CRC_REG_OFFSET_NODE_1_INIT_G9 0x12850 95 #define MFX_MB_COUNT_REG_OFFSET_NODE_1_INIT_G9 0x12868 96 #define MFC_BITSTREAM_BYTECOUNT_FRAME_REG_OFFSET_NODE_1_INIT_G9 0x128A0 97 #define MFC_BITSTREAM_SE_BITCOUNT_FRAME_REG_OFFSET_NODE_1_INIT_G9 0x128A4 98 #define MFC_BITSTREAM_BYTECOUNT_SLICE_REG_OFFSET_NODE_1_INIT_G9 0x128D0 99 #define MFC_VP8_BITSTREAM_BYTECOUNT_FRAME_REG_OFFSET_NODE_1_INIT_G9 0x12908 100 #define MFC_VP8_IMAGE_STATUS_MASK_REG_OFFSET_NODE_1_INIT_G9 0x12900 101 #define MFC_VP8_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_1_INIT_G9 0x12904 102 #define MFX_VP8_BRC_DQ_INDEX_REG_OFFSET_NODE_1_INIT_G9 0x12910 103 #define MFX_VP8_BRC_LOOP_FILTER_REG_OFFSET_NODE_1_INIT_G9 0x12914 104 #define MFX_VP8_BRC_CUMULATIVE_DQ_INDEX01_REG_OFFSET_NODE_1_INIT_G9 0x12918 105 #define MFX_VP8_BRC_CUMULATIVE_DQ_INDEX23_REG_OFFSET_NODE_1_INIT_G9 0x1291C 106 #define MFX_VP8_BRC_CUMULATIVE_LOOP_FILTER01_REG_OFFSET_NODE_1_INIT_G9 0x12920 107 #define MFX_VP8_BRC_CUMULATIVE_LOOP_FILTER23_REG_OFFSET_NODE_1_INIT_G9 0x12924 108 #define MFX_VP8_BRC_CONVERGENCE_STATUS_REG_OFFSET_NODE_1_INIT_G9 0x12928 109 #define MFX_LRA0_REG_OFFSET_NODE_1_INIT_G9 0x04A50 110 #define MFX_LRA1_REG_OFFSET_NODE_1_INIT_G9 0x04A54 111 #define MFX_LRA2_REG_OFFSET_NODE_1_INIT_G9 0x04A58 112 113 #define GENERAL_PURPOSE_REGISTER0_LO_OFFSET_NODE_2_INIT_G9 0x1C600 114 #define GENERAL_PURPOSE_REGISTER0_HI_OFFSET_NODE_2_INIT_G9 0x1C604 115 #define GENERAL_PURPOSE_REGISTER4_LO_OFFSET_NODE_2_INIT_G9 0x1C620 116 #define GENERAL_PURPOSE_REGISTER4_HI_OFFSET_NODE_2_INIT_G9 0x1C624 117 #define GENERAL_PURPOSE_REGISTER11_LO_OFFSET_NODE_2_INIT_G9 0x1C658 118 #define GENERAL_PURPOSE_REGISTER11_HI_OFFSET_NODE_2_INIT_G9 0x1C65C 119 #define GENERAL_PURPOSE_REGISTER12_LO_OFFSET_NODE_2_INIT_G9 0x1C660 120 #define GENERAL_PURPOSE_REGISTER12_HI_OFFSET_NODE_2_INIT_G9 0x1C664 121 #define MFC_IMAGE_STATUS_MASK_REG_OFFSET_NODE_2_INIT_G9 0x1C8B4 122 #define MFC_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_2_INIT_G9 0x1C8B8 123 #define MFC_AVC_NUM_SLICES_REG_OFFSET_NODE_2_INIT_G9 0x1C954 124 #define MFC_QP_STATUS_COUNT_OFFSET_NODE_2_INIT_G9 0x1C8BC 125 #define MFX_ERROR_FLAG_REG_OFFSET_NODE_2_INIT_G9 0x1C800 126 #define MFX_FRAME_CRC_REG_OFFSET_NODE_2_INIT_G9 0x1C850 127 #define MFX_MB_COUNT_REG_OFFSET_NODE_2_INIT_G9 0x1C868 128 #define MFC_BITSTREAM_BYTECOUNT_FRAME_REG_OFFSET_NODE_2_INIT_G9 0x1C8A0 129 #define MFC_BITSTREAM_SE_BITCOUNT_FRAME_REG_OFFSET_NODE_2_INIT_G9 0x1C8A4 130 #define MFC_BITSTREAM_BYTECOUNT_SLICE_REG_OFFSET_NODE_2_INIT_G9 0x1C8D0 131 #define MFC_VP8_BITSTREAM_BYTECOUNT_FRAME_REG_OFFSET_NODE_2_INIT_G9 0x1C908 132 #define MFC_VP8_IMAGE_STATUS_MASK_REG_OFFSET_NODE_2_INIT_G9 0x1C900 133 #define MFC_VP8_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_2_INIT_G9 0x1C904 134 #define MFX_VP8_BRC_DQ_INDEX_REG_OFFSET_NODE_2_INIT_G9 0x1C910 135 #define MFX_VP8_BRC_LOOP_FILTER_REG_OFFSET_NODE_2_INIT_G9 0x1C914 136 #define MFX_VP8_BRC_CUMULATIVE_DQ_INDEX01_REG_OFFSET_NODE_2_INIT_G9 0X1C918 137 #define MFX_VP8_BRC_CUMULATIVE_DQ_INDEX23_REG_OFFSET_NODE_2_INIT_G9 0X1C91C 138 #define MFX_VP8_BRC_CUMULATIVE_LOOP_FILTER01_REG_OFFSET_NODE_2_INIT_G9 0X1C920 139 #define MFX_VP8_BRC_CUMULATIVE_LOOP_FILTER23_REG_OFFSET_NODE_2_INIT_G9 0X1C924 140 #define MFX_VP8_BRC_CONVERGENCE_STATUS_REG_OFFSET_NODE_2_INIT_G9 0X1C928 141 142 143 //VDBOX MFX register initial values 144 #define MFX_LRA0_REG_OFFSET_NODE_2_INIT_G9 0 145 #define MFX_LRA1_REG_OFFSET_NODE_2_INIT_G9 0 146 #define MFX_LRA2_REG_OFFSET_NODE_2_INIT_G9 0 147 148 // VDBOX ENCODER 149 #define MHW_CS_GENERAL_PURPOSE_REGISTER_BASE_G9 (0x2600) 150 #define CS_GPR_REGISTER_INDEX(index) (MHW_CS_GENERAL_PURPOSE_REGISTER_BASE_G9 + 8 * (index)) 151 152 // HAL 153 #define REG_GPR_BASE_G9 MHW_CS_GENERAL_PURPOSE_REGISTER_BASE_G9 154 #define REG_TIMESTAMP_BASE_G9 0x2358 155 156 // RENDER 157 #define L3_CACHE_CNTL2_REG_OFFSET_G9 0xB020 158 #define L3_CACHE_CNTL3_REG_OFFSET_G9 0xB024 159 #define L3_CACHE_SQC_REG_OFFSET_G9 0xB100 160 161 162 #endif //__MHW_MMIO_G9_H__