1## SPDX-License-Identifier: GPL-2.0-only 2 3config NORTHBRIDGE_INTEL_SANDYBRIDGE 4 bool 5 select CACHE_MRC_SETTINGS 6 select CPU_INTEL_MODEL_206AX 7 select HAVE_DEBUG_RAM_SETUP 8 select INTEL_GMA_ACPI 9 select NEED_SMALL_2MB_PAGE_TABLES 10 select USE_DDR3 11 12if NORTHBRIDGE_INTEL_SANDYBRIDGE 13 14config CHIPSET_DEVICETREE 15 default "northbridge/intel/sandybridge/chipset.cb" 16 17config SANDYBRIDGE_VBOOT_IN_ROMSTAGE 18 bool 19 default n 20 help 21 Selected by boards to force VBOOT_STARTS_IN_ROMSTAGE. 22 23config SANDYBRIDGE_VBOOT_IN_BOOTBLOCK 24 depends on VBOOT 25 depends on !SANDYBRIDGE_VBOOT_IN_ROMSTAGE 26 bool "Start verstage in bootblock" 27 default y 28 select VBOOT_STARTS_IN_BOOTBLOCK 29 help 30 Sandy Bridge can either start verstage in a separate stage 31 right after the bootblock has run or it can start it 32 after romstage for compatibility reasons. 33 Sandy Bridge however uses a mrc.bin to initialize memory which 34 needs to be located at a fixed offset. Therefore even with 35 a separate verstage starting after the bootblock that same 36 binary is used meaning a jump is made from RW to the RO region 37 and back to the RW region after the binary is done. 38 39config VBOOT 40 select VBOOT_MUST_REQUEST_DISPLAY 41 select VBOOT_STARTS_IN_ROMSTAGE if !SANDYBRIDGE_VBOOT_IN_BOOTBLOCK 42 43config USE_NATIVE_RAMINIT 44 bool "Use native raminit" 45 default y 46 help 47 Select if you want to use coreboot implementation of raminit rather than 48 System Agent/MRC.bin. You should answer Y. 49 50config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES 51 bool "[OVERCLOCK] Ignore CAPID fuses that limit max DRAM frequency" 52 default n 53 depends on USE_NATIVE_RAMINIT 54 help 55 Ignore the CAPID fuses that might limit the maximum DRAM frequency 56 on overclocking-capable parts. By selecting this option, the fuse 57 values will be ignored and the only limits on DRAM frequency are 58 determined by SPD values, per-board devicetree settings and hard 59 limits in the northbridge's MPLL. Disabled by default as it can 60 cause instability. 61 Consider this to be an overclocking option. Handle with care! 62 63config NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS 64 bool "[OVERCLOCK] Ignore XMP max DIMMs per channel" 65 default n 66 depends on USE_NATIVE_RAMINIT 67 help 68 The more DIMMs are in a channel, the more signal integrity worsens. 69 Because of this, some DIMMs only support running at XMP timings if 70 the number of DIMMs in the channel is below a limit. This limit is 71 usually 1, i.e. there must be no other DIMMs in the channel to use 72 XMP timings. Otherwise, non-XMP timings are used. 73 When this option is enabled, the max DIMMs per channel restriction 74 in XMP is ignored. Depending on available margins, this could work 75 but it can also result in system instability. 76 Consider this to be an overclocking option. Handle with care! 77 78config NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE 79 bool "Ignore XMP profile requested voltage" 80 default n 81 depends on USE_NATIVE_RAMINIT 82 help 83 Native raminit only supports 1.5V operation, but there are DIMMs 84 which request 1.65V operation in XMP profiles. This option allows 85 raminit to use these XMP profiles anyway, instead of falling back 86 to non-XMP settings. 87 Disabled by default because it allows forcing memory to run out of 88 specification. Consider this to be an overclocking option. 89 Handle with care! 90 91config CBFS_SIZE 92 default 0x100000 93 94config VGA_BIOS_ID 95 string 96 default "8086,0106" 97 98config ECAM_MMCONF_BASE_ADDRESS 99 default 0xf0000000 100 help 101 The MRC blob requires it to be at 0xf0000000. 102 103config ECAM_MMCONF_BUS_NUMBER 104 int 105 default 64 106 107config DCACHE_RAM_BASE 108 hex 109 default 0xfefe0000 110 111config DCACHE_BSP_STACK_SIZE 112 hex 113 default 0x10000 114 help 115 The amount of BSP stack anticipated in bootblock and 116 other stages. 117 118if USE_NATIVE_RAMINIT 119 120config DCACHE_RAM_SIZE 121 hex 122 default 0x20000 123 124config DCACHE_RAM_MRC_VAR_SIZE 125 hex 126 default 0x0 127 128config RAMINIT_ALWAYS_ALLOW_DLL_OFF 129 bool "Also enable memory DLL-off mode on desktops and servers" 130 default n 131 help 132 If enabled, allow enabling DLL-off mode for platforms other than 133 mobile. Saves power at the expense of higher exit latencies. Has 134 no effect on mobile platforms, where DLL-off is always allowed. 135 Power down is disabled for stability when running at high clocks. 136 137config RAMINIT_ENABLE_ECC 138 bool "Enable ECC if supported" 139 default y 140 help 141 Enable ECC if supported by both, host and RAM. 142 143endif # USE_NATIVE_RAMINIT 144 145if !USE_NATIVE_RAMINIT 146 147config DCACHE_RAM_SIZE 148 hex 149 default 0x17000 150 151config DCACHE_RAM_MRC_VAR_SIZE 152 hex 153 default 0x9000 154 155config MRC_FILE 156 string "Intel System Agent path and filename" 157 default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin" 158 help 159 The path and filename of the file to use as System Agent 160 binary. 161 162endif # !USE_NATIVE_RAMINIT 163 164config INTEL_GMA_BCLV_OFFSET 165 default 0x48254 166 167config FIXED_MCHBAR_MMIO_BASE 168 default 0xfed10000 169 170config FIXED_DMIBAR_MMIO_BASE 171 default 0xfed18000 172 173config FIXED_EPBAR_MMIO_BASE 174 default 0xfed19000 175 176config PRERAM_CBFS_CACHE_SIZE 177 default 0x0 178 179endif 180