1 /* 2 * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef QEMU_PAS_DEF_H 7 #define QEMU_PAS_DEF_H 8 9 #include <lib/gpt_rme/gpt_rme.h> 10 #include "platform_def.h" 11 12 /***************************************************************************** 13 * PAS regions used to initialize the Granule Protection Table (GPT) 14 ****************************************************************************/ 15 16 /* 17 * The PA space is initially mapped in the GPT as follows: 18 * 19 * =========================================================================== 20 * Base Addr | Size |L? GPT|PAS |Content |Comment 21 * =========================================================================== 22 * | 1GB |L0 GPT|ANY |Flash | 23 * 00000000 | | | |IO | 24 * --------------------------------------------------------------------------- 25 * 224MB | 1KB |L0 GPT|ANY |Secure RAM (EL3) | 26 * 0e000000 | | | | (shared) | 27 * --------------------------------------------------------------------------- 28 * | 1MB-1KB |L1 GPT|ROOT |Secure RAM (EL3) | 29 * 0e001000 | | | | | 30 * --------------------------------------------------------------------------- 31 * 225MB | 14MB |L1 GPT|SECURE|Secure RAM | 32 * 0e100000 | | | | (EL2, EL1) | 33 * --------------------------------------------------------------------------- 34 * | 1MB+8KB |L1 GPT|ROOT |L0 and L1 GPTs | 35 * 0eefe000 | | | | | 36 * --------------------------------------------------------------------------- 37 * 240MB | 800MB |L0 GPT|ANY |IO | 38 * 0f000000 | | | | | 39 * --------------------------------------------------------------------------- 40 * 1GB | 1MB |L1 GPT|NS |DRAM | 41 * 40000000 | | | | (device tree) | 42 * --------------------------------------------------------------------------- 43 * 1GB+1MB | 24MB |L1 GPT|REALM |DRAM (RMM) | 44 * 40100000 | | | | | 45 * --------------------------------------------------------------------------- 46 * 1GB+25MB | 3GB |L1 GPT|NS |DRAM (kernel) | Limit set by 47 * 41900000 | | | | | NS_DRAM0_SIZE 48 * --------------------------------------------------------------------------- 49 * 256GB | 512+GB |L0 GPT|ANY |IO | Floating. Higher 50 * 40000000000 | | | | | when RAM>256GB 51 * ---------------------------------------------------------------------------- 52 */ 53 54 /* EL3 SRAM */ 55 #define QEMU_PAS_ROOT_BASE BL_RAM_BASE 56 #define QEMU_PAS_ROOT_SIZE BL_RAM_SIZE 57 58 /* Secure DRAM */ 59 #define QEMU_PAS_SEC_BASE SEC_DRAM_BASE 60 #define QEMU_PAS_SEC_SIZE (SEC_DRAM_SIZE - RME_GPT_DRAM_SIZE) 61 62 /* GPTs */ 63 #define QEMU_PAS_GPT_BASE RME_GPT_DRAM_BASE 64 #define QEMU_PAS_GPT_SIZE RME_GPT_DRAM_SIZE 65 66 /* RMM */ 67 #define QEMU_PAS_RMM_BASE RMM_BASE 68 #define QEMU_PAS_RMM_SIZE PLAT_QEMU_RMM_SIZE 69 70 /* Shared area between EL3 and RMM */ 71 #define QEMU_PAS_RMM_SHARED_BASE RMM_SHARED_BASE 72 #define QEMU_PAS_RMM_SHARED_SIZE RMM_SHARED_SIZE 73 74 #define QEMU_PAS_NS0_BASE NS_DRAM0_BASE 75 #define QEMU_PAS_NS0_SIZE PLAT_QEMU_DT_MAX_SIZE 76 #define QEMU_PAS_NS1_BASE (REALM_DRAM_BASE + REALM_DRAM_SIZE) 77 #define QEMU_PAS_NS1_SIZE (NS_DRAM0_SIZE - \ 78 (QEMU_PAS_NS0_SIZE + REALM_DRAM_SIZE)) 79 80 #define QEMU_PAS_ROOT GPT_MAP_REGION_GRANULE(QEMU_PAS_ROOT_BASE, \ 81 QEMU_PAS_ROOT_SIZE, \ 82 GPT_GPI_ROOT) 83 84 #define QEMU_PAS_SECURE GPT_MAP_REGION_GRANULE(QEMU_PAS_SEC_BASE, \ 85 QEMU_PAS_SEC_SIZE, \ 86 GPT_GPI_SECURE) 87 88 #define QEMU_PAS_GPTS GPT_MAP_REGION_GRANULE(QEMU_PAS_GPT_BASE, \ 89 QEMU_PAS_GPT_SIZE, \ 90 GPT_GPI_ROOT) 91 92 #define QEMU_PAS_NS0 GPT_MAP_REGION_GRANULE(QEMU_PAS_NS0_BASE, \ 93 QEMU_PAS_NS0_SIZE, \ 94 GPT_GPI_NS) 95 96 #define QEMU_PAS_NS1 GPT_MAP_REGION_GRANULE(QEMU_PAS_NS1_BASE, \ 97 QEMU_PAS_NS1_SIZE, \ 98 GPT_GPI_NS) 99 100 #define QEMU_PAS_REALM GPT_MAP_REGION_GRANULE(QEMU_PAS_RMM_BASE, \ 101 QEMU_PAS_RMM_SIZE + \ 102 QEMU_PAS_RMM_SHARED_SIZE, \ 103 GPT_GPI_REALM) 104 105 /* GPT Configuration options */ 106 #define PLATFORM_L0GPTSZ GPCCR_L0GPTSZ_30BITS 107 108 #endif /* QEMU_PAS_DEF_H */ 109