1 /* 2 * Copyright (c) 2024, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_mfx_hwcmd_xe2_hpm.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of Xe2_HPM as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 29 // DO NOT EDIT 30 31 #ifndef __MHW_VDBOX_MFX_HWCMD_XE2_HPM_H__ 32 #define __MHW_VDBOX_MFX_HWCMD_XE2_HPM_H__ 33 34 #pragma once 35 #pragma pack(1) 36 37 #include "mhw_hwcmd.h" 38 #include <cstdint> 39 #include <cstddef> 40 #include "media_class_trace.h" 41 42 namespace mhw 43 { 44 namespace vdbox 45 { 46 namespace mfx 47 { 48 namespace xe_lpm_plus_base 49 { 50 namespace v1 51 { 52 class Cmd 53 { 54 public: 55 virtual ~Cmd() = default; 56 GetOpLength(uint32_t uiLength)57 static uint32_t GetOpLength(uint32_t uiLength) 58 { 59 return __CODEGEN_OP_LENGTH(uiLength); 60 } 61 62 //! 63 //! \brief MEMORYADDRESSATTRIBUTES 64 //! \details 65 //! This field controls the priority of arbitration used in the GAC/GAM 66 //! pipeline for this surface. It defines the attributes for VDBOX addresses 67 //! on BDW+. 68 //! 69 struct MEMORYADDRESSATTRIBUTES_CMD 70 { 71 union 72 { 73 struct 74 { 75 uint32_t Reserved0 : __CODEGEN_BITFIELD(0, 0); //!< Reserved 76 uint32_t BaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD(1, 6); //!< Base Address - Index to Memory Object Control State (MOCS) Tables 77 uint32_t BaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< Base Address - Arbitration Priority Control 78 uint32_t BaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD(9, 9); //!< Base Address - Memory Compression Enable 79 uint32_t CompressionType : __CODEGEN_BITFIELD(10, 10); //!< COMPRESSION_TYPE 80 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 81 uint32_t BaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12); //!< BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 82 uint32_t Tilemode : __CODEGEN_BITFIELD(13, 14); //!< TILEMODE 83 uint32_t Reserved15 : __CODEGEN_BITFIELD(15, 31); //!< Reserved 84 }; 85 uint32_t Value; 86 } DW0; 87 88 //! \name Local enumerations 89 90 //! \brief COMPRESSION_TYPE 91 //! \details 92 //! Indicates if buffer is render/media compressed. 93 enum COMPRESSION_TYPE 94 { 95 COMPRESSION_TYPE_MEDIACOMPRESSIONENABLE = 0, //!< No additional details 96 COMPRESSION_TYPE_RENDERCOMPRESSIONENABLE = 1, //!< Only support rendered compression with unified memory 97 }; 98 99 //! \brief BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 100 //! \details 101 //! This field controls if the Row Store is going to store inside Media 102 //! Cache (rowstore cache) or to LLC. 103 enum BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 104 { 105 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 106 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage. 107 }; 108 109 enum TILEMODE 110 { 111 TILEMODE_LINEAR = 0, //!< No additional details 112 TILEMODE_TILES_64K = 1, //!< No additional details 113 TILEMODE_TILEX = 2, //!< No additional details 114 TILEMODE_TILEF = 3, //!< No additional details 115 }; 116 117 //! \name Initializations 118 119 //! \brief Explicit member initialization function 120 MEMORYADDRESSATTRIBUTES_CMD(); 121 122 static const size_t dwSize = 1; 123 static const size_t byteSize = 4; 124 }; 125 126 //! 127 //! \brief SPLITBASEADDRESS64BYTEALIGNED 128 //! \details 129 //! Specifies a 64-bit (48-bit canonical) 64-byte aligned memory base 130 //! address. 131 //! 132 //! Bits 63:48 must be zero. 133 //! 134 struct SPLITBASEADDRESS64BYTEALIGNED_CMD 135 { 136 union 137 { 138 struct 139 { 140 uint64_t Reserved0 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 141 uint64_t BaseAddress : __CODEGEN_BITFIELD(6, 56); //!< Base Address 142 uint64_t Reserved57 : __CODEGEN_BITFIELD(57, 63); //!< Reserved 143 }; 144 uint32_t Value[2]; 145 } DW0_1; 146 147 //! \name Local enumerations 148 149 //! \name Initializations 150 151 //! \brief Explicit member initialization function 152 SPLITBASEADDRESS64BYTEALIGNED_CMD(); 153 154 static const size_t dwSize = 2; 155 static const size_t byteSize = 8; 156 }; 157 158 //! 159 //! \brief SPLITBASEADDRESS4KBYTEALIGNED 160 //! \details 161 //! Specifies a 64-bit (48-bit canonical) 4K-byte aligned memory base 162 //! address. GraphicsAddress is a 64-bit value [63:0], but only a portion of 163 //! it is used by hardware. The upper reserved bits are ignored and MBZ. 164 //! 165 //! Bits 63:48 must be zero. 166 //! 167 struct SPLITBASEADDRESS4KBYTEALIGNED_CMD 168 { 169 union 170 { 171 struct 172 { 173 uint64_t Reserved0 : __CODEGEN_BITFIELD(0, 11); //!< Reserved 174 uint64_t BaseAddress : __CODEGEN_BITFIELD(12, 56); //!< Base Address 175 uint64_t Reserved57 : __CODEGEN_BITFIELD(57, 63); //!< Reserved 176 }; 177 uint32_t Value[2]; 178 } DW0_1; 179 180 //! \name Local enumerations 181 182 //! \name Initializations 183 184 //! \brief Explicit member initialization function 185 SPLITBASEADDRESS4KBYTEALIGNED_CMD(); 186 187 static const size_t dwSize = 2; 188 static const size_t byteSize = 8; 189 }; 190 191 //! 192 //! \brief MFX_QM_STATE 193 //! \details 194 //! This is a common state command for AVC encoder modes. For encoder, it 195 //! represents both the forward QM matrices as well as the decoding QM 196 //! matrices.This is a Frame-level state. Only Scaling Lists specified by an 197 //! application are being sent to the hardware. The driver is responsible 198 //! for determining the final set of scaling lists to be used for decoding 199 //! the current slice, based on the AVC Spec Table 7-2 (Fall-Back Rules A 200 //! and B).In MFX AVC PAK mode, PAK needs both forward Q scaling lists and 201 //! IQ scaling lists. The IQ scaling lists are sent as in MFD in raster scan 202 //! order. But the Forward Q scaling lists are sent in column-wise raster 203 //! order (column-by-column) to simplify the H/W. Driver will perform all 204 //! the scan order conversion for both ForwardQ and IQ. 205 //! 206 struct MFX_QM_STATE_CMD 207 { 208 union 209 { 210 struct 211 { 212 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 213 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 214 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 215 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 216 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 217 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 218 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 219 }; 220 uint32_t Value; 221 } DW0; 222 union 223 { 224 struct 225 { 226 uint32_t Mpeg2 : __CODEGEN_BITFIELD(0, 1); //!< MPEG2, MPEG2- Decoder Only 227 uint32_t Reserved34 : __CODEGEN_BITFIELD(2, 31); //!< Reserved, MPEG2- Decoder Only 228 } Obj0; 229 struct 230 { 231 uint32_t Jpeg : __CODEGEN_BITFIELD(0, 1); //!< JPEG, JPEG- Encoder Only 232 uint32_t Reserved34 : __CODEGEN_BITFIELD(2, 31); //!< Reserved, JPEG- Encoder Only 233 } Obj1; 234 struct 235 { 236 uint32_t Avc : __CODEGEN_BITFIELD(0, 1); //!< AVC, AVC- Decoder Only 237 uint32_t Reserved34 : __CODEGEN_BITFIELD(2, 31); //!< Reserved, AVC- Decoder Only 238 } Obj2; 239 uint32_t Value; 240 } DW1; 241 uint32_t ForwardQuantizerMatrix[16]; //!< Forward Quantizer Matrix 242 243 //! \name Local enumerations 244 245 enum SUBOPCODE_B 246 { 247 SUBOPCODE_B_UNNAMED7 = 7, //!< No additional details 248 }; 249 250 enum SUBOPCODE_A 251 { 252 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 253 }; 254 255 enum MEDIA_COMMAND_OPCODE 256 { 257 MEDIA_COMMAND_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 258 }; 259 260 enum PIPELINE 261 { 262 PIPELINE_MFXMULTIDW = 2, //!< No additional details 263 }; 264 265 enum COMMAND_TYPE 266 { 267 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 268 }; 269 270 //! \brief MPEG2 271 //! \details 272 //! For MPEG2 QM Type: This field specifies which Quantizer Matrix is 273 //! loaded. 274 enum MPEG2 275 { 276 MPEG2_MPEGINTRAQUANTIZERMATRIX = 0, //!< No additional details 277 MPEG2_MPEGNONINTRAQUANTIZERMATRIX = 1, //!< No additional details 278 }; 279 280 //! \brief JPEG 281 //! \details 282 //! For JPEG QM Type:This field specifies which Quantizer Matrix is 283 //! loaded. 284 enum JPEG 285 { 286 JPEG_JPEGLUMAYQUANTIZERMATRIX_ORR = 0, //!< No additional details 287 JPEG_JPEGCHROMACBQUANTIZERMATRIX_ORG = 1, //!< No additional details 288 JPEG_JPEGCHROMACRQUANTIZERMATRIX_ORB = 2, //!< No additional details 289 }; 290 291 //! \brief AVC 292 //! \details 293 //! For AVC QM Type: This field specifies which Quantizer Matrix is 294 //! loaded. 295 enum AVC 296 { 297 AVC_AVC4X4INTRAMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 0, //!< No additional details 298 AVC_AVC4X4INTERMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 1, //!< No additional details 299 AVC_AVC8X8INTRAMATRIX = 2, //!< No additional details 300 AVC_AVC8X8INTERMATRIX = 3, //!< No additional details 301 }; 302 303 //! \name Initializations 304 305 //! \brief Explicit member initialization function 306 MFX_QM_STATE_CMD(); 307 308 static const size_t dwSize = 18; 309 static const size_t byteSize = 72; 310 }; 311 312 //! 313 //! \brief MFX_FQM_STATE 314 //! \details 315 //! This is a common state command for AVC encoder modes. For encoder, it 316 //! represents both the forward QM matrices as well as the decoding QM 317 //! matrices.This is a Frame-level state. Only Scaling Lists specified by an 318 //! application are being sent to the hardware. The driver is responsible 319 //! for determining the final set of scaling lists to be used for decoding 320 //! the current slice, based on the AVC Spec Table 7-2 (Fall-Back Rules A 321 //! and B).In MFX AVC PAK mode, PAK needs both forward Q scaling lists and 322 //! IQ scaling lists. The IQ scaling lists are sent as in MFD in raster scan 323 //! order. But the Forward Q scaling lists are sent in column-wise raster 324 //! order (column-by-column) to simplify the H/W. Driver will perform all 325 //! the scan order conversion for both ForwardQ and IQ. 326 //! 327 struct MFX_FQM_STATE_CMD 328 { 329 union 330 { 331 struct 332 { 333 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 334 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 335 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 336 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 337 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 338 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 339 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 340 }; 341 uint32_t Value; 342 } DW0; 343 union 344 { 345 struct 346 { 347 uint32_t Mpeg2 : __CODEGEN_BITFIELD(0, 1); //!< MPEG2, MPEG2- Decoder Only 348 uint32_t Reserved34 : __CODEGEN_BITFIELD(2, 31); //!< Reserved, MPEG2- Decoder Only 349 } Obj0; 350 struct 351 { 352 uint32_t Jpeg : __CODEGEN_BITFIELD(0, 1); //!< JPEG, JPEG- Encoder Only 353 uint32_t Reserved34 : __CODEGEN_BITFIELD(2, 31); //!< Reserved, JPEG- Encoder Only 354 } Obj1; 355 struct 356 { 357 uint32_t Avc : __CODEGEN_BITFIELD(0, 1); //!< AVC, AVC- Decoder Only 358 uint32_t Reserved34 : __CODEGEN_BITFIELD(2, 31); //!< Reserved, AVC- Decoder Only 359 } Obj2; 360 uint32_t Value; 361 } DW1; 362 uint32_t ForwardQuantizerMatrix[32]; //!< Forward Quantizer Matrix 363 364 //! \name Local enumerations 365 366 enum SUBOPCODE_B 367 { 368 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 369 }; 370 371 enum SUBOPCODE_A 372 { 373 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 374 }; 375 376 enum MEDIA_COMMAND_OPCODE 377 { 378 MEDIA_COMMAND_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 379 }; 380 381 enum PIPELINE 382 { 383 PIPELINE_MFXMULTIDW = 2, //!< No additional details 384 }; 385 386 enum COMMAND_TYPE 387 { 388 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 389 }; 390 391 //! \brief MPEG2 392 //! \details 393 //! For MPEG2 QM Type: This field specifies which Quantizer Matrix is 394 //! loaded. 395 enum MPEG2 396 { 397 MPEG2_MPEGINTRAQUANTIZERMATRIX = 0, //!< No additional details 398 MPEG2_MPEGNONINTRAQUANTIZERMATRIX = 1, //!< No additional details 399 }; 400 401 //! \brief JPEG 402 //! \details 403 //! For JPEG QM Type:This field specifies which Quantizer Matrix is 404 //! loaded. 405 enum JPEG 406 { 407 JPEG_JPEGLUMAYQUANTIZERMATRIX_ORR = 0, //!< No additional details 408 JPEG_JPEGCHROMACBQUANTIZERMATRIX_ORG = 1, //!< No additional details 409 JPEG_JPEGCHROMACRQUANTIZERMATRIX_ORB = 2, //!< No additional details 410 }; 411 412 //! \brief AVC 413 //! \details 414 //! For AVC QM Type: This field specifies which Quantizer Matrix is 415 //! loaded. 416 enum AVC 417 { 418 AVC_AVC4X4INTRAMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 0, //!< No additional details 419 AVC_AVC4X4INTERMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 1, //!< No additional details 420 AVC_AVC8X8INTRAMATRIX = 2, //!< No additional details 421 AVC_AVC8X8INTERMATRIX = 3, //!< No additional details 422 }; 423 424 //! \name Initializations 425 426 //! \brief Explicit member initialization function 427 MFX_FQM_STATE_CMD(); 428 429 static const size_t dwSize = 34; 430 static const size_t byteSize = 136; 431 }; 432 433 //! 434 //! \brief MFX_PIPE_MODE_SELECT 435 //! \details 436 //! Specifies which codec and hardware module is being used toencode/decode 437 //! the video data, on a per-frame basis. The MFX_PIPE_MODE_SELECT 438 //! commandspecifies which codec and hardware module is being used to 439 //! encode/decode the video data,on a per-frame basis. It also configures 440 //! the hardware pipeline according to the activeencoder/decoder operating 441 //! mode for encoding/decoding the current picture. Commandsissued 442 //! specifically for AVC and MPEG2 are ignored when VC1 is the activecodec. 443 //! 444 struct MFX_PIPE_MODE_SELECT_CMD 445 { 446 union 447 { 448 struct 449 { 450 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 451 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 452 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 453 uint32_t Subopa : __CODEGEN_BITFIELD(21, 23); //!< SUBOPA 454 uint32_t Opcode : __CODEGEN_BITFIELD(24, 26); //!< OPCODE 455 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 456 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 457 }; 458 uint32_t Value; 459 } DW0; 460 union 461 { 462 struct 463 { 464 uint32_t StandardSelect : __CODEGEN_BITFIELD(0, 3); //!< STANDARD_SELECT 465 uint32_t CodecSelect : __CODEGEN_BITFIELD(4, 4); //!< CODEC_SELECT 466 uint32_t StitchMode : __CODEGEN_BITFIELD(5, 5); //!< STITCH_MODE 467 uint32_t FrameStatisticsStreamoutEnable : __CODEGEN_BITFIELD(6, 6); //!< FRAME_STATISTICS_STREAMOUT_ENABLE 468 uint32_t ScaledSurfaceEnable : __CODEGEN_BITFIELD(7, 7); //!< SCALED_SURFACE_ENABLE 469 uint32_t PreDeblockingOutputEnablePredeblockoutenable : __CODEGEN_BITFIELD(8, 8); //!< PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE 470 uint32_t PostDeblockingOutputEnablePostdeblockoutenable : __CODEGEN_BITFIELD(9, 9); //!< POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE 471 uint32_t StreamOutEnable : __CODEGEN_BITFIELD(10, 10); //!< STREAM_OUT_ENABLE 472 uint32_t PicErrorStatusReportEnable : __CODEGEN_BITFIELD(11, 11); //!< PIC_ERRORSTATUS_REPORT_ENABLE 473 uint32_t DeblockerStreamOutEnable : __CODEGEN_BITFIELD(12, 12); //!< DEBLOCKER_STREAM_OUT_ENABLE 474 uint32_t VdencMode : __CODEGEN_BITFIELD(13, 13); //!< VDENC_MODE 475 uint32_t StandaloneVdencModeEnable : __CODEGEN_BITFIELD(14, 14); //!< STANDALONE_VDENC_MODE_ENABLE 476 uint32_t DecoderModeSelect : __CODEGEN_BITFIELD(15, 16); //!< DECODER_MODE_SELECT 477 uint32_t DecoderShortFormatMode : __CODEGEN_BITFIELD(17, 17); //!< DECODER_SHORT_FORMAT_MODE 478 uint32_t ExtendedStreamOutEnable : __CODEGEN_BITFIELD(18, 18); //!< Extended stream out enable 479 uint32_t Reserved51 : __CODEGEN_BITFIELD(19, 23); //!< Reserved 480 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 481 }; 482 uint32_t Value; 483 } DW1; 484 union 485 { 486 struct 487 { 488 uint32_t PerformanceCounterEnableVmxVmcVadVdsBsp : __CODEGEN_BITFIELD(0, 0); //!< PERFORMANCE_COUNTER_ENABLE_VMX_VMC_VAD_VDS_BSP 489 uint32_t VmxRowStoreCounterOutputSelect : __CODEGEN_BITFIELD(1, 2); //!< VMX_ROW_STORE_COUNTER_OUTPUT_SELECT 490 uint32_t VdsIldbCalculation : __CODEGEN_BITFIELD(3, 3); //!< VDS_ILDB_CALCULATION 491 uint32_t Reserved68 : __CODEGEN_BITFIELD(4, 4); //!< Reserved 492 uint32_t Reserved69 : __CODEGEN_BITFIELD(5, 5); //!< Reserved 493 uint32_t ClockGateEnableAtSliceLevel : __CODEGEN_BITFIELD(6, 6); //!< CLOCK_GATE_ENABLE_AT_SLICE_LEVEL 494 uint32_t Reserved71 : __CODEGEN_BITFIELD(7, 7); //!< Reserved 495 uint32_t VmxDummyFetchControl : __CODEGEN_BITFIELD(8, 8); //!< VMX_DUMMY_FETCH_CONTROL 496 uint32_t Reserved73 : __CODEGEN_BITFIELD(9, 9); //!< Reserved 497 uint32_t MpcPref08X8DisableFlagDefault0 : __CODEGEN_BITFIELD(10, 10); //!< MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0 498 uint32_t VinClockGatingCmclkDisable : __CODEGEN_BITFIELD(11, 11); //!< VIN_CLOCK_GATING_CMCLK_DISABLE_ 499 uint32_t VlfMbaffOsStorageForSvcDisable : __CODEGEN_BITFIELD(12, 12); //!< VLF_MBAFF_OS_STORAGE_FOR_SVC_DISABLE_ 500 uint32_t Reserved77 : __CODEGEN_BITFIELD(13, 13); //!< Reserved 501 uint32_t Vlf720IOddHeightInVc1Mode : __CODEGEN_BITFIELD(14, 14); //!< VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ 502 uint32_t VinClockGatingCuclkDisable : __CODEGEN_BITFIELD(15, 15); //!< VIN_CLOCK_GATING_CUCLK_DISABLE 503 uint32_t VinSliceStartGenerationForItMode : __CODEGEN_BITFIELD(16, 16); //!< VIN_SLICE_START_GENERATION_FOR_IT_MODE 504 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 17); //!< Reserved 505 uint32_t Reserved82 : __CODEGEN_BITFIELD(18, 20); //!< Reserved 506 uint32_t Reserved85 : __CODEGEN_BITFIELD(21, 22); //!< Reserved 507 uint32_t VhrReferenceListGenerationAdjustmentUsingCurrentPocForBFrame : __CODEGEN_BITFIELD(23, 23); //!< VHR_REFERENCE_LIST_GENERATION_ADJUSTMENT_USING_CURRENT_POC_FOR_B_FRAME 508 uint32_t Reserved88 : __CODEGEN_BITFIELD(24, 24); //!< Reserved 509 uint32_t VamErrorHandlingForReferenceIndexInSvcAvcDisable : __CODEGEN_BITFIELD(25, 25); //!< VAM_ERROR_HANDLING_FOR_REFERENCE_INDEX_IN_SVCAVC_DISABLE 510 uint32_t VadSvcDecodeErrorHandlingDisable : __CODEGEN_BITFIELD(26, 26); //!< VAD_SVC_DECODE_ERROR_HANDLING_DISABLE 511 uint32_t VmbSvcTlbDummyFetchDisableForPerformance : __CODEGEN_BITFIELD(27, 27); //!< VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE 512 uint32_t VmbSvcMvReplicationFor8X8EnableErrorHandling : __CODEGEN_BITFIELD(28, 28); //!< VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING 513 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 29); //!< Reserved 514 uint32_t VdsSvcSvcBlktypeEquationAdjustment : __CODEGEN_BITFIELD(30, 30); //!< VDS_SVC_SVC_BLKTYPE_EQUATION_ADJUSTMENT 515 uint32_t Reserved95 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 516 }; 517 uint32_t Value; 518 } DW2; 519 union 520 { 521 struct 522 { 523 uint32_t PicStatusErrorReportId; //!< PIC_STATUSERROR_REPORT_ID 524 }; 525 uint32_t Value; 526 } DW3; 527 union 528 { 529 struct 530 { 531 uint32_t Reserved128; //!< Reserved 532 }; 533 uint32_t Value; 534 } DW4; 535 536 //! \name Local enumerations 537 538 enum SUBOPB 539 { 540 SUBOPB_MFXPIPEMODESELECT = 0, //!< No additional details 541 }; 542 543 enum SUBOPA 544 { 545 SUBOPA_UNNAMED0 = 0, //!< No additional details 546 }; 547 548 enum OPCODE 549 { 550 OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 551 }; 552 553 enum PIPELINE 554 { 555 PIPELINE_MFXCOMMON = 2, //!< No additional details 556 }; 557 558 enum COMMAND_TYPE 559 { 560 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 561 }; 562 563 enum STANDARD_SELECT 564 { 565 STANDARD_SELECT_MPEG2 = 0, //!< No additional details 566 STANDARD_SELECT_VC1 = 1, //!< No additional details 567 STANDARD_SELECT_AVC = 2, //!< Covers both AVC and MVC 568 STANDARD_SELECT_JPEG = 3, //!< No additional details 569 STANDARD_SELECT_SVC = 4, //!< No additional details 570 STANDARD_SELECT_VP8 = 5, //!< Decoder starting from BDW, Encoder starting from CHV 571 STANDARD_SELECT_UVLD = 15, //!< SW decoder w/ embedded micro-controller and co-processor 572 }; 573 574 enum CODEC_SELECT 575 { 576 CODEC_SELECT_DECODE = 0, //!< No additional details 577 CODEC_SELECT_ENCODE = 1, //!< Valid only if StandardSel is AVC, MPEG2 and SVC) 578 }; 579 580 enum STITCH_MODE 581 { 582 STITCH_MODE_NOTINSTITCHMODE = 0, //!< No additional details 583 STITCH_MODE_INTHESPECIALSTITCHMODE = 1, //!< This mode can be used for any Codec as long as bitfield conditions are met. 584 }; 585 586 //! \brief FRAME_STATISTICS_STREAMOUT_ENABLE 587 //! \details 588 //! This field controls the frame level statistics streamout from the PAK. 589 //! Note: This field needs to be always "Enabled" in VD_Enc mode. 590 //! In case of non-VDEnc mode,this can be used to control the frame 591 //! statistics output from the PAK. 592 enum FRAME_STATISTICS_STREAMOUT_ENABLE 593 { 594 FRAME_STATISTICS_STREAMOUT_ENABLE_DISABLE = 0, //!< No additional details 595 FRAME_STATISTICS_STREAMOUT_ENABLE_ENABLE = 1, //!< No additional details 596 }; 597 598 //! \brief SCALED_SURFACE_ENABLE 599 //! \details 600 //! This field indicates if the scaled surface is enabled. This fieldenables 601 //! the 4x HME downscalar of the reconstructed image. Only supported for AVC 602 //! and VP8 formats. 603 enum SCALED_SURFACE_ENABLE 604 { 605 SCALED_SURFACE_ENABLE_DISABLE = 0, //!< No additional details 606 SCALED_SURFACE_ENABLE_ENABLE = 1, //!< No additional details 607 }; 608 609 //! \brief PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE 610 //! \details 611 //! This field controls the output write for the reconstructed pixels BEFORE 612 //! the deblocking filter. 613 enum PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE 614 { 615 PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE_DISABLE = 0, //!< No additional details 616 PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE_ENABLE = 1, //!< No additional details 617 }; 618 619 //! \brief POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE 620 //! \details 621 //! This field controls the output write for the reconstructed pixels AFTER 622 //! the deblocking filter.In MPEG2 decoding mode, if this is enabled, VC1 623 //! deblocking filter is used. 624 enum POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE 625 { 626 POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE_DISABLE = 0, //!< No additional details 627 POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE_ENABLE = 1, //!< No additional details 628 }; 629 630 //! \brief STREAM_OUT_ENABLE 631 //! \details 632 //! This field controls whether the macroblock parameter stream-out is 633 //! enabled during VLD decoding for transcoding purpose. 634 enum STREAM_OUT_ENABLE 635 { 636 STREAM_OUT_ENABLE_DISABLE = 0, //!< No additional details 637 STREAM_OUT_ENABLE_ENABLE = 1, //!< No additional details 638 }; 639 640 //! \brief PIC_ERRORSTATUS_REPORT_ENABLE 641 //! \details 642 //! This field control whether the error/status reporting is enable or 643 //! not.0: Disable1: EnableIn decoder modes: Error reporting is written out 644 //! once per frame. The Error Report frame ID listed in DW3 along with the 645 //! VLD/IT error status bits are packed into one cache and written to the 646 //! "Decoded Picture Error/Status Buffer address" listed in the 647 //! MFX_PIPE_BUF_ADDR_STATE Command. Note: driver shall program different 648 //! error buffer addresses between pictrues; otherwise, hardware might 649 //! overwrite previous written data if driver does not read it fast 650 //! enough.In encoder modes: Not used Please refer to "Media 651 //! VDBOX -> Video Codec -> Other Codec Functions -> MFX Error 652 //! Handling -> Decoder" session for the output format. 653 enum PIC_ERRORSTATUS_REPORT_ENABLE 654 { 655 PIC_ERRORSTATUS_REPORT_ENABLE_DISABLE = 0, //!< No additional details 656 PIC_ERRORSTATUS_REPORT_ENABLE_ENABLE = 1, //!< No additional details 657 }; 658 659 //! \brief DEBLOCKER_STREAM_OUT_ENABLE 660 //! \details 661 //! This field indicates if Deblocker information is going to be streamout 662 //! during VLD decoding.For AVC, it is needed to enable the deblocker 663 //! streamout as the AVC Disable_DLKFilterIdc is a slice level parameters. 664 //! Driver needs to determine ahead of time if at least one slice of the 665 //! current frame/ has deblocker ON. For SVC, there are two deblocking 666 //! control streamout buffers (specified in MFX_BUF_ADDR State Command). 667 //! This field is still associated with the slice level SVC 668 //! Disable.DLK_Filter_Idc. 669 enum DEBLOCKER_STREAM_OUT_ENABLE 670 { 671 DEBLOCKER_STREAM_OUT_ENABLE_DISABLE = 0, //!< Disable streamout of deblocking control information for standalone deblocker operation.It needs other fields to determine one or two SVC deblocking surface streamout (Post Deblocking Output Enable, Pre Deblocking Output Enable, interlayer idc and regular deblock idc). 672 DEBLOCKER_STREAM_OUT_ENABLE_ENABLE = 1, //!< No additional details 673 }; 674 675 //! \brief VDENC_MODE 676 //! \details 677 //! This field indicates if PAK is working in legacy MBEnc mode or the VDEnc 678 //! mode. 679 enum VDENC_MODE 680 { 681 VDENC_MODE_MBENCMODE = 0, //!< PAK is working in legacy mode 682 VDENC_MODE_VDENCMODE = 1, //!< PAK is working in VDEnc mode 683 }; 684 685 //! \brief STANDALONE_VDENC_MODE_ENABLE 686 //! \details 687 //! This field indicates to PAK if this is standalone VDEnc mode. This is 688 //! primarily a validation mode. 689 enum STANDALONE_VDENC_MODE_ENABLE 690 { 691 STANDALONE_VDENC_MODE_ENABLE_VDENCPAK = 0, //!< No additional details 692 STANDALONE_VDENC_MODE_ENABLE_PAKONLY = 1, //!< No additional details 693 }; 694 695 //! \brief DECODER_MODE_SELECT 696 //! \details 697 //! Each coding standard supports two entry points: VLD entry point and IT 698 //! (IDCT) entry point. This field selects which one is in use.This field is 699 //! only valid if Codec Select is 0 (decoder). 700 enum DECODER_MODE_SELECT 701 { 702 DECODER_MODE_SELECT_VLDMODE = 0, //!< All codec minimum must support this mode 703 DECODER_MODE_SELECT_ITMODE = 1, //!< Configure the MFD Engine for IT ModeNote: Only VC1 and MPEG2 support this mode 704 DECODER_MODE_SELECT_DEBLOCKERMODE = 2, //!< Configure the MFD Engine for Standalone Deblocker Mode. Require streamout AVC edge control information from preceeding decoding pass.Note: [HSW, EXCLUDE(HSW:GT3:A, HSW:GT3:B, HSW:GT2:B)] Only AVC, MPEG2 and SVC are supported. 705 DECODER_MODE_SELECT_INTERLAYERMODE = 3, //!< Configure the MFX Engine for standalone SVC interlayer upsampling for motion info, residual and reconstructed pixel. Require information being streamout from the preceding encoding and decoding pass of a reference layer.> 706 }; 707 708 //! \brief DECODER_SHORT_FORMAT_MODE 709 //! \details 710 //! For IT mode, this bit must be 0. 711 enum DECODER_SHORT_FORMAT_MODE 712 { 713 DECODER_SHORT_FORMAT_MODE_SHORTFORMATDRIVERINTERFACE = 0, //!< AVC/VC1/MVC/SVC/VP8 Short Format Mode is in use Note: There is no Short Format for SVC and VP8 yet, so this field must be set to 1 for SVC and VP8. 714 DECODER_SHORT_FORMAT_MODE_LONGFORMATDRIVERINTERFACE = 1, //!< AVC/VC1/MVC/SVC/VP8 Long Format Mode is in use. 715 }; 716 717 //! \brief PERFORMANCE_COUNTER_ENABLE_VMX_VMC_VAD_VDS_BSP 718 //! \details 719 //! This bit enables all performance counters in MFX hardware. 720 enum PERFORMANCE_COUNTER_ENABLE_VMX_VMC_VAD_VDS_BSP 721 { 722 PERFORMANCE_COUNTER_ENABLE_VMX_VMC_VAD_VDS_BSP_DISABLE = 0, //!< No additional details 723 PERFORMANCE_COUNTER_ENABLE_VMX_VMC_VAD_VDS_BSP_ENABLE = 1, //!< No additional details 724 }; 725 726 //! \brief VMX_ROW_STORE_COUNTER_OUTPUT_SELECT 727 //! \details 728 //! This indicates which rowstore counter is going to be visable. 729 enum VMX_ROW_STORE_COUNTER_OUTPUT_SELECT 730 { 731 VMX_ROW_STORE_COUNTER_OUTPUT_SELECT_UNNAMED0 = 0, //!< Default Set of Counters 732 VMX_ROW_STORE_COUNTER_OUTPUT_SELECT_UNNAMED1 = 1, //!< Counter Set #1 733 VMX_ROW_STORE_COUNTER_OUTPUT_SELECT_UNNAMED2 = 2, //!< Counter Set #2 734 VMX_ROW_STORE_COUNTER_OUTPUT_SELECT_UNNAMED3 = 3, //!< Counter Set #3 735 }; 736 737 //! \brief VDS_ILDB_CALCULATION 738 //! \details 739 //! This bit forces all MB into INTRA MBs before doing ILDB control 740 //! generation in VDS. 741 enum VDS_ILDB_CALCULATION 742 { 743 VDS_ILDB_CALCULATION_DISABLE = 0, //!< Use original definition for ILDB calculation. 744 VDS_ILDB_CALCULATION_ENABLE = 1, //!< Force neighbor Intra MB = 1 on ILDB BS calculation. 745 }; 746 747 //! \brief CLOCK_GATE_ENABLE_AT_SLICE_LEVEL 748 //! \details 749 //! BitFieldDesc: 750 enum CLOCK_GATE_ENABLE_AT_SLICE_LEVEL 751 { 752 CLOCK_GATE_ENABLE_AT_SLICE_LEVEL_DISABLE = 0, //!< Disable Slice-level Clock gating, Unit-level Clock gating will apply 753 CLOCK_GATE_ENABLE_AT_SLICE_LEVEL_ENABLE = 1, //!< Enable Slice-level Clock gating, overrides any Unit level Clock gating 754 }; 755 756 //! \brief VMX_DUMMY_FETCH_CONTROL 757 //! \details 758 //! This control if VMX is going to accept the dummy fetch. 759 enum VMX_DUMMY_FETCH_CONTROL 760 { 761 VMX_DUMMY_FETCH_CONTROL_ENABLE = 0, //!< Allow SVC Dummy Fetch to go to GAC (Better Performance) 762 VMX_DUMMY_FETCH_CONTROL_DISABLE = 1, //!< Drops SVC Dummy Fetch (It matches back the original design) 763 }; 764 765 enum MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0 766 { 767 MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0_DISABLE = 0, //!< No additional details 768 MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0_ENABLE = 1, //!< No additional details 769 }; 770 771 //! \brief VIN_CLOCK_GATING_CMCLK_DISABLE_ 772 //! \details 773 //! This bit disable cmclk clock gate for VIN. 774 enum VIN_CLOCK_GATING_CMCLK_DISABLE_ 775 { 776 VIN_CLOCK_GATING_CMCLK_DISABLE_DISABLE = 0, //!< No additional details 777 VIN_CLOCK_GATING_CMCLK_DISABLE_ENABLE = 1, //!< Disable gcmclkvin 778 }; 779 780 //! \brief VLF_MBAFF_OS_STORAGE_FOR_SVC_DISABLE_ 781 //! \details 782 //! This bit disables MBAFF storage for SVC use in VLF. 783 enum VLF_MBAFF_OS_STORAGE_FOR_SVC_DISABLE_ 784 { 785 VLF_MBAFF_OS_STORAGE_FOR_SVC_DISABLE_ENABLE = 0, //!< Enable MBAFF OS storage of storing VOP data for SVC 786 VLF_MBAFF_OS_STORAGE_FOR_SVC_DISABLE_DISABLE = 1, //!< Disable MBAFF OS storage of storign VOP data for SVC 787 }; 788 789 //! \brief VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ 790 //! \details 791 //! This bit indicates VLF write out VC1 picture with odd height (in MBs). 792 enum VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ 793 { 794 VLF_720I_ODD_HEIGHT_IN_VC1_MODE_DISABLE = 0, //!< No additional details 795 VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ENABLE = 1, //!< 720i Enable 796 }; 797 798 //! \brief VIN_CLOCK_GATING_CUCLK_DISABLE 799 //! \details 800 //! This bit disables gcuclk for VIN. 801 enum VIN_CLOCK_GATING_CUCLK_DISABLE 802 { 803 VIN_CLOCK_GATING_CUCLK_DISABLE_DISABLE = 0, //!< No additional details 804 VIN_CLOCK_GATING_CUCLK_DISABLE_ENABLE = 1, //!< Disbales gcuclkvin 805 }; 806 807 //! \brief VIN_SLICE_START_GENERATION_FOR_IT_MODE 808 //! \details 809 //! This bit changes the behavior how VIN generates slice start in IT mode. 810 enum VIN_SLICE_START_GENERATION_FOR_IT_MODE 811 { 812 VIN_SLICE_START_GENERATION_FOR_IT_MODE_FRAME = 0, //!< 1 slice start per frame only 813 VIN_SLICE_START_GENERATION_FOR_IT_MODE_OBJECT = 1, //!< 1 slice start per object (multiple objects per frame) 814 }; 815 816 //! \brief VHR_REFERENCE_LIST_GENERATION_ADJUSTMENT_USING_CURRENT_POC_FOR_B_FRAME 817 //! \details 818 //! This bit is added to handle the discrepancy between spec and reference 819 //! decoder. 820 enum VHR_REFERENCE_LIST_GENERATION_ADJUSTMENT_USING_CURRENT_POC_FOR_B_FRAME 821 { 822 VHR_REFERENCE_LIST_GENERATION_ADJUSTMENT_USING_CURRENT_POC_FOR_B_FRAME_UNNAMED0 = 0, //!< Use " less than or equal to" on POC for B Frame Generation.(Reference Entry POC) =< (Current POC) (during reference list generation) 823 VHR_REFERENCE_LIST_GENERATION_ADJUSTMENT_USING_CURRENT_POC_FOR_B_FRAME_UNNAMED1 = 1, //!< Use "=" on POC for B Frame Generation(Reference Entry POC) = (Current POC) (during reference list generation) 824 }; 825 826 //! \brief VAM_ERROR_HANDLING_FOR_REFERENCE_INDEX_IN_SVCAVC_DISABLE 827 //! \details 828 //! This bit disables Error Handling Logic for Reference Index in SVC/AVC 829 //! mode. 830 enum VAM_ERROR_HANDLING_FOR_REFERENCE_INDEX_IN_SVCAVC_DISABLE 831 { 832 VAM_ERROR_HANDLING_FOR_REFERENCE_INDEX_IN_SVCAVC_DISABLE_ENABLE = 0, //!< Enable VAM Error Handling Logic for Reference Index in SVC/AVC mode 833 VAM_ERROR_HANDLING_FOR_REFERENCE_INDEX_IN_SVCAVC_DISABLE_DISABLE = 1, //!< Disable VAM Error Handling Logic for Reference Index in SVC/AVC mode 834 }; 835 836 //! \brief VAD_SVC_DECODE_ERROR_HANDLING_DISABLE 837 //! \details 838 //! This bit disables SVC Decode Error Handling Logic for MBTYPE, 839 //! Tcoeff/TrailingOnes and Trans8x8Flag. 840 enum VAD_SVC_DECODE_ERROR_HANDLING_DISABLE 841 { 842 VAD_SVC_DECODE_ERROR_HANDLING_DISABLE_ENABLE = 0, //!< Enable SVC Decode Error Handling 843 VAD_SVC_DECODE_ERROR_HANDLING_DISABLE_DISABLE = 1, //!< Disable SVC Decode Error Handling 844 }; 845 846 //! \brief VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE 847 //! \details 848 //! This bit disables TLB dummy fetch in SVC mode in VMB. 849 enum VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE 850 { 851 VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE_ENABLE = 0, //!< Enable VMB TLB Dummy Fetch for Performance 852 VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE_DISABLE = 1, //!< Disable VMB TLB Dummy Fetch 853 }; 854 855 //! \brief VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING 856 //! \details 857 //! This bit enables Motion Vector replication on 8x8 level during SVC mode 858 //! for error handling. 859 enum VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING 860 { 861 VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING_DISABLE = 0, //!< Disable MV 8x8 replication in SVC mode 862 VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING_ENABLE = 1, //!< Enable MV 8x8 Replication in SVC Mode 863 }; 864 865 //! \brief VDS_SVC_SVC_BLKTYPE_EQUATION_ADJUSTMENT 866 //! \details 867 //! This bit adjusts the svc_blktype equation in VDS (whether to use target 868 //! layer flag to be part of equation). 869 enum VDS_SVC_SVC_BLKTYPE_EQUATION_ADJUSTMENT 870 { 871 VDS_SVC_SVC_BLKTYPE_EQUATION_ADJUSTMENT_ENABLE = 0, //!< Target Layer Flag is used for svc_blktype equation 872 VDS_SVC_SVC_BLKTYPE_EQUATION_ADJUSTMENT_DISABLE = 1, //!< Target Layer Flag not used for svc_blktype equation 873 }; 874 875 //! \brief PIC_STATUSERROR_REPORT_ID 876 //! \details 877 //! In decoder modes: Error reporting is written out once per frame. This 878 //! field along with the VLD error status bits are packed into one cache and 879 //! written to the memory location specified by "Decoded Picture 880 //! Error/Status Buffer address" listed in the MFX_PIPE_BUF_ADDR_STATE 881 //! Command. 882 enum PIC_STATUSERROR_REPORT_ID 883 { 884 PIC_STATUSERROR_REPORT_ID_32_BITUNSIGNED = 0, //!< Unique ID Number 885 }; 886 887 //! \name Initializations 888 889 //! \brief Explicit member initialization function 890 MFX_PIPE_MODE_SELECT_CMD(); 891 892 static const size_t dwSize = 5; 893 static const size_t byteSize = 20; 894 }; 895 896 //! 897 //! \brief MFX_SURFACE_STATE 898 //! \details 899 //! This command is common for all encoding/decoding modes, tospecify the 900 //! uncompressed YUV picture (i.e. destination surface) or intermediate 901 //! streamout in/out surface (e.g. coefficient/residual) (field, frame 902 //! orinterleaved frame) format for reading and writing: 903 //! Uncompressed, original input picture to be encoded 904 //! Reconstructed non-filtered/filtered display picturec(becoming reference 905 //! pictures as well for subsequent temporal inter-prediction) 906 //! Residual in SVC 907 //! Reconstructed Intra pixel in SVC 908 //! CoeffPred in SVC 909 //! 910 //! Since there is only one media surface state being active during the 911 //! entire encoding/decodingprocess, all the uncompressed/reconstructed 912 //! pictures are defined to have the samesurface state. For each media 913 //! object call (decoding or encoding), multiple SVC surfaces can be active 914 //! concurrently, to distinguish among them, a surfaceID is added to specify 915 //! for each type of surface. The primary difference among picture surface 916 //! states is their individual programmed base addresses, which are provided 917 //! by other state commands and not included in this command. MFX engine is 918 //! making the association of surface states and corresponding buffer base 919 //! addresses. 920 //! MFX engine currently supports only one media surface type for video 921 //! andthat is the NV12 (Planar YUV420 with interleaved U (Cb) and V (Cr). 922 //! For optimizingmemory efficiency based on access patterns, only TileY is 923 //! supported. For JPEG decoder,only IMC1 and IMC3 are supported. Pitch can 924 //! be wider than the Picture Width in pixelsand garbage will be there at 925 //! the end of each line. The following describes all thedifferent formats 926 //! that are supported and not supported in Gen7 MFX : 927 //! NV12 - 4:2:0 only;UV interleaved; Full Pitch, U and V offset is set to 928 //! 0 (the only format supported forvideo codec); vertical UV offset is MB 929 //! aligned; UV xoffsets = 0. JPEG does not supportNV12 format because 930 //! non-interleave JPEG has performance issue with partial write 931 //! (ininterleaved UV format) 932 //! IMC 1 & 3 - Full Pitch, U and V are separate plane; (JPEGonly; U 933 //! plane + garbage first in full pitch followed by V plane + garbage in 934 //! fullpitch). U and V vertical offsets are block aligned; U and V xoffset 935 //! = 0; there is no gapbetween Y, U and V planes. IMC1 and IMC3 are 936 //! different by a swap of U and V. This is theonly format supported in JPEG 937 //! for all video subsampling types (4:4:4, 4:2:2 and 4:2:0) 938 //! We are not supporting IMC 2 & 4 - Full Pitch, U and V are separate 939 //! plane (JPEG only; Uplane first in full pitch followed by V plane in full 940 //! pitch - U and V plane areside-by-side). U and V vertical offsets are 941 //! 16-pixel aligned; V xoffset is half-pitchaligned; U xoffset is 0; there 942 //! is no gap between Y, U and V planes. IMC2 and IMC4 aredifferent by a 943 //! swap of U and V. 944 //! We are not supporting YV12 - half pitch for each U and Vplane, and 945 //! separate planes for Y, U and V (U plane first in half pitch followed by 946 //! Vplane in half pitch). For YV12, U and V vertical offsets are block 947 //! aligned; U and Vxoffset = 0; there is no gap between Y, U and V planes 948 //! 949 //! Note that the following datastructures are not specified through the 950 //! media surface state 951 //! 1D buffers for row-store and other miscellaneous information. 952 //! 2D buffers for per-MB data-structures (e.g. DMV biffer, MB info record, 953 //! ILDB Control and Tcoeff/Stocoeff). 954 //! 955 //! This surface state here is identical to the Surface State for 956 //! deinterlace and sample_8x8messages described in the Shared Function 957 //! Volume and Sampler Chapter. 958 //! For non pixel data,such as row stores, indirect data (Compressed Slice 959 //! Data, AVC MV record, Coeff recordand AVC ILDB record) and streamin/out 960 //! and output compressed bitstream, a linear buffer isemployed. For row 961 //! stores, the H/W is designed to guarantee legal memory accesses (readand 962 //! write). For the remaining cases, indirect object base address, indirect 963 //! objectaddress upper bound, object data start address (offset) and object 964 //! data length are usedto fully specified their corresponding buffer. This 965 //! mechanism is chosen over the pixelsurface type because of their variable 966 //! record sizes. 967 //! All row store surfaces are linear surface.Their addresses are 968 //! programmed in Pipe_Buf_Base_State orBsp_Buf_Base_Addr_State 969 //! 970 //! VC1 I picture scaling: Even though VC1 allows I reconstructed picture 971 //! scaling (via RESPIC), as such scaling is only allowed at I picture. All 972 //! subsequent P (and B) pictures must have the same picture dimensions with 973 //! the preceding I picture. Therefore, all reference pictures for P or B 974 //! picture can share the same surface state with the current P and B 975 //! picture. Note : H/W is not processing RESPIC. Application is no longer 976 //! expecting intel decoder pipelineand kernel to perform this function, it 977 //! is going to be done in the video post-processing scaler or display 978 //! controller scale as a separate step and controller. 979 //! 980 //! All video codec surfaces must be NV12 Compliant, except JPEG. U/V 981 //! vertical must be MB aligned for all video codec (further contrained for 982 //! field picture), but JPEG can be block aligned. All video codec and JPEG 983 //! uses Tiled - Y format only, for uncompressed pixel surfaces. 984 //! 985 //! Even for JPEG planar 420 surface, application may provide only 1 986 //! buffers, but there is still only one single surface state for all of 987 //! them. If IMC equal to 1, 2, 3 or 4, U and V have the pitch same as Y. 988 //! And U and V will have different offset, each offset is block aligned. 989 //! 990 struct MFX_SURFACE_STATE_CMD 991 { 992 union 993 { 994 struct 995 { 996 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 997 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 998 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPB 999 uint32_t Subopa : __CODEGEN_BITFIELD(21, 23); //!< SUBOPA 1000 uint32_t Opcode : __CODEGEN_BITFIELD(24, 26); //!< OPCODE 1001 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 1002 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 1003 }; 1004 uint32_t Value; 1005 } DW0; 1006 union 1007 { 1008 struct 1009 { 1010 uint32_t SurfaceId : __CODEGEN_BITFIELD(0, 3); //!< SURFACE_ID 1011 uint32_t Reserved36 : __CODEGEN_BITFIELD(4, 31); //!< Reserved 1012 }; 1013 uint32_t Value; 1014 } DW1; 1015 union 1016 { 1017 struct 1018 { 1019 uint32_t CrVCbUPixelOffsetVDirection : __CODEGEN_BITFIELD(0, 1); //!< Cr(V)/Cb(U) Pixel Offset V Direction 1020 uint32_t Reserved66 : __CODEGEN_BITFIELD(2, 3); //!< Reserved 1021 uint32_t Width : __CODEGEN_BITFIELD(4, 17); //!< Width 1022 uint32_t Height : __CODEGEN_BITFIELD(18, 31); //!< Height 1023 }; 1024 uint32_t Value; 1025 } DW2; 1026 union 1027 { 1028 struct 1029 { 1030 uint32_t Tilemode : __CODEGEN_BITFIELD(0, 1); //!< TILEMODE 1031 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD(2, 2); //!< Half Pitch for Chroma 1032 uint32_t SurfacePitch : __CODEGEN_BITFIELD(3, 19); //!< Surface Pitch 1033 uint32_t Reserved116 : __CODEGEN_BITFIELD(20, 21); //!< Reserved21_20 1034 uint32_t CompressionFormat : __CODEGEN_BITFIELD(22, 25); //!< COMPRESSION_FORMAT 1035 uint32_t Reserved122 : __CODEGEN_BITFIELD(26, 26); //!< Reserved 1036 uint32_t InterleaveChroma : __CODEGEN_BITFIELD(27, 27); //!< INTERLEAVE_CHROMA_ 1037 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(28, 31); //!< SURFACE_FORMAT 1038 }; 1039 uint32_t Value; 1040 } DW3; 1041 union 1042 { 1043 struct 1044 { 1045 uint32_t YOffsetForUCb : __CODEGEN_BITFIELD(0, 14); //!< Y Offset for U(Cb) 1046 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 1047 uint32_t XOffsetForUCb : __CODEGEN_BITFIELD(16, 30); //!< X Offset for U(Cb) 1048 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 1049 }; 1050 uint32_t Value; 1051 } DW4; 1052 union 1053 { 1054 struct 1055 { 1056 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD(0, 15); //!< Y Offset for V(Cr) 1057 uint32_t XOffsetForVCr : __CODEGEN_BITFIELD(16, 28); //!< X Offset for V(Cr) 1058 uint32_t Reserved189 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 1059 }; 1060 uint32_t Value; 1061 } DW5; 1062 1063 //! \name Local enumerations 1064 1065 enum SUBOPB 1066 { 1067 SUBOPB_UNNAMED1 = 1, //!< No additional details 1068 }; 1069 1070 enum SUBOPA 1071 { 1072 SUBOPA_UNNAMED0 = 0, //!< No additional details 1073 }; 1074 1075 enum OPCODE 1076 { 1077 OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 1078 }; 1079 1080 enum PIPELINE 1081 { 1082 PIPELINE_MFXCOMMON = 2, //!< No additional details 1083 }; 1084 1085 enum COMMAND_TYPE 1086 { 1087 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1088 }; 1089 1090 enum SURFACE_ID 1091 { 1092 SURFACE_ID_DECODEDPICTUREANDREFERENCEPICTURES_SVCUPSAMPLINGSTREAMOUTRECONSTRUCTEDPIXELSCOEFFPRED_UPPERLAYERSIZE = 0, //!< 8-bit uncompressed data 1093 SURFACE_ID_SVCRESIDUALUPSAMPLINGSTREAMOUTSURFACE_UPPERLAYERSIZE = 1, //!< 16-bit uncompressed data 1094 SURFACE_ID_SVCRECONSTRUCTEDPIXELANDCOEFFPREDUPSAMPLINGSTREAMINSURFACE_LOWERLAYERSIZE = 2, //!< 8-bit uncompressed data. 1095 SURFACE_ID_SVCRESIDUALUPSAMPLINGSTREAMINSURFACE_LOWERLAYERSIZE = 3, //!< 16-bit uncompressed data 1096 SURFACE_ID_SOURCEINPUTPICTURE_ENCODER = 4, //!< 8-bit uncompressed data 1097 SURFACE_ID_RECONSTRUCTEDSCALEDREFERENCEPICTURE = 5, //!< 8-bit data 1098 }; 1099 1100 enum TILEMODE 1101 { 1102 TILEMODE_LINEAR = 0, //!< No additional details 1103 TILEMODE_TILEYS_64K = 1, //!< No additional details 1104 TILEMODE_TILEX = 2, //!< No additional details 1105 TILEMODE_TILEF = 3, //!< No additional details 1106 }; 1107 1108 //! \brief COMPRESSION_FORMAT 1109 //! \details 1110 //! Specifies the compression format. 1111 enum COMPRESSION_FORMAT 1112 { 1113 COMPRESSION_FORMAT_CMFR8 = 0, //!< Single 8bit channel format 1114 COMPRESSION_FORMAT_CMFR8G8 = 1, //!< Two 8bit channel format 1115 COMPRESSION_FORMAT_CMFR8G8B8A8 = 2, //!< Four 8bit channel format 1116 COMPRESSION_FORMAT_CMFR10G10B10A2 = 3, //!< Three 10bit channels and One 2bit channel 1117 COMPRESSION_FORMAT_CMFR11G11B10 = 4, //!< Two 11bit channels and One 10bit channel 1118 COMPRESSION_FORMAT_CMFR16 = 5, //!< Single 16bit channel format 1119 COMPRESSION_FORMAT_CMFR16G16 = 6, //!< Two 16bit channel format 1120 COMPRESSION_FORMAT_CMFR16G16B16A16 = 7, //!< Four 16bit channels 1121 COMPRESSION_FORMAT_CMFR32 = 8, //!< Single 32bit channel 1122 COMPRESSION_FORMAT_CMFR32G32 = 9, //!< Two 32bit channels 1123 COMPRESSION_FORMAT_CMFR32G32B32A32 = 10, //!< Four 32bit channels 1124 COMPRESSION_FORMAT_CMFY16U16Y16V16 = 11, //!< Packed YUV 16/12/10 bit per channel 1125 COMPRESSION_FORMAT_CMFML8 = 15, //!< Machine Learning format / Generic data 1126 }; 1127 1128 //! \brief INTERLEAVE_CHROMA_ 1129 //! \details 1130 //! This field indicates that the chroma fields are interleaved in a single 1131 //! plane rather than stored as two separate planes. This field is only used 1132 //! for PLANAR surface formats.For AVC/VC1/MPEG VLD and IT modes : set to 1133 //! Enable to support interleave U/V only.For JPEG : set to Disable for all 1134 //! formats (including 4:2:0) - because JPEG does not support NV12. (This 1135 //! field is needed only if JPEG will support NV12; otherwise is ignored.) 1136 enum INTERLEAVE_CHROMA_ 1137 { 1138 INTERLEAVE_CHROMA_DISABLE = 0, //!< No additional details 1139 INTERLEAVE_CHROMA_ENABLE = 1, //!< No additional details 1140 }; 1141 1142 //! \brief SURFACE_FORMAT 1143 //! \details 1144 //! Specifies the format of the surface. All of the Y and G channels will 1145 //! use table 0 and all of the Cr/Cb/R/B channels will use table 1.Usage: 1146 //! For 420 planar YUV surface, use 4; for monochrome surfaces, use 12. For 1147 //! monochrome surfaces, hardware ignores control fields for Chroma 1148 //! planes.This field must be set to 4 - PLANAR_420_8, or 12 - Y8_UNORMNot 1149 //! used for MFX, and is ignored. But for JPEG decoding, this field should 1150 //! be programmed to the same format as JPEG_PIC_STATE. For video codec, it 1151 //! should set to 4 always. 1152 enum SURFACE_FORMAT 1153 { 1154 SURFACE_FORMAT_YCRCBNORMAL = 0, //!< No additional details 1155 SURFACE_FORMAT_YCRCBSWAPUVY = 1, //!< No additional details 1156 SURFACE_FORMAT_YCRCBSWAPUV = 2, //!< No additional details 1157 SURFACE_FORMAT_YCRCBSWAPY = 3, //!< No additional details 1158 SURFACE_FORMAT_PLANAR4208 = 4, //!< (NV12, IMC1,2,3,4, YV12) 1159 SURFACE_FORMAT_PLANAR4118 = 5, //!< Deinterlace Only 1160 SURFACE_FORMAT_PLANAR4228 = 6, //!< Deinterlace Only 1161 SURFACE_FORMAT_STMMDNSTATISTICS = 7, //!< Deinterlace Only 1162 SURFACE_FORMAT_R10G10B10A2UNORM = 8, //!< Sample_8x8 Only 1163 SURFACE_FORMAT_R8G8B8A8UNORM = 9, //!< Sample_8x8 Only 1164 SURFACE_FORMAT_R8B8UNORM_CRCB = 10, //!< Sample_8x8 Only 1165 SURFACE_FORMAT_R8UNORM_CRCB = 11, //!< Sample_8x8 Only 1166 SURFACE_FORMAT_Y8UNORM = 12, //!< Sample_8x8 Only 1167 }; 1168 1169 //! \name Initializations 1170 1171 //! \brief Explicit member initialization function 1172 MFX_SURFACE_STATE_CMD(); 1173 1174 static const size_t dwSize = 6; 1175 static const size_t byteSize = 24; 1176 }; 1177 1178 //! 1179 //! \brief MFX_IND_OBJ_BASE_ADDR_STATE 1180 //! \details 1181 //! This state command provides the memory base addresses for all row 1182 //! stores, StreamOut buffer andreconstructed picture output buffers 1183 //! required by the MFD or MFC Engine (that are in addition tothe row stores 1184 //! of the Bit Stream Decoding/Encoding Unit (BSD/BSE) and the reference 1185 //! picture buffers).This is a picture level state command and is common 1186 //! among all codec standards and for both encoderand decoder operating 1187 //! modes. However, some fields may only applicable to a specific codec 1188 //! standard.All Pixel Surfaces (original, reference frame and reconstructed 1189 //! frame) in the Encoder are programmedwith the same surface state (NV12 1190 //! and TileY format), except each has its own frame buffer base address.In 1191 //! the tile format, there is no need to provide buffer offset for each 1192 //! slice; since from each MB address,the hardware can calculated the 1193 //! corresponding memory location within the frame buffer directly. 1194 //! 1195 //! OPEN ??? : ARE WE DOING PER SURFACE UPPERBOUND CHECK OR THE GLOBAL CHECK 1196 //! - YES upper bound check mustalways enabled and restricted to 2G. AR. Sam 1197 //! to confirm with Ricky and update the doc. For encoder,compressed 1198 //! bitstream WRITE, we need to use the linear surface destination buffer. 1199 //! There is no need tohave a global upper bound for linear buffer write, 1200 //! for each linear buffer, there is a size field tocontrol its valid range. 1201 //! 1202 //! The MFX_IND_OBJ_BASE_ADDR command sets the memory base address pointers 1203 //! for the correspondingIndirect Object Data Start Addresses (Offsets) 1204 //! specified in each OBJECT commands. Thecharacteristic of these indirect 1205 //! object data is their variable size (per MB or per Slice).Hence, each 1206 //! OBJECT command must specify the indirect object data offset from the 1207 //! base addressto start fetching or writing object data. 1208 //! 1209 //! It is an API requirement to support the indirection of certain 1210 //! graphics memory accesses (GTT-mapped). 1211 //! 1212 //! While the use of base address is unconditional, the indirection can be 1213 //! effectively disabled by setting thebase address to zero. For decoder, 1214 //! there are: 1 read-only per-slice indirect object in the BSD_OBJECT 1215 //! Command, and 1216 //! 2 read-only per-MB indirect objects in the IT_OBJECT Command. 1217 //! For decoder: the Video Command Streamer (VCS) will perform the memory 1218 //! access bound check automatically using the corresponding MFC Indirect 1219 //! Object Access Upper Bound specification. If any access is at or 1220 //! beyondthe upper bound, zero value is returned. The request to memory is 1221 //! still being sent, but the corresponding codec's BSD unit will detect 1222 //! this condition and perform the zeroing return. If the Upper Bound is 1223 //! turned off,the beyond bound request will return whatever on the bus 1224 //! (invalid data). For encoder, there are: 1 read-only per-MB indirect 1225 //! object in the PAK_OBJECT Command, and 1226 //! 1 write-only per-slice indirect object in the PAK Slice_State Command 1227 //! For encoder: whenever an out of bound address accessing request is 1228 //! generated, VMX will detect such requests and snap theaddress to the 1229 //! corresponding [indirect object base address + indirect data start 1230 //! address]. VMX will returnall 0s as the data to the requestor. 1231 //! NotationDefinitionPhysicalAddress[n:m] Corresponding bits of a 1232 //! physicalgraphics memory byte address (not mapped by a GTT) 1233 //! GraphicsAddress[n:m] Corresponding bits of an absolute,virtual graphics 1234 //! memory byte address (mapped by a GTT). 1235 //! 1236 struct MFX_IND_OBJ_BASE_ADDR_STATE_CMD 1237 { 1238 union 1239 { 1240 struct 1241 { 1242 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 1243 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 1244 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODEB 1245 uint32_t SubOpcodea : __CODEGEN_BITFIELD(21, 23); //!< SUB_OPCODEA 1246 uint32_t CommonOpcode : __CODEGEN_BITFIELD(24, 26); //!< COMMON_OPCODE 1247 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 1248 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 1249 }; 1250 uint32_t Value; 1251 } DW0; 1252 SPLITBASEADDRESS4KBYTEALIGNED_CMD MfxIndirectBitstreamObjectBaseAddress; //!< DW1..2, MFX Indirect Bitstream Object - Base Address 1253 MEMORYADDRESSATTRIBUTES_CMD MfxIndirectBitstreamObjectAttributes; //!< DW3, MFX Indirect Bitstream Object - Attributes 1254 SPLITBASEADDRESS4KBYTEALIGNED_CMD MfxIndirectBitstreamObjectUpperBound; //!< DW4..5, MFX Indirect Bitstream Object - Upper Bound 1255 SPLITBASEADDRESS4KBYTEALIGNED_CMD MfxIndirectMvObjectBaseAddress; //!< DW6..7, MFX Indirect MV Object - Base Address 1256 MEMORYADDRESSATTRIBUTES_CMD MfxIndirectMvObjectAttributes; //!< DW8, MFX Indirect MV Object - Attributes 1257 SPLITBASEADDRESS4KBYTEALIGNED_CMD MfxIndirectMvObjectUpperBound; //!< DW9..10, MFX Indirect MV Object - Upper Bound 1258 SPLITBASEADDRESS4KBYTEALIGNED_CMD MfdIndirectItCoeffObjectBaseAddress; //!< DW11..12, MFD Indirect IT-COEFF Object - Base Address 1259 MEMORYADDRESSATTRIBUTES_CMD MfdIndirectItCoeffObjectAttributes; //!< DW13, MFD Indirect IT-COEFF Object - Attributes 1260 SPLITBASEADDRESS4KBYTEALIGNED_CMD MfdIndirectItCoeffObjectUpperBound; //!< DW14..15, MFD Indirect IT-COEFF Object - Upper Bound 1261 SPLITBASEADDRESS4KBYTEALIGNED_CMD MfdIndirectItDblkObjectBaseAddress; //!< DW16..17, MFD Indirect IT-DBLK Object - Base Address 1262 MEMORYADDRESSATTRIBUTES_CMD MfdIndirectItDblkObjectAttributes; //!< DW18, MFD Indirect IT-DBLK Object - Attributes 1263 SPLITBASEADDRESS4KBYTEALIGNED_CMD MfdIndirectItDblkObjectUpperBound; //!< DW19..20, MFD Indirect IT-DBLK Object - Upper Bound 1264 SPLITBASEADDRESS4KBYTEALIGNED_CMD MfcIndirectPakBseObjectBaseAddress; //!< DW21..22, MFC Indirect PAK-BSE Object - Base Address 1265 MEMORYADDRESSATTRIBUTES_CMD MfcIndirectPakBseObjectAttributes; //!< DW23, MFC Indirect PAK-BSE Object - Attributes 1266 SPLITBASEADDRESS4KBYTEALIGNED_CMD MfcIndirectPakBseObjectUpperBound; //!< DW24..25, MFC Indirect PAK-BSE Object - Upper Bound 1267 1268 //! \name Local enumerations 1269 1270 enum SUBOPCODEB 1271 { 1272 SUBOPCODEB_MFXINDOBJBASEADDRSTATE = 3, //!< No additional details 1273 }; 1274 1275 enum SUB_OPCODEA 1276 { 1277 SUB_OPCODEA_MFXINDOBJBASEADDRSTATE = 0, //!< No additional details 1278 }; 1279 1280 enum COMMON_OPCODE 1281 { 1282 COMMON_OPCODE_MFXINDOBJBASEADDRSTATE = 0, //!< No additional details 1283 }; 1284 1285 enum PIPELINE 1286 { 1287 PIPELINE_MFXINDOBJBASEADDRSTATE = 2, //!< No additional details 1288 }; 1289 1290 enum COMMAND_TYPE 1291 { 1292 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1293 }; 1294 1295 //! \name Initializations 1296 1297 //! \brief Explicit member initialization function 1298 MFX_IND_OBJ_BASE_ADDR_STATE_CMD(); 1299 1300 static const size_t dwSize = 26; 1301 static const size_t byteSize = 104; 1302 }; 1303 1304 //! 1305 //! \brief MFX_BSP_BUF_BASE_ADDR_STATE 1306 //! \details 1307 //! This frame-level state command is used to specify all the buffer base 1308 //! addresses needed for the operation of the AVC Bit Stream Processing 1309 //! Units (for decoder, it is BSD Unit; for encoder, it is BSE Unit)For both 1310 //! encoder and decoder, currently it is assumed that all codec standards 1311 //! can share the same BSP_BUF_BASE_STATE. The simplicity of this command is 1312 //! the result of moving all the direct MV related processing into the ENC 1313 //! Subsystem. Since all implicit weight calculations and directMV 1314 //! calculations are done in ENC and all picture buffer management are done 1315 //! in the Host, there is no need to provide POC (POC List - 1316 //! FieldOrderCntList, CurrPic POC - CurrFieldOrderCnt) information to PAK. 1317 //! For decoder, all the direct mode information are sent in a separate 1318 //! slice-level command (AVC_DIRECTMODE_STATE command).In addition, in 1319 //! Encoder, the row stores for CABAC encoding and MB Parameters 1320 //! Construction (MPC) are combined into one single row store.The row stores 1321 //! specified in this command do not combine with those specified in the 1322 //! MFC_PIPE_BUF_ADDR_STATE command for hardware simplification reason. 1323 //! 1324 struct MFX_BSP_BUF_BASE_ADDR_STATE_CMD 1325 { 1326 union 1327 { 1328 struct 1329 { 1330 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 1331 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 1332 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 1333 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 1334 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 1335 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 1336 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 1337 }; 1338 uint32_t Value; 1339 } DW0; 1340 union 1341 { 1342 struct 1343 { 1344 uint32_t Reserved32 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 1345 uint32_t BsdMpcRowStoreScratchBufferBaseAddressReadWrite : __CODEGEN_BITFIELD(6, 31); //!< BSD/MPC Row Store Scratch Buffer Base Address - Read/Write 1346 }; 1347 uint32_t Value; 1348 } DW1; 1349 union 1350 { 1351 struct 1352 { 1353 uint32_t BsdMpcRowStoreScratchBufferBaseAddressReadWrite4732 : __CODEGEN_BITFIELD(0, 15); //!< BSD/MPC Row Store Scratch Buffer Base Address - Read/Write [47:32] 1354 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 1355 }; 1356 uint32_t Value; 1357 } DW2; 1358 union 1359 { 1360 struct 1361 { 1362 uint32_t Reserved96 : __CODEGEN_BITFIELD(0, 0); //!< Reserved 1363 uint32_t BsdMpcRowStoreScratchBufferIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD(1, 6); //!< BSD/MPC Row Store Scratch Buffer - Index to Memory Object Control State (MOCS) Tables 1364 uint32_t BsdMpcRowStoreScratchBufferArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL 1365 uint32_t Reserved105 : __CODEGEN_BITFIELD(9, 11); //!< Reserved 1366 uint32_t BsdMpcRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12); //!< BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1367 uint32_t BsdMpcRowStoreScratchBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14); //!< BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE 1368 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 31); //!< Reserved 1369 }; 1370 uint32_t Value; 1371 } DW3; 1372 union 1373 { 1374 struct 1375 { 1376 uint32_t Reserved128 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 1377 uint32_t MprRowStoreScratchBufferBaseAddressReadWriteDecoderOnly : __CODEGEN_BITFIELD(6, 31); //!< MPR Row Store Scratch Buffer Base Address - Read/Write (Decoder Only) 1378 }; 1379 uint32_t Value; 1380 } DW4; 1381 union 1382 { 1383 struct 1384 { 1385 uint32_t MprRowStoreScratchBufferBaseAddressReadWrite4732 : __CODEGEN_BITFIELD(0, 15); //!< MPR Row Store Scratch Buffer Base Address - Read/Write [47:32] 1386 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 1387 }; 1388 uint32_t Value; 1389 } DW5; 1390 union 1391 { 1392 struct 1393 { 1394 uint32_t Reserved192 : __CODEGEN_BITFIELD(0, 0); //!< Reserved 1395 uint32_t MprRowStoreScratchBufferIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD(1, 6); //!< MPR Row Store Scratch Buffer - Index to Memory Object Control State (MOCS) Tables 1396 uint32_t MprRowStoreScratchBufferArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL 1397 uint32_t Reserved201 : __CODEGEN_BITFIELD(9, 11); //!< Reserved 1398 uint32_t MprRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12); //!< MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1399 uint32_t MprRowStoreScratchBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14); //!< MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE 1400 uint32_t Reserved207 : __CODEGEN_BITFIELD(15, 31); //!< Reserved 1401 }; 1402 uint32_t Value; 1403 } DW6; 1404 union 1405 { 1406 struct 1407 { 1408 uint32_t Reserved224 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 1409 uint32_t BitplaneReadBufferBaseAddress : __CODEGEN_BITFIELD(6, 31); //!< Bitplane Read Buffer Base Address 1410 }; 1411 uint32_t Value; 1412 } DW7; 1413 union 1414 { 1415 struct 1416 { 1417 uint32_t BitplaneReadBufferBaseAddressReadWrite4732 : __CODEGEN_BITFIELD(0, 15); //!< Bitplane Read Buffer Base Address - Read/Write [47:32] 1418 uint32_t Reserved272 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 1419 }; 1420 uint32_t Value; 1421 } DW8; 1422 union 1423 { 1424 struct 1425 { 1426 uint32_t Reserved288 : __CODEGEN_BITFIELD(0, 0); //!< Reserved 1427 uint32_t BitplaneReadBufferIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD(1, 6); //!< Bitplane Read Buffer - Index to Memory Object Control State (MOCS) Tables 1428 uint32_t BitplaneReadBufferArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL 1429 uint32_t Reserved297 : __CODEGEN_BITFIELD(9, 12); //!< Reserved 1430 uint32_t BitplaneReadBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14); //!< BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE 1431 uint32_t Reserved303 : __CODEGEN_BITFIELD(15, 31); //!< Reserved 1432 }; 1433 uint32_t Value; 1434 } DW9; 1435 1436 //! \name Local enumerations 1437 1438 enum SUBOPCODE_B 1439 { 1440 SUBOPCODE_B_UNNAMED4 = 4, //!< No additional details 1441 }; 1442 1443 enum SUBOPCODE_A 1444 { 1445 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 1446 }; 1447 1448 enum MEDIA_COMMAND_OPCODE 1449 { 1450 MEDIA_COMMAND_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 1451 }; 1452 1453 enum PIPELINE 1454 { 1455 PIPELINE_PIPELINE = 2, //!< No additional details 1456 }; 1457 1458 enum COMMAND_TYPE 1459 { 1460 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1461 }; 1462 1463 //! \brief BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL 1464 //! \details 1465 //! This field controls the priority of arbitration used in the GAC/GAM 1466 //! pipeline for this surface. 1467 enum BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL 1468 { 1469 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1470 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1471 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1472 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1473 }; 1474 1475 //! \brief BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1476 //! \details 1477 //! This field controls if Intra Row Store is going to store inside Media 1478 //! Internal Storage or to LLC. 1479 enum BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1480 { 1481 BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC 1482 BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage 1483 }; 1484 1485 //! \brief BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE 1486 //! \details 1487 //! For Media Surfaces:This field specifies the tiled resource mode. 1488 enum BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE 1489 { 1490 BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1491 BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1492 BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1493 }; 1494 1495 //! \brief MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL 1496 //! \details 1497 //! This field controls the priority of arbitration used in the GAC/GAM 1498 //! pipeline for this surface. 1499 enum MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL 1500 { 1501 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1502 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1503 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1504 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1505 }; 1506 1507 //! \brief MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1508 //! \details 1509 //! This field controls if Intra Row Store is going to store inside Media 1510 //! Internal Storage or to LLC. 1511 enum MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1512 { 1513 MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC 1514 MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage 1515 }; 1516 1517 //! \brief MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE 1518 //! \details 1519 //! For Media Surfaces:This field specifies the tiled resource mode. 1520 enum MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE 1521 { 1522 MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1523 MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1524 MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1525 }; 1526 1527 //! \brief BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL 1528 //! \details 1529 //! This field controls the priority of arbitration used in the GAC/GAM 1530 //! pipeline for this surface. 1531 enum BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL 1532 { 1533 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1534 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1535 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1536 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1537 }; 1538 1539 //! \brief BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE 1540 //! \details 1541 //! For Media Surfaces:This field specifies the tiled resource mode. 1542 enum BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE 1543 { 1544 BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1545 BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1546 BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1547 }; 1548 1549 //! \name Initializations 1550 1551 //! \brief Explicit member initialization function 1552 MFX_BSP_BUF_BASE_ADDR_STATE_CMD(); 1553 1554 static const size_t dwSize = 10; 1555 static const size_t byteSize = 40; 1556 }; 1557 1558 //! 1559 //! \brief MFD_AVC_PICID_STATE 1560 //! \details 1561 //! This is a frame level state command used for both AVC Long and Short 1562 //! Format in VLD mode.PictureID[16] contains the pictureID of each 1563 //! reference picture (16 maximum) so hardware can uniquely identify the 1564 //! reference picture across frames (this will be used for DMV 1565 //! operation).This command will be needed for both short and long format. 1566 //! 1567 struct MFD_AVC_PICID_STATE_CMD 1568 { 1569 union 1570 { 1571 struct 1572 { 1573 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 1574 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 1575 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 1576 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 1577 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 1578 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 1579 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 1580 }; 1581 uint32_t Value; 1582 } DW0; 1583 union 1584 { 1585 struct 1586 { 1587 uint32_t PictureidRemappingDisable : __CODEGEN_BITFIELD(0, 0); //!< PICTUREID_REMAPPING_DISABLE 1588 uint32_t Reserved33 : __CODEGEN_BITFIELD(1, 31); //!< Reserved 1589 }; 1590 uint32_t Value; 1591 } DW1; 1592 uint32_t Pictureidlist1616Bits[8]; //!< PictureIDList[16][16 bits] 1593 1594 //! \name Local enumerations 1595 1596 enum SUBOPCODE_B 1597 { 1598 SUBOPCODE_B_MEDIA = 5, //!< No additional details 1599 }; 1600 1601 enum SUBOPCODE_A 1602 { 1603 SUBOPCODE_A_DEC = 1, //!< No additional details 1604 }; 1605 1606 enum MEDIA_COMMAND_OPCODE 1607 { 1608 MEDIA_COMMAND_OPCODE_MFDAVCDPBSTATE = 1, //!< No additional details 1609 }; 1610 1611 enum PIPELINE 1612 { 1613 PIPELINE_MFXMULTIDW = 2, //!< No additional details 1614 }; 1615 1616 enum COMMAND_TYPE 1617 { 1618 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1619 }; 1620 1621 //! \brief PICTUREID_REMAPPING_DISABLE 1622 //! \details 1623 //! If Picture ID Remapping Disable is "1", PictureIDList will not be used. 1624 enum PICTUREID_REMAPPING_DISABLE 1625 { 1626 PICTUREID_REMAPPING_DISABLE_AVCDECODERWILLUSE16BITSPICTUREIDTOHANDLEDMVANDIDENTIFYTHEREFERENCEPICTURE = 0, //!< Desc 1627 PICTUREID_REMAPPING_DISABLE_AVCDECODERWILLUSE4BITSFRAMESTOREID_INDEXTOREFFRAMELISTTOHANDLEDMVANDIDENTIFYTHEREFERENCEPICTURE_THISCAUSESDMVLOGICTOFUNCTIONTHESAMEINPROJECTIVBANDBEFORE = 1, //!< Desc 1628 }; 1629 1630 //! \name Initializations 1631 1632 //! \brief Explicit member initialization function 1633 MFD_AVC_PICID_STATE_CMD(); 1634 1635 static const size_t dwSize = 10; 1636 static const size_t byteSize = 40; 1637 }; 1638 1639 //! 1640 //! \brief MFX_AVC_IMG_STATE 1641 //! \details 1642 //! This must be the very first command to issue after the surface state, 1643 //! the pipe select and base address setting commands. This command supports 1644 //! both Long and Short VLD and IT AVC Decoding Interface. 1645 //! 1646 struct MFX_AVC_IMG_STATE_CMD 1647 { 1648 union 1649 { 1650 struct 1651 { 1652 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 1653 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 1654 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 1655 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 1656 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 1657 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 1658 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 1659 }; 1660 uint32_t Value; 1661 } DW0; 1662 union 1663 { 1664 struct 1665 { 1666 uint32_t FrameSize : __CODEGEN_BITFIELD(0, 15); //!< Frame Size 1667 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 1668 }; 1669 uint32_t Value; 1670 } DW1; 1671 union 1672 { 1673 struct 1674 { 1675 uint32_t FrameWidth : __CODEGEN_BITFIELD(0, 7); //!< Frame Width 1676 uint32_t Reserved72 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 1677 uint32_t FrameHeight : __CODEGEN_BITFIELD(16, 23); //!< Frame Height 1678 uint32_t Reserved88 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 1679 }; 1680 uint32_t Value; 1681 } DW2; 1682 union 1683 { 1684 struct 1685 { 1686 uint32_t Reserved96 : __CODEGEN_BITFIELD(0, 7); //!< Reserved 1687 uint32_t ImgstructImageStructureImgStructure10 : __CODEGEN_BITFIELD(8, 9); //!< IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10 1688 uint32_t WeightedBipredIdc : __CODEGEN_BITFIELD(10, 11); //!< WEIGHTED_BIPRED_IDC 1689 uint32_t WeightedPredFlag : __CODEGEN_BITFIELD(12, 12); //!< WEIGHTED_PRED_FLAG 1690 uint32_t RhodomainRateControlEnable : __CODEGEN_BITFIELD(13, 13); //!< RHODOMAIN_RATE_CONTROL_ENABLE 1691 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 1692 uint32_t FirstChromaQpOffset : __CODEGEN_BITFIELD(16, 20); //!< First Chroma QP Offset 1693 uint32_t VdaqmEnable : __CODEGEN_BITFIELD(21, 21); //!< VDAQM enable 1694 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 1695 uint32_t SecondChromaQpOffset : __CODEGEN_BITFIELD(24, 28); //!< Second Chroma QP Offset 1696 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 1697 }; 1698 uint32_t Value; 1699 } DW3; 1700 union 1701 { 1702 struct 1703 { 1704 uint32_t Fieldpicflag : __CODEGEN_BITFIELD(0, 0); //!< FIELDPICFLAG 1705 uint32_t Mbaffflameflag : __CODEGEN_BITFIELD(1, 1); //!< MBAFFFLAMEFLAG 1706 uint32_t Framembonlyflag : __CODEGEN_BITFIELD(2, 2); //!< FRAMEMBONLYFLAG 1707 uint32_t Transform8X8Flag : __CODEGEN_BITFIELD(3, 3); //!< TRANSFORM8X8FLAG 1708 uint32_t Direct8X8Infflag : __CODEGEN_BITFIELD(4, 4); //!< DIRECT8X8INFFLAG 1709 uint32_t Constrainedipredflag : __CODEGEN_BITFIELD(5, 5); //!< CONSTRAINEDIPREDFLAG 1710 uint32_t Imgdisposableflag : __CODEGEN_BITFIELD(6, 6); //!< IMGDISPOSABLEFLAG 1711 uint32_t Entropycodingflag : __CODEGEN_BITFIELD(7, 7); //!< ENTROPYCODINGFLAG 1712 uint32_t Mbmvformatflag : __CODEGEN_BITFIELD(8, 8); //!< MBMVFORMATFLAG 1713 uint32_t Reserved137 : __CODEGEN_BITFIELD(9, 9); //!< Reserved 1714 uint32_t Chromaformatidc : __CODEGEN_BITFIELD(10, 11); //!< CHROMAFORMATIDC 1715 uint32_t Mvunpackedflag : __CODEGEN_BITFIELD(12, 12); //!< MVUNPACKEDFLAG 1716 uint32_t Inserttestflag : __CODEGEN_BITFIELD(13, 13); //!< INSERTTESTFLAG 1717 uint32_t Loadslicepointerflag : __CODEGEN_BITFIELD(14, 14); //!< LOADSLICEPOINTERFLAG 1718 uint32_t Mbstatenabled : __CODEGEN_BITFIELD(15, 15); //!< MBSTATENABLED 1719 uint32_t Minframewsize : __CODEGEN_BITFIELD(16, 31); //!< MINFRAMEWSIZE 1720 }; 1721 uint32_t Value; 1722 } DW4; 1723 union 1724 { 1725 struct 1726 { 1727 uint32_t IntrambmaxbitflagIntrambmaxsizereportmask : __CODEGEN_BITFIELD(0, 0); //!< INTRAMBMAXBITFLAG_INTRAMBMAXSIZEREPORTMASK 1728 uint32_t IntermbmaxbitflagIntermbmaxsizereportmask : __CODEGEN_BITFIELD(1, 1); //!< INTERMBMAXBITFLAG_INTERMBMAXSIZEREPORTMASK 1729 uint32_t FrameszoverflagFramebitratemaxreportmask : __CODEGEN_BITFIELD(2, 2); //!< FRAMESZOVERFLAG_FRAMEBITRATEMAXREPORTMASK 1730 uint32_t FrameszunderflagFramebitrateminreportmask : __CODEGEN_BITFIELD(3, 3); //!< FRAMESZUNDERFLAG_FRAMEBITRATEMINREPORTMASK 1731 uint32_t Reserved164 : __CODEGEN_BITFIELD(4, 6); //!< Reserved 1732 uint32_t IntraIntermbipcmflagForceipcmcontrolmask : __CODEGEN_BITFIELD(7, 7); //!< INTRAINTERMBIPCMFLAG_FORCEIPCMCONTROLMASK 1733 uint32_t Reserved168 : __CODEGEN_BITFIELD(8, 8); //!< Reserved 1734 uint32_t MbratectrlflagMbLevelRateControlEnablingFlag : __CODEGEN_BITFIELD(9, 9); //!< MBRATECTRLFLAG_MB_LEVEL_RATE_CONTROL_ENABLING_FLAG 1735 uint32_t Minframewsizeunits : __CODEGEN_BITFIELD(10, 11); //!< MINFRAMEWSIZEUNITS 1736 uint32_t Reserved172 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 1737 uint32_t Nonfirstpassflag : __CODEGEN_BITFIELD(16, 16); //!< NONFIRSTPASSFLAG 1738 uint32_t Reserved177 : __CODEGEN_BITFIELD(17, 26); //!< Reserved 1739 uint32_t TrellisQuantizationChromaDisableTqchromadisable : __CODEGEN_BITFIELD(27, 27); //!< TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE 1740 uint32_t TrellisQuantizationRoundingTqr : __CODEGEN_BITFIELD(28, 30); //!< TRELLIS_QUANTIZATION_ROUNDING_TQR 1741 uint32_t TrellisQuantizationEnabledTqenb : __CODEGEN_BITFIELD(31, 31); //!< TRELLIS_QUANTIZATION_ENABLED_TQENB 1742 }; 1743 uint32_t Value; 1744 } DW5; 1745 union 1746 { 1747 struct 1748 { 1749 uint32_t Intrambmaxsz : __CODEGEN_BITFIELD(0, 11); //!< IntraMbMaxSz 1750 uint32_t Reserved204 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 1751 uint32_t Intermbmaxsz : __CODEGEN_BITFIELD(16, 27); //!< InterMbMaxSz 1752 uint32_t Reserved220 : __CODEGEN_BITFIELD(28, 31); //!< Reserved 1753 }; 1754 uint32_t Value; 1755 } DW6; 1756 union 1757 { 1758 struct 1759 { 1760 uint32_t VslTopMbTrans8X8Flag : __CODEGEN_BITFIELD(0, 0); //!< VSL_TOP_MB_TRANS8X8FLAG 1761 uint32_t Reserved225 : __CODEGEN_BITFIELD(1, 31); //!< Reserved 1762 }; 1763 uint32_t Value; 1764 } DW7; 1765 union 1766 { 1767 struct 1768 { 1769 uint32_t Slicedeltaqppmax0 : __CODEGEN_BITFIELD(0, 7); //!< SliceDeltaQpPMax[0] 1770 uint32_t Slicedeltaqpmax1 : __CODEGEN_BITFIELD(8, 15); //!< SliceDeltaQpMax[1] 1771 uint32_t Slicedeltaqpmax2 : __CODEGEN_BITFIELD(16, 23); //!< SliceDeltaQpMax[2] 1772 uint32_t Slicedeltaqpmax3 : __CODEGEN_BITFIELD(24, 31); //!< SliceDeltaQpMax[3] 1773 }; 1774 uint32_t Value; 1775 } DW8; 1776 union 1777 { 1778 struct 1779 { 1780 uint32_t Slicedeltaqpmin0 : __CODEGEN_BITFIELD(0, 7); //!< SliceDeltaQpMin[0] 1781 uint32_t Slicedeltaqpmin1 : __CODEGEN_BITFIELD(8, 15); //!< SliceDeltaQpMin[1] 1782 uint32_t Slicedeltaqpmin2 : __CODEGEN_BITFIELD(16, 23); //!< SliceDeltaQpMin[2] 1783 uint32_t Slicedeltaqpmin3 : __CODEGEN_BITFIELD(24, 31); //!< SliceDeltaQpMin[3] 1784 }; 1785 uint32_t Value; 1786 } DW9; 1787 union 1788 { 1789 struct 1790 { 1791 uint32_t Framebitratemin : __CODEGEN_BITFIELD(0, 13); //!< FrameBitRateMin 1792 uint32_t Framebitrateminunitmode : __CODEGEN_BITFIELD(14, 14); //!< FRAMEBITRATEMINUNITMODE 1793 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(15, 15); //!< FRAMEBITRATEMINUNIT 1794 uint32_t Framebitratemax : __CODEGEN_BITFIELD(16, 29); //!< FrameBitRateMax 1795 uint32_t Framebitratemaxunitmode : __CODEGEN_BITFIELD(30, 30); //!< FRAMEBITRATEMAXUNITMODE 1796 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31); //!< FRAMEBITRATEMAXUNIT_ 1797 }; 1798 uint32_t Value; 1799 } DW10; 1800 union 1801 { 1802 struct 1803 { 1804 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD(0, 14); //!< FrameBitRateMinDelta 1805 uint32_t Reserved367 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 1806 uint32_t Framebitratemaxdelta : __CODEGEN_BITFIELD(16, 30); //!< FRAMEBITRATEMAXDELTA 1807 uint32_t SliceStatsStreamoutEnable : __CODEGEN_BITFIELD(31, 31); //!< Slice Stats Streamout Enable 1808 }; 1809 uint32_t Value; 1810 } DW11; 1811 union 1812 { 1813 struct 1814 { 1815 uint32_t Reserved384 : __CODEGEN_BITFIELD(0, 16); //!< Reserved 1816 uint32_t Reserved401 : __CODEGEN_BITFIELD(17, 17); //!< Reserved 1817 uint32_t VadErrorLogic : __CODEGEN_BITFIELD(18, 18); //!< VAD_ERROR_LOGIC 1818 uint32_t Reserved403 : __CODEGEN_BITFIELD(19, 19); //!< Reserved 1819 uint32_t VmdErrorLogic : __CODEGEN_BITFIELD(20, 20); //!< VMD_ERROR_LOGIC 1820 uint32_t Reserved405 : __CODEGEN_BITFIELD(21, 31); //!< Reserved 1821 }; 1822 uint32_t Value; 1823 } DW12; 1824 union 1825 { 1826 struct 1827 { 1828 uint32_t InitialQpValue : __CODEGEN_BITFIELD(0, 7); //!< Initial QP Value 1829 uint32_t NumberOfActiveReferencePicturesFromL0 : __CODEGEN_BITFIELD(8, 13); //!< Number of Active Reference Pictures from L0 1830 uint32_t Reserved430 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 1831 uint32_t NumberOfActiveReferencePicturesFromL1 : __CODEGEN_BITFIELD(16, 21); //!< Number of Active Reference Pictures from L1 1832 uint32_t Reserved438 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 1833 uint32_t NumberOfReferenceFrames : __CODEGEN_BITFIELD(24, 28); //!< Number of Reference Frames 1834 uint32_t CurrentPictureHasPerformedMmco5 : __CODEGEN_BITFIELD(29, 29); //!< Current Picture Has Performed MMCO5 1835 uint32_t Reserved446 : __CODEGEN_BITFIELD(30, 31); //!< Reserved 1836 }; 1837 uint32_t Value; 1838 } DW13; 1839 union 1840 { 1841 struct 1842 { 1843 uint32_t PicOrderPresentFlag : __CODEGEN_BITFIELD(0, 0); //!< Pic_order_present_flag 1844 uint32_t DeltaPicOrderAlwaysZeroFlag : __CODEGEN_BITFIELD(1, 1); //!< Delta_pic_order_always_zero_flag 1845 uint32_t PicOrderCntType : __CODEGEN_BITFIELD(2, 3); //!< Pic_order_cnt_type 1846 uint32_t Reserved452 : __CODEGEN_BITFIELD(4, 7); //!< Reserved 1847 uint32_t SliceGroupMapType : __CODEGEN_BITFIELD(8, 10); //!< slice_group_map_type 1848 uint32_t RedundantPicCntPresentFlag : __CODEGEN_BITFIELD(11, 11); //!< redundant_pic_cnt_present_flag 1849 uint32_t NumSliceGroupsMinus1 : __CODEGEN_BITFIELD(12, 14); //!< num_slice_groups_minus1 1850 uint32_t DeblockingFilterControlPresentFlag : __CODEGEN_BITFIELD(15, 15); //!< deblocking_filter_control_present_flag 1851 uint32_t Log2MaxFrameNumMinus4 : __CODEGEN_BITFIELD(16, 23); //!< Log2_max_frame_num_minus4 1852 uint32_t Log2MaxPicOrderCntLsbMinus4 : __CODEGEN_BITFIELD(24, 31); //!< Log2_max_pic_order_cnt_lsb_minus4 1853 }; 1854 uint32_t Value; 1855 } DW14; 1856 union 1857 { 1858 struct 1859 { 1860 uint32_t SliceGroupChangeRate : __CODEGEN_BITFIELD(0, 15); //!< Slice Group Change Rate 1861 uint32_t CurrPicFrameNum : __CODEGEN_BITFIELD(16, 31); //!< Curr Pic Frame Num 1862 }; 1863 uint32_t Value; 1864 } DW15; 1865 union 1866 { 1867 struct 1868 { 1869 uint32_t CurrentFrameViewId : __CODEGEN_BITFIELD(0, 9); //!< Current Frame View ID 1870 uint32_t Reserved522 : __CODEGEN_BITFIELD(10, 11); //!< Reserved 1871 uint32_t MaxViewIdxl0 : __CODEGEN_BITFIELD(12, 15); //!< Max View IDXL0 1872 uint32_t Reserved528 : __CODEGEN_BITFIELD(16, 17); //!< Reserved 1873 uint32_t MaxViewIdxl1 : __CODEGEN_BITFIELD(18, 21); //!< Max View IDXL1 1874 uint32_t Reserved534 : __CODEGEN_BITFIELD(22, 30); //!< Reserved 1875 uint32_t InterViewOrderDisable : __CODEGEN_BITFIELD(31, 31); //!< INTER_VIEW_ORDER_DISABLE 1876 }; 1877 uint32_t Value; 1878 } DW16; 1879 union 1880 { 1881 struct 1882 { 1883 uint32_t FractionalQpInput : __CODEGEN_BITFIELD(0, 2); //!< Fractional QP input 1884 uint32_t FractionalQpOffset : __CODEGEN_BITFIELD(3, 5); //!< Fractional QP offset 1885 uint32_t Reserved550 : __CODEGEN_BITFIELD(6, 7); //!< Reserved 1886 uint32_t ExtendedRhodomainStatisticsEnable : __CODEGEN_BITFIELD(8, 8); //!< Extended RhoDomain Statistics Enable 1887 uint32_t Reserved553 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 1888 uint32_t RhodomainAveragemacroblockqp : __CODEGEN_BITFIELD(16, 21); //!< RhoDomain AverageMacroblockQP 1889 uint32_t Reserved566 : __CODEGEN_BITFIELD(22, 31); //!< Reserved 1890 }; 1891 uint32_t Value; 1892 } DW17; 1893 union 1894 { 1895 struct 1896 { 1897 uint32_t Reserved576; //!< Reserved 1898 }; 1899 uint32_t Value; 1900 } DW18; 1901 union 1902 { 1903 struct 1904 { 1905 uint32_t ThresholdSizeInBytes; //!< Threshold Size in Bytes 1906 }; 1907 uint32_t Value; 1908 } DW19; 1909 union 1910 { 1911 struct 1912 { 1913 uint32_t TargetSliceSizeInBytes; //!< Target Slice Size in Bytes 1914 }; 1915 uint32_t Value; 1916 } DW20; 1917 1918 //! \name Local enumerations 1919 1920 enum SUBOPCODE_B 1921 { 1922 SUBOPCODE_B_UNNAMED0 = 0, //!< No additional details 1923 }; 1924 1925 enum SUBOPCODE_A 1926 { 1927 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 1928 }; 1929 1930 enum MEDIA_COMMAND_OPCODE 1931 { 1932 MEDIA_COMMAND_OPCODE_AVCCOMMON = 1, //!< No additional details 1933 }; 1934 1935 enum PIPELINE 1936 { 1937 PIPELINE_MFXAVCIMGSTATE = 2, //!< No additional details 1938 }; 1939 1940 enum COMMAND_TYPE 1941 { 1942 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1943 }; 1944 1945 //! \brief IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10 1946 //! \details 1947 //! The current encoding picture structure can only takes on 3 possible 1948 //! values 1949 enum IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10 1950 { 1951 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_FRAMEPICTURE = 0, //!< No additional details 1952 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_TOPFIELDPICTURE = 1, //!< No additional details 1953 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_INVALID_NOTALLOWED = 2, //!< No additional details 1954 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_BOTTOMFIELDPICTURE = 3, //!< No additional details 1955 }; 1956 1957 //! \brief WEIGHTED_BIPRED_IDC 1958 //! \details 1959 //! (This field is defined differently from DevSNB; DevIVB follows strictly 1960 //! AVC interface.) 1961 enum WEIGHTED_BIPRED_IDC 1962 { 1963 WEIGHTED_BIPRED_IDC_DEFAULT = 0, //!< Specifies that the default weighted prediction is used for B slices 1964 WEIGHTED_BIPRED_IDC_EXPLICIT = 1, //!< Specifies that explicit weighted prediction is used for B slices 1965 WEIGHTED_BIPRED_IDC_IMPLICIT = 2, //!< Specifies that implicit weighted prediction is used for B slices. 1966 }; 1967 1968 //! \brief WEIGHTED_PRED_FLAG 1969 //! \details 1970 //! (This field is defined differently from Gen6, Gen7 follows strictly AVC 1971 //! interface.) 1972 enum WEIGHTED_PRED_FLAG 1973 { 1974 WEIGHTED_PRED_FLAG_DISABLE = 0, //!< specifies that weighted prediction is not used for P and SP slices 1975 WEIGHTED_PRED_FLAG_ENABLE = 1, //!< specifies that weighted prediction is used for P and SP slices 1976 }; 1977 1978 //! \brief RHODOMAIN_RATE_CONTROL_ENABLE 1979 //! \details 1980 //! This field indicates if RhoDomain related parameters are present in the 1981 //! MFX_AVC_IMAGE_STATE. (AverageMacroblockQP). It enables the Rho Domain 1982 //! statistics collection. 1983 enum RHODOMAIN_RATE_CONTROL_ENABLE 1984 { 1985 RHODOMAIN_RATE_CONTROL_ENABLE_DISABLE = 0, //!< RhoDomain rate control parameters are not present in MFX_AVC_IMAGE_STATE 1986 RHODOMAIN_RATE_CONTROL_ENABLE_ENABLE = 1, //!< RhoDomain rate control parameters are present in MFX_AVC_IMAGE_STATE. 1987 }; 1988 1989 //! \brief FIELDPICFLAG 1990 //! \details 1991 //! Field picture flag, field_pic_flag, specifies the current slice is a 1992 //! coded field or not.It is set to the same value as the syntax element in 1993 //! the Slice Header. It must be consistent with the img_structure[1:0] and 1994 //! the frame_mbs_only_flag settings.Although field_pic_flag is a Slice 1995 //! Header parameter, its value is expected to be the same for all the 1996 //! slices of a picture. 1997 enum FIELDPICFLAG 1998 { 1999 FIELDPICFLAG_FRAME = 0, //!< a slice of a coded frame 2000 FIELDPICFLAG_FIELD = 1, //!< a slice of a coded field 2001 }; 2002 2003 //! \brief MBAFFFLAMEFLAG 2004 //! \details 2005 //! MBAFF mode is active, mbaff_frame_flag.It is derived from MbaffFrameFlag 2006 //! = (mb_adaptive_frame_field_flag && ! field_pic_flag ). 2007 //! mb_adaptive_frame_field_flag is a syntax element in the current active 2008 //! SPS and field_pic_flag is a syntax element in the current Slice Header. 2009 //! They both are present only if frame_mbs_only_flag is 0. Although 2010 //! mbaff_frame_flag is a Slice Header parameter, its value is expected to 2011 //! be the same for all the slices of a picture.It must be consistent with 2012 //! the mb_adaptive_frame_field_flag, the field_pic_flag and the 2013 //! frame_mbs_only_flag settings.This bit is valid only when the 2014 //! img_structure[1:0] indicates the current picture is a frame. 2015 enum MBAFFFLAMEFLAG 2016 { 2017 MBAFFFLAMEFLAG_FALSE = 0, //!< not in MBAFF mode 2018 MBAFFFLAMEFLAG_TRUE = 1, //!< in MBAFF mode 2019 }; 2020 2021 //! \brief FRAMEMBONLYFLAG 2022 //! \details 2023 //! Frame MB only flag, frame_mbs_only_flagIt is set to the value of the 2024 //! syntax element in the current active SPS. 2025 enum FRAMEMBONLYFLAG 2026 { 2027 FRAMEMBONLYFLAG_FALSE = 0, //!< not true ; effectively enables the possibility of MBAFF mode. 2028 FRAMEMBONLYFLAG_TRUE = 1, //!< true, only frame MBs can occur in this sequence, hence disallows the MBAFF mode and field picture. 2029 }; 2030 2031 //! \brief TRANSFORM8X8FLAG 2032 //! \details 2033 //! 8x8 IDCT Transform Mode Flag, trans8x8_mode_flagSpecifies 8x8 IDCT 2034 //! transform may be used in this pictureIt is set to the value of the 2035 //! syntax element in the current active PPS. 2036 enum TRANSFORM8X8FLAG 2037 { 2038 TRANSFORM8X8FLAG_4X4 = 0, //!< no 8x8 IDCT Transform, only 4x4 IDCT transform blocks are present 2039 TRANSFORM8X8FLAG_8X8 = 1, //!< 8x8 Transform is allowed 2040 }; 2041 2042 //! \brief DIRECT8X8INFFLAG 2043 //! \details 2044 //! Direct 8x8 Inference Flag, direct_8x8_inference_flagIt is set to the 2045 //! value of the syntax element in the current active SPS.It specifies the 2046 //! derivation process for luma motion vectors in the Direct MV coding modes 2047 //! (B_Skip, B_Direct_16x16 and B_Direct_8x8). When frame_mbs_only_flag is 2048 //! equal to 0, direct_8x8_inference_flag shall be equal to 1.It must be 2049 //! consistent with the frame_mbs_only_flag and transform_8x8_mode_flag 2050 //! settings. 2051 enum DIRECT8X8INFFLAG 2052 { 2053 DIRECT8X8INFFLAG_SUBBLOCK = 0, //!< allows subpartitioning to go below 8x8 block size (i.e. 4x4, 8x4 or 4x8) 2054 DIRECT8X8INFFLAG_BLOCK = 1, //!< allows processing only at 8x8 block size. MB Info is stored for 8x8 block size. 2055 }; 2056 2057 //! \brief CONSTRAINEDIPREDFLAG 2058 //! \details 2059 //! Constrained Intra Prediction Flag, constrained_ipred_flagIt is set to 2060 //! the value of the syntax element in the current active PPS. 2061 enum CONSTRAINEDIPREDFLAG 2062 { 2063 CONSTRAINEDIPREDFLAG_INTRAANDINTER = 0, //!< allows both intra and inter neighboring MB to be used in the intra-prediction encoding of the current MB. 2064 CONSTRAINEDIPREDFLAG_INTRAONLY = 1, //!< allows only to use neighboring Intra MBs in the intra-prediction encoding of the current MB. If the neighbor is an inter MB, it is considered as not available. 2065 }; 2066 2067 //! \brief IMGDISPOSABLEFLAG 2068 //! \details 2069 //! Current Img Disposable Flag or Non-Reference Picture Flag 2070 enum IMGDISPOSABLEFLAG 2071 { 2072 IMGDISPOSABLEFLAG_REFERENCE = 0, //!< the current decoding picture may be used as a reference picture for others 2073 IMGDISPOSABLEFLAG_DISPOSABLE = 1, //!< the current decoding picture is not used as a reference picture (e.g. a B-picture cannot be a reference picture for any subsequent decoding) 2074 }; 2075 2076 //! \brief ENTROPYCODINGFLAG 2077 //! \details 2078 //! Entropy Coding Flag, entropy_coding_flag 2079 enum ENTROPYCODINGFLAG 2080 { 2081 ENTROPYCODINGFLAG_CAVLCBIT_SERIALENCODINGMODE = 0, //!< Desc 2082 ENTROPYCODINGFLAG_CABACBIT_SERIALENCODINGMODE = 1, //!< Desc 2083 }; 2084 2085 //! \brief MBMVFORMATFLAG 2086 //! \details 2087 //! Use MB level MvFormat flag (Encoder Only)(This bit must be set to zero 2088 //! in IVB:GT2:A0) 2089 enum MBMVFORMATFLAG 2090 { 2091 MBMVFORMATFLAG_IGNORE = 0, //!< HW PAK ignore MvFormat in the MB data. 2092 MBMVFORMATFLAG_FOLLOW = 1, //!< HW PAK will follow MvFormat value set within each MB data. 2093 }; 2094 2095 //! \brief CHROMAFORMATIDC 2096 //! \details 2097 //! Chroma Format IDC, ChromaFormatIdc[1:0]It specifies the sampling of 2098 //! chroma component (Cb, Cr) in the current picture as follows : 2099 enum CHROMAFORMATIDC 2100 { 2101 CHROMAFORMATIDC_MONOCHROMEPICTURE = 0, //!< Desc 2102 CHROMAFORMATIDC_420PICTURE = 1, //!< Desc 2103 CHROMAFORMATIDC_422PICTURE_NOTSUPPORTED = 2, //!< No additional details 2104 CHROMAFORMATIDC_444PICTURE_NOTSUPPORTED = 3, //!< No additional details 2105 }; 2106 2107 //! \brief MVUNPACKEDFLAG 2108 //! \details 2109 //! MVUnPackedEnable (Encoder Only)This field is reserved in Decode mode. 2110 enum MVUNPACKEDFLAG 2111 { 2112 MVUNPACKEDFLAG_PACKED = 0, //!< use packed MV format 2113 MVUNPACKEDFLAG_UNPACKED = 1, //!< use unpacked 8MV/32MV format only 2114 }; 2115 2116 //! \brief INSERTTESTFLAG 2117 //! \details 2118 //! CABAC 0 Word Insertion Test Enable (Encoder Only)This bit will modify 2119 //! CABAC K equation so that a positive K value can be generated easily. 2120 //! This is done for validation purpose only. In normal usage this bit 2121 //! should be set to 0.Regular equation for generating 'K' value when CABAC 2122 //! 0 Word Insertion Test Enable is set to 0.K = { [ ((96 * pic_bin_count()) 2123 //! - (RawMbBits * PicSizeInMbs *3) + 1023) / 1024 ] - bytes_in_picture } / 2124 //! 3Modified equation when CABAC 0 Word Insertion Test Enable bit set to 2125 //! 1.K = { [ ((3072 * pic_bin_count()) - (RawMbBits * PicSizeInMbs *3) + 2126 //! 1023) / 1024 ] - bytes_in_picture } / 3 2127 enum INSERTTESTFLAG 2128 { 2129 INSERTTESTFLAG_UNNAMED0 = 0, //!< No additional details 2130 }; 2131 2132 //! \brief LOADSLICEPOINTERFLAG 2133 //! \details 2134 //! LoadBitStreamPointerPerSlice (Encoder-only)To support multiple slice 2135 //! picture and additional header/data insertion before and after an encoded 2136 //! slice.When this field is set to 0, bitstream pointer is only loaded once 2137 //! for the first slice of a frame. For subsequent slices in the frame, 2138 //! bitstream data are stitched together to form a single output data 2139 //! stream.When this field is set to 1, bitstream pointer is loaded for each 2140 //! slice of a frame. Basically bitstream data for different slices of a 2141 //! frame will be written to different memory locations. 2142 enum LOADSLICEPOINTERFLAG 2143 { 2144 LOADSLICEPOINTERFLAG_DISABLE = 0, //!< Load BitStream Pointer only once for the first slice of a frame 2145 LOADSLICEPOINTERFLAG_ENABLE = 1, //!< Load/reload BitStream Pointer only once for the each slice, reload the start location of the bitstream buffer from the Indirect PAK-BSE Object Data Start Address field 2146 }; 2147 2148 //! \brief MBSTATENABLED 2149 //! \details 2150 //! Enable reading in MB status buffer (a.k.a. encoding stream-out 2151 //! buffer) Note: For multi-pass encoder, all passes except the first one 2152 //! need to set this value to 1. By setting the first pass to 0, it does 2153 //! save some memory bandwidth. <span 2154 //! style="color: rgb(0, 0, 0); font-family: Arial, sans-serif; line-height: 2155 //! normal;">In VDenc mode this must be set to zero as no MB level rate 2156 //! control is used. 2157 enum MBSTATENABLED 2158 { 2159 MBSTATENABLED_DISABLE = 0, //!< Disable Reading of Macroblock Status Buffer 2160 MBSTATENABLED_ENABLE = 1, //!< Enable Reading of Macroblock Status Buffer 2161 }; 2162 2163 //! \brief MINFRAMEWSIZE 2164 //! \details 2165 //! Minimum Frame Size [15:0] (in Word, 16-bit)(Encoder 2166 //! Only) Minimum Frame Size is specified to compensate for intel Rate 2167 //! Control Currently zero fill (no need to perform emulation byte 2168 //! insertion) is done only to the end of the CABAC_ZERO_WORD insertion (if 2169 //! any) at the last slice of a picture. Intel encoder parameter. The caller 2170 //! should always make sure that the value, represented by Minimum Frame 2171 //! Size, is always less than maximum frame size FrameBitRateMax (DWORD 2172 //! 10 bits 29:16). This field is reserved in Decode mode. 2173 //! The programmable range 02^18-1 When 2174 //! MinFrameWSizeUnits is 00. Programmable range is 02^20-1 2175 //! when MinFrameWSizeUnits is 01. Programmable range is 2176 //! 02^26-1 when MinFrameWSizeUnits is 10. Programmable 2177 //! range is 02^32-1 when MinFrameWSizeUnits is 11. 2178 enum MINFRAMEWSIZE 2179 { 2180 MINFRAMEWSIZE_UNNAMED0 = 0, //!< No additional details 2181 }; 2182 2183 //! \brief INTRAMBMAXBITFLAG_INTRAMBMAXSIZEREPORTMASK 2184 //! \details 2185 //! This is a mask bit controlling if the condition of any intra MB in the 2186 //! frame exceeds IntraMBMaxSize. 2187 enum INTRAMBMAXBITFLAG_INTRAMBMAXSIZEREPORTMASK 2188 { 2189 INTRAMBMAXBITFLAG_INTRAMBMAXSIZEREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2190 INTRAMBMAXBITFLAG_INTRAMBMAXSIZEREPORTMASK_ENABLE = 1, //!< set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Intra MB Conformance Max size limit. 2191 }; 2192 2193 //! \brief INTERMBMAXBITFLAG_INTERMBMAXSIZEREPORTMASK 2194 //! \details 2195 //! This is a mask bit controlling if the condition of any inter MB in the 2196 //! frame exceeds InterMBMaxSize. 2197 enum INTERMBMAXBITFLAG_INTERMBMAXSIZEREPORTMASK 2198 { 2199 INTERMBMAXBITFLAG_INTERMBMAXSIZEREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2200 INTERMBMAXBITFLAG_INTERMBMAXSIZEREPORTMASK_ENABLE = 1, //!< Set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Inter MB Conformance Max size limit. 2201 }; 2202 2203 //! \brief FRAMESZOVERFLAG_FRAMEBITRATEMAXREPORTMASK 2204 //! \details 2205 //! This is a mask bit controlling if the condition of frame level bit count 2206 //! exceeds FrameBitRateMax. 2207 enum FRAMESZOVERFLAG_FRAMEBITRATEMAXREPORTMASK 2208 { 2209 FRAMESZOVERFLAG_FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2210 FRAMESZOVERFLAG_FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< Set bit0 and bit 1 of MFC_IMAGE_STATUS control register if the total frame level bit counter is greater than or equal to Frame Bit rate Maximum limit. 2211 }; 2212 2213 //! \brief FRAMESZUNDERFLAG_FRAMEBITRATEMINREPORTMASK 2214 //! \details 2215 //! This is a mask bit controlling if the condition of frame level bit count 2216 //! is less than FrameBitRateMin 2217 enum FRAMESZUNDERFLAG_FRAMEBITRATEMINREPORTMASK 2218 { 2219 FRAMESZUNDERFLAG_FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2220 FRAMESZUNDERFLAG_FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< set bit0 and bit 1of MFC_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit rate Minimum limit. 2221 }; 2222 2223 //! \brief INTRAINTERMBIPCMFLAG_FORCEIPCMCONTROLMASK 2224 //! \details 2225 //! This field is to Force IPCM for Intra or Inter Macroblock size 2226 //! conformance mask. 2227 enum INTRAINTERMBIPCMFLAG_FORCEIPCMCONTROLMASK 2228 { 2229 INTRAINTERMBIPCMFLAG_FORCEIPCMCONTROLMASK_DISABLE = 0, //!< Do not change intra or Inter macroblocks even 2230 INTRAINTERMBIPCMFLAG_FORCEIPCMCONTROLMASK_ENABLE = 1, //!< Change intra or Inter macroblocks MB_type to IPCM 2231 }; 2232 2233 //! \brief MBRATECTRLFLAG_MB_LEVEL_RATE_CONTROL_ENABLING_FLAG 2234 //! \details 2235 //! MB Rate Control conformance mask In VDenc mode, this 2236 //! field must be zero as frame level rate control is used. 2237 enum MBRATECTRLFLAG_MB_LEVEL_RATE_CONTROL_ENABLING_FLAG 2238 { 2239 MBRATECTRLFLAG_MB_LEVEL_RATE_CONTROL_ENABLING_FLAG_DISABLE = 0, //!< Apply accumulative delta QP for consecutive passes on top of the macroblock QP values in inline data 2240 MBRATECTRLFLAG_MB_LEVEL_RATE_CONTROL_ENABLING_FLAG_ENABLE = 1, //!< Apply RC QP delta to suggested QP values in Macroblock Status Buffer except the first pass. 2241 }; 2242 2243 //! \brief MINFRAMEWSIZEUNITS 2244 //! \details 2245 //! This field is the Minimum Frame Size Units 2246 enum MINFRAMEWSIZEUNITS 2247 { 2248 MINFRAMEWSIZEUNITS_COMPATIBILITYMODE = 0, //!< Minimum Frame Size is in old mode (words, 2bytes) 2249 MINFRAMEWSIZEUNITS_16BYTE = 1, //!< Minimum Frame Size is in 16bytes 2250 MINFRAMEWSIZEUNITS_4KB = 2, //!< Minimum Frame Size is in 4Kbytes 2251 MINFRAMEWSIZEUNITS_16KB = 3, //!< Minimum Frame Size is in 16Kbytes 2252 }; 2253 2254 //! \brief NONFIRSTPASSFLAG 2255 //! \details 2256 //! This signals the current pass is not the first pass. It will imply 2257 //! designate HW behavior: e.g 2258 enum NONFIRSTPASSFLAG 2259 { 2260 NONFIRSTPASSFLAG_DISABLE = 0, //!< Always use the MbQpY from initial PAK inline object for all passes of PAK 2261 NONFIRSTPASSFLAG_ENABLE = 1, //!< Use MbQpY from stream-out buffer if MbRateCtrlFlag is set to 1 2262 }; 2263 2264 //! \brief TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE 2265 //! \details 2266 //! This signal is used to disable chroma TQ. To enable TQ for both luma and 2267 //! chroma, TQEnb=1, TQChromaDisable=0. To enable TQ only for luma, TQEnb=1, 2268 //! TQChromaDisable=1. 2269 enum TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE 2270 { 2271 TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE_UNNAMED0 = 0, //!< Enable Trellis Quantization chroma 2272 TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE_DEFAULT = 1, //!< Disable Trellis Quantization chroma 2273 }; 2274 2275 //! \brief TRELLIS_QUANTIZATION_ROUNDING_TQR 2276 //! \details 2277 //! This rounding scheme is only applied to the quantized coefficients 2278 //! ranging from 0 to 1 when TQEnb is set to 1 in AVC CABAC mode. One of the 2279 //! following values is added to quantized coefficients before truncating 2280 //! fractional part. 2281 enum TRELLIS_QUANTIZATION_ROUNDING_TQR 2282 { 2283 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED0 = 0, //!< Add 1/8 2284 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED1 = 1, //!< Add 2/8 2285 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED2 = 2, //!< Add 3/8 2286 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED3 = 3, //!< Add 4/8 (rounding 0.5) 2287 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED4 = 4, //!< Add 5/8 2288 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED5 = 5, //!< Add 6/8 2289 TRELLIS_QUANTIZATION_ROUNDING_TQR_DEFAULT = 6, //!< Add 7/8 (Default rounding 0.875) 2290 }; 2291 2292 //! \brief TRELLIS_QUANTIZATION_ENABLED_TQENB 2293 //! \details 2294 //! The TQ improves output video quality of AVC CABAC encoder by selecting 2295 //! quantized values for each non-zero coefficient so as to minimize the 2296 //! total R-D cost.This flag is only valid AVC CABAC mode. Otherwise, this 2297 //! flag should be disabled. 2298 enum TRELLIS_QUANTIZATION_ENABLED_TQENB 2299 { 2300 TRELLIS_QUANTIZATION_ENABLED_TQENB_DISABLE = 0, //!< Use Normal 2301 TRELLIS_QUANTIZATION_ENABLED_TQENB_ENABLE = 1, //!< Use Trellis quantization 2302 }; 2303 2304 enum VSL_TOP_MB_TRANS8X8FLAG 2305 { 2306 VSL_TOP_MB_TRANS8X8FLAG_DISABLE = 0, //!< VSL will only fetch the current MB data. 2307 VSL_TOP_MB_TRANS8X8FLAG_ENABLE = 1, //!< When this bit is set VSL will make extra fetch to memory to fetch the MB data for top MB. 2308 }; 2309 2310 //! \brief FRAMEBITRATEMINUNITMODE 2311 //! \details 2312 //! This field is the Frame Bitrate Minimum Limit Units. 2313 enum FRAMEBITRATEMINUNITMODE 2314 { 2315 FRAMEBITRATEMINUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 2316 FRAMEBITRATEMINUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 2317 }; 2318 2319 //! \brief FRAMEBITRATEMINUNIT 2320 //! \details 2321 //! This field is the Frame Bitrate Minimum Limit Units. 2322 enum FRAMEBITRATEMINUNIT 2323 { 2324 FRAMEBITRATEMINUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMinUnitMode is 1 and in units of 128 Bytes if FrameBitrateMinUnitMode is 0 2325 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 2326 }; 2327 2328 //! \brief FRAMEBITRATEMAXUNITMODE 2329 //! \details 2330 //! This field is the Frame Bitrate Maximum Limit Units. 2331 enum FRAMEBITRATEMAXUNITMODE 2332 { 2333 FRAMEBITRATEMAXUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 2334 FRAMEBITRATEMAXUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 2335 }; 2336 2337 //! \brief FRAMEBITRATEMAXUNIT_ 2338 //! \details 2339 //! This field is the Frame Bitrate Maximum Limit Units. 2340 enum FRAMEBITRATEMAXUNIT_ 2341 { 2342 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMaxUnitMode is 1 and in units of 128 Bytes if FrameBitrateMaxUnitMode is 0 2343 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 2344 }; 2345 2346 //! \brief FRAMEBITRATEMAXDELTA 2347 //! \details 2348 //! This field is used to select the slice delta QP when FrameBitRateMax Is 2349 //! exceeded. It shares the same FrameBitrateMaxUnit. When 2350 //! FrameBitrateMaxUnitMode is 0(compatibility mode), only bits 16:27 should 2351 //! be used, bits 28, 29 and 30 should be 0. 2352 enum FRAMEBITRATEMAXDELTA 2353 { 2354 FRAMEBITRATEMAXDELTA_UNNAMED0 = 0, //!< No additional details 2355 }; 2356 2357 enum VAD_ERROR_LOGIC 2358 { 2359 VAD_ERROR_LOGIC_ENABLE = 0, //!< Error reporting ON in case of premature Slice done 2360 VAD_ERROR_LOGIC_DISABLE = 1, //!< CABAC Engine will auto decode the bitstream in case of premature slice done. 2361 }; 2362 2363 enum VMD_ERROR_LOGIC 2364 { 2365 VMD_ERROR_LOGIC_DISABLE = 0, //!< No additional details 2366 VMD_ERROR_LOGIC_ENABLE = 1, //!< Error Handling 2367 }; 2368 2369 //! \brief INTER_VIEW_ORDER_DISABLE 2370 //! \details 2371 //! It indicates how to append inter-view picture into initial sorted 2372 //! reference list. (due to ambiguity in the MVC Spec) 2373 enum INTER_VIEW_ORDER_DISABLE 2374 { 2375 INTER_VIEW_ORDER_DISABLE_DEFAULT = 0, //!< View Order Ascending 2376 INTER_VIEW_ORDER_DISABLE_DISABLE = 1, //!< View ID Ascending 2377 }; 2378 2379 //! \name Initializations 2380 2381 //! \brief Explicit member initialization function 2382 MFX_AVC_IMG_STATE_CMD(); 2383 2384 static const size_t dwSize = 21; 2385 static const size_t byteSize = 84; 2386 }; 2387 2388 //! 2389 //! \brief MFX_AVC_REF_IDX_STATE 2390 //! \details 2391 //! This is a slice level command and can be issued multiple times within a 2392 //! picture that is comprised of multiple slices. The same command is used 2393 //! for AVC encoder (PAK mode) and decoder (VLD mode); it is not need in 2394 //! decoder IT mode. The inline data of this command is interpreted 2395 //! differently for encoder as for decoder. For decoder, it is interpreted 2396 //! as RefIdx List L0/L1 as in AVC spec., and it matches with the AVC API 2397 //! data structure for decoder in VLD mode : RefPicList[2][32] (L0:L1, 0:31 2398 //! RefPic). But for encoder, it is interpreted as a Reference Index 2399 //! Mapping Table for L0 and L1 reference pictures. For packing the bits at 2400 //! the output of PAK, the syntax elements must follow the definition of 2401 //! RefIdxL0/L1 list according to the AVC spec. However, the decoder 2402 //! pipeline was designed to use a variation of that standard definition, as 2403 //! such a conversion (mapping) is needed to support the hardware design.The 2404 //! Reference lists are needed in processing both P and B slice in AVC 2405 //! codec. For P-MB, only L0 list is used; for B-MB both L0 and L1 lists are 2406 //! needed. For a B-MB that is coded in L1-only Prediction, only L1 list is 2407 //! used. 2408 //! 2409 //! An application will create the RefPicList L0 and L1 and pass onto the 2410 //! driver. The content of each entry of RefPicList L0/L1[ ] is a 7-bit 2411 //! picture index. This picture index is the same as that of RefFrameList[ 2412 //! ] content. This picture index, however, is not defined the same as the 2413 //! frame store ID (0 to 16, 5-bits) we have implemented in H/W. Hence, 2414 //! driver is required to manage a table to convert between picture index 2415 //! and intel frame store ID. As such, the final RefPicList L0/L1[ ] that 2416 //! the driver passes onto the H/W is not the same as that defined. 2417 //! 2418 struct MFX_AVC_REF_IDX_STATE_CMD 2419 { 2420 union 2421 { 2422 struct 2423 { 2424 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 2425 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 2426 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODEB 2427 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODEA 2428 uint32_t CommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< COMMAND_OPCODE 2429 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 2430 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 2431 }; 2432 uint32_t Value; 2433 } DW0; 2434 union 2435 { 2436 struct 2437 { 2438 uint32_t RefpiclistSelect : __CODEGEN_BITFIELD(0, 0); //!< REFPICLIST_SELECT 2439 uint32_t Reserved33 : __CODEGEN_BITFIELD(1, 31); //!< Reserved 2440 }; 2441 uint32_t Value; 2442 } DW1; 2443 uint32_t ReferenceListEntry[8]; //!< Reference List Entry 2444 2445 //! \name Local enumerations 2446 2447 enum SUBOPCODEB 2448 { 2449 SUBOPCODEB_MFXAVCREFIDXSTATE = 4, //!< No additional details 2450 }; 2451 2452 enum SUBOPCODEA 2453 { 2454 SUBOPCODEA_MFXAVCREFIDXSTATE = 0, //!< No additional details 2455 }; 2456 2457 enum COMMAND_OPCODE 2458 { 2459 COMMAND_OPCODE_AVC = 1, //!< No additional details 2460 }; 2461 2462 enum PIPELINE 2463 { 2464 PIPELINE_MFXAVCREFIDXSTATE = 2, //!< No additional details 2465 }; 2466 2467 enum COMMAND_TYPE 2468 { 2469 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2470 }; 2471 2472 //! \brief REFPICLIST_SELECT 2473 //! \details 2474 //! Num_ref_idx_l1_active is resulted from the specifications in both PPS 2475 //! and Slice Header for the current slice. However, since the full 2476 //! reference list L0 and/or L1 are always sent, only present flags are 2477 //! specified instead. This parameter is specified for Intel 2478 //! interface only. 2479 enum REFPICLIST_SELECT 2480 { 2481 REFPICLIST_SELECT_REFPICLIST0 = 0, //!< The list that followed represents RefList L0 (Decoder VLD mode) or Ref Idx Mapping Table L0 (Encoder PAK mode) 2482 REFPICLIST_SELECT_REFPICLIST1 = 1, //!< The list that followed represents RefList L1 (Decoder VLD mode) or Ref Idx Mapping Table L1 (Encoder PAK mode) 2483 }; 2484 2485 //! \name Initializations 2486 2487 //! \brief Explicit member initialization function 2488 MFX_AVC_REF_IDX_STATE_CMD(); 2489 2490 static const size_t dwSize = 10; 2491 static const size_t byteSize = 40; 2492 }; 2493 2494 //! 2495 //! \brief MFX_AVC_WEIGHTOFFSET_STATE 2496 //! \details 2497 //! This is a slice level command and can be issued multiple times within a 2498 //! picture that is comprised of multiple slices. The same command is used 2499 //! for AVC encoder (PAK mode) and decoder (VLD and IT modes). However, 2500 //! since for AVC decoder VLD and IT modes, and AVC encoder mode, the 2501 //! implicit weights are computed in hardware, this command is not issued. 2502 //! For encoder, regardless of the type of weight calculation is active for 2503 //! the current slice (default, implicit or explicit), they are all sent to 2504 //! the PAK as if they were all in explicit mode. However, for implicit 2505 //! weight and offset, each entry contains only a 16-bit weight and no 2506 //! offset (offset = 0 always in implicit mode and can be hard-coded inside 2507 //! the hardware).The weights (and offsets) are needed in processing both P 2508 //! and B slice in AVC codec. For P-MB, at most only L0 list is used; for 2509 //! B-MB both L0 and L1 lists may be needed. For a B-MB that is coded in 2510 //! L1-only Prediction, only L1 list is sent.The content of this command 2511 //! matches with the AVC API data structure for explicit prediction mode 2512 //! only : Weights[2][32][3][2] (L0:L1, 0:31 RefPic, Y:Cb:Cr, W:0) 2513 //! 2514 struct MFX_AVC_WEIGHTOFFSET_STATE_CMD 2515 { 2516 union 2517 { 2518 struct 2519 { 2520 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 2521 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 2522 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 2523 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 2524 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 2525 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 2526 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 2527 }; 2528 uint32_t Value; 2529 } DW0; 2530 union 2531 { 2532 struct 2533 { 2534 uint32_t WeightAndOffsetSelect : __CODEGEN_BITFIELD(0, 0); //!< WEIGHT_AND_OFFSET_SELECT 2535 uint32_t Reserved33 : __CODEGEN_BITFIELD(1, 31); //!< Reserved 2536 }; 2537 uint32_t Value; 2538 } DW1; 2539 uint32_t Weightoffset[96]; //!< WeightOffset 2540 2541 //! \name Local enumerations 2542 2543 enum SUBOPCODE_B 2544 { 2545 SUBOPCODE_B_UNNAMED5 = 5, //!< No additional details 2546 }; 2547 2548 enum SUBOPCODE_A 2549 { 2550 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 2551 }; 2552 2553 enum MEDIA_COMMAND_OPCODE 2554 { 2555 MEDIA_COMMAND_OPCODE_AVCCOMMON = 1, //!< No additional details 2556 }; 2557 2558 enum PIPELINE 2559 { 2560 PIPELINE_MFXAVCWEIGHTOFFSETSTATE = 2, //!< No additional details 2561 }; 2562 2563 enum COMMAND_TYPE 2564 { 2565 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2566 }; 2567 2568 //! \brief WEIGHT_AND_OFFSET_SELECT 2569 //! \details 2570 //! It must be set in consistent with the WeightedPredFlag and 2571 //! WeightedBiPredIdc in the Img_State command.This parameter is specified 2572 //! for Intel interface only. For implicit even though only one entry may be 2573 //! used, still loading the whole 32-entry table. 2574 enum WEIGHT_AND_OFFSET_SELECT 2575 { 2576 WEIGHT_AND_OFFSET_SELECT_WEIGHTANDOFFSETL0TABLE = 0, //!< The list that followed is associated with the weight and offset for RefPicList L0 2577 WEIGHT_AND_OFFSET_SELECT_WEIGHTANDOFFSETL1TABLE = 1, //!< The list that followed is associated with the weight and offset for RefPicList L1 2578 }; 2579 2580 //! \name Initializations 2581 2582 //! \brief Explicit member initialization function 2583 MFX_AVC_WEIGHTOFFSET_STATE_CMD(); 2584 2585 static const size_t dwSize = 98; 2586 static const size_t byteSize = 392; 2587 }; 2588 2589 //! 2590 //! \brief MFX_AVC_SLICE_STATE 2591 //! \details 2592 //! This is a slice level command and can be issued multiple times within a 2593 //! picture that is comprised of multiple slices. The same command is used 2594 //! for AVC encoder (PAK mode) and decoder (VLD and IT modes). 2595 //! 2596 //! In VDEnc mode, this command is programmed for every super-slice. However 2597 //! not all parameters are allowed to change across super-slices. 2598 //! 2599 //! MFX_AVC_SLICE_STATE command is not issued for AVC Short Format Bitstream 2600 //! decode, instead MFD_AVC_SLICEADDR command is executed to retrieve the 2601 //! next slice MB Start Address X and Y by H/W itself. 2602 //! 2603 struct MFX_AVC_SLICE_STATE_CMD 2604 { 2605 union 2606 { 2607 struct 2608 { 2609 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 2610 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 2611 uint32_t CommandSubopcodeb : __CODEGEN_BITFIELD(16, 20); //!< COMMAND_SUBOPCODEB 2612 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODEA 2613 uint32_t CommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< COMMAND_OPCODE 2614 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 2615 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 2616 }; 2617 uint32_t Value; 2618 } DW0; 2619 union 2620 { 2621 struct 2622 { 2623 uint32_t SliceType : __CODEGEN_BITFIELD(0, 3); //!< SLICE_TYPE 2624 uint32_t Reserved36 : __CODEGEN_BITFIELD(4, 31); //!< Reserved 2625 }; 2626 uint32_t Value; 2627 } DW1; 2628 union 2629 { 2630 struct 2631 { 2632 uint32_t Log2WeightDenomLuma : __CODEGEN_BITFIELD(0, 2); //!< Log 2 Weight Denom Luma 2633 uint32_t Reserved67 : __CODEGEN_BITFIELD(3, 7); //!< Reserved 2634 uint32_t Log2WeightDenomChroma : __CODEGEN_BITFIELD(8, 10); //!< Log 2 Weight Denom Chroma 2635 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 15); //!< Reserved 2636 uint32_t NumberOfReferencePicturesInInterPredictionList0 : __CODEGEN_BITFIELD(16, 21); //!< Number of Reference Pictures in Inter-prediction List 0 2637 uint32_t Reserved86 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 2638 uint32_t NumberOfReferencePicturesInInterPredictionList1 : __CODEGEN_BITFIELD(24, 29); //!< Number of Reference Pictures in Inter-prediction List 1 2639 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31); //!< Reserved 2640 }; 2641 uint32_t Value; 2642 } DW2; 2643 union 2644 { 2645 struct 2646 { 2647 uint32_t SliceAlphaC0OffsetDiv2 : __CODEGEN_BITFIELD(0, 3); //!< Slice Alpha C0 Offset Div2 2648 uint32_t Reserved100 : __CODEGEN_BITFIELD(4, 7); //!< Reserved 2649 uint32_t SliceBetaOffsetDiv2 : __CODEGEN_BITFIELD(8, 11); //!< Slice Beta Offset Div2 2650 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 2651 uint32_t SliceQuantizationParameter : __CODEGEN_BITFIELD(16, 21); //!< Slice Quantization Parameter 2652 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 2653 uint32_t CabacInitIdc10 : __CODEGEN_BITFIELD(24, 25); //!< Cabac Init Idc[1:0] 2654 uint32_t Reserved122 : __CODEGEN_BITFIELD(26, 26); //!< Reserved 2655 uint32_t DisableDeblockingFilterIndicator : __CODEGEN_BITFIELD(27, 28); //!< DISABLE_DEBLOCKING_FILTER_INDICATOR 2656 uint32_t DirectPredictionType : __CODEGEN_BITFIELD(29, 29); //!< DIRECT_PREDICTION_TYPE 2657 uint32_t WeightedPredictionIndicator : __CODEGEN_BITFIELD(30, 31); //!< Weighted Prediction Indicator 2658 }; 2659 uint32_t Value; 2660 } DW3; 2661 union 2662 { 2663 struct 2664 { 2665 uint32_t SliceStartMbNum : __CODEGEN_BITFIELD(0, 14); //!< Slice Start Mb Num 2666 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 2667 uint32_t SliceHorizontalPosition : __CODEGEN_BITFIELD(16, 23); //!< Slice Horizontal Position 2668 uint32_t SliceVerticalPosition : __CODEGEN_BITFIELD(24, 31); //!< Slice Vertical Position 2669 }; 2670 uint32_t Value; 2671 } DW4; 2672 union 2673 { 2674 struct 2675 { 2676 uint32_t NextSliceHorizontalPosition : __CODEGEN_BITFIELD(0, 7); //!< Next Slice Horizontal Position 2677 uint32_t Reserved168 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 2678 uint32_t NextSliceVerticalPosition : __CODEGEN_BITFIELD(16, 23); //!< Next Slice Vertical Position 2679 uint32_t Reserved184 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 2680 }; 2681 uint32_t Value; 2682 } DW5; 2683 union 2684 { 2685 struct 2686 { 2687 uint32_t StreamId10 : __CODEGEN_BITFIELD(0, 1); //!< Stream ID [1:0] 2688 uint32_t Reserved194 : __CODEGEN_BITFIELD(2, 3); //!< Reserved 2689 uint32_t SliceId30 : __CODEGEN_BITFIELD(4, 7); //!< Slice ID [3:0] 2690 uint32_t Reserved200 : __CODEGEN_BITFIELD(8, 11); //!< Reserved 2691 uint32_t Cabaczerowordinsertionenable : __CODEGEN_BITFIELD(12, 12); //!< CABACZEROWORDINSERTIONENABLE 2692 uint32_t Emulationbytesliceinsertenable : __CODEGEN_BITFIELD(13, 13); //!< EMULATIONBYTESLICEINSERTENABLE 2693 uint32_t Reserved206 : __CODEGEN_BITFIELD(14, 14); //!< Reserved 2694 uint32_t TailInsertionPresentInBitstream : __CODEGEN_BITFIELD(15, 15); //!< TAIL_INSERTION_PRESENT_IN_BITSTREAM 2695 uint32_t SlicedataInsertionPresentInBitstream : __CODEGEN_BITFIELD(16, 16); //!< SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM 2696 uint32_t HeaderInsertionPresentInBitstream : __CODEGEN_BITFIELD(17, 17); //!< HEADER_INSERTION_PRESENT_IN_BITSTREAM 2697 uint32_t CompressedBitstreamOutputDisableFlag : __CODEGEN_BITFIELD(18, 18); //!< COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG 2698 uint32_t IsLastSlice : __CODEGEN_BITFIELD(19, 19); //!< IS_LAST_SLICE 2699 uint32_t MbTypeSkipConversionDisable : __CODEGEN_BITFIELD(20, 20); //!< MB_TYPE_SKIP_CONVERSION_DISABLE 2700 uint32_t MbTypeDirectConversionDisable : __CODEGEN_BITFIELD(21, 21); //!< MB_TYPE_DIRECT_CONVERSION_DISABLE 2701 uint32_t RcPanicType : __CODEGEN_BITFIELD(22, 22); //!< RC_PANIC_TYPE 2702 uint32_t RcPanicEnable : __CODEGEN_BITFIELD(23, 23); //!< RC_PANIC_ENABLE 2703 uint32_t RcStableTolerance : __CODEGEN_BITFIELD(24, 27); //!< RC Stable Tolerance 2704 uint32_t RcTriggleMode : __CODEGEN_BITFIELD(28, 29); //!< RC_TRIGGLE_MODE 2705 uint32_t Resetratecontrolcounter : __CODEGEN_BITFIELD(30, 30); //!< RESETRATECONTROLCOUNTER 2706 uint32_t RateControlCounterEnable : __CODEGEN_BITFIELD(31, 31); //!< RATE_CONTROL_COUNTER_ENABLE 2707 }; 2708 uint32_t Value; 2709 } DW6; 2710 union 2711 { 2712 struct 2713 { 2714 uint32_t IndirectPakBseDataStartAddressWrite : __CODEGEN_BITFIELD(0, 28); //!< Indirect PAK-BSE Data Start Address (Write) 2715 uint32_t Reserved253 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 2716 }; 2717 uint32_t Value; 2718 } DW7; 2719 union 2720 { 2721 struct 2722 { 2723 uint32_t GrowParamGrowInit : __CODEGEN_BITFIELD(0, 3); //!< Grow Param - Grow Init 2724 uint32_t GrowParamGrowResistance : __CODEGEN_BITFIELD(4, 7); //!< Grow Param - Grow Resistance 2725 uint32_t ShrinkParamShrinkInit : __CODEGEN_BITFIELD(8, 11); //!< Shrink Param - Shrink Init 2726 uint32_t ShrinkParamShrinkResistance : __CODEGEN_BITFIELD(12, 15); //!< Shrink Param - Shrink Resistance 2727 uint32_t MagnitudeOfQpMaxPositiveModifier : __CODEGEN_BITFIELD(16, 23); //!< Magnitude of QP Max Positive Modifier 2728 uint32_t MagnitudeOfQpMaxNegativeModifier : __CODEGEN_BITFIELD(24, 31); //!< Magnitude of QP Max Negative Modifier 2729 }; 2730 uint32_t Value; 2731 } DW8; 2732 union 2733 { 2734 struct 2735 { 2736 uint32_t Correct1 : __CODEGEN_BITFIELD(0, 3); //!< Correct 1 2737 uint32_t Correct2 : __CODEGEN_BITFIELD(4, 7); //!< Correct 2 2738 uint32_t Correct3 : __CODEGEN_BITFIELD(8, 11); //!< Correct 3 2739 uint32_t Correct4 : __CODEGEN_BITFIELD(12, 15); //!< Correct 4 2740 uint32_t Correct5 : __CODEGEN_BITFIELD(16, 19); //!< Correct 5 2741 uint32_t Correct6 : __CODEGEN_BITFIELD(20, 23); //!< Correct 6 2742 uint32_t Roundintra : __CODEGEN_BITFIELD(24, 26); //!< ROUNDINTRA 2743 uint32_t Roundintraenable : __CODEGEN_BITFIELD(27, 27); //!< RoundIntraEnable 2744 uint32_t Roundinter : __CODEGEN_BITFIELD(28, 30); //!< ROUNDINTER 2745 uint32_t Roundinterenable : __CODEGEN_BITFIELD(31, 31); //!< RoundInterEnable 2746 }; 2747 uint32_t Value; 2748 } DW9; 2749 union 2750 { 2751 struct 2752 { 2753 uint32_t Cv0ClampValue0 : __CODEGEN_BITFIELD(0, 3); //!< CV0 - Clamp Value 0 2754 uint32_t Cv1 : __CODEGEN_BITFIELD(4, 7); //!< CV1 2755 uint32_t Cv2 : __CODEGEN_BITFIELD(8, 11); //!< CV2 2756 uint32_t Cv3 : __CODEGEN_BITFIELD(12, 15); //!< CV3 2757 uint32_t Cv4 : __CODEGEN_BITFIELD(16, 19); //!< CV4 2758 uint32_t Cv5 : __CODEGEN_BITFIELD(20, 23); //!< CV5 2759 uint32_t Cv6 : __CODEGEN_BITFIELD(24, 27); //!< CV6 2760 uint32_t ClampvaluesCv7 : __CODEGEN_BITFIELD(28, 31); //!< ClampValues - CV7 2761 }; 2762 uint32_t Value; 2763 } DW10; 2764 2765 //! \name Local enumerations 2766 2767 enum COMMAND_SUBOPCODEB 2768 { 2769 COMMAND_SUBOPCODEB_MFXAVCSLICESTATE = 3, //!< No additional details 2770 }; 2771 2772 enum SUBOPCODEA 2773 { 2774 SUBOPCODEA_MFXAVCSLICESTATE = 0, //!< No additional details 2775 }; 2776 2777 enum COMMAND_OPCODE 2778 { 2779 COMMAND_OPCODE_AVC = 1, //!< No additional details 2780 }; 2781 2782 enum PIPELINE 2783 { 2784 PIPELINE_MFXAVCSLICESTATE = 2, //!< No additional details 2785 }; 2786 2787 enum COMMAND_TYPE 2788 { 2789 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2790 }; 2791 2792 //! \brief SLICE_TYPE 2793 //! \details 2794 //! It is set to the value of the syntax element read from the Slice Header. 2795 enum SLICE_TYPE 2796 { 2797 SLICE_TYPE_PSLICE = 0, //!< No additional details 2798 SLICE_TYPE_BSLICE = 1, //!< No additional details 2799 SLICE_TYPE_ISLICE = 2, //!< No additional details 2800 }; 2801 2802 enum DISABLE_DEBLOCKING_FILTER_INDICATOR 2803 { 2804 DISABLE_DEBLOCKING_FILTER_INDICATOR_UNNAMED0 = 0, //!< FilterInternalEdgesFlag is set equal to 1 2805 DISABLE_DEBLOCKING_FILTER_INDICATOR_UNNAMED1 = 1, //!< Disable all deblocking operation, no deblocking parameter syntax element is read; filterInternalEdgesFlag is set equal to 0 2806 DISABLE_DEBLOCKING_FILTER_INDICATOR_UNNAMED2 = 2, //!< Macroblocks in different slices are considered not available; filterInternalEdgesFlag is set equal to 1 2807 }; 2808 2809 //! \brief DIRECT_PREDICTION_TYPE 2810 //! \details 2811 //! Type of direct prediction used for B Slices. This field is valid only 2812 //! for Slice_Type = B Slice; otherwise, it must be set to 0. 2813 enum DIRECT_PREDICTION_TYPE 2814 { 2815 DIRECT_PREDICTION_TYPE_TEMPORAL = 0, //!< No additional details 2816 DIRECT_PREDICTION_TYPE_SPATIAL = 1, //!< No additional details 2817 }; 2818 2819 //! \brief CABACZEROWORDINSERTIONENABLE 2820 //! \details 2821 //! To pad the end of a SliceLayer RBSP to meet the encoded size 2822 //! requirement. 2823 enum CABACZEROWORDINSERTIONENABLE 2824 { 2825 CABACZEROWORDINSERTIONENABLE_UNNAMED0 = 0, //!< No Cabac_Zero_Word Insertion 2826 CABACZEROWORDINSERTIONENABLE_UNNAMED1 = 1, //!< Allow internal Cabac_Zero_Word generation and append to the end of RBSP(effectively can be used as an indicator for last slice of a picture, if the assumption is only the last slice of a picture needs to insert CABAC_ZERO_WORDs. 2827 }; 2828 2829 //! \brief EMULATIONBYTESLICEINSERTENABLE 2830 //! \details 2831 //! To have PAK outputting SODB or EBSP to the output bitstream buffer 2832 enum EMULATIONBYTESLICEINSERTENABLE 2833 { 2834 EMULATIONBYTESLICEINSERTENABLE_UNNAMED0 = 0, //!< outputting RBSP 2835 EMULATIONBYTESLICEINSERTENABLE_UNNAMED1 = 1, //!< outputting EBSP 2836 }; 2837 2838 //! \brief TAIL_INSERTION_PRESENT_IN_BITSTREAM 2839 //! \details 2840 //! This bit should only be set for the last super slice. 2841 //! style="color: rgb(0, 0, 0); font-family: Arial, 2842 //! sans-serif; line-height: normal;">SKL Restriction: In VDENC mode, SW 2843 //! should insert 1000style="color: rgb(0, 0, 0); 2844 //! font-family: Arial, sans-serif; line-height: normal;">VD_PIPELINE_FLUSH 2845 //! commands with VDENC_pipeline_Done set to 1before inserting tail command. 2846 //! This is for delaying the tail insertion in HW. The HW recommendation is 2847 //! to insert tail only at the end of sequence to avoid performance loss 2848 //! since this restriction potentially cause performance degradation. 2849 //! 2850 enum TAIL_INSERTION_PRESENT_IN_BITSTREAM 2851 { 2852 TAIL_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED0 = 0, //!< No tail insertion into the output bitstream buffer, after the current slice encoded bits 2853 TAIL_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED1 = 1, //!< Tail insertion into the output bitstream buffer is present, and is after the current slice encoded bits. 2854 }; 2855 2856 //! \brief SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM 2857 //! \details 2858 //! This bit should be set for all super-slices. 2859 enum SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM 2860 { 2861 SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED0 = 0, //!< No Slice Data insertion into the output bitstream buffer 2862 SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED1 = 1, //!< Slice Data insertion into the output bitstream buffer is present. 2863 }; 2864 2865 //! \brief HEADER_INSERTION_PRESENT_IN_BITSTREAM 2866 //! \details 2867 //! Note: In VDEnc mode, the slice header PAK object maximum size is 25 DWs. 2868 enum HEADER_INSERTION_PRESENT_IN_BITSTREAM 2869 { 2870 HEADER_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED0 = 0, //!< No header insertion into the output bitstream buffer, in front of the current slice encoded bits. 2871 HEADER_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED1 = 1, //!< Header insertion into the output bitstream buffer is present, and is in front of the current slice encoded bits. 2872 }; 2873 2874 //! \brief COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG 2875 //! \details 2876 //! This field could be set to 1 only if LoadBitStreamPointerPerSlice is set 2877 //! to 1 as well, for debugging purpose. Otherwise when multiple slices are 2878 //! stitched together (with LoadBitStreamPointerPerSlice is set to 0), it 2879 //! doesn't make sense to disable bitstream output. 2880 enum COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG 2881 { 2882 COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENABLETHEWRITINGOFTHEOUTPUTCOMPRESSEDBITSTREAM = 0, //!< No additional details 2883 COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_DISABLETHEWRITINGOFTHEOUTPUTCOMPRESSEDBITSTREAM = 1, //!< See description above 2884 }; 2885 2886 //! \brief IS_LAST_SLICE 2887 //! \details 2888 //! It is used by the zero filling in the Minimum Frame Size test. 2889 enum IS_LAST_SLICE 2890 { 2891 IS_LAST_SLICE_UNNAMED0 = 0, //!< Current slice is NOT the last slice of a picture 2892 IS_LAST_SLICE_UNNAMED1 = 1, //!< Current slice is the last slice of a picture 2893 }; 2894 2895 //! \brief MB_TYPE_SKIP_CONVERSION_DISABLE 2896 //! \details 2897 //! For all Macroblock type conversions in different slices, refer to 2898 //! Section "Macroblock Type Conversion Rules" in the same volume. 2899 enum MB_TYPE_SKIP_CONVERSION_DISABLE 2900 { 2901 MB_TYPE_SKIP_CONVERSION_DISABLE_ENABLESKIPTYPECONVERSION = 0, //!< No additional details 2902 MB_TYPE_SKIP_CONVERSION_DISABLE_DISABLESKIPTYPECONVERSION = 1, //!< No additional details 2903 }; 2904 2905 //! \brief MB_TYPE_DIRECT_CONVERSION_DISABLE 2906 //! \details 2907 //! For all Macroblock type conversions in different slices, refer to 2908 //! Section "Macroblock Type Conversion Rules" in the same volume. 2909 enum MB_TYPE_DIRECT_CONVERSION_DISABLE 2910 { 2911 MB_TYPE_DIRECT_CONVERSION_DISABLE_ENABLEDIRECTMODECONVERSION = 0, //!< No additional details 2912 MB_TYPE_DIRECT_CONVERSION_DISABLE_DISABLEDIRECTMODECONVERSION = 1, //!< No additional details 2913 }; 2914 2915 //! \brief RC_PANIC_TYPE 2916 //! \details 2917 //! This field selects between two RC Panic methods 2918 enum RC_PANIC_TYPE 2919 { 2920 RC_PANIC_TYPE_QPPANIC = 0, //!< No additional details 2921 RC_PANIC_TYPE_CBPPANIC = 1, //!< No additional details 2922 }; 2923 2924 //! \brief RC_PANIC_ENABLE 2925 //! \details 2926 //! If this field is set to 1, RC enters panic mode when sum_act > 2927 //! sum_max. RC Panic Type field controls what type of panic behavior is 2928 //! invoked. 2929 enum RC_PANIC_ENABLE 2930 { 2931 RC_PANIC_ENABLE_DISABLE = 0, //!< No additional details 2932 RC_PANIC_ENABLE_ENABLE = 1, //!< No additional details 2933 }; 2934 2935 enum RC_TRIGGLE_MODE 2936 { 2937 RC_TRIGGLE_MODE_ALWAYSRATECONTROL = 0, //!< Whereas RC becomes active if sum_act > sum_target or sum_act < sum_target 2938 RC_TRIGGLE_MODE_GENTLERATECONTROL = 1, //!< whereas RC becomes active if sum_act > upper_midpt or sum_act < lower_midpt 2939 RC_TRIGGLE_MODE_LOOSERATECONTROL = 2, //!< whereas RC becomes active if sum_act > sum_max or sum_act < sum_min 2940 }; 2941 2942 //! \brief RESETRATECONTROLCOUNTER 2943 //! \details 2944 //! To reset the bit allocation accumulation counter to 0 to restart the 2945 //! rate control. 2946 enum RESETRATECONTROLCOUNTER 2947 { 2948 RESETRATECONTROLCOUNTER_NOTRESET = 0, //!< No additional details 2949 RESETRATECONTROLCOUNTER_RESET = 1, //!< No additional details 2950 }; 2951 2952 //! \brief RATE_CONTROL_COUNTER_ENABLE 2953 //! \details 2954 //! To enable the accumulation of bit allocation for rate controlThis field 2955 //! enables hardware Rate Control logic. The rest of the RC control fields 2956 //! are only valid when this field is set to 1. Otherwise, hardware ignores 2957 //! these fields. 2958 enum RATE_CONTROL_COUNTER_ENABLE 2959 { 2960 RATE_CONTROL_COUNTER_ENABLE_DISABLE = 0, //!< No additional details 2961 RATE_CONTROL_COUNTER_ENABLE_ENABLE = 1, //!< No additional details 2962 }; 2963 2964 //! \brief ROUNDINTRA 2965 //! \details 2966 //! Rounding precision for Intra quantized coefficients 2967 enum ROUNDINTRA 2968 { 2969 ROUNDINTRA_116 = 0, //!< No additional details 2970 ROUNDINTRA_216 = 1, //!< No additional details 2971 ROUNDINTRA_316 = 2, //!< No additional details 2972 ROUNDINTRA_416 = 3, //!< No additional details 2973 ROUNDINTRA_516 = 4, //!< No additional details 2974 ROUNDINTRA_616 = 5, //!< No additional details 2975 ROUNDINTRA_716 = 6, //!< No additional details 2976 ROUNDINTRA_816 = 7, //!< No additional details 2977 }; 2978 2979 //! \brief ROUNDINTER 2980 //! \details 2981 //! Rounding precision for Inter quantized coefficients 2982 enum ROUNDINTER 2983 { 2984 ROUNDINTER_116 = 0, //!< No additional details 2985 ROUNDINTER_216 = 1, //!< No additional details 2986 ROUNDINTER_316 = 2, //!< No additional details 2987 ROUNDINTER_416 = 3, //!< No additional details 2988 ROUNDINTER_516 = 4, //!< No additional details 2989 ROUNDINTER_616 = 5, //!< No additional details 2990 ROUNDINTER_716 = 6, //!< No additional details 2991 ROUNDINTER_816 = 7, //!< No additional details 2992 }; 2993 2994 //! \name Initializations 2995 2996 //! \brief Explicit member initialization function 2997 MFX_AVC_SLICE_STATE_CMD(); 2998 2999 static const size_t dwSize = 11; 3000 static const size_t byteSize = 44; 3001 }; 3002 3003 //! 3004 //! \brief MFD_AVC_DPB_STATE 3005 //! \details 3006 //! This is a frame level state command used only in AVC Short Slice 3007 //! Bitstream Format VLD mode.RefFrameList[16] of interface is replaced with 3008 //! intel Reference Picture Addresses[16] of MFX_PIPE_BUF_ADDR_STATE 3009 //! command. The LongTerm Picture flag indicator of all reference pictures 3010 //! are collected into LongTermPic_Flag[16].FieldOrderCntList[16][2] and 3011 //! CurrFieldOrderCnt[2] of interface are replaced with intel POCList[34] of 3012 //! MFX_AVC_DIRECTMODE_STATE command. 3013 //! 3014 struct MFD_AVC_DPB_STATE_CMD 3015 { 3016 union 3017 { 3018 struct 3019 { 3020 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 3021 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3022 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 3023 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 3024 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 3025 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3026 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3027 }; 3028 uint32_t Value; 3029 } DW0; 3030 union 3031 { 3032 struct 3033 { 3034 uint32_t NonExistingframeFlag161Bit : __CODEGEN_BITFIELD(0, 15); //!< NON_EXISTINGFRAME_FLAG161_BIT 3035 uint32_t LongtermframeFlag161Bit : __CODEGEN_BITFIELD(16, 31); //!< LONGTERMFRAME_FLAG161_BIT 3036 }; 3037 uint32_t Value; 3038 } DW1; 3039 union 3040 { 3041 struct 3042 { 3043 uint32_t UsedforreferenceFlag162Bits; //!< USEDFORREFERENCE_FLAG162_BITS 3044 }; 3045 uint32_t Value; 3046 } DW2; 3047 uint32_t Ltstframenumlist1616Bits[8]; //!< LTSTFRAMENUMLIST1616_BITS 3048 uint32_t Viewidlist1616Bits[8]; //!< ViewIDList[16][16 bits] 3049 uint32_t Vieworderlistl0168Bits[4]; //!< ViewOrderListL0[16][8 bits] 3050 uint32_t Vieworderlistl1168Bits[4]; //!< ViewOrderListL1[16][8 bits] 3051 3052 //! \name Local enumerations 3053 3054 enum SUBOPCODE_B 3055 { 3056 SUBOPCODE_B_UNNAMED6 = 6, //!< No additional details 3057 }; 3058 3059 enum SUBOPCODE_A 3060 { 3061 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 3062 }; 3063 3064 enum MEDIA_COMMAND_OPCODE 3065 { 3066 MEDIA_COMMAND_OPCODE_AVCDEC = 1, //!< No additional details 3067 }; 3068 3069 enum PIPELINE 3070 { 3071 PIPELINE_MFXMULTIDW = 2, //!< No additional details 3072 }; 3073 3074 enum COMMAND_TYPE 3075 { 3076 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3077 }; 3078 3079 //! \brief NON_EXISTINGFRAME_FLAG161_BIT 3080 //! \details 3081 //! One-to-one correspondence with the entries of the Intel 3082 //! RefFrameList[16]. 1 bit per reference frame. 3083 enum NON_EXISTINGFRAME_FLAG161_BIT 3084 { 3085 NON_EXISTINGFRAME_FLAG161_BIT_VALID = 0, //!< the reference picture in that entry of RefFrameList[] is a valid reference 3086 NON_EXISTINGFRAME_FLAG161_BIT_INVALID = 1, //!< the reference picture in that entry of RefFrameList[] does not exist anymore. 3087 }; 3088 3089 //! \brief LONGTERMFRAME_FLAG161_BIT 3090 //! \details 3091 //! One-to-one correspondence with the entries of the Intel 3092 //! RefFrameList[16]. 1 bit per reference frame. 3093 enum LONGTERMFRAME_FLAG161_BIT 3094 { 3095 LONGTERMFRAME_FLAG161_BIT_THEPICTUREISASHORTTERMREFERENCEPICTURE = 0, //!< No additional details 3096 LONGTERMFRAME_FLAG161_BIT_THEPICTUREISALONGTERMREFERENCEPICTURE = 1, //!< No additional details 3097 }; 3098 3099 //! \brief USEDFORREFERENCE_FLAG162_BITS 3100 //! \details 3101 //! One-to-one correspondence with the entries of the Intel 3102 //! RefFrameList[16]. 2 bits per reference frame. 3103 enum USEDFORREFERENCE_FLAG162_BITS 3104 { 3105 USEDFORREFERENCE_FLAG162_BITS_NOTREFERENCE = 0, //!< indicates a frame is "not used for reference". 3106 USEDFORREFERENCE_FLAG162_BITS_TOPFIELD = 1, //!< bit[0] indicates that the top field of a frame is marked as "used for reference". 3107 USEDFORREFERENCE_FLAG162_BITS_BOTTOMFIELD = 2, //!< bit[1] indicates that the bottom field of a frame is marked as "used for reference". 3108 USEDFORREFERENCE_FLAG162_BITS_FRAME = 3, //!< bit[1:0] indicates that a frame (or field pair) is marked as "used for reference". 3109 }; 3110 3111 //! \brief LTSTFRAMENUMLIST1616_BITS 3112 //! \details 3113 //! One-to-one correspondence with the entries of the Intel 3114 //! RefFrameList[16]. 16 bits per reference frame.Depending on the 3115 //! corresponding LongTermFrame_Flag[], the content of this field is 3116 //! interpreted differently. 3117 enum LTSTFRAMENUMLIST1616_BITS 3118 { 3119 LTSTFRAMENUMLIST1616_BITS_SHORTTERMFRAMEFLAGI = 0, //!< LTSTFrameNumList[i]represent Short Term Picture FrameNum. 3120 LTSTFRAMENUMLIST1616_BITS_LONGTERMFRAMEFLAGI = 1, //!< LTSTFrameNumList[i] represent LongTermFrameIdx. 3121 }; 3122 3123 //! \name Initializations 3124 3125 //! \brief Explicit member initialization function 3126 MFD_AVC_DPB_STATE_CMD(); 3127 3128 static const size_t dwSize = 27; 3129 static const size_t byteSize = 108; 3130 }; 3131 3132 //! 3133 //! \brief MFD_AVC_SLICEADDR 3134 //! \details 3135 //! This is a Slice level command used only for AVC Short Slice Bitstream 3136 //! Format VLD mode.When decoding a slice, H/W needs to know the last MB of 3137 //! the slice has reached in order to start decoding the next slice. It also 3138 //! needs to know if a slice is terminated but the last MB has not reached, 3139 //! error conealment should be invoked to generate those missing MBs. For 3140 //! AVC Short Format, the only way to know the last MB position of the 3141 //! current slice, H/W needs to snoop into the next slice's start MB address 3142 //! (a linear address encoded in the Slice Header). Since each BSD Object 3143 //! command can have only one indirect bitstream buffer address, this 3144 //! command is added to help H/W to snoop into the next slice's slice header 3145 //! and retrieve its Start MB Address. This command will take the next 3146 //! slice's bitstream buffer address as input (exactly the same way as a BSD 3147 //! Object command), and parse only the first_mb_in_slice syntax element. 3148 //! The result will stored inside the H/W, and will be used to decode the 3149 //! current slice specified in the BSD Object command.Only the very first 3150 //! few bytes (max 5 bytes for a max 4K picture) of the Slice Header will be 3151 //! decoded, the rest of the bitstream are don't care. This is because the 3152 //! first_mb_in_slice is encoded in Exponential Golomb, and will take 33 3153 //! bits to represent the max 256 x 256 = 64K-1 value. The indirect data of 3154 //! MFD_AVC_SLICEADDR is a valid BSD object and is decoded as in BSD OBJECT 3155 //! command.The next Slice Start MB Address is also exposed to the MMIO 3156 //! interface.The Slice Start MB Address (first_mb_in_slice) is a linear MB 3157 //! address count; but it is translated into the corresponding 2D MB X and Y 3158 //! raster position, and are stored internally as NextSliceMbY and 3159 //! NextSliceMbX. 3160 //! 3161 struct MFD_AVC_SLICEADDR_CMD 3162 { 3163 union 3164 { 3165 struct 3166 { 3167 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 3168 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3169 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 3170 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 3171 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 3172 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3173 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3174 }; 3175 uint32_t Value; 3176 } DW0; 3177 union 3178 { 3179 struct 3180 { 3181 uint32_t IndirectBsdDataLength; //!< Indirect BSD Data Length 3182 }; 3183 uint32_t Value; 3184 } DW1; 3185 union 3186 { 3187 struct 3188 { 3189 uint32_t IndirectBsdDataStartAddress : __CODEGEN_BITFIELD(0, 28); //!< INDIRECT_BSD_DATA_START_ADDRESS 3190 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 3191 }; 3192 uint32_t Value; 3193 } DW2; 3194 union 3195 { 3196 struct 3197 { 3198 uint32_t DriverProvidedNalTypeValue : __CODEGEN_BITFIELD(0, 7); //!< Driver Provided NAL Type Value 3199 uint32_t AvcNalTypeFirstByteOverrideBit : __CODEGEN_BITFIELD(8, 8); //!< AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3200 uint32_t Reserved105 : __CODEGEN_BITFIELD(9, 12); //!< Reserved 3201 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 31); //!< Reserved 3202 }; 3203 uint32_t Value; 3204 } DW3; 3205 3206 //! \name Local enumerations 3207 3208 enum SUBOPCODE_B 3209 { 3210 SUBOPCODE_B_UNNAMED7 = 7, //!< No additional details 3211 }; 3212 3213 enum SUBOPCODE_A 3214 { 3215 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 3216 }; 3217 3218 enum MEDIA_COMMAND_OPCODE 3219 { 3220 MEDIA_COMMAND_OPCODE_AVCDEC = 1, //!< No additional details 3221 }; 3222 3223 enum PIPELINE 3224 { 3225 PIPELINE_MFDAVCSLICEADDR = 2, //!< No additional details 3226 }; 3227 3228 enum COMMAND_TYPE 3229 { 3230 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3231 }; 3232 3233 //! \brief INDIRECT_BSD_DATA_START_ADDRESS 3234 //! \details 3235 //! This field specifies the Graphics Memory starting address of the data 3236 //! to be fetched into BSD Unit for processing. This pointer is relative to 3237 //! the MFD Indirect Object Base Address.Hardware ignores this field if 3238 //! indirect data is not present. It is a byte-aligned address for the AVC 3239 //! bitstream data in both CABAC/CAVLD Modes.In implementing a phantom slice 3240 //! at the end of a picture for automatic error concealment, this field 3241 //! should set to 0.It includes the NAL Header Byte. (but does not perform 3242 //! EMU detection).Must provide a valid MB address, even if error. MB must 3243 //! be clamped to within a pic boundary. 3244 enum INDIRECT_BSD_DATA_START_ADDRESS 3245 { 3246 INDIRECT_BSD_DATA_START_ADDRESS_UNNAMED0 = 0, //!< No additional details 3247 INDIRECT_BSD_DATA_START_ADDRESS_UNNAMED512 = 512, //!< No additional details 3248 }; 3249 3250 //! \brief AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3251 //! \details 3252 //! This bit indicates hardware should use the NAL Type (provided below) 3253 //! programmed by driver instead of using the one from bitstream. The NAL 3254 //! byte from bitstream will not be correct. 3255 enum AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3256 { 3257 AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT_USEBITSTREAMDECODEDNALTYPE = 0, //!< NAL Type should come from first byte of decoded bitstream. 3258 AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT_USEDRIVERPROGRAMMEDNALTYPE = 1, //!< NAL Type should come from "Driver Provided NAL Type Values" programmed by driver. 3259 }; 3260 3261 //! \name Initializations 3262 3263 //! \brief Explicit member initialization function 3264 MFD_AVC_SLICEADDR_CMD(); 3265 3266 static const size_t dwSize = 4; 3267 static const size_t byteSize = 16; 3268 }; 3269 3270 //! 3271 //! \brief MFD_AVC_BSD_OBJECT 3272 //! \details 3273 //! The MFD_AVC_BSD_OBJECT command is the only primitive command for the AVC 3274 //! Decoding Pipeline. The same command is used for both CABAC and CAVLD 3275 //! modes. The Slice Data portion of the bitstream is loaded as indirect 3276 //! data object.Before issuing a MFD_AVC_BSD_OBJECT command, all AVC states 3277 //! of the MFD Engine need to be valid. Therefore the commands used to set 3278 //! these states need to have been issued prior to the issue of a 3279 //! MFD_AVC_BSD_OBJECT command. 3280 //! 3281 //! Context switch interrupt is not supported by this command. 3282 //! 3283 struct MFD_AVC_BSD_OBJECT_CMD 3284 { 3285 union 3286 { 3287 struct 3288 { 3289 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 3290 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3291 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 3292 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 3293 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 3294 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3295 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3296 }; 3297 uint32_t Value; 3298 } DW0; 3299 union 3300 { 3301 struct 3302 { 3303 uint32_t IndirectBsdDataLength; //!< Indirect BSD Data Length 3304 }; 3305 uint32_t Value; 3306 } DW1; 3307 union 3308 { 3309 struct 3310 { 3311 uint32_t IndirectBsdDataStartAddress : __CODEGEN_BITFIELD(0, 28); //!< INDIRECT_BSD_DATA_START_ADDRESS 3312 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 3313 }; 3314 uint32_t Value; 3315 } DW2; 3316 union 3317 { 3318 struct 3319 { 3320 uint32_t MbErrorConcealmentPSliceWeightPredictionDisableFlag : __CODEGEN_BITFIELD(0, 0); //!< MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG 3321 uint32_t MbErrorConcealmentPSliceMotionVectorsOverrideDisableFlag : __CODEGEN_BITFIELD(1, 1); //!< MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3322 uint32_t Reserved98 : __CODEGEN_BITFIELD(2, 2); //!< Reserved 3323 uint32_t MbErrorConcealmentBSpatialWeightPredictionDisableFlag : __CODEGEN_BITFIELD(3, 3); //!< MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG 3324 uint32_t MbErrorConcealmentBSpatialMotionVectorsOverrideDisableFlag : __CODEGEN_BITFIELD(4, 4); //!< MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3325 uint32_t Reserved101 : __CODEGEN_BITFIELD(5, 5); //!< Reserved 3326 uint32_t MbErrorConcealmentBSpatialPredictionMode : __CODEGEN_BITFIELD(6, 7); //!< MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_ 3327 uint32_t MbHeaderErrorHandling : __CODEGEN_BITFIELD(8, 8); //!< MB_HEADER_ERROR_HANDLING_ 3328 uint32_t Reserved105 : __CODEGEN_BITFIELD(9, 9); //!< Reserved 3329 uint32_t EntropyErrorHandling : __CODEGEN_BITFIELD(10, 10); //!< ENTROPY_ERROR_HANDLING 3330 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 3331 uint32_t MprErrorMvOutOfRangeHandling : __CODEGEN_BITFIELD(12, 12); //!< MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 3332 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 13); //!< Reserved 3333 uint32_t BsdPrematureCompleteErrorHandling : __CODEGEN_BITFIELD(14, 14); //!< BSD_PREMATURE_COMPLETE_ERROR_HANDLING 3334 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 3335 uint32_t ConcealmentPictureId : __CODEGEN_BITFIELD(16, 21); //!< Concealment Picture ID 3336 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 3337 uint32_t MbErrorConcealmentBTemporalWeightPredictionDisableFlag : __CODEGEN_BITFIELD(24, 24); //!< MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG 3338 uint32_t MbErrorConcealmentBTemporalMotionVectorsOverrideEnableFlag : __CODEGEN_BITFIELD(25, 25); //!< MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG 3339 uint32_t Reserved122 : __CODEGEN_BITFIELD(26, 26); //!< Reserved 3340 uint32_t MbErrorConcealmentBTemporalPredictionMode : __CODEGEN_BITFIELD(27, 28); //!< MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE 3341 uint32_t IntraPredmode4X48X8LumaErrorControlBit : __CODEGEN_BITFIELD(29, 29); //!< INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT 3342 uint32_t InitCurrentMbNumber : __CODEGEN_BITFIELD(30, 30); //!< Init Current MB Number 3343 uint32_t ConcealmentMethod : __CODEGEN_BITFIELD(31, 31); //!< CONCEALMENT_METHOD 3344 }; 3345 uint32_t Value; 3346 } DW3; 3347 union 3348 { 3349 struct 3350 { 3351 uint32_t FirstMacroblockMbBitOffset : __CODEGEN_BITFIELD(0, 2); //!< First Macroblock (MB)Bit Offset 3352 uint32_t LastsliceFlag : __CODEGEN_BITFIELD(3, 3); //!< LASTSLICE_FLAG 3353 uint32_t EmulationPreventionBytePresent : __CODEGEN_BITFIELD(4, 4); //!< EMULATION_PREVENTION_BYTE_PRESENT 3354 uint32_t Reserved133 : __CODEGEN_BITFIELD(5, 6); //!< Reserved 3355 uint32_t FixPrevMbSkipped : __CODEGEN_BITFIELD(7, 7); //!< Fix Prev Mb Skipped 3356 uint32_t Reserved136 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 3357 uint32_t FirstMbByteOffsetOfSliceDataOrSliceHeader : __CODEGEN_BITFIELD(16, 31); //!< First MB Byte Offset of Slice Data or Slice Header 3358 }; 3359 uint32_t Value; 3360 } DW4; 3361 union 3362 { 3363 struct 3364 { 3365 uint32_t IntraPredictionErrorControlBitAppliedToIntra16X16Intra8X8Intra4X4LumaAndChroma : __CODEGEN_BITFIELD(0, 0); //!< INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA 3366 uint32_t Intra8X84X4PredictionErrorConcealmentControlBit : __CODEGEN_BITFIELD(1, 1); //!< INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT 3367 uint32_t Reserved162 : __CODEGEN_BITFIELD(2, 3); //!< Reserved 3368 uint32_t BSliceTemporalInterConcealmentMode : __CODEGEN_BITFIELD(4, 6); //!< B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE 3369 uint32_t Reserved167 : __CODEGEN_BITFIELD(7, 7); //!< Reserved 3370 uint32_t BSliceSpatialInterConcealmentMode : __CODEGEN_BITFIELD(8, 10); //!< B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE 3371 uint32_t Reserved171 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 3372 uint32_t BSliceInterDirectTypeConcealmentMode : __CODEGEN_BITFIELD(12, 13); //!< B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE 3373 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 14); //!< Reserved 3374 uint32_t BSliceConcealmentMode : __CODEGEN_BITFIELD(15, 15); //!< B_SLICE_CONCEALMENT_MODE 3375 uint32_t PSliceInterConcealmentMode : __CODEGEN_BITFIELD(16, 18); //!< P_SLICE_INTER_CONCEALMENT_MODE 3376 uint32_t Reserved179 : __CODEGEN_BITFIELD(19, 22); //!< Reserved 3377 uint32_t PSliceConcealmentMode : __CODEGEN_BITFIELD(23, 23); //!< P_SLICE_CONCEALMENT_MODE 3378 uint32_t ConcealmentReferencePictureFieldBit : __CODEGEN_BITFIELD(24, 29); //!< Concealment Reference Picture + Field Bit 3379 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 30); //!< Reserved 3380 uint32_t ISliceConcealmentMode : __CODEGEN_BITFIELD(31, 31); //!< I_SLICE_CONCEALMENT_MODE 3381 }; 3382 uint32_t Value; 3383 } DW5; 3384 union 3385 { 3386 struct 3387 { 3388 uint32_t Reserved192; //!< Reserved 3389 }; 3390 uint32_t Value; 3391 } DW6; 3392 3393 //! \name Local enumerations 3394 3395 enum SUBOPCODE_B 3396 { 3397 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 3398 }; 3399 3400 enum SUBOPCODE_A 3401 { 3402 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 3403 }; 3404 3405 enum MEDIA_COMMAND_OPCODE 3406 { 3407 MEDIA_COMMAND_OPCODE_AVCDEC = 1, //!< No additional details 3408 }; 3409 3410 enum PIPELINE 3411 { 3412 PIPELINE_MFDAVCBSDOBJECT = 2, //!< No additional details 3413 }; 3414 3415 enum COMMAND_TYPE 3416 { 3417 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3418 }; 3419 3420 //! \brief INDIRECT_BSD_DATA_START_ADDRESS 3421 //! \details 3422 //! This field specifies the Graphics Memory starting address of the data 3423 //! to be fetched into BSD Unit for processing. This pointer is relative to 3424 //! the MFD Indirect Object Base Address. Hardware ignores this 3425 //! field if indirect data is not present. It is a byte-aligned address for 3426 //! the AVC bitstream data in both CABAC/CAVLD Modes. In implementing a 3427 //! phantom slice at the end of a picture for automatic error concealment, 3428 //! this field should set to 0. It includes the NAL Header (the NAL Header 3429 //! does not need to perform EMU detection). For AVC and SVC Base Layer, it 3430 //! is a single byte. But for SVC and MVC, the NAL Header is 4 Bytes long. 3431 //! These NAL Header Unit must be passed to HW in the compressed bitstream 3432 //! buffer. 3433 enum INDIRECT_BSD_DATA_START_ADDRESS 3434 { 3435 INDIRECT_BSD_DATA_START_ADDRESS_UNNAMED0 = 0, //!< No additional details 3436 INDIRECT_BSD_DATA_START_ADDRESS_UNNAMED512 = 512, //!< No additional details 3437 }; 3438 3439 //! \brief MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG 3440 //! \details 3441 //! During MB Error Concealment on P slice, weight prediction is disabled to 3442 //! improve image quality.This bit can be set to preserve the original 3443 //! weight prediction. This bit does not affect normal decoded MB. 3444 enum MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG 3445 { 3446 MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED0 = 0, //!< Weight Prediction is Disabled during MB Concealment. 3447 MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED1 = 1, //!< Weight Prediction will not be overridden during MB Concealment. 3448 }; 3449 3450 //! \brief MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3451 //! \details 3452 //! During MB Error Concealment on P slice, motion vectors are forced to 0 3453 //! to improve image quality. This bit can be set to use the predicted 3454 //! motion vectors instead. This bit does not affect normal decoded MB. 3455 enum MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3456 { 3457 MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED0 = 0, //!< Motion Vectors are Overridden to 0 during MB Concealment 3458 MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED1 = 1, //!< Predicted Motion Vectors are used during MB Concealment 3459 }; 3460 3461 //! \brief MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG 3462 //! \details 3463 //! During MB Error Concealment on B slice with Spatial Direct Prediction, 3464 //! weight prediction is disabled to improve image quality.This bit can be 3465 //! set to preserve the original weight prediction. This bit does not 3466 //! affect normal decoded MB. 3467 enum MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG 3468 { 3469 MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED0 = 0, //!< Weight Prediction is Disabled during MB Concealment. 3470 MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED1 = 1, //!< Weight Prediction will not be overridden during MB Concealment. 3471 }; 3472 3473 //! \brief MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3474 //! \details 3475 //! During MB Error Concealment on B slice with Spatial Direct Prediction, 3476 //! motion vectors are forced to 0 to improve image quality. This bit can be 3477 //! set to use the predicted motion vectors instead. This bit does not 3478 //! affect normal decoded MB. 3479 enum MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3480 { 3481 MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED0 = 0, //!< Motion Vectors are Overridden to 0 during MB Concealment 3482 MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED1 = 1, //!< Predicted Motion Vectors are used during MB Concealment 3483 }; 3484 3485 //! \brief MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_ 3486 //! \details 3487 //! These two bits control how the reference L0/L1 are overridden in B 3488 //! spatial slice. 3489 enum MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_ 3490 { 3491 MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_UNNAMED0 = 0, //!< Both Reference Indexes L0/L1 are forced to 0 during Concealment 3492 MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_UNNAMED1 = 1, //!< Only Reference Index L1 is forced to 0; Reference Index L0 is forced to -1 3493 MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_UNNAMED2 = 2, //!< Only Reference Index L0 is forced to 0; Reference Index L1 is forced to -1 3494 }; 3495 3496 //! \brief MB_HEADER_ERROR_HANDLING_ 3497 //! \details 3498 //! Software must follow the action for each Value as follow: 3499 enum MB_HEADER_ERROR_HANDLING_ 3500 { 3501 MB_HEADER_ERROR_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically perform the error concealment. 3502 MB_HEADER_ERROR_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W). 3503 }; 3504 3505 //! \brief ENTROPY_ERROR_HANDLING 3506 //! \details 3507 //! Software must follow the action for each Value as follow: 3508 enum ENTROPY_ERROR_HANDLING 3509 { 3510 ENTROPY_ERROR_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically perform the error handling. 3511 ENTROPY_ERROR_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W). 3512 }; 3513 3514 //! \brief MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 3515 //! \details 3516 //! Software must follow the action for each Value as follow: 3517 enum MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 3518 { 3519 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically performs the error handling 3520 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W) 3521 }; 3522 3523 //! \brief BSD_PREMATURE_COMPLETE_ERROR_HANDLING 3524 //! \details 3525 //! BSD Premature Complete Error occurs in situation where the Slice decode 3526 //! is completed but there are still data in the bitstream. 3527 enum BSD_PREMATURE_COMPLETE_ERROR_HANDLING 3528 { 3529 BSD_PREMATURE_COMPLETE_ERROR_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically performs the error handling 3530 BSD_PREMATURE_COMPLETE_ERROR_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W) 3531 }; 3532 3533 //! \brief MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG 3534 //! \details 3535 //! During MB Error Concealment on B slice with Temporal Direct Prediction, 3536 //! weight prediction is disabled to improve image quality.This bit can be 3537 //! set to preserve the original weight prediction. 3538 enum MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG 3539 { 3540 MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED0 = 0, //!< Weight Prediction is Disabled during MB Concealment 3541 MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED1 = 1, //!< Weight Prediction will not be overridden during MB Concealment 3542 }; 3543 3544 //! \brief MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG 3545 //! \details 3546 //! During MB Error Concealment on B slice with Temporal Direct Prediction, 3547 //! motion vectors are forced to 0 to improve image quality.This bit can be 3548 //! set to preserve the original weight prediction. 3549 enum MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG 3550 { 3551 MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG_UNNAMED0 = 0, //!< Predicted Motion Vectors are used during MB Concealment 3552 MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG_UNNAMED1 = 1, //!< Motion Vectors are Overridden to 0 during MB Concealment 3553 }; 3554 3555 //! \brief MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE 3556 //! \details 3557 //! These two bits control how the reference L0/L1 are overridden in B 3558 //! temporal slice. 3559 enum MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE 3560 { 3561 MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE_UNNAMED0 = 0, //!< Both Reference Indexes L0/L1 are forced to 0 during Concealment 3562 MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE_UNNAMED1 = 1, //!< Only Reference Index L1 is forced to 0; Reference Index L0 is forced to -1 3563 MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE_UNNAMED2 = 2, //!< Only Reference Index L0 is forced to 0; Reference Index L1 is forced to -1 3564 }; 3565 3566 //! \brief INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT 3567 //! \details 3568 //! This field controls if AVC decoder will fix Intra Prediction Mode if the 3569 //! decoded value is incorrect according to MB position 3570 enum INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT 3571 { 3572 INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT_UNNAMED0 = 0, //!< AVC decoder will detect and fix IntraPredMode (4x4/8x8 Luma) Errors. 3573 INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT_UNNAMED1 = 1, //!< AVC decoder will NOT detect IntraPredMode (4x4/8x8 Luma) Errors. The wrong IntraPredMode value will be retaind. 3574 }; 3575 3576 //! \brief CONCEALMENT_METHOD 3577 //! \details 3578 //! This field specifies the method used for concealment when error is 3579 //! detected. If set, a copy from collocated macroblock location is 3580 //! performed from the concealment reference indicated by the ConCeal_Pic_Id 3581 //! field. If it is not set, a copy from the current picture is performed 3582 //! using Intra 16x16 Prediction method. 3583 enum CONCEALMENT_METHOD 3584 { 3585 CONCEALMENT_METHOD_UNNAMED0 = 0, //!< Intra 16x16 Prediction 3586 CONCEALMENT_METHOD_UNNAMED1 = 1, //!< Inter P Copy 3587 }; 3588 3589 //! \brief LASTSLICE_FLAG 3590 //! \details 3591 //! It is needed for both error concealment at the end of a picture (so, no 3592 //! more phantom slice as in DevSNB). It is also needed to know to set the 3593 //! last MB in a picture correctly. 3594 enum LASTSLICE_FLAG 3595 { 3596 LASTSLICE_FLAG_UNNAMED0 = 0, //!< If the current Slice to be decoded is any slice other than the very last slice of the current picture 3597 LASTSLICE_FLAG_UNNAMED1 = 1, //!< If the current Slice to be decoded is the very last slice of the current picture. 3598 }; 3599 3600 enum EMULATION_PREVENTION_BYTE_PRESENT 3601 { 3602 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED0 = 0, //!< H/W needs to perform Emulation Byte Removal 3603 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED1 = 1, //!< H/W does not need to perform Emulation Byte Removal 3604 }; 3605 3606 //! \brief INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA 3607 //! \details 3608 //! This field controls if AVC decoder will fix Intra Prediction Mode if the 3609 //! decoded value is incorrect according to MB position. 3610 enum INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA 3611 { 3612 INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA_UNNAMED0 = 0, //!< AVC decoder will detect and fix Intra Prediction Mode Errors. 3613 INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA_UNNAMED1 = 1, //!< AVC decoder will retain the Intra Prediction value decoded from bitstream. 3614 }; 3615 3616 //! \brief INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT 3617 //! \details 3618 //! This field controls if AVC goes into MB concealment mode (next MB) when 3619 //! an error is detected on Intra8x8/4x4 Prediction Mode (these 2 modes have 3620 //! fixed coding so it may not affect the bitstream. 3621 enum INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT 3622 { 3623 INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT_UNNAMED0 = 0, //!< AVC decoder will NOT go into MB concealment when Intra8x8/4x4 Prediction mode is incorrect. 3624 INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT_UNNAMED1 = 1, //!< AVC decoder will go into MB concealment when Intra8x8/4x4 Prediction mode is incorrect. 3625 }; 3626 3627 //! \brief B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE 3628 //! \details 3629 //! This field controls how AVC decoder select reference picture for 3630 //! Temporal Inter Concealment in B Slice 3631 enum B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE 3632 { 3633 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Top of Reference List L0/L1 (Use top entry of Reference List L0/L1) 3634 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Driver Specified Concealment Reference 3635 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED2 = 2, //!< Predicted Reference (Use reference picture predicted using B-Skip Algorithm) 3636 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED3 = 3, //!< " Temporal Closest (Using POC to select the closest forward picture)[For L0: Closest POC smaller than current POC][For L1: Closest POC larger than current POC] 3637 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED4 = 4, //!< First Long Term Picture in Reference List L0/L1(If no long term picture available, use Temporal Closest Picture) 3638 }; 3639 3640 //! \brief B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE 3641 //! \details 3642 //! This field controls how AVC decoder select reference picture for Spatial 3643 //! Inter Concealment in B Slice. 3644 enum B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE 3645 { 3646 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Top of Reference List L0/L1 (Use top entry of Reference List L0/L1). 3647 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Driver Specified Concealment Reference 3648 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED3 = 3, //!< Temporal Closest (Using POC to select the closest forward picture)[For L0: Closest POC smaller than current POC][For L1: Closest POC larger than current POC] 3649 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED4 = 4, //!< " First Long Term Picture in Reference List L0/L1 (If no long term picture available, use Temporal Closest Picture) 3650 }; 3651 3652 //! \brief B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE 3653 //! \details 3654 //! AVC decoder can use Spatial or Temporal Direct for B Skip/Direct. This 3655 //! field determine can override the mode on how AVC decoder handles MB 3656 //! concealment in B slice. 3657 enum B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE 3658 { 3659 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Use Default Direct Type (slice programmed direct type) 3660 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Forced to Spatial Direct Only 3661 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED2 = 2, //!< Forced to Temporal Direct Only 3662 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED3 = 3, //!< Spatial Direct without Temporal Componenet (MovingBlock information) 3663 }; 3664 3665 //! \brief B_SLICE_CONCEALMENT_MODE 3666 //! \details 3667 //! This field controls how AVC decoder handle MB concealment in B Slice 3668 enum B_SLICE_CONCEALMENT_MODE 3669 { 3670 B_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 0, //!< No additional details 3671 B_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 1, //!< No additional details 3672 }; 3673 3674 //! \brief P_SLICE_INTER_CONCEALMENT_MODE 3675 //! \details 3676 //! This field controls how AVC decoder select reference picture for 3677 //! Concealment in P Slice. 3678 enum P_SLICE_INTER_CONCEALMENT_MODE 3679 { 3680 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Top of Reference List L0 (Use top entry of Reference List L0) 3681 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Driver Specified Concealment Reference 3682 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED2 = 2, //!< Predicted Reference (Use reference picture predicted using P-Skip Algorithm) 3683 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED3 = 3, //!< Temporal Closest (Using POC to select the closest forward picture)[For L0: Closest POC smaller than current POC] 3684 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED4 = 4, //!< First Long Term Picture in Reference List L0 (If no long term picture available, use Temporal Closest Picture) 3685 }; 3686 3687 //! \brief P_SLICE_CONCEALMENT_MODE 3688 //! \details 3689 //! This field controls how AVC decoder handle MB concealment in P Slice 3690 enum P_SLICE_CONCEALMENT_MODE 3691 { 3692 P_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 0, //!< No additional details 3693 P_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 1, //!< No additional details 3694 }; 3695 3696 //! \brief I_SLICE_CONCEALMENT_MODE 3697 //! \details 3698 //! This field controls how AVC decoder handle MB concealment in I Slice 3699 enum I_SLICE_CONCEALMENT_MODE 3700 { 3701 I_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 0, //!< No additional details 3702 I_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 1, //!< No additional details 3703 }; 3704 3705 //! \name Initializations 3706 3707 //! \brief Explicit member initialization function 3708 MFD_AVC_BSD_OBJECT_CMD(); 3709 3710 static const size_t dwSize = 7; 3711 static const size_t byteSize = 28; 3712 }; 3713 3714 //! 3715 //! \brief MFX_PAK_INSERT_OBJECT 3716 //! \details 3717 //! The MFX_PAK_INSERT_OBJECT command is the first primitive command for the 3718 //! AVC, MPEG2, JPEG, SVC and VP8 Encoding Pipeline. 3719 //! 3720 //! This command is issued to setup the control and parameters of inserting 3721 //! a chunk of compressed/encoded bits into the current bitstream output 3722 //! buffer starting at the specified bit locationto perform the actual 3723 //! insertion by transferring the command inline data to the output buffer 3724 //! max, 32 bits at a time.It is a variable length command as the data to be 3725 //! inserted are presented as inline data of this command. It is a multiple 3726 //! of 32-bit (1 DW), as the data bus to the bitstream buffer is 32-bit 3727 //! wide.Multiple insertion commands can be issued back to back in a series. 3728 //! It is host software's responsibility to make sure their corresponding 3729 //! data will properly stitch together to form a valid H.264 3730 //! bitstream.Internally, MFX hardware will keep track of the very last two 3731 //! bytes' (the very last byte can be a partial byte) values of the previous 3732 //! insertion. It is required that the next Insertion Object Command or the 3733 //! next PAK Object Command to perform the start code emulation sequence 3734 //! check and prevention 0x03 byte insertion with this end condition of the 3735 //! previous insertion.Hardware will keep track of an output bitstream 3736 //! buffer current byte position and the associated next bit insertion 3737 //! position index. Data to be inserted can be a valid H.264 NAL units or a 3738 //! partial NAL unit. Certain NAL unit has a minimum byte size requirement. 3739 //! As such the hardware will optionally (enabled by STATE Command) 3740 //! determines the number of CABAC_ZERO_WORD to be inserted to the end of 3741 //! the current NAL, based on the minimum byte size of a NAL and the actual 3742 //! bin count of the encoded Slice. Since prior to the CABAC_ZERO_WORD 3743 //! insertion, the RBSP or EBSP is already byte-aligned, so each 3744 //! CABAC_ZERO_WORD insertion is actually a 3-byte sequence 0x00 00 03. The 3745 //! inline data may have already been processed for start code emulation 3746 //! byte insertion, except the possibility of the last 2 bytes plus the very 3747 //! last partial byte (if any). Hence, when hardware performing the 3748 //! concatenation of multiple consecutive insertion commands, or 3749 //! concatenation of an insertion command and a PAK object command, it must 3750 //! check and perform the necessary start code emulation byte insert at the 3751 //! junction.The inline data is required to be byte aligned on the left 3752 //! (first transmitted bit order) and may or may not be byte aligned on the 3753 //! right (last transmitted bits). The command will specify the bit offset 3754 //! of the last valid DW.Each insertion state command defines a chunk of 3755 //! bits (compressed data) to be inserted at a specific location of the 3756 //! output compressed bitstream in the output buffer.Depend on CABAC or 3757 //! CAVLC encoding mode (from Slice State), PAK Object Command is always 3758 //! ended in byte aligned output bitstream except for CABAC header insertion 3759 //! which is bit aligned. In the aligned cases, PAK will perform 0 filling 3760 //! in CAVLC mode, and 1 filling in CABAC mode.Insertion data can 3761 //! include:any encoded syntax elements bit data before the encoded Slice 3762 //! Data (PAK Object Command) of the current SliceSPS NALPPS NALSEI NALOther 3763 //! Non-Slice NALLeading_Zero_8_bits (as many bytes as there is)Start Code 3764 //! PrefixNAL Header ByteSlice HeaderAny encoded syntax elements bit data 3765 //! after the encoded Slice Data (PAK Object Command) of the current Slice 3766 //! and prior to the next encoded Slice Data of the next Slice or prior to 3767 //! the end of the bistream, whichever comes firstCabac_Zero_Word or 3768 //! Trailing_Zero_8bits (as many bytes as there is).Anything listed above 3769 //! before a Slice DataContext switch interrupt is not supported by this 3770 //! command. 3771 //! 3772 struct MFX_PAK_INSERT_OBJECT_CMD 3773 { 3774 union 3775 { 3776 struct 3777 { 3778 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWord Length 3779 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3780 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 3781 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 3782 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 3783 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3784 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3785 }; 3786 uint32_t Value; 3787 } DW0; 3788 union 3789 { 3790 struct 3791 { 3792 uint32_t BitstreamstartresetResetbitstreamstartingpos : __CODEGEN_BITFIELD(0, 0); //!< BITSTREAMSTARTRESET_RESETBITSTREAMSTARTINGPOS 3793 uint32_t EndofsliceflagLastdstdatainsertcommandflag : __CODEGEN_BITFIELD(1, 1); //!< EndOfSliceFlag - LastDstDataInsertCommandFlag 3794 uint32_t LastheaderflagLastsrcheaderdatainsertcommandflag : __CODEGEN_BITFIELD(2, 2); //!< LastHeaderFlag - LastSrcHeaderDataInsertCommandFlag 3795 uint32_t EmulationflagEmulationbytebitsinsertenable : __CODEGEN_BITFIELD(3, 3); //!< EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3796 uint32_t SkipemulbytecntSkipEmulationByteCount : __CODEGEN_BITFIELD(4, 7); //!< SkipEmulByteCnt - Skip Emulation Byte Count 3797 uint32_t DatabitsinlastdwSrcdataendingbitinclusion50 : __CODEGEN_BITFIELD(8, 13); //!< DataBitsInLastDW - SrCDataEndingBitInclusion[5:0] 3798 uint32_t SliceHeaderIndicator : __CODEGEN_BITFIELD(14, 14); //!< SLICE_HEADER_INDICATOR 3799 uint32_t Headerlengthexcludefrmsize : __CODEGEN_BITFIELD(15, 15); //!< HEADERLENGTHEXCLUDEFRMSIZE_ 3800 uint32_t DatabyteoffsetSrcdatastartingbyteoffset10 : __CODEGEN_BITFIELD(16, 17); //!< DataByteOffset - SrcDataStartingByteOffset[1:0] 3801 uint32_t Reserved50 : __CODEGEN_BITFIELD(18, 31); //!< Reserved 3802 }; 3803 uint32_t Value; 3804 } DW1; 3805 3806 //! \name Local enumerations 3807 3808 enum SUBOPCODE_B 3809 { 3810 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 3811 }; 3812 3813 enum SUBOPCODE_A 3814 { 3815 SUBOPCODE_A_UNNAMED2 = 2, //!< No additional details 3816 }; 3817 3818 enum MEDIA_COMMAND_OPCODE 3819 { 3820 MEDIA_COMMAND_OPCODE_MFXCOMMON = 0, //!< No additional details 3821 }; 3822 3823 enum PIPELINE 3824 { 3825 PIPELINE_MFXPAKINSERTOBJECT = 2, //!< No additional details 3826 }; 3827 3828 enum COMMAND_TYPE 3829 { 3830 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3831 }; 3832 3833 //! \brief BITSTREAMSTARTRESET_RESETBITSTREAMSTARTINGPOS 3834 //! \details 3835 //! OPEN: This bit is redundant, the control is already in the Slice State 3836 //! command 3837 enum BITSTREAMSTARTRESET_RESETBITSTREAMSTARTINGPOS 3838 { 3839 BITSTREAMSTARTRESET_RESETBITSTREAMSTARTINGPOS_INSERT = 0, //!< Insert the current command inline data starting at the current bitstream buffer insertion position 3840 BITSTREAMSTARTRESET_RESETBITSTREAMSTARTINGPOS_RESET = 1, //!< Reset the bitstream buffer insertion position to the bitstream buffer starting position. 3841 }; 3842 3843 //! \brief EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3844 //! \details 3845 //! Must be set to 0 for JPEG encoder 3846 enum EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3847 { 3848 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_NONE = 0, //!< No emulation 3849 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_EMULATE = 1, //!< Instruct the hardware to perform Start Code Prefix (0x 00 00 01/02/03/00) Search and Prevention Byte (0x 03) insertion on the insertion data of this command. It is required that hardware will handle a start code prefix crossing the boundary between insertion commands, or an insertion command followed by a PAK Object command. 3850 }; 3851 3852 //! \brief SLICE_HEADER_INDICATOR 3853 //! \details 3854 //! This bit indicates if the insert object is a slice header. In the VDEnc 3855 //! mode, PAK only gets this command at the beginning of the frame for slice 3856 //! position X=0, Y=0. It internally generates the header that needs to be 3857 //! inserted per slice. For VDEnc mode, this bit should always be set. 3858 enum SLICE_HEADER_INDICATOR 3859 { 3860 SLICE_HEADER_INDICATOR_LEGACY = 0, //!< Legacy Insertion Object command. The PAK Insertion Object command is not stored in HW. 3861 SLICE_HEADER_INDICATOR_SLICEHEADER = 1, //!< Insertion Object is a Slice Header. The command is stored internally by HW and is used for inserting slice headers. 3862 }; 3863 3864 //! \brief HEADERLENGTHEXCLUDEFRMSIZE_ 3865 //! \details 3866 //! In case this flag is on, bits are NOT accumulated during current access 3867 //! unit coding neither for Cabac Zero Word insertion bits counting or for 3868 //! output in MMIO register MFC_BITSTREAM_BYTECOUNT_FRAME_NO_HEADER. When 3869 //! using HeaderLenghtExcludeFrmSize for header insertion, the software 3870 //! needs to make sure that data comes already with inserted start code 3871 //! emulation bytes. SW shouldn't set EmulationFlag bit ( Bit 3 of DWORD1 of 3872 //! MFX_PAK_INSERT_OBJECT). 3873 enum HEADERLENGTHEXCLUDEFRMSIZE_ 3874 { 3875 HEADERLENGTHEXCLUDEFRMSIZE_ACCUMULATE = 0, //!< All bits accumulated 3876 HEADERLENGTHEXCLUDEFRMSIZE_NOACCUMULATION = 1, //!< Bits during current call are not accumulated 3877 }; 3878 3879 //! \name Initializations 3880 3881 //! \brief Explicit member initialization function 3882 MFX_PAK_INSERT_OBJECT_CMD(); 3883 3884 static const size_t dwSize = 2; 3885 static const size_t byteSize = 8; 3886 }; 3887 3888 //! 3889 //! \brief MFX_MPEG2_PIC_STATE 3890 //! \details 3891 //! This must be the very first command to issue after the surface state, 3892 //! the pipe select and base address setting commands. For MPEG-2 the 3893 //! encoder is called per slice-group, however the picture state is called 3894 //! per picture.Notice that a slice-group is a group of consecutive slices 3895 //! that no non-trivial slice headers are inserted in between. 3896 //! 3897 struct MFX_MPEG2_PIC_STATE_CMD 3898 { 3899 union 3900 { 3901 struct 3902 { 3903 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 3904 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 3905 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 3906 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 3907 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 3908 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 3909 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 3910 }; 3911 uint32_t Value; 3912 } DW0; 3913 union 3914 { 3915 struct 3916 { 3917 uint32_t Reserved32 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 3918 uint32_t ScanOrder : __CODEGEN_BITFIELD(6, 6); //!< SCAN_ORDER 3919 uint32_t IntraVlcFormat : __CODEGEN_BITFIELD(7, 7); //!< Intra VLC Format 3920 uint32_t QuantizerScaleType : __CODEGEN_BITFIELD(8, 8); //!< QUANTIZER_SCALE_TYPE 3921 uint32_t ConcealmentMotionVectorFlag : __CODEGEN_BITFIELD(9, 9); //!< Concealment Motion Vector Flag 3922 uint32_t FramePredictionFrameDct : __CODEGEN_BITFIELD(10, 10); //!< Frame Prediction Frame DCT 3923 uint32_t TffTopFieldFirst : __CODEGEN_BITFIELD(11, 11); //!< TFF (Top Field First) 3924 uint32_t PictureStructure : __CODEGEN_BITFIELD(12, 13); //!< Picture Structure 3925 uint32_t IntraDcPrecision : __CODEGEN_BITFIELD(14, 15); //!< Intra DC Precision 3926 uint32_t FCode00 : __CODEGEN_BITFIELD(16, 19); //!< f_code[0][0] 3927 uint32_t FCode01 : __CODEGEN_BITFIELD(20, 23); //!< f_code[0][1] 3928 uint32_t FCode10 : __CODEGEN_BITFIELD(24, 27); //!< f_code[1][0]. 3929 uint32_t FCode11 : __CODEGEN_BITFIELD(28, 31); //!< f_code[1][1]. 3930 }; 3931 uint32_t Value; 3932 } DW1; 3933 union 3934 { 3935 struct 3936 { 3937 uint32_t Mismatchcontroldisabled : __CODEGEN_BITFIELD(0, 1); //!< MISMATCHCONTROLDISABLED 3938 uint32_t Reserved66 : __CODEGEN_BITFIELD(2, 8); //!< Reserved 3939 uint32_t PictureCodingType : __CODEGEN_BITFIELD(9, 10); //!< PICTURE_CODING_TYPE 3940 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 13); //!< Reserved 3941 uint32_t LoadslicepointerflagLoadbitstreampointerperslice : __CODEGEN_BITFIELD(14, 14); //!< LOADSLICEPOINTERFLAG_LOADBITSTREAMPOINTERPERSLICE 3942 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 23); //!< Reserved 3943 uint32_t PBSlicePredictedMotionVectorOverrideFinalMvValueOverride : __CODEGEN_BITFIELD(24, 24); //!< PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE 3944 uint32_t PBSlicePredictedBidirMotionTypeOverrideBiDirectionMvTypeOverride : __CODEGEN_BITFIELD(25, 26); //!< PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE 3945 uint32_t Reserved91 : __CODEGEN_BITFIELD(27, 27); //!< Reserved 3946 uint32_t PBSliceConcealmentMode : __CODEGEN_BITFIELD(28, 29); //!< PB_SLICE_CONCEALMENT_MODE_ 3947 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 30); //!< Reserved 3948 uint32_t ISliceConcealmentMode : __CODEGEN_BITFIELD(31, 31); //!< I_SLICE_CONCEALMENT_MODE_ 3949 }; 3950 uint32_t Value; 3951 } DW2; 3952 union 3953 { 3954 struct 3955 { 3956 uint32_t Framewidthinmbsminus170PictureWidthInMacroblocks : __CODEGEN_BITFIELD(0, 7); //!< FrameWidthInMBsMinus1[7:0] (Picture Width in Macroblocks) 3957 uint32_t Reserved104 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 3958 uint32_t Frameheightinmbsminus170PictureHeightInMacroblocks : __CODEGEN_BITFIELD(16, 23); //!< FrameHeightInMBsMinus1[7:0] (Picture Height in Macroblocks) 3959 uint32_t MFX_MPEG2_PIC_STATE_CMD_DW3_BIT24_28 : __CODEGEN_BITFIELD(24, 28); //!< Reserved 3960 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 30); //!< Reserved 3961 uint32_t SliceConcealmentDisableBit : __CODEGEN_BITFIELD(31, 31); //!< SLICE_CONCEALMENT_DISABLE_BIT 3962 }; 3963 uint32_t Value; 3964 } DW3; 3965 union 3966 { 3967 struct 3968 { 3969 uint32_t Reserved128 : __CODEGEN_BITFIELD(0, 0); //!< Reserved 3970 uint32_t Roundintradc : __CODEGEN_BITFIELD(1, 2); //!< RoundIntraDC 3971 uint32_t Reserved131 : __CODEGEN_BITFIELD(3, 3); //!< Reserved 3972 uint32_t Roundinterdc : __CODEGEN_BITFIELD(4, 6); //!< RoundInterDC 3973 uint32_t Reserved135 : __CODEGEN_BITFIELD(7, 7); //!< Reserved 3974 uint32_t Roundintraac : __CODEGEN_BITFIELD(8, 10); //!< RoundIntraAC 3975 uint32_t Reserved139 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 3976 uint32_t Roundinterac : __CODEGEN_BITFIELD(12, 14); //!< RoundInterAC, 3977 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 3978 uint32_t Minframewsize : __CODEGEN_BITFIELD(16, 31); //!< MinFrameWSize 3979 }; 3980 uint32_t Value; 3981 } DW4; 3982 union 3983 { 3984 struct 3985 { 3986 uint32_t Intrambmaxsizereportmask : __CODEGEN_BITFIELD(0, 0); //!< INTRAMBMAXSIZEREPORTMASK 3987 uint32_t Intermbmaxsizereportmask : __CODEGEN_BITFIELD(1, 1); //!< INTERMBMAXSIZEREPORTMASK 3988 uint32_t Framebitratemaxreportmask : __CODEGEN_BITFIELD(2, 2); //!< FRAMEBITRATEMAXREPORTMASK_ 3989 uint32_t Framebitrateminreportmask : __CODEGEN_BITFIELD(3, 3); //!< FRAMEBITRATEMINREPORTMASK 3990 uint32_t Reserved164 : __CODEGEN_BITFIELD(4, 8); //!< Reserved 3991 uint32_t Mbratecontrolmask : __CODEGEN_BITFIELD(9, 9); //!< MBRATECONTROLMASK 3992 uint32_t Minframewsizeunits : __CODEGEN_BITFIELD(10, 11); //!< MINFRAMEWSIZEUNITS 3993 uint32_t Intermbforcecbpzerocontrolmask : __CODEGEN_BITFIELD(12, 12); //!< INTERMBFORCECBPZEROCONTROLMASK 3994 uint32_t Reserved173 : __CODEGEN_BITFIELD(13, 15); //!< Reserved 3995 uint32_t Framesizecontrolmask : __CODEGEN_BITFIELD(16, 16); //!< FRAMESIZECONTROLMASK 3996 uint32_t Reserved177 : __CODEGEN_BITFIELD(17, 31); //!< Reserved 3997 }; 3998 uint32_t Value; 3999 } DW5; 4000 union 4001 { 4002 struct 4003 { 4004 uint32_t Intrambmaxsize : __CODEGEN_BITFIELD(0, 11); //!< INTRAMBMAXSIZE 4005 uint32_t Reserved204 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4006 uint32_t Intermbmaxsize : __CODEGEN_BITFIELD(16, 27); //!< INTERMBMAXSIZE 4007 uint32_t Reserved220 : __CODEGEN_BITFIELD(28, 31); //!< Reserved 4008 }; 4009 uint32_t Value; 4010 } DW6; 4011 union 4012 { 4013 struct 4014 { 4015 uint32_t VslTopMbTrans8X8Flag : __CODEGEN_BITFIELD(0, 0); //!< VSL_TOP_MB_TRANS8X8FLAG 4016 uint32_t Reserved225 : __CODEGEN_BITFIELD(1, 31); //!< Reserved 4017 }; 4018 uint32_t Value; 4019 } DW7; 4020 union 4021 { 4022 struct 4023 { 4024 uint32_t Slicedeltaqpmax0 : __CODEGEN_BITFIELD(0, 7); //!< SliceDeltaQPMax[0] 4025 uint32_t Slicedeltaqpmax1 : __CODEGEN_BITFIELD(8, 15); //!< SliceDeltaQPMax[1] 4026 uint32_t Slicedeltaqpmax2 : __CODEGEN_BITFIELD(16, 23); //!< SliceDeltaQPMax[2] 4027 uint32_t Slicedeltaqpmax3 : __CODEGEN_BITFIELD(24, 31); //!< SLICEDELTAQPMAX3 4028 }; 4029 uint32_t Value; 4030 } DW8; 4031 union 4032 { 4033 struct 4034 { 4035 uint32_t Slicedeltaqpmin0 : __CODEGEN_BITFIELD(0, 7); //!< SliceDeltaQPMin[0] 4036 uint32_t Slicedeltaqpmin1 : __CODEGEN_BITFIELD(8, 15); //!< SliceDeltaQPMin[1] 4037 uint32_t Slicedeltaqpmin2 : __CODEGEN_BITFIELD(16, 23); //!< SliceDeltaQPMin[2] 4038 uint32_t Slicedeltaqpmin3 : __CODEGEN_BITFIELD(24, 31); //!< SliceDeltaQPMin[3] 4039 }; 4040 uint32_t Value; 4041 } DW9; 4042 union 4043 { 4044 struct 4045 { 4046 uint32_t Framebitratemin : __CODEGEN_BITFIELD(0, 13); //!< FrameBitRateMin 4047 uint32_t Framebitrateminunitmode : __CODEGEN_BITFIELD(14, 14); //!< FRAMEBITRATEMINUNITMODE 4048 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(15, 15); //!< FRAMEBITRATEMINUNIT 4049 uint32_t Framebitratemax : __CODEGEN_BITFIELD(16, 29); //!< FrameBitRateMax 4050 uint32_t Framebitratemaxunitmode : __CODEGEN_BITFIELD(30, 30); //!< FRAMEBITRATEMAXUNITMODE 4051 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31); //!< FRAMEBITRATEMAXUNIT_ 4052 }; 4053 uint32_t Value; 4054 } DW10; 4055 union 4056 { 4057 struct 4058 { 4059 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD(0, 14); //!< FrameBitRateMinDelta 4060 uint32_t Reserved367 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 4061 uint32_t Framebitratemaxdelta : __CODEGEN_BITFIELD(16, 30); //!< FRAMEBITRATEMAXDELTA 4062 uint32_t Reserved383 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 4063 }; 4064 uint32_t Value; 4065 } DW11; 4066 union 4067 { 4068 struct 4069 { 4070 uint32_t Reserved384 : __CODEGEN_BITFIELD(0, 16); //!< Reserved 4071 uint32_t Reserved401 : __CODEGEN_BITFIELD(17, 17); //!< Reserved 4072 uint32_t VadErrorLogic : __CODEGEN_BITFIELD(18, 18); //!< VAD_ERROR_LOGIC 4073 uint32_t Reserved403 : __CODEGEN_BITFIELD(19, 19); //!< Reserved 4074 uint32_t VmdErrorLogic : __CODEGEN_BITFIELD(20, 20); //!< VMD_ERROR_LOGIC 4075 uint32_t Reserved405 : __CODEGEN_BITFIELD(21, 31); //!< Reserved 4076 }; 4077 uint32_t Value; 4078 } DW12; 4079 4080 //! \name Local enumerations 4081 4082 enum SUBOPCODE_B 4083 { 4084 SUBOPCODE_B_UNNAMED0 = 0, //!< No additional details 4085 }; 4086 4087 enum SUBOPCODE_A 4088 { 4089 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 4090 }; 4091 4092 enum MEDIA_COMMAND_OPCODE 4093 { 4094 MEDIA_COMMAND_OPCODE_MPEG2COMMON = 3, //!< No additional details 4095 }; 4096 4097 enum PIPELINE 4098 { 4099 PIPELINE_MFXMPEG2PICSTATE = 2, //!< No additional details 4100 }; 4101 4102 enum COMMAND_TYPE 4103 { 4104 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4105 }; 4106 4107 //! \brief SCAN_ORDER 4108 //! \details 4109 //! This field specifies the Inverse Scan method for the DCT-domain 4110 //! coefficients in the blocks of the current picture. 4111 enum SCAN_ORDER 4112 { 4113 SCAN_ORDER_UNNAMED0 = 0, //!< MPEG_ZIGZAG_SCAN 4114 SCAN_ORDER_UNNAMED1 = 1, //!< MPEG_ALTERNATE_VERTICAL_SCAN 4115 }; 4116 4117 //! \brief QUANTIZER_SCALE_TYPE 4118 //! \details 4119 //! This field specifies the quantizer scaling type. 4120 enum QUANTIZER_SCALE_TYPE 4121 { 4122 QUANTIZER_SCALE_TYPE_UNNAMED0 = 0, //!< MPEG_QSCALE_LINEAR 4123 QUANTIZER_SCALE_TYPE_UNNAMED1 = 1, //!< D MPEG_QSCALE_NONLINEAR esc 4124 }; 4125 4126 //! \brief MISMATCHCONTROLDISABLED 4127 //! \details 4128 //! These 2 bits flag disables mismatch control of the inverse 4129 //! transformation for some specific cases during reference 4130 //! reconstruction.To disable MPEG2 IDCT fixed point arithmetic correction. 4131 enum MISMATCHCONTROLDISABLED 4132 { 4133 MISMATCHCONTROLDISABLED_UNNAMED0 = 0, //!< Mismatch control applies to all MBs 4134 MISMATCHCONTROLDISABLED_UNNAMED1 = 1, //!< Disable mismatch control to all intra MBs whose all AC-coefficients are zero. 4135 MISMATCHCONTROLDISABLED_UNNAMED2 = 2, //!< Disable mismatch control to all MBs whose all AC-coefficients are zero. 4136 MISMATCHCONTROLDISABLED_UNNAMED3 = 3, //!< Disable mismatch control to all MBs. 4137 }; 4138 4139 //! \brief PICTURE_CODING_TYPE 4140 //! \details 4141 //! This field identifies whether the picture is an intra-coded picture (I), 4142 //! predictive-coded picture (P) or bi-directionally predictive-coded 4143 //! picture (B). See ISO/IEC 13818-2 6.3.9 for details. 4144 enum PICTURE_CODING_TYPE 4145 { 4146 PICTURE_CODING_TYPE_MPEGIPICTURE = 1, //!< No additional details 4147 PICTURE_CODING_TYPE_10MPEGPPICTURE = 2, //!< No additional details 4148 PICTURE_CODING_TYPE_MPEGBPICTURE = 3, //!< No additional details 4149 }; 4150 4151 //! \brief LOADSLICEPOINTERFLAG_LOADBITSTREAMPOINTERPERSLICE 4152 //! \details 4153 //! To support multiple slice picture and additional header/data insertion 4154 //! before and after an encoded slice.When this field is set to 0, bitstream 4155 //! pointer is only loaded once for the first slice of a frame. For 4156 //! subsequent slices in the frame, bitstream data are stitched together to 4157 //! form a single output data stream.When this field is set to 1, bitstream 4158 //! pointer is loaded for each slice of a frame. Basically bitstream data 4159 //! for different slices of a frame will be written to different memory 4160 //! locations. 4161 enum LOADSLICEPOINTERFLAG_LOADBITSTREAMPOINTERPERSLICE 4162 { 4163 LOADSLICEPOINTERFLAG_LOADBITSTREAMPOINTERPERSLICE_UNNAMED0 = 0, //!< Load BitStream Pointer only once for the first slice of a frame 4164 LOADSLICEPOINTERFLAG_LOADBITSTREAMPOINTERPERSLICE_UNNAMED1 = 1, //!< Load/reload BitStream Pointer only once for the each slice, reload the start location of the bitstream buffer from the Indirect PAK-BSE Object Data Start Address field 4165 }; 4166 4167 //! \brief PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE 4168 //! \details 4169 //! This field is only applicable if the Concealment Motion Vectors are 4170 //! non-zero.It is only possible if "P/B Slice Concealment Mode" is set to 4171 //! "00" or "01" and left MB has non-zero motion vectors). 4172 enum PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE 4173 { 4174 PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE_PREDICTED = 0, //!< Motion Vectors use predicted values 4175 PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE_ZERO = 1, //!< Motion Vectors force to 0 4176 }; 4177 4178 //! \brief PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE 4179 //! \details 4180 //! This field is only applicable if the Concealment Motion Type is 4181 //! predicted to be Bi-directional. (It is only possible if "P/B Slice 4182 //! Concealment Mode" is set to "00" or "01" and left MB is a bi-directional 4183 //! MB). 4184 enum PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE 4185 { 4186 PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE_BID = 0, //!< Keep Bi-direction Prediction 4187 PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE_FWD = 2, //!< Only use Forward Prediction (Backward MV is forced to invalid 4188 PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE_BWD = 3, //!< Only use Backward Prediction (Forward MV is forced to invalid) 4189 }; 4190 4191 //! \brief PB_SLICE_CONCEALMENT_MODE_ 4192 //! \details 4193 //! This field controls how MPEG decoder handles MB concealment in P/B 4194 //! Slice. 4195 enum PB_SLICE_CONCEALMENT_MODE_ 4196 { 4197 PB_SLICE_CONCEALMENT_MODE_INTER = 0, //!< If left MB is NOT Intra MB type (including skipMB), use left MB inter prediction mode [frame/field or forward/backward/bi] and MV final values as concealment.Otherwise (left MB is Intra MB), use forward reference (same polarity for field pic) with MV final values set to 0. 4198 PB_SLICE_CONCEALMENT_MODE_LEFT = 1, //!< If left MB is NOT Intra MB type (including skipMB), use left MB inter prediction mode [frame/field or forward/backward/bi] and MV final values as concealment.Otherwise (left MB is Intra MB), use left MB dct_dc_pred[cc] values for concealment (Macroblock is concealed as INTRA MB and dct_dc_pred[cc] are DC predictor for Luma, Cr, Cb data) 4199 PB_SLICE_CONCEALMENT_MODE_ZERO = 2, //!< Always use forward reference (same polarity for field pic) with MV final values set to 0 (Macroblock is concealed as INTER coded) 4200 PB_SLICE_CONCEALMENT_MODE_INTRA = 3, //!< Use left MB dct_dc_pred[cc] values for concealment (Macroblock is concealed as INTRA MB and dct_dc_pred[cc] are DC predictor for Luma, Cr, Cb data 4201 }; 4202 4203 //! \brief I_SLICE_CONCEALMENT_MODE_ 4204 //! \details 4205 //! This field controls how MPEG decoder handles MB concealment in I Slice 4206 enum I_SLICE_CONCEALMENT_MODE_ 4207 { 4208 I_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 0, //!< Using Coefficient values to handle MB concealment 4209 I_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 1, //!< Using Motion Vectors to handle MB concealment 4210 }; 4211 4212 //! \brief SLICE_CONCEALMENT_DISABLE_BIT 4213 //! \details 4214 //! If VINunit detects the next slice starting position is either 4215 //! out-of-bound or smaller than or equal to the current slice starting 4216 //! position, VIN will set the current slice to be 1 MB and force VMDunit to 4217 //! do slice concealment on the next slice.This bit will disable this 4218 //! feature and the MB data from the next slice will be decoded from 4219 //! bitstream. 4220 enum SLICE_CONCEALMENT_DISABLE_BIT 4221 { 4222 SLICE_CONCEALMENT_DISABLE_BIT_ENABLE = 0, //!< VIN will force next slice to be concealment if detects slice boundary error 4223 SLICE_CONCEALMENT_DISABLE_BIT_DISABLE = 1, //!< VIN will not force next slice to be in concealment 4224 }; 4225 4226 //! \brief INTRAMBMAXSIZEREPORTMASK 4227 //! \details 4228 //! This is a mask bit controlling if the condition of any intra MB in the 4229 //! frame exceeds IntraMBMaxSize. 4230 enum INTRAMBMAXSIZEREPORTMASK 4231 { 4232 INTRAMBMAXSIZEREPORTMASK_UNNAMED0 = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4233 INTRAMBMAXSIZEREPORTMASK_UNNAMED1 = 1, //!< set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Intra MB Conformance Max size limit. 4234 }; 4235 4236 //! \brief INTERMBMAXSIZEREPORTMASK 4237 //! \details 4238 //! This is a mask bit controlling if the condition of any inter MB in the 4239 //! frame exceeds InterMBMaxSize. 4240 enum INTERMBMAXSIZEREPORTMASK 4241 { 4242 INTERMBMAXSIZEREPORTMASK_UNNAMED0 = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4243 INTERMBMAXSIZEREPORTMASK_UNNAMED1 = 1, //!< set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Inter MB Conformance Max size limit. 4244 }; 4245 4246 //! \brief FRAMEBITRATEMAXREPORTMASK_ 4247 //! \details 4248 //! This is a mask bit controlling if the condition of frame level bit count 4249 //! exceeds FrameBitRateMax. 4250 enum FRAMEBITRATEMAXREPORTMASK_ 4251 { 4252 FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4253 FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< set bit0 and bit 1 of MFC_IMAGE_STATUS control register if the total frame level bit counter is greater than or equal to Frame Bit rate Maximum limit. 4254 }; 4255 4256 //! \brief FRAMEBITRATEMINREPORTMASK 4257 //! \details 4258 //! This is a mask bit controlling if the condition of frame level bit count 4259 //! is less than FrameBitRateMin. 4260 enum FRAMEBITRATEMINREPORTMASK 4261 { 4262 FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4263 FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< set bit0 and bit 1of MFC_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit rate Minimum limit. 4264 }; 4265 4266 //! \brief MBRATECONTROLMASK 4267 //! \details 4268 //! MB Rate Control conformance maskThis field is ignored when 4269 //! MacroblockStatEnable is disabled or MB level Rate control flag for the 4270 //! current MB is disable in Macroblock Status Buffer. 4271 enum MBRATECONTROLMASK 4272 { 4273 MBRATECONTROLMASK_UNNAMED0 = 0, //!< Do not change QP values of inter macroblock with suggested QP values in Macroblock Status Buffer 4274 MBRATECONTROLMASK_UNNAMED1 = 1, //!< Apply RC QP delta for all macroblock 4275 }; 4276 4277 //! \brief MINFRAMEWSIZEUNITS 4278 //! \details 4279 //! This field is the Minimum Frame Size Units 4280 enum MINFRAMEWSIZEUNITS 4281 { 4282 MINFRAMEWSIZEUNITS_COMPATIBILITYMODE = 0, //!< Minimum Frame Size is in old mode (words, 2bytes) 4283 MINFRAMEWSIZEUNITS_16BYTE = 1, //!< Minimum Frame Size is in 16bytes 4284 MINFRAMEWSIZEUNITS_4KB = 2, //!< Minimum Frame Size is in 4Kbytes 4285 MINFRAMEWSIZEUNITS_16KB = 3, //!< Minimum Frame Size is in 16Kbytes 4286 }; 4287 4288 //! \brief INTERMBFORCECBPZEROCONTROLMASK 4289 //! \details 4290 //! Inter MB Force CBP ZERO mask. 4291 enum INTERMBFORCECBPZEROCONTROLMASK 4292 { 4293 INTERMBFORCECBPZEROCONTROLMASK_UNNAMED0 = 0, //!< No effect 4294 INTERMBFORCECBPZEROCONTROLMASK_UNNAMED1 = 1, //!< Zero out all A/C coefficients for the inter MB violating Inter Confirmance 4295 }; 4296 4297 //! \brief FRAMESIZECONTROLMASK 4298 //! \details 4299 //! Frame size conformance maskThis field is used when MacroblockStatEnable 4300 //! is set to 1. 4301 enum FRAMESIZECONTROLMASK 4302 { 4303 FRAMESIZECONTROLMASK_UNNAMED0 = 0, //!< Do not change Slice Quantization Parameter values in MFC_MPEG2_SLICEGROUP_STATE with suggested slice QP value for frame level Rate control 4304 FRAMESIZECONTROLMASK_UNNAMED1 = 1, //!< Replace Slice Quantization Parameter values in MFC_MPEG2_SLICEGROUP_STATE with suggested slice QP value for frame level Rate control values in MFC_IMAGE_STATUS control register. 4305 }; 4306 4307 //! \brief INTRAMBMAXSIZE 4308 //! \details 4309 //! This field, Intra MB Conformance Max size limit,indicates the allowed 4310 //! max bit count size for Intra MB 4311 enum INTRAMBMAXSIZE 4312 { 4313 INTRAMBMAXSIZE_UNNAMED4095 = 4095, //!< No additional details 4314 }; 4315 4316 //! \brief INTERMBMAXSIZE 4317 //! \details 4318 //! This field, Inter MB Conformance Max size limit,indicates the allowed 4319 //! max bit count size for Inter MB 4320 enum INTERMBMAXSIZE 4321 { 4322 INTERMBMAXSIZE_UNNAMED4095 = 4095, //!< No additional details 4323 }; 4324 4325 enum VSL_TOP_MB_TRANS8X8FLAG 4326 { 4327 VSL_TOP_MB_TRANS8X8FLAG_DISABLE = 0, //!< VSL will only fetch the current MB data. 4328 VSL_TOP_MB_TRANS8X8FLAG_ENABLE = 1, //!< When this bit is set VSL will make extra fetch to memory to fetch the MB data for top MB. 4329 }; 4330 4331 //! \brief SLICEDELTAQPMAX3 4332 //! \details 4333 //! This field is the Slice level delta QP for totalbit-count above 4334 //! FrameBitRateMax - first 1/8 regionThis field is used tocalculate the 4335 //! suggested slice QP into the MFC_IMAGE_STATUS control register whentotal 4336 //! bit count for the entire frame exceeds FrameBitRateMax but is within 4337 //! 1/8of FrameBitRateMaxDelta above FrameBitRateMax, i.e., in the range 4338 //! of(FrameBitRateMax, (FrameBitRateMax+FrameBitRateMaxDelta>>3). 4339 enum SLICEDELTAQPMAX3 4340 { 4341 SLICEDELTAQPMAX3_DISABLE = 0, //!< No additional details 4342 SLICEDELTAQPMAX3_ENABLE = 1, //!< No additional details 4343 }; 4344 4345 //! \brief FRAMEBITRATEMINUNITMODE 4346 //! \details 4347 //! This field is the Frame Bitrate Minimum Limit 4348 //! Units.ValueNameDescriptionProject 4349 enum FRAMEBITRATEMINUNITMODE 4350 { 4351 FRAMEBITRATEMINUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 4352 FRAMEBITRATEMINUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 4353 }; 4354 4355 //! \brief FRAMEBITRATEMINUNIT 4356 //! \details 4357 //! This field is the Frame Bitrate Minimum Limit Units. 4358 enum FRAMEBITRATEMINUNIT 4359 { 4360 FRAMEBITRATEMINUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMinUnitMode is 1 and in units of 128 Bytes if FrameBitrateMinUnitMode is 0 4361 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 4362 }; 4363 4364 //! \brief FRAMEBITRATEMAXUNITMODE 4365 //! \details 4366 //! BitFiel This field is the Frame Bitrate Maximum Limit Units.dDesc 4367 enum FRAMEBITRATEMAXUNITMODE 4368 { 4369 FRAMEBITRATEMAXUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 4370 FRAMEBITRATEMAXUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 4371 }; 4372 4373 //! \brief FRAMEBITRATEMAXUNIT_ 4374 //! \details 4375 //! This field is the Frame Bitrate Maximum Limit Units. 4376 enum FRAMEBITRATEMAXUNIT_ 4377 { 4378 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMaxUnitMode is 1 and in units of 128 Bytes if FrameBitrateMaxUnitMode is 0 4379 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 4380 }; 4381 4382 //! \brief FRAMEBITRATEMAXDELTA 4383 //! \details 4384 //! This field is used to select the slice delta QP when FrameBitRateMax Is 4385 //! exceeded. It shares the same FrameBitrateMaxUnit. When 4386 //! FrameBitrateMaxUnitMode is 0(compatibility mode), only bits 16:27 should 4387 //! be used, bits 28, 29 and 30 should be 0. 4388 enum FRAMEBITRATEMAXDELTA 4389 { 4390 FRAMEBITRATEMAXDELTA_UNNAMED0 = 0, //!< No additional details 4391 }; 4392 4393 enum VAD_ERROR_LOGIC 4394 { 4395 VAD_ERROR_LOGIC_ENABLE = 0, //!< Error reporting ON in case of premature Slice done 4396 VAD_ERROR_LOGIC_DISABLE = 1, //!< CABAC Engine will auto decode the bitstream in case of premature slice done. 4397 }; 4398 4399 enum VMD_ERROR_LOGIC 4400 { 4401 VMD_ERROR_LOGIC_DISABLE = 0, //!< No additional details 4402 VMD_ERROR_LOGIC_ENABLE = 1, //!< Error Handling 4403 }; 4404 4405 //! \name Initializations 4406 4407 //! \brief Explicit member initialization function 4408 MFX_MPEG2_PIC_STATE_CMD(); 4409 4410 static const size_t dwSize = 13; 4411 static const size_t byteSize = 52; 4412 }; 4413 4414 //! 4415 //! \brief MFD_MPEG2_BSD_OBJECT 4416 //! \details 4417 //! Different from AVC and VC1, MFD_MPEG2_BSD_OBJECT command is pipelinable. 4418 //! This is for performance purpose as in MPEG2 a slice is defined as a 4419 //! group of MBs of any size that must be within a macroblock row.Slice 4420 //! header parameters are passed in as inline data and the bitstream data 4421 //! for the slice is passed in as indirect data. Of the inline data, 4422 //! slice_horizontal_position and slice_vertical_position determines the 4423 //! location within the destination picture of the first macroblock in the 4424 //! slice. The content in this command is identical to that in the 4425 //! MEDIA_OBJECT command in VLD mode described in the Media Chapter. 4426 //! 4427 struct MFD_MPEG2_BSD_OBJECT_CMD 4428 { 4429 union 4430 { 4431 struct 4432 { 4433 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 4434 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4435 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 4436 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 4437 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 4438 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 4439 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 4440 }; 4441 uint32_t Value; 4442 } DW0; 4443 union 4444 { 4445 struct 4446 { 4447 uint32_t IndirectBsdDataLength; //!< Indirect BSD Data Length 4448 }; 4449 uint32_t Value; 4450 } DW1; 4451 union 4452 { 4453 struct 4454 { 4455 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD(0, 28); //!< Indirect Data Start Address 4456 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 4457 }; 4458 uint32_t Value; 4459 } DW2; 4460 union 4461 { 4462 struct 4463 { 4464 uint32_t FirstMacroblockBitOffset : __CODEGEN_BITFIELD(0, 2); //!< First Macroblock Bit Offset 4465 uint32_t IsLastMb : __CODEGEN_BITFIELD(3, 3); //!< IS_LAST_MB 4466 uint32_t MbRowLastSlice : __CODEGEN_BITFIELD(4, 4); //!< MB_ROW_LAST_SLICE 4467 uint32_t LastPicSlice : __CODEGEN_BITFIELD(5, 5); //!< LAST_PIC_SLICE 4468 uint32_t SliceConcealmentTypeBit : __CODEGEN_BITFIELD(6, 6); //!< SLICE_CONCEALMENT_TYPE_BIT 4469 uint32_t SliceConcealmentOverrideBit : __CODEGEN_BITFIELD(7, 7); //!< SLICE_CONCEALMENT_OVERRIDE_BIT 4470 uint32_t MacroblockCount : __CODEGEN_BITFIELD(8, 15); //!< Macroblock Count 4471 uint32_t SliceVerticalPosition : __CODEGEN_BITFIELD(16, 23); //!< Slice Vertical Position 4472 uint32_t SliceHorizontalPosition : __CODEGEN_BITFIELD(24, 31); //!< Slice Horizontal Position 4473 }; 4474 uint32_t Value; 4475 } DW3; 4476 union 4477 { 4478 struct 4479 { 4480 uint32_t NextSliceHorizontalPosition : __CODEGEN_BITFIELD(0, 7); //!< Next Slice Horizontal Position 4481 uint32_t NextSliceVerticalPosition : __CODEGEN_BITFIELD(8, 16); //!< Next Slice Vertical Position 4482 uint32_t Reserved145 : __CODEGEN_BITFIELD(17, 23); //!< Reserved 4483 uint32_t QuantizerScaleCode : __CODEGEN_BITFIELD(24, 28); //!< Quantizer Scale Code 4484 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 4485 }; 4486 uint32_t Value; 4487 } DW4; 4488 4489 //! \name Local enumerations 4490 4491 enum SUBOPCODE_B 4492 { 4493 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 4494 }; 4495 4496 enum SUBOPCODE_A 4497 { 4498 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 4499 }; 4500 4501 enum MEDIA_COMMAND_OPCODE 4502 { 4503 MEDIA_COMMAND_OPCODE_MPEG2DEC = 3, //!< No additional details 4504 }; 4505 4506 enum PIPELINE 4507 { 4508 PIPELINE_MFDMPEG2BSDOBJECT = 2, //!< No additional details 4509 }; 4510 4511 enum COMMAND_TYPE 4512 { 4513 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4514 }; 4515 4516 enum IS_LAST_MB 4517 { 4518 IS_LAST_MB_UNNAMED0 = 0, //!< The current MB is not the last MB in the current Slice 4519 IS_LAST_MB_UNNAMED1 = 1, //!< The current MB is the last MB in the current Slice 4520 }; 4521 4522 //! \brief MB_ROW_LAST_SLICE 4523 //! \details 4524 //! This bit is added to support error concealment when Context Switch at 4525 //! row boundary in debugging mode is active. 4526 enum MB_ROW_LAST_SLICE 4527 { 4528 MB_ROW_LAST_SLICE_UNNAMED0 = 0, //!< The current Slice is not the last Slice of MB row 4529 MB_ROW_LAST_SLICE_UNNAMED1 = 1, //!< The current Slice is the last Slice of the current MB row 4530 }; 4531 4532 //! \brief LAST_PIC_SLICE 4533 //! \details 4534 //! This bit is added to support error concealment at the end of a picture. 4535 enum LAST_PIC_SLICE 4536 { 4537 LAST_PIC_SLICE_UNNAMED0 = 0, //!< The current Slice is not the last Slice of current picture 4538 LAST_PIC_SLICE_UNNAMED1 = 1, //!< The current Slice is the last Slice of the entire picture 4539 }; 4540 4541 //! \brief SLICE_CONCEALMENT_TYPE_BIT 4542 //! \details 4543 //! This bit can be forced by driver ("Slice Concealment Override Bit") or 4544 //! set by VINunit depending on slice boundary errors. 4545 enum SLICE_CONCEALMENT_TYPE_BIT 4546 { 4547 SLICE_CONCEALMENT_TYPE_BIT_UNNAMED0 = 0, //!< VMD will decode MBs from the bitstream until the bitstream is run-out. Then VMD will conceal the remaining MBs. 4548 SLICE_CONCEALMENT_TYPE_BIT_UNNAMED1 = 1, //!< VMD will conceal all MBs of the slice regardless of bitstream. (If driver does not force the value of this bit, VIN will set this bit depending on slice boundary error. If the next slice position of the current slice is out-of-bound or the same or earlier than the current slice start position, VIN will set this bit for the next slice) 4549 }; 4550 4551 //! \brief SLICE_CONCEALMENT_OVERRIDE_BIT 4552 //! \details 4553 //! This bit forces hardware to handle the current slice in Conceal or 4554 //! Deocde Mode. If this bit is set to one, VIN will force the current 4555 //! slice to do concealment or to decode from bitstream regardless if the 4556 //! slice boundary has errors or not. 4557 enum SLICE_CONCEALMENT_OVERRIDE_BIT 4558 { 4559 SLICE_CONCEALMENT_OVERRIDE_BIT_UNNAMED0 = 0, //!< Driver must program "Slice Concealment Type" to '0'. VIN will set "Slice Concealment Type" depending if the slice boundary has error or not 4560 SLICE_CONCEALMENT_OVERRIDE_BIT_UNNAMED1 = 1, //!< VIN will use driver-provided "Slice Concealment Type" regardless of valid slice boundary 4561 }; 4562 4563 //! \name Initializations 4564 4565 //! \brief Explicit member initialization function 4566 MFD_MPEG2_BSD_OBJECT_CMD(); 4567 4568 static const size_t dwSize = 5; 4569 static const size_t byteSize = 20; 4570 }; 4571 4572 //! 4573 //! \brief MFD_IT_OBJECT_MPEG2_INLINE_DATA 4574 //! \details 4575 //! The content in this command is similar to that in the MEDIA_OBJECT 4576 //! command in IS mode described in the Media Chapter. Each MFD_IT_OBJECT 4577 //! command corresponds to the processing of one macroblock. Macroblock 4578 //! parameters are passed in as inline data and the non-zero DCT coefficient 4579 //! data for the macroblock is passed in as indirect data. Inline data 4580 //! starts at dword 7 of MFD_IT_OBJECT command. There are 7 dwords total. 4581 //! 4582 struct MFD_IT_OBJECT_MPEG2_INLINE_DATA_CMD 4583 { 4584 union 4585 { 4586 struct 4587 { 4588 uint32_t Reserved0 : __CODEGEN_BITFIELD(0, 2); //!< Reserved 4589 uint32_t Lastmbinrow : __CODEGEN_BITFIELD(3, 3); //!< LastMBInRow 4590 uint32_t Reserved4 : __CODEGEN_BITFIELD(4, 5); //!< Reserved 4591 uint32_t CodedBlockPattern : __CODEGEN_BITFIELD(6, 11); //!< Coded Block Pattern 4592 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4593 uint32_t MacroblockIntraType : __CODEGEN_BITFIELD(16, 16); //!< MACROBLOCK_INTRA_TYPE 4594 uint32_t MacroblockMotionForward : __CODEGEN_BITFIELD(17, 17); //!< MACROBLOCK_MOTION_FORWARD 4595 uint32_t MacroblockMotionBackward : __CODEGEN_BITFIELD(18, 18); //!< MACROBLOCK_MOTION_BACKWARD 4596 uint32_t Reserved19 : __CODEGEN_BITFIELD(19, 20); //!< Reserved 4597 uint32_t DctType : __CODEGEN_BITFIELD(21, 21); //!< DCT_TYPE 4598 uint32_t Reserved22 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 4599 uint32_t MotionType : __CODEGEN_BITFIELD(24, 25); //!< Motion Type 4600 uint32_t Reserved26 : __CODEGEN_BITFIELD(26, 27); //!< Reserved 4601 uint32_t MotionVerticalFieldSelect : __CODEGEN_BITFIELD(28, 31); //!< MOTION_VERTICAL_FIELD_SELECT 4602 }; 4603 uint32_t Value; 4604 } DW0; 4605 union 4606 { 4607 struct 4608 { 4609 uint32_t Horzorigin : __CODEGEN_BITFIELD(0, 7); //!< HorzOrigin 4610 uint32_t Vertorigin : __CODEGEN_BITFIELD(8, 15); //!< VertOrigin 4611 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 4612 }; 4613 uint32_t Value; 4614 } DW1; 4615 union 4616 { 4617 struct 4618 { 4619 uint32_t MotionVectorsField0ForwardHorizontalComponent : __CODEGEN_BITFIELD(0, 15); //!< Motion Vectors - Field 0, Forward, Horizontal Component 4620 uint32_t MotionVectorsField0ForwardVerticalComponent : __CODEGEN_BITFIELD(16, 31); //!< Motion Vectors - Field 0, Forward, Vertical Component 4621 }; 4622 uint32_t Value; 4623 } DW2; 4624 union 4625 { 4626 struct 4627 { 4628 uint32_t MotionVectorsField0BackwardHorizontalComponent : __CODEGEN_BITFIELD(0, 15); //!< Motion Vectors - Field 0, Backward, Horizontal Component 4629 uint32_t MotionVectorsField0BackwardVerticalComponent : __CODEGEN_BITFIELD(16, 31); //!< Motion Vectors - Field 0, Backward, Vertical Component 4630 }; 4631 uint32_t Value; 4632 } DW3; 4633 union 4634 { 4635 struct 4636 { 4637 uint32_t MotionVectorsField1ForwardHorizontalComponent : __CODEGEN_BITFIELD(0, 15); //!< Motion Vectors - Field 1, Forward, Horizontal Component 4638 uint32_t MotionVectorsField1ForwardVerticalComponent : __CODEGEN_BITFIELD(16, 31); //!< Motion Vectors - Field 1, Forward, Vertical Component 4639 }; 4640 uint32_t Value; 4641 } DW4; 4642 union 4643 { 4644 struct 4645 { 4646 uint32_t MotionVectorsField1BackwardHorizontalComponent : __CODEGEN_BITFIELD(0, 15); //!< Motion Vectors - Field 1, Backward, Horizontal Component 4647 uint32_t MotionVectorsField1BackwardVerticalComponent : __CODEGEN_BITFIELD(16, 31); //!< Motion Vectors - Field 1, Backward, Vertical Component 4648 }; 4649 uint32_t Value; 4650 } DW5; 4651 4652 //! \name Local enumerations 4653 4654 //! \brief MACROBLOCK_INTRA_TYPE 4655 //! \details 4656 //! This field specifies if the current macroblock is intra-coded. When set, 4657 //! Coded Block Pattern is ignored and no prediction is performed (i.e., no 4658 //! motion vectors are used). See ISO/IEC 13818-2 Tables B-2 through B-4. 4659 enum MACROBLOCK_INTRA_TYPE 4660 { 4661 MACROBLOCK_INTRA_TYPE_NON_INTRAMACROBLOCK = 0, //!< No additional details 4662 MACROBLOCK_INTRA_TYPE_INTRAMACROBLOCK = 1, //!< No additional details 4663 }; 4664 4665 //! \brief MACROBLOCK_MOTION_FORWARD 4666 //! \details 4667 //! This field specifies if the forward motion vector is active. See ISO/IEC 4668 //! 13818-2 Tables B-2 through B-4. 4669 enum MACROBLOCK_MOTION_FORWARD 4670 { 4671 MACROBLOCK_MOTION_FORWARD_NOFORWARDMOTIONVECTOR = 0, //!< No additional details 4672 MACROBLOCK_MOTION_FORWARD_USEFORWARDMOTIONVECTOR_S = 1, //!< No additional details 4673 }; 4674 4675 //! \brief MACROBLOCK_MOTION_BACKWARD 4676 //! \details 4677 //! This field specifies if the backward motion vector is active. See 4678 //! ISO/IEC 13818-2 Tables B-2 through B-4. 4679 enum MACROBLOCK_MOTION_BACKWARD 4680 { 4681 MACROBLOCK_MOTION_BACKWARD_NOBACKWARDMOTIONVECTOR = 0, //!< No additional details 4682 MACROBLOCK_MOTION_BACKWARD_USEBACKWARDMOTIONVECTOR_S = 1, //!< No additional details 4683 }; 4684 4685 //! \brief DCT_TYPE 4686 //! \details 4687 //! This field specifies the DCT type of the current macroblock. The kernel 4688 //! should ignore this field when processing Cb/Cr data. See ISO/IEC 13818-2 4689 //! #167;6.3.17.1. This field is zero if Coded Block Pattern is also zero 4690 //! (no coded blocks present). 4691 enum DCT_TYPE 4692 { 4693 DCT_TYPE_MCFRAMEDCT = 0, //!< Macroblock is frame DCT coded 4694 DCT_TYPE_MCFIELDDCT = 1, //!< Macroblock is field DCT coded 4695 }; 4696 4697 //! \brief MOTION_VERTICAL_FIELD_SELECT 4698 //! \details 4699 //! A bit-wise representation of a long [2][2] array as defined in 4700 //! #167;6.3.17.2 of the ISO/IEC 13818-2 (see also 4701 //! #167;7.6.4).<table><thead><tr><td>Bit</td><td>MVector[r]</td><td>MVector[s]</td><td>MotionVerticalFieldSelect 4702 //! Index</td></tr></thead><tbody><tr><td>28</td><td>0</td><td>0</td><td>0</td></tr><tr><td>29</td><td>0</td><td>1</td><td>1</td></tr><tr><td>30</td><td>1</td><td>0</td><td>2</td></tr><tr><td>31</td><td>1</td><td>1</td><td>3</td></tr></tbody></table> 4703 enum MOTION_VERTICAL_FIELD_SELECT 4704 { 4705 MOTION_VERTICAL_FIELD_SELECT_TOPFIELD = 0, //!< The prediction is taken from the top reference field 4706 MOTION_VERTICAL_FIELD_SELECT_BOTTOMFIELD = 1, //!< The prediction is taken from the bottom reference field. 4707 }; 4708 4709 //! \name Initializations 4710 4711 //! \brief Explicit member initialization function 4712 MFD_IT_OBJECT_MPEG2_INLINE_DATA_CMD(); 4713 4714 static const size_t dwSize = 6; 4715 static const size_t byteSize = 24; 4716 }; 4717 4718 //! 4719 //! \brief MFD_IT_OBJECT 4720 //! \details 4721 //! All weight mode (default and implicit) are mapped to explicit mode. But 4722 //! the weights come in either as explicit or implicit. 4723 //! 4724 struct MFD_IT_OBJECT_CMD 4725 { 4726 union 4727 { 4728 struct 4729 { 4730 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 4731 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4732 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 4733 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 4734 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 4735 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 4736 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 4737 }; 4738 uint32_t Value; 4739 } DW0; 4740 union 4741 { 4742 struct 4743 { 4744 uint32_t IndirectItMvDataLength : __CODEGEN_BITFIELD(0, 9); //!< Indirect IT-MV Data Length 4745 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 31); //!< Reserved 4746 }; 4747 uint32_t Value; 4748 } DW1; 4749 union 4750 { 4751 struct 4752 { 4753 uint32_t IndirectItMvDataStartAddressOffset : __CODEGEN_BITFIELD(0, 28); //!< INDIRECT_IT_MV_DATA_START_ADDRESS_OFFSET 4754 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 4755 }; 4756 uint32_t Value; 4757 } DW2; 4758 union 4759 { 4760 struct 4761 { 4762 uint32_t IndirectItCoeffDataLength : __CODEGEN_BITFIELD(0, 11); //!< Indirect IT-COEFF Data Length 4763 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 31); //!< Reserved 4764 }; 4765 uint32_t Value; 4766 } DW3; 4767 union 4768 { 4769 struct 4770 { 4771 uint32_t IndirectItCoeffDataStartAddressOffset : __CODEGEN_BITFIELD(0, 28); //!< INDIRECT_IT_COEFF_DATA_START_ADDRESS_OFFSET 4772 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 4773 }; 4774 uint32_t Value; 4775 } DW4; 4776 union 4777 { 4778 struct 4779 { 4780 uint32_t IndirectItDblkControlDataLength : __CODEGEN_BITFIELD(0, 5); //!< Indirect IT-DBLK Control Data Length 4781 uint32_t Reserved166 : __CODEGEN_BITFIELD(6, 31); //!< Reserved 4782 }; 4783 uint32_t Value; 4784 } DW5; 4785 union 4786 { 4787 struct 4788 { 4789 uint32_t IndirectItDblkControlDataStartAddressOffset : __CODEGEN_BITFIELD(0, 28); //!< INDIRECT_IT_DBLK_CONTROL_DATA_START_ADDRESS_OFFSET 4790 uint32_t Reserved221 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 4791 }; 4792 uint32_t Value; 4793 } DW6; 4794 4795 //! \name Local enumerations 4796 4797 enum SUBOPCODE_B 4798 { 4799 SUBOPCODE_B_UNNAMED9 = 9, //!< No additional details 4800 }; 4801 4802 enum SUBOPCODE_A 4803 { 4804 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 4805 }; 4806 4807 enum MEDIA_COMMAND_OPCODE 4808 { 4809 MEDIA_COMMAND_OPCODE_MFXCOMMONDEC = 0, //!< No additional details 4810 }; 4811 4812 enum PIPELINE 4813 { 4814 PIPELINE_MFDITOBJECT = 2, //!< No additional details 4815 }; 4816 4817 enum COMMAND_TYPE 4818 { 4819 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4820 }; 4821 4822 //! \brief INDIRECT_IT_MV_DATA_START_ADDRESS_OFFSET 4823 //! \details 4824 //! This field specifies the memory starting address (offset) of the MV data 4825 //! to be fetched into the IT pipeline for processing. This pointer is 4826 //! relative to the Indirect IT-MV Object Base Address.Hardware ignores this 4827 //! field if indirect data is not present, i.e. the Indirect MV Data Length 4828 //! is set to 0. Alignment of this address depends on the mode of 4829 //! operation.AVC-IT Mode: It must be DWord aligned (since each MV is 4 4830 //! bytes in size). This field is only valid in AVC decoder IT mode (VC1 and 4831 //! MPEG uses inline MV data). 4832 enum INDIRECT_IT_MV_DATA_START_ADDRESS_OFFSET 4833 { 4834 INDIRECT_IT_MV_DATA_START_ADDRESS_OFFSET_UNNAMED0 = 0, //!< No additional details 4835 INDIRECT_IT_MV_DATA_START_ADDRESS_OFFSET_UNNAMED512 = 512, //!< No additional details 4836 }; 4837 4838 //! \brief INDIRECT_IT_COEFF_DATA_START_ADDRESS_OFFSET 4839 //! \details 4840 //! This field specifies the memory starting address (offset) of the coeff 4841 //! data to be loaded into the IT pipeline for processing. This pointer is 4842 //! relative to the Indirect IT-COEFF Object Base Address.Hardware ignores 4843 //! this field if indirect IT-COEFF data is not present, i.e. the Indirect 4844 //! IT-COEFF Data Length is set to 0.This field must be DW aligned, since 4845 //! each coeff icient is 4 bytes in size.Driver will determine the Num of 4846 //! EOB 4x4/8x8 must match the block cbp flags, if not match, hardware 4847 //! cannot hang - add error handling.This field is only valid in AVC, VC1, 4848 //! MPEG2 decoder IT mode. 4849 enum INDIRECT_IT_COEFF_DATA_START_ADDRESS_OFFSET 4850 { 4851 INDIRECT_IT_COEFF_DATA_START_ADDRESS_OFFSET_UNNAMED0 = 0, //!< No additional details 4852 INDIRECT_IT_COEFF_DATA_START_ADDRESS_OFFSET_UNNAMED512 = 512, //!< No additional details 4853 }; 4854 4855 //! \brief INDIRECT_IT_DBLK_CONTROL_DATA_START_ADDRESS_OFFSET 4856 //! \details 4857 //! This field specifies the memory starting address (offset) of the 4858 //! Deblocker control data to be fetched into the IT Pipeline for 4859 //! processing. This pointer is relative to the Indirect IT-DBLK Object Base 4860 //! Address.Hardware ignores this field if indirect data is not present, ie. 4861 //! The indirect IT-DBLK Control Data Length is set to 0.It must be DWord 4862 //! aligned. Each Deblock Control Data record is 48 bytes or 12 DWords in 4863 //! size.This field is only valid in AVC decoder IT mode. 4864 enum INDIRECT_IT_DBLK_CONTROL_DATA_START_ADDRESS_OFFSET 4865 { 4866 INDIRECT_IT_DBLK_CONTROL_DATA_START_ADDRESS_OFFSET_UNNAMED0 = 0, //!< No additional details 4867 INDIRECT_IT_DBLK_CONTROL_DATA_START_ADDRESS_OFFSET_UNNAMED512 = 512, //!< No additional details 4868 }; 4869 4870 //! \name Initializations 4871 4872 //! \brief Explicit member initialization function 4873 MFD_IT_OBJECT_CMD(); 4874 4875 static const size_t dwSize = 7; 4876 static const size_t byteSize = 28; 4877 }; 4878 4879 //! 4880 //! \brief MFC_MPEG2_SLICEGROUP_STATE 4881 //! \details 4882 //! This is a slice group level command and can be issued multiple times 4883 //! within a picture that is comprised of multiple slice groups. The same 4884 //! command is used for AVC encoder (PAK mode) and decoder (VLD and IT 4885 //! modes). 4886 //! 4887 struct MFC_MPEG2_SLICEGROUP_STATE_CMD 4888 { 4889 union 4890 { 4891 struct 4892 { 4893 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 4894 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4895 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 4896 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 4897 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 4898 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 4899 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 4900 }; 4901 uint32_t Value; 4902 } DW0; 4903 union 4904 { 4905 struct 4906 { 4907 uint32_t Streamid10EncoderOnly : __CODEGEN_BITFIELD(0, 1); //!< StreamID[1:0] (Encoder-only) 4908 uint32_t Reserved34 : __CODEGEN_BITFIELD(2, 3); //!< Reserved 4909 uint32_t Sliceid30EncoderOnly : __CODEGEN_BITFIELD(4, 7); //!< SliceID[3:0] (Encoder-only) 4910 uint32_t Reserved40 : __CODEGEN_BITFIELD(8, 11); //!< Reserved 4911 uint32_t Intrasliceflag : __CODEGEN_BITFIELD(12, 12); //!< IntraSliceFlag 4912 uint32_t Intraslice : __CODEGEN_BITFIELD(13, 13); //!< IntraSlice 4913 uint32_t Firstslicehdrdisabled : __CODEGEN_BITFIELD(14, 14); //!< FirstSliceHdrDisabled 4914 uint32_t TailpresentflagTailInsertionPresentInBitstreamEncoderOnly : __CODEGEN_BITFIELD(15, 15); //!< TAILPRESENTFLAG_TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 4915 uint32_t SlicedataPresentflagSlicedataInsertionPresentInBitstreamEncoderOnly : __CODEGEN_BITFIELD(16, 16); //!< SLICEDATA_PRESENTFLAG_SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 4916 uint32_t HeaderpresentflagHeaderInsertionPresentInBitstreamEncoderOnly : __CODEGEN_BITFIELD(17, 17); //!< HEADERPRESENTFLAG_HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 4917 uint32_t BitstreamoutputflagCompressedBitstreamOutputDisableFlagEncoderOnly : __CODEGEN_BITFIELD(18, 18); //!< BITSTREAMOUTPUTFLAG_COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY 4918 uint32_t Islastslicegrp : __CODEGEN_BITFIELD(19, 19); //!< IsLastSliceGrp 4919 uint32_t SkipconvdisabledMbTypeSkipConversionDisableEncoderOnly : __CODEGEN_BITFIELD(20, 20); //!< SKIPCONVDISABLED_MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY 4920 uint32_t Reserved53 : __CODEGEN_BITFIELD(21, 21); //!< Reserved 4921 uint32_t RatectrlpanictypeRcPanicTypeEncoderOnly : __CODEGEN_BITFIELD(22, 22); //!< RATECTRLPANICTYPE_RC_PANIC_TYPE_ENCODER_ONLY 4922 uint32_t RatectrlpanicflagRcPanicEnableEncoderOnly : __CODEGEN_BITFIELD(23, 23); //!< RATECTRLPANICFLAG_RC_PANIC_ENABLE_ENCODER_ONLY 4923 uint32_t MbratectrlparamRcStableToleranceEncoderOnly : __CODEGEN_BITFIELD(24, 27); //!< MbRateCtrlParam- RC Stable Tolerance (Encoder-only) 4924 uint32_t MbratectrlmodeRcTriggleModeEncoderOnly : __CODEGEN_BITFIELD(28, 29); //!< MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY 4925 uint32_t MbratectrlresetResetratecontrolcounterEncoderOnly : __CODEGEN_BITFIELD(30, 30); //!< MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY 4926 uint32_t MbratectrlflagRatecontrolcounterenableEncoderOnly : __CODEGEN_BITFIELD(31, 31); //!< MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY 4927 }; 4928 uint32_t Value; 4929 } DW1; 4930 union 4931 { 4932 struct 4933 { 4934 uint32_t FirstmbxcntAlsoCurrstarthorzpos : __CODEGEN_BITFIELD(0, 7); //!< FirstMbXcnt - also CurrStartHorzPos 4935 uint32_t FirstmbycntAlsoCurrstartvertpos : __CODEGEN_BITFIELD(8, 15); //!< FirstMbYcnt - also CurrStartVertPos 4936 uint32_t NextsgmbxcntAlsoNextstarthorzpos : __CODEGEN_BITFIELD(16, 23); //!< NextSgMbXcnt - also NextStartHorzPos 4937 uint32_t NextsgmbycntAlsoNextstartvertpos : __CODEGEN_BITFIELD(24, 31); //!< NextSgMbYcnt - also NextStartVertPos 4938 }; 4939 uint32_t Value; 4940 } DW2; 4941 union 4942 { 4943 struct 4944 { 4945 uint32_t Slicegroupqp : __CODEGEN_BITFIELD(0, 5); //!< SliceGroupQp 4946 uint32_t Reserved102 : __CODEGEN_BITFIELD(6, 7); //!< Reserved 4947 uint32_t Slicegroupskip : __CODEGEN_BITFIELD(8, 8); //!< SliceGroupSkip 4948 uint32_t Reserved105 : __CODEGEN_BITFIELD(9, 31); //!< Reserved 4949 }; 4950 uint32_t Value; 4951 } DW3; 4952 union 4953 { 4954 struct 4955 { 4956 uint32_t BitstreamoffsetIndirectPakBseDataStartAddressWrite : __CODEGEN_BITFIELD(0, 28); //!< BITSTREAMOFFSET_INDIRECT_PAK_BSE_DATA_START_ADDRESS_WRITE 4957 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 4958 }; 4959 uint32_t Value; 4960 } DW4; 4961 union 4962 { 4963 struct 4964 { 4965 uint32_t GrowparamGrowInitEncoderOnly : __CODEGEN_BITFIELD(0, 3); //!< GrowParam - Grow Init (Encoder-only) 4966 uint32_t GrowparamGrowResistanceEncoderOnly : __CODEGEN_BITFIELD(4, 7); //!< GrowParam - Grow Resistance (Encoder-only) 4967 uint32_t ShrinkaramShrinkInitEncoderOnly : __CODEGEN_BITFIELD(8, 11); //!< Shrinkaram - Shrink Init (Encoder-only) 4968 uint32_t ShrinkparamShrinkResistanceEncoderOnly : __CODEGEN_BITFIELD(12, 15); //!< ShrinkParam - Shrink Resistance (Encoder-only) 4969 uint32_t MaxqpposmodifierMagnitudeOfQpMaxPositiveModifierEncoderOnly : __CODEGEN_BITFIELD(16, 23); //!< MaxQpPosModifier - Magnitude of QP Max Positive Modifier (Encoder-only) 4970 uint32_t MaxqpnegmodifierMagnitudeOfQpMaxNegativeModifierEncoderOnly : __CODEGEN_BITFIELD(24, 31); //!< MaxQpNegModifier - Magnitude of QP Max Negative Modifier (Encoder-only) 4971 }; 4972 uint32_t Value; 4973 } DW5; 4974 union 4975 { 4976 struct 4977 { 4978 uint32_t CorrectpointsCorrect1EncoderOnly : __CODEGEN_BITFIELD(0, 3); //!< CorrectPoints - Correct 1 (Encoder-only) 4979 uint32_t CorrectpointsCorrect2EncoderOnly : __CODEGEN_BITFIELD(4, 7); //!< CorrectPoints - Correct 2 (Encoder-only) 4980 uint32_t CorrectpointsCorrect3EncoderOnly : __CODEGEN_BITFIELD(8, 11); //!< CorrectPoints - Correct 3 (Encoder-only) 4981 uint32_t CorrectpointsCorrect4EncoderOnly : __CODEGEN_BITFIELD(12, 15); //!< CorrectPoints - Correct 4 (Encoder-only) 4982 uint32_t CorrectpointsCorrect5EncoderOnly : __CODEGEN_BITFIELD(16, 19); //!< CorrectPoints - Correct 5 (Encoder-only) 4983 uint32_t CorrectpointsCorrect6EncoderOnly : __CODEGEN_BITFIELD(20, 23); //!< CorrectPoints - Correct 6 (Encoder-only) 4984 uint32_t Reserved216 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 4985 }; 4986 uint32_t Value; 4987 } DW6; 4988 union 4989 { 4990 struct 4991 { 4992 uint32_t Cv0ClampValue0EncoderOnly : __CODEGEN_BITFIELD(0, 3); //!< CV0 - Clamp Value 0 (Encoder-only) 4993 uint32_t Cv1ClampValue1EncoderOnly : __CODEGEN_BITFIELD(4, 7); //!< CV1 - Clamp Value 1 (Encoder-only) 4994 uint32_t Cv2ClampValue2EncoderOnly : __CODEGEN_BITFIELD(8, 11); //!< CV2 - Clamp Value 2 (Encoder-only) 4995 uint32_t Cv3ClampValue3EncoderOnly : __CODEGEN_BITFIELD(12, 15); //!< CV3 - Clamp Value 3 (Encoder-only) 4996 uint32_t Cv4ClampValue4EncoderOnly : __CODEGEN_BITFIELD(16, 19); //!< CV4 - Clamp Value 4 (Encoder-only) 4997 uint32_t Cv5ClampValue5EncoderOnly : __CODEGEN_BITFIELD(20, 23); //!< CV5 - Clamp Value 5 (Encoder-only) 4998 uint32_t Cv6ClampValue6EncoderOnly : __CODEGEN_BITFIELD(24, 27); //!< CV6 - Clamp Value 6 (Encoder-only) 4999 uint32_t Cv7ClampValue7EncoderOnly : __CODEGEN_BITFIELD(28, 31); //!< CV7 - Clamp Value 7 (Encoder-only) 5000 }; 5001 uint32_t Value; 5002 } DW7; 5003 5004 //! \name Local enumerations 5005 5006 enum SUBOPCODE_B 5007 { 5008 SUBOPCODE_B_MEDIA = 3, //!< No additional details 5009 }; 5010 5011 enum SUBOPCODE_A 5012 { 5013 SUBOPCODE_A_MEDIA = 2, //!< No additional details 5014 }; 5015 5016 enum MEDIA_COMMAND_OPCODE 5017 { 5018 MEDIA_COMMAND_OPCODE_MPEG2 = 3, //!< No additional details 5019 }; 5020 5021 enum PIPELINE 5022 { 5023 PIPELINE_MFXMPEG2SLICEGROUPSTATE = 2, //!< No additional details 5024 }; 5025 5026 enum COMMAND_TYPE 5027 { 5028 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5029 }; 5030 5031 enum TAILPRESENTFLAG_TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5032 { 5033 TAILPRESENTFLAG_TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_UNNAMED0 = 0, //!< no tail insertion into the output bitstream buffer, after the current slice encoded bits 5034 TAILPRESENTFLAG_TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_UNNAMED1 = 1, //!< tail insertion into the output bitstream buffer is present, and is after the current slice encoded bits. 5035 }; 5036 5037 enum SLICEDATA_PRESENTFLAG_SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5038 { 5039 SLICEDATA_PRESENTFLAG_SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_DISABLE = 0, //!< no Slice Data insertion into the output bitstream buffer 5040 SLICEDATA_PRESENTFLAG_SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_ENABLE = 1, //!< Slice Data insertion into the output bitstream buffer is present. 5041 }; 5042 5043 enum HEADERPRESENTFLAG_HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5044 { 5045 HEADERPRESENTFLAG_HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_DISABLE = 0, //!< no header insertion into the output bitstream buffer, in front of the current slice encoded bits 5046 HEADERPRESENTFLAG_HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_ENABLE = 1, //!< header insertion into the output bitstream buffer is present, and is in front of the current slice encoded bits. 5047 }; 5048 5049 //! \brief BITSTREAMOUTPUTFLAG_COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY 5050 //! \details 5051 //! This field could be set to 1 only if LoadBitStreamPointerPerSlice is set 5052 //! to 1 as well, for debugging purpose. Otherwise whenmultiple slices are 5053 //! stitched together (with LoadBitStreamPointerPerSlice is set to 0), it 5054 //! doesn't make sense to disable bitstream output. 5055 enum BITSTREAMOUTPUTFLAG_COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY 5056 { 5057 BITSTREAMOUTPUTFLAG_COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY_ENABLE = 0, //!< enable the writing of the output compressed bitstream 5058 BITSTREAMOUTPUTFLAG_COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY_DISABLE = 1, //!< disable the writing of the output compressed bitstream 5059 }; 5060 5061 //! \brief SKIPCONVDISABLED_MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY 5062 //! \details 5063 //! This field is only valid for a P or B slice. It must be zero for other 5064 //! slice types. Rules are provided in Section 2.3.3.1.6 5065 enum SKIPCONVDISABLED_MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY 5066 { 5067 SKIPCONVDISABLED_MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY_ENABLE = 0, //!< Enable skip type conversion 5068 SKIPCONVDISABLED_MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY_DISABLE = 1, //!< Disable skip type conversion 5069 }; 5070 5071 //! \brief RATECTRLPANICTYPE_RC_PANIC_TYPE_ENCODER_ONLY 5072 //! \details 5073 //! This field selects between two RC Panic methods. If it is set to 0, in 5074 //! panic mode, the macroblock QP is maxed out, setting to requested QP + 5075 //! QP_max_pos_mod. If it is set to 1, for an intra macroblock, AC CBPs are 5076 //! set to zero (note that DC CBPs are not modified). For inter macroblocks, 5077 //! AC and DC CBPs are forced to zero. 5078 enum RATECTRLPANICTYPE_RC_PANIC_TYPE_ENCODER_ONLY 5079 { 5080 RATECTRLPANICTYPE_RC_PANIC_TYPE_ENCODER_ONLY_UNNAMED0 = 0, //!< QP Panic 5081 RATECTRLPANICTYPE_RC_PANIC_TYPE_ENCODER_ONLY_UNNAMED1 = 1, //!< CBP Panic 5082 }; 5083 5084 //! \brief RATECTRLPANICFLAG_RC_PANIC_ENABLE_ENCODER_ONLY 5085 //! \details 5086 //! If this field is set to 1, RC enters panic modewhen sum_act > 5087 //! sum_max. RC Panic Type field controls what type of panicbehavior is 5088 //! invoked. 5089 enum RATECTRLPANICFLAG_RC_PANIC_ENABLE_ENCODER_ONLY 5090 { 5091 RATECTRLPANICFLAG_RC_PANIC_ENABLE_ENCODER_ONLY_DISABLE = 0, //!< No additional details 5092 RATECTRLPANICFLAG_RC_PANIC_ENABLE_ENCODER_ONLY_ENABLE = 1, //!< No additional details 5093 }; 5094 5095 enum MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY 5096 { 5097 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED0 = 0, //!< Always Rate Control, whereas RC becomes activeif sum_act > sum_target or sum_act < sum_target 5098 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED1 = 1, //!< Gentle Rate Control, whereas RC becomes activeif sum_act > upper_midpt or sum_act < lower_midpt 5099 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED2 = 2, //!< Loose Rate Control, whereas RC becomes activeif sum_act > sum_max or sum_act < sum_min 5100 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED3 = 3, //!< Reserved 5101 }; 5102 5103 //! \brief MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY 5104 //! \details 5105 //! To reset the bit allocation accumulation counter to 0 to restart the 5106 //! rate control. 5107 enum MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY 5108 { 5109 MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY_DISABLE = 0, //!< Not reset 5110 MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY_ENABLE = 1, //!< reset 5111 }; 5112 5113 //! \brief MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY 5114 //! \details 5115 //! To enable the accumulation of bit allocation for rate controlThis field 5116 //! enables hardware Rate Control logic. The rest of the RC control fields 5117 //! are only valid when this field is set to 1. Otherwise, hardware ignores 5118 //! these fields.Note: To reset MB level rate control (QRC), we need to set 5119 //! both bits MbRateCtrlFlag and MbRateCtrlReset to 1 in the new slice 5120 enum MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY 5121 { 5122 MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY_DISABLE = 0, //!< No additional details 5123 MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY_ENABLE = 1, //!< No additional details 5124 }; 5125 5126 //! \brief BITSTREAMOFFSET_INDIRECT_PAK_BSE_DATA_START_ADDRESS_WRITE 5127 //! \details 5128 //! This field specifies the memory starting address (offset) to write out 5129 //! the compressed bitstream data from the BSE processing. This pointer is 5130 //! relative to the MFC Indirect PAK-BSE Object Base Address.It is a 5131 //! byte-aligned address for the AVC bitstream data in both CABAC/CAVLC 5132 //! Modes.For Write, there is no need to have a data length field. It is 5133 //! assumed the global memory bound check specified in the 5134 //! IND_OBJ_BASE_ADDRESS command (Indirect PAK-BSE Object Access Upper 5135 //! Bound) will take care of any illegal write access.This field is only 5136 //! valid for AVC encode mode. 5137 enum BITSTREAMOFFSET_INDIRECT_PAK_BSE_DATA_START_ADDRESS_WRITE 5138 { 5139 BITSTREAMOFFSET_INDIRECT_PAK_BSE_DATA_START_ADDRESS_WRITE_UNNAMED0 = 0, //!< No additional details 5140 BITSTREAMOFFSET_INDIRECT_PAK_BSE_DATA_START_ADDRESS_WRITE_UNNAMED512 = 512, //!< No additional details 5141 }; 5142 5143 //! \name Initializations 5144 5145 //! \brief Explicit member initialization function 5146 MFC_MPEG2_SLICEGROUP_STATE_CMD(); 5147 5148 static const size_t dwSize = 8; 5149 static const size_t byteSize = 32; 5150 }; 5151 5152 //! 5153 //! \brief MFX_VC1_PRED_PIPE_STATE 5154 //! \details 5155 //! This command is used to set the operating states of the MFD Engine 5156 //! beyond the BSD unit. It is used with both VC1 Long and Short 5157 //! format.Driver is responsible to take the intensity compensation enable 5158 //! signal, the LumScale and the LumShift provided from the VC1 interface, 5159 //! and maintain a history of these values for reference pictures. Together 5160 //! with these three parameters specified for the current picture being 5161 //! decoded, driver will derive and supply the above sets of LumScaleX, 5162 //! LumShiftX and intensity compensation enable (single or double, forward 5163 //! or backward) signals. H/W is responsible to take these state values, and 5164 //! use them to build the lookup table (including the derivation of iScale 5165 //! and iShift) for remapping the reference frame pixels, as well as 5166 //! perfoming the actual pixel remapping calculations/process. 5167 //! 5168 struct MFX_VC1_PRED_PIPE_STATE_CMD 5169 { 5170 union 5171 { 5172 struct 5173 { 5174 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 5175 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 5176 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 5177 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 5178 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 5179 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 5180 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 5181 }; 5182 uint32_t Value; 5183 } DW0; 5184 union 5185 { 5186 struct 5187 { 5188 uint32_t Reserved32 : __CODEGEN_BITFIELD(0, 3); //!< Reserved 5189 uint32_t ReferenceFrameBoundaryReplicationMode : __CODEGEN_BITFIELD(4, 7); //!< Reference Frame Boundary Replication Mode 5190 uint32_t VinIntensitycompSingleBwden : __CODEGEN_BITFIELD(8, 9); //!< vin_intensitycomp_Single_BWDen 5191 uint32_t VinIntensitycompSingleFwden : __CODEGEN_BITFIELD(10, 11); //!< vin_intensitycomp_Single_FWDen 5192 uint32_t VinIntensitycompDoubleBwden : __CODEGEN_BITFIELD(12, 13); //!< vin_intensitycomp_Double_BWDen 5193 uint32_t VinIntensitycompDoubleFwden : __CODEGEN_BITFIELD(14, 15); //!< vin_intensitycomp_Double_FWDen 5194 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 5195 }; 5196 uint32_t Value; 5197 } DW1; 5198 union 5199 { 5200 struct 5201 { 5202 uint32_t Lumscale1SingleFwd : __CODEGEN_BITFIELD(0, 5); //!< LumScale1 - Single - FWD 5203 uint32_t Reserved70 : __CODEGEN_BITFIELD(6, 7); //!< Reserved 5204 uint32_t Lumscale2SingleFwd : __CODEGEN_BITFIELD(8, 13); //!< LumScale2 - single - FWD 5205 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 5206 uint32_t Lumshift1SingleFwd : __CODEGEN_BITFIELD(16, 21); //!< LumShift1 - single - FWD 5207 uint32_t Reserved86 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 5208 uint32_t Lumshift2SingleFwd : __CODEGEN_BITFIELD(24, 29); //!< LumShift2- single - FWD 5209 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31); //!< Reserved 5210 }; 5211 uint32_t Value; 5212 } DW2; 5213 union 5214 { 5215 struct 5216 { 5217 uint32_t Lumscale1DoubleFwd : __CODEGEN_BITFIELD(0, 5); //!< LumScale1 - double - FWD 5218 uint32_t Reserved102 : __CODEGEN_BITFIELD(6, 7); //!< Reserved 5219 uint32_t Lumscale2DoubleFwd : __CODEGEN_BITFIELD(8, 13); //!< LumScale2 - double - FWD 5220 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 5221 uint32_t Lumshift1DoubleFwd : __CODEGEN_BITFIELD(16, 21); //!< LumShift1 - double -FWD 5222 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 5223 uint32_t Lumshift2DoubleFwd : __CODEGEN_BITFIELD(24, 29); //!< LumShift2- double - FWD 5224 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31); //!< Reserved 5225 }; 5226 uint32_t Value; 5227 } DW3; 5228 union 5229 { 5230 struct 5231 { 5232 uint32_t Lumscale1SingleBwd : __CODEGEN_BITFIELD(0, 5); //!< LumScale1 - Single - BWD 5233 uint32_t Reserved134 : __CODEGEN_BITFIELD(6, 7); //!< Reserved 5234 uint32_t Lumscale2SingleBwd : __CODEGEN_BITFIELD(8, 13); //!< LumScale2 - single - BWD 5235 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 5236 uint32_t Lumshift1SingleBwd : __CODEGEN_BITFIELD(16, 21); //!< LumShift1 - single - BWD 5237 uint32_t Reserved150 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 5238 uint32_t Lumshift2SingleBwd : __CODEGEN_BITFIELD(24, 29); //!< LumShift2- single - BWD 5239 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31); //!< Reserved 5240 }; 5241 uint32_t Value; 5242 } DW4; 5243 union 5244 { 5245 struct 5246 { 5247 uint32_t Lumscale1DoubleBwd : __CODEGEN_BITFIELD(0, 5); //!< LumScale1 - double - BWD 5248 uint32_t Reserved166 : __CODEGEN_BITFIELD(6, 7); //!< Reserved 5249 uint32_t Lumscale2DoubleBwd : __CODEGEN_BITFIELD(8, 13); //!< LumScale2 - double - BWD 5250 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 5251 uint32_t Lumshift1DoubleBwd : __CODEGEN_BITFIELD(16, 21); //!< LumShift1 - double -BWD 5252 uint32_t Reserved182 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 5253 uint32_t Lumshift2DoubleBwd : __CODEGEN_BITFIELD(24, 29); //!< LumShift2- double - BWD 5254 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 31); //!< Reserved 5255 }; 5256 uint32_t Value; 5257 } DW5; 5258 5259 //! \name Local enumerations 5260 5261 enum SUBOPCODE_B 5262 { 5263 SUBOPCODE_B_UNNAMED1 = 1, //!< No additional details 5264 }; 5265 5266 enum SUBOPCODE_A 5267 { 5268 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 5269 }; 5270 5271 enum MEDIA_COMMAND_OPCODE 5272 { 5273 MEDIA_COMMAND_OPCODE_VC1COMMON = 2, //!< No additional details 5274 }; 5275 5276 enum PIPELINE 5277 { 5278 PIPELINE_MFXVC1PREDPIPESTATE = 2, //!< No additional details 5279 }; 5280 5281 enum COMMAND_TYPE 5282 { 5283 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5284 }; 5285 5286 //! \name Initializations 5287 5288 //! \brief Explicit member initialization function 5289 MFX_VC1_PRED_PIPE_STATE_CMD(); 5290 5291 static const size_t dwSize = 6; 5292 static const size_t byteSize = 24; 5293 }; 5294 5295 //! 5296 //! \brief MFD_VC1_LONG_PIC_STATE 5297 //! \details 5298 //! MFX_VC1_LONG PIC_STATE command encapsulates the decoding parameters that 5299 //! are read or derived from bitstream syntax elements above (inclusive) 5300 //! picture header layer. These parameters are static for a picture and when 5301 //! slice structure is present, these parameters are not changed from slice 5302 //! to slice of the same picture. Hence, this command is only issued at the 5303 //! beginning of processing a new picture and prior to the VC1_*_OBJECT 5304 //! command. The values set for these state variables are retained 5305 //! internally across slices.Only the parameters needed by hardware (BSD 5306 //! unit) to decode bit sequence for the macroblocks in a picture layer or a 5307 //! slice layer are presented in this command. Other parameters such as the 5308 //! ones used for inverse transform or motion compensation are provided in 5309 //! MFX_VC1_PRED_PIPE_STATE command.This Long interface format is intel 5310 //! proprietary interface. Driver will need to perform addition operations 5311 //! to generate all the fields in this command. 5312 //! 5313 struct MFD_VC1_LONG_PIC_STATE_CMD 5314 { 5315 union 5316 { 5317 struct 5318 { 5319 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 5320 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 5321 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 5322 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 5323 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 5324 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 5325 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 5326 }; 5327 uint32_t Value; 5328 } DW0; 5329 union 5330 { 5331 struct 5332 { 5333 uint32_t Picturewidthinmbsminus1PictureWidthMinus1InMacroblocks : __CODEGEN_BITFIELD(0, 7); //!< PictureWidthInMBsMinus1 (Picture Width Minus 1 in Macroblocks) 5334 uint32_t Reserved40 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 5335 uint32_t Pictureheightinmbsminus1PictureHeightMinus1InMacroblocks : __CODEGEN_BITFIELD(16, 23); //!< PictureHeightInMBsMinus1 (Picture Height Minus 1 in Macroblocks) 5336 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 5337 }; 5338 uint32_t Value; 5339 } DW1; 5340 union 5341 { 5342 struct 5343 { 5344 uint32_t Vc1Profile : __CODEGEN_BITFIELD(0, 0); //!< VC1_PROFILE 5345 uint32_t Reserved65 : __CODEGEN_BITFIELD(1, 2); //!< Reserved 5346 uint32_t Secondfield : __CODEGEN_BITFIELD(3, 3); //!< Secondfield 5347 uint32_t OverlapSmoothingEnableFlag : __CODEGEN_BITFIELD(4, 4); //!< OVERLAP_SMOOTHING_ENABLE_FLAG 5348 uint32_t LoopfilterEnableFlag : __CODEGEN_BITFIELD(5, 5); //!< LOOPFILTER_ENABLE_FLAG 5349 uint32_t RangereductionEnable : __CODEGEN_BITFIELD(6, 6); //!< RANGEREDUCTION_ENABLE 5350 uint32_t Rangereductionscale : __CODEGEN_BITFIELD(7, 7); //!< RANGEREDUCTIONSCALE 5351 uint32_t MotionVectorMode : __CODEGEN_BITFIELD(8, 11); //!< MOTION_VECTOR_MODE 5352 uint32_t Syncmarker : __CODEGEN_BITFIELD(12, 12); //!< SYNCMARKER 5353 uint32_t InterpolationRounderContro : __CODEGEN_BITFIELD(13, 13); //!< Interpolation Rounder Contro 5354 uint32_t Implicitquantizer : __CODEGEN_BITFIELD(14, 14); //!< ImplicitQuantizer 5355 uint32_t Dmvsurfacevalid : __CODEGEN_BITFIELD(15, 15); //!< DmvSurfaceValid 5356 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 23); //!< Reserved 5357 uint32_t BitplaneBufferPitchMinus1 : __CODEGEN_BITFIELD(24, 31); //!< Bitplane Buffer Pitch Minus 1 5358 }; 5359 uint32_t Value; 5360 } DW2; 5361 union 5362 { 5363 struct 5364 { 5365 uint32_t Bscalefactor : __CODEGEN_BITFIELD(0, 7); //!< BScaleFactor 5366 uint32_t PquantPictureQuantizationValue : __CODEGEN_BITFIELD(8, 12); //!< PQuant (Picture Quantization Value) 5367 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 15); //!< Reserved 5368 uint32_t AltpquantAlternativePictureQuantizationValue : __CODEGEN_BITFIELD(16, 20); //!< AltPQuant (Alternative Picture Quantization Value) 5369 uint32_t Reserved117 : __CODEGEN_BITFIELD(21, 23); //!< Reserved 5370 uint32_t FcmFrameCodingMode : __CODEGEN_BITFIELD(24, 25); //!< FCM_FRAME_CODING_MODE 5371 uint32_t PictypePictureType : __CODEGEN_BITFIELD(26, 28); //!< PicType (Picture Type) 5372 uint32_t Condover : __CODEGEN_BITFIELD(29, 30); //!< CONDOVER 5373 uint32_t Reserved127 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 5374 }; 5375 uint32_t Value; 5376 } DW3; 5377 union 5378 { 5379 struct 5380 { 5381 uint32_t Pquantuniform : __CODEGEN_BITFIELD(0, 0); //!< PQUANTUNIFORM 5382 uint32_t Halfqp : __CODEGEN_BITFIELD(1, 1); //!< HalfQP 5383 uint32_t AltpquantconfigAlternativePictureQuantizationConfiguration : __CODEGEN_BITFIELD(2, 3); //!< ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION 5384 uint32_t AltpquantedgemaskAlternativePictureQuantizationEdgeMask : __CODEGEN_BITFIELD(4, 7); //!< AltPQuantEdgeMask (Alternative Picture Quantization Edge Mask) 5385 uint32_t ExtendedmvrangeExtendedMotionVectorRangeFlag : __CODEGEN_BITFIELD(8, 9); //!< EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG 5386 uint32_t ExtendeddmvrangeExtendedDifferentialMotionVectorRangeFlag : __CODEGEN_BITFIELD(10, 11); //!< EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG 5387 uint32_t Reserved140 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 5388 uint32_t FwdrefdistReferenceDistance : __CODEGEN_BITFIELD(16, 19); //!< FwdRefDist (Reference Distance) 5389 uint32_t BwdrefdistReferenceDistance : __CODEGEN_BITFIELD(20, 23); //!< BwdRefDist (Reference Distance) 5390 uint32_t NumrefNumberOfReferences : __CODEGEN_BITFIELD(24, 24); //!< NUMREF_NUMBER_OF_REFERENCES 5391 uint32_t ReffieldpicpolarityReferenceFieldPicturePolarity : __CODEGEN_BITFIELD(25, 25); //!< REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY 5392 uint32_t FastuvmcflagFastUvMotionCompensationFlag : __CODEGEN_BITFIELD(26, 26); //!< FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 5393 uint32_t FourmvswitchFourMotionVectorSwitch : __CODEGEN_BITFIELD(27, 27); //!< FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH 5394 uint32_t UnifiedmvmodeUnifiedMotionVectorMode : __CODEGEN_BITFIELD(28, 29); //!< UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE 5395 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31); //!< Reserved 5396 }; 5397 uint32_t Value; 5398 } DW4; 5399 union 5400 { 5401 struct 5402 { 5403 uint32_t CbptabCodedBlockPatternTable : __CODEGEN_BITFIELD(0, 2); //!< CbpTab (Coded Block Pattern Table) 5404 uint32_t TransdctabIntraTransformDcTable : __CODEGEN_BITFIELD(3, 3); //!< TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE 5405 uint32_t TransacuvPictureLevelTransformChromaAcCodingSetIndexTransactable : __CODEGEN_BITFIELD(4, 5); //!< TransAcUV (Picture-level Transform Chroma AC Coding Set Index, TRANSACTABLE) 5406 uint32_t TransacyPictureLevelTransformLumaAcCodingSetIndexTransactable2 : __CODEGEN_BITFIELD(6, 7); //!< TransAcY (Picture-level Transform Luma AC Coding Set Index, TRANSACTABLE2 5407 uint32_t MbmodetabMacroblockModeTable : __CODEGEN_BITFIELD(8, 10); //!< MbModeTab (Macroblock Mode Table) 5408 uint32_t TranstypembflagMacroblockTransformTypeFlag : __CODEGEN_BITFIELD(11, 11); //!< TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG 5409 uint32_t TranstypePictureLevelTransformType : __CODEGEN_BITFIELD(12, 13); //!< TransType (Picture-level Transform Type) 5410 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 5411 uint32_t Twomvbptab2MvBlockPatternTable : __CODEGEN_BITFIELD(16, 17); //!< TwoMvBpTab (2MV Block Pattern Table) 5412 uint32_t Fourmvbptab4MvBlockPatternTable : __CODEGEN_BITFIELD(18, 19); //!< FourMvBpTab (4-MV Block Pattern Table) 5413 uint32_t MvtabMotionVectorTable : __CODEGEN_BITFIELD(20, 22); //!< MvTab (Motion Vector Table) 5414 uint32_t Reserved183 : __CODEGEN_BITFIELD(23, 23); //!< Reserved 5415 uint32_t Fieldtxraw : __CODEGEN_BITFIELD(24, 24); //!< FIELDTXRAW 5416 uint32_t Acpredraw : __CODEGEN_BITFIELD(25, 25); //!< ACPREDRAW 5417 uint32_t Overflagsraw : __CODEGEN_BITFIELD(26, 26); //!< OVERFLAGSRAW 5418 uint32_t Directmbraw : __CODEGEN_BITFIELD(27, 27); //!< DIRECTMBRAW 5419 uint32_t Skipmbraw : __CODEGEN_BITFIELD(28, 28); //!< SKIPMBRAW 5420 uint32_t Mvtypembraw : __CODEGEN_BITFIELD(29, 29); //!< MVTYPEMBRAW 5421 uint32_t Forwardmbraw : __CODEGEN_BITFIELD(30, 30); //!< FORWARDMBRAW 5422 uint32_t BitplanepresentflagBitplaneBufferPresentFlag : __CODEGEN_BITFIELD(31, 31); //!< BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG 5423 }; 5424 uint32_t Value; 5425 } DW5; 5426 5427 //! \name Local enumerations 5428 5429 enum SUBOPCODE_B 5430 { 5431 SUBOPCODE_B_UNNAMED1 = 1, //!< No additional details 5432 }; 5433 5434 enum SUBOPCODE_A 5435 { 5436 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 5437 }; 5438 5439 enum MEDIA_COMMAND_OPCODE 5440 { 5441 MEDIA_COMMAND_OPCODE_VC1DEC = 2, //!< No additional details 5442 }; 5443 5444 enum PIPELINE 5445 { 5446 PIPELINE_MFDVC1LONGPICSTATE = 2, //!< No additional details 5447 }; 5448 5449 enum COMMAND_TYPE 5450 { 5451 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5452 }; 5453 5454 //! \brief VC1_PROFILE 5455 //! \details 5456 //! specifies the bitstream profile.This field is used in both VLD and IT 5457 //! modes. 5458 enum VC1_PROFILE 5459 { 5460 VC1_PROFILE_DISABLE = 0, //!< current picture is in Simple or Main Profile (No need to distinguish Simple and Main Profile) 5461 VC1_PROFILE_ENABLE = 1, //!< current picture is in Advanced Profile 5462 }; 5463 5464 //! \brief OVERLAP_SMOOTHING_ENABLE_FLAG 5465 //! \details 5466 //! This field is the decoded syntax element OVERLAP in bitstreamIndicates 5467 //! if Overlap smoothing is ON at the picture levelThis field is used in 5468 //! both VLD and IT modes. 5469 enum OVERLAP_SMOOTHING_ENABLE_FLAG 5470 { 5471 OVERLAP_SMOOTHING_ENABLE_FLAG_DISABLE = 0, //!< to disable overlap smoothing filter 5472 OVERLAP_SMOOTHING_ENABLE_FLAG_ENABLE = 1, //!< to enable overlap smoothing filter 5473 }; 5474 5475 //! \brief LOOPFILTER_ENABLE_FLAG 5476 //! \details 5477 //! This filed is the decoded syntax element LOOPFILTER in bitstream. It 5478 //! indicates if In-loop Deblocking is ON according to picture level 5479 //! bitstream syntax control. This bit affects BSD unit and also the loop 5480 //! filter unit.When this bit is set to 1, PostDeblockOutEnable field in 5481 //! MFX_PIPE_MODE_SELECT command must also be set to 1. In this case, 5482 //! in-loop deblocking operation follows the VC1 standard - deblocking 5483 //! doesn't cross slice boundary.When this bit is set to 0, but 5484 //! PostDeblockOutEnable field in MFX_PIPE_MODE_SELECT command is set to 1. 5485 //! It indicates the loop filter unit is used for out-of-loop deblocking. In 5486 //! this case, deblocking operation does cross slice boundary.This field is 5487 //! used in VLD mode only, not in IT mode. 5488 enum LOOPFILTER_ENABLE_FLAG 5489 { 5490 LOOPFILTER_ENABLE_FLAG_DISABLE = 0, //!< Disables loop filter 5491 LOOPFILTER_ENABLE_FLAG_ENABLE = 1, //!< Enables loop filter 5492 }; 5493 5494 //! \brief RANGEREDUCTION_ENABLE 5495 //! \details 5496 //! This field specifies whether on-the-fly pixel value range reduction 5497 //! should be performed for the preceding (or forward) reference picture. 5498 //! Along with RangeReductionScale to specify whether scale up or down 5499 //! should be performed. It is not the same value as RANGEREDFRM Syntax 5500 //! Element (PictureParameters bPicDeblocked bit 5) in the Picture Header. 5501 enum RANGEREDUCTION_ENABLE 5502 { 5503 RANGEREDUCTION_ENABLE_DISABLE = 0, //!< Range reduction is not performed 5504 RANGEREDUCTION_ENABLE_ENABLE = 1, //!< Range reduction is performed 5505 }; 5506 5507 //! \brief RANGEREDUCTIONSCALE 5508 //! \details 5509 //! This field specifies whether the reference picture pixel values should 5510 //! be scaled up or scaled down on-the-fly, if RangeReduction is Enabled. 5511 enum RANGEREDUCTIONSCALE 5512 { 5513 RANGEREDUCTIONSCALE_UNNAMED0 = 0, //!< Scale down reference picture by factor of 2 5514 RANGEREDUCTIONSCALE_UNNAMED1 = 1, //!< Scale up reference picture by factor of 2 5515 }; 5516 5517 //! \brief MOTION_VECTOR_MODE 5518 //! \details 5519 //! This field indicates one of the following motion compensation 5520 //! interpolation modes for P and B pictures. The MC interpolation modes 5521 //! apply to prediction values of luminance blocks and are always in 5522 //! quarter-sample. For chrominance blocks, it always performs bilinear 5523 //! interpolation with either half-pel or quarter-pel precision.Before the 5524 //! polarity of Chroma Half-pel or Q-pel is reversed from Spec, now I have 5525 //! fixed it to match with VC1 Spec. 5526 enum MOTION_VECTOR_MODE 5527 { 5528 MOTION_VECTOR_MODE_UNNAMED0 = 0, //!< Chroma Quarter -pel + Luma bicubic. (can only be 1MV) 5529 MOTION_VECTOR_MODE_UNNAMED1 = 1, //!< Chroma Half-pel + Luma bicubic. (can be 1MV or 4MV) 5530 MOTION_VECTOR_MODE_UNNAMED8 = 8, //!< Chroma Quarter -pel + Luma bilinear. (can only be 1MV) 5531 MOTION_VECTOR_MODE_UNNAMED9 = 9, //!< Chroma Half-pel + Luma bilinear 5532 }; 5533 5534 //! \brief SYNCMARKER 5535 //! \details 5536 //! Indicates whether sync markers are enabled/disabled. If enable, sync 5537 //! markers "may be" present in the current video sequence being decoded. It 5538 //! is a sequence level syntax element and is valid only for Simple and Main 5539 //! Profiles. 5540 enum SYNCMARKER 5541 { 5542 SYNCMARKER_NOTPRESENT = 0, //!< Sync Marker is not present in the bitstream 5543 SYNCMARKER_MAYBEPRESENT = 1, //!< Sync Marker maybe present in the bitstream 5544 }; 5545 5546 //! \brief FCM_FRAME_CODING_MODE 5547 //! \details 5548 //! This is the same as the variable FCM defined in VC1.This field must be 5549 //! set to 0 for Simple and Main ProfilesThis field is unique to intel VC1 5550 //! VLD Long format, and is used in IT mode as well. For VC1 IT mode, driver 5551 //! needs to convert the interface to intel HW VLD Long Format interface. 5552 enum FCM_FRAME_CODING_MODE 5553 { 5554 FCM_FRAME_CODING_MODE_DISABLE = 0, //!< Progressive Frame Picture 5555 FCM_FRAME_CODING_MODE_ENABLE = 1, //!< Interlaced Frame Picture 5556 FCM_FRAME_CODING_MODE_UNNAMED2 = 2, //!< Field Picture with Top Field First 5557 FCM_FRAME_CODING_MODE_UNNAMED3 = 3, //!< Field Picture with Bottom Field First 5558 }; 5559 5560 //! \brief CONDOVER 5561 //! \details 5562 //! This field is the decoded syntax element CONDOVER in a bitstream of 5563 //! advanced profile. It controls the overlap smoothing filter operation for 5564 //! an I frame or an BI frame when the picture level qualization step size 5565 //! PQUANT is 8 or lower.This field is used in intel VC1 VLD mode only, not 5566 //! in VC1 and IT modes. 5567 enum CONDOVER 5568 { 5569 CONDOVER_UNNAMED0 = 0, //!< No overlap smoothing 5570 CONDOVER_UNNAMED1 = 1, //!< Reserved 5571 CONDOVER_UNNAMED2 = 2, //!< Always perform overlap smoothing filter 5572 CONDOVER_UNNAMED3 = 3, //!< Overlap smoothing on a per macroblock basis based on OVERFLAGS 5573 }; 5574 5575 //! \brief PQUANTUNIFORM 5576 //! \details 5577 //! Indicating if uniform quantization applies to thepicture. It is used for 5578 //! inverse quantization of the AC coefficients.QUANTIZER001123PQUANTIZER 5579 //! --01--PQINDEX>=9<=8----PQuantUniform010201ImplicitQuantizer = 0, 5580 //! andPQuantUniform = 0 is used to represent 2 cases : 1) QUANTIZER=01 5581 //! andPQUANTIZER=0; and 2) QUANTIZER = 10b.ImplicitQuantizer = 0, and 5582 //! PQuantUniform =1 is used to represent 2 cases : 1) QUANTIZER=01 and 5583 //! PQUANTIZER=1; and 2)QUANTIZER = 11bThis field is unique to intel VC1 VLD 5584 //! Long format mode, and isnot used in IT and VC1 modes. 5585 enum PQUANTUNIFORM 5586 { 5587 PQUANTUNIFORM_UNNAMED0 = 0, //!< Non-uniform 5588 PQUANTUNIFORM_UNNAMED1 = 1, //!< Uniform 5589 }; 5590 5591 //! \brief ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION 5592 //! \details 5593 //! This field specifies the way AltPQuant is used in the picture. It 5594 //! determines how to compute the macroblock quantizer step size, MQUANT. It 5595 //! is derived based on the following variables DQUANT, DQUANTFRM, 5596 //! DQPROFILE, DQSBEDGE, DQDBEDGE, and DQBILEVEL defined in the VC1 5597 //! standard, as shown in Error! Reference source not found..This field is 5598 //! unique to intel VC1 VLD Long format mode, and is not used in IT and 5599 //! modes. 5600 enum ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION 5601 { 5602 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED0 = 0, //!< AltPQuant not used 5603 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED1 = 1, //!< AltPQuant is used and applied to edge macroblocks only 5604 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED2 = 2, //!< MQUANT is encoded in macroblock layer 5605 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED3 = 3, //!< AltPQuant and PQuant are selected on macroblock basis 5606 }; 5607 5608 //! \brief EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG 5609 //! \details 5610 //! This field specifies the motion vector range in quarter-pel or half-pel 5611 //! modes. It is equivalent to the variable MVRANGE in the VC1 standard. 5612 //! This field is unique to intel VC1 VLD Long format mode, and is not used 5613 //! in IT and VC1 modes 5614 enum EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG 5615 { 5616 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED0 = 0, //!< [-256, 255] x [-128, 127] 5617 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED1 = 1, //!< 512, 511] x [-256, 255] 5618 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED2 = 2, //!< [-2048, 2047] x [-1024, 1023] 5619 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED3 = 3, //!< [-4096, 4095] x [-2048, 2047] 5620 }; 5621 5622 //! \brief EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG 5623 //! \details 5624 //! This field specifies the differential motion vector range in interlaced 5625 //! pictures. It is equivalent to the variable DMVRANGE in the VC1 standard. 5626 //! This field is unique to intel VC1 VLD Long format mode, and is not used 5627 //! in IT and VC1 modes. 5628 enum EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG 5629 { 5630 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED0 = 0, //!< No extended range 5631 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED1 = 1, //!< Extended horizontally 5632 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED2 = 2, //!< Extended vertically 5633 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED3 = 3, //!< Extended in both directions 5634 }; 5635 5636 //! \brief NUMREF_NUMBER_OF_REFERENCES 5637 //! \details 5638 //! This field indicates how many reference fields are referenced by the 5639 //! current (field) picture. It is identical to the variable NUMREF in the 5640 //! VC1 standard. This field is only valid for field P picture (FCM = 10 | 5641 //! 11).This field is unique to intel VC1 VLD Long format mode, and is not 5642 //! used in IT and VC1 modes. 5643 enum NUMREF_NUMBER_OF_REFERENCES 5644 { 5645 NUMREF_NUMBER_OF_REFERENCES_UNNAMED0 = 0, //!< One field referenced 5646 NUMREF_NUMBER_OF_REFERENCES_UNNAMED1 = 1, //!< Two fields referenced 5647 }; 5648 5649 //! \brief REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY 5650 //! \details 5651 //! This field specifies the polarity of the one reference field picture 5652 //! used for a field P picture. It is derived from the variable REFFIELD 5653 //! defined in VC1 standard and is only valid when one field is referenced 5654 //! (NUMREF = 0) for a field P picture.When NUMREF = 0 and REFFIELD = 0, 5655 //! this field is the polarity of the reference I/P field that is temporally 5656 //! closest; When NUMREF = 0 and REFFIELD = 1, this field is the polarity of 5657 //! the reference I/P field that is the second most temporally closest. The 5658 //! distance is measured based on display order but ignoring the repeated 5659 //! field if present (due to RFF = 1).This field is unique to intel VC1 VLD 5660 //! Long format mode, and is not used in IT and VC1 modes. 5661 enum REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY 5662 { 5663 REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY_UNNAMED0 = 0, //!< Top (even) field 5664 REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY_UNNAMED1 = 1, //!< Bottom (odd) field 5665 }; 5666 5667 //! \brief FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 5668 //! \details 5669 //! This field specifies whether the motion vectors forUV is rounded to half 5670 //! or full pel position. It is identical to the variableFASTUVMC in VC1 5671 //! standard.This field is used in both VLD and IT modes.It isderived from 5672 //! FASTUVMC = (bPicSpatialResid8 >> 4) & 1 in both VLD andIT 5673 //! modes, and should have the same value as Motion Vector ModeLSBit. 5674 enum FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 5675 { 5676 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED0 = 0, //!< no rounding 5677 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED1 = 1, //!< quarter-pel offsets to half/full pel positions 5678 }; 5679 5680 //! \brief FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH 5681 //! \details 5682 //! This field indicates if 4-MV is present for an interlaced frame P 5683 //! picture. It is identical to the variable 4MVSWITCH (4 Motion Vector 5684 //! Switch) in VC1 standard.This field is used in intel VC1 VLD Long Format 5685 //! mode only, it is not used in VC1 VLD and IT modes. 5686 enum FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH 5687 { 5688 FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH_DISABLE = 0, //!< only 1-MV 5689 FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH_ENABLE = 1, //!< 1, 2, or 4 Motion Vectors 5690 }; 5691 5692 //! \brief UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE 5693 //! \details 5694 //! This field is a combination of the variables MVMODE and MVMODE2 in the 5695 //! VC1 standard, for parsing Luma MVD from the bitstream. This field is 5696 //! used to signal 1MV vs 4MVallowed (Mixed Mode). This field is also used 5697 //! to signal Q-pel or Half-pel MVD read from the bitstream. The bicubic or 5698 //! bilinear Luma MC interpolation mode is duplicate information from Motion 5699 //! Vector Mode field, and is ignored here.This field is used in intel VC1 5700 //! VLD Long Format mode only, it is not used in VC1 VLD and IT modes. 5701 enum UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE 5702 { 5703 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED0 = 0, //!< Mixed MV, Q-pel bicubic 5704 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED1 = 1, //!< 1-MV, Q-pel bicubic 5705 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED2 = 2, //!< 1-MV half-pel bicubic 5706 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED3 = 3, //!< 1-MV half-pel bilinear 5707 }; 5708 5709 //! \brief TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE 5710 //! \details 5711 //! This field specifies whether the low motion tables or the high motion 5712 //! tables are used to decode the Transform DC coefficients in intra-coded 5713 //! blocks. This field is identical to the variable TRANSDCTAB in the VC1 5714 //! standard, section 8.1.1.2.This field is valid for all picture types.This 5715 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 5716 //! and VC1 modes. 5717 enum TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE 5718 { 5719 TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE_UNNAMED0 = 0, //!< The high motion tables 5720 TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE_UNNAMED1 = 1, //!< The low motion tables 5721 }; 5722 5723 //! \brief TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG 5724 //! \details 5725 //! This field indicates whether Transform Type is fixed at picture level or 5726 //! variable at macroblock level. It is identical to the variable TTMBF in 5727 //! the VC1 standard, section 7.1.1.40.This field is set to 1 when 5728 //! VSTRANSFORM is 0 in the entry point layer.This field is unique to intel 5729 //! VC1 VLD Long format mode, and is not used in IT and VC1 modes. 5730 enum TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG 5731 { 5732 TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG_UNNAMED0 = 0, //!< variable transform type in macroblock layer 5733 TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG_UNNAMED1 = 1, //!< use picture level transform type TransType 5734 }; 5735 5736 //! \brief FIELDTXRAW 5737 //! \details 5738 //! This field indicates whether the FIELDTX field is coded in raw or 5739 //! non-raw mode.This field is only valid when PictureType is I or BI.This 5740 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 5741 //! and VC1 modes. 5742 enum FIELDTXRAW 5743 { 5744 FIELDTXRAW_DISABLE = 0, //!< Non-Raw Mode 5745 FIELDTXRAW_ENABLE = 1, //!< Raw Mode 5746 }; 5747 5748 //! \brief ACPREDRAW 5749 //! \details 5750 //! This field indicates whether the ACPRED field is coded in raw or non-raw 5751 //! mode.This field is only valid when PictureType is I or BI.This field is 5752 //! unique to intel VC1 VLD Long format mode, and is not used in IT and VC1 5753 //! modes. 5754 enum ACPREDRAW 5755 { 5756 ACPREDRAW_DISABLE = 0, //!< Non-Raw Mode 5757 ACPREDRAW_ENABLE = 1, //!< Raw Mode 5758 }; 5759 5760 //! \brief OVERFLAGSRAW 5761 //! \details 5762 //! This field indicates whether the OVERFLAGS field is coded in raw or 5763 //! non-raw mode.This field is only valid when PictureType is I or BI.This 5764 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 5765 //! and VC1 modes. 5766 enum OVERFLAGSRAW 5767 { 5768 OVERFLAGSRAW_UNNAMED0 = 0, //!< Non-Raw Mode 5769 OVERFLAGSRAW_UNNAMED1 = 1, //!< Raw Mode 5770 }; 5771 5772 //! \brief DIRECTMBRAW 5773 //! \details 5774 //! This field indicates whether the DIRECTMB field is coded in raw or 5775 //! non-raw mode.This field is only valid when PictureType is P or B.This 5776 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 5777 //! and VC1 modes. 5778 enum DIRECTMBRAW 5779 { 5780 DIRECTMBRAW_UNNAMED0 = 0, //!< Non-Raw Mode 5781 DIRECTMBRAW_UNNAMED1 = 1, //!< Raw Mode 5782 }; 5783 5784 //! \brief SKIPMBRAW 5785 //! \details 5786 //! This field indicates whether the SKIPMB field is coded in raw or non-raw 5787 //! mode.This field is only valid when PictureType is P or B.0 = non-raw 5788 //! mode1 = raw modeThis field is unique to intel VC1 VLD Long format mode, 5789 //! and is not used in IT and VC1 modes. 5790 enum SKIPMBRAW 5791 { 5792 SKIPMBRAW_DISABLE = 0, //!< Non-Raw Mode 5793 SKIPMBRAW_ENABLE = 1, //!< Raw Mode 5794 }; 5795 5796 //! \brief MVTYPEMBRAW 5797 //! \details 5798 //! This field indicates whether the MVTYPREMB field is coded in raw or 5799 //! non-raw mode.This field is only valid when PictureType is P.This field 5800 //! is unique to intel VC1 VLD Long format mode, and is not used in IT and 5801 //! VC1 modes. 5802 enum MVTYPEMBRAW 5803 { 5804 MVTYPEMBRAW_UNNAMED0 = 0, //!< Non-Raw Mode 5805 MVTYPEMBRAW_UNNAMED1 = 1, //!< Raw Mode 5806 }; 5807 5808 //! \brief FORWARDMBRAW 5809 //! \details 5810 //! This field indicates whether the FORWARDMB field is coded in raw or 5811 //! non-raw mode.This field is only valid when PictureType is B.This field 5812 //! is unique to intel VC1 VLD Long format mode, and is not used in IT and 5813 //! VC1 modes. 5814 enum FORWARDMBRAW 5815 { 5816 FORWARDMBRAW_UNNAMED0 = 0, //!< non-raw mode 5817 FORWARDMBRAW_UNNAMED1 = 1, //!< raw mode 5818 }; 5819 5820 //! \brief BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG 5821 //! \details 5822 //! This field indicates whether the bitplane buffer is present for the 5823 //! picture. If set, at least one of the fields listed in bits 22:16 is 5824 //! coded in non-raw mode, and Bitplane Buffer Base Address field in the 5825 //! VC1_BSD_BUF_BASE_STATE command points to the bitplane buffer. Otherwise, 5826 //! all the fields that are applicable for the current picture in bits 22:16 5827 //! must be coded in raw mode.This field is unique to intel VC1 VLD Long 5828 //! format mode, and is not used in IT and VC1 modes. 5829 enum BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG 5830 { 5831 BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG_UNNAMED0 = 0, //!< bitplane buffer is not present 5832 BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG_UNNAMED1 = 1, //!< bitplane buffer is present 5833 }; 5834 5835 //! \name Initializations 5836 5837 //! \brief Explicit member initialization function 5838 MFD_VC1_LONG_PIC_STATE_CMD(); 5839 5840 static const size_t dwSize = 6; 5841 static const size_t byteSize = 24; 5842 }; 5843 5844 //! 5845 //! \brief MFD_VC1_SHORT_PIC_STATE 5846 //! \details 5847 //! 5848 //! 5849 struct MFD_VC1_SHORT_PIC_STATE_CMD 5850 { 5851 union 5852 { 5853 struct 5854 { 5855 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 5856 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 5857 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 5858 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 5859 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 5860 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 5861 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 5862 }; 5863 uint32_t Value; 5864 } DW0; 5865 union 5866 { 5867 struct 5868 { 5869 uint32_t PictureWidth : __CODEGEN_BITFIELD(0, 7); //!< Picture Width 5870 uint32_t Reserved40 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 5871 uint32_t PictureHeight : __CODEGEN_BITFIELD(16, 23); //!< Picture Height 5872 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 5873 }; 5874 uint32_t Value; 5875 } DW1; 5876 union 5877 { 5878 struct 5879 { 5880 uint32_t PictureStructure : __CODEGEN_BITFIELD(0, 1); //!< PICTURE_STRUCTURE 5881 uint32_t Reserved66 : __CODEGEN_BITFIELD(2, 2); //!< Reserved 5882 uint32_t Secondfield : __CODEGEN_BITFIELD(3, 3); //!< SecondField 5883 uint32_t IntraPictureFlag : __CODEGEN_BITFIELD(4, 4); //!< INTRA_PICTURE_FLAG 5884 uint32_t BackwardPredictionPresentFlag : __CODEGEN_BITFIELD(5, 5); //!< Backward Prediction Present Flag 5885 uint32_t Reserved70 : __CODEGEN_BITFIELD(6, 10); //!< Reserved 5886 uint32_t Vc1Profile : __CODEGEN_BITFIELD(11, 11); //!< VC1_PROFILE 5887 uint32_t Reserved76 : __CODEGEN_BITFIELD(12, 14); //!< Reserved 5888 uint32_t Dmvsurfacevalid : __CODEGEN_BITFIELD(15, 15); //!< DmvSurfaceValid 5889 uint32_t MotionVectorMode : __CODEGEN_BITFIELD(16, 19); //!< Motion Vector Mode 5890 uint32_t Reserved84 : __CODEGEN_BITFIELD(20, 22); //!< Reserved 5891 uint32_t InterpolationRounderControl : __CODEGEN_BITFIELD(23, 23); //!< Interpolation Rounder Control 5892 uint32_t BitplaneBufferPitchMinus1 : __CODEGEN_BITFIELD(24, 31); //!< Bitplane Buffer Pitch Minus 1 5893 }; 5894 uint32_t Value; 5895 } DW2; 5896 union 5897 { 5898 struct 5899 { 5900 uint32_t VstransformFlag : __CODEGEN_BITFIELD(0, 0); //!< VSTRANSFORM_FLAG 5901 uint32_t Dquant : __CODEGEN_BITFIELD(1, 2); //!< DQUANT 5902 uint32_t ExtendedMvPresentFlag : __CODEGEN_BITFIELD(3, 3); //!< EXTENDED_MV_PRESENT_FLAG 5903 uint32_t FastuvmcflagFastUvMotionCompensationFlag : __CODEGEN_BITFIELD(4, 4); //!< FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 5904 uint32_t LoopfilterEnableFlag : __CODEGEN_BITFIELD(5, 5); //!< LOOPFILTER_ENABLE_FLAG 5905 uint32_t RefdistFlag : __CODEGEN_BITFIELD(6, 6); //!< REFDIST_FLAG 5906 uint32_t PanscanPresentFlag : __CODEGEN_BITFIELD(7, 7); //!< PANSCAN_PRESENT_FLAG 5907 uint32_t Maxbframes : __CODEGEN_BITFIELD(8, 10); //!< MAXBFRAMES 5908 uint32_t RangeredPresentFlagForSimpleMainProfileOnly : __CODEGEN_BITFIELD(11, 11); //!< RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 5909 uint32_t SyncmarkerPresentFlagForSimpleMainProfileOnly : __CODEGEN_BITFIELD(12, 12); //!< SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 5910 uint32_t MultiresPresentFlagForSimpleMainProfileOnly : __CODEGEN_BITFIELD(13, 13); //!< MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 5911 uint32_t Quantizer : __CODEGEN_BITFIELD(14, 15); //!< QUANTIZER 5912 uint32_t PPicRefDistance : __CODEGEN_BITFIELD(16, 20); //!< P_PIC_REF_DISTANCE 5913 uint32_t Reserved117 : __CODEGEN_BITFIELD(21, 21); //!< Reserved 5914 uint32_t ProgressivePicType : __CODEGEN_BITFIELD(22, 23); //!< PROGRESSIVE_PIC_TYPE 5915 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 27); //!< Reserved 5916 uint32_t RangeReductionEnable : __CODEGEN_BITFIELD(28, 28); //!< RANGE_REDUCTION_ENABLE 5917 uint32_t RangeReductionScale : __CODEGEN_BITFIELD(29, 29); //!< RANGE_REDUCTION_SCALE 5918 uint32_t OverlapSmoothingEnableFlag : __CODEGEN_BITFIELD(30, 30); //!< OVERLAP_SMOOTHING_ENABLE_FLAG 5919 uint32_t Reserved127 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 5920 }; 5921 uint32_t Value; 5922 } DW3; 5923 union 5924 { 5925 struct 5926 { 5927 uint32_t ExtendedDmvPresentFlag : __CODEGEN_BITFIELD(0, 0); //!< EXTENDED_DMV_PRESENT_FLAG 5928 uint32_t Psf : __CODEGEN_BITFIELD(1, 1); //!< PSF 5929 uint32_t RefpicFlag : __CODEGEN_BITFIELD(2, 2); //!< REFPIC_FLAG 5930 uint32_t Finterflag : __CODEGEN_BITFIELD(3, 3); //!< FINTERFLAG 5931 uint32_t Tfcntrflag : __CODEGEN_BITFIELD(4, 4); //!< TFCNTRFLAG 5932 uint32_t Interlace : __CODEGEN_BITFIELD(5, 5); //!< INTERLACE 5933 uint32_t Pulldown : __CODEGEN_BITFIELD(6, 6); //!< PULLDOWN 5934 uint32_t PostprocFlag : __CODEGEN_BITFIELD(7, 7); //!< POSTPROC Flag 5935 uint32_t _4MvAllowedFlag : __CODEGEN_BITFIELD(8, 8); //!< 4MV Allowed Flag 5936 uint32_t Reserved137 : __CODEGEN_BITFIELD(9, 23); //!< Reserved 5937 uint32_t BfractionEnumeration : __CODEGEN_BITFIELD(24, 28); //!< BFraction Enumeration 5938 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 5939 }; 5940 uint32_t Value; 5941 } DW4; 5942 5943 //! \name Local enumerations 5944 5945 enum SUBOPCODE_B 5946 { 5947 SUBOPCODE_B_UNNAMED0 = 0, //!< No additional details 5948 }; 5949 5950 enum SUBOPCODE_A 5951 { 5952 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 5953 }; 5954 5955 enum MEDIA_COMMAND_OPCODE 5956 { 5957 MEDIA_COMMAND_OPCODE_VC1DEC = 2, //!< No additional details 5958 }; 5959 5960 enum PIPELINE 5961 { 5962 PIPELINE_MFDVC1SHORTPICSTATE = 2, //!< No additional details 5963 }; 5964 5965 enum COMMAND_TYPE 5966 { 5967 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5968 }; 5969 5970 //! \brief PICTURE_STRUCTURE 5971 //! \details 5972 //! This field is used in both VC1 VLD mode and IT mode. It is the same 5973 //! parameter as bPicStructure in VC1 spec.The Picture Structure and 5974 //! Progressive Pic Type are used to derive the picture structure as 5975 //! specified in FCM, in VC1 VLD and IT mode. 5976 enum PICTURE_STRUCTURE 5977 { 5978 PICTURE_STRUCTURE_UNNAMED0 = 0, //!< illegal 5979 PICTURE_STRUCTURE_UNNAMED1 = 1, //!< top field (bit 0) 5980 PICTURE_STRUCTURE_UNNAMED2 = 2, //!< bottom field (bit 1) 5981 PICTURE_STRUCTURE_UNNAMED3 = 3, //!< frame (both fields are present) 5982 }; 5983 5984 //! \brief INTRA_PICTURE_FLAG 5985 //! \details 5986 //! This field is used in both VC1 VLD mode and IT mode. It is the same 5987 //! parameter as bPicIntra in VC1 spec. The Intra Picture Flag, Backward 5988 //! Prediction Present Flag and RefPicFlag are used to derive the picture 5989 //! type, as specified in PTYPE for a frame, and in FPTYPE for a field, in 5990 //! VC1 VLD and IT mode. 5991 enum INTRA_PICTURE_FLAG 5992 { 5993 INTRA_PICTURE_FLAG_UNNAMED0 = 0, //!< entire picture can have a mixture of intra and inter MB type or just inter MB type. 5994 INTRA_PICTURE_FLAG_UNNAMED1 = 1, //!< entire picture is coded in intra MB type 5995 }; 5996 5997 //! \brief VC1_PROFILE 5998 //! \details 5999 //! specifies the bitstream profile.Note: This is required because 128 is 6000 //! added for intra blocks post inverse transform in advanced profile and 6001 //! also to find out if Motion vectors are adjusted or not.This field is 6002 //! used in both VLD and IT modes. 6003 enum VC1_PROFILE 6004 { 6005 VC1_PROFILE_UNNAMED0 = 0, //!< current picture is in Simple or Main Profile (No need to distinguish Simple and Main Profile) 6006 VC1_PROFILE_UNNAMED1 = 1, //!< current picture is in Advanced Profile 6007 }; 6008 6009 enum VSTRANSFORM_FLAG 6010 { 6011 VSTRANSFORM_FLAG_DISABLE = 0, //!< variable-sized transform coding is not enabled 6012 VSTRANSFORM_FLAG_ENABLE = 1, //!< variable-sized transform coding is enabled 6013 }; 6014 6015 //! \brief DQUANT 6016 //! \details 6017 //! Use for Picture Header Parsing of VOPDUANT elements 6018 enum DQUANT 6019 { 6020 DQUANT_UNNAMED0 = 0, //!< no VOPDQUANT elements; Quantizer cannot vary in frame, same quantization step size PQUANT is used for all MBs in the frame 6021 DQUANT_UNNAMED1 = 1, //!< refer to VC1 Spec. for all the MB position dependent quantizer selection 6022 DQUANT_UNNAMED2 = 2, //!< The macroblocks located on the picture edge boundary shall be quantized with ALTPQUANT while the rest of the macroblocks shall be quantized with PQUANT. 6023 }; 6024 6025 //! \brief EXTENDED_MV_PRESENT_FLAG 6026 //! \details 6027 //! BitFieldDesc 6028 enum EXTENDED_MV_PRESENT_FLAG 6029 { 6030 EXTENDED_MV_PRESENT_FLAG_UNNAMED0 = 0, //!< Extended_MV is not present in the picture header 6031 EXTENDED_MV_PRESENT_FLAG_UNNAMED1 = 1, //!< Extended_MV is present in the picture header 6032 }; 6033 6034 //! \brief FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6035 //! \details 6036 //! This field specifies whether the motion vectors forUV is rounded to half 6037 //! or full pel position. It is identical to the variableFASTUVMC in VC1 6038 //! standard.This field is used in both VLD and IT modes.It isderived from 6039 //! FASTUVMC = (bPicSpatialResid8 >> 4) & 1 in both VLD andIT 6040 //! modes, and should have the same value as Motion Vector ModeLSBit. 6041 enum FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6042 { 6043 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED0 = 0, //!< no rounding 6044 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED1 = 1, //!< quarter-pel offsets to half/full pel positions 6045 }; 6046 6047 //! \brief LOOPFILTER_ENABLE_FLAG 6048 //! \details 6049 //! This filed is the decoded syntax element LOOPFILTER in bitstream. It 6050 //! indicates if In-loop Deblocking is ON according to picture level 6051 //! bitstream syntax control. This bit affects BSD unit and also the loop 6052 //! filter unit.When this bit is set to 1, PostDeblockOutEnable field in 6053 //! MFX_PIPE_MODE_SELECT command must also be set to 1. In this case, 6054 //! in-loop deblocking operation follows the VC1 standard - deblocking 6055 //! doesn't cross slice boundary.When this bit is set to 0, but 6056 //! PostDeblockOutEnable field in MFX_PIPE_MODE_SELECT command is set to 1. 6057 //! It indicates the loop filter unit is used for out-of-loop deblocking. In 6058 //! this case, deblocking operation does cross slice boundary.This field is 6059 //! used in VLD mode only, not in IT mode. 6060 enum LOOPFILTER_ENABLE_FLAG 6061 { 6062 LOOPFILTER_ENABLE_FLAG_UNNAMED0 = 0, //!< In-Loop-Deblocking-Filter is disabled 6063 LOOPFILTER_ENABLE_FLAG_UNNAMED1 = 1, //!< In-Loop-Deblocking-Filter is enabled 6064 }; 6065 6066 enum PANSCAN_PRESENT_FLAG 6067 { 6068 PANSCAN_PRESENT_FLAG_UNNAMED0 = 0, //!< Pan Scan Parameters are not present in the picture header 6069 PANSCAN_PRESENT_FLAG_UNNAMED1 = 1, //!< Pan Scan Parameters are present in the picture header 6070 }; 6071 6072 //! \brief RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6073 //! \details 6074 //! It is needed for Picture Header Parsing.Driver is responsible to keep 6075 //! RangeReductionScale, RangeReduction Enable and RANGERED Present Flag of 6076 //! current picture coherent. 6077 enum RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6078 { 6079 RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED0 = 0, //!< Range Reduction Parameter (RANGEREDFRM) is not present in the picture header 6080 RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED1 = 1, //!< Range Reduction Parameter (RANGEREDFRM) is present in the picture header. 6081 }; 6082 6083 enum SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6084 { 6085 SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED0 = 0, //!< Bitstream for Simple and Main Profile has no sync marker 6086 SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED1 = 1, //!< Bitstream for Simple and Main Profile may have sync marker(s) 6087 }; 6088 6089 enum MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6090 { 6091 MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED0 = 0, //!< RESPIC Parameter is present in the picture header 6092 MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED1 = 1, //!< RESPIC Parameter is present in the picture header 6093 }; 6094 6095 enum QUANTIZER 6096 { 6097 QUANTIZER_UNNAMED0 = 0, //!< implicit quantizer at frame leve 6098 QUANTIZER_UNNAMED1 = 1, //!< explicit quantizer at frame level, and use PQUANTIZER SE to specify uniform or non-uniform 6099 QUANTIZER_UNNAMED2 = 2, //!< explicit quantizer, and non-uniform quantizer for all frames 6100 QUANTIZER_UNNAMED3 = 3, //!< explicit quantizer, and uniform quantizer for all frames 6101 }; 6102 6103 //! \brief P_PIC_REF_DISTANCE 6104 //! \details 6105 //! This element defines the number of frames between the current frame and 6106 //! the reference frame. It is the same as the REFDIST SE in VC1 interlaced 6107 //! field picture header. It is present if the entry-level flag REFDIST_FLAG 6108 //! == 1, and if the picture type is not one of the following types: B/B, 6109 //! B/BI, BI/B, BI/BI. If the entry level flag REFDIST_FLAG == 0, REFDIST 6110 //! shall be set to the default value of 0.This field is used in VC1 VLD 6111 //! mode only, not used in IT and intel VC1 VLD Long Format modes. 6112 enum P_PIC_REF_DISTANCE 6113 { 6114 P_PIC_REF_DISTANCE_UNNAMED0 = 0, //!< No additional details 6115 }; 6116 6117 //! \brief PROGRESSIVE_PIC_TYPE 6118 //! \details 6119 //! This field is used in both VC1 VLD mode and IT mode. It is the same 6120 //! parameter as bPicExtrapolation in VC1 spec.The Picture Structure and 6121 //! Progressive Pic Type are used to derive the picture structure as 6122 //! specified in FCM, in VC1 VLD and IT mode. 6123 enum PROGRESSIVE_PIC_TYPE 6124 { 6125 PROGRESSIVE_PIC_TYPE_UNNAMED0 = 0, //!< progressive only picture 6126 PROGRESSIVE_PIC_TYPE_UNNAMED1 = 1, //!< progressive only picture 6127 PROGRESSIVE_PIC_TYPE_UNNAMED2 = 2, //!< interlace picture (frame-interlace or field-interlace) 6128 PROGRESSIVE_PIC_TYPE_UNNAMED3 = 3, //!< illegal 6129 }; 6130 6131 //! \brief RANGE_REDUCTION_ENABLE 6132 //! \details 6133 //! This field specifies whether on-the-fly pixel valuerange reduction 6134 //! should be performed for the preceding (or forward) referencepicture. 6135 //! Along with RangeReductionScale to specify whether scale up or downshould 6136 //! be performed. It is not the same value as RANGEREDFRM Syntax 6137 //! Element(PictureParameters bPicDeblocked bit 5) in the Picture 6138 //! Header.This field isfor Main Profile only. Simple Profile is always 6139 //! disable, and not applicable toAdvanced Profile. This field is used in 6140 //! both VLD and IT modes.This is derived bydriver from the history of 6141 //! RANGERED and RANGEREDFRM syntax elements (i.e. offorward/preceding 6142 //! reference picture) and those of the current picture.RANGEREDis the same 6143 //! as (bPicOverflowBlocks >> 3) & 1. RANGEREDFRM is the sameas 6144 //! (bPicDeblocked >> 5) & 1.For the current picture is a B 6145 //! picture,this field represents the state of the forward/preceding 6146 //! reference pictureonlyDriver is responsible to keep RangeReductionScale, 6147 //! RangeReduction Enable andRANGERED Present Flag of current picture 6148 //! coherent. 6149 enum RANGE_REDUCTION_ENABLE 6150 { 6151 RANGE_REDUCTION_ENABLE_DISABLE = 0, //!< Range reduction is not performed 6152 RANGE_REDUCTION_ENABLE_ENABLE = 1, //!< Range reduction is performed 6153 }; 6154 6155 //! \brief RANGE_REDUCTION_SCALE 6156 //! \details 6157 //! This field specifies whether the reference picturepixel values should be 6158 //! scaled up or scaled down on-the-fly, if RangeReduction isEnabled.NOTE: 6159 //! This bit is derived by driver for Main Profile only. Ignored inSimple 6160 //! and Advanced Profiles. This field is used in both VLD and IT 6161 //! modes.Thisis derived by driver from the history of RANGERED and 6162 //! RANGEREDFRM syntaxelements (i.e. of forward/preceding reference picture) 6163 //! and those of the currentpicture. RANGERED is the same as 6164 //! (bPicOverflowBlocks >> 3) & 1.RANGEREDFRM is the same as 6165 //! (bPicDeblocked >> 5) & 1. For the currentpicture is a B 6166 //! picture, this field represents the state of the 6167 //! forward/precedingreference picture onlyDriver is responsible to keep 6168 //! RangeReductionScale,RangeReduction Enable and RANGERED Present Flag of 6169 //! current picturecoherent. 6170 enum RANGE_REDUCTION_SCALE 6171 { 6172 RANGE_REDUCTION_SCALE_DISABLE = 0, //!< Scale down reference picture by factor of 2 6173 RANGE_REDUCTION_SCALE_ENABLE = 1, //!< Scale up reference picture by factor of 2 6174 }; 6175 6176 //! \brief OVERLAP_SMOOTHING_ENABLE_FLAG 6177 //! \details 6178 //! This field is the decoded syntax element OVERLAP in bitstreamIndicates 6179 //! if Overlap smoothing is ON at the picture levelThis field is used in 6180 //! both VLD and IT modes 6181 enum OVERLAP_SMOOTHING_ENABLE_FLAG 6182 { 6183 OVERLAP_SMOOTHING_ENABLE_FLAG_DISABLE = 0, //!< to disable overlap smoothing filter 6184 OVERLAP_SMOOTHING_ENABLE_FLAG_ENABLE = 1, //!< to enable overlap smoothing filter 6185 }; 6186 6187 enum EXTENDED_DMV_PRESENT_FLAG 6188 { 6189 EXTENDED_DMV_PRESENT_FLAG_UNNAMED0 = 0, //!< Extended_DMV is not present in the picture header 6190 EXTENDED_DMV_PRESENT_FLAG_UNNAMED1 = 1, //!< Extended_DMV is present in the picture header 6191 }; 6192 6193 //! \brief REFPIC_FLAG 6194 //! \details 6195 //! For a BI picture, REFPIC flag must set to 0For I and P picture, REFPIC 6196 //! flag must set to 0.For a B picture, REFPIC flag must set to 0, except 6197 //! for a B-field in interlaced field mode which can be 0 or 1 (e.g. the top 6198 //! B field can be used as a reference for decoding its corresponding bottom 6199 //! B-field in a field pair).In VLD mode, this flag cannot be used as an 6200 //! optimization signaling for an I or P picture that is not used as a 6201 //! reference picture.This field is used in both VC1 VLD mode and IT mode. 6202 //! It is the same parameter as bPicDeblockConfined[bit2] in VC1 spec.The 6203 //! Intra Picture Flag, Backward Prediction Present Flag and RefPicFlag are 6204 //! used to derive the picture type, as specified in PTYPE for a frame, and 6205 //! in FPTYPE for a field, in VC1 VLD and IT mode. 6206 enum REFPIC_FLAG 6207 { 6208 REFPIC_FLAG_UNNAMED0 = 0, //!< the current picture after decoded, will never used as a reference picture 6209 REFPIC_FLAG_UNNAMED1 = 1, //!< the current picture after decoded, will be used as a reference picture later 6210 }; 6211 6212 //! \name Initializations 6213 6214 //! \brief Explicit member initialization function 6215 MFD_VC1_SHORT_PIC_STATE_CMD(); 6216 6217 static const size_t dwSize = 5; 6218 static const size_t byteSize = 20; 6219 }; 6220 6221 //! 6222 //! \brief MFX_VC1_DIRECTMODE_STATE 6223 //! \details 6224 //! This is a picture level command and should be issued only once, even for 6225 //! a multi-slices picture. There is only one DMV buffer for read (when 6226 //! processing a B-picture) and one for write (when processing a P-Picture). 6227 //! Each DMV record is 64 bits per MB, to store the top and bottom field 6228 //! Motion Vectors (32-bit MVx,y each). 6229 //! 6230 struct MFX_VC1_DIRECTMODE_STATE_CMD 6231 { 6232 union 6233 { 6234 struct 6235 { 6236 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 6237 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 6238 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 6239 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 6240 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 6241 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 6242 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 6243 }; 6244 uint32_t Value; 6245 } DW0; 6246 SPLITBASEADDRESS64BYTEALIGNED_CMD DirectMvWriteBufferBaseAddress; //!< DW1..2, Direct MV Write Buffer - Base Address 6247 MEMORYADDRESSATTRIBUTES_CMD DirectMvWriteBufferAttributes; //!< DW3, Direct MV Write Buffer - Attributes 6248 SPLITBASEADDRESS64BYTEALIGNED_CMD DirectMvReferenceBufferBaseAddress; //!< DW4..5, Direct MV Reference Buffer - Base Address 6249 MEMORYADDRESSATTRIBUTES_CMD DirectMvReferenceBufferAttributes; //!< DW6, Direct MV Reference Buffer - Attributes 6250 6251 //! \name Local enumerations 6252 6253 enum SUBOPCODE_B 6254 { 6255 SUBOPCODE_B_UNNAMED2 = 2, //!< No additional details 6256 }; 6257 6258 enum SUBOPCODE_A 6259 { 6260 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 6261 }; 6262 6263 enum MEDIA_COMMAND_OPCODE 6264 { 6265 MEDIA_COMMAND_OPCODE_VC1COMMON = 2, //!< No additional details 6266 }; 6267 6268 enum PIPELINE 6269 { 6270 PIPELINE_MFXVC1DIRECTMODESTATE = 2, //!< No additional details 6271 }; 6272 6273 enum COMMAND_TYPE 6274 { 6275 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6276 }; 6277 6278 //! \name Initializations 6279 6280 //! \brief Explicit member initialization function 6281 MFX_VC1_DIRECTMODE_STATE_CMD(); 6282 6283 static const size_t dwSize = 7; 6284 static const size_t byteSize = 28; 6285 }; 6286 6287 //! 6288 //! \brief MFD_VC1_BSD_OBJECT 6289 //! \details 6290 //! The MFD_VC1_BSD_OBJECT command is the only primitive command for the VC1 6291 //! Decoding Pipeline. The macroblock data portion of the bitstream is 6292 //! loaded as indirect data object.Before issuing a MFD_VC1_BSD_OBJECT 6293 //! command, all VC1 states of the MFD Engine need to be valid. Therefore 6294 //! the commands used to set these states need to have been issued prior to 6295 //! the issue of a MFD_VC1_BSD_OBJECT command.VC1 deblock filter kernel 6296 //! cross the slice boundary if in the last MB row of a slice, so need to 6297 //! know the last MB row of a slice to disable the edge mask. There is why 6298 //! VC1 BSD hardware need to know the end of MB address for the current 6299 //! slice. As such no more phantom slice is needed for VC1, as long as the 6300 //! driver will program both start MB address in the current slice and the 6301 //! start MB address of the next slice. As a result, we can also support 6302 //! multiple picture state commands in between slices. 6303 //! 6304 struct MFD_VC1_BSD_OBJECT_CMD 6305 { 6306 union 6307 { 6308 struct 6309 { 6310 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 6311 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 6312 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 6313 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 6314 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 6315 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 6316 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 6317 }; 6318 uint32_t Value; 6319 } DW0; 6320 union 6321 { 6322 struct 6323 { 6324 uint32_t IndirectBsdDataLength : __CODEGEN_BITFIELD(0, 23); //!< Indirect BSD Data Length 6325 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 6326 }; 6327 uint32_t Value; 6328 } DW1; 6329 union 6330 { 6331 struct 6332 { 6333 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD(0, 28); //!< INDIRECT_DATA_START_ADDRESS 6334 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 6335 }; 6336 uint32_t Value; 6337 } DW2; 6338 union 6339 { 6340 struct 6341 { 6342 uint32_t NextSliceVerticalPosition : __CODEGEN_BITFIELD(0, 8); //!< Next Slice Vertical Position 6343 uint32_t Reserved105 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 6344 uint32_t SliceStartVerticalPosition : __CODEGEN_BITFIELD(16, 23); //!< Slice Start Vertical Position 6345 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 6346 }; 6347 uint32_t Value; 6348 } DW3; 6349 union 6350 { 6351 struct 6352 { 6353 uint32_t FirstmbbitoffsetFirstMacroblockBitOffset : __CODEGEN_BITFIELD(0, 2); //!< FirstMbBitOffset (First Macroblock Bit Offset ) 6354 uint32_t Reserved131 : __CODEGEN_BITFIELD(3, 3); //!< Reserved 6355 uint32_t EmulationPreventionBytePresent : __CODEGEN_BITFIELD(4, 4); //!< EMULATION_PREVENTION_BYTE_PRESENT 6356 uint32_t Reserved133 : __CODEGEN_BITFIELD(5, 15); //!< Reserved 6357 uint32_t FirstMbByteOffsetOfSliceDataOrSliceHeader : __CODEGEN_BITFIELD(16, 31); //!< First_MB_Byte_Offset of Slice Data or Slice Header 6358 }; 6359 uint32_t Value; 6360 } DW4; 6361 6362 //! \name Local enumerations 6363 6364 enum SUBOPCODE_B 6365 { 6366 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 6367 }; 6368 6369 enum SUBOPCODE_A 6370 { 6371 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 6372 }; 6373 6374 enum MEDIA_COMMAND_OPCODE 6375 { 6376 MEDIA_COMMAND_OPCODE_VC1DEC = 2, //!< No additional details 6377 }; 6378 6379 enum PIPELINE 6380 { 6381 PIPELINE_MFXMULTIDW = 2, //!< No additional details 6382 }; 6383 6384 enum COMMAND_TYPE 6385 { 6386 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6387 }; 6388 6389 //! \brief INDIRECT_DATA_START_ADDRESS 6390 //! \details 6391 //! This field specifies the Graphics Memory starting address of the data to 6392 //! be fetched into BSD Unit for processing. This pointer is relative to the 6393 //! MFD Indirect Object Base Address.Hardware ignores this field if indirect 6394 //! data is not present. It is a byte-aligned address for the VC1 bitstream 6395 //! data. 6396 enum INDIRECT_DATA_START_ADDRESS 6397 { 6398 INDIRECT_DATA_START_ADDRESS_UNNAMED0 = 0, //!< No additional details 6399 INDIRECT_DATA_START_ADDRESS_UNNAMED512 = 512, //!< No additional details 6400 }; 6401 6402 enum EMULATION_PREVENTION_BYTE_PRESENT 6403 { 6404 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED0 = 0, //!< H/W needs to perform Emulation Byte Removal 6405 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED1 = 1, //!< H/W does not need to perform Emulation Byte Removal 6406 }; 6407 6408 //! \name Initializations 6409 6410 //! \brief Explicit member initialization function 6411 MFD_VC1_BSD_OBJECT_CMD(); 6412 6413 static const size_t dwSize = 5; 6414 static const size_t byteSize = 20; 6415 }; 6416 6417 //! 6418 //! \brief MFX_JPEG_PIC_STATE 6419 //! \details 6420 //! 6421 //! 6422 struct MFX_JPEG_PIC_STATE_CMD 6423 { 6424 union 6425 { 6426 struct 6427 { 6428 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 6429 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 6430 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 6431 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 6432 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 6433 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 6434 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 6435 }; 6436 uint32_t Value; 6437 } DW0; 6438 union 6439 { 6440 struct 6441 { 6442 uint32_t OutputMcuStructure : __CODEGEN_BITFIELD(0, 2); //!< OUTPUT_MCU_STRUCTURE, Encoder Only 6443 uint32_t Reserved35 : __CODEGEN_BITFIELD(3, 7); //!< Reserved, Encoder Only 6444 uint32_t InputSurfaceFormatYuv : __CODEGEN_BITFIELD(8, 11); //!< INPUT_SURFACE_FORMAT_YUV, Encoder Only 6445 uint32_t Reserved44 : __CODEGEN_BITFIELD(12, 20); //!< Reserved, Encoder Only 6446 uint32_t PixelsInVerticalLastMcu : __CODEGEN_BITFIELD(21, 25); //!< Pixels In Vertical Last MCU, Encoder Only 6447 uint32_t PixelsInHorizontalLastMcu : __CODEGEN_BITFIELD(26, 30); //!< Pixels In Horizontal Last MCU, Encoder Only 6448 uint32_t Reserved63 : __CODEGEN_BITFIELD(31, 31); //!< Reserved, Encoder Only 6449 } Obj0; 6450 struct 6451 { 6452 uint32_t InputFormatYuv : __CODEGEN_BITFIELD(0, 2); //!< INPUT_FORMAT_YUV, Decoder Only 6453 uint32_t Reserved35 : __CODEGEN_BITFIELD(3, 3); //!< Reserved, Decoder Only 6454 uint32_t Rotation : __CODEGEN_BITFIELD(4, 5); //!< ROTATION, Decoder Only 6455 uint32_t Reserved38 : __CODEGEN_BITFIELD(6, 7); //!< Reserved, Decoder Only 6456 uint32_t OutputFormatYuv : __CODEGEN_BITFIELD(8, 11); //!< OUTPUT_FORMAT_YUV, Decoder Only 6457 uint32_t Reserved44 : __CODEGEN_BITFIELD(12, 15); //!< Reserved, Decoder Only 6458 uint32_t AverageDownSampling : __CODEGEN_BITFIELD(16, 16); //!< AVERAGE_DOWN_SAMPLING, Decoder Only 6459 uint32_t VerticalDownSamplingEnable : __CODEGEN_BITFIELD(17, 17); //!< VERTICAL_DOWN_SAMPLING_ENABLE, Decoder Only 6460 uint32_t HorizontalDownSamplingEnable : __CODEGEN_BITFIELD(18, 18); //!< HORIZONTAL_DOWN_SAMPLING_ENABLE, Decoder Only 6461 uint32_t Reserved51 : __CODEGEN_BITFIELD(19, 19); //!< Reserved, Decoder Only 6462 uint32_t VerticalUpSamplingEnable : __CODEGEN_BITFIELD(20, 20); //!< VERTICAL_UP_SAMPLING_ENABLE, Decoder Only 6463 uint32_t Reserved53 : __CODEGEN_BITFIELD(21, 31); //!< Reserved, Decoder Only 6464 } Obj1; 6465 uint32_t Value; 6466 } DW1; 6467 union 6468 { 6469 struct 6470 { 6471 uint32_t FrameWidthInBlocksMinus1 : __CODEGEN_BITFIELD(0, 12); //!< Frame Width In Blocks Minus 1, Decoder Only 6472 uint32_t Reserved77 : __CODEGEN_BITFIELD(13, 15); //!< Reserved, Decoder Only 6473 uint32_t FrameHeightInBlocksMinus1 : __CODEGEN_BITFIELD(16, 28); //!< Frame Height In Blocks Minus 1, Decoder Only 6474 uint32_t OutputPixelNormalize : __CODEGEN_BITFIELD(29, 29); //!< OUTPUT_PIXEL_NORMALIZE, Decoder Only 6475 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31); //!< Reserved, Decoder Only 6476 } Obj0; 6477 struct 6478 { 6479 uint32_t FrameWidthInBlksMinus1 : __CODEGEN_BITFIELD(0, 12); //!< Frame Width In Blks Minus 1, Encoder Only 6480 uint32_t Roundingquant : __CODEGEN_BITFIELD(13, 15); //!< ROUNDINGQUANT, Encoder Only 6481 uint32_t FrameHeightInBlksMinus1 : __CODEGEN_BITFIELD(16, 28); //!< Frame Height In Blks Minus 1, Encoder Only 6482 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31); //!< Reserved, Encoder Only 6483 } Obj1; 6484 uint32_t Value; 6485 } DW2; 6486 6487 //! \name Local enumerations 6488 6489 enum SUBOPCODE_B 6490 { 6491 SUBOPCODE_B_MEDIA = 0, //!< No additional details 6492 }; 6493 6494 enum SUBOPCODE_A 6495 { 6496 SUBOPCODE_A_COMMON = 0, //!< No additional details 6497 }; 6498 6499 enum MEDIA_COMMAND_OPCODE 6500 { 6501 MEDIA_COMMAND_OPCODE_JPEG = 7, //!< No additional details 6502 }; 6503 6504 enum PIPELINE 6505 { 6506 PIPELINE_MFXMULTIDW = 2, //!< No additional details 6507 }; 6508 6509 enum COMMAND_TYPE 6510 { 6511 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6512 }; 6513 6514 //! \brief OUTPUT_MCU_STRUCTURE 6515 //! \details 6516 //! />Output MCU Structure(OutputMcuStructure) should be set 6517 //! accordingly for each Input Surface Format 6518 //! YUV(InputSurfaceFormatYUV):If 6519 //! InputSurfaceFormatYUV is set to NV12, OutputMCUStructure 6520 //! is set to YUV420. 6521 //If InputSurfaceFormatYUV is set to UYVY 6522 //! or YUY2, OutputMCUStructure is set to YUV422H_2Y. 6523 //If 6524 //! InputSurfaceFormatYUV is set to Y8, OutputMCuStructure is 6525 //! set to YUV400. 6526 //If InputSurfaceFormatYUV is set to RGB (or 6527 //! GBR, BGR, YUV), OutputMCuStructure is set to RGB. 6528 //If 6529 //! InputSurfaceFormatYUV is set to RGB, the order of encoded blocks 6530 //! in MCU will be same as the order of input image components. If the order 6531 //! of input image components is RGB (or GBR, BGR, YUV), then the order of 6532 //! blocks will be RGB (or GBR, BGR, YUV respectively). 6533 /// > 6534 enum OUTPUT_MCU_STRUCTURE 6535 { 6536 OUTPUT_MCU_STRUCTURE_YUV400 = 0, //!< Grayscale Image 6537 OUTPUT_MCU_STRUCTURE_YUV420 = 1, //!< Both horizontally and vertically chroma 2:1 subsampled 6538 OUTPUT_MCU_STRUCTURE_YUV422H2Y = 2, //!< Horizontally chroma 2:1 subsampled - horizontal 2 Y-blocks, 1 U and 1 V block 6539 OUTPUT_MCU_STRUCTURE_RGB = 3, //!< RGB or YUV444: No subsample 6540 OUTPUT_MCU_STRUCTURE_UNNAMED4 = 4, //!< Reserved for YUV411: Horizontally chroma 4:1 subsampled -- horizontal 4 Y-block, 1U and 1V 6541 OUTPUT_MCU_STRUCTURE_UNNAMED5 = 5, //!< Reserved for YUV422V_2Y: Vertically chroma 2:1 subsampled - vertical 2 Y-blocks, 1U and 1V 6542 OUTPUT_MCU_STRUCTURE_UNNAMED6 = 6, //!< Reserved for YUV422H_4Y: Horizontally chroma 2:1 subsampled - 2x2 Y-blocks, vertical 2U and 2V 6543 OUTPUT_MCU_STRUCTURE_UNNAMED7 = 7, //!< Reserved for YUV422V_4Y: Vertically chroma 2:1 subsampled - 2x2 Y-blocks, horizontal 2U and 2V 6544 }; 6545 6546 enum INPUT_FORMAT_YUV 6547 { 6548 INPUT_FORMAT_YUV_UNNAMED0 = 0, //!< YUV400 (grayscale image) 6549 INPUT_FORMAT_YUV_UNNAMED1 = 1, //!< YUV420 6550 INPUT_FORMAT_YUV_UNNAMED2 = 2, //!< YUV422H_2Y (Horizontally chroma 2:1 subsampled) - horizontal 2 Y-block, 1U and 1V 6551 INPUT_FORMAT_YUV_UNNAMED3 = 3, //!< YUV444 6552 INPUT_FORMAT_YUV_UNNAMED4 = 4, //!< YUV411 6553 INPUT_FORMAT_YUV_UNNAMED5 = 5, //!< YUV422V_2Y (Vertically chroma 2:1 subsampled) - vertical 2 Y-blocks, 1U and 1V 6554 INPUT_FORMAT_YUV_UNNAMED6 = 6, //!< YUV422H_4Y - 2x2 Y-blocks, vertical 2U and 2V 6555 INPUT_FORMAT_YUV_UNNAMED7 = 7, //!< YUV422V_4Y - 2x2 Y-blocks, horizontal 2U and 2V 6556 }; 6557 6558 //! \brief ROTATION 6559 //! \details 6560 //! Rotation can be set to 01b, 10b, or 11b when OutputFormatYUV is set to 6561 //! 0000b. For other OutputFormatYUV, Rotation is not allowed. 6562 enum ROTATION 6563 { 6564 ROTATION_UNNAMED0 = 0, //!< no rotation 6565 ROTATION_UNNAMED1 = 1, //!< rotate clockwise 90 degree 6566 ROTATION_UNNAMED2 = 2, //!< rotate counter-clockwise 90 degree (same as rotating 270 degree clockwise) 6567 ROTATION_UNNAMED3 = 3, //!< rotate 180 degree (NOT the same as flipped on the x-axis) 6568 }; 6569 6570 //! \brief OUTPUT_FORMAT_YUV 6571 //! \details 6572 //! This field specifies the surface format to write the decoded JPEG 6573 //! image.Note that any non-interleaved JPEG input should be set to "0000". 6574 //! For the interleaved input Scan data, it can be set either "0000" or the 6575 //! corresponding format. 6576 enum OUTPUT_FORMAT_YUV 6577 { 6578 OUTPUT_FORMAT_YUV_UNNAMED0 = 0, //!< 3 separate plane for Y, U, and V respectively 6579 OUTPUT_FORMAT_YUV_UNNAMED1 = 1, //!< NV12 for chroma 4:2:0 6580 OUTPUT_FORMAT_YUV_UNNAMED2 = 2, //!< UYVY for chroma 4:2:2 6581 OUTPUT_FORMAT_YUV_UNNAMED3 = 3, //!< YUY2 for chroma 4:2:2 6582 }; 6583 6584 //! \brief INPUT_SURFACE_FORMAT_YUV 6585 //! \details 6586 //! This field specifies the surface format to read a YUV image data 6587 enum INPUT_SURFACE_FORMAT_YUV 6588 { 6589 INPUT_SURFACE_FORMAT_YUV_UNNAMED0 = 0, //!< Reserved 6590 INPUT_SURFACE_FORMAT_YUV_NV12 = 1, //!< NV12 for chroma 4:2:0 6591 INPUT_SURFACE_FORMAT_YUV_UYVY = 2, //!< UYVY for chroma 4:2:2 6592 INPUT_SURFACE_FORMAT_YUV_YUY2 = 3, //!< YUY2 for chroma 4:2:2 6593 INPUT_SURFACE_FORMAT_YUV_Y8 = 4, //!< Y8 for chroma400 Y-only image 6594 INPUT_SURFACE_FORMAT_YUV_RGB = 5, //!< RGB or YUV for chroma 4:4:4 6595 }; 6596 6597 //! \brief AVERAGE_DOWN_SAMPLING 6598 //! \details 6599 //! This flag is used to select a down-sampling method when 6600 //! VertDownSamplingEnb or HoriDownSamplingEnb is set to 1. 6601 enum AVERAGE_DOWN_SAMPLING 6602 { 6603 AVERAGE_DOWN_SAMPLING_UNNAMED0 = 0, //!< Drop every other line (or column) pixels 6604 AVERAGE_DOWN_SAMPLING_UNNAMED1 = 1, //!< Average neighboring two pixels 6605 }; 6606 6607 //! \brief VERTICAL_DOWN_SAMPLING_ENABLE 6608 //! \details 6609 //! Only applied to chroma blocks. This flag is used for 2:1 vertical 6610 //! down-sampling for chroma 422 and outputting chroma420 NV21 format. To 6611 //! enable this flag, the input should be interleaved Scan, 6612 //! InputFormatYUV should be set to YUV422H_2Y or YUV422H_4Y, and 6613 //! OutputFormatYUV should be set to NV12. 6614 enum VERTICAL_DOWN_SAMPLING_ENABLE 6615 { 6616 VERTICAL_DOWN_SAMPLING_ENABLE_UNNAMED0 = 0, //!< no down-sampling 6617 VERTICAL_DOWN_SAMPLING_ENABLE_UNNAMED1 = 1, //!< 2:1 vertical down-sampling 6618 }; 6619 6620 //! \brief HORIZONTAL_DOWN_SAMPLING_ENABLE 6621 //! \details 6622 //! Only applied to chroma blocks. This flag is used for 2:1 horizontal 6623 //! down-sampling for chroma 422 and outputting chroma420 NV21 format. To 6624 //! enable this flag, the input should be interleaved Scan, 6625 //! InputFormatYUV should be set to YUV422V_2Y or YUV422V_4Y, and 6626 //! OutputFormatYUV should be set to NV12. 6627 enum HORIZONTAL_DOWN_SAMPLING_ENABLE 6628 { 6629 HORIZONTAL_DOWN_SAMPLING_ENABLE_UNNAMED0 = 0, //!< no down-sampling 6630 HORIZONTAL_DOWN_SAMPLING_ENABLE_UNNAMED1 = 1, //!< 2:1 horizonatl down-sampling 6631 }; 6632 6633 //! \brief VERTICAL_UP_SAMPLING_ENABLE 6634 //! \details 6635 //! Only applied to chroma blocks. This flag is used for 2:1 vertical 6636 //! up-sampling for chroma 420 and outputting chroma422 YUY2 or UYVY format. 6637 //! To enable this flag, the input should be interleaved Scan, 6638 //! InputFormatYUV should be set to YUV420, and 6639 //! OutputFormatYUV should be set to YUY2 or UYVY. 6640 enum VERTICAL_UP_SAMPLING_ENABLE 6641 { 6642 VERTICAL_UP_SAMPLING_ENABLE_UNNAMED0 = 0, //!< no up-sampling 6643 VERTICAL_UP_SAMPLING_ENABLE_UNNAMED1 = 1, //!< 2:1 vertical up-sampling 6644 }; 6645 6646 //! \brief ROUNDINGQUANT 6647 //! \details 6648 //! Rounding value applied to quantization output 6649 enum ROUNDINGQUANT 6650 { 6651 ROUNDINGQUANT_UNNAMED0 = 0, //!< 1/2 6652 ROUNDINGQUANT_UNNAMED1 = 1, //!< (1/2 - 1/128) 6653 ROUNDINGQUANT_UNNAMED2 = 2, //!< (1/2 + 1/128) 6654 ROUNDINGQUANT_UNNAMED3 = 3, //!< (1/2 - 1/64) 6655 ROUNDINGQUANT_UNNAMED4 = 4, //!< (1/2 + 1/64) 6656 ROUNDINGQUANT_UNNAMED5 = 5, //!< (1/2 - 1/32) 6657 ROUNDINGQUANT_UNNAMED6 = 6, //!< (1/2 - 1/16) 6658 ROUNDINGQUANT_UNNAMED7 = 7, //!< (1/2 - 1/8) 6659 }; 6660 6661 //! \brief OUTPUT_PIXEL_NORMALIZE 6662 //! \details 6663 //! JPEG decoded output pixels for Y and U/V in order to adjust display YUV 6664 //! range. 6665 enum OUTPUT_PIXEL_NORMALIZE 6666 { 6667 OUTPUT_PIXEL_NORMALIZE_UNNAMED0 = 0, //!< No Normalization 6668 OUTPUT_PIXEL_NORMALIZE_UNNAMED1 = 1, //!< Normalize output pixels from [0,255] to [16,239] 6669 }; 6670 6671 //! \name Initializations 6672 6673 //! \brief Explicit member initialization function 6674 MFX_JPEG_PIC_STATE_CMD(); 6675 6676 static const size_t dwSize = 3; 6677 static const size_t byteSize = 12; 6678 }; 6679 6680 //! 6681 //! \brief MFC_JPEG_HUFF_TABLE_STATE 6682 //! \details 6683 //! This Huffman table commands contains both DC and AC tables for either 6684 //! luma or chroma. Once a Huffman table has been defined for a particular 6685 //! destination, it replaces the previous tables stored in that destination 6686 //! and shall be used in the remaining Scans of the current image. Two 6687 //! Huffman tables for luma and chroma will be sent to H/W, and chroma table 6688 //! is used for both U and V. 6689 //! 6690 struct MFC_JPEG_HUFF_TABLE_STATE_CMD 6691 { 6692 union 6693 { 6694 struct 6695 { 6696 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 6697 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 6698 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 6699 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 6700 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 6701 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 6702 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 6703 }; 6704 uint32_t Value; 6705 } DW0; 6706 union 6707 { 6708 struct 6709 { 6710 uint32_t HuffTableId : __CODEGEN_BITFIELD(0, 0); //!< HUFF_TABLE_ID 6711 uint32_t Reserved33 : __CODEGEN_BITFIELD(1, 31); //!< Reserved 6712 }; 6713 uint32_t Value; 6714 } DW1; 6715 uint32_t DcTable[12]; //!< DC_TABLE 6716 uint32_t AcTable[162]; //!< AC_TABLE 6717 6718 //! \name Local enumerations 6719 6720 enum SUBOPCODE_B 6721 { 6722 SUBOPCODE_B_MEDIA = 3, //!< No additional details 6723 }; 6724 6725 enum SUBOPCODE_A 6726 { 6727 SUBOPCODE_A_COMMON = 2, //!< No additional details 6728 }; 6729 6730 enum MEDIA_COMMAND_OPCODE 6731 { 6732 MEDIA_COMMAND_OPCODE_JPEG = 7, //!< No additional details 6733 }; 6734 6735 enum PIPELINE 6736 { 6737 PIPELINE_MFCJPEGHUFFTABLESTATE = 2, //!< No additional details 6738 }; 6739 6740 enum COMMAND_TYPE 6741 { 6742 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6743 }; 6744 6745 //! \brief HUFF_TABLE_ID 6746 //! \details 6747 //! Huffman table destination identifier will specify one of two 6748 //! destinations at the encoder into which the Huffman table must be stored. 6749 enum HUFF_TABLE_ID 6750 { 6751 HUFF_TABLE_ID_UNNAMED0 = 0, //!< Huffman table 0 6752 HUFF_TABLE_ID_UNNAMED1 = 1, //!< Huffman table 1 6753 }; 6754 6755 //! \name Initializations 6756 6757 //! \brief Explicit member initialization function 6758 MFC_JPEG_HUFF_TABLE_STATE_CMD(); 6759 6760 static const size_t dwSize = 176; 6761 static const size_t byteSize = 704; 6762 }; 6763 6764 //! 6765 //! \brief MFD_JPEG_BSD_OBJECT 6766 //! \details 6767 //! 6768 //! 6769 struct MFD_JPEG_BSD_OBJECT_CMD 6770 { 6771 union 6772 { 6773 struct 6774 { 6775 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 6776 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 6777 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 6778 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 6779 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 6780 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 6781 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 6782 }; 6783 uint32_t Value; 6784 } DW0; 6785 union 6786 { 6787 struct 6788 { 6789 uint32_t IndirectDataLength; //!< Indirect Data Length 6790 }; 6791 uint32_t Value; 6792 } DW1; 6793 union 6794 { 6795 struct 6796 { 6797 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD(0, 28); //!< Indirect Data Start Address 6798 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 6799 }; 6800 uint32_t Value; 6801 } DW2; 6802 union 6803 { 6804 struct 6805 { 6806 uint32_t ScanVerticalPosition : __CODEGEN_BITFIELD(0, 12); //!< Scan Vertical Position 6807 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 15); //!< Reserved 6808 uint32_t ScanHorizontalPosition : __CODEGEN_BITFIELD(16, 28); //!< Scan Horizontal Position 6809 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 6810 }; 6811 uint32_t Value; 6812 } DW3; 6813 union 6814 { 6815 struct 6816 { 6817 uint32_t McuCount : __CODEGEN_BITFIELD(0, 25); //!< MCU Count 6818 uint32_t Reserved154 : __CODEGEN_BITFIELD(26, 26); //!< Reserved 6819 uint32_t ScanComponents : __CODEGEN_BITFIELD(27, 29); //!< Scan Components 6820 uint32_t Interleaved : __CODEGEN_BITFIELD(30, 30); //!< INTERLEAVED 6821 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 6822 }; 6823 uint32_t Value; 6824 } DW4; 6825 union 6826 { 6827 struct 6828 { 6829 uint32_t Restartinterval16Bit : __CODEGEN_BITFIELD(0, 15); //!< RestartInterval(16 bit) 6830 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 6831 }; 6832 uint32_t Value; 6833 } DW5; 6834 6835 //! \name Local enumerations 6836 6837 enum SUBOPCODE_B 6838 { 6839 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 6840 }; 6841 6842 enum SUBOPCODE_A 6843 { 6844 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 6845 }; 6846 6847 enum MEDIA_COMMAND_OPCODE 6848 { 6849 MEDIA_COMMAND_OPCODE_JPEGDEC = 7, //!< No additional details 6850 }; 6851 6852 enum PIPELINE 6853 { 6854 PIPELINE_MFDJPEGBSDOBJECT = 2, //!< No additional details 6855 }; 6856 6857 enum COMMAND_TYPE 6858 { 6859 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6860 }; 6861 6862 enum INTERLEAVED 6863 { 6864 INTERLEAVED_NON_INTERLEAVED = 0, //!< one component in the Scan 6865 INTERLEAVED_INTERLEAVED = 1, //!< multiple components in the Scan 6866 }; 6867 6868 //! \name Initializations 6869 6870 //! \brief Explicit member initialization function 6871 MFD_JPEG_BSD_OBJECT_CMD(); 6872 6873 static const size_t dwSize = 6; 6874 static const size_t byteSize = 24; 6875 }; 6876 6877 //! 6878 //! \brief MFC_JPEG_SCAN_OBJECT 6879 //! \details 6880 //! Encoder Only 6881 //! 6882 struct MFC_JPEG_SCAN_OBJECT_CMD 6883 { 6884 union 6885 { 6886 struct 6887 { 6888 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 6889 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 6890 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 6891 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 6892 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 6893 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 6894 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 6895 }; 6896 uint32_t Value; 6897 } DW0; 6898 union 6899 { 6900 struct 6901 { 6902 uint32_t McuCount : __CODEGEN_BITFIELD(0, 25); //!< MCU Count 6903 uint32_t Reserved58 : __CODEGEN_BITFIELD(26, 31); //!< Reserved 6904 }; 6905 uint32_t Value; 6906 } DW1; 6907 union 6908 { 6909 struct 6910 { 6911 uint32_t RestartInterval : __CODEGEN_BITFIELD(0, 15); //!< Restart Interval 6912 uint32_t IsLastScan : __CODEGEN_BITFIELD(16, 16); //!< IS_LAST_SCAN 6913 uint32_t HeadPresentFlag : __CODEGEN_BITFIELD(17, 17); //!< HEAD_PRESENT_FLAG 6914 uint32_t HuffmanDcTable : __CODEGEN_BITFIELD(18, 20); //!< HUFFMAN_DC_TABLE 6915 uint32_t Reserved85 : __CODEGEN_BITFIELD(21, 21); //!< Reserved 6916 uint32_t HuffmanAcTable : __CODEGEN_BITFIELD(22, 24); //!< HUFFMAN_AC_TABLE 6917 uint32_t Reserved89 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 6918 }; 6919 uint32_t Value; 6920 } DW2; 6921 6922 //! \name Local enumerations 6923 6924 enum SUBOPCODE_B 6925 { 6926 SUBOPCODE_B_UNNAMED9 = 9, //!< No additional details 6927 }; 6928 6929 enum SUBOPCODE_A 6930 { 6931 SUBOPCODE_A_UNNAMED2 = 2, //!< No additional details 6932 }; 6933 6934 enum MEDIA_COMMAND_OPCODE 6935 { 6936 MEDIA_COMMAND_OPCODE_JPEGENC = 7, //!< No additional details 6937 }; 6938 6939 enum PIPELINE 6940 { 6941 PIPELINE_MFCJPEGSCANOBJECT = 2, //!< No additional details 6942 }; 6943 6944 enum COMMAND_TYPE 6945 { 6946 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6947 }; 6948 6949 //! \brief IS_LAST_SCAN 6950 //! \details 6951 //! If this flag is set, then HW will insert EOI (0xFFD9) to the end of Scan 6952 //! encoded bitstream. 6953 enum IS_LAST_SCAN 6954 { 6955 IS_LAST_SCAN_UNNAMED0 = 0, //!< Not the last Scan. 6956 IS_LAST_SCAN_UNNAMED1 = 1, //!< Indicates that the current Scan is the last one. 6957 }; 6958 6959 //! \brief HEAD_PRESENT_FLAG 6960 //! \details 6961 //! If this flag is set to 0, then no MFC_JPEG_PAK_INSERT_OBJECT commands 6962 //! will be sent. If this flag is set to 1, then one or more 6963 //! MFC_JPEG_PAK_INSERT_OBJECT commands will be sent after 6964 //! MFC_JPEG_SCAN_OBJECT command. 6965 enum HEAD_PRESENT_FLAG 6966 { 6967 HEAD_PRESENT_FLAG_UNNAMED0 = 0, //!< No insertion into the output bitstream buffer before Scan encoded bitstream 6968 HEAD_PRESENT_FLAG_UNNAMED1 = 1, //!< Headers, tables, App data insertion into the output bitstream buffer. HW will insert the insertion data before the Scan encoded bitstream. 6969 }; 6970 6971 //! \brief HUFFMAN_DC_TABLE 6972 //! \details 6973 //! DC Huffman table destination selector specifies one of two possible DC 6974 //! table destinations for each Y, U, V, or R, G, B.The DC Huffman tables 6975 //! shall have been loaded in destination 0 and 1 by the time of issuing 6976 //! MFC_JPEG_HUFF_TABLE_STATE Command. 6977 enum HUFFMAN_DC_TABLE 6978 { 6979 HUFFMAN_DC_TABLE_BIT20_V0 = 0, //!< The third image component must use the DC table 0. 6980 HUFFMAN_DC_TABLE_BIT19_U0 = 0, //!< The second image component must use the DC table 0. 6981 HUFFMAN_DC_TABLE_BIT18_Y0 = 0, //!< The first image component must use the DC table 0. 6982 HUFFMAN_DC_TABLE_BIT18_Y1 = 1, //!< The first image component must use the DC table 1. 6983 HUFFMAN_DC_TABLE_BIT19_U1 = 2, //!< The second image component must use the DC table 1. 6984 HUFFMAN_DC_TABLE_BIT20_V1 = 4, //!< The third image component must use the DC table 1. 6985 }; 6986 6987 //! \brief HUFFMAN_AC_TABLE 6988 //! \details 6989 //! AC Huffman table destination selector specifies one of two possible AC 6990 //! table destinations for each Y, U, V, or R, G, B.The AC Huffman tables 6991 //! must have been loaded in destination 0 and 1 by the time of issuing 6992 //! MFC_JPEG_HUFF_TABLE_STATE Command. 6993 enum HUFFMAN_AC_TABLE 6994 { 6995 HUFFMAN_AC_TABLE_BIT24_V0 = 0, //!< The third image component must use the AC table 0. 6996 HUFFMAN_AC_TABLE_BIT23_U0 = 0, //!< The second image component must use the AC table 0. 6997 HUFFMAN_AC_TABLE_BIT22_Y0 = 0, //!< The first image component must use the AC table 0. 6998 HUFFMAN_AC_TABLE_BIT22_Y1 = 1, //!< The first image component must use the AC table 1. 6999 HUFFMAN_AC_TABLE_BIT23_U1 = 2, //!< The second image component must use the AC table 1. 7000 HUFFMAN_AC_TABLE_BIT24_V1 = 4, //!< The third image component must use the AC table 1. 7001 }; 7002 7003 //! \name Initializations 7004 7005 //! \brief Explicit member initialization function 7006 MFC_JPEG_SCAN_OBJECT_CMD(); 7007 7008 static const size_t dwSize = 3; 7009 static const size_t byteSize = 12; 7010 }; 7011 7012 //! 7013 //! \brief MFX_VP8_Encoder_CFG 7014 //! \details 7015 //! This must be the very first command to issue after the surface state, 7016 //! the pipe select and base address setting commands and must be issued 7017 //! before MFX_VP8_PIC_STATE. 7018 //! 7019 struct MFX_VP8_Encoder_CFG_CMD 7020 { 7021 union 7022 { 7023 struct 7024 { 7025 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 7026 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 7027 uint32_t SubOpcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUB_OPCODE_B 7028 uint32_t SubOpcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUB_OPCODE_A 7029 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 7030 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 7031 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 7032 }; 7033 uint32_t Value; 7034 } DW0; 7035 union 7036 { 7037 struct 7038 { 7039 uint32_t PerformanceCounterEnable : __CODEGEN_BITFIELD(0, 0); //!< Performance Counter Enable 7040 uint32_t FinalBitstreamOutputDisable : __CODEGEN_BITFIELD(1, 1); //!< Final Bitstream Output Disable 7041 uint32_t TokenStatisticsOutputEnable : __CODEGEN_BITFIELD(2, 2); //!< Token Statistics Output Enable 7042 uint32_t BitstreamStatisticsOutputEnable : __CODEGEN_BITFIELD(3, 3); //!< Bitstream Statistics Output Enable 7043 uint32_t UpdateSegmentFeatureDataFlag : __CODEGEN_BITFIELD(4, 4); //!< Update Segment Feature Data Flag 7044 uint32_t SkipFinalBitstreamWhenOverUnderFlow : __CODEGEN_BITFIELD(5, 5); //!< Skip Final Bitstream when Over / Under flow 7045 uint32_t RateControlInitialPass : __CODEGEN_BITFIELD(6, 6); //!< RATE_CONTROL_INITIAL_PASS 7046 uint32_t PerSegmentDeltaQindexLoopfilterDisable : __CODEGEN_BITFIELD(7, 7); //!< Per Segment Delta Qindex / LoopFilter Disable 7047 uint32_t FinerBrcEnable : __CODEGEN_BITFIELD(8, 8); //!< Finer BRC Enable 7048 uint32_t CompressedBitstreamOutputDisable : __CODEGEN_BITFIELD(9, 9); //!< Compressed Bitstream Output Disable 7049 uint32_t VbspunitpowerclockGatingDisable : __CODEGEN_BITFIELD(10, 10); //!< VBSPunitPowerClock Gating Disable 7050 uint32_t Reserved43 : __CODEGEN_BITFIELD(11, 31); //!< Reserved 7051 }; 7052 uint32_t Value; 7053 } DW1; 7054 union 7055 { 7056 struct 7057 { 7058 uint32_t MaxFrameBitCountRateControlEnableMask : __CODEGEN_BITFIELD(0, 0); //!< MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7059 uint32_t MinFrameBitCountRateControlEnableMask : __CODEGEN_BITFIELD(1, 1); //!< MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7060 uint32_t MaxInterMbBitCountCheckEnableMask : __CODEGEN_BITFIELD(2, 2); //!< Max Inter MB Bit Count Check Enable Mask 7061 uint32_t MaxIntraMbBitCountCheckEnableMask : __CODEGEN_BITFIELD(3, 3); //!< Max Intra MB Bit Count Check Enable Mask 7062 uint32_t IntermediateBitBufferOverrunEnableMask : __CODEGEN_BITFIELD(4, 4); //!< Intermediate Bit Buffer Overrun Enable Mask 7063 uint32_t FinalBistreamBufferOverrunEnableMask : __CODEGEN_BITFIELD(5, 5); //!< Final Bistream Buffer Overrun Enable Mask 7064 uint32_t QindexClampHighMaskForUnderflow : __CODEGEN_BITFIELD(6, 6); //!< Qindex_Clamp_High_mask for underflow 7065 uint32_t QindexClampHighMaskForOverflow : __CODEGEN_BITFIELD(7, 7); //!< Qindex_Clamp_High_mask for overflow 7066 uint32_t Reserved72 : __CODEGEN_BITFIELD(8, 31); //!< Reserved 7067 }; 7068 uint32_t Value; 7069 } DW2; 7070 union 7071 { 7072 struct 7073 { 7074 uint32_t MaxInterMbBitCount : __CODEGEN_BITFIELD(0, 11); //!< Max Inter MB bit count 7075 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 7076 uint32_t MaxIntraMbBitCountLimit : __CODEGEN_BITFIELD(16, 27); //!< Max Intra MB Bit Count Limit 7077 uint32_t Reserved124 : __CODEGEN_BITFIELD(28, 31); //!< Reserved 7078 }; 7079 uint32_t Value; 7080 } DW3; 7081 union 7082 { 7083 struct 7084 { 7085 uint32_t FrameBitRateMax : __CODEGEN_BITFIELD(0, 13); //!< Frame Bit Rate Max 7086 uint32_t FrameBitRateMaxUnit : __CODEGEN_BITFIELD(14, 14); //!< FRAME_BIT_RATE_MAX_UNIT 7087 uint32_t FrameBitrateMaxUnitMode : __CODEGEN_BITFIELD(15, 15); //!< FRAME_BITRATE_MAX_UNIT_MODE 7088 uint32_t FrameBitRateMin : __CODEGEN_BITFIELD(16, 29); //!< Frame Bit Rate Min 7089 uint32_t FrameBitRateMinUnit : __CODEGEN_BITFIELD(30, 30); //!< FRAME_BIT_RATE_MIN_UNIT 7090 uint32_t FrameBitrateMinUnitMode : __CODEGEN_BITFIELD(31, 31); //!< FRAME_BITRATE_MIN_UNIT_MODE 7091 }; 7092 uint32_t Value; 7093 } DW4; 7094 union 7095 { 7096 struct 7097 { 7098 uint32_t FrameDeltaQindexMax0 : __CODEGEN_BITFIELD(0, 7); //!< Frame Delta QIndex Max [0] 7099 uint32_t FrameDeltaQindexMax1 : __CODEGEN_BITFIELD(8, 15); //!< Frame Delta QIndex Max[1] 7100 uint32_t FrameDeltaqIndexMax2 : __CODEGEN_BITFIELD(16, 23); //!< Frame DeltaQ Index Max[2] 7101 uint32_t FrameDeltaQindexMax3 : __CODEGEN_BITFIELD(24, 31); //!< Frame Delta QIndex Max[3] 7102 }; 7103 uint32_t Value; 7104 } DW5; 7105 union 7106 { 7107 struct 7108 { 7109 uint32_t FrameDeltaQindexMin0 : __CODEGEN_BITFIELD(0, 7); //!< Frame Delta QIndex Min[0] 7110 uint32_t FrameDeltaQindexMin1 : __CODEGEN_BITFIELD(8, 15); //!< Frame Delta QIndex Min[1] 7111 uint32_t FrameDeltaQindexMin2 : __CODEGEN_BITFIELD(16, 23); //!< Frame Delta QIndex Min[2] 7112 uint32_t FrameDeltaQindexMin3 : __CODEGEN_BITFIELD(24, 31); //!< Frame Delta QIndex Min[3] 7113 }; 7114 uint32_t Value; 7115 } DW6; 7116 union 7117 { 7118 struct 7119 { 7120 uint32_t PerSegmentFrameDeltaQindexMax1; //!< Per Segment Frame Delta QIndex Max[1] 7121 }; 7122 uint32_t Value; 7123 } DW7; 7124 union 7125 { 7126 struct 7127 { 7128 uint32_t PerSegmentFrameDeltaQindexMin1; //!< Per Segment Frame Delta QIndex Min[1] 7129 }; 7130 uint32_t Value; 7131 } DW8; 7132 union 7133 { 7134 struct 7135 { 7136 uint32_t PerSegmentFrameDeltaQindexMax2; //!< Per Segment Frame Delta QIndex Max[2] 7137 }; 7138 uint32_t Value; 7139 } DW9; 7140 union 7141 { 7142 struct 7143 { 7144 uint32_t PerSegmentFrameDeltaQindexMin2; //!< Per Segment Frame Delta QIndex Min[2] 7145 }; 7146 uint32_t Value; 7147 } DW10; 7148 union 7149 { 7150 struct 7151 { 7152 uint32_t PerSegmentFrameDeltaQindexMax3; //!< Per Segment Frame Delta QIndex Max[3] 7153 }; 7154 uint32_t Value; 7155 } DW11; 7156 union 7157 { 7158 struct 7159 { 7160 uint32_t PerSegmentFrameDeltaQindexMin3; //!< Per Segment Frame Delta QIndex Min[3] 7161 }; 7162 uint32_t Value; 7163 } DW12; 7164 union 7165 { 7166 struct 7167 { 7168 uint32_t FrameDeltaLoopFilterMax0 : __CODEGEN_BITFIELD(0, 7); //!< Frame Delta Loop Filter Max[0] 7169 uint32_t FramEdeltaLoopFilterMax1 : __CODEGEN_BITFIELD(8, 15); //!< Fram eDelta Loop Filter Max[1] 7170 uint32_t FrameDeltaLoopFilterMax2 : __CODEGEN_BITFIELD(16, 23); //!< Frame Delta Loop Filter Max[2] 7171 uint32_t FrameDeltaLoopFilterMax3 : __CODEGEN_BITFIELD(24, 31); //!< Frame Delta Loop Filter Max[3] 7172 }; 7173 uint32_t Value; 7174 } DW13; 7175 union 7176 { 7177 struct 7178 { 7179 uint32_t FrameDeltaLoopFilterMin0 : __CODEGEN_BITFIELD(0, 7); //!< Frame Delta Loop Filter Min[0] 7180 uint32_t FrameDeltaLoopFilterMin1 : __CODEGEN_BITFIELD(8, 15); //!< Frame Delta Loop Filter Min[1] 7181 uint32_t FrameDeltaLoopFilterMin2 : __CODEGEN_BITFIELD(16, 23); //!< Frame Delta Loop Filter Min[2] 7182 uint32_t FrameDeltaLoopFilterMin3 : __CODEGEN_BITFIELD(24, 31); //!< Frame Delta Loop Filter Min[3] 7183 }; 7184 uint32_t Value; 7185 } DW14; 7186 union 7187 { 7188 struct 7189 { 7190 uint32_t PerSegmentFrameDeltaLoopfilterMax1; //!< Per Segment Frame Delta LoopFilter Max[1] 7191 }; 7192 uint32_t Value; 7193 } DW15; 7194 union 7195 { 7196 struct 7197 { 7198 uint32_t PerSegmentFrameDeltaLoopfilterMin1; //!< Per Segment Frame Delta LoopFilter Min[1] 7199 }; 7200 uint32_t Value; 7201 } DW16; 7202 union 7203 { 7204 struct 7205 { 7206 uint32_t PerSegmentFrameDeltaLoopfilterMax2; //!< Per Segment Frame Delta LoopFilter Max[2] 7207 }; 7208 uint32_t Value; 7209 } DW17; 7210 union 7211 { 7212 struct 7213 { 7214 uint32_t PerSegmentFrameDeltaLoopfilterMin2; //!< Per Segment Frame Delta LoopFilter Min[2] 7215 }; 7216 uint32_t Value; 7217 } DW18; 7218 union 7219 { 7220 struct 7221 { 7222 uint32_t PerSegmentFrameDeltaLoopfilterMax3; //!< Per Segment Frame Delta LoopFilter Max[3] 7223 }; 7224 uint32_t Value; 7225 } DW19; 7226 union 7227 { 7228 struct 7229 { 7230 uint32_t PerSegmentFrameDeltaLoopfilterMin3; //!< Per Segment Frame Delta LoopFilter Min[3] 7231 }; 7232 uint32_t Value; 7233 } DW20; 7234 union 7235 { 7236 struct 7237 { 7238 uint32_t FrameBitRateMaxDelta : __CODEGEN_BITFIELD(0, 14); //!< Frame Bit Rate Max Delta 7239 uint32_t Reserved687 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 7240 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD(16, 30); //!< FrameBitRateMinDelta 7241 uint32_t Reserved703 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 7242 }; 7243 uint32_t Value; 7244 } DW21; 7245 union 7246 { 7247 struct 7248 { 7249 uint32_t MinFrameWsize : __CODEGEN_BITFIELD(0, 15); //!< Min Frame WSize 7250 uint32_t MinFrameWsizeUnit : __CODEGEN_BITFIELD(16, 17); //!< MIN_FRAME_WSIZE_UNIT 7251 uint32_t Reserved722 : __CODEGEN_BITFIELD(18, 19); //!< Reserved 7252 uint32_t BitstreamFormatVersion : __CODEGEN_BITFIELD(20, 22); //!< Bitstream Format Version 7253 uint32_t ShowFrame : __CODEGEN_BITFIELD(23, 23); //!< Show Frame 7254 uint32_t Reserved728 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7255 }; 7256 uint32_t Value; 7257 } DW22; 7258 union 7259 { 7260 struct 7261 { 7262 uint32_t HorizontalSizeCode : __CODEGEN_BITFIELD(0, 15); //!< Horizontal_Size_Code 7263 uint32_t VerticalSizeCode : __CODEGEN_BITFIELD(16, 31); //!< Vertical_Size_Code 7264 }; 7265 uint32_t Value; 7266 } DW23; 7267 union 7268 { 7269 struct 7270 { 7271 uint32_t FrameHeaderBitCount; //!< Frame Header Bit Count 7272 }; 7273 uint32_t Value; 7274 } DW24; 7275 union 7276 { 7277 struct 7278 { 7279 uint32_t FrameHeaderBinBufferQindexUpdatePointer; //!< Frame Header Bin Buffer Qindex Update Pointer 7280 }; 7281 uint32_t Value; 7282 } DW25; 7283 union 7284 { 7285 struct 7286 { 7287 uint32_t FrameHeaderBinBufferLoopfilterUpdatePointer; //!< Frame Header Bin Buffer LoopFilter Update Pointer 7288 }; 7289 uint32_t Value; 7290 } DW26; 7291 union 7292 { 7293 struct 7294 { 7295 uint32_t FrameHeaderBinBufferTokenUpdatePointer; //!< Frame Header Bin Buffer Token Update Pointer 7296 }; 7297 uint32_t Value; 7298 } DW27; 7299 union 7300 { 7301 struct 7302 { 7303 uint32_t FrameHeaderBinBufferMvupdatePointer; //!< Frame Header Bin Buffer MVUpdate Pointer 7304 }; 7305 uint32_t Value; 7306 } DW28; 7307 union 7308 { 7309 struct 7310 { 7311 uint32_t Cv0ClampValue0 : __CODEGEN_BITFIELD(0, 3); //!< CV0 - Clamp Value 0 7312 uint32_t Cv1 : __CODEGEN_BITFIELD(4, 7); //!< CV1 7313 uint32_t Cv2 : __CODEGEN_BITFIELD(8, 11); //!< CV2 7314 uint32_t Cv3 : __CODEGEN_BITFIELD(12, 15); //!< CV3 7315 uint32_t Cv4 : __CODEGEN_BITFIELD(16, 19); //!< CV4 7316 uint32_t Cv5 : __CODEGEN_BITFIELD(20, 23); //!< CV5 7317 uint32_t Cv6 : __CODEGEN_BITFIELD(24, 27); //!< CV6 7318 uint32_t ClampvaluesCv7 : __CODEGEN_BITFIELD(28, 31); //!< ClampValues - CV7 7319 }; 7320 uint32_t Value; 7321 } DW29; 7322 7323 //! \name Local enumerations 7324 7325 enum SUB_OPCODE_B 7326 { 7327 SUB_OPCODE_B_MFXVP8ENCODERCFG = 1, //!< No additional details 7328 }; 7329 7330 enum SUB_OPCODE_A 7331 { 7332 SUB_OPCODE_A_VP8COMMON = 2, //!< No additional details 7333 }; 7334 7335 enum MEDIA_COMMAND_OPCODE 7336 { 7337 MEDIA_COMMAND_OPCODE_VP8 = 4, //!< No additional details 7338 }; 7339 7340 enum PIPELINE 7341 { 7342 PIPELINE_VIDEOCODEC = 2, //!< No additional details 7343 }; 7344 7345 enum COMMAND_TYPE 7346 { 7347 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7348 }; 7349 7350 enum RATE_CONTROL_INITIAL_PASS 7351 { 7352 RATE_CONTROL_INITIAL_PASS_SUBSEQUENCEPASS_ES = 0, //!< No additional details 7353 RATE_CONTROL_INITIAL_PASS_INITIALPASS = 1, //!< No additional details 7354 }; 7355 7356 //! \brief MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7357 //! \details 7358 //! Enable Max. Frame Rate Control.This is a mask bit controlling if the 7359 //! condition of frame level bit count is greater than or equal to 7360 //! FrameBitRateMax. 7361 enum MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7362 { 7363 MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED0 = 0, //!< Do not update bit[0] of MFX_VP8_IMAGE_STATUS control register. 7364 MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED1 = 1, //!< If (Total Frame Level Bit Counter) >= (Frame Bit Rate Maximum Limit)Set bit[0] and bit[1] of MFX_VP8_IMAGE_STATUS control register. 7365 }; 7366 7367 //! \brief MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7368 //! \details 7369 //! Enable Min. Frame Rate Control. This is a mask bit controlling if the 7370 //! condition of frame level bit count is less than or equal to 7371 //! FrameBitRateMin. 7372 enum MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7373 { 7374 MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED0 = 0, //!< Do not update bit[0] of MFX_VP8_IMAGE_STATUS Control Register. 7375 MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED1 = 1, //!< If (Total Frame Level Bit Counter) =< (Frame Bit Rate Minimum limit)Set bit[0] and bit[1] of MFX_VP8_IMAGE_STATUS Control Register. 7376 }; 7377 7378 //! \brief FRAME_BIT_RATE_MAX_UNIT 7379 //! \details 7380 //! This field is Frame Bitrate Maximum Mode 7381 enum FRAME_BIT_RATE_MAX_UNIT 7382 { 7383 FRAME_BIT_RATE_MAX_UNIT_32_B = 0, //!< No additional details 7384 FRAME_BIT_RATE_MAX_UNIT_4_KB = 1, //!< No additional details 7385 }; 7386 7387 //! \brief FRAME_BITRATE_MAX_UNIT_MODE 7388 //! \details 7389 //! This field is the Frame Bitrate Maximum Limit Units. 7390 enum FRAME_BITRATE_MAX_UNIT_MODE 7391 { 7392 FRAME_BITRATE_MAX_UNIT_MODE_COMPATIBILITYMODE = 0, //!< Frame BitRate Max Unit is in old mode (128b/16Kb) 7393 FRAME_BITRATE_MAX_UNIT_MODE_NEWMODE = 1, //!< Frame BitRate Max Unit is in new mode (32byte/4Kb) 7394 }; 7395 7396 //! \brief FRAME_BIT_RATE_MIN_UNIT 7397 //! \details 7398 //! This field is Frame Bitrate Minimum Mode. 7399 enum FRAME_BIT_RATE_MIN_UNIT 7400 { 7401 FRAME_BIT_RATE_MIN_UNIT_32_B = 0, //!< No additional details 7402 FRAME_BIT_RATE_MIN_UNIT_4_KB = 1, //!< No additional details 7403 }; 7404 7405 //! \brief FRAME_BITRATE_MIN_UNIT_MODE 7406 //! \details 7407 //! This field is the Frame Bitrate Minimum Limit Units. 7408 enum FRAME_BITRATE_MIN_UNIT_MODE 7409 { 7410 FRAME_BITRATE_MIN_UNIT_MODE_COMPATIBILITYMODE = 0, //!< Frame BitRate Min Unit is in old mode (128b/16Kb) 7411 FRAME_BITRATE_MIN_UNIT_MODE_NEWMODE = 1, //!< Frame BitRate Min Unit is in new mode (32byte/4Kb) 7412 }; 7413 7414 enum MIN_FRAME_WSIZE_UNIT 7415 { 7416 MIN_FRAME_WSIZE_UNIT_COMPATIBILITYMODE = 0, //!< MinFrameWSizeUnit is in old mode (128b/16Kb) 7417 MIN_FRAME_WSIZE_UNIT_NEWMODE = 1, //!< MinFrameWSizeUnit is in new mode (32byte/4Kb) 7418 }; 7419 7420 //! \name Initializations 7421 7422 //! \brief Explicit member initialization function 7423 MFX_VP8_Encoder_CFG_CMD(); 7424 7425 static const size_t dwSize = 30; 7426 static const size_t byteSize = 120; 7427 }; 7428 7429 //! 7430 //! \brief MFX_VP8_BSP_BUF_BASE_ADDR_STATE 7431 //! \details 7432 //! 7433 //! 7434 struct MFX_VP8_BSP_BUF_BASE_ADDR_STATE_CMD 7435 { 7436 union 7437 { 7438 struct 7439 { 7440 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 7441 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 7442 uint32_t SubOpcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUB_OPCODE_B 7443 uint32_t SubOpcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUB_OPCODE_A 7444 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 7445 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 7446 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 7447 }; 7448 uint32_t Value; 7449 } DW0; 7450 SPLITBASEADDRESS64BYTEALIGNED_CMD FrameHeaderBaseAddress; //!< DW1..2, Frame Header - Base Address 7451 MEMORYADDRESSATTRIBUTES_CMD FrameHeaderAttributes; //!< DW3, Frame Header - Attributes 7452 SPLITBASEADDRESS64BYTEALIGNED_CMD IntermediateBufferBaseAddress; //!< DW4..5, Intermediate Buffer - Base Address 7453 MEMORYADDRESSATTRIBUTES_CMD IntermediateBufferAttributes; //!< DW6, Intermediate Buffer - Attributes 7454 uint32_t IntermediateBufferPartitionOffset[8]; //!< Intermediate Buffer Partition Offset 7455 union 7456 { 7457 struct 7458 { 7459 uint32_t IntermediateBufferMaxSize; //!< Intermediate Buffer Max Size 7460 }; 7461 uint32_t Value; 7462 } DW15; 7463 SPLITBASEADDRESS64BYTEALIGNED_CMD FinalFrameBaseAddress; //!< DW16..17, Final Frame - Base Address 7464 MEMORYADDRESSATTRIBUTES_CMD FinalFrameAttributes; //!< DW18, Final Frame - Attributes 7465 union 7466 { 7467 struct 7468 { 7469 uint32_t FinalFrameByteOffset : __CODEGEN_BITFIELD(0, 5); //!< Final Frame Byte Offset 7470 uint32_t Reserved614 : __CODEGEN_BITFIELD(6, 31); //!< Reserved 7471 }; 7472 uint32_t Value; 7473 } DW19; 7474 SPLITBASEADDRESS64BYTEALIGNED_CMD StreamoutBaseAddress; //!< DW20..21, Streamout - Base Address 7475 MEMORYADDRESSATTRIBUTES_CMD StreamoutAttributes; //!< DW22, Streamout - Attributes 7476 SPLITBASEADDRESS64BYTEALIGNED_CMD CoeffProbsStreaminSurfaceBaseAddress; //!< DW23..24, Coeff Probs StreamIn Surface - Base Address 7477 MEMORYADDRESSATTRIBUTES_CMD CoeffProbsStreaminSurfaceAttributes; //!< DW25, Coeff Probs StreamIn Surface - Attributes 7478 SPLITBASEADDRESS64BYTEALIGNED_CMD TokenStatisticsSurfaceBaseAddress; //!< DW26..27, Token Statistics Surface - Base Address 7479 MEMORYADDRESSATTRIBUTES_CMD TokenStatisticsSurfaceAttributes; //!< DW28, Token Statistics Surface - Attributes 7480 SPLITBASEADDRESS64BYTEALIGNED_CMD MpcRowstoreSurfaceBaseAddress; //!< DW29..30, MPC RowStore Surface - Base Address 7481 MEMORYADDRESSATTRIBUTES_CMD MpcRowstoreSurfaceAttributes; //!< DW31, MPC RowStore Surface - Attributes 7482 7483 //! \name Local enumerations 7484 7485 enum SUB_OPCODE_B 7486 { 7487 SUB_OPCODE_B_MFXVP8BSPBUFBASEADDRSTATE = 3, //!< No additional details 7488 }; 7489 7490 enum SUB_OPCODE_A 7491 { 7492 SUB_OPCODE_A_VP8COMMON = 2, //!< No additional details 7493 }; 7494 7495 enum MEDIA_COMMAND_OPCODE 7496 { 7497 MEDIA_COMMAND_OPCODE_VP8 = 4, //!< No additional details 7498 }; 7499 7500 enum PIPELINE 7501 { 7502 PIPELINE_VIDEOCODEC = 2, //!< No additional details 7503 }; 7504 7505 enum COMMAND_TYPE 7506 { 7507 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7508 }; 7509 7510 //! \name Initializations 7511 7512 //! \brief Explicit member initialization function 7513 MFX_VP8_BSP_BUF_BASE_ADDR_STATE_CMD(); 7514 7515 static const size_t dwSize = 32; 7516 static const size_t byteSize = 128; 7517 }; 7518 7519 //! 7520 //! \brief MFD_VP8_BSD_OBJECT 7521 //! \details 7522 //! The MFD_VP8_BSD_OBJECT command is the only primitive command for the VP8 7523 //! Decoding Pipeline. The Partitions of the bitstream is loaded as indirect 7524 //! data object. Before issuing a MFD_VP8_BSD_OBJECT command, all VP8 frame 7525 //! level states of the MFD Engine need to be valid. Therefore the commands 7526 //! used to set these states need to have been issued prior to the issue of 7527 //! a MFD_VP8_BSD_OBJECT command.Context switch interrupt is not supported 7528 //! by this command. 7529 //! 7530 struct MFD_VP8_BSD_OBJECT_CMD 7531 { 7532 union 7533 { 7534 struct 7535 { 7536 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 7537 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 7538 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODEB 7539 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODEA 7540 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 7541 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 7542 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 7543 }; 7544 uint32_t Value; 7545 } DW0; 7546 union 7547 { 7548 struct 7549 { 7550 uint32_t Partition0FirstmbbitoffsetFromFrameHeader : __CODEGEN_BITFIELD(0, 2); //!< Partition0 FirstMBBitOffset from Frame Header 7551 uint32_t Reserved35 : __CODEGEN_BITFIELD(3, 3); //!< Reserved 7552 uint32_t CodedNumOfCoeffTokenPartitions : __CODEGEN_BITFIELD(4, 5); //!< Coded Num of Coeff Token Partitions 7553 uint32_t Reserved38 : __CODEGEN_BITFIELD(6, 7); //!< Reserved 7554 uint32_t Partition0CpbacEntropyRange : __CODEGEN_BITFIELD(8, 15); //!< Partition0 CPBAC Entropy Range 7555 uint32_t Partition0CpbacEntropyCount : __CODEGEN_BITFIELD(16, 20); //!< Partition0 CPBAC Entropy Count 7556 uint32_t Reserved53 : __CODEGEN_BITFIELD(21, 31); //!< Reserved 7557 }; 7558 uint32_t Value; 7559 } DW1; 7560 union 7561 { 7562 struct 7563 { 7564 uint32_t Reserved64 : __CODEGEN_BITFIELD(0, 23); //!< Reserved 7565 uint32_t Partition0CpbacEntropyValue : __CODEGEN_BITFIELD(24, 31); //!< Partition0 CPBAC Entropy Value 7566 }; 7567 uint32_t Value; 7568 } DW2; 7569 union 7570 { 7571 struct 7572 { 7573 uint32_t IndirectPartition0DataLength : __CODEGEN_BITFIELD(0, 23); //!< Indirect Partition0 Data Length 7574 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7575 }; 7576 uint32_t Value; 7577 } DW3; 7578 union 7579 { 7580 struct 7581 { 7582 uint32_t IndirectPartition0DataStartOffset; //!< Indirect Partition0 Data Start Offset 7583 }; 7584 uint32_t Value; 7585 } DW4; 7586 union 7587 { 7588 struct 7589 { 7590 uint32_t IndirectPartition1DataLength : __CODEGEN_BITFIELD(0, 23); //!< Indirect Partition1 Data Length 7591 uint32_t Reserved184 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7592 }; 7593 uint32_t Value; 7594 } DW5; 7595 union 7596 { 7597 struct 7598 { 7599 uint32_t IndirectPartition1DataStartOffset; //!< Indirect Partition1 Data Start Offset 7600 }; 7601 uint32_t Value; 7602 } DW6; 7603 union 7604 { 7605 struct 7606 { 7607 uint32_t IndirectPartition2DataLength : __CODEGEN_BITFIELD(0, 23); //!< Indirect Partition2 Data Length 7608 uint32_t Reserved248 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7609 }; 7610 uint32_t Value; 7611 } DW7; 7612 union 7613 { 7614 struct 7615 { 7616 uint32_t IndirectPartition2DataStartOffset; //!< Indirect Partition2 Data Start Offset 7617 }; 7618 uint32_t Value; 7619 } DW8; 7620 union 7621 { 7622 struct 7623 { 7624 uint32_t IndirectPartition3DataLength : __CODEGEN_BITFIELD(0, 23); //!< Indirect Partition3 Data Length 7625 uint32_t Reserved312 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7626 }; 7627 uint32_t Value; 7628 } DW9; 7629 union 7630 { 7631 struct 7632 { 7633 uint32_t IndirectPartition3DataStartOffset; //!< Indirect Partition3 Data Start Offset 7634 }; 7635 uint32_t Value; 7636 } DW10; 7637 union 7638 { 7639 struct 7640 { 7641 uint32_t IndirectPartition4DataLength : __CODEGEN_BITFIELD(0, 23); //!< Indirect Partition4 Data Length 7642 uint32_t Reserved376 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7643 }; 7644 uint32_t Value; 7645 } DW11; 7646 union 7647 { 7648 struct 7649 { 7650 uint32_t IndirectPartition4DataStartOffset; //!< Indirect Partition4 Data Start Offset 7651 }; 7652 uint32_t Value; 7653 } DW12; 7654 union 7655 { 7656 struct 7657 { 7658 uint32_t IndirectPartition5DataLength : __CODEGEN_BITFIELD(0, 23); //!< Indirect Partition5 Data Length 7659 uint32_t Reserved440 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7660 }; 7661 uint32_t Value; 7662 } DW13; 7663 union 7664 { 7665 struct 7666 { 7667 uint32_t IndirectPartition5DataStartOffset; //!< Indirect Partition5 Data Start Offset 7668 }; 7669 uint32_t Value; 7670 } DW14; 7671 union 7672 { 7673 struct 7674 { 7675 uint32_t IndirectPartition6DataLength : __CODEGEN_BITFIELD(0, 23); //!< Indirect Partition6 Data Length 7676 uint32_t Reserved504 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7677 }; 7678 uint32_t Value; 7679 } DW15; 7680 union 7681 { 7682 struct 7683 { 7684 uint32_t IndirectPartition6DataStartOffset; //!< Indirect Partition6 Data Start Offset 7685 }; 7686 uint32_t Value; 7687 } DW16; 7688 union 7689 { 7690 struct 7691 { 7692 uint32_t IndirectPartition7DataLength : __CODEGEN_BITFIELD(0, 23); //!< Indirect Partition7 Data Length 7693 uint32_t Reserved568 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7694 }; 7695 uint32_t Value; 7696 } DW17; 7697 union 7698 { 7699 struct 7700 { 7701 uint32_t IndirectPartition7DataStartOffset; //!< Indirect Partition7 Data Start Offset 7702 }; 7703 uint32_t Value; 7704 } DW18; 7705 union 7706 { 7707 struct 7708 { 7709 uint32_t IndirectPartition8DataLength : __CODEGEN_BITFIELD(0, 23); //!< Indirect Partition8 Data Length 7710 uint32_t Reserved632 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7711 }; 7712 uint32_t Value; 7713 } DW19; 7714 union 7715 { 7716 struct 7717 { 7718 uint32_t IndirectPartition8DataStartOffset; //!< Indirect Partition8 Data Start Offset 7719 }; 7720 uint32_t Value; 7721 } DW20; 7722 union 7723 { 7724 struct 7725 { 7726 uint32_t Reserved672 : __CODEGEN_BITFIELD(0, 7); //!< Reserved 7727 uint32_t MbHeaderErrorHandling : __CODEGEN_BITFIELD(8, 8); //!< MB_HEADER_ERROR_HANDLING 7728 uint32_t Reserved681 : __CODEGEN_BITFIELD(9, 9); //!< Reserved 7729 uint32_t EntropyErrorHandling : __CODEGEN_BITFIELD(10, 10); //!< ENTROPY_ERROR_HANDLING 7730 uint32_t Reserved683 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 7731 uint32_t MprErrorMvOutOfRangeHandling : __CODEGEN_BITFIELD(12, 12); //!< MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 7732 uint32_t Reserved685 : __CODEGEN_BITFIELD(13, 13); //!< Reserved 7733 uint32_t BsdprematurecompleteErrorHandling : __CODEGEN_BITFIELD(14, 14); //!< BSDPREMATURECOMPLETE_ERROR_HANDLING 7734 uint32_t Reserved687 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 7735 uint32_t ConcealPicIdConcealmentPictureId : __CODEGEN_BITFIELD(16, 17); //!< Conceal_Pic_Id (Concealment Picture ID) 7736 uint32_t Reserved690 : __CODEGEN_BITFIELD(18, 30); //!< Reserved 7737 uint32_t ConcealmentMethod : __CODEGEN_BITFIELD(31, 31); //!< CONCEALMENT_METHOD 7738 }; 7739 uint32_t Value; 7740 } DW21; 7741 7742 //! \name Local enumerations 7743 7744 enum SUBOPCODEB 7745 { 7746 SUBOPCODEB_UNNAMED8 = 8, //!< No additional details 7747 }; 7748 7749 enum SUBOPCODEA 7750 { 7751 SUBOPCODEA_UNNAMED1 = 1, //!< No additional details 7752 }; 7753 7754 enum MEDIA_COMMAND_OPCODE 7755 { 7756 MEDIA_COMMAND_OPCODE_VP8DEC = 4, //!< No additional details 7757 }; 7758 7759 enum PIPELINE 7760 { 7761 PIPELINE_MFDVP8BSDOBJECT = 2, //!< No additional details 7762 }; 7763 7764 enum COMMAND_TYPE 7765 { 7766 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7767 }; 7768 7769 enum MB_HEADER_ERROR_HANDLING 7770 { 7771 MB_HEADER_ERROR_HANDLING_IGNORETHEERRORANDCONTINUE_MASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 7772 MB_HEADER_ERROR_HANDLING_SETTHEINTERRUPTTOTHEDRIVER_PROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 7773 }; 7774 7775 enum ENTROPY_ERROR_HANDLING 7776 { 7777 ENTROPY_ERROR_HANDLING_IGNORETHEERRORANDCONTINUE_MASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 7778 ENTROPY_ERROR_HANDLING_SETTHEINTERRUPTTOTHEDRIVER_PROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 7779 }; 7780 7781 enum MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 7782 { 7783 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_IGNORETHEERRORANDCONTINUE_MASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 7784 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_SETTHEINTERRUPTTOTHEDRIVER_PROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 7785 }; 7786 7787 //! \brief BSDPREMATURECOMPLETE_ERROR_HANDLING 7788 //! \details 7789 //! It occurs in situation where the decode is completed but there are still 7790 //! data in the bitstream. 7791 enum BSDPREMATURECOMPLETE_ERROR_HANDLING 7792 { 7793 BSDPREMATURECOMPLETE_ERROR_HANDLING_IGNORETHEERRORANDCONTINUE_MASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 7794 BSDPREMATURECOMPLETE_ERROR_HANDLING_SETTHEINTERRUPTTOTHEDRIVER_PROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 7795 }; 7796 7797 //! \brief CONCEALMENT_METHOD 7798 //! \details 7799 //! This field specifies the method used for concealment when error is 7800 //! detected. 7801 enum CONCEALMENT_METHOD 7802 { 7803 CONCEALMENT_METHOD_INTRA16X16PREDICTION = 0, //!< A copy from the current picture is performed using Intra 16x16 Prediction method. 7804 CONCEALMENT_METHOD_INTERPCOPY = 1, //!< A copy from collocated macroblock location is performed from the concealment reference indicated by the ConCeal_Pic_Id field. 7805 }; 7806 7807 //! \name Initializations 7808 7809 //! \brief Explicit member initialization function 7810 MFD_VP8_BSD_OBJECT_CMD(); 7811 7812 static const size_t dwSize = 22; 7813 static const size_t byteSize = 88; 7814 }; 7815 7816 //! 7817 //! \brief MFX_VP8_PIC_STATE 7818 //! \details 7819 //! This must be the very first command to issue after the surface state, 7820 //! the pipe select and base address setting commands and must be issued 7821 //! before MFX_VP8_IMG_STATE. 7822 //! 7823 struct MFX_VP8_PIC_STATE_CMD 7824 { 7825 union 7826 { 7827 struct 7828 { 7829 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 7830 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 7831 uint32_t SubOpcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUB_OPCODE_B 7832 uint32_t SubOpcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUB_OPCODE_A 7833 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 7834 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 7835 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 7836 }; 7837 uint32_t Value; 7838 } DW0; 7839 union 7840 { 7841 struct 7842 { 7843 uint32_t FrameWidthMinus1 : __CODEGEN_BITFIELD(0, 7); //!< Frame Width Minus 1 7844 uint32_t Reserved40 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 7845 uint32_t FrameHeightMinus1 : __CODEGEN_BITFIELD(16, 23); //!< Frame Height Minus 1 7846 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 7847 }; 7848 uint32_t Value; 7849 } DW1; 7850 union 7851 { 7852 struct 7853 { 7854 uint32_t McFilterSelect : __CODEGEN_BITFIELD(0, 0); //!< MC_FILTER_SELECT 7855 uint32_t ChromaFullPixelMcFilterMode : __CODEGEN_BITFIELD(1, 1); //!< CHROMA_FULL_PIXEL_MC_FILTER_MODE 7856 uint32_t Reserved66 : __CODEGEN_BITFIELD(2, 3); //!< Reserved 7857 uint32_t Dblkfiltertype : __CODEGEN_BITFIELD(4, 4); //!< DBLKFILTERTYPE 7858 uint32_t Skeyframeflag : __CODEGEN_BITFIELD(5, 5); //!< SKEYFRAMEFLAG 7859 uint32_t SegmentationIdStreamoutEnable : __CODEGEN_BITFIELD(6, 6); //!< SEGMENTATION_ID_STREAMOUT_ENABLE 7860 uint32_t SegmentationIdStreaminEnable : __CODEGEN_BITFIELD(7, 7); //!< SEGMENTATION_ID_STREAMIN_ENABLE 7861 uint32_t SegmentEnableFlag : __CODEGEN_BITFIELD(8, 8); //!< SEGMENT_ENABLE_FLAG 7862 uint32_t UpdateMbsegmentMapFlag : __CODEGEN_BITFIELD(9, 9); //!< UPDATE_MBSEGMENT_MAP_FLAG 7863 uint32_t MbNocoeffSkipflag : __CODEGEN_BITFIELD(10, 10); //!< MB_NOCOEFF_SKIPFLAG 7864 uint32_t ModeReferenceLoopFilterDeltaEnabled : __CODEGEN_BITFIELD(11, 11); //!< MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED 7865 uint32_t GoldenRefPictureMvSignbiasFlag : __CODEGEN_BITFIELD(12, 12); //!< Golden Ref Picture MV SignBias Flag 7866 uint32_t AlternateRefPicMvSignbiasFlag : __CODEGEN_BITFIELD(13, 13); //!< Alternate Ref Pic MV SignBias Flag 7867 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 7868 uint32_t DeblockSharpnessLevel : __CODEGEN_BITFIELD(16, 18); //!< Deblock Sharpness Level 7869 uint32_t Reserved83 : __CODEGEN_BITFIELD(19, 23); //!< Reserved 7870 uint32_t Log2NumOfPartition : __CODEGEN_BITFIELD(24, 25); //!< LOG2_NUM_OF_PARTITION 7871 uint32_t Reserved90 : __CODEGEN_BITFIELD(26, 31); //!< Reserved 7872 }; 7873 uint32_t Value; 7874 } DW2; 7875 union 7876 { 7877 struct 7878 { 7879 uint32_t DblkfilterlevelForSegment0 : __CODEGEN_BITFIELD(0, 5); //!< DBLKFILTERLEVEL_FOR_SEGMENT0 7880 uint32_t Reserved102 : __CODEGEN_BITFIELD(6, 7); //!< Reserved 7881 uint32_t DblkfilterlevelForSegment1 : __CODEGEN_BITFIELD(8, 13); //!< DBLKFILTERLEVEL_FOR_SEGMENT1 7882 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 7883 uint32_t DblkfilterlevelForSegment2 : __CODEGEN_BITFIELD(16, 21); //!< DBLKFILTERLEVEL_FOR_SEGMENT2 7884 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 7885 uint32_t DblkfilterlevelForSegment3 : __CODEGEN_BITFIELD(24, 29); //!< DBLKFILTERLEVEL_FOR_SEGMENT3 7886 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31); //!< Reserved 7887 }; 7888 uint32_t Value; 7889 } DW3; 7890 union 7891 { 7892 struct 7893 { 7894 uint32_t QuantizerValue0Blocktype0Y1Dc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [0][BlockType0=Y1DC], Decoder Only 7895 uint32_t Reserved137 : __CODEGEN_BITFIELD(9, 15); //!< Reserved, Decoder Only 7896 uint32_t QuantizerValue0Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [0][BlockType1=Y1AC], Decoder Only 7897 uint32_t Reserved153 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 7898 } dec; 7899 struct 7900 { 7901 uint32_t Seg0Qindex : __CODEGEN_BITFIELD(0, 6); //!< Seg 0 Qindex, Encoder Only 7902 uint32_t Reserved135 : __CODEGEN_BITFIELD(7, 7); //!< Reserved, Encoder Only 7903 uint32_t Seg1Qindex : __CODEGEN_BITFIELD(8, 14); //!< Seg 1 Qindex, Encoder Only 7904 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15); //!< Reserved, Encoder Only 7905 uint32_t Seg2Qindex : __CODEGEN_BITFIELD(16, 22); //!< Seg 2 Qindex, Encoder Only 7906 uint32_t Reserved151 : __CODEGEN_BITFIELD(23, 23); //!< Reserved, Encoder Only 7907 uint32_t Seg3Qindex : __CODEGEN_BITFIELD(24, 30); //!< Seg 3 Qindex, Encoder Only 7908 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 7909 } enc; 7910 uint32_t Value; 7911 } DW4; 7912 union 7913 { 7914 struct 7915 { 7916 uint32_t QuantizerValue0Blocktype2Uvdc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [0][BlockType2=UVDC], Decoder Only 7917 uint32_t Reserved169 : __CODEGEN_BITFIELD(9, 15); //!< Reserved, Decoder Only 7918 uint32_t QuantizerValue0Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [0][BlockType3=UVAC], Decoder Only 7919 uint32_t Reserved185 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 7920 } dec; 7921 struct 7922 { 7923 uint32_t Y2DcQindexDelta : __CODEGEN_BITFIELD(0, 3); //!< Y2dc Qindex Delta, Encoder Only 7924 uint32_t Y2AcQindexDeltaSign : __CODEGEN_BITFIELD(4, 4); //!< Y2ac Qindex Delta Sign , Encoder Only 7925 uint32_t Reserved165 : __CODEGEN_BITFIELD(5, 7); //!< Reserved, Encoder Only 7926 uint32_t Y2AcQindexDelta : __CODEGEN_BITFIELD(8, 11); //!< Y2ac Qindex Delta , Encoder Only 7927 uint32_t Y2AcQindexSign : __CODEGEN_BITFIELD(12, 12); //!< Y2ac Qindex Sign, Encoder Only 7928 uint32_t Reserved173 : __CODEGEN_BITFIELD(13, 15); //!< Reserved, Encoder Only 7929 uint32_t UvdcQindexDelta : __CODEGEN_BITFIELD(16, 19); //!< UVdc Qindex Delta, Encoder Only 7930 uint32_t UvdcQindexDeltaSign : __CODEGEN_BITFIELD(20, 20); //!< UVdc Qindex Delta Sign, Encoder Only 7931 uint32_t Reserved181 : __CODEGEN_BITFIELD(21, 23); //!< Reserved, Encoder Only 7932 uint32_t UvacQindexdelta : __CODEGEN_BITFIELD(24, 27); //!< UVac QindexDelta, Encoder Only 7933 uint32_t UvacQindexDeltaSign : __CODEGEN_BITFIELD(28, 28); //!< UVac Qindex Delta Sign, Encoder Only 7934 uint32_t Reserved189 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 7935 } enc; 7936 uint32_t Value; 7937 } DW5; 7938 union 7939 { 7940 struct 7941 { 7942 uint32_t QuantizerValue0Blocktype4Y2Dc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [0][BlockType4=Y2DC], Decoder Only 7943 uint32_t Reserved201 : __CODEGEN_BITFIELD(9, 15); //!< Reserved, Decoder Only 7944 uint32_t QuantizerValue0Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [0][BlockType5=Y2AC], Decoder Only 7945 uint32_t Reserved217 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 7946 } dec; 7947 struct 7948 { 7949 uint32_t Y1DcQindexDelta : __CODEGEN_BITFIELD(0, 3); //!< Y1dc Qindex Delta, Encoder Only 7950 uint32_t Y1DcQindexDeltaSign : __CODEGEN_BITFIELD(4, 4); //!< Y1dc Qindex Delta Sign , Encoder Only 7951 uint32_t Reserved197 : __CODEGEN_BITFIELD(5, 31); //!< Reserved 7952 } enc; 7953 uint32_t Value; 7954 } DW6; 7955 union 7956 { 7957 struct 7958 { 7959 uint32_t QuantizerValue1Blocktype0Y1Dc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [1][BlockType0=Y1DC], Decoder Only 7960 uint32_t Reserved233 : __CODEGEN_BITFIELD(9, 15); //!< Reserved, Decoder Only 7961 uint32_t QuantizerValue1Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [1][BlockType1=Y1AC], Decoder Only 7962 uint32_t Reserved249 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 7963 } dec; 7964 struct 7965 { 7966 uint32_t ClampQindexLow : __CODEGEN_BITFIELD(0, 6); //!< Clamp Qindex Low, Encoder Only 7967 uint32_t Reserved231 : __CODEGEN_BITFIELD(7, 7); //!< Reserved, Encoder Only 7968 uint32_t ClampQindexHigh : __CODEGEN_BITFIELD(8, 14); //!< Clamp Qindex high, Encoder Only 7969 uint32_t Reserved239 : __CODEGEN_BITFIELD(15, 31); //!< Reserved 7970 } enc; 7971 uint32_t Value; 7972 } DW7; 7973 union 7974 { 7975 struct 7976 { 7977 uint32_t QuantizerValue1Blocktype2Uvdc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [1][BlockType2=UVDC] 7978 uint32_t Reserved265 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 7979 uint32_t QuantizerValue1Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [1][BlockType3=UVAC] 7980 uint32_t Reserved281 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 7981 }; 7982 uint32_t Value; 7983 } DW8; 7984 union 7985 { 7986 struct 7987 { 7988 uint32_t QuantizerValue1Blocktype4Y2Dc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [1][BlockType4=Y2DC] 7989 uint32_t Reserved297 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 7990 uint32_t QuantizerValue1Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [1][BlockType5=Y2AC] 7991 uint32_t Reserved313 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 7992 }; 7993 uint32_t Value; 7994 } DW9; 7995 union 7996 { 7997 struct 7998 { 7999 uint32_t QuantizerValue2Blocktype0Y1Dc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [2][BlockType0=Y1DC] 8000 uint32_t Reserved329 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 8001 uint32_t QuantizerValue2Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [2][BlockType1=Y1AC] 8002 uint32_t Reserved345 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 8003 }; 8004 uint32_t Value; 8005 } DW10; 8006 union 8007 { 8008 struct 8009 { 8010 uint32_t QuantizerValue2Blocktype2Uvdc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [2][BlockType2=UVDC] 8011 uint32_t Reserved361 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 8012 uint32_t QuantizerValue2Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [2][BlockType3=UVAC] 8013 uint32_t Reserved377 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 8014 }; 8015 uint32_t Value; 8016 } DW11; 8017 union 8018 { 8019 struct 8020 { 8021 uint32_t QuantizerValue2Blocktype4Y2Dc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [2][BlockType4=Y2DC] 8022 uint32_t Reserved393 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 8023 uint32_t QuantizerValue2Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [2][BlockType5=Y2AC] 8024 uint32_t Reserved409 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 8025 }; 8026 uint32_t Value; 8027 } DW12; 8028 union 8029 { 8030 struct 8031 { 8032 uint32_t QuantizerValue3Blocktype0Y1Dc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [3][BlockType0=Y1DC] 8033 uint32_t Reserved425 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 8034 uint32_t QuantizerValue3Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [3][BlockType1=Y1AC] 8035 uint32_t Reserved441 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 8036 }; 8037 uint32_t Value; 8038 } DW13; 8039 union 8040 { 8041 struct 8042 { 8043 uint32_t QuantizerValue3Blocktype2Uvdc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [3][BlockType2=UVDC] 8044 uint32_t Reserved457 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 8045 uint32_t QuantizerValue3Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [3][BlockType3=UVAC] 8046 uint32_t Reserved473 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 8047 }; 8048 uint32_t Value; 8049 } DW14; 8050 union 8051 { 8052 struct 8053 { 8054 uint32_t QuantizerValue3Blocktype4Y2Dc : __CODEGEN_BITFIELD(0, 8); //!< Quantizer Value [3][BlockType4=Y2DC] 8055 uint32_t Reserved489 : __CODEGEN_BITFIELD(9, 15); //!< Reserved 8056 uint32_t QuantizerValue3Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24); //!< Quantizer Value [3][BlockType5=Y2AC] 8057 uint32_t Reserved505 : __CODEGEN_BITFIELD(25, 31); //!< Reserved 8058 }; 8059 uint32_t Value; 8060 } DW15; 8061 SPLITBASEADDRESS4KBYTEALIGNED_CMD CoeffprobabilityStreaminBaseAddress; //!< DW16..17, CoeffProbability StreamIn Base Address 8062 union 8063 { 8064 struct 8065 { 8066 uint32_t Reserved576 : __CODEGEN_BITFIELD(0, 0); //!< Reserved 8067 uint32_t CoeffprobabilityStreaminAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD(1, 6); //!< CoeffProbability StreamIn Address - Index to Memory Object Control State (MOCS) Tables 8068 uint32_t CoeffprobabilityStreaminArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL 8069 uint32_t CoeffprobabilityStreaminMemoryCompressionEnable : __CODEGEN_BITFIELD(9, 9); //!< CoeffProbability StreamIn - Memory Compression Enable 8070 uint32_t CoeffprobabilityStreaminMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10); //!< COEFFPROBABILITY_STREAMIN_MEMORY_COMPRESSION_MODE 8071 uint32_t Reserved587 : __CODEGEN_BITFIELD(11, 12); //!< Reserved 8072 uint32_t CoeffprobabilityStreaminTiledResourceMode : __CODEGEN_BITFIELD(13, 14); //!< COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE 8073 uint32_t Reserved591 : __CODEGEN_BITFIELD(15, 31); //!< Reserved 8074 }; 8075 uint32_t Value; 8076 } DW18; 8077 union 8078 { 8079 struct 8080 { 8081 uint32_t Mbsegmentidtreeprobs0 : __CODEGEN_BITFIELD(0, 7); //!< MBSegmentIDTreeProbs[0] 8082 uint32_t Mbsegmentidtreeprobs1 : __CODEGEN_BITFIELD(8, 15); //!< MBSegmentIDTreeProbs[1] 8083 uint32_t Mbsegmentidtreeprobs2 : __CODEGEN_BITFIELD(16, 23); //!< MBSegmentIDTreeProbs[2] 8084 uint32_t Reserved632 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 8085 }; 8086 uint32_t Value; 8087 } DW19; 8088 union 8089 { 8090 struct 8091 { 8092 uint32_t Interpredfromgrefrefprob : __CODEGEN_BITFIELD(0, 7); //!< InterPredFromGRefRefProb 8093 uint32_t Interpredfromlastrefprob : __CODEGEN_BITFIELD(8, 15); //!< InterPredFromLastRefProb 8094 uint32_t Intrambprob : __CODEGEN_BITFIELD(16, 23); //!< IntraMBProb 8095 uint32_t Mbnocoeffskipfalseprob : __CODEGEN_BITFIELD(24, 31); //!< MBNoCoeffSkipFalseProb 8096 }; 8097 uint32_t Value; 8098 } DW20; 8099 union 8100 { 8101 struct 8102 { 8103 uint32_t Ymodeprob0 : __CODEGEN_BITFIELD(0, 7); //!< YModeProb[0] 8104 uint32_t Ymodeprob1 : __CODEGEN_BITFIELD(8, 15); //!< YModeProb[1] 8105 uint32_t Ymodeprob2 : __CODEGEN_BITFIELD(16, 23); //!< YModeProb[2] 8106 uint32_t Ymodeprob3 : __CODEGEN_BITFIELD(24, 31); //!< YModeProb[3] 8107 }; 8108 uint32_t Value; 8109 } DW21; 8110 union 8111 { 8112 struct 8113 { 8114 uint32_t Uvmodeprob0 : __CODEGEN_BITFIELD(0, 7); //!< UVModeProb[0] 8115 uint32_t Uvmodeprob1 : __CODEGEN_BITFIELD(8, 15); //!< UVModeProb[1] 8116 uint32_t Uvmodeprob2 : __CODEGEN_BITFIELD(16, 23); //!< UVModeProb[2] 8117 uint32_t Reserved728 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 8118 }; 8119 uint32_t Value; 8120 } DW22; 8121 union 8122 { 8123 struct 8124 { 8125 uint32_t Mvupdateprobs00 : __CODEGEN_BITFIELD(0, 7); //!< MVUpdateProbs[0][0] 8126 uint32_t Mvupdateprobs01 : __CODEGEN_BITFIELD(8, 15); //!< MVUpdateProbs[0][1] 8127 uint32_t Mvupdateprobs02 : __CODEGEN_BITFIELD(16, 23); //!< MVUpdateProbs[0][2] 8128 uint32_t Mvupdateprobs03 : __CODEGEN_BITFIELD(24, 31); //!< MVUpdateProbs[0][3] 8129 }; 8130 uint32_t Value; 8131 } DW23; 8132 union 8133 { 8134 struct 8135 { 8136 uint32_t Mvupdateprobs04 : __CODEGEN_BITFIELD(0, 7); //!< MVUpdateProbs[0][4] 8137 uint32_t Mvupdateprobs05 : __CODEGEN_BITFIELD(8, 15); //!< MVUpdateProbs[0][5] 8138 uint32_t Mvupdateprobs06 : __CODEGEN_BITFIELD(16, 23); //!< MVUpdateProbs[0][6] 8139 uint32_t Mvupdateprobs07 : __CODEGEN_BITFIELD(24, 31); //!< MVUpdateProbs[0][7] 8140 }; 8141 uint32_t Value; 8142 } DW24; 8143 union 8144 { 8145 struct 8146 { 8147 uint32_t Mvupdateprobs08 : __CODEGEN_BITFIELD(0, 7); //!< MVUpdateProbs[0][8] 8148 uint32_t Mvupdateprobs09 : __CODEGEN_BITFIELD(8, 15); //!< MVUpdateProbs[0][9] 8149 uint32_t Mvupdateprobs010 : __CODEGEN_BITFIELD(16, 23); //!< MVUpdateProbs[0][10] 8150 uint32_t Mvupdateprobs011 : __CODEGEN_BITFIELD(24, 31); //!< MVUpdateProbs[0][11] 8151 }; 8152 uint32_t Value; 8153 } DW25; 8154 union 8155 { 8156 struct 8157 { 8158 uint32_t Mvupdateprobs012 : __CODEGEN_BITFIELD(0, 7); //!< MVUpdateProbs[0][12] 8159 uint32_t Mvupdateprobs013 : __CODEGEN_BITFIELD(8, 15); //!< MVUpdateProbs[0][13] 8160 uint32_t Mvupdateprobs014 : __CODEGEN_BITFIELD(16, 23); //!< MVUpdateProbs[0][14] 8161 uint32_t Mvupdateprobs015 : __CODEGEN_BITFIELD(24, 31); //!< MVUpdateProbs[0][15] 8162 }; 8163 uint32_t Value; 8164 } DW26; 8165 union 8166 { 8167 struct 8168 { 8169 uint32_t Mvupdateprobs016 : __CODEGEN_BITFIELD(0, 7); //!< MVUpdateProbs[0][16] 8170 uint32_t Mvupdateprobs017 : __CODEGEN_BITFIELD(8, 15); //!< MVUpdateProbs[0][17] 8171 uint32_t Mvupdateprobs018 : __CODEGEN_BITFIELD(16, 23); //!< MVUpdateProbs[0][18] 8172 uint32_t Reserved888 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 8173 }; 8174 uint32_t Value; 8175 } DW27; 8176 union 8177 { 8178 struct 8179 { 8180 uint32_t Mvupdateprobs10 : __CODEGEN_BITFIELD(0, 7); //!< MVUpdateProbs[1][0] 8181 uint32_t Mvupdateprobs11 : __CODEGEN_BITFIELD(8, 15); //!< MVUpdateProbs[1][1] 8182 uint32_t Mvupdateprobs12 : __CODEGEN_BITFIELD(16, 23); //!< MVUpdateProbs[1][2] 8183 uint32_t Mvupdateprobs13 : __CODEGEN_BITFIELD(24, 31); //!< MVUpdateProbs[1][3] 8184 }; 8185 uint32_t Value; 8186 } DW28; 8187 union 8188 { 8189 struct 8190 { 8191 uint32_t Mvupdateprobs14 : __CODEGEN_BITFIELD(0, 7); //!< MVUpdateProbs[1][4] 8192 uint32_t Mvupdateprobs15 : __CODEGEN_BITFIELD(8, 15); //!< MVUpdateProbs[1][5] 8193 uint32_t Mvupdateprobs16 : __CODEGEN_BITFIELD(16, 23); //!< MVUpdateProbs[1][6] 8194 uint32_t Mvupdateprobs17 : __CODEGEN_BITFIELD(24, 31); //!< MVUpdateProbs[1][7] 8195 }; 8196 uint32_t Value; 8197 } DW29; 8198 union 8199 { 8200 struct 8201 { 8202 uint32_t Mvupdateprobs18 : __CODEGEN_BITFIELD(0, 7); //!< MVUpdateProbs[1][8] 8203 uint32_t Mvupdateprobs19 : __CODEGEN_BITFIELD(8, 15); //!< MVUpdateProbs[1][9] 8204 uint32_t Mvupdateprobs110 : __CODEGEN_BITFIELD(16, 23); //!< MVUpdateProbs[1][10] 8205 uint32_t Mvupdateprobs111 : __CODEGEN_BITFIELD(24, 31); //!< MVUpdateProbs[1][11] 8206 }; 8207 uint32_t Value; 8208 } DW30; 8209 union 8210 { 8211 struct 8212 { 8213 uint32_t Mvupdateprobs112 : __CODEGEN_BITFIELD(0, 7); //!< MVUpdateProbs[1][12] 8214 uint32_t Mvupdateprobs113 : __CODEGEN_BITFIELD(8, 15); //!< MVUpdateProbs[1][13] 8215 uint32_t Mvupdateprobs114 : __CODEGEN_BITFIELD(16, 23); //!< MVUpdateProbs[1][14] 8216 uint32_t Mvupdateprobs115 : __CODEGEN_BITFIELD(24, 31); //!< MVUpdateProbs[1][15] 8217 }; 8218 uint32_t Value; 8219 } DW31; 8220 union 8221 { 8222 struct 8223 { 8224 uint32_t Mvupdateprobs116 : __CODEGEN_BITFIELD(0, 7); //!< MVUpdateProbs[1][16] 8225 uint32_t Mvupdateprobs117 : __CODEGEN_BITFIELD(8, 15); //!< MVUpdateProbs[1][17] 8226 uint32_t Mvupdateprobs118 : __CODEGEN_BITFIELD(16, 23); //!< MVUpdateProbs[1][18] 8227 uint32_t Reserved1048 : __CODEGEN_BITFIELD(24, 31); //!< Reserved 8228 }; 8229 uint32_t Value; 8230 } DW32; 8231 union 8232 { 8233 struct 8234 { 8235 uint32_t Reflfdelta0ForIntraFrame : __CODEGEN_BITFIELD(0, 6); //!< RefLFDelta0 (for INTRA FRAME) 8236 uint32_t Reserved1063 : __CODEGEN_BITFIELD(7, 7); //!< Reserved 8237 uint32_t Reflfdelta1ForLastFrame : __CODEGEN_BITFIELD(8, 14); //!< RefLFDelta1 (for LAST FRAME) 8238 uint32_t Reserved1071 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 8239 uint32_t Reflfdelta2ForGoldenFrame : __CODEGEN_BITFIELD(16, 22); //!< RefLFDelta2 (for GOLDEN FRAME) 8240 uint32_t Reserved1079 : __CODEGEN_BITFIELD(23, 23); //!< Reserved 8241 uint32_t Reflfdelta3ForAltrefFrame : __CODEGEN_BITFIELD(24, 30); //!< RefLFDelta3 (for ALTREF FRAME) 8242 uint32_t Reserved1087 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 8243 }; 8244 uint32_t Value; 8245 } DW33; 8246 union 8247 { 8248 struct 8249 { 8250 uint32_t Modelfdelta0ForBPredMode : __CODEGEN_BITFIELD(0, 6); //!< ModeLFDelta0 (for B_PRED mode) 8251 uint32_t Reserved1095 : __CODEGEN_BITFIELD(7, 7); //!< Reserved 8252 uint32_t Modelfdelta1ForZeromvMode : __CODEGEN_BITFIELD(8, 14); //!< ModeLFDelta1(for ZEROMV mode) 8253 uint32_t Reserved1103 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 8254 uint32_t Modelfdelta2ForNearestNearAndNewMode : __CODEGEN_BITFIELD(16, 22); //!< ModeLFDelta2 (for Nearest, Near and New mode) 8255 uint32_t Reserved1111 : __CODEGEN_BITFIELD(23, 23); //!< Reserved 8256 uint32_t Modelfdelta3ForSplitmvMode : __CODEGEN_BITFIELD(24, 30); //!< ModeLFDelta3 (for SPLITMV mode) 8257 uint32_t Reserved1119 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 8258 }; 8259 uint32_t Value; 8260 } DW34; 8261 SPLITBASEADDRESS4KBYTEALIGNED_CMD SegmentationIdStreamBaseAddress; //!< DW35..36, Segmentation ID Stream Base Address 8262 union 8263 { 8264 struct 8265 { 8266 uint32_t Reserved1184 : __CODEGEN_BITFIELD(0, 0); //!< Reserved 8267 uint32_t CoeffprobabilityStreaminAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD(1, 6); //!< CoeffProbability StreamIn Address - Index to Memory Object Control State (MOCS) Tables 8268 uint32_t SegmentationIdStreamArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL 8269 uint32_t SegmentationIdStreamMemoryCompressionEnable : __CODEGEN_BITFIELD(9, 9); //!< Segmentation ID Stream - Memory Compression Enable 8270 uint32_t SegmentationIdStreamMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10); //!< SEGMENTATION_ID_STREAM_MEMORY_COMPRESSION_MODE 8271 uint32_t Reserved1195 : __CODEGEN_BITFIELD(11, 12); //!< Reserved 8272 uint32_t SegmentationIdStreamTiledResourceMode : __CODEGEN_BITFIELD(13, 14); //!< SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE 8273 uint32_t Reserved1199 : __CODEGEN_BITFIELD(15, 31); //!< Reserved 8274 }; 8275 uint32_t Value; 8276 } DW37; 8277 8278 //! \name Local enumerations 8279 8280 enum SUB_OPCODE_B 8281 { 8282 SUB_OPCODE_B_MFXVP8PICSTATE = 0, //!< No additional details 8283 }; 8284 8285 enum SUB_OPCODE_A 8286 { 8287 SUB_OPCODE_A_VP8COMMON = 0, //!< No additional details 8288 }; 8289 8290 enum MEDIA_COMMAND_OPCODE 8291 { 8292 MEDIA_COMMAND_OPCODE_VP8 = 4, //!< No additional details 8293 }; 8294 8295 enum PIPELINE 8296 { 8297 PIPELINE_VIDEOCODEC = 2, //!< No additional details 8298 }; 8299 8300 enum COMMAND_TYPE 8301 { 8302 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 8303 }; 8304 8305 //! \brief MC_FILTER_SELECT 8306 //! \details 8307 //! To specify VP8 Profile of operation. 8308 enum MC_FILTER_SELECT 8309 { 8310 MC_FILTER_SELECT_UNNAMED0 = 0, //!< 6-tap filter (regular filter mode) 8311 MC_FILTER_SELECT_UNNAMED1 = 1, //!< 2-tap bilinear filter (simple profile/version mode) 8312 }; 8313 8314 //! \brief CHROMA_FULL_PIXEL_MC_FILTER_MODE 8315 //! \details 8316 //! To specify VP8 Profile of operation. 8317 enum CHROMA_FULL_PIXEL_MC_FILTER_MODE 8318 { 8319 CHROMA_FULL_PIXEL_MC_FILTER_MODE_UNNAMED0 = 0, //!< Chroma MC filter operates in sub-pixel mode 8320 CHROMA_FULL_PIXEL_MC_FILTER_MODE_UNNAMED1 = 1, //!< Chroma MC filter only operates in full pixel position, i.e. no sub-pixel interpolation. 8321 }; 8322 8323 //! \brief DBLKFILTERTYPE 8324 //! \details 8325 //! To specify VP8 Profile of operation. 8326 enum DBLKFILTERTYPE 8327 { 8328 DBLKFILTERTYPE_UNNAMED0 = 0, //!< Use a full feature normal deblocking filter 8329 DBLKFILTERTYPE_UNNAMED1 = 1, //!< Use a simple filter for deblocking 8330 }; 8331 8332 enum SKEYFRAMEFLAG 8333 { 8334 SKEYFRAMEFLAG_NON_KEYFRAME_P_FRAME = 0, //!< No additional details 8335 SKEYFRAMEFLAG_KEYFRAME_I_FRAME = 1, //!< No additional details 8336 }; 8337 8338 //! \brief SEGMENTATION_ID_STREAMOUT_ENABLE 8339 //! \details 8340 //! When 0, no output needed. 8341 enum SEGMENTATION_ID_STREAMOUT_ENABLE 8342 { 8343 SEGMENTATION_ID_STREAMOUT_ENABLE_STREAMOUTDISABLED = 0, //!< No additional details 8344 SEGMENTATION_ID_STREAMOUT_ENABLE_STREAMOUTENABLED = 1, //!< No additional details 8345 }; 8346 8347 //! \brief SEGMENTATION_ID_STREAMIN_ENABLE 8348 //! \details 8349 //! When 0, no input needed. 8350 enum SEGMENTATION_ID_STREAMIN_ENABLE 8351 { 8352 SEGMENTATION_ID_STREAMIN_ENABLE_STREAMINDISABLED = 0, //!< No additional details 8353 SEGMENTATION_ID_STREAMIN_ENABLE_STREAMINENABLED = 1, //!< No additional details 8354 }; 8355 8356 enum SEGMENT_ENABLE_FLAG 8357 { 8358 SEGMENT_ENABLE_FLAG_UNNAMED0 = 0, //!< Disable Segmentation processing in the current frame 8359 SEGMENT_ENABLE_FLAG_UNNAMED1 = 1, //!< Enable Segmentation processing in the current frame 8360 }; 8361 8362 enum UPDATE_MBSEGMENT_MAP_FLAG 8363 { 8364 UPDATE_MBSEGMENT_MAP_FLAG_UNNAMED0 = 0, //!< Disable segmentation update 8365 UPDATE_MBSEGMENT_MAP_FLAG_UNNAMED1 = 1, //!< Enable segmentation update, and to enable reading segment_id for each MB. 8366 }; 8367 8368 //! \brief MB_NOCOEFF_SKIPFLAG 8369 //! \details 8370 //! Frame level control if Skip MB (with no non-zero coefficient) is allowed 8371 //! or not. 8372 enum MB_NOCOEFF_SKIPFLAG 8373 { 8374 MB_NOCOEFF_SKIPFLAG_UNNAMED0 = 0, //!< All MBs will have its MB level signaling mb_skip_coeff forced to 0. That is, no skip of coefficient record in the bitstream (even their values are all 0s) 8375 MB_NOCOEFF_SKIPFLAG_UNNAMED1 = 1, //!< Skip MB is enabled in the per MB record. 8376 }; 8377 8378 enum MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED 8379 { 8380 MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED_UNNAMED0 = 0, //!< Mode or Reference Loop Filter Delta Adjustment for current frame is disabled. 8381 MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED_UNNAMED1 = 1, //!< Mode or Reference Loop Filter Delta Adjustment for current frame is enabled. 8382 }; 8383 8384 enum LOG2_NUM_OF_PARTITION 8385 { 8386 LOG2_NUM_OF_PARTITION_1TOKENPARTITION = 0, //!< No additional details 8387 LOG2_NUM_OF_PARTITION_2TOKENPARTITION = 1, //!< No additional details 8388 LOG2_NUM_OF_PARTITION_4TOKENPARTITION = 2, //!< No additional details 8389 LOG2_NUM_OF_PARTITION_8TOKENPARTITION = 3, //!< No additional details 8390 }; 8391 8392 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT0 8393 //! \details 8394 //! There are max 4 segments per frame, each segment can have its own 8395 //! deblocking filter level. When segmentation is disabled, only segment 0 8396 //! parameter is used for the entire frame. 8397 enum DBLKFILTERLEVEL_FOR_SEGMENT0 8398 { 8399 DBLKFILTERLEVEL_FOR_SEGMENT0_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 8400 }; 8401 8402 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT1 8403 //! \details 8404 //! There are max 4 segments per frame, each segment can have its own 8405 //! deblocking filter level. When segmentation is disabled, only segment 0 8406 //! parameter is used for the entire frame. 8407 enum DBLKFILTERLEVEL_FOR_SEGMENT1 8408 { 8409 DBLKFILTERLEVEL_FOR_SEGMENT1_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 8410 }; 8411 8412 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT2 8413 //! \details 8414 //! There are max 4 segments per frame, each segment can have its own 8415 //! deblocking filter level. When segmentation is disabled, only segment 0 8416 //! parameter is used for the entire frame. 8417 enum DBLKFILTERLEVEL_FOR_SEGMENT2 8418 { 8419 DBLKFILTERLEVEL_FOR_SEGMENT2_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 8420 }; 8421 8422 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT3 8423 //! \details 8424 //! There are max 4 segments per frame, each segment can have its own 8425 //! deblocking filter level. When segmentation is disabled, only segment 0 8426 //! parameter is used for the entire frame. 8427 enum DBLKFILTERLEVEL_FOR_SEGMENT3 8428 { 8429 DBLKFILTERLEVEL_FOR_SEGMENT3_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 8430 }; 8431 8432 //! \brief COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL 8433 //! \details 8434 //! This field controls the priority of arbitration used in the GAC/GAM 8435 //! pipeline for this surface. 8436 enum COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL 8437 { 8438 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8439 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8440 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8441 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8442 }; 8443 8444 //! \brief COEFFPROBABILITY_STREAMIN_MEMORY_COMPRESSION_MODE 8445 //! \details 8446 //! Distinguishes Vertical from Horizontal compression. Please refer to 8447 //! vol1aMemory Data Formats chapter, Media Memory Compression 8448 //! section for more details. 8449 enum COEFFPROBABILITY_STREAMIN_MEMORY_COMPRESSION_MODE 8450 { 8451 COEFFPROBABILITY_STREAMIN_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 8452 COEFFPROBABILITY_STREAMIN_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 8453 }; 8454 8455 //! \brief COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE 8456 //! \details 8457 //! For Media Surfaces:This field specifies the tiled resource mode. 8458 enum COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE 8459 { 8460 COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 8461 COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 8462 COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 8463 }; 8464 8465 //! \brief SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL 8466 //! \details 8467 //! This field controls the priority of arbitration used in the GAC/GAM 8468 //! pipeline for this surface. 8469 enum SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL 8470 { 8471 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8472 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8473 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8474 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8475 }; 8476 8477 //! \brief SEGMENTATION_ID_STREAM_MEMORY_COMPRESSION_MODE 8478 //! \details 8479 //! Distinguishes Vertical from Horizontal compression. Please refer to 8480 //! vol1aMemory Data Formats chapter, Media Memory Compression 8481 //! section for more details. 8482 enum SEGMENTATION_ID_STREAM_MEMORY_COMPRESSION_MODE 8483 { 8484 SEGMENTATION_ID_STREAM_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 8485 SEGMENTATION_ID_STREAM_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 8486 }; 8487 8488 //! \brief SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE 8489 //! \details 8490 //! For Media Surfaces:This field specifies the tiled resource mode. 8491 enum SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE 8492 { 8493 SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 8494 SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 8495 SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 8496 }; 8497 8498 //! \name Initializations 8499 8500 //! \brief Explicit member initialization function 8501 MFX_VP8_PIC_STATE_CMD(); 8502 8503 static const size_t dwSize = 38; 8504 static const size_t byteSize = 152; 8505 }; 8506 8507 //! 8508 //! \brief MFX_JPEG_HUFF_TABLE_STATE 8509 //! \details 8510 //! This Huffman table commands contains both DC and AC tables for either 8511 //! luma or chroma. Once a Huffman table has been defined for a particular 8512 //! destination, it replaces the previous tables stored in that destination 8513 //! and shall be used in the remaining Scans of the current image. A Huffman 8514 //! table will be sent to H/W only when it is loaded from bitstream. 8515 //! 8516 struct MFX_JPEG_HUFF_TABLE_STATE_CMD 8517 { 8518 union 8519 { 8520 struct 8521 { 8522 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 8523 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 8524 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 8525 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 8526 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 8527 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 8528 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 8529 }; 8530 uint32_t Value; 8531 } DW0; 8532 union 8533 { 8534 struct 8535 { 8536 uint32_t Hufftableid1Bit : __CODEGEN_BITFIELD(0, 0); //!< HUFFTABLEID_1_BIT 8537 uint32_t Reserved33 : __CODEGEN_BITFIELD(1, 31); //!< Reserved 8538 }; 8539 uint32_t Value; 8540 } DW1; 8541 uint32_t DcBits128BitArray[3]; //!< DC_BITS (12 8-bit array) 8542 uint32_t DcHuffval128BitArray[3]; //!< DC_HUFFVAL (12 8-bit array) 8543 uint32_t AcBits168BitArray[4]; //!< AC_BITS (16 8-bit array) 8544 uint32_t AcHuffval1608BitArray[40]; //!< AC_HUFFVAL (160 8-bit array) 8545 union 8546 { 8547 struct 8548 { 8549 uint32_t AcHuffval28BitArray : __CODEGEN_BITFIELD(0, 15); //!< AC_HUFFVAL(2-8 bit array) 8550 uint32_t Reserved1680 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8551 }; 8552 uint32_t Value; 8553 } DW52; 8554 8555 //! \name Local enumerations 8556 8557 enum SUBOPCODE_B 8558 { 8559 SUBOPCODE_B_UNNAMED2 = 2, //!< No additional details 8560 }; 8561 8562 enum SUBOPCODE_A 8563 { 8564 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 8565 }; 8566 8567 enum MEDIA_COMMAND_OPCODE 8568 { 8569 MEDIA_COMMAND_OPCODE_JPEGCOMMON = 7, //!< No additional details 8570 }; 8571 8572 enum PIPELINE 8573 { 8574 PIPELINE_MFXMULTIDW = 2, //!< No additional details 8575 }; 8576 8577 enum COMMAND_TYPE 8578 { 8579 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 8580 }; 8581 8582 //! \brief HUFFTABLEID_1_BIT 8583 //! \details 8584 //! Identifies the huffman table. 8585 enum HUFFTABLEID_1_BIT 8586 { 8587 HUFFTABLEID_1_BIT_Y = 0, //!< Huffman table for Y 8588 }; 8589 8590 //! \name Initializations 8591 8592 //! \brief Explicit member initialization function 8593 MFX_JPEG_HUFF_TABLE_STATE_CMD(); 8594 8595 static const size_t dwSize = 53; 8596 static const size_t byteSize = 212; 8597 }; 8598 8599 //! 8600 //! \brief MFX_PIPE_BUF_ADDR_STATE 8601 //! \details 8602 //! This state command provides the memory base addresses for all row 8603 //! stores, StreamOut buffer and reconstructed picture output buffers 8604 //! required by the MFD or MFC Engine (that are in addition to the row 8605 //! stores of the Bit Stream Decoding/Encoding Unit (BSD/BSE) and the 8606 //! reference picture buffers). This is a picture level state command and 8607 //! is common among all codec standards and for both encoder and decoder 8608 //! operating modes. However, some fields may only applicable to a specific 8609 //! codec standard. All Pixel Surfaces (original, reference frame and 8610 //! reconstructed frame) in the Encoder are programmed with the same surface 8611 //! state (NV12 and TileY format), except each has its own frame buffer base 8612 //! address. In the tile format, there is no need to provide buffer offset 8613 //! for each slice; since from each MB address, the hardware can calculated 8614 //! the corresponding memory location within the frame buffer directly. 8615 //! 8616 struct MFX_PIPE_BUF_ADDR_STATE_CMD 8617 { 8618 union 8619 { 8620 struct 8621 { 8622 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 8623 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 8624 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODE_B 8625 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODE_A 8626 uint32_t CommonOpcode : __CODEGEN_BITFIELD(24, 26); //!< COMMON_OPCODE 8627 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 8628 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 8629 }; 8630 uint32_t Value; 8631 } DW0; 8632 union 8633 { 8634 struct 8635 { 8636 uint32_t Reserved32 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8637 uint32_t PreDeblockingDestinationAddress : __CODEGEN_BITFIELD(6, 31); //!< Pre Deblocking Destination Address 8638 }; 8639 uint32_t Value; 8640 } DW1; 8641 union 8642 { 8643 struct 8644 { 8645 uint32_t PreDeblockingDestinationAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< Pre Deblocking Destination Address High 8646 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8647 }; 8648 uint32_t Value; 8649 } DW2; 8650 union 8651 { 8652 struct 8653 { 8654 uint32_t PreDeblockingMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Pre Deblocking - Memory Object Control State 8655 uint32_t PreDeblockingArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL 8656 uint32_t PreDeblockingCompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 9, 9); //!< Pre Deblocking - Compression Accumulation Buffer Enable 8657 uint32_t Reserved106 : __CODEGEN_BITFIELD(10, 31); //!< Reserved 8658 }; 8659 uint32_t Value; 8660 } DW3; 8661 union 8662 { 8663 struct 8664 { 8665 uint32_t Reserved128 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8666 uint32_t PostDeblockingDestinationAddress : __CODEGEN_BITFIELD(6, 31); //!< Post Deblocking Destination Address 8667 }; 8668 uint32_t Value; 8669 } DW4; 8670 union 8671 { 8672 struct 8673 { 8674 uint32_t PostDeblockingDestinationAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< Post Deblocking Destination Address High 8675 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8676 }; 8677 uint32_t Value; 8678 } DW5; 8679 union 8680 { 8681 struct 8682 { 8683 uint32_t PostDeblockingMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Post Deblocking - Memory Object Control State 8684 uint32_t PostDeblockingArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL 8685 uint32_t PostDeblockingCompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 9, 9); //!< Post Deblocking - Compression Accumulation Buffer Enable 8686 uint32_t Reserved202 : __CODEGEN_BITFIELD(10, 31); //!< Reserved 8687 }; 8688 uint32_t Value; 8689 } DW6; 8690 union 8691 { 8692 struct 8693 { 8694 uint32_t Reserved224 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8695 uint32_t OriginalUncompressedPictureSourceAddress : __CODEGEN_BITFIELD(6, 31); //!< Original Uncompressed Picture Source Address 8696 }; 8697 uint32_t Value; 8698 } DW7; 8699 union 8700 { 8701 struct 8702 { 8703 uint32_t OriginalUncompressedPictureSourceAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< Original Uncompressed Picture Source Address High 8704 uint32_t Reserved272 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8705 }; 8706 uint32_t Value; 8707 } DW8; 8708 union 8709 { 8710 struct 8711 { 8712 uint32_t OriginalUncompressedPictureSourceMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Original Uncompressed Picture Source - Memory Object Control State 8713 uint32_t OriginalUncompressedPictureSourceArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL 8714 uint32_t OriginalUncompressedPictureCompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 9, 9); //!< Original Uncompressed Picture - Compression Accumulation Buffer Enable 8715 uint32_t Reserved298 : __CODEGEN_BITFIELD(10, 31); //!< Reserved 8716 }; 8717 uint32_t Value; 8718 } DW9; 8719 union 8720 { 8721 struct 8722 { 8723 uint32_t Reserved320 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8724 uint32_t StreamoutDataDestinationBaseAddress : __CODEGEN_BITFIELD(6, 31); //!< StreamOut Data Destination Base Address 8725 }; 8726 uint32_t Value; 8727 } DW10; 8728 union 8729 { 8730 struct 8731 { 8732 uint32_t StreamoutDataDestinationBaseAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< StreamOut Data Destination Base Address High 8733 uint32_t Reserved368 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8734 }; 8735 uint32_t Value; 8736 } DW11; 8737 union 8738 { 8739 struct 8740 { 8741 uint32_t StreamoutDataDestinationMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< StreamOut Data Destination - Memory Object Control State 8742 uint32_t StreamoutDataDestinationArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL 8743 uint32_t StreamoutDataDestinationCompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 9, 9); //!< StreamOut Data Destination - Compression Accumulation Buffer Enable 8744 uint32_t Reserved394 : __CODEGEN_BITFIELD(10, 31); //!< Reserved 8745 }; 8746 uint32_t Value; 8747 } DW12; 8748 union 8749 { 8750 struct 8751 { 8752 uint32_t Reserved416 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8753 uint32_t IntraRowStoreScratchBufferBaseAddress : __CODEGEN_BITFIELD(6, 31); //!< Intra Row Store Scratch Buffer Base Address 8754 }; 8755 uint32_t Value; 8756 } DW13; 8757 union 8758 { 8759 struct 8760 { 8761 uint32_t IntraRowStoreScratchBufferBaseAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< Intra Row Store Scratch Buffer Base Address High 8762 uint32_t Reserved464 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8763 }; 8764 uint32_t Value; 8765 } DW14; 8766 union 8767 { 8768 struct 8769 { 8770 uint32_t IntraRowStoreScratchBufferMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Intra Row Store Scratch Buffer - Memory Object Control State 8771 uint32_t IntraRowStoreScratchBufferArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL 8772 uint32_t IntraRowStoreScratchBufferCompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 9, 9); //!< Intra Row Store Scratch Buffer - Compression Accumulation Buffer Enable 8773 uint32_t Reserved490 : __CODEGEN_BITFIELD(10, 11); //!< Reserved - Intra Row Store 8774 uint32_t IntraRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12); //!< INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 8775 uint32_t Reserved493 : __CODEGEN_BITFIELD(13, 31); //!< Reserved 8776 }; 8777 uint32_t Value; 8778 } DW15; 8779 union 8780 { 8781 struct 8782 { 8783 uint32_t Reserved512 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8784 uint32_t DeblockingFilterRowStoreScratchBaseAddress : __CODEGEN_BITFIELD(6, 31); //!< Deblocking Filter Row Store Scratch Base Address 8785 }; 8786 uint32_t Value; 8787 } DW16; 8788 union 8789 { 8790 struct 8791 { 8792 uint32_t DeblockingFilterRowStoreScratchBaseAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< Deblocking Filter Row Store Scratch Base Address High 8793 uint32_t Reserved560 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8794 }; 8795 uint32_t Value; 8796 } DW17; 8797 union 8798 { 8799 struct 8800 { 8801 uint32_t DeblockingFilterRowStoreScratchMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Deblocking Filter Row Store Scratch - Memory Object Control State 8802 uint32_t DeblockingFilterRowStoreScratchArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL 8803 uint32_t DeblockingFilterRowStoreScratchCompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 9, 9); //!< Deblocking Filter Row Store Scratch - Compression Accumulation Buffer Enable 8804 uint32_t DeblockingFilterRowStoreScratchMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10); //!< Deblocking Filter Row Store Scratch - Memory Compression Mode 8805 uint32_t Reserved587 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 8806 uint32_t DeblockingFilterRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12); //!< DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 8807 uint32_t Reserved589 : __CODEGEN_BITFIELD(13, 31); //!< Reserved 8808 }; 8809 uint32_t Value; 8810 } DW18; 8811 8812 SPLITBASEADDRESS64BYTEALIGNED_CMD Refpicbaseaddr[16]; //!< RefPicBaseAddr 8813 8814 union 8815 { 8816 struct 8817 { 8818 uint32_t ReferncePictureMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Refernce Picture - Memory Object Control State 8819 uint32_t ReferencePictureArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL 8820 uint32_t Reserved1641 : __CODEGEN_BITFIELD(9, 31); //!< Reserved 8821 }; 8822 uint32_t Value; 8823 } DW51; 8824 union 8825 { 8826 struct 8827 { 8828 uint32_t Reserved1664 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8829 uint32_t MacroblockBufferBaseAddressOrDecodedPictureErrorStatusBufferBaseAddress : __CODEGEN_BITFIELD(6, 31); //!< Macroblock Buffer Base Address or Decoded Picture Error/Status Buffer Base Address 8830 }; 8831 uint32_t Value; 8832 } DW52; 8833 union 8834 { 8835 struct 8836 { 8837 uint32_t MacroblockBufferBaseAddressOrDecodedPictureErrorStatusBufferBaseAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< Macroblock Buffer Base Address or Decoded Picture Error/Status Buffer Base Address High 8838 uint32_t Reserved1712 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8839 }; 8840 uint32_t Value; 8841 } DW53; 8842 union 8843 { 8844 struct 8845 { 8846 uint32_t MacroblockStatusBufferMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Macroblock Status Buffer - Memory Object Control State 8847 uint32_t MacroblockStatusBufferArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL 8848 uint32_t MacroblockStatusBufferCompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 9, 9); //!< Macroblock Status Buffer - Compression Accumulation Buffer Enable 8849 uint32_t MacroblockStatusBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10); //!< Macroblock Status Buffer - Memory Compression Mode 8850 uint32_t Reserved1739 : __CODEGEN_BITFIELD(11, 31); //!< Reserved 8851 }; 8852 uint32_t Value; 8853 } DW54; 8854 union 8855 { 8856 struct 8857 { 8858 uint32_t Reserved1760 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8859 uint32_t MacroblockIldbStreamoutBufferBaseAddress : __CODEGEN_BITFIELD(6, 31); //!< Macroblock ILDB StreamOut Buffer Base Address 8860 }; 8861 uint32_t Value; 8862 } DW55; 8863 union 8864 { 8865 struct 8866 { 8867 uint32_t MacroblockIldbStreamoutBufferBaseAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< Macroblock ILDB StreamOut Buffer Base Address High 8868 uint32_t Reserved1808 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8869 }; 8870 uint32_t Value; 8871 } DW56; 8872 union 8873 { 8874 struct 8875 { 8876 uint32_t MacroblockIldbStreamoutBufferMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Macroblock ILDB StreamOut Buffer - Memory Object Control State 8877 uint32_t MacroblockIldbStreamoutBufferArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL 8878 uint32_t MacroblockIldbStreamoutBufferCompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 9, 9); //!< Macroblock ILDB StreamOut Buffer - Compression Accumulation Buffer Enable 8879 uint32_t MacroblockIldbStreamoutBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10); //!< Macroblock ILDB StreamOut Buffer - Memory Compression Mode 8880 uint32_t Reserved1835 : __CODEGEN_BITFIELD(11, 31); //!< Reserved 8881 }; 8882 uint32_t Value; 8883 } DW57; 8884 union 8885 { 8886 struct 8887 { 8888 uint32_t Reserved1856 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8889 uint32_t SecondMacroblockIldbStreamoutBufferBaseAddress : __CODEGEN_BITFIELD(6, 31); //!< Second Macroblock ILDB StreamOut Buffer Base Address 8890 }; 8891 uint32_t Value; 8892 } DW58; 8893 union 8894 { 8895 struct 8896 { 8897 uint32_t SecondMacroblockIldbStreamoutBufferBaseAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< Second Macroblock ILDB StreamOut Buffer Base Address High 8898 uint32_t Reserved1904 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8899 }; 8900 uint32_t Value; 8901 } DW59; 8902 union 8903 { 8904 struct 8905 { 8906 uint32_t SecondMacroblockIldbStreamoutBufferMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Second Macroblock ILDB StreamOut Buffer - Memory Object Control State 8907 uint32_t SecondMacroblockIldbStreamoutBufferArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< Second Macroblock ILDB StreamOut Buffer - Arbitration Priority Control 8908 uint32_t SecondMacroblockIldbStreamoutBufferCompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 9, 9); //!< Second Macroblock ILDB StreamOut Buffer - Compression Accumulation Buffer Enable 8909 uint32_t SecondMacroblockIldbStreamoutBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10); //!< Second Macroblock ILDB StreamOut Buffer - Memory Compression Mode 8910 uint32_t Reserved1931 : __CODEGEN_BITFIELD(11, 31); //!< Reserved 8911 }; 8912 uint32_t Value; 8913 } DW60; 8914 union 8915 { 8916 struct 8917 { 8918 uint32_t ReferencePicture0CompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 0, 0); //!< Reference Picture 0 - Compression Accumulation Buffer Enable 8919 uint32_t Reserved1953 : __CODEGEN_BITFIELD( 1, 1); //!< Reserved 8920 uint32_t ReferencePicture1CompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 2, 2); //!< Reference Picture 1 - Compression Accumulation Buffer Enable 8921 uint32_t Reserved1955 : __CODEGEN_BITFIELD( 3, 3); //!< Reserved 8922 uint32_t ReferencePicture2CompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 4, 4); //!< Reference Picture 2 - Compression Accumulation Buffer Enable 8923 uint32_t Reserved1957 : __CODEGEN_BITFIELD( 5, 5); //!< Reserved 8924 uint32_t ReferencePicture3CompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 6, 6); //!< Reference Picture 3 - Compression Accumulation Buffer Enable 8925 uint32_t Reserved1959 : __CODEGEN_BITFIELD( 7, 7); //!< Reserved 8926 uint32_t ReferencePicture4CompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 8, 8); //!< Reference Picture 4 - Compression Accumulation Buffer Enable 8927 uint32_t Reserved1961 : __CODEGEN_BITFIELD( 9, 9); //!< Reserved 8928 uint32_t ReferencePicture5CompressionAccumulationBufferEnable : __CODEGEN_BITFIELD(10, 10); //!< Reference Picture 5 - Compression Accumulation Buffer Enable 8929 uint32_t Reserved1963 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 8930 uint32_t ReferencePicture6CompressionAccumulationBufferEnable : __CODEGEN_BITFIELD(12, 12); //!< Reference Picture 6 - Compression Accumulation Buffer Enable 8931 uint32_t Reserved1965 : __CODEGEN_BITFIELD(13, 13); //!< Reserved 8932 uint32_t ReferencePicture7CompressionAccumulationBufferEnable : __CODEGEN_BITFIELD(14, 14); //!< Reference Picture 7 - Compression Accumulation Buffer Enable 8933 uint32_t Reserved1967 : __CODEGEN_BITFIELD(15, 15); //!< Reserved 8934 uint32_t ReferencePicture8CompressionAccumulationBufferEnable : __CODEGEN_BITFIELD(16, 16); //!< Reference Picture 8 - Compression Accumulation Buffer Enable 8935 uint32_t Reserved1969 : __CODEGEN_BITFIELD(17, 17); //!< Reserved 8936 uint32_t ReferencePicture9CompressionAccumulationBufferEnable : __CODEGEN_BITFIELD(18, 18); //!< Reference Picture 9 - Compression Accumulation Buffer Enable 8937 uint32_t Reserved1971 : __CODEGEN_BITFIELD(19, 19); //!< Reserved 8938 uint32_t ReferencePicture10CompressionAccumulationBufferEnable : __CODEGEN_BITFIELD(20, 20); //!< Reference Picture 10 - Compression Accumulation Buffer Enable 8939 uint32_t Reserved1973 : __CODEGEN_BITFIELD(21, 21); //!< Reserved 8940 uint32_t ReferencePicture11CompressionAccumulationEnable : __CODEGEN_BITFIELD(22, 22); //!< Reference Picture 11 - Compression Accumulation Enable 8941 uint32_t Reserved1975 : __CODEGEN_BITFIELD(23, 23); //!< Reserved 8942 uint32_t ReferencePicture12CompressionAccumulationBufferEnable : __CODEGEN_BITFIELD(24, 24); //!< Reference Picture 12 - Compression Accumulation Buffer Enable 8943 uint32_t Reserved1977 : __CODEGEN_BITFIELD(25, 25); //!< Reserved 8944 uint32_t ReferencePicture13CompressionAccumulationBufferEnable : __CODEGEN_BITFIELD(26, 26); //!< Reference Picture 13 - Compression Accumulation Buffer Enable 8945 uint32_t Reserved1979 : __CODEGEN_BITFIELD(27, 27); //!< Reserved 8946 uint32_t ReferencePicture14CompressionAccumulationBufferEnable : __CODEGEN_BITFIELD(28, 28); //!< Reference Picture 14 - Compression Accumulation Buffer Enable 8947 uint32_t Reserved1981 : __CODEGEN_BITFIELD(29, 29); //!< Reserved 8948 uint32_t ReferencePicture15CompressionAccumulationBufferEnable : __CODEGEN_BITFIELD(30, 30); //!< Reference Picture 15 - Compression Accumulation Buffer Enable 8949 uint32_t Reserved1983 : __CODEGEN_BITFIELD(31, 31); //!< Reserved 8950 }; 8951 uint32_t Value; 8952 } DW61; 8953 union 8954 { 8955 struct 8956 { 8957 uint32_t Reserved1984 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8958 uint32_t ScaledReferenceSurfaceBaseAddress : __CODEGEN_BITFIELD(6, 31); //!< Scaled Reference Surface Base Address 8959 }; 8960 uint32_t Value; 8961 } DW62; 8962 union 8963 { 8964 struct 8965 { 8966 uint32_t ScaledReferenceSurfaceBaseAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< Scaled Reference Surface Base Address High 8967 uint32_t Reserved2032 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8968 }; 8969 uint32_t Value; 8970 } DW63; 8971 union 8972 { 8973 struct 8974 { 8975 uint32_t ScaledReferenceSurfaceMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Scaled Reference Surface - Memory Object Control State 8976 uint32_t ScaleReferenceSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL 8977 uint32_t ScaledReferenceSurfaceMemoryCompressionEnable : __CODEGEN_BITFIELD(9, 9); //!< Scaled Reference Surface - Memory Compression Enable 8978 uint32_t ScaledReferenceSurfaceRenderCompressionEnable : __CODEGEN_BITFIELD(10, 10); //!< SCALED_REFERENCE_SURFACE_RENDER_COMPRESSION_ENABLE 8979 uint32_t Reserved2059 : __CODEGEN_BITFIELD(11, 31); //!< Reserved 8980 }; 8981 uint32_t Value; 8982 } DW64; 8983 union 8984 { 8985 struct 8986 { 8987 uint32_t Reserved2080 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 8988 uint32_t SlicesizeStreamoutDataDestinationBaseAddress : __CODEGEN_BITFIELD(6, 31); //!< SliceSize StreamOut Data Destination Base Address 8989 }; 8990 uint32_t Value; 8991 } DW65; 8992 union 8993 { 8994 struct 8995 { 8996 uint32_t SlicesizeStreamoutDataDestinationBaseAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< SliceSize StreamOut Data Destination Base Address High 8997 uint32_t Reserved2128 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 8998 }; 8999 uint32_t Value; 9000 } DW66; 9001 union 9002 { 9003 struct 9004 { 9005 uint32_t SlicesizeStreamoutDataDestinationMemoryObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< SliceSize StreamOut Data Destination - Memory Object Control State 9006 uint32_t SlicesizeStreamoutDataDestinationArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL 9007 uint32_t SlicesizeStreamoutDataDestinationMemoryCompressionEnable : __CODEGEN_BITFIELD(9, 9); //!< SliceSize StreamOut Data Destination - Memory Compression Enable 9008 uint32_t SlicesizeStreamoutDataDestinationMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10); //!< SliceSize StreamOut Data Destination - Memory Compression Mode 9009 uint32_t Reserved2155 : __CODEGEN_BITFIELD(11, 31); //!< Reserved 9010 }; 9011 uint32_t Value; 9012 } DW67; 9013 9014 //! \name Local enumerations 9015 9016 enum SUBOPCODE_B 9017 { 9018 SUBOPCODE_B_UNNAMED2 = 2, //!< No additional details 9019 }; 9020 9021 enum SUBOPCODE_A 9022 { 9023 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 9024 }; 9025 9026 enum COMMON_OPCODE 9027 { 9028 COMMON_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 9029 }; 9030 9031 enum PIPELINE 9032 { 9033 PIPELINE_MFXPIPEBUFADDRSTATE = 2, //!< No additional details 9034 }; 9035 9036 enum COMMAND_TYPE 9037 { 9038 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 9039 }; 9040 9041 //! \brief PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL 9042 //! \details 9043 //! This field controls the priority of arbitration used in the GAC/GAM 9044 //! pipeline for this surface. 9045 enum PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL 9046 { 9047 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9048 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9049 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9050 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9051 }; 9052 9053 //! \brief POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL 9054 //! \details 9055 //! This field controls the priority of arbitration used in the GAC/GAM 9056 //! pipeline for this surface. 9057 enum POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL 9058 { 9059 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9060 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9061 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9062 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9063 }; 9064 9065 //! \brief ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL 9066 //! \details 9067 //! This field controls the priority of arbitration used in the GAC/GAM 9068 //! pipeline for this surface. 9069 enum ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL 9070 { 9071 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9072 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9073 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9074 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9075 }; 9076 9077 //! \brief STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL 9078 //! \details 9079 //! This field controls the priority of arbitration used in the GAC/GAM 9080 //! pipeline for this surface. 9081 enum STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL 9082 { 9083 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9084 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9085 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9086 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9087 }; 9088 9089 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL 9090 //! \details 9091 //! This field controls the priority of arbitration used in the GAC/GAM 9092 //! pipeline for this surface. 9093 enum INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL 9094 { 9095 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9096 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9097 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9098 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9099 }; 9100 9101 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 9102 //! \details 9103 //! This field controls if Intra Row Store is going to store inside Media 9104 //! Cache or to LLC. 9105 enum INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 9106 { 9107 INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 9108 INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage 9109 }; 9110 9111 //! \brief DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL 9112 //! \details 9113 //! This field controls the priority of arbitration used in the GAC/GAM 9114 //! pipeline for this surface. 9115 enum DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL 9116 { 9117 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9118 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9119 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9120 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9121 }; 9122 9123 //! \brief DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 9124 //! \details 9125 //! This field controls if Intra Row Store is going to store inside Media 9126 //! Internal Storage or to LLC. 9127 enum DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 9128 { 9129 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC 9130 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Media Internal Storage 9131 }; 9132 9133 //! \brief REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL 9134 //! \details 9135 //! This field controls the priority of arbitration used in the GAC/GAM 9136 //! pipeline for this surface. 9137 enum REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL 9138 { 9139 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9140 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9141 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9142 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9143 }; 9144 9145 //! \brief MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL 9146 //! \details 9147 //! This field controls the priority of arbitration used in the GAC/GAM 9148 //! pipeline for this surface. 9149 enum MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL 9150 { 9151 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9152 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9153 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9154 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9155 }; 9156 9157 //! \brief MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL 9158 //! \details 9159 //! This field controls the priority of arbitration used in the GAC/GAM 9160 //! pipeline for this surface. 9161 enum MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL 9162 { 9163 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9164 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9165 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9166 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9167 }; 9168 9169 //! \brief SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL 9170 //! \details 9171 //! This field controls the priority of arbitration used in the GAC/GAM 9172 //! pipeline for this surface. 9173 enum SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL 9174 { 9175 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9176 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9177 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9178 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9179 }; 9180 9181 enum SCALED_REFERENCE_SURFACE_RENDER_COMPRESSION_ENABLE 9182 { 9183 SCALED_REFERENCE_SURFACE_RENDER_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 9184 SCALED_REFERENCE_SURFACE_RENDER_COMPRESSION_ENABLE_ENABLE = 1, //!< No additional details 9185 }; 9186 9187 //! \brief SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL 9188 //! \details 9189 //! This field controls the priority of arbitration used in the GAC/GAM 9190 //! pipeline for this surface. 9191 enum SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL 9192 { 9193 SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9194 SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9195 SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9196 SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9197 }; 9198 9199 //! \name Initializations 9200 9201 //! \brief Explicit member initialization function 9202 MFX_PIPE_BUF_ADDR_STATE_CMD(); 9203 9204 static const size_t dwSize = 68; 9205 static const size_t byteSize = 272; 9206 }; 9207 9208 //! 9209 //! \brief MFX_AVC_DIRECTMODE_STATE 9210 //! \details 9211 //! This is a picture level command and is issued once per picture. All DMV 9212 //! buffers are treated as standard media surfaces, in which the lower 6 9213 //! bits are used for conveying surface states.Current Pic POC number is 9214 //! assumed to be available in POCList[32 and 33] of the 9215 //! MFX_AVC_DIRECTMODE_STATE Command.This command is only valid in the AVC 9216 //! decoding in VLD and IT modes, and AVC encoder mode. The same command 9217 //! supports both Long and Short AVC Interface. The DMV buffers are not 9218 //! required to be programmed for encoder mode. 9219 //! 9220 struct MFX_AVC_DIRECTMODE_STATE_CMD 9221 { 9222 union 9223 { 9224 struct 9225 { 9226 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 9227 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 9228 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20); //!< SUBOPCODEB 9229 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23); //!< SUBOPCODEA 9230 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< MEDIA_COMMAND_OPCODE 9231 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE 9232 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 9233 }; 9234 uint32_t Value; 9235 } DW0; 9236 SPLITBASEADDRESS64BYTEALIGNED_CMD DirectMvBufferBaseAddress[16]; //!< DW1..32, Direct MV Buffer for Reference Frame 0 to 15 - Base Address 9237 MEMORYADDRESSATTRIBUTES_CMD DirectMvBufferAttributes; //!< DW33, Direct MV Buffer for Reference Frame 0 to 15 - Attributes 9238 SPLITBASEADDRESS64BYTEALIGNED_CMD DirectMvBufferForWriteBaseAddress; //!< DW34..35, Direct MV Buffer for Write - Base Address 9239 MEMORYADDRESSATTRIBUTES_CMD DirectMvBufferForWriteAttributes; //!< DW36, Direct MV Buffer for Write - Attributes 9240 uint32_t PocList[34]; //!< POCList[34][31:0] 9241 9242 //! \name Local enumerations 9243 9244 enum SUBOPCODEB 9245 { 9246 SUBOPCODEB_UNNAMED2 = 2, //!< No additional details 9247 }; 9248 9249 enum SUBOPCODEA 9250 { 9251 SUBOPCODEA_UNNAMED0 = 0, //!< No additional details 9252 }; 9253 9254 enum MEDIA_COMMAND_OPCODE 9255 { 9256 MEDIA_COMMAND_OPCODE_AVCCOMMON = 1, //!< No additional details 9257 }; 9258 9259 enum PIPELINE 9260 { 9261 PIPELINE_MFXSINGLEDW = 2, //!< No additional details 9262 }; 9263 9264 enum COMMAND_TYPE 9265 { 9266 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 9267 }; 9268 9269 //! \name Initializations 9270 9271 //! \brief Explicit member initialization function 9272 MFX_AVC_DIRECTMODE_STATE_CMD(); 9273 9274 static const size_t dwSize = 71; 9275 static const size_t byteSize = 284; 9276 }; 9277 MEDIA_CLASS_DEFINE_END(mhw__vdbox__mfx__xe_lpm_plus_base__v1__Cmd) 9278 }; 9279 } // namespace v1 9280 } // namespace xe_lpm_plus_base 9281 } // namespace mfx 9282 } // namespace vdbox 9283 } // namespace mhw 9284 9285 #pragma pack() 9286 9287 #endif // __MHW_VDBOX_MFX_HWCMD_XE2_HPM_H__ 9288