1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef _SOC_APOLLOLAKE_IOMAP_H_ 4 #define _SOC_APOLLOLAKE_IOMAP_H_ 5 6 #include <commonlib/helpers.h> 7 8 #define P2SB_BAR CONFIG_PCR_BASE_ADDRESS 9 #define P2SB_SIZE (16 * MiB) 10 #define MCH_BASE_ADDRESS 0xfed10000 11 #define MCH_BASE_SIZE (32 * KiB) 12 13 #define ACPI_BASE_ADDRESS 0x400 14 #define ACPI_BASE_SIZE 0x100 15 #define R_ACPI_PM1_TMR 0x8 16 17 #define TCO_BASE_ADDRESS (ACPI_BASE_ADDRESS + 0x60) 18 #define TCO_BASE_SIZE 0x20 19 20 /* CST Range (R/W) IO port block size */ 21 #define PMG_IO_BASE_CST_RNG_BLK_SIZE 0x5 22 /* ACPI PMIO Offset to C-state register*/ 23 #define ACPI_PMIO_CST_REG (ACPI_BASE_ADDRESS + 0x14) 24 25 /* Accesses to these BARs are hardcoded in FSP */ 26 #define PCH_PWRM_BASE_ADDRESS 0xfe042000 27 #define PMC_BAR1 0xfe044000 28 #define PMC_BAR0_SIZE (8 * KiB) 29 30 #define SRAM_BASE_0 0xfe900000 31 #define SRAM_SIZE_0 (8 * KiB) 32 #define SRAM_BASE_2 0xfe902000 33 #define SRAM_SIZE_2 (4 * KiB) 34 #define SHARED_SRAM_BASE 0xfffe0000 35 #define SHARED_SRAM_SIZE (128 * KiB) 36 37 #define HECI1_BASE_ADDRESS 0xfed1a000 38 #define PSF3_BASE_ADDRESS 0x1e00 39 40 /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ 41 #define SPI_BASE_ADDRESS 0xfe010000 42 #define EARLY_GSPI_BASE_ADDRESS 0xfe011000 43 44 /* Temporary BAR for early I2C bus access */ 45 #define EARLY_I2C_BASE_ADDRESS 0xfe020000 46 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) 47 48 #endif /* _SOC_APOLLOLAKE_IOMAP_H_ */ 49