1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 /* 4 * This file is created based on MT8186 Functional Specification 5 * Chapter number: 3.7 6 */ 7 8 #ifndef __SOC_MEDIATEK_MT6366_H__ 9 #define __SOC_MEDIATEK_MT6366_H__ 10 11 #include <types.h> 12 13 enum { 14 PMIC_SWCID = 0x000a, 15 PMIC_VM_MODE = 0x004e, 16 PMIC_TOP_CKPDN_CON0_SET = 0x010e, 17 PMIC_TOP_CKPDN_CON0_CLR = 0x0110, 18 PMIC_TOP_CKHWEN_CON0_SET = 0x012c, 19 PMIC_TOP_CKHWEN_CON0_CLR = 0x012e, 20 PMIC_TOP_RST_MISC = 0x014c, 21 PMIC_TOP_RST_MISC_SET = 0x014e, 22 PMIC_TOP_RST_MISC_CLR = 0x0150, 23 PMIC_OTP_CON0 = 0x038a, 24 PMIC_OTP_CON8 = 0x039a, 25 PMIC_OTP_CON11 = 0x03a0, 26 PMIC_OTP_CON12 = 0x03a2, 27 PMIC_OTP_CON13 = 0x03a4, 28 PMIC_TOP_TMA_KEY = 0x03a8, 29 PMIC_PWRHOLD = 0x0a08, 30 PMIC_CPSDSA4 = 0x0a2e, 31 PMIC_VPROC12_OP_EN = 0x1410, 32 PMIC_VPROC12_DBG0 = 0x141e, 33 PMIC_VPROC12_VOSEL = 0x1426, 34 PMIC_VCORE_OP_EN = 0x1490, 35 PMIC_VCORE_DBG0 = 0x149e, 36 PMIC_VCORE_VOSEL = 0x14aa, 37 PMIC_VDRAM1_VOSEL_SLEEP = 0x160a, 38 PMIC_VDRAM1_OP_EN = 0x1610, 39 PMIC_VDRAM1_DBG0 = 0x161e, 40 PMIC_VDRAM1_VOSEL = 0x1626, 41 PMIC_SMPS_ANA_CON0 = 0x1808, 42 PMIC_LDO_VIO18_CON0 = 0x1aec, 43 PMIC_VDDQ_OP_EN = 0x1b16, 44 PMIC_VSRAM_PROC12_OP_EN = 0x1b90, 45 PMIC_VSRAM_PROC12_DBG0 = 0x1ba2, 46 PMIC_VSRAM_PROC12_VOSEL = 0x1bf0, 47 PMIC_LDO_VRF12_CON0 = 0x1c30, 48 PMIC_LDO_VRF12_OP_EN = 0x1c32, 49 PMIC_LDO_VMC_CON0 = 0x1cc4, 50 PMIC_LDO_VMC_OP_EN = 0x1cc6, 51 PMIC_LDO_VMCH_CON0 = 0x1cd8, 52 PMIC_LDO_VMCH_OP_EN = 0x1cda, 53 PMIC_LDO_VCN33_CON0_0 = 0x1d1c, 54 PMIC_VCN33_ANA_CON0 = 0x1e28, 55 PMIC_VSIM2_ANA_CON0 = 0x1e30, 56 PMIC_VMCH_ANA_CON0 = 0x1e48, 57 PMIC_VMC_ANA_CON0 = 0x1e4c, 58 PMIC_VDDQ_ELR_0 = 0x1ec4, 59 }; 60 61 enum mt6366_regulator_id { 62 MT6366_VCORE = 0, 63 MT6366_VDRAM1, 64 MT6366_VDDQ, 65 MT6366_VMCH, 66 MT6366_VMC, 67 MT6366_VPROC12, 68 MT6366_VSRAM_PROC12, 69 MT6366_VRF12, 70 MT6366_VCN33, 71 MT6366_VIO18, 72 MT6366_REGULATOR_NUM, 73 }; 74 75 struct pmic_setting { 76 unsigned short addr; 77 unsigned short val; 78 unsigned short mask; 79 unsigned char shift; 80 }; 81 82 void mt6366_init(void); 83 void mt6366_set_power_hold(bool enable); 84 void mt6366_set_vsim2_cali_mv(u32 vsim2_mv); 85 void mt6366_init_scp_voltage(void); 86 void mt6366_set_voltage(enum mt6366_regulator_id id, u32 vcore_uv); 87 u32 mt6366_get_voltage(enum mt6366_regulator_id id); 88 89 #endif /* __SOC_MEDIATEK_MT6366_H__ */ 90