1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_MT8173_MT6391_H__ 4 #define __SOC_MEDIATEK_MT8173_MT6391_H__ 5 6 #include <types.h> 7 8 /* 9 * PMIC definition 10 */ 11 enum { 12 PMIC6391_E1_CID_CODE = 0x1091, 13 PMIC6391_E2_CID_CODE = 0x2091, 14 PMIC6397_E1_CID_CODE = 0x1097, 15 PMIC6397_E2_CID_CODE = 0x2097, 16 PMIC6397_E3_CID_CODE = 0x3097, 17 PMIC6397_E4_CID_CODE = 0x4097 18 }; 19 20 /* 21 * PMIC Register Index 22 */ 23 24 /* PCHR Register Definition */ 25 enum { 26 PMIC_RG_CHR_CON1 = 0x0002, 27 PMIC_RG_CHR_CON6 = 0x000C, 28 PMIC_RG_CHR_CON13 = 0x001A, 29 PMIC_RG_CHR_CON18 = 0x0024, 30 PMIC_RG_CHR_CON21 = 0x002A, 31 PMIC_RG_CHR_CON23 = 0x002E, 32 }; 33 34 /* TOP Register Definition */ 35 enum{ 36 PMIC_RG_CID = 0x0100, 37 PMIC_RG_TOP_CKPDN = 0x0102, 38 PMIC_RG_TOP_CKPDN2 = 0x0108, 39 PMIC_RG_TOP_RST_CON = 0x0114, 40 PMIC_RG_WRP_CKPDN = 0x011A, 41 PMIC_RG_TOP_RST_MISC = 0x0126, 42 PMIC_RG_TOP_CKCON1 = 0x0128, 43 PMIC_RG_TOP_CKCON2 = 0x012A, 44 PMIC_RG_TOP_CKTST1 = 0x012C, 45 PMIC_RG_TOP_CKTST2 = 0x012E, 46 PMIC_RG_OC_DEG_EN = 0x0130, 47 PMIC_RG_OC_CTL1 = 0x0134, 48 PMIC_RG_CHRSTATUS = 0x0144, 49 PMIC_RG_OCSTATUS0 = 0x0146, 50 PMIC_RG_OCSTATUS1 = 0x0148, 51 PMIC_RG_OCSTATUS2 = 0x014A, 52 PMIC_RG_TOP_CKPDN3 = 0x01CE, 53 PMIC_RG_TOP_CKCON3 = 0x01D4 54 }; 55 56 /* INT Register Definition */ 57 enum{ 58 PMIC_RG_INT_CON0 = 0x0178, 59 PMIC_RG_INT_CON1 = 0x017E, 60 }; 61 62 /* FQMTR Register Definition */ 63 enum{ 64 PMIC_RG_FQMTR_CON0 = 0x0188, 65 PMIC_RG_FQMTR_CON1 = 0x018A, 66 PMIC_RG_FQMTR_CON2 = 0x018C 67 }; 68 69 /* EFUSE Register Definition */ 70 enum{ 71 PMIC_RG_EFUSE_DOUT_256_271 = 0x01EE, 72 PMIC_RG_EFUSE_DOUT_272_287 = 0x01F0, 73 PMIC_RG_EFUSE_DOUT_288_303 = 0x01F2, 74 PMIC_RG_EFUSE_DOUT_304_319 = 0x01F4 75 }; 76 77 /* BUCK Register Definition */ 78 enum{ 79 PMIC_RG_BUCK_CON3 = 0x0206, 80 PMIC_RG_BUCK_CON8 = 0x0210, 81 PMIC_RG_VCA15_CON1 = 0x0216, 82 PMIC_RG_VCA15_CON5 = 0x021E, 83 PMIC_RG_VCA15_CON7 = 0x0222, 84 PMIC_RG_VCA15_CON8 = 0x0224, 85 PMIC_RG_VCA15_CON9 = 0x0226, 86 PMIC_RG_VCA15_CON10 = 0x0228, 87 PMIC_RG_VCA15_CON11 = 0x022A, 88 PMIC_RG_VCA15_CON12 = 0x022C, 89 PMIC_RG_VCA15_CON18 = 0x0238, 90 PMIC_RG_VSRMCA15_CON5 = 0x0244, 91 PMIC_RG_VSRMCA15_CON6 = 0x0246, 92 PMIC_RG_VSRMCA15_CON7 = 0x0248, 93 PMIC_RG_VSRMCA15_CON8 = 0x024A, 94 PMIC_RG_VSRMCA15_CON9 = 0x024C, 95 PMIC_RG_VSRMCA15_CON10 = 0x024E, 96 PMIC_RG_VSRMCA15_CON11 = 0x0250, 97 PMIC_RG_VSRMCA15_CON18 = 0x025E, 98 PMIC_RG_VSRMCA15_CON19 = 0x0260, 99 PMIC_RG_VSRMCA15_CON20 = 0x0262, 100 PMIC_RG_VSRMCA15_CON21 = 0x0264, 101 PMIC_RG_VCORE_CON5 = 0x0270, 102 PMIC_RG_VCORE_CON6 = 0x0272, 103 PMIC_RG_VCORE_CON8 = 0x0276, 104 PMIC_RG_VCORE_CON9 = 0x0278, 105 PMIC_RG_VCORE_CON10 = 0x027A, 106 PMIC_RG_VCORE_CON11 = 0x027C, 107 PMIC_RG_VCORE_CON18 = 0x028A, 108 PMIC_RG_VGPU_CON1 = 0x028E, 109 PMIC_RG_VGPU_CON8 = 0x029C, 110 PMIC_RG_VGPU_CON18 = 0x02B0, 111 PMIC_RG_VIO18_CON18 = 0x0324, 112 PMIC_RG_VPCA7_CON5 = 0x0330, 113 PMIC_RG_VPCA7_CON6 = 0x0332, 114 PMIC_RG_VPCA7_CON7 = 0x0334, 115 PMIC_RG_VPCA7_CON8 = 0x0336, 116 PMIC_RG_VPCA7_CON9 = 0x0338, 117 PMIC_RG_VPCA7_CON10 = 0x033A, 118 PMIC_RG_VPCA7_CON11 = 0x033C, 119 PMIC_RG_VPCA7_CON18 = 0x034A, 120 PMIC_RG_VSRMCA7_CON5 = 0x0356, 121 PMIC_RG_VSRMCA7_CON6 = 0x0358, 122 PMIC_RG_VSRMCA7_CON8 = 0x035C, 123 PMIC_RG_VSRMCA7_CON9 = 0x035E, 124 PMIC_RG_VSRMCA7_CON10 = 0x0360, 125 PMIC_RG_VSRMCA7_CON11 = 0x0362, 126 PMIC_RG_VSRMCA7_CON18 = 0x0370, 127 PMIC_RG_VSRMCA7_CON19 = 0x0372, 128 PMIC_RG_VSRMCA7_CON20 = 0x0374, 129 PMIC_RG_VSRMCA7_CON21 = 0x0376, 130 PMIC_RG_VDRM_CON9 = 0x038A, 131 PMIC_RG_VDRM_CON10 = 0x038C, 132 PMIC_RG_VDRM_CON18 = 0x039C, 133 PMIC_RG_BUCK_K_CON0 = 0x039E 134 }; 135 136 /* ANALDO Register Definition */ 137 enum{ 138 PMIC_RG_ANALDO_CON0 = 0x0400, 139 PMIC_RG_ANALDO_CON2 = 0x0404, 140 PMIC_RG_ANALDO_CON6 = 0x040C, 141 }; 142 143 /* DIGLDO Register Definition */ 144 enum{ 145 PMIC_RG_DIGLDO_CON5 = 0x041A, 146 PMIC_RG_DIGLDO_CON6 = 0x041C, 147 PMIC_RG_DIGLDO_CON8 = 0x0420, 148 PMIC_RG_DIGLDO_CON10 = 0x0424, 149 PMIC_RG_DIGLDO_CON19 = 0x0436, 150 PMIC_RG_DIGLDO_CON20 = 0x0438, 151 PMIC_RG_DIGLDO_CON22 = 0x043C, 152 PMIC_RG_DIGLDO_CON24 = 0x0440, 153 PMIC_RG_DIGLDO_CON27 = 0x0446, 154 PMIC_RG_DIGLDO_CON30 = 0x044C, 155 PMIC_RG_DIGLDO_CON33 = 0x045A 156 }; 157 158 /* STRUP Register Definition */ 159 enum{ 160 PMIC_RG_STRUP_CON0 = 0x0500, 161 PMIC_RG_STRUP_CON2 = 0x0502, 162 PMIC_RG_STRUP_CON5 = 0x0508, 163 PMIC_RG_STRUP_CON7 = 0x050C, 164 PMIC_RG_STRUP_CON10 = 0x0512 165 }; 166 167 /* AUXADC Register Definition */ 168 enum{ 169 PMIC_RG_AUXADC_CON14 = 0x055E 170 }; 171 172 /* Driver Register Definition */ 173 enum{ 174 PMIC_RG_FLASH_CON0 = 0x0560, 175 PMIC_RG_KPLED_CON0 = 0x0566 176 }; 177 178 /* SPK Register Definition */ 179 enum{ 180 PMIC_RG_SPK_CON0 = 0x0600, 181 PMIC_RG_SPK_CON2 = 0x0604, 182 PMIC_RG_SPK_CON3 = 0x0606, 183 PMIC_RG_SPK_CON5 = 0x060A, 184 PMIC_RG_SPK_CON9 = 0x0612 185 }; 186 187 /* FGADC Register Definition */ 188 enum{ 189 PMIC_RG_FGADC_CON13 = 0x0632, 190 PMIC_RG_FGADC_CON16 = 0x0638, 191 PMIC_RG_FGADC_CON17 = 0x063A, 192 PMIC_RG_FGADC_CON18 = 0x063C 193 }; 194 195 /* AUDDAC Register Definition */ 196 enum{ 197 PMIC_RG_AUDLDO_CFG0 = 0x0714, 198 PMIC_RG_AUD_NCP0 = 0x071A 199 }; 200 201 /* DCXO Register Definition */ 202 enum{ 203 PMIC_RG_PMIC_RG_RG_DCXO_CON0 = 0x83a, 204 PMIC_RG_DCXO_CON2 = 0x83e, 205 PMIC_RG_DCXO_MANUAL_CON1 = 0x844, 206 PMIC_RG_DCXO_ANALOG_CON1 = 0x84a, 207 PMIC_RG_DCXO_FORCE_MODE1 = 0x854, 208 PMIC_RG_DCXO_POR2_CON3 = 0x85c 209 }; 210 211 /* TOP MASK and SHIFT Definition */ 212 enum{ 213 PMIC_RG_FQMTR_PDN_SHIFT = 1, 214 PMIC_RG_AP_RST_DIS_MASK = 0x1, 215 PMIC_RG_AP_RST_DIS_SHIFT = 0, 216 PMIC_RG_RST_PART_SEL_MASK = 0x1, 217 PMIC_RG_RST_PART_SEL_SHIFT = 4, 218 PMIC_RG_TOP_RST_MISC_RSV_3_MASK = 0x1, 219 PMIC_RG_TOP_RST_MISC_RSV_3_SHIFT = 3, 220 PMIC_RG_STRUP_MAN_RST_EN_MASK = 0x1, 221 PMIC_RG_STRUP_MAN_RST_EN_SHIFT = 2, 222 PMIC_RG_SYSRSTB_EN_MASK = 0x1, 223 PMIC_RG_SYSRSTB_EN_SHIFT = 1, 224 PMIC_RG_PWRKEY_DEB_MASK = 0x1, 225 PMIC_RG_PWRKEY_DEB_SHIFT = 3, 226 PMIC_RG_HOMEKEY_DEB_MASK = 0x1, 227 PMIC_RG_HOMEKEY_DEB_SHIFT = 4 228 }; 229 230 /* ANALDO MASK and SHIFT Definition */ 231 enum{ 232 PMIC_RG_VCAMA_VOSEL_MASK = 0x3, 233 PMIC_RG_VCAMA_VOSEL_SHIFT = 6, 234 PMIC_RG_VCAMA_EN_MASK = 0x1, 235 PMIC_RG_VCAMA_EN_SHIFT = 15, 236 }; 237 238 /* DCXO MASK and SHIFT Definition */ 239 enum{ 240 PMIC_RG_DCXO_C2_UNTRIM_MASK = 0x1, 241 PMIC_RG_DCXO_C2_UNTRIM_SHIFT = 15, 242 PMIC_RG_DCXO_MANUAL_C1C2_SYNC_EN_MASK = 0x1, 243 PMIC_RG_DCXO_MANUAL_C1C2_SYNC_EN_SHIFT = 9, 244 PMIC_RG_DCXO_MANUAL_SYNC_EN_MASK = 0x1, 245 PMIC_RG_DCXO_MANUAL_SYNC_EN_SHIFT = 8, 246 PMIC_RG_DCXO_ATTEN_BB_MASK = 0x3, 247 PMIC_RG_DCXO_ATTEN_BB_SHIFT = 11, 248 PMIC_RG_DCXO_LDO_BB_V_MASK = 0x3, 249 PMIC_RG_DCXO_LDO_BB_V_SHIFT = 2 250 }; 251 252 enum ldo_power { 253 LDO_VCAMD = 0, /* VGP1 */ 254 LDO_VGP2 = 1, /* VGP2 */ 255 LDO_VCAMAF = 2, /* VGP3 */ 256 LDO_VGP4 = 3, 257 LDO_VGP5 = 4, 258 LDO_VGP6 = 5, 259 /* special, not part of main register set */ 260 LDO_VCAMA = 6, 261 }; 262 263 enum ldo_voltage { 264 LDO_1P2 = 0, 265 LDO_1P3 = 1, 266 LDO_1P5 = 2, 267 LDO_1P8 = 3, 268 LDO_2P5 = 4, 269 LDO_2P8 = 5, 270 LDO_3P0 = 6, 271 LDO_3P3 = 7, 272 LDO_NUM_VOLTAGES, 273 274 LDO_1P22, /* only VCAMD */ 275 LDO_1P0, /* only VCAMIO */ 276 LDO_2P0, /* only VGP5 */ 277 }; 278 279 /* 280 * PMIC Exported Function 281 */ 282 int mt6391_configure_ca53_voltage(int uv); 283 void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel); 284 void mt6391_enable_reset_when_ap_resets(void); 285 void mt6391_init(void); 286 287 /* 288 * PMIC GPIO REGISTER DEFINITION 289 */ 290 enum { 291 MT6391_GPIO_DIR_BASE = 0xC000, 292 MT6391_GPIO_PULLEN_BASE = 0xC020, 293 MT6391_GPIO_PULLSEL_BASE = 0xC040, 294 MT6391_GPIO_DOUT_BASE = 0xC080, 295 MT6391_GPIO_DIN_BASE = 0xC0A0, 296 MT6391_GPIO_MODE_BASE = 0xC0C0, 297 }; 298 299 enum mt6391_pull_enable { 300 MT6391_GPIO_PULL_DISABLE = 0, 301 MT6391_GPIO_PULL_ENABLE = 1, 302 }; 303 304 enum mt6391_pull_select { 305 MT6391_GPIO_PULL_DOWN = 0, 306 MT6391_GPIO_PULL_UP = 1, 307 }; 308 309 enum { 310 MT6391_PMU_INT = 0, 311 MT6391_SRCVOLTEN = 1, 312 MT6391_SRCLKEN_PERI = 2, 313 MT6391_RTC32K_1V8 = 3, 314 MT6391_WRAP_EVENT = 4, 315 MT6391_SPI_CLK = 5, 316 MT6391_SPI_CSN = 6, 317 MT6391_SPI_MOSI = 7, 318 MT6391_SPI_MISO = 8, 319 MT6391_AUD_CLK_MOSI = 9, 320 MT6391_AUD_DAT_MISO = 10, 321 MT6391_AUD_DAT_MOSI = 11, 322 MT6391_KP_COL0 = 12, 323 MT6391_KP_COL1 = 13, 324 MT6391_KP_COL2 = 14, 325 MT6391_KP_COL3 = 15, 326 MT6391_KP_COL4 = 16, 327 MT6391_KP_COL5 = 17, 328 MT6391_KP_COL6 = 18, 329 MT6391_KP_COL7 = 19, 330 MT6391_KP_ROW0 = 20, 331 MT6391_KP_ROW1 = 21, 332 MT6391_KP_ROW2 = 22, 333 MT6391_KP_ROW3 = 23, 334 MT6391_KP_ROW4 = 24, 335 MT6391_KP_ROW5 = 25, 336 MT6391_KP_ROW6 = 26, 337 MT6391_KP_ROW7 = 27, 338 MT6391_VMSEL1 = 28, 339 MT6391_VMSEL2 = 29, 340 MT6391_PWM = 30, 341 MT6391_SCL0 = 31, 342 MT6391_SDA0 = 32, 343 MT6391_SCL1 = 33, 344 MT6391_SDA1 = 34, 345 MT6391_SCL2 = 35, 346 MT6391_SDA2 = 36, 347 MT6391_HDMISD = 37, 348 MT6391_HDMISCK = 38, 349 MT6391_HTPLG = 39, 350 MT6391_CEC = 40, 351 }; 352 353 /* 354 * PMIC GPIO Exported Function 355 */ 356 int mt6391_gpio_get(u32 gpio); 357 void mt6391_gpio_set(u32 gpio, int value); 358 void mt6391_gpio_input_pulldown(u32 gpio); 359 void mt6391_gpio_input_pullup(u32 gpio); 360 void mt6391_gpio_input(u32 gpio); 361 void mt6391_gpio_output(u32 gpio, int value); 362 void mt6391_gpio_set_pull(u32 gpio, enum mt6391_pull_enable enable, 363 enum mt6391_pull_select select); 364 void mt6391_gpio_set_mode(u32 gpio, int mode); 365 366 #endif /* __SOC_MEDIATEK_MT8173_MT6391_H__ */ 367