1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _TEGRA210_CLK_RST_H_ 4 #define _TEGRA210_CLK_RST_H_ 5 #include <stdint.h> 6 #include <stddef.h> 7 8 /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ 9 struct __packed clk_rst_ctlr { 10 u32 rst_src; /* _RST_SOURCE, 0x000 */ 11 u32 rst_dev_l; /* _RST_DEVICES_L, 0x004 */ 12 u32 rst_dev_h; /* _RST_DEVICES_H, 0x008 */ 13 u32 rst_dev_u; /* _RST_DEVICES_U, 0x00c */ 14 u32 clk_out_enb_l; /* _CLK_OUT_ENB_L, 0x010 */ 15 u32 clk_out_enb_h; /* _CLK_OUT_ENB_H, 0x014 */ 16 u32 clk_out_enb_u; /* _CLK_OUT_ENB_U, 0x018 */ 17 u32 _rsv0; /* 0x01c */ 18 u32 cclk_brst_pol; /* _CCLK_BURST_POLICY, 0x020 */ 19 u32 super_cclk_div; /* _SUPER_CCLK_DIVIDER, 0x024 */ 20 u32 sclk_brst_pol; /* _SCLK_BURST_POLICY, 0x028 */ 21 u32 super_sclk_div; /* _SUPER_SCLK_DIVIDER, 0x02C */ 22 u32 clk_sys_rate; /* _CLK_SYSTEM_RATE, 0x030 */ 23 u32 _rsv1[3]; /* 0x034-03c */ 24 u32 cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY, 0x040 */ 25 u32 clk_mask_arm; /* _CLK_MASK_ARM, 0x044 */ 26 u32 misc_clk_enb; /* _MISC_CLK_ENB, 0x048 */ 27 u32 clk_cpu_cmplx; /* _CLK_CPU_CMPLX, 0x04C */ 28 u32 osc_ctrl; /* _OSC_CTRL, 0x050 */ 29 u32 pll_lfsr; /* _PLL_LFSR, 0x054 */ 30 u32 osc_freq_det; /* _OSC_FREQ_DET, 0x058 */ 31 u32 osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS, 0x05C */ 32 u32 _rsv2[8]; /* 0x060-07C */ 33 u32 pllc_base; /* _PLLC_BASE, 0x080 */ 34 u32 pllc_out; /* _PLLC_OUT, 0x084 */ 35 u32 pllc_misc; /* _PLLC_MISC, 0x088 */ 36 u32 pllc_misc_1; /* _PLLC_MISC_1, 0x08c */ 37 u32 pllm_base; /* _PLLM_BASE, 0x090 */ 38 u32 pllm_out; /* _PLLM_OUT, 0x094 */ 39 u32 pllm_misc1; /* _PLLM_MISC1, 0x098 */ 40 u32 pllm_misc2; /* _PLLM_MISC2, 0x09c */ 41 u32 pllp_base; /* _PLLP_BASE, 0x0a0 */ 42 u32 pllp_outa; /* _PLLP_OUTA, 0x0a4 */ 43 u32 pllp_outb; /* _PLLP_OUTB, 0x0a8 */ 44 u32 pllp_misc; /* _PLLP_MISC, 0x0ac */ 45 u32 plla_base; /* _PLLA_BASE, 0x0b0 */ 46 u32 plla_out; /* _PLLA_OUT, 0x0b4 */ 47 u32 _rsv3; /* 0x0b8 */ 48 u32 plla_misc; /* _PLLA_MISC, 0x0bc */ 49 u32 pllu_base; /* _PLLU_BASE, 0x0c0 */ 50 u32 _rsv4[2]; /* 0x0c4-0c8 */ 51 u32 pllu_misc; /* _PLLU_MISC, 0x0cc */ 52 u32 plld_base; /* _PLLD_BASE, 0x0d0 */ 53 u32 _rsv5[1]; /* 0x0d4 */ 54 u32 plld_misc1; /* _PLLD_MISC1, 0x0d8 */ 55 u32 plld_misc; /* _PLLD_MISC, 0x0dc */ 56 u32 pllx_base; /* _PLLX_BASE, 0x0e0 */ 57 u32 pllx_misc; /* _PLLX_MISC, 0x0e4 */ 58 u32 plle_base; /* _PLLE_BASE, 0x0e8 */ 59 u32 plle_misc; /* _PLLE_MISC, 0x0ec */ 60 u32 plls_base; /* _PLLS_BASE, 0x0f0 */ 61 u32 plls_misc; /* _PLLS_MISC, 0x0f4 */ 62 u32 _rsv6[2]; /* 0x0f8-0fc */ 63 u32 clk_src_i2s1; /* _CLK_SOURCE_I2S1, 0x100 */ 64 u32 clk_src_i2s2; /* _CLK_SOURCE_I2S2, 0x104 */ 65 u32 clk_src_spdif_out; /* _CLK_SOURCE_SPDIF_OUT, 0x108 */ 66 u32 clk_src_spdif_in; /* _CLK_SOURCE_SPDIF_IN, 0x10c */ 67 u32 clk_src_pwm; /* _CLK_SOURCE_PWM, 0x110 */ 68 u32 _rsv7; /* 0x114 */ 69 u32 clk_src_sbc2; /* _CLK_SOURCE_SBC2, 0x118 */ 70 u32 clk_src_sbc3; /* _CLK_SOURCE_SBC3, 0x11c */ 71 u32 _rsv8; /* 0x120 */ 72 u32 clk_src_i2c1; /* _CLK_SOURCE_I2C1, 0x124 */ 73 u32 clk_src_i2c5; /* _CLK_SOURCE_I2C5, 0x128 */ 74 u32 _rsv9[2]; /* 0x12c-130 */ 75 u32 clk_src_sbc1; /* _CLK_SOURCE_SBC1, 0x134 */ 76 u32 clk_src_disp1; /* _CLK_SOURCE_DISP1, 0x138 */ 77 u32 clk_src_disp2; /* _CLK_SOURCE_DISP2, 0x13c */ 78 u32 _rsv10[2]; /* 0x140-144 */ 79 u32 clk_src_vi; /* _CLK_SOURCE_VI, 0x148 */ 80 u32 _rsv11; /* 0x14c */ 81 u32 clk_src_sdmmc1; /* _CLK_SOURCE_SDMMC1, 0x150 */ 82 u32 clk_src_sdmmc2; /* _CLK_SOURCE_SDMMC2, 0x154 */ 83 u32 clk_src_g3d; /* _CLK_SOURCE_G3D, 0x158 */ 84 u32 clk_src_g2d; /* _CLK_SOURCE_G2D, 0x15c */ 85 u32 clk_src_ndflash; /* _CLK_SOURCE_NDFLASH, 0x160 */ 86 u32 clk_src_sdmmc4; /* _CLK_SOURCE_SDMMC4, 0x164 */ 87 u32 clk_src_vfir; /* _CLK_SOURCE_VFIR, 0x168 */ 88 u32 clk_src_epp; /* _CLK_SOURCE_EPP, 0x16c */ 89 u32 clk_src_mpe; /* _CLK_SOURCE_MPE, 0x170 */ 90 u32 clk_src_hsi; /* _CLK_SOURCE_HSI, 0x174 */ 91 u32 clk_src_uarta; /* _CLK_SOURCE_UARTA, 0x178 */ 92 u32 clk_src_uartb; /* _CLK_SOURCE_UARTB, 0x17c */ 93 u32 clk_src_host1x; /* _CLK_SOURCE_HOST1X, 0x180 */ 94 u32 _rsv12[2]; /* 0x184-188 */ 95 u32 clk_src_hdmi; /* _CLK_SOURCE_HDMI, 0x18c */ 96 u32 _rsv13[2]; /* 0x190-194 */ 97 u32 clk_src_i2c2; /* _CLK_SOURCE_I2C2, 0x198 */ 98 u32 clk_src_emc; /* _CLK_SOURCE_EMC, 0x19c */ 99 u32 clk_src_uartc; /* _CLK_SOURCE_UARTC, 0x1a0 */ 100 u32 _rsv14; /* 0x1a4 */ 101 u32 clk_src_vi_sensor; /* _CLK_SOURCE_VI_SENSOR, 0x1a8 */ 102 u32 _rsv15[2]; /* 0x1ac-1b0 */ 103 u32 clk_src_sbc4; /* _CLK_SOURCE_SBC4, 0x1b4 */ 104 u32 clk_src_i2c3; /* _CLK_SOURCE_I2C3, 0x1b8 */ 105 u32 clk_src_sdmmc3; /* _CLK_SOURCE_SDMMC3, 0x1bc */ 106 u32 clk_src_uartd; /* _CLK_SOURCE_UARTD, 0x1c0 */ 107 u32 clk_src_uarte; /* _CLK_SOURCE_UARTE, 0x1c4 */ 108 u32 clk_src_vde; /* _CLK_SOURCE_VDE, 0x1c8 */ 109 u32 clk_src_owr; /* _CLK_SOURCE_OWR, 0x1cc */ 110 u32 clk_src_nor; /* _CLK_SOURCE_NOR, 0x1d0 */ 111 u32 clk_src_csite; /* _CLK_SOURCE_CSITE, 0x1d4 */ 112 u32 clk_src_i2s0; /* _CLK_SOURCE_I2S0, 0x1d8 */ 113 u32 clk_src_dtv; /* _CLK_SOURCE_DTV, 0x1dc */ 114 u32 _rsv16[4]; /* 0x1e0-1ec */ 115 u32 clk_src_msenc; /* _CLK_SOURCE_MSENC, 0x1f0 */ 116 u32 clk_src_tsec; /* _CLK_SOURCE_TSEC, 0x1f4 */ 117 u32 _rsv17; /* 0x1f8 */ 118 u32 clk_src_osc; /* _CLK_SOURCE_OSC, 0x1fc */ 119 u32 _rsv18[32]; /* 0x200-27c */ 120 u32 clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ 121 u32 clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ 122 u32 clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ 123 u32 rst_dev_x; /* _RST_DEVICES_X_0, 0x28c */ 124 u32 rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ 125 u32 rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ 126 u32 clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */ 127 u32 clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29C */ 128 u32 clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2A0 */ 129 u32 rst_dev_y; /* _RST_DEVICES_Y_0, 0x2A4 */ 130 u32 rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2A8 */ 131 u32 rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2AC */ 132 u32 _rsv19[17]; /* 0x2B0-2f0 */ 133 u32 dfll_base; /* _DFLL_BASE_0, 0x2f4 */ 134 u32 _rsv20[2]; /* 0x2f8-2fc */ 135 u32 rst_dev_l_set; /* _RST_DEV_L_SET 0x300 */ 136 u32 rst_dev_l_clr; /* _RST_DEV_L_CLR 0x304 */ 137 u32 rst_dev_h_set; /* _RST_DEV_H_SET 0x308 */ 138 u32 rst_dev_h_clr; /* _RST_DEV_H_CLR 0x30c */ 139 u32 rst_dev_u_set; /* _RST_DEV_U_SET 0x310 */ 140 u32 rst_dev_u_clr; /* _RST_DEV_U_CLR 0x314 */ 141 u32 _rsv21[2]; /* 0x318-31c */ 142 u32 clk_enb_l_set; /* _CLK_ENB_L_SET 0x320 */ 143 u32 clk_enb_l_clr; /* _CLK_ENB_L_CLR 0x324 */ 144 u32 clk_enb_h_set; /* _CLK_ENB_H_SET 0x328 */ 145 u32 clk_enb_h_clr; /* _CLK_ENB_H_CLR 0x32c */ 146 u32 clk_enb_u_set; /* _CLK_ENB_U_SET 0x330 */ 147 u32 clk_enb_u_clr; /* _CLK_ENB_U_CLR 0x334 */ 148 u32 _rsv22; /* 0x338 */ 149 u32 ccplex_pg_sm_ovrd; /* _CCPLEX_PG_SM_OVRD, 0x33c */ 150 u32 rst_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET, 0x340 */ 151 u32 rst_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR, 0x344 */ 152 u32 clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET, 0x348 */ 153 u32 clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET, 0x34c */ 154 u32 _rsv23[2]; /* 0x350-354 */ 155 u32 rst_dev_v; /* _RST_DEVICES_V, 0x358 */ 156 u32 rst_dev_w; /* _RST_DEVICES_W, 0x35c */ 157 u32 clk_out_enb_v; /* _CLK_OUT_ENB_V, 0x360 */ 158 u32 clk_out_enb_w; /* _CLK_OUT_ENB_W, 0x364 */ 159 u32 cclkg_brst_pol; /* _CCLKG_BURST_POLICY, 0x368 */ 160 u32 super_cclkg_div; /* _SUPER_CCLKG_DIVIDER, 0x36c */ 161 u32 cclklp_brst_pol; /* _CCLKLP_BURST_POLICY, 0x370 */ 162 u32 super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER, 0x374 */ 163 u32 clk_cpug_cmplx; /* _CLK_CPUG_CMPLX, 0x378 */ 164 u32 clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX, 0x37c */ 165 u32 cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL, 0x380 */ 166 u32 cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1, 0x384 */ 167 u32 cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2, 0x388 */ 168 u32 _rsv24[9]; /* 0x38c-3ac */ 169 u32 clk_src_g3d2; /* _CLK_SOURCE_G3D2, 0x3b0 */ 170 u32 clk_src_mselect; /* _CLK_SOURCE_MSELECT, 0x3b4 */ 171 u32 clk_src_tsensor; /* _CLK_SOURCE_TSENSOR, 0x3b8 */ 172 u32 clk_src_i2s3; /* _CLK_SOURCE_I2S3, 0x3bc */ 173 u32 clk_src_i2s4; /* _CLK_SOURCE_I2S4, 0x3c0 */ 174 u32 clk_src_i2c4; /* _CLK_SOURCE_I2C4, 0x3c4 */ 175 u32 clk_src_sbc5; /* _CLK_SOURCE_SBC5, 0x3c8 */ 176 u32 clk_src_sbc6; /* _CLK_SOURCE_SBC6, 0x3cc */ 177 u32 clk_src_audio; /* _CLK_SOURCE_AUDIO, 0x3d0 */ 178 u32 _rsv25; /* 0x3d4 */ 179 u32 clk_src_dam0; /* _CLK_SOURCE_DAM0, 0x3d8 */ 180 u32 clk_src_dam1; /* _CLK_SOURCE_DAM1, 0x3dc */ 181 u32 clk_src_dam2; /* _CLK_SOURCE_DAM2, 0x3e0 */ 182 u32 clk_src_hda2codec_2x; /* _CLK_SOURCE_HDA2CODEC_2X,0x3e4 */ 183 u32 clk_src_actmon; /* _CLK_SOURCE_ACTMON, 0x3e8 */ 184 u32 clk_src_extperiph1; /* _CLK_SOURCE_EXTPERIPH1, 0x3ec */ 185 u32 clk_src_extperiph2; /* _CLK_SOURCE_EXTPERIPH2, 0x3f0 */ 186 u32 clk_src_extperiph3; /* _CLK_SOURCE_EXTPERIPH3, 0x3f4 */ 187 u32 clk_src_nand_speed; /* _CLK_SOURCE_NAND_SPEED, 0x3f8 */ 188 u32 clk_src_i2c_slow; /* _CLK_SOURCE_I2C_SLOW, 0x3fc */ 189 u32 clk_src_sys; /* _CLK_SOURCE_SYS, 0x400 */ 190 u32 _rsv26[4]; /* 0x404-410 */ 191 u32 clk_src_sor; /* _CLK_SOURCE_SOR_0, 0x414 */ 192 u32 _rsv261[2]; /* 0x404-410 */ 193 u32 clk_src_sata_oob; /* _CLK_SOURCE_SATA_OOB, 0x420 */ 194 u32 clk_src_sata; /* _CLK_SOURCE_SATA, 0x424 */ 195 u32 clk_src_hda; /* _CLK_SOURCE_HDA, 0x428 */ 196 u32 _rsv27; /* 0x42c */ 197 u32 rst_dev_v_set; /* _RST_DEV_V_SET, 0x430 */ 198 u32 rst_dev_v_clr; /* _RST_DEV_V_CLR, 0x434 */ 199 u32 rst_dev_w_set; /* _RST_DEV_W_SET, 0x438 */ 200 u32 rst_dev_w_clr; /* _RST_DEV_W_CLR, 0x43c */ 201 u32 clk_enb_v_set; /* _CLK_ENB_V_SET, 0x440 */ 202 u32 clk_enb_v_clr; /* _CLK_ENB_V_CLR, 0x444 */ 203 u32 clk_enb_w_set; /* _CLK_ENB_W_SET, 0x448 */ 204 u32 clk_enb_w_clr; /* _CLK_ENB_W_CLR, 0x44c */ 205 u32 rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET, 0x450 */ 206 u32 rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR, 0x454 */ 207 u32 rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET, 0x458 */ 208 u32 rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR, 0x45C */ 209 u32 clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET, 0x460 */ 210 u32 clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR, 0x464 */ 211 u32 clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET, 0x468 */ 212 u32 clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR, 0x46c */ 213 u32 cpu_cmplx_status; /* _CPU_CMPLX_STATUS, 0x470 */ 214 u32 _rsv28; /* 0x474 */ 215 u32 intstatus; /* _INTSTATUS, 0x478 */ 216 u32 intmask; /* _INTMASK, 0x47c */ 217 u32 utmip_pll_cfg0; /* _UTMIP_PLL_CFG0, 0x480 */ 218 u32 utmip_pll_cfg1; /* _UTMIP_PLL_CFG1, 0x484 */ 219 u32 utmip_pll_cfg2; /* _UTMIP_PLL_CFG2, 0x488 */ 220 u32 plle_aux; /* _PLLE_AUX, 0x48c */ 221 u32 sata_pll_cfg0; /* _SATA_PLL_CFG0, 0x490 */ 222 u32 sata_pll_cfg1; /* _SATA_PLL_CFG1, 0x494 */ 223 u32 pcie_pll_cfg0; /* _PCIE_PLL_CFG0, 0x498 */ 224 u32 prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK, 0x49c */ 225 u32 audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0, 0x4a0 */ 226 u32 audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1, 0x4a4 */ 227 u32 audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2, 0x4a8 */ 228 u32 audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3, 0x4ac */ 229 u32 audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4, 0x4b0 */ 230 u32 audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF, 0x4b4 */ 231 u32 plld2_base; /* _PLLD2_BASE, 0x4b8 */ 232 u32 plld2_misc; /* _PLLD2_MISC, 0x4bc */ 233 u32 utmip_pll_cfg3; /* _UTMIP_PLL_CFG3, 0x4c0 */ 234 u32 pllrefe_base; /* _PLLREFE_BASE, 0x4c4 */ 235 u32 pllrefe_misc; /* _PLLREFE_MISC, 0x4c8 */ 236 u32 _rsv29[7]; /* 0x4cc-4e4 */ 237 u32 pllc2_base; /* _PLLC2_BASE, 0x4e8 */ 238 u32 pllc2_misc0; /* _PLLC2_MISC_0, 0x4ec */ 239 u32 pllc2_misc1; /* _PLLC2_MISC_1, 0x4f0 */ 240 u32 pllc2_misc2; /* _PLLC2_MISC_2, 0x4f4 */ 241 u32 pllc2_misc3; /* _PLLC2_MISC_3, 0x4f8 */ 242 u32 pllc3_base; /* _PLLC3_BASE, 0x4fc */ 243 u32 pllc3_misc0; /* _PLLC3_MISC_0, 0x500 */ 244 u32 pllc3_misc1; /* _PLLC3_MISC_1, 0x504 */ 245 u32 pllc3_misc2; /* _PLLC3_MISC_2, 0x508 */ 246 u32 pllc3_misc3; /* _PLLC3_MISC_3, 0x50c */ 247 u32 pllx_misc1; /* _PLLX_MISC_1, 0x510 */ 248 u32 pllx_misc2; /* _PLLX_MISC_2, 0x514 */ 249 u32 pllx_misc3; /* _PLLX_MISC_3, 0x518 */ 250 u32 xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0, 0x51c */ 251 u32 xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG1, 0x520 */ 252 u32 plle_aux1; /* _PLLE_AUX1, 0x524 */ 253 u32 pllp_reshift; /* _PLLP_RESHIFT, 0x528 */ 254 u32 utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0, 0x52c */ 255 u32 pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0, 0x530 */ 256 u32 xusb_pll_cfg0; /* _XUSB_PLL_CFG0, 0x534 */ 257 u32 _rsv30; /* 0x538 */ 258 u32 clk_cpu_misc; /* _CLK_CPU_MISC, 0x53c */ 259 u32 clk_cpug_misc; /* _CLK_CPUG_MISC, 0x540 */ 260 u32 clk_cpulp_misc; /* _CLK_CPULP_MISC, 0x544 */ 261 u32 pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG, 0x548 */ 262 u32 pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG, 0x54c */ 263 u32 pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS, 0x550 */ 264 u32 _rsv31; /* 0x554 */ 265 u32 super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER, 0x558 */ 266 u32 spare_reg0; /* _SPARE_REG0, 0x55c */ 267 u32 _rsv32[4]; /* 0x560-0x56c */ 268 u32 plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */ 269 u32 _rsv32_1[7]; /* 0x574-58c */ 270 u32 plldp_base; /* _PLLDP_BASE, 0x590 */ 271 u32 plldp_misc; /* _PLLDP_MISC, 0x594 */ 272 u32 plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ 273 u32 _rsrv32_2[25]; 274 u32 clk_src_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST 0x600 */ 275 u32 clk_src_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON 0x604 */ 276 u32 clk_src_xusb_fs; /* _CLK_SOURCE_XUSB_FS 0x608 */ 277 u32 clk_src_xusb_core_dev; /* _CLK_SOURCE_XUSB_CORE_DEV 0x60c */ 278 u32 clk_src_xusb_ss; /* _CLK_SOURCE_XUSB_SS 0x610 */ 279 u32 clk_src_cilab; /* _CLK_SOURCE_CILAB 0x614 */ 280 u32 clk_src_cilcd; /* _CLK_SOURCE_CILCD 0x618 */ 281 u32 clk_src_cile; /* _CLK_SOURCE_CILE 0x61c */ 282 u32 clk_src_dsia_lp; /* _CLK_SOURCE_DSIA_LP 0x620 */ 283 u32 clk_src_dsib_lp; /* _CLK_SOURCE_DSIB_LP 0x624 */ 284 u32 clk_src_entropy; /* _CLK_SOURCE_ENTROPY 0x628 */ 285 u32 clk_src_dvfs_ref; /* _CLK_SOURCE_DVFS_REF 0x62c */ 286 u32 clk_src_dvfs_soc; /* _CLK_SOURCE_DVFS_SOC 0x630 */ 287 u32 clk_src_traceclkin; /* _CLK_SOURCE_TRACECLKIN 0x634 */ 288 u32 clk_src_adx0; /* _CLK_SOURCE_ADX0 0x638 */ 289 u32 clk_src_amx0; /* _CLK_SOURCE_AMX0 0x63c */ 290 u32 clk_src_emc_latency; /* _CLK_SOURCE_EMC_LATENCY 0x640 */ 291 u32 clk_src_soc_therm; /* _CLK_SOURCE_SOC_THERM 0x644 */ 292 u32 _rsv33[5]; /* 0x648-658 */ 293 u32 clk_src_i2c6; /* _CLK_SOURCE_I2C6, 0x65c */ 294 u32 clk_src_mipibif; /* _CLK_SOURCE_MIPIBIF, 0x660 */ 295 u32 clk_src_emc_dll; /* _CLK_SOURCE_EMC_DLL, 0x664 */ 296 u32 _rsv34; /* 0x668 */ 297 u32 clk_src_uart_fst_mipi_cal; /* _CLK_SOURCE_UART_FST_MIP_CAL, 0x66c */ 298 u32 _rsv35[21]; /* 0x670-6c0 */ 299 u32 clk_src_qspi; /* _CLK_SOURCE_QSPI 0x6C4 */ 300 }; 301 check_member(clk_rst_ctlr, clk_src_qspi, 0x6C4); 302 303 #define CLK_RST_REG(field_) \ 304 (&(((struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE)->field_)) 305 306 /* L, H, U, V, W, X, Y */ 307 #define DEV_CONFIG_BLOCKS 7 308 309 #define TEGRA_DEV_L 0 310 #define TEGRA_DEV_H 1 311 #define TEGRA_DEV_U 2 312 #define TEGRA_DEV_V 0 313 #define TEGRA_DEV_W 1 314 315 #define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE) 316 317 /* Bits to enable/reset modules */ 318 #define CLK_ENB_CPU (1 << 0) 319 #define SWR_TRIG_SYS_RST (1 << 2) 320 #define SWR_CSITE_RST (1 << 9) 321 #define CLK_ENB_CSITE (1 << 9) 322 #define CLK_ENB_EMC_DLL (1 << 14) 323 324 /* _CCLK_BURST_POLICY 0x20 */ 325 #define CCLK_BURST_POLICY_VAL 0x20008888 326 /* CLK_M divisor */ 327 #define CLK_M_DIVISOR_MASK (0x3 << 2) 328 #define CLK_M_DIVISOR_BY_2 (1 << 2) 329 330 /* CRC_SUPER_CCLK_DIVIDER_0 0x24 */ 331 #define SUPER_CDIV_ENB_ENABLE (1 << 31) 332 333 /* CLK_RST_CONTROLLER_MISC_CLK_ENB 0x48 */ 334 #define EN_PPSB_STOPCLK (1 << 0) 335 336 /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 (0x4C) */ 337 #define CPU3_CLK_STP_SHIFT 11 338 #define CPU2_CLK_STP_SHIFT 10 339 #define CPU1_CLK_STP_SHIFT 9 340 #define CPU0_CLK_STP_SHIFT 8 341 #define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT) 342 343 /* CRC_OSC_CTRL_0 0x50 */ 344 #define OSC_FREQ_SHIFT 28 345 #define OSC_FREQ_MASK (0xf << OSC_FREQ_SHIFT) 346 #define OSC_PREDIV_SHIFT 26 347 #define OSC_PREDIV_MASK (0x3 << OSC_PREDIV_SHIFT) 348 #define OSC_XOFS_SHIFT 4 349 #define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT) 350 #define OSC_DRIVE_STRENGTH 7 351 #define OSC_XOBP (1 << 1) 352 #define OSC_XOE (1 << 0) 353 354 enum { 355 OSC_FREQ_12 = 8, /* 12.0MHz */ 356 OSC_FREQ_13 = 0, /* 13.0MHz */ 357 OSC_FREQ_16P8 = 1, /* 16.8MHz */ 358 OSC_FREQ_19P2 = 4, /* 19.2MHz */ 359 OSC_FREQ_26 = 12, /* 26.0MHz */ 360 OSC_FREQ_38P4 = 5, /* 38.4MHz */ 361 OSC_FREQ_48 = 9, /* 48.0MHz */ 362 }; 363 364 /* CLK_RST_CONTROLLER_PLL*_BASE_0 */ 365 #define PLL_BASE_BYPASS (1U << 31) 366 #define PLL_BASE_ENABLE (1U << 30) 367 #define PLL_BASE_REF_DIS (1U << 29) 368 #define PLL_BASE_OVRRIDE (1U << 28) 369 #define PLL_BASE_LOCK (1U << 27) 370 #define PLLC_BASE_LOCK (1U << 26) 371 372 #define PLL_BASE_DIVP_SHIFT 20 373 #define PLL_BASE_DIVP_MASK (7U << PLL_BASE_DIVP_SHIFT) 374 375 #define PLL_BASE_DIVN_SHIFT 8 376 #define PLL_BASE_DIVN_MASK (0x3ffU << PLL_BASE_DIVN_SHIFT) 377 378 #define PLL_BASE_DIVM_SHIFT 0 379 #define PLL_BASE_DIVM_MASK (0x1f << PLL_BASE_DIVM_SHIFT) 380 381 /* SPECIAL CASE: PLLM, PLLC and PLLX use different-sized fields here */ 382 #define PLLCX_BASE_DIVP_MASK (0xfU << PLL_BASE_DIVP_SHIFT) 383 #define PLLM_BASE_DIVP_MASK (0x1fU << PLL_BASE_DIVP_SHIFT) 384 #define PLLCMX_BASE_DIVN_MASK (0xffU << PLL_BASE_DIVN_SHIFT) 385 #define PLLCMX_BASE_DIVM_MASK (0xffU << PLL_BASE_DIVM_SHIFT) 386 387 /* Added based on T210 TRM */ 388 #define PLLC_MISC_RESET (1U << 30) 389 #define PLLC_MISC_1_IDDQ (1U << 27) 390 #define PLLD_N_SHIFT 11 391 #define PLLD_M_SHIFT 0 392 #define PLLD_P_SHIFT 20 393 #define PLLD_MISC1_SETUP 0x20 394 #define PLLD_MISC_EN_SDM (1 << 16) 395 #define PLLD_MISC_SDM_DIN 0x9aa 396 397 /* PLLM specific registers */ 398 #define PLLM_MISC1_SETUP_SHIFT 0 399 #define PLLM_MISC1_PD_LSHIFT_PH45_SHIFT 28 400 #define PLLM_MISC1_PD_LSHIFT_PH90_SHIFT 29 401 #define PLLM_MISC1_PD_LSHIFT_PH135_SHIFT 30 402 #define PLLM_MISC2_KCP_SHIFT 1 403 #define PLLM_MISC2_KVCO_SHIFT 0 404 #define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0) 405 #define PLLM_EN_LCKDET (1 << 4) 406 407 /* PLLU specific registers */ 408 #define PLLU_MISC_IDDQ (1U << 31) 409 410 /* UTMIP PLL specific registers */ 411 #define UTMIP_CFG0_PLL_MDIV_SHIFT (8) 412 #define UTMIP_CFG0_PLL_NDIV_SHIFT (16) 413 #define UTMIP_CFG1_XTAL_FREQ_COUNT_SHIFT (0) 414 #define UTMIP_CFG1_FORCE_PLL_ACTIVE_POWERDOWN_DISABLE (0 << 12) 415 #define UTMIP_CFG1_FORCE_PLL_ENABLE_POWERDOWN_DISABLE (0 << 14) 416 #define UTMIP_CFG1_FORCE_PLL_ENABLE_POWERUP_ENABLE (1 << 15) 417 #define UTMIP_CFG1_FORCE_PLLU_POWERDOWN_ENABLE (1 << 16) 418 #define UTMIP_CFG1_PLLU_ENABLE_DLY_COUNT_SHIFT (27) 419 #define UTMIP_CFG2_FORCE_PD_SAMP_A_POWERDOWN_DISABLE (0 << 0) 420 #define UTMIP_CFG2_FORCE_PD_SAMP_A_POWERUP_ENABLE (1 << 1) 421 #define UTMIP_CFG2_FORCE_PD_SAMP_B_POWERDOWN_DISABLE (0 << 2) 422 #define UTMIP_CFG2_FORCE_PD_SAMP_B_POWERUP_ENABLE (1 << 3) 423 #define UTMIP_CFG2_FORCE_PD_SAMP_C_POWERDOWN_DISABLE (0 << 4) 424 #define UTMIP_CFG2_FORCE_PD_SAMP_C_POWERUP_ENABLE (1 << 5) 425 #define UTMIP_CFG2_FORCE_PD_SAMP_D_POWERDOWN_DISABLE (0 << 24) 426 #define UTMIP_CFG2_FORCE_PD_SAMP_D_POWERUP_ENABLE (1 << 25) 427 #define UTMIP_CFG2_PLLU_STABLE_COUNT_SHIFT (6) 428 #define UTMIP_CFG2_PLL_ACTIVE_DLY_COUNT_SHIFT (18) 429 #define UTMIP_CFG2_PHY_XTAL_CLOCKEN (1U << 30) 430 431 /* Generic, indiscriminate divisor mask. May catch some innocent bystander bits 432 * on the side that we don't particularly care about. */ 433 #define PLL_BASE_DIV_MASK (0xffffff) 434 435 /* CLK_RST_CONTROLLER_PLL*_OUT*_0 */ 436 #define PLL_OUT_RSTN (1 << 0) 437 #define PLL_OUT_CLKEN (1 << 1) 438 #define PLL_OUT_OVR (1 << 2) 439 440 #define PLL_OUT_RATIO_SHIFT 8 441 #define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT) 442 443 #define PLL_OUT1_SHIFT 0 444 #define PLL_OUT2_SHIFT 16 445 #define PLL_OUT3_SHIFT 0 446 #define PLL_OUT4_SHIFT 16 447 448 /* This bit is different all over the place. */ 449 #define PLLDPD2_MISC_LOCK_ENABLE (1 << 30) 450 #define PLLU_MISC_LOCK_ENABLE (1 << 29) 451 #define PLLD_MISC_LOCK_ENABLE (1 << 18) 452 #define PLLD_MISC_CLK_ENABLE (1 << 21) 453 #define PLLPAXS_MISC_LOCK_ENABLE (1 << 18) 454 #define PLLE_MISC_LOCK_ENABLE (1 << 9) 455 456 /* PLLX_BASE_0 0xe0 */ 457 #define PLLX_BASE_PLLX_ENABLE (1 << 30) 458 459 /* CLK_RST_CONTROLLER_PLLX_MISC_3 */ 460 #define PLLX_IDDQ_SHIFT 3 461 #define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT) 462 463 #define CLK_DIVISOR_MASK (0xffff) 464 465 #define CLK_SOURCE_SHIFT 29 466 #define CLK_SOURCE_MASK (0x7 << CLK_SOURCE_SHIFT) 467 468 #define CLK_SOURCE_EMC_MC_EMC_SAME_FREQ (1 << 16) 469 #define EMC_2X_CLK_SRC_SHIFT 29 470 #define PLLM_UD 4 471 472 #define CLK_UART_DIV_OVERRIDE (1 << 24) 473 474 /* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */ 475 #define SCLK_SYS_STATE_SHIFT 28U 476 #define SCLK_SYS_STATE_MASK (15U << SCLK_SYS_STATE_SHIFT) 477 enum { 478 SCLK_SYS_STATE_STDBY, 479 SCLK_SYS_STATE_IDLE, 480 SCLK_SYS_STATE_RUN, 481 SCLK_SYS_STATE_IRQ = 4U, 482 SCLK_SYS_STATE_FIQ = 8U, 483 }; 484 #define SCLK_COP_FIQ_MASK (1 << 27) 485 #define SCLK_CPU_FIQ_MASK (1 << 26) 486 #define SCLK_COP_IRQ_MASK (1 << 25) 487 #define SCLK_CPU_IRQ_MASK (1 << 24) 488 489 #define SCLK_FIQ_SHIFT 12 490 #define SCLK_FIQ_MASK (7 << SCLK_FIQ_SHIFT) 491 #define SCLK_IRQ_SHIFT 8 492 #define SCLK_IRQ_MASK (7 << SCLK_FIQ_SHIFT) 493 #define SCLK_RUN_SHIFT 4 494 #define SCLK_RUN_MASK (7 << SCLK_FIQ_SHIFT) 495 #define SCLK_IDLE_SHIFT 0 496 #define SCLK_IDLE_MASK (7 << SCLK_FIQ_SHIFT) 497 enum { 498 SCLK_SOURCE_CLKM, 499 SCLK_SOURCE_PLLC_OUT1, 500 SCLK_SOURCE_PLLP_OUT4, 501 SCLK_SOURCE_PLLP_OUT3, 502 SCLK_SOURCE_PLLP_OUT2, 503 SCLK_SOURCE_PLLC_OUT0, 504 SCLK_SOURCE_CLKS, 505 SCLK_SOURCE_PLLM_OUT1, 506 }; 507 508 /* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER 0x2c */ 509 #define SCLK_DIV_ENB (1 << 31) 510 #define SCLK_DIVIDEND_SHIFT 8 511 #define SCLK_DIVIDEND_MASK (0xff << SCLK_DIVIDEND_SHIFT) 512 #define SCLK_DIVISOR_SHIFT 0 513 #define SCLK_DIVISOR_MASK (0xff << SCLK_DIVISOR_SHIFT) 514 515 /* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */ 516 #define HCLK_DISABLE (1 << 7) 517 #define HCLK_DIVISOR_SHIFT 4 518 #define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) 519 #define PCLK_DISABLE (1 << 3) 520 #define PCLK_DIVISOR_SHIFT 0 521 #define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) 522 523 /* CPU_SOFTRST_CTRL2_0 0x388 */ 524 #define CAR2PMC_CPU_ACK_WIDTH_MASK 0xfff 525 526 /* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */ 527 #define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29) 528 529 /* CRC_CLK_ENB_V_SET_0 0x440 */ 530 #define SET_CLK_ENB_CPUG_ENABLE (1 << 0) 531 #define SET_CLK_ENB_CPULP_ENABLE (1 << 1) 532 #define SET_CLK_ENB_MSELECT_ENABLE (1 << 3) 533 534 /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */ 535 #define PLLU_POWERDOWN (1 << 16) 536 #define PLL_ENABLE_POWERDOWN (1 << 14) 537 #define PLL_ACTIVE_POWERDOWN (1 << 12) 538 539 /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */ 540 #define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) 541 #define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) 542 #define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) 543 544 // CCLK_BRST_POL 545 enum { 546 CRC_CCLK_BRST_POL_PLLX_OUT0 = 0x8, 547 CRC_CCLK_BRST_POL_CPU_STATE_RUN = 0x2 548 }; 549 550 // SUPER_CCLK_DIVIDER 551 enum { 552 CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB = 1 << 31 553 }; 554 555 // CLK_CPU_CMPLX_CLR 556 enum { 557 CRC_CLK_CLR_CPU0_STP = 0x1 << 8, 558 CRC_CLK_CLR_CPU1_STP = 0x1 << 9, 559 CRC_CLK_CLR_CPU2_STP = 0x1 << 10, 560 CRC_CLK_CLR_CPU3_STP = 0x1 << 11 561 }; 562 563 // RST_CPUG_CMPLX_CLR 564 enum { 565 CRC_RST_CPUG_CLR_CPU0 = 0x1 << 0, 566 CRC_RST_CPUG_CLR_CPU1 = 0x1 << 1, 567 CRC_RST_CPUG_CLR_CPU2 = 0x1 << 2, 568 CRC_RST_CPUG_CLR_CPU3 = 0x1 << 3, 569 CRC_RST_CPUG_CLR_DBG0 = 0x1 << 12, 570 CRC_RST_CPUG_CLR_DBG1 = 0x1 << 13, 571 CRC_RST_CPUG_CLR_DBG2 = 0x1 << 14, 572 CRC_RST_CPUG_CLR_DBG3 = 0x1 << 15, 573 CRC_RST_CPUG_CLR_CORE0 = 0x1 << 16, 574 CRC_RST_CPUG_CLR_CORE1 = 0x1 << 17, 575 CRC_RST_CPUG_CLR_CORE2 = 0x1 << 18, 576 CRC_RST_CPUG_CLR_CORE3 = 0x1 << 19, 577 CRC_RST_CPUG_CLR_CX0 = 0x1 << 20, 578 CRC_RST_CPUG_CLR_CX1 = 0x1 << 21, 579 CRC_RST_CPUG_CLR_CX2 = 0x1 << 22, 580 CRC_RST_CPUG_CLR_CX3 = 0x1 << 23, 581 CRC_RST_CPUG_CLR_L2 = 0x1 << 24, 582 CRC_RST_CPUG_CLR_NONCPU = 0x1 << 29, 583 CRC_RST_CPUG_CLR_PDBG = 0x1 << 30, 584 }; 585 586 // RST_CPULP_CMPLX_CLR 587 enum { 588 CRC_RST_CPULP_CLR_CPU0 = 0x1 << 0, 589 CRC_RST_CPULP_CLR_DBG0 = 0x1 << 12, 590 CRC_RST_CPULP_CLR_CORE0 = 0x1 << 16, 591 CRC_RST_CPULP_CLR_CX0 = 0x1 << 20, 592 CRC_RST_CPULP_CLR_L2 = 0x1 << 24, 593 CRC_RST_CPULP_CLR_NONCPU = 0x1 << 29, 594 CRC_RST_CPULP_CLR_PDBG = 0x1 << 30, 595 }; 596 597 #define TIMERUS_CNTR_1US 0x0 598 #define TIMERUS_USEC_CFG 0x4 599 #define TIMERUS_USEC_CFG_19P2_CLK_M 0x045F 600 601 #endif /* _TEGRA210_CLK_RST_H_ */ 602