1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <lib/utils_def.h> 13 #include <plat/common/common_def.h> 14 15 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 16 #define QEMU_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 17 18 #define PLATFORM_STACK_SIZE 0x1000 19 20 #if ARM_ARCH_MAJOR == 7 21 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 22 #define PLATFORM_CLUSTER_COUNT U(1) 23 #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 24 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 25 #else 26 /* 27 * Define the number of cores per cluster used in calculating core position. 28 * The cluster number is shifted by this value and added to the core ID, 29 * so its value represents log2(cores/cluster). 30 * Default is 2**(4) = 16 cores per cluster. 31 */ 32 #define PLATFORM_CPU_PER_CLUSTER_SHIFT U(4) 33 #define PLATFORM_MAX_CPUS_PER_CLUSTER (U(1) << PLATFORM_CPU_PER_CLUSTER_SHIFT) 34 #define PLATFORM_CLUSTER_COUNT U(2) 35 #define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 36 #define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER 37 #endif 38 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ 39 PLATFORM_CLUSTER1_CORE_COUNT) 40 41 #define QEMU_PRIMARY_CPU U(0) 42 43 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ 44 PLATFORM_CORE_COUNT) 45 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 46 47 #define PLAT_MAX_RET_STATE U(1) 48 #define PLAT_MAX_OFF_STATE U(2) 49 50 /* Local power state for power domains in Run state. */ 51 #define PLAT_LOCAL_STATE_RUN U(0) 52 /* Local power state for retention. Valid only for CPU power domains */ 53 #define PLAT_LOCAL_STATE_RET U(1) 54 /* 55 * Local power state for OFF/power-down. Valid for CPU and cluster power 56 * domains. 57 */ 58 #define PLAT_LOCAL_STATE_OFF 2 59 60 /* 61 * Macros used to parse state information from State-ID if it is using the 62 * recommended encoding for State-ID. 63 */ 64 #define PLAT_LOCAL_PSTATE_WIDTH 4 65 #define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) 66 67 /* 68 * Some data must be aligned on the biggest cache line size in the platform. 69 * This is known only to the platform as it might have a combination of 70 * integrated and external caches. 71 */ 72 #define CACHE_WRITEBACK_SHIFT 6 73 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 74 75 /* 76 * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", 77 * and secure DRAM. 78 */ 79 #define SEC_ROM_BASE 0x00000000 80 #define SEC_ROM_SIZE 0x00020000 81 82 #define NS_DRAM0_BASE ULL(0x40000000) 83 #define NS_DRAM0_SIZE ULL(0xc0000000) 84 85 #define SEC_SRAM_BASE 0x0e000000 86 #define SEC_SRAM_SIZE 0x00200000 87 88 #define SEC_DRAM_BASE 0x0e200000 89 #define SEC_DRAM_SIZE 0x2fe00000 90 91 #define SECURE_GPIO_BASE 0x090b0000 92 #define SECURE_GPIO_SIZE 0x00001000 93 #define SECURE_GPIO_POWEROFF 0 94 #define SECURE_GPIO_RESET 1 95 96 /* Load pageable part of OP-TEE 2MB above secure DRAM base */ 97 #define QEMU_OPTEE_PAGEABLE_LOAD_BASE (SEC_DRAM_BASE + 0x00200000) 98 #define QEMU_OPTEE_PAGEABLE_LOAD_SIZE 0x00400000 99 100 /* 101 * ARM-TF lives in SRAM, partition it here 102 */ 103 104 #define SHARED_RAM_BASE SEC_SRAM_BASE 105 #define SHARED_RAM_SIZE 0x00001000 106 107 #define PLAT_QEMU_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE 108 #define PLAT_QEMU_TRUSTED_MAILBOX_SIZE (8 + PLAT_QEMU_HOLD_SIZE) 109 #define PLAT_QEMU_HOLD_BASE (PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8) 110 #define PLAT_QEMU_HOLD_SIZE (PLATFORM_CORE_COUNT * \ 111 PLAT_QEMU_HOLD_ENTRY_SIZE) 112 #define PLAT_QEMU_HOLD_ENTRY_SHIFT 3 113 #define PLAT_QEMU_HOLD_ENTRY_SIZE (1 << PLAT_QEMU_HOLD_ENTRY_SHIFT) 114 #define PLAT_QEMU_HOLD_STATE_WAIT 0 115 #define PLAT_QEMU_HOLD_STATE_GO 1 116 117 #define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) 118 #define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) 119 120 #define TB_FW_CONFIG_BASE BL_RAM_BASE 121 #define TB_FW_CONFIG_LIMIT (TB_FW_CONFIG_BASE + PAGE_SIZE) 122 #define TOS_FW_CONFIG_BASE TB_FW_CONFIG_LIMIT 123 #define TOS_FW_CONFIG_LIMIT (TOS_FW_CONFIG_BASE + PAGE_SIZE) 124 125 /* 126 * BL1 specific defines. 127 * 128 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 129 * addresses. 130 * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using 131 * the current BL1 RW debug size plus a little space for growth. 132 */ 133 #define BL1_RO_BASE SEC_ROM_BASE 134 #define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE) 135 #define BL1_RW_BASE (BL1_RW_LIMIT - 0x12000) 136 #define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) 137 138 /* 139 * BL2 specific defines. 140 * 141 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 142 * size plus a little space for growth. 143 */ 144 #define BL2_BASE (BL31_BASE - 0x35000) 145 #define BL2_LIMIT BL31_BASE 146 147 /* 148 * BL3-1 specific defines. 149 * 150 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 151 * current BL3-1 debug size plus a little space for growth. 152 */ 153 #define BL31_BASE (BL31_LIMIT - 0x160000) 154 #define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE - FW_HANDOFF_SIZE) 155 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 156 157 #if TRANSFER_LIST 158 #define FW_HANDOFF_BASE BL31_LIMIT 159 #define FW_HANDOFF_LIMIT (FW_HANDOFF_BASE + FW_HANDOFF_SIZE) 160 #define FW_HANDOFF_SIZE 0x4000 161 #else 162 #define FW_HANDOFF_SIZE 0 163 #endif 164 165 166 /* 167 * BL3-2 specific defines. 168 * 169 * BL3-2 can execute from Secure SRAM, or Secure DRAM. 170 */ 171 #define BL32_SRAM_BASE BL_RAM_BASE 172 #define BL32_SRAM_LIMIT BL31_BASE 173 #define BL32_DRAM_BASE SEC_DRAM_BASE 174 #define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE - \ 175 RME_GPT_DRAM_SIZE) 176 177 #define SEC_SRAM_ID 0 178 #define SEC_DRAM_ID 1 179 180 #if BL32_RAM_LOCATION_ID == SEC_SRAM_ID 181 # define BL32_MEM_BASE BL_RAM_BASE 182 # define BL32_MEM_SIZE BL_RAM_SIZE 183 # define BL32_BASE BL32_SRAM_BASE 184 # define BL32_LIMIT (BL32_SRAM_LIMIT - FW_HANDOFF_SIZE) 185 #elif BL32_RAM_LOCATION_ID == SEC_DRAM_ID 186 # define BL32_MEM_BASE SEC_DRAM_BASE 187 # define BL32_MEM_SIZE SEC_DRAM_SIZE 188 # define BL32_BASE BL32_DRAM_BASE 189 # define BL32_LIMIT (BL32_DRAM_LIMIT - FW_HANDOFF_SIZE) 190 #else 191 # error "Unsupported BL32_RAM_LOCATION_ID value" 192 #endif 193 194 #if TRANSFER_LIST 195 #define FW_NS_HANDOFF_BASE (NS_IMAGE_OFFSET - FW_HANDOFF_SIZE) 196 #endif 197 198 #define NS_IMAGE_OFFSET (NS_DRAM0_BASE + 0x20000000) 199 #define NS_IMAGE_MAX_SIZE (NS_DRAM0_SIZE - 0x20000000) 200 201 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 202 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 203 #define MAX_MMAP_REGIONS (13 + MAX_MMAP_REGIONS_SPMC) 204 #define MAX_XLAT_TABLES (6 + MAX_XLAT_TABLES_SPMC) 205 #define MAX_IO_DEVICES 4 206 #define MAX_IO_HANDLES 4 207 208 /* 209 * PL011 related constants 210 */ 211 #define UART0_BASE 0x09000000 212 #define UART1_BASE 0x09040000 213 #define UART0_CLK_IN_HZ 1 214 #define UART1_CLK_IN_HZ 1 215 216 #define PLAT_QEMU_BOOT_UART_BASE UART0_BASE 217 #define PLAT_QEMU_BOOT_UART_CLK_IN_HZ UART0_CLK_IN_HZ 218 219 #define PLAT_QEMU_CRASH_UART_BASE UART1_BASE 220 #define PLAT_QEMU_CRASH_UART_CLK_IN_HZ UART1_CLK_IN_HZ 221 222 #define PLAT_QEMU_CONSOLE_BAUDRATE 115200 223 224 #define QEMU_FLASH0_BASE 0x00000000 225 #define QEMU_FLASH0_SIZE 0x04000000 226 #define QEMU_FLASH1_BASE 0x04000000 227 #define QEMU_FLASH1_SIZE 0x04000000 228 229 #define PLAT_QEMU_FIP_BASE 0x00040000 230 #define PLAT_QEMU_FIP_MAX_SIZE (QEMU_FLASH0_SIZE - PLAT_QEMU_FIP_BASE) 231 232 #define DEVICE0_BASE 0x08000000 233 #define DEVICE0_SIZE 0x01000000 234 #define DEVICE1_BASE 0x09000000 235 #define DEVICE1_SIZE 0x00c00000 236 237 /* 238 * GIC related constants 239 */ 240 241 #define GICD_BASE 0x8000000 242 #define GICC_BASE 0x8010000 243 #define GICR_BASE 0x80A0000 244 245 246 #define QEMU_IRQ_SEC_SGI_0 8 247 #define QEMU_IRQ_SEC_SGI_1 9 248 #define QEMU_IRQ_SEC_SGI_2 10 249 #define QEMU_IRQ_SEC_SGI_3 11 250 #define QEMU_IRQ_SEC_SGI_4 12 251 #define QEMU_IRQ_SEC_SGI_5 13 252 #define QEMU_IRQ_SEC_SGI_6 14 253 #define QEMU_IRQ_SEC_SGI_7 15 254 255 /****************************************************************************** 256 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 257 * interrupts. 258 *****************************************************************************/ 259 #define PLATFORM_G1S_PROPS(grp) \ 260 DESC_G1S_IRQ_SEC_SGI_0(grp) \ 261 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ 262 grp, GIC_INTR_CFG_EDGE), \ 263 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ 264 grp, GIC_INTR_CFG_EDGE), \ 265 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ 266 grp, GIC_INTR_CFG_EDGE), \ 267 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ 268 grp, GIC_INTR_CFG_EDGE), \ 269 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ 270 grp, GIC_INTR_CFG_EDGE), \ 271 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 272 grp, GIC_INTR_CFG_EDGE), \ 273 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ 274 grp, GIC_INTR_CFG_EDGE) 275 276 #if SDEI_SUPPORT 277 #define DESC_G0_IRQ_SEC_SGI(grp) \ 278 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 279 GIC_INTR_CFG_EDGE) 280 #define DESC_G1S_IRQ_SEC_SGI_0(grp) 281 #else 282 #define DESC_G0_IRQ_SEC_SGI(grp) 283 #define DESC_G1S_IRQ_SEC_SGI_0(grp) \ 284 INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 285 GIC_INTR_CFG_EDGE), 286 #endif 287 288 #define PLATFORM_G0_PROPS(grp) DESC_G0_IRQ_SEC_SGI(grp) 289 290 /* 291 * DT related constants 292 */ 293 #define PLAT_QEMU_DT_BASE NS_DRAM0_BASE 294 #define PLAT_QEMU_DT_MAX_SIZE 0x100000 295 296 /* 297 * Platforms macros to support SDEI 298 */ 299 #define PLAT_PRI_BITS U(3) 300 #define PLAT_SDEI_CRITICAL_PRI 0x60 301 #define PLAT_SDEI_NORMAL_PRI 0x70 302 #define PLAT_SDEI_SGI_PRIVATE QEMU_IRQ_SEC_SGI_0 303 304 /* 305 * Maximum size of Event Log buffer used in Measured Boot Event Log driver 306 */ 307 #define PLAT_EVENT_LOG_MAX_SIZE UL(0x400) 308 309 #if SPMC_AT_EL3 310 /* 311 * Number of Secure Partitions supported. 312 * SPMC at EL3, uses this count to configure the maximum number of 313 * supported secure partitions. 314 */ 315 #define SECURE_PARTITION_COUNT 1 316 317 /* 318 * Number of Logical Partitions supported. 319 * SPMC at EL3, uses this count to configure the maximum number of 320 * supported logical partitions. 321 */ 322 #define MAX_EL3_LP_DESCS_COUNT 0 323 324 /* 325 * Number of Normal World Partitions supported. 326 * SPMC at EL3, uses this count to configure the maximum number of 327 * supported normal world partitions. 328 */ 329 #define NS_PARTITION_COUNT 1 330 331 #define MAX_MMAP_REGIONS_SPMC 2 332 #define MAX_XLAT_TABLES_SPMC 4 333 #else 334 #define MAX_MMAP_REGIONS_SPMC 0 335 #define MAX_XLAT_TABLES_SPMC 0 336 #endif 337 338 #if ENABLE_RME 339 340 /* 341 * Reserve some space at the end of secure DRAM for the Granule Protection 342 * Tables 343 */ 344 #define PLAT_QEMU_L0_GPT_BASE (PLAT_QEMU_L1_GPT_BASE - \ 345 PLAT_QEMU_L0_GPT_SIZE) 346 #define PLAT_QEMU_L0_GPT_SIZE (2 * PAGE_SIZE) 347 348 #define PLAT_QEMU_L1_GPT_BASE (SEC_DRAM_BASE + SEC_DRAM_SIZE - \ 349 PLAT_QEMU_L1_GPT_SIZE) 350 #define PLAT_QEMU_L1_GPT_END (PLAT_QEMU_L1_GPT_BASE + \ 351 PLAT_QEMU_L1_GPT_SIZE - 1U) 352 #define PLAT_QEMU_L1_GPT_SIZE UL(0x00100000) /* 1MB */ 353 354 #define RME_GPT_DRAM_BASE PLAT_QEMU_L0_GPT_BASE 355 #define RME_GPT_DRAM_SIZE (PLAT_QEMU_L1_GPT_SIZE + \ 356 PLAT_QEMU_L0_GPT_SIZE) 357 358 #ifndef __ASSEMBLER__ 359 /* L0 table greater than 4KB must be naturally aligned */ 360 CASSERT((PLAT_QEMU_L0_GPT_BASE & (PLAT_QEMU_L0_GPT_SIZE - 1)) == 0, 361 assert_l0_gpt_naturally_aligned); 362 #endif 363 364 /* Reserved some DRAM space for RMM (24MB) */ 365 #define REALM_DRAM_BASE (NS_DRAM0_BASE + PLAT_QEMU_DT_MAX_SIZE) 366 #define REALM_DRAM_SIZE 0x01800000 367 368 #define PLAT_QEMU_RMM_SIZE (REALM_DRAM_SIZE - RMM_SHARED_SIZE) 369 #define PLAT_QEMU_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */ 370 371 #define RMM_BASE (REALM_DRAM_BASE) 372 #define RMM_LIMIT (RMM_BASE + PLAT_QEMU_RMM_SIZE) 373 #define RMM_SHARED_BASE (RMM_LIMIT) 374 #define RMM_SHARED_SIZE PLAT_QEMU_RMM_SHARED_SIZE 375 376 #define MAP_GPT_L0_REGION MAP_REGION_FLAT( \ 377 PLAT_QEMU_L0_GPT_BASE, \ 378 PLAT_QEMU_L0_GPT_SIZE, \ 379 MT_MEMORY | MT_RW | EL3_PAS) 380 381 #define MAP_GPT_L1_REGION MAP_REGION_FLAT( \ 382 PLAT_QEMU_L1_GPT_BASE, \ 383 PLAT_QEMU_L1_GPT_SIZE, \ 384 MT_MEMORY | MT_RW | EL3_PAS) 385 /* 386 * We add the RMM_SHARED size to RMM mapping to map the region as a block. 387 * Else we end up requiring more pagetables in BL2 for ROMLIB build. 388 */ 389 #define MAP_RMM_DRAM MAP_REGION_FLAT( \ 390 RMM_BASE, \ 391 (PLAT_QEMU_RMM_SIZE + \ 392 RMM_SHARED_SIZE), \ 393 MT_MEMORY | MT_RW | MT_REALM) 394 395 #define MAP_RMM_SHARED_MEM MAP_REGION_FLAT( \ 396 RMM_SHARED_BASE, \ 397 RMM_SHARED_SIZE, \ 398 MT_MEMORY | MT_RW | MT_REALM) 399 #else /* !ENABLE_RME */ 400 401 #define RME_GPT_DRAM_SIZE 0 402 403 #endif /* ENABLE_RME */ 404 405 #endif /* PLATFORM_DEF_H */ 406